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-rw-r--r--amforth-6.5/LICENSE.txt674
-rw-r--r--amforth-6.5/appl/arduino/Makefile191
-rw-r--r--amforth-6.5/appl/arduino/blocks/led-mega.frt38
-rw-r--r--amforth-6.5/appl/arduino/blocks/led-mega.readme114
-rw-r--r--amforth-6.5/appl/arduino/blocks/ports-leonardo.frt74
-rw-r--r--amforth-6.5/appl/arduino/blocks/ports-mega128.frt104
-rw-r--r--amforth-6.5/appl/arduino/blocks/ports-standard.frt49
-rw-r--r--amforth-6.5/appl/arduino/blocks/test_danger_shield.fs437
-rw-r--r--amforth-6.5/appl/arduino/blocks/wiring_analog.frt65
-rw-r--r--amforth-6.5/appl/arduino/build.xml95
-rw-r--r--amforth-6.5/appl/arduino/dict_appl.inc7
-rw-r--r--amforth-6.5/appl/arduino/dict_appl_core.inc2
-rw-r--r--amforth-6.5/appl/arduino/diecimila.asm9
-rw-r--r--amforth-6.5/appl/arduino/duemilanove.asm13
-rw-r--r--amforth-6.5/appl/arduino/duemilanove.eep.hex7
-rw-r--r--amforth-6.5/appl/arduino/duemilanove.hex613
-rw-r--r--amforth-6.5/appl/arduino/duemilanove.lst10094
-rw-r--r--amforth-6.5/appl/arduino/duemilanove.map2021
-rw-r--r--amforth-6.5/appl/arduino/leonardo.asm15
-rw-r--r--amforth-6.5/appl/arduino/leonardo.eep.hex7
-rw-r--r--amforth-6.5/appl/arduino/leonardo.hex630
-rw-r--r--amforth-6.5/appl/arduino/leonardo.lst10136
-rw-r--r--amforth-6.5/appl/arduino/leonardo.map2333
-rw-r--r--amforth-6.5/appl/arduino/mega128.asm18
-rw-r--r--amforth-6.5/appl/arduino/mega128.eep.hex7
-rw-r--r--amforth-6.5/appl/arduino/mega128.hex657
-rw-r--r--amforth-6.5/appl/arduino/mega128.lst10415
-rw-r--r--amforth-6.5/appl/arduino/mega128.map2715
-rw-r--r--amforth-6.5/appl/arduino/readme.txt50
-rw-r--r--amforth-6.5/appl/arduino/sanguino.asm10
-rw-r--r--amforth-6.5/appl/arduino/uno.asm15
-rw-r--r--amforth-6.5/appl/arduino/uno.eep.hex7
-rw-r--r--amforth-6.5/appl/arduino/uno.hex620
-rw-r--r--amforth-6.5/appl/arduino/uno.lst10263
-rw-r--r--amforth-6.5/appl/arduino/uno.map2030
-rw-r--r--amforth-6.5/appl/arduino/words/applturnkey.asm25
-rw-r--r--amforth-6.5/appl/atmega2561/atmega256.asm18
-rw-r--r--amforth-6.5/appl/atmega2561/atmega256.eep.hex7
-rw-r--r--amforth-6.5/appl/atmega2561/atmega256.hex647
-rw-r--r--amforth-6.5/appl/atmega2561/atmega256.lst10182
-rw-r--r--amforth-6.5/appl/atmega2561/atmega256.map2503
-rw-r--r--amforth-6.5/appl/atmega2561/build.xml21
-rw-r--r--amforth-6.5/appl/atmega2561/dict_appl.inc5
-rw-r--r--amforth-6.5/appl/atmega2561/dict_appl_core.inc2
-rw-r--r--amforth-6.5/appl/atmega2561/words/applturnkey.asm32
-rw-r--r--amforth-6.5/appl/avr-build.xml113
-rw-r--r--amforth-6.5/appl/build.xml20
-rw-r--r--amforth-6.5/appl/common-build.xml47
-rw-r--r--amforth-6.5/appl/eval-pollin/blocks/hd44780.frt115
-rw-r--r--amforth-6.5/appl/eval-pollin/blocks/hello-world.frt81
-rw-r--r--amforth-6.5/appl/eval-pollin/blocks/netio.frt32
-rw-r--r--amforth-6.5/appl/eval-pollin/build.xml15
-rw-r--r--amforth-6.5/appl/eval-pollin/dict_appl.inc8
-rw-r--r--amforth-6.5/appl/eval-pollin/dict_appl_core.inc2
-rw-r--r--amforth-6.5/appl/eval-pollin/p1284-16.eep.hex7
-rw-r--r--amforth-6.5/appl/eval-pollin/p1284-16.hex646
-rw-r--r--amforth-6.5/appl/eval-pollin/p1284-16.lst10495
-rw-r--r--amforth-6.5/appl/eval-pollin/p1284-16.map2253
-rw-r--r--amforth-6.5/appl/eval-pollin/p1284-16.xml36
-rw-r--r--amforth-6.5/appl/eval-pollin/p16-8.eep.hex7
-rw-r--r--amforth-6.5/appl/eval-pollin/p16-8.hex625
-rw-r--r--amforth-6.5/appl/eval-pollin/p16-8.lst10363
-rw-r--r--amforth-6.5/appl/eval-pollin/p16-8.map1961
-rw-r--r--amforth-6.5/appl/eval-pollin/p16-8.xml36
-rw-r--r--amforth-6.5/appl/eval-pollin/p32-16.xml45
-rw-r--r--amforth-6.5/appl/eval-pollin/p32-8.eep.hex7
-rw-r--r--amforth-6.5/appl/eval-pollin/p32-8.hex628
-rw-r--r--amforth-6.5/appl/eval-pollin/p32-8.lst10420
-rw-r--r--amforth-6.5/appl/eval-pollin/p32-8.map1933
-rw-r--r--amforth-6.5/appl/eval-pollin/p32-8.xml35
-rw-r--r--amforth-6.5/appl/eval-pollin/p328-16.eep.hex7
-rw-r--r--amforth-6.5/appl/eval-pollin/p328-16.hex633
-rw-r--r--amforth-6.5/appl/eval-pollin/p328-16.lst10427
-rw-r--r--amforth-6.5/appl/eval-pollin/p328-16.map2054
-rw-r--r--amforth-6.5/appl/eval-pollin/p328-16.xml36
-rw-r--r--amforth-6.5/appl/eval-pollin/p644-16.eep.hex7
-rw-r--r--amforth-6.5/appl/eval-pollin/p644-16.hex635
-rw-r--r--amforth-6.5/appl/eval-pollin/p644-16.lst10444
-rw-r--r--amforth-6.5/appl/eval-pollin/p644-16.map2133
-rw-r--r--amforth-6.5/appl/eval-pollin/p644-16.xml27
-rw-r--r--amforth-6.5/appl/eval-pollin/p8-12.xml25
-rw-r--r--amforth-6.5/appl/eval-pollin/pollin.asm21
-rw-r--r--amforth-6.5/appl/eval-pollin/words/applturnkey.asm30
-rw-r--r--amforth-6.5/appl/launchpad430/Makefile41
-rw-r--r--amforth-6.5/appl/launchpad430/blocks/1-ms.frt6
-rw-r--r--amforth-6.5/appl/launchpad430/build.xml40
-rw-r--r--amforth-6.5/appl/launchpad430/dict_appl.inc66
-rw-r--r--amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.hex537
-rw-r--r--amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.lst516
-rw-r--r--amforth-6.5/appl/launchpad430/lp-2553.asm17
-rw-r--r--amforth-6.5/appl/launchpad430/lp-2553.hex524
-rw-r--r--amforth-6.5/appl/launchpad430/lp-2553.lst508
-rw-r--r--amforth-6.5/appl/launchpad430/lp-5529.asm18
-rw-r--r--amforth-6.5/appl/launchpad430/lp-5529.hex522
-rw-r--r--amforth-6.5/appl/launchpad430/lp-5529.lst508
-rw-r--r--amforth-6.5/appl/launchpad430/lp-5969.asm19
-rw-r--r--amforth-6.5/appl/launchpad430/lp-5969.hex510
-rw-r--r--amforth-6.5/appl/launchpad430/lp-5969.lst508
-rw-r--r--amforth-6.5/appl/launchpad430/readme.txt31
-rw-r--r--amforth-6.5/appl/launchpad430/words/applturnkey.asm37
-rw-r--r--amforth-6.5/appl/launchpad430/words/dump.asm19
-rw-r--r--amforth-6.5/appl/msp-build.xml40
-rw-r--r--amforth-6.5/appl/programmer.properties19
-rw-r--r--amforth-6.5/appl/template/build.xml21
-rw-r--r--amforth-6.5/appl/template/dict_appl.inc32
-rw-r--r--amforth-6.5/appl/template/dict_appl_core.inc5
-rw-r--r--amforth-6.5/appl/template/makefile78
-rw-r--r--amforth-6.5/appl/template/template.asm124
-rw-r--r--amforth-6.5/appl/template/template.eep.hex7
-rw-r--r--amforth-6.5/appl/template/template.hex632
-rw-r--r--amforth-6.5/appl/template/template.lst10414
-rw-r--r--amforth-6.5/appl/template/template.map2234
-rw-r--r--amforth-6.5/appl/template/words/applturnkey.asm18
-rw-r--r--amforth-6.5/appl/template/words/build-info.asm26
-rw-r--r--amforth-6.5/appl/template/words/qmark.asm17
-rw-r--r--amforth-6.5/avr8/amforth-eeprom.inc64
-rw-r--r--amforth-6.5/avr8/amforth-interpreter.asm33
-rw-r--r--amforth-6.5/avr8/amforth-low.asm31
-rw-r--r--amforth-6.5/avr8/amforth.asm39
-rw-r--r--amforth-6.5/avr8/devices/at90can128/at90can128.frt465
-rw-r--r--amforth-6.5/avr8/devices/at90can128/device.asm145
-rw-r--r--amforth-6.5/avr8/devices/at90can128/device.inc1707
-rw-r--r--amforth-6.5/avr8/devices/at90can128/device.py507
-rw-r--r--amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/at90can128/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90can32/at90can32.frt465
-rw-r--r--amforth-6.5/avr8/devices/at90can32/device.asm139
-rw-r--r--amforth-6.5/avr8/devices/at90can32/device.inc1707
-rw-r--r--amforth-6.5/avr8/devices/at90can32/device.py507
-rw-r--r--amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/at90can32/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90can64/at90can64.frt465
-rw-r--r--amforth-6.5/avr8/devices/at90can64/device.asm139
-rw-r--r--amforth-6.5/avr8/devices/at90can64/device.inc1707
-rw-r--r--amforth-6.5/avr8/devices/at90can64/device.py507
-rw-r--r--amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/at90can64/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt381
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/device.asm121
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/device.inc1143
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/device.py404
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt71
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt69
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt114
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt21
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt17
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt90
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt126
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt27
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt25
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt15
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.asm52
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.frt613
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.py389
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt193
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/device.asm137
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/device.inc1539
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/device.py155
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt423
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/device.asm123
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/device.inc1281
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/device.py448
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt423
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.asm123
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.inc1281
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.py448
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt217
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/device.asm139
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/device.inc1791
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/device.py175
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt478
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/device.asm125
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/device.inc1467
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/device.py505
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt478
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/device.asm125
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/device.inc1467
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/device.py505
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt370
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.asm96
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.inc1080
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.py389
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt486
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/device.asm145
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/device.inc1611
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/device.py523
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt587
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/device.asm146
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/device.inc1914
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/device.py625
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-rw-r--r--amforth-6.5/avr8/devices/at90usb162/at90usb162.frt367
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/device.asm113
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/device.inc1155
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/device.py387
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/at90usb646.frt587
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/device.asm140
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/device.inc1914
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/device.py625
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/at90usb647.frt587
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/device.asm140
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/device.inc1914
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/device.py625
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/at90usb82.frt367
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/device.asm113
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/device.inc1155
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/device.py387
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-rw-r--r--amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/words/sleep.asm19
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-rw-r--r--amforth-6.5/msp430/words/environment.asm4
-rw-r--r--amforth-6.5/msp430/words/equal.asm7
-rw-r--r--amforth-6.5/msp430/words/execute.asm7
-rw-r--r--amforth-6.5/msp430/words/exit.asm4
-rw-r--r--amforth-6.5/msp430/words/fetch.asm4
-rw-r--r--amforth-6.5/msp430/words/fill.asm12
-rw-r--r--amforth-6.5/msp430/words/fm-mod.asm12
-rw-r--r--amforth-6.5/msp430/words/forth-recognizer.asm8
-rw-r--r--amforth-6.5/msp430/words/forth-wordlist.asm4
-rw-r--r--amforth-6.5/msp430/words/g-mark.asm3
-rw-r--r--amforth-6.5/msp430/words/g-resolve.asm5
-rw-r--r--amforth-6.5/msp430/words/get-current.asm2
-rw-r--r--amforth-6.5/msp430/words/greater.asm3
-rw-r--r--amforth-6.5/msp430/words/header.asm14
-rw-r--r--amforth-6.5/msp430/words/here.asm4
-rw-r--r--amforth-6.5/msp430/words/hld.asm4
-rw-r--r--amforth-6.5/msp430/words/i-allot.asm4
-rw-r--r--amforth-6.5/msp430/words/i-cellplus.asm4
-rw-r--r--amforth-6.5/msp430/words/i-fetch.asm2
-rw-r--r--amforth-6.5/msp430/words/i-here.asm4
-rw-r--r--amforth-6.5/msp430/words/i.asm8
-rw-r--r--amforth-6.5/msp430/words/ic-fetch.asm2
-rw-r--r--amforth-6.5/msp430/words/icount.asm3
-rw-r--r--amforth-6.5/msp430/words/idp.asm4
-rw-r--r--amforth-6.5/msp430/words/immediate-q.asm15
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-rw-r--r--amforth-6.5/msp430/words/int-fetch.asm4
-rw-r--r--amforth-6.5/msp430/words/int-off.asm3
-rw-r--r--amforth-6.5/msp430/words/int-on.asm3
-rw-r--r--amforth-6.5/msp430/words/int-store.asm5
-rw-r--r--amforth-6.5/msp430/words/int-trap.asm4
-rw-r--r--amforth-6.5/msp430/words/invert.asm4
-rw-r--r--amforth-6.5/msp430/words/isr-exec.asm7
-rw-r--r--amforth-6.5/msp430/words/itype.asm6
-rw-r--r--amforth-6.5/msp430/words/j.asm9
-rw-r--r--amforth-6.5/msp430/words/l-0.asm3
-rw-r--r--amforth-6.5/msp430/words/l-mark.asm2
-rw-r--r--amforth-6.5/msp430/words/l-resolve.asm4
-rw-r--r--amforth-6.5/msp430/words/latest.asm3
-rw-r--r--amforth-6.5/msp430/words/less.asm7
-rw-r--r--amforth-6.5/msp430/words/lit.asm8
-rw-r--r--amforth-6.5/msp430/words/lp.asm4
-rw-r--r--amforth-6.5/msp430/words/lshift.asm10
-rw-r--r--amforth-6.5/msp430/words/m-plus.asm6
-rw-r--r--amforth-6.5/msp430/words/m-star.asm8
-rw-r--r--amforth-6.5/msp430/words/mcu-sr-fetch.asm5
-rw-r--r--amforth-6.5/msp430/words/minus.asm6
-rw-r--r--amforth-6.5/msp430/words/n_r_from.asm17
-rw-r--r--amforth-6.5/msp430/words/n_to_r.asm15
-rw-r--r--amforth-6.5/msp430/words/name2flags.asm3
-rw-r--r--amforth-6.5/msp430/words/negate.asm5
-rw-r--r--amforth-6.5/msp430/words/newest.asm3
-rw-r--r--amforth-6.5/msp430/words/nfa-to-cfa.asm5
-rw-r--r--amforth-6.5/msp430/words/nfa-to-lfa.asm4
-rw-r--r--amforth-6.5/msp430/words/nip.asm4
-rw-r--r--amforth-6.5/msp430/words/or.asm4
-rw-r--r--amforth-6.5/msp430/words/over.asm8
-rw-r--r--amforth-6.5/msp430/words/pause.asm7
-rw-r--r--amforth-6.5/msp430/words/plus-store.asm5
-rw-r--r--amforth-6.5/msp430/words/plus.asm4
-rw-r--r--amforth-6.5/msp430/words/q-branch.asm7
-rw-r--r--amforth-6.5/msp430/words/qdup.asm5
-rw-r--r--amforth-6.5/msp430/words/r-0.asm3
-rw-r--r--amforth-6.5/msp430/words/r-fetch.asm6
-rw-r--r--amforth-6.5/msp430/words/r-from.asm6
-rw-r--r--amforth-6.5/msp430/words/reg-a.asm95
-rw-r--r--amforth-6.5/msp430/words/restore.asm7
-rw-r--r--amforth-6.5/msp430/words/rot.asm7
-rw-r--r--amforth-6.5/msp430/words/rp-fetch.asm6
-rw-r--r--amforth-6.5/msp430/words/rp-store.asm5
-rw-r--r--amforth-6.5/msp430/words/rshift.asm11
-rw-r--r--amforth-6.5/msp430/words/s-0.asm3
-rw-r--r--amforth-6.5/msp430/words/s-equal.asm19
-rw-r--r--amforth-6.5/msp430/words/scomma.asm10
-rw-r--r--amforth-6.5/msp430/words/set-current.asm2
-rw-r--r--amforth-6.5/msp430/words/slash-mod.asm4
-rw-r--r--amforth-6.5/msp430/words/sm-rem.asm12
-rw-r--r--amforth-6.5/msp430/words/sp-fetch.asm6
-rw-r--r--amforth-6.5/msp430/words/sp-store.asm5
-rw-r--r--amforth-6.5/msp430/words/state.asm4
-rw-r--r--amforth-6.5/msp430/words/store.asm5
-rw-r--r--amforth-6.5/msp430/words/swap.asm6
-rw-r--r--amforth-6.5/msp430/words/to-body.asm3
-rw-r--r--amforth-6.5/msp430/words/to-r.asm5
-rw-r--r--amforth-6.5/msp430/words/turnkey.asm5
-rw-r--r--amforth-6.5/msp430/words/u-less.asm6
-rw-r--r--amforth-6.5/msp430/words/uinit.asm39
-rw-r--r--amforth-6.5/msp430/words/um-slash-mod.asm31
-rw-r--r--amforth-6.5/msp430/words/um-star.asm38
-rw-r--r--amforth-6.5/msp430/words/unloop.asm5
-rw-r--r--amforth-6.5/msp430/words/up.asm11
-rw-r--r--amforth-6.5/msp430/words/usart-rx.asm10
-rw-r--r--amforth-6.5/msp430/words/usart-rxq.asm14
-rw-r--r--amforth-6.5/msp430/words/usart-tx.asm14
-rw-r--r--amforth-6.5/msp430/words/usart-txq.asm15
-rw-r--r--amforth-6.5/msp430/words/user.asm9
-rw-r--r--amforth-6.5/msp430/words/wlscope.asm5
-rw-r--r--amforth-6.5/msp430/words/wordlist.asm14
-rw-r--r--amforth-6.5/msp430/words/xor.asm5
-rw-r--r--amforth-6.5/msp430/words/zero-equal.asm5
-rw-r--r--amforth-6.5/msp430/words/zero-less.asm6
-rw-r--r--amforth-6.5/readme.txt54
-rw-r--r--amforth-6.5/tests/assembler-test.frt58
-rw-r--r--amforth-6.5/tests/multitask-test.frt45
-rw-r--r--amforth-6.5/tests/quotations-test.frt19
-rw-r--r--amforth-6.5/tests/test-quotations.frt19
-rw-r--r--amforth-6.5/tests/test-rega.frt41
-rw-r--r--amforth-6.5/tools/am4up.c120
-rwxr-xr-xamforth-6.5/tools/amforth-shell.py1365
-rwxr-xr-xamforth-6.5/tools/amforth-upload.py269
1906 files changed, 0 insertions, 456318 deletions
diff --git a/amforth-6.5/LICENSE.txt b/amforth-6.5/LICENSE.txt
deleted file mode 100644
index 94a9ed0..0000000
--- a/amforth-6.5/LICENSE.txt
+++ /dev/null
@@ -1,674 +0,0 @@
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diff --git a/amforth-6.5/appl/arduino/Makefile b/amforth-6.5/appl/arduino/Makefile
deleted file mode 100644
index acec7c8..0000000
--- a/amforth-6.5/appl/arduino/Makefile
+++ /dev/null
@@ -1,191 +0,0 @@
-# Simple makefile for building the
-# Arduino amforth vor various targets
-
-# Examples of usage for Arduino leonardo:
-#
-# 1) Assemble the whole flash and eemprom files
-# make leonardo.hex
-#
-# 2) Backup the current flash & eeprom values
-# make leonardo.bak
-#
-# 3) Erase the whole MCU Flash
-# make leonardo.era
-#
-# 4) Upload the new firmware using the hex file generated
-# make leonardo
-#
-# 5) Set the appropiate MCU fuses
-# make leonardo.fuse
-#
-# 6) Clear files (except backup)
-# make leonardo.clr
-
-
-SHELL=/bin/bash
-
-##############################
-# TARGET DEPENDANT VARIABLES #
-##############################
-
-# 1) MCU should be identical to the device
-# Look at the .../avr8/devices/ folder
-# 2) PART is the device model passed to avrdude.
-# 3) LFUSE, HFUSE, EFUSE are the device-specific fuses
-# there is a useful fuse calc tool at:
-# http://www.engbedded.com/fusecalc/
-# --------------------------------------
-# Example fuse settings for 'leonardo'
-# Low Fuse LFUSE=0xFF
-# - No Div8 prescaler,
-# - No ouptput Clock,
-# - Low Crystal mode: >=8 MHz + start-up time: 16K CK cycles + 65 ms
-# High Fuse HFUSE=0xD9
-# - Enable Serial Programming & Downloading
-# - Bootsize 2048 words (4096 bytes)
-# Extended Fuse EFUSE=0xF9
-# - Brown-out detection @ 3.5V
-# - no Hardware Boot Vector (=boot at $0000)
-# --------------------------------------
-
-leonardo: PART=m32u4
-leonardo.hex: MCU=atmega32u4
-leonardo.era: PART=m32u4
-leonardo.bak: PART=m32u4
-leonardo.fuse: PART=m32u4
-leonardo.fuse: LFUSE=0xFF
-leonardo.fuse: HFUSE=0xD9
-leonardo.fuse: EFUSE=0xE9
-
-uno: PART=m328p
-uno.hex: MCU=atmega328p
-uno.era: PART=m328p
-uno.bak: PART=m328p
-uno.fuse: PART=m328p
-uno.fuse: LFUSE=0xFF
-uno.fuse: HFUSE=0xD9
-uno.fuse: EFUSE=0x05
-
-mega128: PART=m1280
-mega128.hex: MCU=atmega1280
-mega128.era: PART=m1280
-mega128.bak: PART=m1280
-mega128.fuse: PART=m1280
-mega128.fuse: LFUSE=0xFF
-mega128.fuse: HFUSE=0xD9
-mega128.fuse: EFUSE=0xF7
-
-sanguino: PART=m644p
-sanguino.hex: MCU=atmega644p
-sanguino.era: PART=m644p
-sanguino.bak: PART=m644p
-sanguino.fuse: PART=m644p
-sanguino.fuse: LFUSE=0xFF
-sanguino.fuse: HFUSE=0xF9
-sanguino.fuse: EFUSE=0xFD
-
-duemilanove: PART=m328p
-duemilanove.hex: MCU=atmega328p
-duemilanove.era: PART=m328p
-duemilanove.bak: PART=m328p
-duemilanove.fuse: PART=m328p
-duemilanove.fuse: LFUSE=0xFF
-duemilanove.fuse: HFUSE=0xD9
-duemilanove.fuse: EFUSE=0x05
-
-diecimila: PART=m168
-diecimila.hex: MCU=atmega168
-diecimila.era: PART=m168
-diecimila.bak: PART=m168
-diecimila.fuse: PART=m168
-diecimila.fuse: LFUSE=0xFF
-diecimila.fuse: HFUSE=0xDD
-diecimila.fuse: EFUSE=0xF9
-
-# AMFORTH VERSION TO USE
-# 'code' for trunk and x.y for the releases (i.e 5.0)
-#VERSION=5.0
-VERSION=code
-CORE=$(AMFORTH)/avr8
-
-# directories
-ATMEL=$(AMFORTH)/avr8/Atmel
-
-# ------------------------
-# PROGRAMMER CONFIGURATION
-# ------------------------
-
-PROGRAMMER=avrisp2
-PORT=/dev/ttyUSB0
-
-AVRDUDE=avrdude
-AVRDUDE_FLAGS=-q -P $(PORT) -c $(PROGRAMMER)
-
-# ----------------
-# ASSEMBLER TO USE
-# ----------------
-
-AS_INCLUDE=-I $(ATMEL)/Appnotes2 -I$(CORE) -I$(CORE)/devices/ -I$(AMFORTH)/common
-
-ASM=wine $(ATMEL)/avrasm2.exe
-# flags Specific to avrasm2.exe
-AS_FLAGS=$(AS_INCLUDE) -fI -v0
-
-#ASM=avra $(AS_FLAGS)
-
-#--------------------------
-# Generic assemble patterns
-#--------------------------
-
-# Assemble the target
-%.hex : %.asm
- @echo "Producing Hexfiles for Arduino $*"
- @$(ASM) $(AS_FLAGS) -I $(CORE)/devices/$(MCU) -e $*.eep.hex -m $*.map -l $*.lst $<
-
-# Flash the target
-% : %.hex
- @echo "Uploading Hexfiles to Arduino $*"
- $(AVRDUDE) $(AVRDUDE_FLAGS) -p $(PART) -e -U flash:w:$*.hex:i -U eeprom:w:$*.eep.hex:i
-
-# Set the fuse bits
-%.fuse :
- @echo "Setting fuses to Arduino $*"
- $(AVRDUDE) $(AVRDUDE_FLAGS) -p $(PART) -U efuse:w:$(EFUSE):m -U hfuse:w:$(HFUSE):m -U lfuse:w:$(LFUSE):m
-
-# Erase the whole MCU
-%.era :
- @echo "Erasing entire Arduino $*"
- $(AVRDUDE) $(AVRDUDE_FLAGS) -p $(PART) -e
-
-# Clear assembled & auxilars files
-%.clr:
- @echo "Cleaning all aux files"
- @rm -f $*.hex ; rm -f $*.eep.hex ; rm -f $*.lst ; rm -f $*.map ; rm -f $*.cof ; rm -f $*.obj
-
-# Backup arduino Flash & EEPROM files
-%.bak:
- @echo "Backup Flash & EEPRON from Arduino $*"
- $(AVRDUDE) $(AVRDUDE_FLAGS) -p $(PART) -U flash:r:$*.hex.bak:i -U eeprom:r:$*.eep.hex.bak:i
-
-# ----------------------------------------------------------
-
-GENERIC_DEPENDECIES=*.inc words/*.asm $(CORE)/*.asm $(CORE)/words/*.asm $(CORE)/drivers/*.asm
-
-# Assemble all targets is the default action
-
-TARGET = leonardo.hex uno.hex duemilanove.hex mega128.hex sanguino.hex diecimila.hex
-
-%.asm: MCU=atmega328p
-
-default: $(TARGET)
-
-$(TARGET) : $(GENERIC_DEPENDENCIES) $(CORE)/devices/*/*.asm $(CORE)/devices/*/*.inc
-
-
-# Cleans everything
-clean:
- rm -f *.hex ; rm -f *.eep.hex ; rm -f *.lst ; rm -f *.map ; rm -f *.cof ; rm -f *.obj
-
-# All other rules are target specific and must be typed one by one
-# as shown in the top.
-
diff --git a/amforth-6.5/appl/arduino/blocks/led-mega.frt b/amforth-6.5/appl/arduino/blocks/led-mega.frt
deleted file mode 100644
index ada5b36..0000000
--- a/amforth-6.5/appl/arduino/blocks/led-mega.frt
+++ /dev/null
@@ -1,38 +0,0 @@
-\ let the led at digital-13 aka PortB.7 blink
-
-\
-$25 constant PORTB
-$24 constant DDRB
-
-\ initialize the Port: change to output mode
-: led-init
- $80 DDRB c!
-;
-
-\ turn the led on
-: led-on
- $80 PORTB c!
-;
-
-\ turn the led off
-: led-off
- 0 PORTB c!
-;
-
-\ let led blink once
-: led-blink
- led-on 500 ms led-off 500 ms
-;
-
-\ let led blink until a keystroke
-: blink
- ." press any key to stop "
- begin
- led-blink
- key?
- until
- key drop \ we do not want to keep this key stroke
-;
-
-\ and do it....
-led-init blink
diff --git a/amforth-6.5/appl/arduino/blocks/led-mega.readme b/amforth-6.5/appl/arduino/blocks/led-mega.readme
deleted file mode 100644
index cc56aff..0000000
--- a/amforth-6.5/appl/arduino/blocks/led-mega.readme
+++ /dev/null
@@ -1,114 +0,0 @@
-The example for the blinking LED works on every arduino with a LED
-attached to Digital-13. It is tested on a arduino mega only however.
-
-What does the code do? It lets the LED blink and
-gives some hints for using and enjoying amforth.
-
-
-First: it defines a few constants:
-
-$25 constant PORTB
-$24 constant DDRB
-
-The arduino uses its own numbering schema for pins, but
-for now we use the atmega ones: digial-13 is the same as
-bit 7 of PORT-B. Port B has three registers, we need only
-two of them: The Data Direction Register (DDR) and the PORT
-(Output) Register. The third register is used for reading
-from the port (PIN).
-
-To quickly test the hardware enter the following commands
-
-$80 DDRB c! $80 PORTB c! <enter>
-
-The led turns on. With
-
-0 PORTB c!
-
-the led turns off. You can repeat these commands and watch the LED.
-
-The next step is to define some commands and use them. And add some
-more features that makes live easier.
-
-Forth usually uses many small words which do exactly one thing.
-When entering forth commands take care that every word is
-seperated by at least one space. In forth almost every character
-can be used as part of a command name.
-
-The first command in this example sets up the Data Direction Register
-to make the LED Port an output pin. In arduino sketch it would be
-void setup() { pinMode(13, OUTPUT); }
-
-: led-init $80 DDRB c! ;
-
-By entering the command line the interpreter will learn a new command:
-led-init. This command can be called immediatly after the command prompt
-says OK. And it can be used in further command definitions.
-
-It writes the 8bit number 128 (hex 80) to the register DDRB (hex 24)
-as defined above. This makes the 7th bit of PORTB an Output pin.
-
-Calling our newly defined word does not change anything
-visible. But with the next word, the LED will turn on
-
-: led-on $80 PORTB c! ;
-
-Here the 7th bit will be set to 1, and that makes the led to be connected
-to VCC (5V) and it will turn on (the LED is connected to ground already).
-
-If the led-on command does not turn on the LED just call the
-led-init command (again). The led-init is needed after an reset
-or power cycle as well.
-
-Now that the led is active, we want a command to turn it off. One solution
-is to repeat the command from above: 0 PORTB c! . Smarter is a new command
-word:
-
-: led-off 0 PORTB c! ;
-
-You can now use the newly defined commands to turn the led on and off:
-
- led-on led-off led-on led-off
-
-(since there is no timing involved yet, you may not even see the led glow)
-
-Our next word will simplify this, saves many keystrokes, and gives the
-real blink experience:
-
-: led-blink
- led-on 500 ms led-off 500 ms
-;
-
-Calling this command will turn the led on, waits half a second, turn it
-off again and waits again half a second before returning to the command
-prompt.
-
-With a command line like
-
-led-blink led-blink led-blink
-
-The led will blink for a few seconds.
-
-To make it blink "forever", the next word is helpful
-
-: blink-forever
- ." press any key to stop "
- begin
- led-blink
- key?
- until
- key drop \ we do not want to keep this key stroke
-;
-
-This wird prints some text ("press any key to stop) and starts a loop.
-This loop lets the led blink one and checks for a keystroke. If no key
-is pressed, the loops is repeated. If a key is pressed, the loop is
-finished. The last two commands are housekeeping: read the key pressed
-and forget it. Otherwise the key pressed would be the first character
-of the next command line.
-
-The advantage of defining many words is that you can test them immediatly.
-Thus any further code can rely on words already being tested and that
-makes debugging alot easier. The drawback of that many words? You need
-more code space for the names of the commmands. There is no real speed
-penalty however.
diff --git a/amforth-6.5/appl/arduino/blocks/ports-leonardo.frt b/amforth-6.5/appl/arduino/blocks/ports-leonardo.frt
deleted file mode 100644
index 54d1117..0000000
--- a/amforth-6.5/appl/arduino/blocks/ports-leonardo.frt
+++ /dev/null
@@ -1,74 +0,0 @@
-\
-\ port definitions for Atmegas as found on the Arduino Standard
-\ Atmega168, Atmega328p
-\
-decimal
-
-
-};
-
-PORTD 2 portpin: digital.0
-PORTD 3 portpin: digital.1
-PORTD 1 portpin: digital.2
-PORTD 0 portpin: digital.3
-PORTD 4 portpin: digital.4
-PORTC 6 portpin: digital.5
-PORTD 7 portpin: digital.6
-PORTE 6 portpin: digital.7
-
-PORTB 4 portpin: digital.8
-PORTB 5 portpin: digital.9
-PORTB 6 portpin: digital.10
-PORTB 7 portpin: digital.11
-PORTD 6 portpin: digital.12
-PORTC 7 portpin: digital.13
-
-PORTB 3 portpin: digital.14
-PORTB 1 portpin: digital.15
-PORTB 2 portpin: digital.16
-PORTB 0 portpin: digital.17
-PORTF 7 portpin: digital.18
-PORTF 6 portpin: digital.19
-
-PORTF 5 portpin: digital.20
-PORTF 4 portpin: digital.21
-PORTF 1 portpin: digital.22
-PORTF 0 portpin: digital.23
-PORTD 4 portpin: digital.24
-PORTD 7 portpin: digital.25
-PORTB 4 portpin: digital.26
-PORTB 5 portpin: digital.27
-PORTB 6 portpin: digital.28
-PORTD 6 portpin: digital.29
-
-PORTD 5 portpin: TXLED
-PORTB 0 portpin: RXLED
-PORTE 2 portpin: HWB
-
-\ some digital ports have an alternative use
-\ synonym is available since amforth 5.0
-
-synonym SPI:SS digital.17
-synonym SPI:MOSI digital.16
-synonym SPI:MISO digital.14
-synonym SPI:SCK digital.15
-
-synonym TWI:SDA digital.2
-synonym TWI:SCL digital.3
-synonym SERIAL:RX digital.0
-synonym SERIAL:TX digital.1
-synonym LED_BUILTIN digital.13
-
-synonym analog.0 digital.18
-synonym analog.1 digital.19
-synonym analog.2 digital.20
-synonym analog.3 digital.21
-synonym analog.4 digital.22
-synonym analog.5 digital.23
-
-synonym analog.6 digital.24
-synonym analog.7 digital.25
-synonym analog.8 digital.26
-synonym analog.9 digital.27
-synonym analog.10 digital.28
-synonym analog.11 digital.29
diff --git a/amforth-6.5/appl/arduino/blocks/ports-mega128.frt b/amforth-6.5/appl/arduino/blocks/ports-mega128.frt
deleted file mode 100644
index 61a32df..0000000
--- a/amforth-6.5/appl/arduino/blocks/ports-mega128.frt
+++ /dev/null
@@ -1,104 +0,0 @@
-\
-\ port definitions for Atmega128 as found on the Arduino Mega128
-\
-decimal
-PORTE 0 portpin: digital.0 \ PE 0 ** 0 ** USART0_RX
-PORTE 1 portpin: digital.1 \ PE 1 ** 1 ** USART0_TX
-PORTE 4 portpin: digital.2 \ PE 4 ** 2 ** PWM2
-PORTE 5 portpin: digital.3 \ PE 5 ** 3 ** PWM3
-PORTG 5 portpin: digital.4 \ PG 5 ** 4 ** PWM4
-PORTE 3 portpin: digital.5 \ PE 3 ** 5 ** PWM5
-PORTH 3 portpin: digital.6 \ PH 3 ** 6 ** PWM6
-PORTH 4 portpin: digital.7 \ PH 4 ** 7 ** PWM7
-PORTH 5 portpin: digital.8 \ PH 5 ** 8 ** PWM8
-PORTH 6 portpin: digital.9 \ PH 6 ** 9 ** PWM9
-PORTB 4 portpin: digital.10 \ PB 4 ** 10 ** PWM10
-PORTB 5 portpin: digital.11 \ PB 5 ** 11 ** PWM11
-PORTB 6 portpin: digital.12 \ PB 6 ** 12 ** PWM12
-PORTB 7 portpin: digital.13 \ PB 7 ** 13 ** PWM13
-PORTJ 2 portpin: digital.14 \ PJ 1 ** 14 ** USART3_TX
-PORTJ 0 portpin: digital.15 \ PJ 0 ** 15 ** USART3_RX
-PORTH 2 portpin: digital.16 \ PH 1 ** 16 ** USART2_TX
-PORTH 0 portpin: digital.17 \ PH 0 ** 17 ** USART2_RX
-PORTD 3 portpin: digital.18 \ PD 3 ** 18 ** USART1_TX
-PORTD 2 portpin: digital.19 \ PD 2 ** 19 ** USART1_RX
-PORTD 1 portpin: digital.20 \ PD 1 ** 20 ** I2C_SDA
-PORTD 0 portpin: digital.21 \ PD 0 ** 21 ** I2C_SCL
-PORTA 0 portpin: digital.22 \ PA 0 ** 22 ** D22
-PORTA 1 portpin: digital.23 \ PA 1 ** 23 ** D23
-PORTA 2 portpin: digital.24 \ PA 2 ** 24 ** D24
-PORTA 3 portpin: digital.25 \ PA 3 ** 25 ** D25
-PORTA 4 portpin: digital.26 \ PA 4 ** 26 ** D26
-PORTA 5 portpin: digital.27 \ PA 5 ** 27 ** D27
-PORTA 6 portpin: digital.28 \ PA 6 ** 28 ** D28
-PORTA 7 portpin: digital.29 \ PA 7 ** 29 ** D29
-PORTC 8 portpin: digital.30 \ PC 7 ** 30 ** D30
-PORTC 6 portpin: digital.31 \ PC 6 ** 31 ** D31
-PORTC 5 portpin: digital.32 \ PC 5 ** 32 ** D32
-PORTC 4 portpin: digital.33 \ PC 4 ** 33 ** D33
-PORTC 3 portpin: digital.34 \ PC 3 ** 34 ** D34
-PORTC 2 portpin: digital.35 \ PC 2 ** 35 ** D35
-PORTC 1 portpin: digital.36 \ PC 1 ** 36 ** D36
-PORTC 0 portpin: digital.37 \ PC 0 ** 37 ** D37
-PORTD 7 portpin: digital.38 \ PD 7 ** 38 ** D38
-PORTG 2 portpin: digital.39 \ PG 2 ** 39 ** D39
-PORTG 1 portpin: digital.40 \ PG 1 ** 40 ** D40
-PORTG 0 portpin: digital.41 \ PG 0 ** 41 ** D41
-PORTL 7 portpin: digital.42 \ PL 7 ** 42 ** D42
-PORTL 6 portpin: digital.43 \ PL 6 ** 43 ** D43
-PORTL 5 portpin: digital.44 \ PL 5 ** 44 ** D44
-PORTL 4 portpin: digital.45 \ PL 4 ** 45 ** D45
-PORTL 3 portpin: digital.46 \ PL 3 ** 46 ** D46
-PORTL 2 portpin: digital.47 \ PL 2 ** 47 ** D47
-PORTL 1 portpin: digital.48 \ PL 1 ** 48 ** D48
-PORTL 0 portpin: digital.49 \ PL 0 ** 49 ** D49
-PORTB 3 portpin: digital.50 \ PB 3 ** 50 ** SPI_MISO
-PORTB 2 portpin: digital.51 \ PB 2 ** 51 ** SPI_MOSI
-PORTB 1 portpin: digital.52 \ PB 1 ** 52 ** SPI_SCK
-PORTB 0 portpin: digital.53 \ PB 0 ** 53 ** SPI_SS
-PORTF 0 portpin: digital.54 \ PF 0 ** 54 ** A0
-PORTF 1 portpin: digital.55 \ PF 1 ** 55 ** A1
-PORTF 2 portpin: digital.56 \ PF 2 ** 56 ** A2
-PORTF 3 portpin: digital.57 \ PF 3 ** 57 ** A3
-PORTF 4 portpin: digital.58 \ PF 4 ** 58 ** A4
-PORTF 5 portpin: digital.59 \ PF 5 ** 59 ** A5
-PORTF 6 portpin: digital.60 \ PF 6 ** 60 ** A6
-PORTF 7 portpin: digital.61 \ PF 7 ** 61 ** A7
-PORTK 0 portpin: digital.62 \ PK 0 ** 62 ** A8
-PORTK 1 portpin: digital.63 \ PK 1 ** 63 ** A9
-PORTK 2 portpin: digital.64 \ PK 2 ** 64 ** A10
-PORTK 3 portpin: digital.65 \ PK 3 ** 65 ** A11
-PORTK 4 portpin: digital.66 \ PK 4 ** 66 ** A12
-PORTK 5 portpin: digital.67 \ PK 5 ** 67 ** A13
-PORTK 6 portpin: digital.68 \ PK 6 ** 68 ** A14
-PORTK 7 portpin: digital.69 \ PK 7 ** 69 ** A15
-
-\ some digital ports have an alternative use
-\ synonym is available since amforth 5.0
-
-synonym analog.0 digital.54
-synonym analog.1 digital.55
-synonym analog.2 digital.56
-synonym analog.3 digital.57
-synonym analog.4 digital.58
-synonym analog.5 digital.59
-synonym analog.6 digital.60
-synonym analog.7 digital.61
-synonym analog.8 digital.62
-synonym analog.9 digital.63
-synonym analog.10 digital.64
-synonym analog.11 digital.65
-synonym analog.12 digital.66
-synonym analog.13 digital.67
-synonym analog.14 digital.68
-synonym analog.15 digital.69
-synonym SPI:SS digital.53
-synonym SPI:MOSI digital.51
-synonym SPI:MISO digital.50
-synonym SPI:SCK digital.52
-synonym TWI:SDA digital.20
-synonym TWI:SCL digital.21
-synonym LED_BUILTIN digital.13
-
-synonym SERIAL:RX digital.0
-synonym SERIAL:TX digital.1 \ No newline at end of file
diff --git a/amforth-6.5/appl/arduino/blocks/ports-standard.frt b/amforth-6.5/appl/arduino/blocks/ports-standard.frt
deleted file mode 100644
index 5f2e2de..0000000
--- a/amforth-6.5/appl/arduino/blocks/ports-standard.frt
+++ /dev/null
@@ -1,49 +0,0 @@
-\
-\ port definitions for Atmegas as found on the Arduino Standard
-\ Atmega168, Atmega328p
-\
-decimal
-
-PORTD 0 portpin: digital.0
-PORTD 1 portpin: digital.1
-PORTD 2 portpin: digital.2
-PORTD 3 portpin: digital.3
-PORTD 4 portpin: digital.4
-PORTD 5 portpin: digital.5
-PORTD 6 portpin: digital.6
-PORTD 7 portpin: digital.7
-
-PORTB 0 portpin: digital.8
-PORTB 1 portpin: digital.9
-PORTB 2 portpin: digital.10
-PORTB 3 portpin: digital.11
-PORTB 4 portpin: digital.12
-PORTB 5 portpin: digital.13
-
-PORTC 0 portpin: digital.14
-PORTC 1 portpin: digital.15
-PORTC 2 portpin: digital.16
-PORTC 3 portpin: digital.17
-PORTC 4 portpin: digital.18
-PORTC 5 portpin: digital.19
-
-\ some digital ports have an alternative use
-\ synonym is available since amforth 5.0
-synonym SPI:SS digital.10
-synonym SPI:MOSI digital.11
-synonym SPI:MISO digital.12
-synonym SPI:SCK digital.13
-synonym TWI:SDA digital.18
-synonym TWI:SCL digital.19
-synonym LED_BUILTIN digital.13
-synonym SERIAL:RX digital.0
-synonym SERIAL:TX digital.1
-synonym analog.0 digital.14
-synonym analog.1 digital.15
-synonym analog.2 digital.16
-synonym analog.3 digital.17
-synonym analog.4 digital.18
-synonym analog.5 digital.19
-\ not on all chips but defined in arduino sources
-synonym analog.6 digital.20
-synonym analog.7 digital.21
diff --git a/amforth-6.5/appl/arduino/blocks/test_danger_shield.fs b/amforth-6.5/appl/arduino/blocks/test_danger_shield.fs
deleted file mode 100644
index 0b6d493..0000000
--- a/amforth-6.5/appl/arduino/blocks/test_danger_shield.fs
+++ /dev/null
@@ -1,437 +0,0 @@
-\ 2011-03-06 EW
-\ test arduino duemilanove + danger shield
-
-\ hw layout
-\ arduino | atmega328p | danger shield
-\ D0 | PD0 rx |
-\ D1 | PD1 tx |
-\ D2 | PD2 int0 |
-\ D3 | PD3 int1 oc2b | bz (buzzer)
-\ D4 | PD4 t0 | sr_in (shift register DS)
-\ D5 | PD5 t1 oc0b | led1
-\ D6 | PD6 oc0a | led2
-\ D7 | PD7 | sr_latch (shift register /OE)
-\ |
-\ D8 | PB0 icp | sr_clk (shift register SH_CP)
-\ D9 | PB1 oc1a |
-\ D10 | PB2 /ss oc1b | sw1 (switch)
-\ D11 | PB3 mosi oc2a | sw2 (switch)
-\ D12 | PB4 miso | sw3 (switch)
-\ D13 | PB5 sck |
-\ |
-\ A0 | PC0 adc0 | sl3 (slider)
-\ A1 | PC1 adc1 | sl2 (slider)
-\ A2 | PC2 adc2 | sl1 (slider)
-\ A3 | PC3 adc3 | light (photo cell)
-\ A4 | PC4 adc4 scl | temp (temperature)
-\ A5 | PC5 adc5 sda | knock (buzzer 2)
-
-\ make marker
-
-marker --start--
-
-decimal
-
-PORTB 2 portpin: sw1
-PORTB 3 portpin: sw2
-PORTB 4 portpin: sw3
-
-PORTD 5 portpin: led1
-PORTD 6 portpin: led2
-
-PORTD 3 portpin: bz
-
-PORTC 2 portpin: sl1
-PORTC 1 portpin: sl2
-PORTC 0 portpin: sl3
-
-PORTC 3 portpin: photocell
-PORTC 4 portpin: thermometer
-PORTC 5 portpin: knocksensor
-
-PORTD 4 portpin: sr_in
-PORTD 7 portpin: sr_oe \ output enable
-PORTB 0 portpin: sr_cl
-
-variable 1delay 20 1delay !
-: msg_quit
- ." press switch 1 (D10) to quit" cr
-;
-
-
-\ --- switches -----------------------------------------------
-: sw1?
- sw1 pin_low? if
- 20 ms \ very simple debounce
- sw1 pin_low? if
- -1
- else
- 0
- then
- else
- 0
- then
-;
-
-\ --- buzzer -------------------------------------------------
-
-\ 2 ms T_period =^= 500 Hz
-: buzz ( cycles -- )
- 0 ?do bz low 1ms bz high 1ms loop
-;
-
-\ --- analog digital converter -------------------------------
-\ --- adc ---
-
-: or! dup c@ rot or swap c! ;
-
-\ pin>pos
-\ convert bitmask of portpin: back to value (bitposition)
-: pin>pos ( pinmask portaddr -- pos )
- drop ( -- pinmask )
- log2 ( -- pos_of_most_significant_bit )
-;
-
-: adc.init ( -- )
- \ ADMUX
- \ A_ref is NOT connected externally
- \ ==> need to set bit REFS0 in register ADMUX
- [ 1 5 lshift \ ADLAR
- 1 6 lshift or \ REFS0
- ] literal ADMUX c!
- \ ADCSRA
- [ 1 7 lshift \ ADEN ADC enabled
- 1 2 lshift or \ ADPS2 prescaler = 128
- 1 1 lshift or \ ADPS1 .
- 1 or \ ADPS0 .
- ] literal ADCSRA c!
-;
-: adc.init.pin ( bitmask portaddr -- )
- over over high
- pin_input
-;
-
-1 6 lshift constant ADSC_MSK \ ADStartConversion bitmask
-: adc.start
- \ start conversion
- ADSC_MSK ADCSRA or!
-;
-: adc.wait
- \ wait for completion of conversion
- begin
- ADCSRA c@ ADSC_MSK and 0=
- until
-;
-: adc.channel! ( channel -- )
- 7 and \ clip channel to 0..7
- ADMUX c@ 7 invert and \ read ADMUX, clear old channel
- or \ add new channel
- ADMUX c! \ write
-;
-: adc.get10 ( channel -- a )
- adc.channel! adc.start adc.wait
-\ 10 bit
- ADCL c@
- ADCH c@ 8 lshift + 6 rshift
-;
-: adc.get ( channel -- a )
- adc.channel! adc.start adc.wait
-\ 8 bit
- ADCH c@
-;
-
-\ --- shift register -----------------------------------------
-
-\ --- shift register ---
-
-: bit>sr ( bit -- )
- if sr_in high else sr_in low then
- sr_cl high noop sr_cl low noop
-;
-
-: get.bit ( byte pos -- bit )
- 1 swap lshift \ -- byte bitmask
- and \ -- bit
-;
-
-\ clock one byte out, MSB first!
-: byte>sr ( byte -- )
- 8 0 do
- dup 7 i - \ 7 6 5 ... 0: MSB first!
- get.bit
- bit>sr
- loop
- drop
-;
-
-: >7seg
- invert
- byte>sr
- sr_oe low noop sr_oe high
-;
-
-
-create HexDigits
-$3f , \ 0
-$06 , \ 1
-$5b , \ 2
-$4f , \ 3
-$66 , \ 4
-$6d , \ 5
-$7d , \ 6
-$07 , \ 7
-$7f , \ 8
-$6f , \ 9
-$77 , \ A
-$7c , \ b
-$58 , \ c
-$5e , \ d
-$79 , \ E
-$71 , \ F
-
-$80 constant dec.point
-: emit.7seg ( n -- )
- dup 0 $F within if
- HexDigits + i@ >7seg
- else
- drop
- then
-;
-
-\ --- convert thermometer reading --------------------------
-
-: >T
- 51 -
- 100 256 */
- 25 +
-;
-
-: .T
- thermometer pin>pos adc.get dup . space >T . cr
-;
-
-
-\ --- test functions ---------------------------------------
-: test_switches
- ." press switch 2,3 to light up led 1,2" cr
- msg_quit
-
- begin
- sw2 pin_low? if led1 high else led1 low then
- sw3 pin_low? if led2 high else led2 low then
- sw1? until
-;
-
-: test_buzzer
- ." press switch 2 (D11) to test buzzer" cr
- msg_quit
- begin
- sw2 pin_low? if 500 buzz then
- sw1? until
-;
-
-: test_sliders
- ." move sliders" cr
- msg_quit
- begin
- sl1 pin>pos adc.get 4 u0.r space space
- sl2 pin>pos adc.get 4 u0.r space space
- sl3 pin>pos adc.get 4 u0.r $0d emit
- 1delay @ ms
- sw1? until
- cr
-;
-
-: test_photocell
- ." light/shadow photocell" cr
- msg_quit
- begin
- photocell pin>pos adc.get 4 u0.r $0d emit
- 1delay @ ms
- sw1? until
- cr
-;
-
-: test_thermometer
- ." warm/cool thermometer" cr
- msg_quit
- begin
- thermometer pin>pos adc.get 4 u0.r $0d emit
- 1delay @ ms
- sw1? until
- cr
-;
-
-
-: test_bits.7seg
- 8 0 do
- 1 i lshift >7seg
- 500 ms
- loop
-;
-: test_emit.7seg
- $10 0 do
- i emit.7seg
- 500 ms
- loop
-;
-: test_7seg
- ." show single segments on 7seg" cr
- test_bits.7seg
- 1000 ms
- ." show hex numbers on 7seg" cr
- test_emit.7seg
- 1000 ms
-;
-
-\ --- main: init, run --------------------------------------
-: init
- 20 1delay !
-
- led1 pin_output
- led2 pin_output
- bz pin_output
-
- sw1 pin_input
- sw2 pin_input
- sw3 pin_input
-
- adc.init
- sl1 adc.init.pin
- sl2 adc.init.pin
- sl3 adc.init.pin
- photocell adc.init.pin
- thermometer adc.init.pin
- knocksensor adc.init.pin
-
- sr_in high sr_in pin_output
- sr_oe high sr_oe pin_output
- sr_cl low sr_cl pin_output
- $ff >7seg
-;
-
-
-\ --- pwm: timer/counter0, led1,2 ---
-\ D5 | PD5 t1 oc0b | led1
-\ D6 | PD6 oc0a | led2
-\ timer/counter0
-\ fast pwm mode
-\ TCCR0A bits
-\ . COM0A[1,0] = 1,0 (non inverted mode)
-\ . COM0B[1,0] = 1,0 (non inverted mode)
-\ . WGM0[1,0] = 1,1 (mode3: fast pwm)
-\ TCCR0B bits
-\ . CS[2,1,0] = 0,1,1 (clk_io/64)
-
-\ TIMSK0 TIFR0 TCNT0 TCCR0B TCCR0A OCR0B OCR0A
-
-: pwm.leds.init
- 0 TCNT0 c! \ clear counter
- led1 high led1 pin_output
- led2 high led2 pin_output
- \ TCCR0A = COM0A1 | COM0B1 | WGM01 | WGM00
- %10100011 TCCR0A c!
- \ TCCR0B = CS1 | CS0
- %00000011 TCCR0B c!
-;
-\ control brightness via registers
-\ OCR0A (D6)
-\ OCR0B (D5)
-
-variable pwm5
-variable pwm6
-: test_leds_pwm
- pwm.leds.init
- 0 pwm5 !
- $ff pwm6 !
- begin
- pwm5 @ 1+ $00ff and dup pwm5 ! OCR0B c!
- pwm6 @ 1- $00ff and dup pwm6 ! OCR0A c!
- 10 ms
- key? until
-
-;
-
-: test_leds_pwm_slider
- pwm.leds.init
- \ adc.init
- \ sl1 adc.init.pin
- \ sl2 adc.init.pin
- begin
- sl1 pin>pos adc.get OCR0B c!
- sl2 pin>pos adc.get OCR0A c!
- 1 ms
- key? until
-;
-
-
-\ --- pwm: timer/counter2, buzzer ---
-\ D3 | PD3 int1 oc2b | bz
-
-\ timer/counter2
-\ clear timer on compare match, ctc mode
-\ TCCR2A bits
-\ . COM2B[1,0] = 0,1 (non inverted mode)
-\ . WGM2[1,0] = 1,0 (mode2: ctc)
-\ TCCR2B bits
-\ . CS[2,1,0] = 1,1,1 (clk_t2s/256)
-
-\ TIMSK0 TIFR0 TCNT0 TCCR0B TCCR0A OCR0B OCR0A
-
-: pwm.bz.init
- 0 TCNT2 c! \ clear counter
- bz high bz pin_output
-
- \ TCCR2A = COM0B0 | WGM01
- %00010010 TCCR2A c!
- \ TCCR2B = CS1 | CS0
- %00000110 TCCR0B c!
-;
-\ control frequency via register
-\ OCR2A
-
-: test_bz_pwm
- pwm.bz.init
- $20 OCR2A c! 200 ms
- $30 OCR2A c! 200 ms
- $40 OCR2A c! 200 ms
- $0 OCR2A c!
-;
-
-
-\ --- --- ---
-
-variable state
-8 constant max_state
-
-: run
-
- init
- 0 state !
-
- ." press switch 1 (D10) for next test" cr
- begin
-
- sw1? if
- state @ 1+
- dup max_state > if drop 0 then
- dup state !
- . cr
- then
-
-\ state @ 0 = ( do nothing )
-
- state @ 1 = if test_switches then
- state @ 2 = if test_buzzer then
- state @ 3 = if test_sliders then
- state @ 4 = if test_photocell then
- state @ 5 = if test_thermometer then
- state @ 6 = if test_7seg 1 state +! then
-
- \ wait some
- 1delay @ 5 * ms
-
- key? until
-;
-
-\ fin
diff --git a/amforth-6.5/appl/arduino/blocks/wiring_analog.frt b/amforth-6.5/appl/arduino/blocks/wiring_analog.frt
deleted file mode 100644
index e3faa9a..0000000
--- a/amforth-6.5/appl/arduino/blocks/wiring_analog.frt
+++ /dev/null
@@ -1,65 +0,0 @@
-\ analog read functions for arduino.
-\
-\ usage
-\ once (in turnkey): adc.init (sets up the subsystem)
-\ repeated: analog.X analog_read ( -- n)
-\
-
-\ \\\\\\\\\\\\\\\\\\\\\\\\\\\
-\ HELPER ROUTINES \
-\ \\\\\\\\\\\\\\\\\\\\\\\\\\\
-\ pin>channel
-\ convert bitmask of portpin: back to value (bitposition)
-: pin>channel ( pinmask portaddr -- pos )
- drop ( -- pinmask )
- log2 ( -- pos_of_most_significant_bit )
-;
-
-: adc.init ( -- )
- \ ADMUX
- \ A_ref is NOT connected externally
- \ ==> need to set bit REFS0 in register ADMUX
- [ 0 5 lshift \ ADLAR off, makes read operation simpler
- 1 6 lshift or \ REFS0
- ] literal ADMUX c!
- \ ADCSRA
- [ 1 7 lshift \ ADEN ADC enabled
- 1 2 lshift or \ ADPS2 prescaler = 128
- 1 1 lshift or \ ADPS1 .
- 1 or \ ADPS0 .
- ] literal ADCSRA c!
-;
-: adc.init.pin ( bitmask portaddr -- )
- over over high
- pin_input
-;
-
-1 6 lshift constant ADSC_MSK \ ADStartConversion bitmask
-: adc.start
- \ start conversion
- ADSC_MSK ADCSRA high
-;
-: adc.wait
- \ wait for completion of conversion
- begin
- ADCSRA c@ ADSC_MSK and 0=
- until
-;
-: adc.channel! ( channel -- )
- 7 and \ clip channel to 0..7
- ADMUX c@ 7 invert and \ read ADMUX, clear old channel
- or \ add new channel
- ADMUX c! \ write
-;
-
-: adc.get ( namedpin -- a )
- pin>channel adc.channel! adc.start adc.wait
- ADC @ \ always 10bit
-;
-
-\ make sure the ports are set up and do one
-\ conversion.
-: analog_read ( pinmask portaddr -- n )
- 2dup adc.init.pin
- adc.get
-;
diff --git a/amforth-6.5/appl/arduino/build.xml b/amforth-6.5/appl/arduino/build.xml
deleted file mode 100644
index 7affe8e..0000000
--- a/amforth-6.5/appl/arduino/build.xml
+++ /dev/null
@@ -1,95 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="ForthDuino" basedir="." default="Help">
- <import file="../avr-build.xml"/>
-
- <target name="uno.hex" description="Hexfiles for Arduino UNO (Atmega 328P) www.arduino.cc">
- <avrasm2 projectname="uno" mcu="atmega328p"/>
- </target>
-
- <target name="uno" depends="uno.hex" description="Arduino UNO Board www.arduino.cc">
- <echo>Uploading Hexfiles to Arduino UNO</echo>
- <avrdude
- type="avrisp2"
- mcu="m328p"
- flashfile="uno.hex"
- eepromfile="uno.eep.hex"
- />
- </target>
- <target name="uno.fuses" description="Set fuses for UNO">
- <echo>Writing fuses</echo>
- <avrdude-3fuses
- type="avrisp2"
- mcu="m328p"
- efuse="0x05"
- hfuse="0xd9"
- lfuse="0xff"
- />
- </target>
-
- <target name="leonardo.hex" description="Hexfiles for Arduino Leonardo (Atmega 32U4) www.arduino.cc">
- <avrasm2 projectname="leonardo" mcu="atmega32u4"/>
- </target>
-
- <target name="leonardo" depends="leonardo.hex" description="Arduino Leonardo Board www.arduino.cc">
- <echo>Uploading Hexfiles to Arduino Leonardo</echo>
- <avrdude
- type="avrisp2"
- mcu="m32u4"
- flashfile="leonardo.hex"
- eepromfile="leonardo.eep.hex"
- />
- </target>
- <target name="leonardo.fuses" description="Set fuses for LEONARDO">
- <echo>Writing fuses</echo>
- <avrdude-3fuses
- type="avrisp2"
- mcu="m32u4"
- efuse="0xc7"
- hfuse="0x99"
- lfuse="0xcf"
- />
- </target>
-
- <target name="mega128.hex" description="Hexfiles for Arduino Mega Board (Atmega1280) www.arduino.cc">
- <avrasm2 projectname="mega128" mcu="atmega1280"/>
- </target>
-
- <target name="mega128" depends="mega128.hex" description="Arduino Mega Board www.arduino.cc">
- <echo>Uploading Hexfiles to Arduino mega128</echo>
- <avrdude
- type="avrisp2"
- mcu="m1280"
- flashfile="mega128.hex"
- eepromfile="mega128.eep.hex"
- />
- </target>
-
- <target name="duemilanove.hex" description="Hexfiles for Arduino Duemilanove Board (Atmega 328P) www.arduino.cc">
- <avrasm2 projectname="duemilanove" mcu="atmega328p"/>
- </target>
-
- <target name="duemilanove" depends="duemilanove.hex" description="Arduino Duemilanove Board www.arduino.cc">
- <echo>Uploading Hexfiles to Arduino Duemilanove</echo>
- <avrdude
- type="stk200"
- mcu="m328p"
- flashfile="duemilanove.hex"
- eepromfile="duemilanove.eep.hex"
- />
- </target>
- <target name="diecimila.hex" description="Hexfiles for Arduino Diecimila Board (Atmega168) www.arduino.cc">
- <avrasm2 projectname="diecimila" mcu="atmega168"/>
- </target>
-
- <target name="diecimila" depends="diecimila.hex" description="Arduino Diecimila Board www.arduino.cc">
- <echo>Uploading Hexfiles to Arduino Diecimila</echo>
- <avrdude
- type="avrisp2"
- mcu="m168"
- flashfile="diecimila.hex"
- eepromfile="diecimila.eep.hex"
- />
- </target>
-
- <target name="compile" depends="uno.hex, mega128.hex, duemilanove.hex, leonardo.hex"/>
-</project>
diff --git a/amforth-6.5/appl/arduino/dict_appl.inc b/amforth-6.5/appl/arduino/dict_appl.inc
deleted file mode 100644
index 6a828ca..0000000
--- a/amforth-6.5/appl/arduino/dict_appl.inc
+++ /dev/null
@@ -1,7 +0,0 @@
-; this dictionary contains optional words
-; they may be moved to the core dictionary if needed
-
-.include "dict/compiler2.inc" ; additional words for the compiler
-
-.include "words/applturnkey.asm"
-
diff --git a/amforth-6.5/appl/arduino/dict_appl_core.inc b/amforth-6.5/appl/arduino/dict_appl_core.inc
deleted file mode 100644
index 93c0d8a..0000000
--- a/amforth-6.5/appl/arduino/dict_appl_core.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-; This file is intentionally left empty
-; do not delete it!
diff --git a/amforth-6.5/appl/arduino/diecimila.asm b/amforth-6.5/appl/arduino/diecimila.asm
deleted file mode 100644
index b04b52f..0000000
--- a/amforth-6.5/appl/arduino/diecimila.asm
+++ /dev/null
@@ -1,9 +0,0 @@
-.include "preamble.inc"
-
-.set WANT_IGNORECASE = 1
-
-.equ F_CPU = 16000000
-.include "drivers/usart_0.asm"
-
-; include the whole source tree.
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/arduino/duemilanove.asm b/amforth-6.5/appl/arduino/duemilanove.asm
deleted file mode 100644
index c8750ef..0000000
--- a/amforth-6.5/appl/arduino/duemilanove.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; for a description, what can be done in this
-; file see ../template/template.asm. You may want to
-; copy that file to this one and edit it afterwards.
-
-.include "preamble.inc"
-
-.set WANT_IGNORECASE = 1
-
-; cpu clock in hertz
-.equ F_CPU = 16000000
-.include "drivers/usart_0.asm"
-
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/arduino/duemilanove.eep.hex b/amforth-6.5/appl/arduino/duemilanove.eep.hex
deleted file mode 100644
index c5d5bac..0000000
--- a/amforth-6.5/appl/arduino/duemilanove.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10003400FFFF7F0AC2018E0093095C00B008710AB9
-:0A004400C4024800EC3F0100480030
-:06005C000200350621063A
-:100066007D3B680000000000FF08AF08AF080000F5
-:100076000A00A300B100780093003C0200002902A8
-:08008600C83CE73CD73C19001F
-:00000001FF
diff --git a/amforth-6.5/appl/arduino/duemilanove.hex b/amforth-6.5/appl/arduino/duemilanove.hex
deleted file mode 100644
index f6f0783..0000000
--- a/amforth-6.5/appl/arduino/duemilanove.hex
+++ /dev/null
@@ -1,613 +0,0 @@
-:020000020000FC
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diff --git a/amforth-6.5/appl/arduino/duemilanove.lst b/amforth-6.5/appl/arduino/duemilanove.lst
deleted file mode 100644
index e2162c3..0000000
--- a/amforth-6.5/appl/arduino/duemilanove.lst
+++ /dev/null
@@ -1,10094 +0,0 @@
-
-AVRASM ver. 2.1.52 duemilanove.asm Sun Apr 30 20:10:13 2017
-
-duemilanove.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega328p\device.asm'
-../../avr8/devices/atmega328p\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m328Pdef.inc'
-duemilanove.asm(11): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-duemilanove.asm(13): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(11): Including file '../../avr8\dict/appl_4k.inc'
-../../avr8\dict/appl_4k.inc(1): Including file '../../common\words/ver.asm'
-../../avr8\dict/appl_4k.inc(4): Including file '../../common\words/noop.asm'
-../../avr8\dict/appl_4k.inc(5): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/appl_4k.inc(6): Including file '../../common\words/to.asm'
-../../avr8\dict/appl_4k.inc(7): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/appl_4k.inc(8): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/appl_4k.inc(9): Including file '../../common\words/star.asm'
-../../avr8\dict/appl_4k.inc(10): Including file '../../avr8\words/j.asm'
-../../avr8\dict/appl_4k.inc(11): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/appl_4k.inc(12): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/appl_4k.inc(13): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/appl_4k.inc(14): Including file '../../common\words/2swap.asm'
-../../avr8\dict/appl_4k.inc(15): Including file '../../common\words/tib.asm'
-../../avr8\dict/appl_4k.inc(16): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/appl_4k.inc(20): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/appl_4k.inc(21): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/appl_4k.inc(22): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/appl_4k.inc(23): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/appl_4k.inc(24): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/appl_4k.inc(25): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/appl_4k.inc(26): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/appl_4k.inc(27): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/appl_4k.inc(28): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/appl_4k.inc(30): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/appl_4k.inc(31): Including file '../../common\words/hold.asm'
-../../avr8\dict/appl_4k.inc(32): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/appl_4k.inc(33): Including file '../../common\words/sharp.asm'
-../../avr8\dict/appl_4k.inc(34): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/appl_4k.inc(35): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/appl_4k.inc(36): Including file '../../common\words/sign.asm'
-../../avr8\dict/appl_4k.inc(37): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/appl_4k.inc(38): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/appl_4k.inc(39): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/appl_4k.inc(40): Including file '../../common\words/dot.asm'
-../../avr8\dict/appl_4k.inc(41): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/appl_4k.inc(42): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/appl_4k.inc(43): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/appl_4k.inc(44): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/appl_4k.inc(46): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/appl_4k.inc(47): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/appl_4k.inc(48): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/appl_4k.inc(49): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/appl_4k.inc(50): Including file '../../common\words/type.asm'
-../../avr8\dict/appl_4k.inc(51): Including file '../../common\words/tick.asm'
-../../avr8\dict/appl_4k.inc(53): Including file '../../common\words/cskip.asm'
-../../avr8\dict/appl_4k.inc(54): Including file '../../common\words/cscan.asm'
-../../avr8\dict/appl_4k.inc(55): Including file '../../common\words/accept.asm'
-../../avr8\dict/appl_4k.inc(56): Including file '../../common\words/refill.asm'
-../../avr8\dict/appl_4k.inc(57): Including file '../../common\words/char.asm'
-../../avr8\dict/appl_4k.inc(58): Including file '../../common\words/number.asm'
-../../avr8\dict/appl_4k.inc(59): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/appl_4k.inc(60): Including file '../../common\words/set-base.asm'
-../../avr8\dict/appl_4k.inc(61): Including file '../../common\words/to-number.asm'
-../../avr8\dict/appl_4k.inc(62): Including file '../../common\words/parse.asm'
-../../avr8\dict/appl_4k.inc(63): Including file '../../common\words/source.asm'
-../../avr8\dict/appl_4k.inc(64): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/appl_4k.inc(65): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/appl_4k.inc(66): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/appl_4k.inc(67): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/appl_4k.inc(68): Including file '../../common\words/depth.asm'
-../../avr8\dict/appl_4k.inc(69): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/appl_4k.inc(70): Including file '../../common\words/recognize.asm'
-../../avr8\dict/appl_4k.inc(71): Including file '../../common\words/interpret.asm'
-../../avr8\dict/appl_4k.inc(72): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/appl_4k.inc(73): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/appl_4k.inc(74): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/appl_4k.inc(75): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/appl_4k.inc(76): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/appl_4k.inc(77): Including file '../../common\words/name2string.asm'
-../../avr8\dict/appl_4k.inc(78): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/appl_4k.inc(79): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/appl_4k.inc(81): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(4): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(104): Including file '../../avr8\dict/core_4k.inc'
-../../avr8\dict/core_4k.inc(3): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_4k.inc(4): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_4k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_4k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_4k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_4k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_4k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_4k.inc(10): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_4k.inc(11): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_4k.inc(12): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_4k.inc(13): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_4k.inc(14): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_4k.inc(17): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_4k.inc(18): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_4k.inc(19): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_4k.inc(21): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_4k.inc(22): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_4k.inc(23): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_4k.inc(24): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_4k.inc(26): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_4k.inc(27): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_4k.inc(28): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_4k.inc(31): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_4k.inc(32): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_4k.inc(33): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_4k.inc(34): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_4k.inc(35): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_4k.inc(36): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_4k.inc(37): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_4k.inc(38): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_4k.inc(39): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_4k.inc(41): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_4k.inc(42): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_4k.inc(45): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_4k.inc(46): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_4k.inc(47): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_4k.inc(48): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_4k.inc(50): Including file '../../common\words/min.asm'
-../../avr8\dict/core_4k.inc(51): Including file '../../common\words/max.asm'
-../../avr8\dict/core_4k.inc(52): Including file '../../common\words/within.asm'
-../../avr8\dict/core_4k.inc(54): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_4k.inc(55): Including file '../../common\words/words.asm'
-../../avr8\dict/core_4k.inc(57): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_4k.inc(58): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_4k.inc(59): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_4k.inc(61): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_4k.inc(62): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_4k.inc(63): Including file '../../common\words/base.asm'
-../../avr8\dict/core_4k.inc(65): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_4k.inc(67): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_4k.inc(68): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_4k.inc(69): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_4k.inc(71): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_4k.inc(72): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_4k.inc(73): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_4k.inc(74): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_4k.inc(75): Including file '../../common\words/key.asm'
-../../avr8\dict/core_4k.inc(76): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_4k.inc(78): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_4k.inc(79): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_4k.inc(80): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_4k.inc(81): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_4k.inc(83): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_4k.inc(84): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_4k.inc(85): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_4k.inc(86): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_4k.inc(88): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_4k.inc(89): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_4k.inc(90): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_4k.inc(92): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_4k.inc(93): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_4k.inc(94): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_4k.inc(95): Including file '../../common\words/space.asm'
-../../avr8\dict/core_4k.inc(96): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_4k.inc(97): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_4k.inc(98): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_USART0 = 0
- .set WANT_TWI = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_SPI = 0
- .set WANT_WATCHDOG = 0
- .set WANT_CPU = 0
- .set WANT_EEPROM = 0
- .equ intvecsize = 2 ; please verify; flash size: 32768 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d0da rcall isr ; External Interrupt Request 0
- .org 4
-000004 d0d8 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d0d6 rcall isr ; Pin Change Interrupt Request 0
- .org 8
-000008 d0d4 rcall isr ; Pin Change Interrupt Request 0
- .org 10
-00000a d0d2 rcall isr ; Pin Change Interrupt Request 1
- .org 12
-00000c d0d0 rcall isr ; Watchdog Time-out Interrupt
- .org 14
-00000e d0ce rcall isr ; Timer/Counter2 Compare Match A
- .org 16
-000010 d0cc rcall isr ; Timer/Counter2 Compare Match A
- .org 18
-000012 d0ca rcall isr ; Timer/Counter2 Overflow
- .org 20
-000014 d0c8 rcall isr ; Timer/Counter1 Capture Event
- .org 22
-000016 d0c6 rcall isr ; Timer/Counter1 Compare Match A
- .org 24
-000018 d0c4 rcall isr ; Timer/Counter1 Compare Match B
- .org 26
-00001a d0c2 rcall isr ; Timer/Counter1 Overflow
- .org 28
-00001c d0c0 rcall isr ; TimerCounter0 Compare Match A
- .org 30
-00001e d0be rcall isr ; TimerCounter0 Compare Match B
- .org 32
-000020 d0bc rcall isr ; Timer/Couner0 Overflow
- .org 34
-000022 d0ba rcall isr ; SPI Serial Transfer Complete
- .org 36
-000024 d0b8 rcall isr ; USART Rx Complete
- .org 38
-000026 d0b6 rcall isr ; USART, Data Register Empty
- .org 40
-000028 d0b4 rcall isr ; USART Tx Complete
- .org 42
-00002a d0b2 rcall isr ; ADC Conversion Complete
- .org 44
-00002c d0b0 rcall isr ; EEPROM Ready
- .org 46
-00002e d0ae rcall isr ; Analog Comparator
- .org 48
-000030 d0ac rcall isr ; Two-wire Serial Interface
- .org 50
-000032 d0aa rcall isr ; Store Program Memory Read
- .equ INTVECTORS = 26
- .nooverlap
-
- ; compatability layer (maybe empty)
- .equ SPMEN = SELFPRGEN
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000033 0800 .dw 2048
- mcu_eepromsize:
-000034 0400 .dw 1024
- mcu_maxdp:
-000035 7000 .dw 28672
- mcu_numints:
-000036 001a .dw 26
- mcu_name:
-000037 000a .dw 10
-000038 5441
-000039 656d
-00003a 6167
-00003b 3233
-00003c 5038 .db "ATmega328P"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set WANT_IGNORECASE = 1
-
- ; cpu clock in hertz
- .equ F_CPU = 16000000
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-00003d ff07 .dw $ff07
-00003e 723e
-00003f 2d78
-000040 7562
-000041 0066 .db ">rx-buf",0
-000042 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000043 0044 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000044 2f08 mov temp0, tosl
-000045 9110 0110 lds temp1, usart_rx_in
-000047 e0e0 ldi zl, low(usart_rx_data)
-000048 e0f1 ldi zh, high(usart_rx_data)
-000049 0fe1 add zl, temp1
-00004a 1df3 adc zh, zeroh
-00004b 8300 st Z, temp0
-00004c 9513 inc temp1
-00004d 701f andi temp1,usart_rx_mask
-00004e 9310 0110 sts usart_rx_in, temp1
-000050 9189
-000051 9199 loadtos
-000052 940c 3804 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000054 ff06 .dw $ff06
-000055 7369
-000056 2d72
-000057 7872 .db "isr-rx"
-000058 003d .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-000059 3800 .dw DO_COLON
- usart_rx_isr:
-00005a 383c .dw XT_DOLITERAL
-00005b 00c6 .dw usart_data
-00005c 3897 .dw XT_CFETCH
-00005d 38b0 .dw XT_DUP
-00005e 383c .dw XT_DOLITERAL
-00005f 0003 .dw 3
-000060 3fde .dw XT_EQUAL
-000061 3835 .dw XT_DOCONDBRANCH
-000062 0064 .dw usart_rx_isr1
-000063 3d37 .dw XT_COLD
- usart_rx_isr1:
-000064 0043 .dw XT_TO_RXBUF
-000065 381f .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-000066 3800 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-000067 383c
-000068 0059 .dw XT_DOLITERAL, XT_ISR_RX
-000069 383c
-00006a 0024 .dw XT_DOLITERAL, URXCaddr
-00006b 3ca4 .dw XT_INTSTORE
-
-00006c 383c .dw XT_DOLITERAL
-00006d 0100 .dw usart_rx_data
-00006e 383c .dw XT_DOLITERAL
-00006f 0016 .dw usart_rx_size + 6
-000070 3953 .dw XT_ZERO
-000071 3e97 .dw XT_FILL
-000072 381f .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000073 ff06 .dw $ff06
-000074 7872
-000075 622d
-000076 6675 .db "rx-buf"
-000077 0054 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-000078 3800 .dw DO_COLON
- PFA_RX_BUFFER:
-000079 0093 .dw XT_RXQ_BUFFER
-00007a 3835 .dw XT_DOCONDBRANCH
-00007b 0079 .dw PFA_RX_BUFFER
-00007c 383c .dw XT_DOLITERAL
-00007d 0111 .dw usart_rx_out
-00007e 3897 .dw XT_CFETCH
-00007f 38b0 .dw XT_DUP
-000080 383c .dw XT_DOLITERAL
-000081 0100 .dw usart_rx_data
-000082 399c .dw XT_PLUS
-000083 3897 .dw XT_CFETCH
-000084 38c3 .dw XT_SWAP
-000085 3a2e .dw XT_1PLUS
-000086 383c .dw XT_DOLITERAL
-000087 000f .dw usart_rx_mask
-000088 3a12 .dw XT_AND
-000089 383c .dw XT_DOLITERAL
-00008a 0111 .dw usart_rx_out
-00008b 388c .dw XT_CSTORE
-00008c 381f .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-00008d ff07 .dw $ff07
-00008e 7872
-00008f 2d3f
-000090 7562
-000091 0066 .db "rx?-buf",0
-000092 0073 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-000093 3800 .dw DO_COLON
- PFA_RXQ_BUFFER:
-000094 3d2f .dw XT_PAUSE
-000095 383c .dw XT_DOLITERAL
-000096 0111 .dw usart_rx_out
-000097 3897 .dw XT_CFETCH
-000098 383c .dw XT_DOLITERAL
-000099 0110 .dw usart_rx_in
-00009a 3897 .dw XT_CFETCH
-00009b 3912 .dw XT_NOTEQUAL
-00009c 381f .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-00009d ff07 .dw $ff07
-00009e 7874
-00009f 702d
-0000a0 6c6f
-0000a1 006c .db "tx-poll",0
-0000a2 008d .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000a3 3800 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000a4 00b1 .dw XT_TXQ_POLL
-0000a5 3835 .dw XT_DOCONDBRANCH
-0000a6 00a4 .dw PFA_TX_POLL
- ; send to usart
-0000a7 383c .dw XT_DOLITERAL
-0000a8 00c6 .dw USART_DATA
-0000a9 388c .dw XT_CSTORE
-0000aa 381f .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000ab ff08 .dw $ff08
-0000ac 7874
-0000ad 2d3f
-0000ae 6f70
-0000af 6c6c .db "tx?-poll"
-0000b0 009d .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000b1 3800 .dw DO_COLON
- PFA_TXQ_POLL:
-0000b2 3d2f .dw XT_PAUSE
-0000b3 383c .dw XT_DOLITERAL
-0000b4 00c0 .dw USART_A
-0000b5 3897 .dw XT_CFETCH
-0000b6 383c .dw XT_DOLITERAL
-0000b7 0020 .dw bm_USART_TXRD
-0000b8 3a12 .dw XT_AND
-0000b9 381f .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000ba ff04 .dw $ff04
-0000bb 6275
-0000bc 7272 .db "ubrr"
-0000bd 00ab .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000be 386e .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000bf 008c .dw EE_UBRRVAL
-0000c0 3d9f .dw XT_EDEFERFETCH
-0000c1 3da9 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000c2 ff06 .dw $ff06
-0000c3 752b
-0000c4 6173
-0000c5 7472 .db "+usart"
-0000c6 00ba .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000c7 3800 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000c8 383c .dw XT_DOLITERAL
-0000c9 0098 .dw USART_B_VALUE
-0000ca 383c .dw XT_DOLITERAL
-0000cb 00c1 .dw USART_B
-0000cc 388c .dw XT_CSTORE
-
-0000cd 383c .dw XT_DOLITERAL
-0000ce 0006 .dw USART_C_VALUE
-0000cf 383c .dw XT_DOLITERAL
-0000d0 00c2 .dw USART_C | bm_USARTC_en
-0000d1 388c .dw XT_CSTORE
-
-0000d2 00be .dw XT_UBRR
-0000d3 38b0 .dw XT_DUP
-0000d4 3af8 .dw XT_BYTESWAP
-0000d5 383c .dw XT_DOLITERAL
-0000d6 00c5 .dw BAUDRATE_HIGH
-0000d7 388c .dw XT_CSTORE
-0000d8 383c .dw XT_DOLITERAL
-0000d9 00c4 .dw BAUDRATE_LOW
-0000da 388c .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000db 0066 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000dc 381f .dw XT_EXIT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 3d38 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-0000dd 920a st -Y, r0
-0000de b60f in r0, SREG
-0000df 920a st -Y, r0
- .if (pclen==3)
- .endif
-0000e0 900f pop r0
-0000e1 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-0000e2 940a dec r0
- .if intvecsize == 1 ;
- .endif
-0000e3 2cb0 mov isrflag, r0
-0000e4 93ff push zh
-0000e5 93ef push zl
-0000e6 e1e2 ldi zl, low(intcnt)
-0000e7 e0f1 ldi zh, high(intcnt)
-0000e8 9406 lsr r0 ; we use byte addresses in the counter array, not words
-0000e9 0de0 add zl, r0
-0000ea 1df3 adc zh, zeroh
-0000eb 8000 ld r0, Z
-0000ec 9403 inc r0
-0000ed 8200 st Z, r0
-0000ee 91ef pop zl
-0000ef 91ff pop zh
-
-0000f0 9009 ld r0, Y+
-0000f1 be0f out SREG, r0
-0000f2 9009 ld r0, Y+
-0000f3 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-0000f4 ff02 .dw $ff02
-0000f5 2b6d .db "m+"
-0000f6 00c2 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-0000f7 3800 .dw DO_COLON
- PFA_MPLUS:
-0000f8 3fc6 .dw XT_S2D
-0000f9 3c14 .dw XT_DPLUS
-0000fa 381f .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-0000fb ff03 .dw $ff03
-0000fc 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-0000fd 002a .db "ud*"
-0000fe 00f4 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-0000ff 3800 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000100 38b0
-000101 38fe
-000102 39df
-000103 38d8 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000104 38c3
-000105 38f5
-000106 39df
-000107 38e0
-000108 399c
-000109 381f .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00010a ff04 .dw $ff04
-00010b 6d75
-00010c 7861 .db "umax"
-00010d 00fb .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00010e 3800 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-00010f 3ec8
-000110 395b .DW XT_2DUP,XT_ULESS
-000111 3835 .dw XT_DOCONDBRANCH
-000112 0114 DEST(UMAX1)
-000113 38c3 .DW XT_SWAP
-000114 38d8 UMAX1: .DW XT_DROP
-000115 381f .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000116 ff04 .dw $ff04
-000117 6d75
-000118 6e69 .db "umin"
-000119 010a .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00011a 3800 .dw DO_COLON
- PFA_UMIN:
- .endif
-00011b 3ec8
-00011c 3966 .DW XT_2DUP,XT_UGREATER
-00011d 3835 .dw XT_DOCONDBRANCH
-00011e 0120 DEST(UMIN1)
-00011f 38c3 .DW XT_SWAP
-000120 38d8 UMIN1: .DW XT_DROP
-000121 381f .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000122 3800 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000123 383c .dw XT_DOLITERAL
-000124 8000 .dw $8000
-000125 3a12 .dw XT_AND
-000126 3919 .dw XT_ZEROEQUAL
-000127 3835 .dw XT_DOCONDBRANCH
-000128 012b DEST(IMMEDIATEQ1)
-000129 3fe5 .dw XT_ONE
-00012a 381f .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00012b 394a .dw XT_TRUE
-00012c 381f .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00012d ff0a .dw $ff0a
-00012e 616e
-00012f 656d
-000130 663e
-000131 616c
-000132 7367 .db "name>flags"
-000133 0116 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000134 3800 .dw DO_COLON
- PFA_NAME2FLAGS:
-000135 3bca .dw XT_FETCHI ; skip to link field
-000136 383c .dw XT_DOLITERAL
-000137 ff00 .dw $ff00
-000138 3a12 .dw XT_AND
-000139 381f .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .elif AMFORTH_NRWW_SIZE > 4000
- .include "dict/appl_4k.inc"
-
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-00013a ff03 .dw $ff03
-00013b 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-00013c 0072 .db "ver"
-00013d 012d .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00013e 3800 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-00013f 029f .dw XT_ENV_FORTHNAME
-000140 03c8 .dw XT_ITYPE
-000141 3fad .dw XT_SPACE
-000142 3ebc .dw XT_BASE
-000143 3878 .dw XT_FETCH
-
-000144 02ad .dw XT_ENV_FORTHVERSION
-000145 3f40 .dw XT_DECIMAL
-000146 3fc6 .dw XT_S2D
-000147 02e6 .dw XT_L_SHARP
-000148 02ee .dw XT_SHARP
-000149 383c .dw XT_DOLITERAL
-00014a 002e .dw '.'
-00014b 02d7 .dw XT_HOLD
-00014c 0304 .dw XT_SHARP_S
-00014d 030f .dw XT_SHARP_G
-00014e 03fe .dw XT_TYPE
-00014f 3ebc .dw XT_BASE
-000150 3880 .dw XT_STORE
-000151 3fad .dw XT_SPACE
-000152 02b5 .dw XT_ENV_CPU
-000153 03c8 .dw XT_ITYPE
-
-000154 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-000155 ff04 .dw $ff04
-000156 6f6e
-000157 706f .db "noop"
-000158 013a .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-000159 3800 .dw DO_COLON
- PFA_NOOP:
- .endif
-00015a 381f .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-00015b ff06 .dw $ff06
-00015c 6e75
-00015d 7375
-00015e 6465 .db "unused"
-00015f 0155 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-000160 3800 .dw DO_COLON
- PFA_UNUSED:
-000161 3a8c .dw XT_SP_FETCH
-000162 3f22 .dw XT_HERE
-000163 3992 .dw XT_MINUS
-000164 381f .dw XT_EXIT
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-000165 0002 .dw $0002
-000166 6f74 .db "to"
-000167 015b .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-000168 3800 .dw DO_COLON
- PFA_TO:
- .endif
-000169 040d .dw XT_TICK
-00016a 3fcf .dw XT_TO_BODY
-00016b 3eb6 .dw XT_STATE
-00016c 3878 .dw XT_FETCH
-00016d 3835 .dw XT_DOCONDBRANCH
-00016e 0179 DEST(PFA_TO1)
-00016f 0721 .dw XT_COMPILE
-000170 0173 .dw XT_DOTO
-000171 072c .dw XT_COMMA
-000172 381f .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-000173 3800 .dw DO_COLON
- PFA_DOTO:
- .endif
-000174 38f5 .dw XT_R_FROM
-000175 38b0 .dw XT_DUP
-000176 0185 .dw XT_ICELLPLUS
-000177 38fe .dw XT_TO_R
-000178 3bca .dw XT_FETCHI
- PFA_TO1:
-000179 38b0 .dw XT_DUP
-00017a 0185 .dw XT_ICELLPLUS
-00017b 0185 .dw XT_ICELLPLUS
-00017c 3bca .dw XT_FETCHI
-00017d 3829 .dw XT_EXECUTE
-00017e 381f .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-00017f ff07 .dw $FF07
-000180 2d69
-000181 6563
-000182 6c6c
-000183 002b .db "i-cell+",0
-000184 0165 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-000185 3800 .dw DO_COLON
- PFA_ICELLPLUS:
-000186 3a2e .dw XT_1PLUS
-000187 381f .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-000188 ff08 .dw $ff08
-000189 6369
-00018a 6d6f
-00018b 6170
-00018c 6572 .db "icompare"
-00018d 017f .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-00018e 3800 .dw DO_COLON
- PFA_ICOMPARE:
-00018f 38fe .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-000190 38ce .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-000191 38f5 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-000192 3912 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-000193 3835 .dw XT_DOCONDBRANCH
-000194 0199 .dw PFA_ICOMPARE_SAMELEN
-000195 3ed1 .dw XT_2DROP
-000196 38d8 .dw XT_DROP
-000197 394a .dw XT_TRUE
-000198 381f .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-000199 38c3 .dw XT_SWAP ; ( -- r-addr f-addr len )
-00019a 3953 .dw XT_ZERO
-00019b 07eb .dw XT_QDOCHECK
-00019c 3835 .dw XT_DOCONDBRANCH
-00019d 01be .dw PFA_ICOMPARE_DONE
-00019e 3a9a .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-00019f 38ce .dw XT_OVER
-0001a0 3878 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
-0001a1 01c1 .dw XT_ICOMPARE_LC
- .endif
-0001a2 38ce .dw XT_OVER
-0001a3 3bca .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
-0001a4 01c1 .dw XT_ICOMPARE_LC
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-0001a5 38b0 .dw XT_DUP
- ;.dw XT_BYTESWAP
-0001a6 383c .dw XT_DOLITERAL
-0001a7 0100 .dw $100
-0001a8 395b .dw XT_ULESS
-0001a9 3835 .dw XT_DOCONDBRANCH
-0001aa 01af .dw PFA_ICOMPARE_LASTCELL
-0001ab 38c3 .dw XT_SWAP
-0001ac 383c .dw XT_DOLITERAL
-0001ad 00ff .dw $00FF
-0001ae 3a12 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-0001af 3912 .dw XT_NOTEQUAL
-0001b0 3835 .dw XT_DOCONDBRANCH
-0001b1 01b6 .dw PFA_ICOMPARE_NEXTLOOP
-0001b2 3ed1 .dw XT_2DROP
-0001b3 394a .dw XT_TRUE
-0001b4 3ad3 .dw XT_UNLOOP
-0001b5 381f .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-0001b6 3a2e .dw XT_1PLUS
-0001b7 38c3 .dw XT_SWAP
-0001b8 3c8f .dw XT_CELLPLUS
-0001b9 38c3 .dw XT_SWAP
-0001ba 383c .dw XT_DOLITERAL
-0001bb 0002 .dw 2
-0001bc 3ab9 .dw XT_DOPLUSLOOP
-0001bd 019f .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-0001be 3ed1 .dw XT_2DROP
-0001bf 3953 .dw XT_ZERO
-0001c0 381f .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- ; ( cc1 cc2 -- f)
- ; Tools
- ; compares two packed characters
- ;VE_ICOMPARELC:
- ; .dw $ff08
- ; .db "icompare-lower"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ICOMPARELC
- XT_ICOMPARE_LC:
-0001c1 3800 .dw DO_COLON
- PFA_ICOMPARE_LC:
-0001c2 38b0 .dw XT_DUP
-0001c3 383c .dw XT_DOLITERAL
-0001c4 00ff .dw $00ff
-0001c5 3a12 .dw XT_AND
-0001c6 3f78 .dw XT_TOLOWER
-0001c7 38c3 .dw XT_SWAP
-0001c8 3af8 .dw XT_BYTESWAP
-0001c9 383c .dw XT_DOLITERAL
-0001ca 00ff .dw $00ff
-0001cb 3a12 .dw XT_AND
-0001cc 3f78 .dw XT_TOLOWER
-0001cd 3af8 .dw XT_BYTESWAP
-0001ce 3a1b .dw XT_OR
-0001cf 381f .dw XT_EXIT
- .endif
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-0001d0 ff01 .dw $ff01
-0001d1 002a .db "*",0
-0001d2 0188 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-0001d3 3800 .dw DO_COLON
- PFA_STAR:
- .endif
-
-0001d4 39a5 .dw XT_MSTAR
-0001d5 38d8 .dw XT_DROP
-0001d6 381f .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-0001d7 ff01 .dw $FF01
-0001d8 006a .db "j",0
-0001d9 01d0 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-0001da 3800 .dw DO_COLON
- PFA_J:
-0001db 3a75 .dw XT_RP_FETCH
-0001dc 383c .dw XT_DOLITERAL
-0001dd 0007 .dw 7
-0001de 399c .dw XT_PLUS
-0001df 3878 .dw XT_FETCH
-0001e0 3a75 .dw XT_RP_FETCH
-0001e1 383c .dw XT_DOLITERAL
-0001e2 0009 .dw 9
-0001e3 399c .dw XT_PLUS
-0001e4 3878 .dw XT_FETCH
-0001e5 399c .dw XT_PLUS
-0001e6 381f .dw XT_EXIT
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-0001e7 ff04 .dw $ff04
-0001e8 6164
-0001e9 7362 .db "dabs"
-0001ea 01d7 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-0001eb 3800 .dw DO_COLON
- PFA_DABS:
-0001ec 38b0 .dw XT_DUP
-0001ed 3920 .dw XT_ZEROLESS
-0001ee 3835 .dw XT_DOCONDBRANCH
-0001ef 01f1 .dw PFA_DABS1
-0001f0 01f8 .dw XT_DNEGATE
- PFA_DABS1:
-0001f1 381f .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-0001f2 ff07 .dw $ff07
-0001f3 6e64
-0001f4 6765
-0001f5 7461
-0001f6 0065 .db "dnegate",0
-0001f7 01e7 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-0001f8 3800 .dw DO_COLON
- PFA_DNEGATE:
-0001f9 3c3a .dw XT_DINVERT
-0001fa 3fe5 .dw XT_ONE
-0001fb 3953 .dw XT_ZERO
-0001fc 3c14 .dw XT_DPLUS
-0001fd 381f .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-0001fe ff05 .dw $ff05
-0001ff 6d63
-000200 766f
-000201 0065 .db "cmove",0
-000202 01f2 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-000203 0204 .dw PFA_CMOVE
- PFA_CMOVE:
-000204 93bf push xh
-000205 93af push xl
-000206 91e9 ld zl, Y+
-000207 91f9 ld zh, Y+ ; addr-to
-000208 91a9 ld xl, Y+
-000209 91b9 ld xh, Y+ ; addr-from
-00020a 2f09 mov temp0, tosh
-00020b 2b08 or temp0, tosl
-00020c f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00020d 911d ld temp1, X+
-00020e 9311 st Z+, temp1
-00020f 9701 sbiw tosl, 1
-000210 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-000211 91af pop xl
-000212 91bf pop xh
-000213 9189
-000214 9199 loadtos
-000215 940c 3804 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-000217 ff05 .dw $ff05
-000218 7332
-000219 6177
-00021a 0070 .db "2swap",0
-00021b 01fe .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00021c 3800 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00021d 38e0 .dw XT_ROT
-00021e 38fe .dw XT_TO_R
-00021f 38e0 .dw XT_ROT
-000220 38f5 .dw XT_R_FROM
-000221 381f .dw XT_EXIT
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-000222 ff0a .dw $ff0a
-000223 6572
-000224 6966
-000225 6c6c
-000226 742d
-000227 6269 .db "refill-tib"
-000228 0217 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-000229 3800 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-00022a 0245 .dw XT_TIB
-00022b 383c .dw XT_DOLITERAL
-00022c 005a .dw TIB_SIZE
-00022d 045d .dw XT_ACCEPT
-00022e 024b .dw XT_NUMBERTIB
-00022f 3880 .dw XT_STORE
-000230 3953 .dw XT_ZERO
-000231 3ee1 .dw XT_TO_IN
-000232 3880 .dw XT_STORE
-000233 394a .dw XT_TRUE ; -1
-000234 381f .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-000235 ff0a .dw $FF0A
-000236 6f73
-000237 7275
-000238 6563
-000239 742d
-00023a 6269 .db "source-tib"
-00023b 0222 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00023c 3800 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00023d 0245 .dw XT_TIB
-00023e 024b .dw XT_NUMBERTIB
-00023f 3878 .dw XT_FETCH
-000240 381f .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-000241 ff03 .dw $ff03
-000242 6974
-000243 0062 .db "tib",0
-000244 0235 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-000245 3847 .dw PFA_DOVARIABLE
- PFA_TIB:
-000246 012c .dw ram_tib
- .dseg
-00012c ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-000247 ff04 .dw $ff04
-000248 7423
-000249 6269 .db "#tib"
-00024a 0241 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00024b 3847 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00024c 0186 .dw ram_sharptib
- .dseg
-000186 ram_sharptib: .byte 2
- .cseg
- .endif
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00024d ff06 .dw $ff06
-00024e 6565
-00024f 723e
-000250 6d61 .db "ee>ram"
-000251 0247 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-000252 3800 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-000253 3953 .dw XT_ZERO
-000254 3a9a .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-000255 38ce .dw XT_OVER
-000256 3b5e .dw XT_FETCHE
-000257 38ce .dw XT_OVER
-000258 3880 .dw XT_STORE
-000259 3c8f .dw XT_CELLPLUS
-00025a 38c3 .dw XT_SWAP
-00025b 3c8f .dw XT_CELLPLUS
-00025c 38c3 .dw XT_SWAP
-00025d 3ac8 .dw XT_DOLOOP
-00025e 0255 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00025f 3ed1 .dw XT_2DROP
-000260 381f .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-000261 ff08 .dw $ff08
-000262 6e69
-000263 7469
-000264 722d
-000265 6d61 .db "init-ram"
-000266 024d .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-000267 3800 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-000268 383c .dw XT_DOLITERAL
-000269 006a .dw EE_INITUSER
-00026a 3b01 .dw XT_UP_FETCH
-00026b 383c .dw XT_DOLITERAL
-00026c 0022 .dw SYSUSERSIZE
-00026d 3a03 .dw XT_2SLASH
-00026e 0252 .dw XT_EE2RAM
-00026f 381f .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-000270 ff0b .dw $ff0b
-000271 6e65
-000272 6976
-000273 6f72
-000274 6d6e
-000275 6e65
-000276 0074 .db "environment",0
-000277 0261 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-000278 3847 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-000279 0044 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00027a ff09 .dw $ff09
-00027b 6f77
-00027c 6472
-00027d 696c
-00027e 7473
-00027f 0073 .db "wordlists",0
-000280 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-000281 3800 .dw DO_COLON
- PFA_ENVWORDLISTS:
-000282 383c .dw XT_DOLITERAL
-000283 0008 .dw NUMWORDLISTS
-000284 381f .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-000285 ff04 .dw $ff04
-000286 702f
-000287 6461 .db "/pad"
-000288 027a .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-000289 3800 .dw DO_COLON
- PFA_ENVSLASHPAD:
-00028a 3a8c .dw XT_SP_FETCH
-00028b 3ee7 .dw XT_PAD
-00028c 3992 .dw XT_MINUS
-00028d 381f .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-00028e ff05 .dw $ff05
-00028f 682f
-000290 6c6f
-000291 0064 .db "/hold",0
-000292 0285 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-000293 3800 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-000294 3ee7 .dw XT_PAD
-000295 3f22 .dw XT_HERE
-000296 3992 .dw XT_MINUS
-000297 381f .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-000298 ff0a .dw $ff0a
-000299 6f66
-00029a 7472
-00029b 2d68
-00029c 616e
-00029d 656d .db "forth-name"
-00029e 028e .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-00029f 3800 .dw DO_COLON
- PFA_EN_FORTHNAME:
-0002a0 0395 .dw XT_DOSLITERAL
-0002a1 0007 .dw 7
- .endif
-0002a2 6d61
-0002a3 6f66
-0002a4 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-0002a5 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-0002a6 381f .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-0002a7 ff07 .dw $ff07
-0002a8 6576
-0002a9 7372
-0002aa 6f69
-0002ab 006e .db "version",0
-0002ac 0298 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-0002ad 3800 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-0002ae 383c .dw XT_DOLITERAL
-0002af 0041 .dw 65
-0002b0 381f .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-0002b1 ff03 .dw $ff03
-0002b2 7063
-0002b3 0075 .db "cpu",0
-0002b4 02a7 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-0002b5 3800 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-0002b6 383c .dw XT_DOLITERAL
-0002b7 0037 .dw mcu_name
-0002b8 03f4 .dw XT_ICOUNT
-0002b9 381f .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-0002ba ff08 .dw $ff08
-0002bb 636d
-0002bc 2d75
-0002bd 6e69
-0002be 6f66 .db "mcu-info"
-0002bf 02b1 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-0002c0 3800 .dw DO_COLON
- PFA_EN_MCUINFO:
-0002c1 383c .dw XT_DOLITERAL
-0002c2 0033 .dw mcu_info
-0002c3 381f .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-0002c4 ff05 .dw $ff05
-0002c5 752f
-0002c6 6573
-0002c7 0072 .db "/user",0
-0002c8 02ba .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-0002c9 3800 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-0002ca 383c .dw XT_DOLITERAL
-0002cb 002c .dw SYSUSERSIZE + APPUSERSIZE
-0002cc 381f .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-0002cd ff03 .dw $ff03
-0002ce 6c68
-0002cf 0064 .db "hld",0
-0002d0 0270 .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-0002d1 3847 .dw PFA_DOVARIABLE
- PFA_HLD:
-0002d2 0188 .dw ram_hld
-
- .dseg
-000188 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-0002d3 ff04 .dw $ff04
-0002d4 6f68
-0002d5 646c .db "hold"
-0002d6 02cd .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-0002d7 3800 .dw DO_COLON
- PFA_HOLD:
- .endif
-0002d8 02d1 .dw XT_HLD
-0002d9 38b0 .dw XT_DUP
-0002da 3878 .dw XT_FETCH
-0002db 3a34 .dw XT_1MINUS
-0002dc 38b0 .dw XT_DUP
-0002dd 38fe .dw XT_TO_R
-0002de 38c3 .dw XT_SWAP
-0002df 3880 .dw XT_STORE
-0002e0 38f5 .dw XT_R_FROM
-0002e1 388c .dw XT_CSTORE
-0002e2 381f .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-0002e3 ff02 .dw $ff02
-0002e4 233c .db "<#"
-0002e5 02d3 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-0002e6 3800 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-0002e7 3ee7 .dw XT_PAD
-0002e8 02d1 .dw XT_HLD
-0002e9 3880 .dw XT_STORE
-0002ea 381f .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-0002eb ff01 .dw $ff01
-0002ec 0023 .db "#",0
-0002ed 02e3 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-0002ee 3800 .dw DO_COLON
- PFA_SHARP:
- .endif
-0002ef 3ebc .dw XT_BASE
-0002f0 3878 .dw XT_FETCH
-0002f1 036b .dw XT_UDSLASHMOD
-0002f2 38e0 .dw XT_ROT
-0002f3 383c .dw XT_DOLITERAL
-0002f4 0009 .dw 9
-0002f5 38ce .dw XT_OVER
-0002f6 396d .dw XT_LESS
-0002f7 3835 .dw XT_DOCONDBRANCH
-0002f8 02fc DEST(PFA_SHARP1)
-0002f9 383c .dw XT_DOLITERAL
-0002fa 0007 .dw 7
-0002fb 399c .dw XT_PLUS
- PFA_SHARP1:
-0002fc 383c .dw XT_DOLITERAL
-0002fd 0030 .dw 48 ; ASCII 0
-0002fe 399c .dw XT_PLUS
-0002ff 02d7 .dw XT_HOLD
-000300 381f .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-000301 ff02 .dw $ff02
-000302 7323 .db "#s"
-000303 02eb .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-000304 3800 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000305 02ee .dw XT_SHARP
-000306 3ec8 .dw XT_2DUP
-000307 3a1b .dw XT_OR
-000308 3919 .dw XT_ZEROEQUAL
-000309 3835 .dw XT_DOCONDBRANCH
-00030a 0305 DEST(NUMS1) ; PFA_SHARP_S
-00030b 381f .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00030c ff02 .dw $ff02
-00030d 3e23 .db "#>"
-00030e 0301 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00030f 3800 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-000310 3ed1 .dw XT_2DROP
-000311 02d1 .dw XT_HLD
-000312 3878 .dw XT_FETCH
-000313 3ee7 .dw XT_PAD
-000314 38ce .dw XT_OVER
-000315 3992 .dw XT_MINUS
-000316 381f .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000317 ff04 .dw $ff04
-000318 6973
-000319 6e67 .db "sign"
-00031a 030c .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00031b 3800 .dw DO_COLON
- PFA_SIGN:
- .endif
-00031c 3920 .dw XT_ZEROLESS
-00031d 3835 .dw XT_DOCONDBRANCH
-00031e 0322 DEST(PFA_SIGN1)
-00031f 383c .dw XT_DOLITERAL
-000320 002d .dw 45 ; ascii -
-000321 02d7 .dw XT_HOLD
- PFA_SIGN1:
-000322 381f .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-000323 ff03 .dw $ff03
-000324 2e64
-000325 0072 .db "d.r",0
-000326 0317 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000327 3800 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-000328 38fe .dw XT_TO_R
-000329 3ed9 .dw XT_TUCK
-00032a 01eb .dw XT_DABS
-00032b 02e6 .dw XT_L_SHARP
-00032c 0304 .dw XT_SHARP_S
-00032d 38e0 .dw XT_ROT
-00032e 031b .dw XT_SIGN
-00032f 030f .dw XT_SHARP_G
-000330 38f5 .dw XT_R_FROM
-000331 38ce .dw XT_OVER
-000332 3992 .dw XT_MINUS
-000333 3fb6 .dw XT_SPACES
-000334 03fe .dw XT_TYPE
-000335 381f .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000336 ff02 .dw $ff02
-000337 722e .db ".r"
-000338 0323 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-000339 3800 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-00033a 38fe .dw XT_TO_R
-00033b 3fc6 .dw XT_S2D
-00033c 38f5 .dw XT_R_FROM
-00033d 0327 .dw XT_DDOTR
-00033e 381f .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00033f ff02 .dw $ff02
-000340 2e64 .db "d."
-000341 0336 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-000342 3800 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-000343 3953 .dw XT_ZERO
-000344 0327 .dw XT_DDOTR
-000345 3fad .dw XT_SPACE
-000346 381f .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-000347 ff01 .dw $ff01
-000348 002e .db ".",0
-000349 033f .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-00034a 3800 .dw DO_COLON
- PFA_DOT:
- .endif
-00034b 3fc6 .dw XT_S2D
-00034c 0342 .dw XT_DDOT
-00034d 381f .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-00034e ff03 .dw $ff03
-00034f 6475
-000350 002e .db "ud.",0
-000351 0347 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-000352 3800 .dw DO_COLON
- PFA_UDDOT:
- .endif
-000353 3953 .dw XT_ZERO
-000354 035b .dw XT_UDDOTR
-000355 3fad .dw XT_SPACE
-000356 381f .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-000357 ff04 .dw $ff04
-000358 6475
-000359 722e .db "ud.r"
-00035a 034e .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-00035b 3800 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-00035c 38fe .dw XT_TO_R
-00035d 02e6 .dw XT_L_SHARP
-00035e 0304 .dw XT_SHARP_S
-00035f 030f .dw XT_SHARP_G
-000360 38f5 .dw XT_R_FROM
-000361 38ce .dw XT_OVER
-000362 3992 .dw XT_MINUS
-000363 3fb6 .dw XT_SPACES
-000364 03fe .dw XT_TYPE
-000365 381f .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-000366 ff06 .dw $ff06
-000367 6475
-000368 6d2f
-000369 646f .db "ud/mod"
-00036a 0357 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-00036b 3800 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-00036c 38fe .dw XT_TO_R
-00036d 3953 .dw XT_ZERO
-00036e 3907 .dw XT_R_FETCH
-00036f 39c1 .dw XT_UMSLASHMOD
-000370 38f5 .dw XT_R_FROM
-000371 38c3 .dw XT_SWAP
-000372 38fe .dw XT_TO_R
-000373 39c1 .dw XT_UMSLASHMOD
-000374 38f5 .dw XT_R_FROM
-000375 381f .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-000376 ff06 .dw $ff06
-000377 6964
-000378 6967
-000379 3f74 .db "digit?"
-00037a 0366 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-00037b 3800 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-00037c 3f65 .dw XT_TOUPPER
-00037d 38b0
-00037e 383c
-00037f 0039
-000380 3977
-000381 383c
-000382 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-000383 3a12
-000384 399c
-000385 38b0
-000386 383c
-000387 0140
-000388 3977 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-000389 383c
-00038a 0107
-00038b 3a12
-00038c 3992
-00038d 383c
-00038e 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-00038f 3992
-000390 38b0
-000391 3ebc
-000392 3878
-000393 395b .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-000394 381f .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-000395 3800 .dw DO_COLON
- PFA_DOSLITERAL:
-000396 3907 .dw XT_R_FETCH ; ( -- addr )
-000397 03f4 .dw XT_ICOUNT
-000398 38f5 .dw XT_R_FROM
-000399 38ce .dw XT_OVER ; ( -- addr' n addr n)
-00039a 3a2e .dw XT_1PLUS
-00039b 3a03 .dw XT_2SLASH ; ( -- addr' n addr k )
-00039c 399c .dw XT_PLUS ; ( -- addr' n addr'' )
-00039d 3a2e .dw XT_1PLUS
-00039e 38fe .dw XT_TO_R ; ( -- )
-00039f 381f .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-0003a0 ff02 .dw $ff02
-0003a1 2c73 .db "s",$2c
-0003a2 0376 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-0003a3 3800 .dw DO_COLON
- PFA_SCOMMA:
-0003a4 38b0 .dw XT_DUP
-0003a5 03a7 .dw XT_DOSCOMMA
-0003a6 381f .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-0003a7 3800 .dw DO_COLON
- PFA_DOSCOMMA:
-0003a8 072c .dw XT_COMMA
-0003a9 38b0 .dw XT_DUP ; ( --addr len len)
-0003aa 3a03 .dw XT_2SLASH ; ( -- addr len len/2
-0003ab 3ed9 .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003ac 3a0a .dw XT_2STAR ; ( -- addr len/2 len len'
-0003ad 3992 .dw XT_MINUS ; ( -- addr len/2 rem
-0003ae 38fe .dw XT_TO_R
-0003af 3953 .dw XT_ZERO
-0003b0 07eb .dw XT_QDOCHECK
-0003b1 3835 .dw XT_DOCONDBRANCH
-0003b2 03ba .dw PFA_SCOMMA2
-0003b3 3a9a .dw XT_DODO
- PFA_SCOMMA1:
-0003b4 38b0 .dw XT_DUP ; ( -- addr addr )
-0003b5 3878 .dw XT_FETCH ; ( -- addr c1c2 )
-0003b6 072c .dw XT_COMMA ; ( -- addr )
-0003b7 3c8f .dw XT_CELLPLUS ; ( -- addr+cell )
-0003b8 3ac8 .dw XT_DOLOOP
-0003b9 03b4 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-0003ba 38f5 .dw XT_R_FROM
-0003bb 3927 .dw XT_GREATERZERO
-0003bc 3835 .dw XT_DOCONDBRANCH
-0003bd 03c1 .dw PFA_SCOMMA3
-0003be 38b0 .dw XT_DUP ; well, tricky
-0003bf 3897 .dw XT_CFETCH
-0003c0 072c .dw XT_COMMA
- PFA_SCOMMA3:
-0003c1 38d8 .dw XT_DROP ; ( -- )
-0003c2 381f .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-0003c3 ff05 .dw $ff05
-0003c4 7469
-0003c5 7079
-0003c6 0065 .db "itype",0
-0003c7 03a0 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-0003c8 3800 .dw DO_COLON
- PFA_ITYPE:
-0003c9 38b0 .dw XT_DUP ; ( --addr len len)
-0003ca 3a03 .dw XT_2SLASH ; ( -- addr len len/2
-0003cb 3ed9 .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003cc 3a0a .dw XT_2STAR ; ( -- addr len/2 len len'
-0003cd 3992 .dw XT_MINUS ; ( -- addr len/2 rem
-0003ce 38fe .dw XT_TO_R
-0003cf 3953 .dw XT_ZERO
-0003d0 07eb .dw XT_QDOCHECK
-0003d1 3835 .dw XT_DOCONDBRANCH
-0003d2 03dc .dw PFA_ITYPE2
-0003d3 3a9a .dw XT_DODO
- PFA_ITYPE1:
-0003d4 38b0 .dw XT_DUP ; ( -- addr addr )
-0003d5 3bca .dw XT_FETCHI ; ( -- addr c1c2 )
-0003d6 38b0 .dw XT_DUP
-0003d7 03e9 .dw XT_LOWEMIT
-0003d8 03e5 .dw XT_HIEMIT
-0003d9 3a2e .dw XT_1PLUS ; ( -- addr+cell )
-0003da 3ac8 .dw XT_DOLOOP
-0003db 03d4 .dw PFA_ITYPE1
- PFA_ITYPE2:
-0003dc 38f5 .dw XT_R_FROM
-0003dd 3927 .dw XT_GREATERZERO
-0003de 3835 .dw XT_DOCONDBRANCH
-0003df 03e3 .dw PFA_ITYPE3
-0003e0 38b0 .dw XT_DUP ; make sure the drop below has always something to do
-0003e1 3bca .dw XT_FETCHI
-0003e2 03e9 .dw XT_LOWEMIT
- PFA_ITYPE3:
-0003e3 38d8 .dw XT_DROP
-0003e4 381f .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-0003e5 3800 .dw DO_COLON
- PFA_HIEMIT:
-0003e6 3af8 .dw XT_BYTESWAP
-0003e7 03e9 .dw XT_LOWEMIT
-0003e8 381f .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-0003e9 3800 .dw DO_COLON
- PFA_LOWEMIT:
-0003ea 383c .dw XT_DOLITERAL
-0003eb 00ff .dw $00ff
-0003ec 3a12 .dw XT_AND
-0003ed 3ef1 .dw XT_EMIT
-0003ee 381f .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-0003ef ff06 .dw $ff06
-0003f0 6369
-0003f1 756f
-0003f2 746e .db "icount"
-0003f3 03c3 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-0003f4 3800 .dw DO_COLON
- PFA_ICOUNT:
-0003f5 38b0 .dw XT_DUP
-0003f6 3a2e .dw XT_1PLUS
-0003f7 38c3 .dw XT_SWAP
-0003f8 3bca .dw XT_FETCHI
-0003f9 381f .dw XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-0003fa ff04 .dw $ff04
-0003fb 7974
-0003fc 6570 .db "type"
-0003fd 03ef .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-0003fe 3800 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-0003ff 3f98 .dw XT_BOUNDS
-000400 07eb .dw XT_QDOCHECK
-000401 3835 .dw XT_DOCONDBRANCH
-000402 0409 DEST(PFA_TYPE2)
-000403 3a9a .dw XT_DODO
- PFA_TYPE1:
-000404 3aab .dw XT_I
-000405 3897 .dw XT_CFETCH
-000406 3ef1 .dw XT_EMIT
-000407 3ac8 .dw XT_DOLOOP
-000408 0404 DEST(PFA_TYPE1)
- PFA_TYPE2:
-000409 381f .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00040a ff01 .dw $ff01
-00040b 0027 .db "'",0
-00040c 03fa .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00040d 3800 .dw DO_COLON
- PFA_TICK:
- .endif
-00040e 0580 .dw XT_PARSENAME
-00040f 05c3 .dw XT_FORTHRECOGNIZER
-000410 05ce .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-000411 38b0 .dw XT_DUP
-000412 065b .dw XT_DT_NULL
-000413 3fde .dw XT_EQUAL
-000414 38c3 .dw XT_SWAP
-000415 3bca .dw XT_FETCHI
-000416 383c .dw XT_DOLITERAL
-000417 0159 .dw XT_NOOP
-000418 3fde .dw XT_EQUAL
-000419 3a1b .dw XT_OR
-00041a 3835 .dw XT_DOCONDBRANCH
-00041b 041f DEST(PFA_TICK1)
-00041c 383c .dw XT_DOLITERAL
-00041d fff3 .dw -13
-00041e 3d85 .dw XT_THROW
- PFA_TICK1:
-00041f 38d8 .dw XT_DROP
-000420 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-000421 ff05 .dw $ff05
-000422 7363
-000423 696b
-000424 0070 .db "cskip",0
-000425 040a .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-000426 3800 .dw DO_COLON
- PFA_CSKIP:
- .endif
-000427 38fe .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-000428 38b0 .dw XT_DUP ; ( -- addr' n' n' )
-000429 3835 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00042a 0435 DEST(PFA_CSKIP2)
-00042b 38ce .dw XT_OVER ; ( -- addr' n' addr' )
-00042c 3897 .dw XT_CFETCH ; ( -- addr' n' c' )
-00042d 3907 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-00042e 3fde .dw XT_EQUAL ; ( -- addr' n' f )
-00042f 3835 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000430 0435 DEST(PFA_CSKIP2)
-000431 3fe5 .dw XT_ONE
-000432 0571 .dw XT_SLASHSTRING
-000433 382e .dw XT_DOBRANCH
-000434 0428 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-000435 38f5 .dw XT_R_FROM
-000436 38d8 .dw XT_DROP ; ( -- addr2 n2)
-000437 381f .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-000438 ff05 .dw $ff05
-000439 7363
-00043a 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00043b 006e .db "cscan"
-00043c 0421 .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-00043d 3800 .dw DO_COLON
- PFA_CSCAN:
- .endif
-00043e 38fe .dw XT_TO_R
-00043f 38ce .dw XT_OVER
- PFA_CSCAN1:
-000440 38b0 .dw XT_DUP
-000441 3897 .dw XT_CFETCH
-000442 3907 .dw XT_R_FETCH
-000443 3fde .dw XT_EQUAL
-000444 3919 .dw XT_ZEROEQUAL
-000445 3835 .dw XT_DOCONDBRANCH
-000446 0452 DEST(PFA_CSCAN2)
-000447 38c3 .dw XT_SWAP
-000448 3a34 .dw XT_1MINUS
-000449 38c3 .dw XT_SWAP
-00044a 38ce .dw XT_OVER
-00044b 3920 .dw XT_ZEROLESS ; not negative
-00044c 3919 .dw XT_ZEROEQUAL
-00044d 3835 .dw XT_DOCONDBRANCH
-00044e 0452 DEST(PFA_CSCAN2)
-00044f 3a2e .dw XT_1PLUS
-000450 382e .dw XT_DOBRANCH
-000451 0440 DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-000452 38ef .dw XT_NIP
-000453 38ce .dw XT_OVER
-000454 3992 .dw XT_MINUS
-000455 38f5 .dw XT_R_FROM
-000456 38d8 .dw XT_DROP
-000457 381f .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-000458 ff06 .dw $ff06
-000459 6361
-00045a 6563
-00045b 7470 .db "accept"
-00045c 0438 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-00045d 3800 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-00045e 38ce
-00045f 399c
-000460 3a34
-000461 38ce .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-000462 3f02
-000463 38b0
-000464 049e
-000465 3919
-000466 3835 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-000467 0490 DEST(ACC5)
-000468 38b0
-000469 383c
-00046a 0008
-00046b 3fde
-00046c 3835 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-00046d 0480 DEST(ACC3)
-00046e 38d8
-00046f 38e0
-000470 3ec8
-000471 3977
-000472 38fe
-000473 38e0
-000474 38e0
-000475 38f5
-000476 3835 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-000477 047e DEST(ACC6)
-000478 0496
-000479 3a34
-00047a 38fe
-00047b 38ce
-00047c 38f5
-00047d 010e .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-00047e 382e ACC6: .DW XT_DOBRANCH
-00047f 048e DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-000480 38b0 .dw XT_DUP ; ( -- addr k k )
-000481 3f53 .dw XT_BL
-000482 396d .dw XT_LESS
-000483 3835 .dw XT_DOCONDBRANCH
-000484 0487 DEST(PFA_ACCEPT6)
-000485 38d8 .dw XT_DROP
-000486 3f53 .dw XT_BL
- PFA_ACCEPT6:
-000487 38b0
-000488 3ef1
-000489 38ce
-00048a 388c
-00048b 3a2e
-00048c 38ce
-00048d 011a .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-00048e 382e ACC4: .DW XT_DOBRANCH
-00048f 0462 DEST(ACC1)
-000490 38d8
-000491 38ef
-000492 38c3
-000493 3992
-000494 3fa0
-000495 381f ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-000496 3800 .dw DO_COLON
- .endif
-000497 383c .dw XT_DOLITERAL
-000498 0008 .dw 8
-000499 38b0 .dw XT_DUP
-00049a 3ef1 .dw XT_EMIT
-00049b 3fad .dw XT_SPACE
-00049c 3ef1 .dw XT_EMIT
-00049d 381f .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-00049e 3800 .dw DO_COLON
- .endif
-00049f 38b0 .dw XT_DUP
-0004a0 383c .dw XT_DOLITERAL
-0004a1 000d .dw 13
-0004a2 3fde .dw XT_EQUAL
-0004a3 38c3 .dw XT_SWAP
-0004a4 383c .dw XT_DOLITERAL
-0004a5 000a .dw 10
-0004a6 3fde .dw XT_EQUAL
-0004a7 3a1b .dw XT_OR
-0004a8 381f .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-0004a9 ff06 .dw $ff06
-0004aa 6572
-0004ab 6966
-0004ac 6c6c .db "refill"
-0004ad 0458 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-0004ae 3dfe .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-0004af 001a .dw USER_REFILL
-0004b0 3dc7 .dw XT_UDEFERFETCH
-0004b1 3dd3 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-0004b2 ff04 .dw $ff04
-0004b3 6863
-0004b4 7261 .db "char"
-0004b5 04a9 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-0004b6 3800 .dw DO_COLON
- PFA_CHAR:
- .endif
-0004b7 0580 .dw XT_PARSENAME
-0004b8 38d8 .dw XT_DROP
-0004b9 3897 .dw XT_CFETCH
-0004ba 381f .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-0004bb ff06 .dw $ff06
-0004bc 756e
-0004bd 626d
-0004be 7265 .db "number"
-0004bf 04b2 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-0004c0 3800 .dw DO_COLON
- PFA_NUMBER:
- .endif
-0004c1 3ebc .dw XT_BASE
-0004c2 3878 .dw XT_FETCH
-0004c3 38fe .dw XT_TO_R
-0004c4 0504 .dw XT_QSIGN
-0004c5 38fe .dw XT_TO_R
-0004c6 0517 .dw XT_SET_BASE
-0004c7 0504 .dw XT_QSIGN
-0004c8 38f5 .dw XT_R_FROM
-0004c9 3a1b .dw XT_OR
-0004ca 38fe .dw XT_TO_R
- ; check whether something is left
-0004cb 38b0 .dw XT_DUP
-0004cc 3919 .dw XT_ZEROEQUAL
-0004cd 3835 .dw XT_DOCONDBRANCH
-0004ce 04d7 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-0004cf 3ed1 .dw XT_2DROP
-0004d0 38f5 .dw XT_R_FROM
-0004d1 38d8 .dw XT_DROP
-0004d2 38f5 .dw XT_R_FROM
-0004d3 3ebc .dw XT_BASE
-0004d4 3880 .dw XT_STORE
-0004d5 3953 .dw XT_ZERO
-0004d6 381f .dw XT_EXIT
- PFA_NUMBER0:
-0004d7 3b1d .dw XT_2TO_R
-0004d8 3953 .dw XT_ZERO ; starting value
-0004d9 3953 .dw XT_ZERO
-0004da 3b2c .dw XT_2R_FROM
-0004db 0535 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-0004dc 38b8 .dw XT_QDUP
-0004dd 3835 .dw XT_DOCONDBRANCH
-0004de 04f9 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-0004df 3fe5 .dw XT_ONE
-0004e0 3fde .dw XT_EQUAL
-0004e1 3835 .dw XT_DOCONDBRANCH
-0004e2 04f0 DEST(PFA_NUMBER2)
- ; excatly one character is left
-0004e3 3897 .dw XT_CFETCH
-0004e4 383c .dw XT_DOLITERAL
-0004e5 002e .dw 46 ; .
-0004e6 3fde .dw XT_EQUAL
-0004e7 3835 .dw XT_DOCONDBRANCH
-0004e8 04f1 DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-0004e9 38f5 .dw XT_R_FROM
-0004ea 3835 .dw XT_DOCONDBRANCH
-0004eb 04ed DEST(PFA_NUMBER3)
-0004ec 01f8 .dw XT_DNEGATE
- PFA_NUMBER3:
-0004ed 3fea .dw XT_TWO
-0004ee 382e .dw XT_DOBRANCH
-0004ef 04ff DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-0004f0 38d8 .dw XT_DROP
- PFA_NUMBER6:
-0004f1 3ed1 .dw XT_2DROP
-0004f2 38f5 .dw XT_R_FROM
-0004f3 38d8 .dw XT_DROP
-0004f4 38f5 .dw XT_R_FROM
-0004f5 3ebc .dw XT_BASE
-0004f6 3880 .dw XT_STORE
-0004f7 3953 .dw XT_ZERO
-0004f8 381f .dw XT_EXIT
- PFA_NUMBER1:
-0004f9 3ed1 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-0004fa 38f5 .dw XT_R_FROM
-0004fb 3835 .dw XT_DOCONDBRANCH
-0004fc 04fe DEST(PFA_NUMBER4)
-0004fd 3e26 .dw XT_NEGATE
- PFA_NUMBER4:
-0004fe 3fe5 .dw XT_ONE
- PFA_NUMBER5:
-0004ff 38f5 .dw XT_R_FROM
-000500 3ebc .dw XT_BASE
-000501 3880 .dw XT_STORE
-000502 394a .dw XT_TRUE
-000503 381f .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-000504 3800 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-000505 38ce .dw XT_OVER ; ( -- addr len addr )
-000506 3897 .dw XT_CFETCH
-000507 383c .dw XT_DOLITERAL
-000508 002d .dw '-'
-000509 3fde .dw XT_EQUAL ; ( -- addr len flag )
-00050a 38b0 .dw XT_DUP
-00050b 38fe .dw XT_TO_R
-00050c 3835 .dw XT_DOCONDBRANCH
-00050d 0510 DEST(PFA_NUMBERSIGN_DONE)
-00050e 3fe5 .dw XT_ONE ; skip sign character
-00050f 0571 .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-000510 38f5 .dw XT_R_FROM
-000511 381f .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-000512 3851 .dw PFA_DOCONSTANT
- .endif
-000513 000a
-000514 0010
-000515 0002
-000516 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-000517 3800 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-000518 38ce .dw XT_OVER
-000519 3897 .dw XT_CFETCH
-00051a 383c .dw XT_DOLITERAL
-00051b 0023 .dw 35
-00051c 3992 .dw XT_MINUS
-00051d 38b0 .dw XT_DUP
-00051e 3953 .dw XT_ZERO
-00051f 383c .dw XT_DOLITERAL
-000520 0004 .dw 4
-000521 3e56 .dw XT_WITHIN
-000522 3835 .dw XT_DOCONDBRANCH
-000523 052d DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-000524 0512 .dw XT_BASES
-000525 399c .dw XT_PLUS
-000526 3bca .dw XT_FETCHI
-000527 3ebc .dw XT_BASE
-000528 3880 .dw XT_STORE
-000529 3fe5 .dw XT_ONE
-00052a 0571 .dw XT_SLASHSTRING
-00052b 382e .dw XT_DOBRANCH
-00052c 052e DEST(SET_BASE2)
- SET_BASE1:
-00052d 38d8 .dw XT_DROP
- SET_BASE2:
-00052e 381f .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00052f ff07 .dw $ff07
-000530 6e3e
-000531 6d75
-000532 6562
-000533 0072 .db ">number",0
-000534 04bb .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-000535 3800 .dw DO_COLON
-
- .endif
-
-000536 38b0
-000537 3835 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-000538 054d DEST(TONUM3)
-000539 38ce
-00053a 3897
-00053b 037b .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-00053c 3919
-00053d 3835 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-00053e 0541 DEST(TONUM2)
-00053f 38d8
-000540 381f .DW XT_DROP,XT_EXIT
-000541 38fe
-000542 021c
-000543 3ebc
-000544 3878
-000545 00ff TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000546 38f5
-000547 00f7
-000548 021c .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-000549 3fe5
-00054a 0571
-00054b 382e .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-00054c 0536 DEST(TONUM1)
-00054d 381f TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-00054e ff05 .dw $ff05
-00054f 6170
-000550 7372
-000551 0065 .db "parse",0
-000552 052f .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-000553 3800 .dw DO_COLON
- PFA_PARSE:
- .endif
-000554 38fe .dw XT_TO_R ; ( -- )
-000555 0567 .dw XT_SOURCE ; ( -- addr len)
-000556 3ee1 .dw XT_TO_IN ; ( -- addr len >in)
-000557 3878 .dw XT_FETCH
-000558 0571 .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-000559 38f5 .dw XT_R_FROM ; ( -- addr' len' c)
-00055a 043d .dw XT_CSCAN ; ( -- addr' len'')
-00055b 38b0 .dw XT_DUP ; ( -- addr' len'' len'')
-00055c 3a2e .dw XT_1PLUS
-00055d 3ee1 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-00055e 3a64 .dw XT_PLUSSTORE ; ( -- addr' len')
-00055f 3fe5 .dw XT_ONE
-000560 0571 .dw XT_SLASHSTRING
-000561 381f .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-000562 ff06 .dw $FF06
-000563 6f73
-000564 7275
-000565 6563 .db "source"
-000566 054e .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-000567 3dfe .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-000568 0016 .dw USER_SOURCE
-000569 3dc7 .dw XT_UDEFERFETCH
-00056a 3dd3 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00056b ff07 .dw $ff07
-00056c 732f
-00056d 7274
-00056e 6e69
-00056f 0067 .db "/string",0
-000570 0562 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-000571 3800 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-000572 38e0 .dw XT_ROT
-000573 38ce .dw XT_OVER
-000574 399c .dw XT_PLUS
-000575 38e0 .dw XT_ROT
-000576 38e0 .dw XT_ROT
-000577 3992 .dw XT_MINUS
-000578 381f .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-000579 ff0a .dw $FF0A
-00057a 6170
-00057b 7372
-00057c 2d65
-00057d 616e
-00057e 656d .db "parse-name"
-00057f 056b .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-000580 3800 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-000581 3f53 .dw XT_BL
-000582 0584 .dw XT_SKIPSCANCHAR
-000583 381f .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-000584 3800 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-000585 38fe .dw XT_TO_R
-000586 0567 .dw XT_SOURCE
-000587 3ee1 .dw XT_TO_IN
-000588 3878 .dw XT_FETCH
-000589 0571 .dw XT_SLASHSTRING
-
-00058a 3907 .dw XT_R_FETCH
-00058b 0426 .dw XT_CSKIP
-00058c 38f5 .dw XT_R_FROM
-00058d 043d .dw XT_CSCAN
-
- ; adjust >IN
-00058e 3ec8 .dw XT_2DUP
-00058f 399c .dw XT_PLUS
-000590 0567 .dw XT_SOURCE
-000591 38d8 .dw XT_DROP
-000592 3992 .dw XT_MINUS
-000593 3ee1 .dw XT_TO_IN
-000594 3880 .dw XT_STORE
-000595 381f .dw XT_EXIT
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-000596 ff03 .dw $ff03
-000597 7073
-000598 0030 .db "sp0",0
-000599 0579 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-00059a 386e .dw PFA_DOVALUE1
- PFA_SP0:
-00059b 0006 .dw USER_SP0
-00059c 3dc7 .dw XT_UDEFERFETCH
-00059d 3dd3 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-00059e ff02 .dw $ff02
-00059f 7073 .db "sp"
-0005a0 0596 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-0005a1 3857 .dw PFA_DOUSER
- PFA_SP:
-0005a2 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-0005a3 ff03 .dw $ff03
-0005a4 7072
-0005a5 0030 .db "rp0",0
-0005a6 059e .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-0005a7 3800 .dw DO_COLON
- PFA_RP0:
-0005a8 05ab .dw XT_DORP0
-0005a9 3878 .dw XT_FETCH
-0005aa 381f .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-0005ab 3857 .dw PFA_DOUSER
- PFA_DORP0:
-0005ac 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-0005ad ff05 .dw $ff05
-0005ae 6564
-0005af 7470
-0005b0 0068 .db "depth",0
-0005b1 05a3 .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-0005b2 3800 .dw DO_COLON
- PFA_DEPTH:
- .endif
-0005b3 059a .dw XT_SP0
-0005b4 3a8c .dw XT_SP_FETCH
-0005b5 3992 .dw XT_MINUS
-0005b6 3a03 .dw XT_2SLASH
-0005b7 3a34 .dw XT_1MINUS
-0005b8 381f .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-0005b9 ff10 .dw $ff10
-0005ba 6f66
-0005bb 7472
-0005bc 2d68
-0005bd 6572
-0005be 6f63
-0005bf 6e67
-0005c0 7a69
-0005c1 7265 .db "forth-recognizer"
-0005c2 05ad .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-0005c3 386e .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-0005c4 003e .dw CFG_FORTHRECOGNIZER
-0005c5 3d9f .dw XT_EDEFERFETCH
-0005c6 3da9 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-0005c7 ff09 .dw $ff09
-0005c8 6572
-0005c9 6f63
-0005ca 6e67
-0005cb 7a69
-0005cc 0065 .db "recognize",0
-0005cd 05b9 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-0005ce 3800 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-0005cf 383c .dw XT_DOLITERAL
-0005d0 05d9 .dw XT_RECOGNIZE_A
-0005d1 38c3 .dw XT_SWAP
-0005d2 096c .dw XT_MAPSTACK
-0005d3 3919 .dw XT_ZEROEQUAL
-0005d4 3835 .dw XT_DOCONDBRANCH
-0005d5 05d8 DEST(PFA_RECOGNIZE1)
-0005d6 3ed1 .dw XT_2DROP
-0005d7 065b .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-0005d8 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-0005d9 3800 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-0005da 38e0 .dw XT_ROT ; -- len xt addr
-0005db 38e0 .dw XT_ROT ; -- xt addr len
-0005dc 3ec8 .dw XT_2DUP
-0005dd 3b1d .dw XT_2TO_R
-0005de 38e0 .dw XT_ROT ; -- addr len xt
-0005df 3829 .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-0005e0 3b2c .dw XT_2R_FROM
-0005e1 38e0 .dw XT_ROT
-0005e2 38b0 .dw XT_DUP
-0005e3 065b .dw XT_DT_NULL
-0005e4 3fde .dw XT_EQUAL
-0005e5 3835 .dw XT_DOCONDBRANCH
-0005e6 05ea DEST(PFA_RECOGNIZE_A1)
-0005e7 38d8 .dw XT_DROP
-0005e8 3953 .dw XT_ZERO
-0005e9 381f .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-0005ea 38ef .dw XT_NIP
-0005eb 38ef .dw XT_NIP
-0005ec 394a .dw XT_TRUE
-0005ed 381f .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-0005ee ff09 .dw $ff09
-0005ef 6e69
-0005f0 6574
-0005f1 7072
-0005f2 6572
-0005f3 0074 .db "interpret",0
-0005f4 05c7 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-0005f5 3800 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-0005f6 0580 .dw XT_PARSENAME ; ( -- addr len )
-0005f7 38b0 .dw XT_DUP ; ( -- addr len flag)
-0005f8 3835 .dw XT_DOCONDBRANCH
-0005f9 0606 DEST(PFA_INTERPRET2)
-0005fa 05c3 .dw XT_FORTHRECOGNIZER
-0005fb 05ce .dw XT_RECOGNIZE
-0005fc 3eb6 .dw XT_STATE
-0005fd 3878 .dw XT_FETCH
-0005fe 3835 .dw XT_DOCONDBRANCH
-0005ff 0601 DEST(PFA_INTERPRET1)
-000600 0185 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-000601 3bca .dw XT_FETCHI
-000602 3829 .dw XT_EXECUTE
-000603 3f8a .dw XT_QSTACK
-000604 382e .dw XT_DOBRANCH
-000605 05f6 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000606 3ed1 .dw XT_2DROP
-000607 381f .dw XT_EXIT
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-000608 ff06 .dw $ff06
-000609 7464
-00060a 6e3a
-00060b 6d75 .db "dt:num"
-00060c 05ee .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-00060d 3851 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-00060e 0159 .dw XT_NOOP ; interpret
-00060f 0742 .dw XT_LITERAL ; compile
-000610 0742 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-000611 ff07 .dw $ff07
-000612 7464
-000613 643a
-000614 756e
-000615 006d .db "dt:dnum",0
-000616 0608 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000617 3851 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-000618 0159 .dw XT_NOOP ; interpret
-000619 3fd6 .dw XT_2LITERAL ; compile
-00061a 3fd6 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-00061b ff07 .dw $ff07
-00061c 6572
-00061d 3a63
-00061e 756e
-00061f 006d .db "rec:num",0
-000620 0611 .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-000621 3800 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-000622 04c0 .dw XT_NUMBER
-000623 3835 .dw XT_DOCONDBRANCH
-000624 062d DEST(PFA_REC_NONUMBER)
-000625 3fe5 .dw XT_ONE
-000626 3fde .dw XT_EQUAL
-000627 3835 .dw XT_DOCONDBRANCH
-000628 062b DEST(PFA_REC_INTNUM2)
-000629 060d .dw XT_DT_NUM
-00062a 381f .dw XT_EXIT
- PFA_REC_INTNUM2:
-00062b 0617 .dw XT_DT_DNUM
-00062c 381f .dw XT_EXIT
- PFA_REC_NONUMBER:
-00062d 065b .dw XT_DT_NULL
-00062e 381f .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00062f ff08 .dw $ff08
-000630 6572
-000631 3a63
-000632 6966
-000633 646e .db "rec:find"
-000634 061b .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000635 3800 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000636 06d0 .DW XT_FINDXT
-000637 38b0 .dw XT_DUP
-000638 3919 .dw XT_ZEROEQUAL
-000639 3835 .dw XT_DOCONDBRANCH
-00063a 063e DEST(PFA_REC_WORD_FOUND)
-00063b 38d8 .dw XT_DROP
-00063c 065b .dw XT_DT_NULL
-00063d 381f .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-00063e 0645 .dw XT_DT_XT
-
-00063f 381f .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-000640 ff05 .dw $ff05
-000641 7464
-000642 783a
-000643 0074 .db "dt:xt",0
-000644 062f .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000645 3851 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000646 0649 .dw XT_R_WORD_INTERPRET
-000647 064d .dw XT_R_WORD_COMPILE
-000648 3fd6 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-000649 3800 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-00064a 38d8 .dw XT_DROP ; the flags are in the way
-00064b 3829 .dw XT_EXECUTE
-00064c 381f .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-00064d 3800 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-00064e 3920 .dw XT_ZEROLESS
-00064f 3835 .dw XT_DOCONDBRANCH
-000650 0653 DEST(PFA_R_WORD_COMPILE1)
-000651 072c .dw XT_COMMA
-000652 381f .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-000653 3829 .dw XT_EXECUTE
-000654 381f .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000655 ff07 .dw $ff07
-000656 7464
-000657 6e3a
-000658 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-000659 006c .db "dt:null"
-00065a 0640 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-00065b 3851 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-00065c 065f .dw XT_FAIL ; interpret
-00065d 065f .dw XT_FAIL ; compile
-00065e 065f .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00065f 3800 .dw DO_COLON
- PFA_FAIL:
- .endif
-000660 383c .dw XT_DOLITERAL
-000661 fff3 .dw -13
-000662 3d85 .dw XT_THROW
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-000663 ff0f .dw $ff0f
-000664 6573
-000665 7261
-000666 6863
-000667 772d
-000668 726f
-000669 6c64
-00066a 7369
-00066b 0074 .db "search-wordlist",0
-00066c 0655 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00066d 3800 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-00066e 38fe .dw XT_TO_R
-00066f 3953 .dw XT_ZERO
-000670 383c .dw XT_DOLITERAL
-000671 0682 .dw XT_ISWORD
-000672 38f5 .dw XT_R_FROM
-000673 069f .dw XT_TRAVERSEWORDLIST
-000674 38b0 .dw XT_DUP
-000675 3919 .dw XT_ZEROEQUAL
-000676 3835 .dw XT_DOCONDBRANCH
-000677 067c DEST(PFA_SEARCH_WORDLIST1)
-000678 3ed1 .dw XT_2DROP
-000679 38d8 .dw XT_DROP
-00067a 3953 .dw XT_ZERO
-00067b 381f .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-00067c 38b0 .dw XT_DUP
-00067d 06c6 .dw XT_NFA2CFA
- ; .. and get the header flag
-00067e 38c3 .dw XT_SWAP
-00067f 0134 .dw XT_NAME2FLAGS
-000680 0122 .dw XT_IMMEDIATEQ
-000681 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-000682 3800 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-000683 38fe .dw XT_TO_R
-000684 38d8 .dw XT_DROP
-000685 3ec8 .dw XT_2DUP
-000686 3907 .dw XT_R_FETCH ; -- addr len addr len nt
-000687 06ba .dw XT_NAME2STRING
-000688 018e .dw XT_ICOMPARE ; (-- addr len f )
-000689 3835 .dw XT_DOCONDBRANCH
-00068a 0690 DEST(PFA_ISWORD3)
- ; not now
-00068b 38f5 .dw XT_R_FROM
-00068c 38d8 .dw XT_DROP
-00068d 3953 .dw XT_ZERO
-00068e 394a .dw XT_TRUE ; maybe next word
-00068f 381f .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-000690 3ed1 .dw XT_2DROP
-000691 38f5 .dw XT_R_FROM
-000692 3953 .dw XT_ZERO ; finish traverse-wordlist
-000693 381f .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-000694 ff11 .dw $ff11
-000695 7274
-000696 7661
-000697 7265
-000698 6573
-000699 772d
-00069a 726f
-00069b 6c64
-00069c 7369
-00069d 0074 .db "traverse-wordlist",0
-00069e 0663 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-00069f 3800 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-0006a0 3b5e .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-0006a1 38b0 .dw XT_DUP ; ( -- xt nt nt )
-0006a2 3835 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-0006a3 06b0 DEST(PFA_TRAVERSEWORDLIST2)
-0006a4 3ec8 .dw XT_2DUP
-0006a5 3b1d .dw XT_2TO_R
-0006a6 38c3 .dw XT_SWAP
-0006a7 3829 .dw XT_EXECUTE
-0006a8 3b2c .dw XT_2R_FROM
-0006a9 38e0 .dw XT_ROT
-0006aa 3835 .dw XT_DOCONDBRANCH
-0006ab 06b0 DEST(PFA_TRAVERSEWORDLIST2)
-0006ac 09db .dw XT_NFA2LFA
-0006ad 3bca .dw XT_FETCHI
-0006ae 382e .dw XT_DOBRANCH ; ( -- addr )
-0006af 06a1 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-0006b0 3ed1 .dw XT_2DROP
-0006b1 381f .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-0006b2 ff0b .dw $ff0b
-0006b3 616e
-0006b4 656d
-0006b5 733e
-0006b6 7274
-0006b7 6e69
-0006b8 0067 .db "name>string",0
-0006b9 0694 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-0006ba 3800 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-0006bb 03f4 .dw XT_ICOUNT ; ( -- addr n )
-0006bc 383c .dw XT_DOLITERAL
-0006bd 00ff .dw 255
-0006be 3a12 .dw XT_AND ; mask immediate bit
-0006bf 381f .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-0006c0 ff07 .dw $ff07
-0006c1 666e
-0006c2 3e61
-0006c3 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-0006c4 0061 .db "nfa>cfa"
-0006c5 06b2 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-0006c6 3800 .dw DO_COLON
- PFA_NFA2CFA:
-0006c7 09db .dw XT_NFA2LFA ; skip to link field
-0006c8 3a2e .dw XT_1PLUS ; next is the execution token
-0006c9 381f .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-0006ca ff07 .dw $ff07
-0006cb 6966
-0006cc 646e
-0006cd 782d
-0006ce 0074 .db "find-xt",0
-0006cf 06c0 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-0006d0 3800 .dw DO_COLON
- PFA_FINDXT:
- .endif
-0006d1 383c .dw XT_DOLITERAL
-0006d2 06dc .dw XT_FINDXTA
-0006d3 383c .dw XT_DOLITERAL
-0006d4 004a .dw CFG_ORDERLISTLEN
-0006d5 096c .dw XT_MAPSTACK
-0006d6 3919 .dw XT_ZEROEQUAL
-0006d7 3835 .dw XT_DOCONDBRANCH
-0006d8 06db DEST(PFA_FINDXT1)
-0006d9 3ed1 .dw XT_2DROP
-0006da 3953 .dw XT_ZERO
- PFA_FINDXT1:
-0006db 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-0006dc 3800 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-0006dd 38fe .dw XT_TO_R
-0006de 3ec8 .dw XT_2DUP
-0006df 38f5 .dw XT_R_FROM
-0006e0 066d .dw XT_SEARCH_WORDLIST
-0006e1 38b0 .dw XT_DUP
-0006e2 3835 .dw XT_DOCONDBRANCH
-0006e3 06e9 DEST(PFA_FINDXTA1)
-0006e4 38fe .dw XT_TO_R
-0006e5 38ef .dw XT_NIP
-0006e6 38ef .dw XT_NIP
-0006e7 38f5 .dw XT_R_FROM
-0006e8 394a .dw XT_TRUE
- PFA_FINDXTA1:
-0006e9 381f .dw XT_EXIT
-
- .include "dict/compiler1.inc"
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-0006ea ff06 .dw $ff06
-0006eb 656e
-0006ec 6577
-0006ed 7473 .db "newest"
-0006ee 06ca .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-0006ef 3847 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-0006f0 018a .dw ram_newest
-
- .dseg
-00018a ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-0006f1 ff06 .dw $ff06
-0006f2 616c
-0006f3 6574
-0006f4 7473 .db "latest"
-0006f5 06ea .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-0006f6 3847 .dw PFA_DOVARIABLE
- PFA_LATEST:
-0006f7 018e .dw ram_latest
-
- .dseg
-00018e ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-0006f8 ff08 .dw $ff08
-0006f9 6328
-0006fa 6572
-0006fb 7461
-0006fc 2965 .db "(create)"
-0006fd 06f1 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-0006fe 3800 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-0006ff 0580
-000700 0855 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-000701 38b0
-000702 06ef
-000703 3c8f
-000704 3880 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000705 083a
-000706 06ef
-000707 3880 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-000708 381f .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-000709 0001 .dw $0001
-00070a 005c .db $5c,0
-00070b 06f8 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-00070c 3800 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-00070d 0567 .dw XT_SOURCE
-00070e 38ef .dw XT_NIP
-00070f 3ee1 .dw XT_TO_IN
-000710 3880 .dw XT_STORE
-000711 381f .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-000712 0001 .dw $0001
-000713 0028 .db "(" ,0
-000714 0709 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000715 3800 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000716 383c .dw XT_DOLITERAL
-000717 0029 .dw ')'
-000718 0553 .dw XT_PARSE
-000719 3ed1 .dw XT_2DROP
-00071a 381f .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-00071b ff07 .dw $ff07
-00071c 6f63
-00071d 706d
-00071e 6c69
-00071f 0065 .db "compile",0
-000720 0712 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-000721 3800 .dw DO_COLON
- PFA_COMPILE:
- .endif
-000722 38f5 .dw XT_R_FROM
-000723 38b0 .dw XT_DUP
-000724 0185 .dw XT_ICELLPLUS
-000725 38fe .dw XT_TO_R
-000726 3bca .dw XT_FETCHI
-000727 072c .dw XT_COMMA
-000728 381f .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-000729 ff01 .dw $ff01
-00072a 002c .db ',',0 ; ,
-00072b 071b .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-00072c 3800 .dw DO_COLON
- PFA_COMMA:
-00072d 3f11 .dw XT_DP
-00072e 3b72 .dw XT_STOREI
-00072f 3f11 .dw XT_DP
-000730 3a2e .dw XT_1PLUS
-000731 0173 .dw XT_DOTO
-000732 3f12 .dw PFA_DP
-000733 381f .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-000734 0003 .dw $0003
-000735 275b
-000736 005d .db "[']",0
-000737 0729 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-000738 3800 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-000739 040d .dw XT_TICK
-00073a 0742 .dw XT_LITERAL
-00073b 381f .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-00073c 0007 .dw $0007
-00073d 696c
-00073e 6574
-00073f 6172
-000740 006c .db "literal",0
-000741 0734 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-000742 3800 .dw DO_COLON
- PFA_LITERAL:
- .endif
-000743 0721 .DW XT_COMPILE
-000744 383c .DW XT_DOLITERAL
-000745 072c .DW XT_COMMA
-000746 381f .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-000747 0008 .dw $0008
-000748 6c73
-000749 7469
-00074a 7265
-00074b 6c61 .db "sliteral"
-00074c 073c .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-00074d 3800 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-00074e 0721 .dw XT_COMPILE
-00074f 0395 .dw XT_DOSLITERAL ; ( -- addr n)
-000750 03a3 .dw XT_SCOMMA
-000751 381f .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-000752 3800 .dw DO_COLON
- PFA_GMARK:
-000753 3f11 .dw XT_DP
-000754 0721 .dw XT_COMPILE
-000755 ffff .dw -1 ; ffff does not erase flash
-000756 381f .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000757 3800 .dw DO_COLON
- PFA_GRESOLVE:
-000758 3f8a .dw XT_QSTACK
-000759 3f11 .dw XT_DP
-00075a 38c3 .dw XT_SWAP
-00075b 3b72 .dw XT_STOREI
-00075c 381f .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-00075d 3800 .dw DO_COLON
- PFA_LMARK:
-00075e 3f11 .dw XT_DP
-00075f 381f .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-000760 3800 .dw DO_COLON
- PFA_LRESOLVE:
-000761 3f8a .dw XT_QSTACK
-000762 072c .dw XT_COMMA
-000763 381f .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-000764 0005 .dw $0005
-000765 6861
-000766 6165
-000767 0064 .db "ahead",0
-000768 0747 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-000769 3800 .dw DO_COLON
- PFA_AHEAD:
- .endif
-00076a 0721 .dw XT_COMPILE
-00076b 382e .dw XT_DOBRANCH
-00076c 0752 .dw XT_GMARK
-00076d 381f .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-00076e 0002 .dw $0002
-00076f 6669 .db "if"
-000770 0764 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-000771 3800 .dw DO_COLON
- PFA_IF:
- .endif
-000772 0721 .dw XT_COMPILE
-000773 3835 .dw XT_DOCONDBRANCH
-000774 0752 .dw XT_GMARK
-000775 381f .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-000776 0004 .dw $0004
-000777 6c65
-000778 6573 .db "else"
-000779 076e .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-00077a 3800 .dw DO_COLON
- PFA_ELSE:
- .endif
-00077b 0721 .dw XT_COMPILE
-00077c 382e .dw XT_DOBRANCH
-00077d 0752 .dw XT_GMARK
-00077e 38c3 .dw XT_SWAP
-00077f 0757 .dw XT_GRESOLVE
-000780 381f .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-000781 0004 .dw $0004
-000782 6874
-000783 6e65 .db "then"
-000784 0776 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-000785 3800 .dw DO_COLON
- PFA_THEN:
- .endif
-000786 0757 .dw XT_GRESOLVE
-000787 381f .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-000788 0005 .dw $0005
-000789 6562
-00078a 6967
-00078b 006e .db "begin",0
-00078c 0781 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-00078d 3800 .dw DO_COLON
- PFA_BEGIN:
- .endif
-00078e 075d .dw XT_LMARK
-00078f 381f .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-000790 0005 .dw $0005
-000791 6877
-000792 6c69
-000793 0065 .db "while",0
-000794 0788 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-000795 3800 .dw DO_COLON
- PFA_WHILE:
- .endif
-000796 0771 .dw XT_IF
-000797 38c3 .dw XT_SWAP
-000798 381f .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-000799 0006 .dw $0006
-00079a 6572
-00079b 6570
-00079c 7461 .db "repeat"
-00079d 0790 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-00079e 3800 .dw DO_COLON
- PFA_REPEAT:
- .endif
-00079f 07b2 .dw XT_AGAIN
-0007a0 0785 .dw XT_THEN
-0007a1 381f .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-0007a2 0005 .dw $0005
-0007a3 6e75
-0007a4 6974
-0007a5 006c .db "until",0
-0007a6 0799 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-0007a7 3800 .dw DO_COLON
- PFA_UNTIL:
- .endif
-0007a8 383c .dw XT_DOLITERAL
-0007a9 3835 .dw XT_DOCONDBRANCH
-0007aa 072c .dw XT_COMMA
-
-0007ab 0760 .dw XT_LRESOLVE
-0007ac 381f .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-0007ad 0005 .dw $0005
-0007ae 6761
-0007af 6961
-0007b0 006e .db "again",0
-0007b1 07a2 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-0007b2 3800 .dw DO_COLON
- PFA_AGAIN:
- .endif
-0007b3 0721 .dw XT_COMPILE
-0007b4 382e .dw XT_DOBRANCH
-0007b5 0760 .dw XT_LRESOLVE
-0007b6 381f .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-0007b7 0002 .dw $0002
-0007b8 6f64 .db "do"
-0007b9 07ad .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-0007ba 3800 .dw DO_COLON
- PFA_DO:
-
- .endif
-0007bb 0721 .dw XT_COMPILE
-0007bc 3a9a .dw XT_DODO
-0007bd 075d .dw XT_LMARK
-0007be 3953 .dw XT_ZERO
-0007bf 0815 .dw XT_TO_L
-0007c0 381f .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-0007c1 0004 .dw $0004
-0007c2 6f6c
-0007c3 706f .db "loop"
-0007c4 07b7 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-0007c5 3800 .dw DO_COLON
- PFA_LOOP:
- .endif
-0007c6 0721 .dw XT_COMPILE
-0007c7 3ac8 .dw XT_DOLOOP
-0007c8 07fc .dw XT_ENDLOOP
-0007c9 381f .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-0007ca 0005 .dw $0005
-0007cb 6c2b
-0007cc 6f6f
-0007cd 0070 .db "+loop",0
-0007ce 07c1 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-0007cf 3800 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-0007d0 0721 .dw XT_COMPILE
-0007d1 3ab9 .dw XT_DOPLUSLOOP
-0007d2 07fc .dw XT_ENDLOOP
-0007d3 381f .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-0007d4 0005 .dw $0005
-0007d5 656c
-0007d6 7661
-0007d7 0065 .db "leave",0
-0007d8 07ca .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-0007d9 3800 .dw DO_COLON
- PFA_LEAVE:
- .endif
-0007da 0721
-0007db 3ad3 .DW XT_COMPILE,XT_UNLOOP
-0007dc 0769
-0007dd 0815
-0007de 381f .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-0007df 0003 .dw $0003
-0007e0 643f
-0007e1 006f .db "?do",0
-0007e2 07d4 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-0007e3 3800 .dw DO_COLON
- PFA_QDO:
- .endif
-0007e4 0721 .dw XT_COMPILE
-0007e5 07eb .dw XT_QDOCHECK
-0007e6 0771 .dw XT_IF
-0007e7 07ba .dw XT_DO
-0007e8 38c3 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-0007e9 0815 .dw XT_TO_L ; then follows at the end.
-0007ea 381f .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-0007eb 3800 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-0007ec 3ec8 .dw XT_2DUP
-0007ed 3fde .dw XT_EQUAL
-0007ee 38b0 .dw XT_DUP
-0007ef 38fe .dw XT_TO_R
-0007f0 3835 .dw XT_DOCONDBRANCH
-0007f1 07f3 DEST(PFA_QDOCHECK1)
-0007f2 3ed1 .dw XT_2DROP
- PFA_QDOCHECK1:
-0007f3 38f5 .dw XT_R_FROM
-0007f4 39fc .dw XT_INVERT
-0007f5 381f .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-0007f6 ff07 .dw $ff07
-0007f7 6e65
-0007f8 6c64
-0007f9 6f6f
-0007fa 0070 .db "endloop",0
-0007fb 07df .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-0007fc 3800 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-0007fd 0760 .DW XT_LRESOLVE
-0007fe 0809
-0007ff 38b8
-000800 3835 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-000801 0805 DEST(LOOP2)
-000802 0785 .DW XT_THEN
-000803 382e .dw XT_DOBRANCH
-000804 07fe DEST(LOOP1)
-000805 381f LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000806 ff02 .dw $ff02
-000807 3e6c .db "l>"
-000808 07f6 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-000809 3800 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-00080a 0828 .dw XT_LP
-00080b 3878 .dw XT_FETCH
-00080c 3878 .dw XT_FETCH
-00080d 383c .dw XT_DOLITERAL
-00080e fffe .dw -2
-00080f 0828 .dw XT_LP
-000810 3a64 .dw XT_PLUSSTORE
-000811 381f .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-000812 ff02 .dw $ff02
-000813 6c3e .db ">l"
-000814 0806 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000815 3800 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000816 3fea .dw XT_TWO
-000817 0828 .dw XT_LP
-000818 3a64 .dw XT_PLUSSTORE
-000819 0828 .dw XT_LP
-00081a 3878 .dw XT_FETCH
-00081b 3880 .dw XT_STORE
-00081c 381f .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-00081d ff03 .dw $ff03
-00081e 706c
-00081f 0030 .db "lp0",0
-000820 0812 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-000821 386e .dw PFA_DOVALUE1
- PFA_LP0:
-000822 0040 .dw CFG_LP0
-000823 3d9f .dw XT_EDEFERFETCH
-000824 3da9 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-000825 ff02 .dw $ff02
-000826 706c .db "lp"
-000827 081d .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-000828 3847 .dw PFA_DOVARIABLE
- PFA_LP:
-000829 0190 .dw ram_lp
-
- .dseg
-000190 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-00082a ff06 .dw $ff06
-00082b 7263
-00082c 6165
-00082d 6574 .db "create"
-00082e 0825 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-00082f 3800 .dw DO_COLON
- PFA_CREATE:
- .endif
-000830 06fe .dw XT_DOCREATE
-000831 085e .dw XT_REVEAL
-000832 0721 .dw XT_COMPILE
-000833 3851 .dw PFA_DOCONSTANT
-000834 381f .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-000835 ff06 .dw $ff06
-000836 6568
-000837 6461
-000838 7265 .db "header"
-000839 082a .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-00083a 3800 .dw DO_COLON
- PFA_HEADER:
-00083b 3f11 .dw XT_DP ; the new Name Field
-00083c 38fe .dw XT_TO_R
-00083d 38fe .dw XT_TO_R ; ( R: NFA WID )
-00083e 38b0 .dw XT_DUP
-00083f 3927 .dw XT_GREATERZERO
-000840 3835 .dw XT_DOCONDBRANCH
-000841 084c .dw PFA_HEADER1
-000842 38b0 .dw XT_DUP
-000843 383c .dw XT_DOLITERAL
-000844 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-000845 3a1b .dw XT_OR
-000846 03a7 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-000847 38f5 .dw XT_R_FROM
-000848 3b5e .dw XT_FETCHE
-000849 072c .dw XT_COMMA
-00084a 38f5 .dw XT_R_FROM
-00084b 381f .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-00084c 383c .dw XT_DOLITERAL
-00084d fff0 .dw -16
-00084e 3d85 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-00084f ff07 .dw $ff07
-000850 6c77
-000851 6373
-000852 706f
-000853 0065 .db "wlscope",0
-000854 0835 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000855 3dfe .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000856 003c .dw CFG_WLSCOPE
-000857 3d9f .dw XT_EDEFERFETCH
-000858 3da9 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000859 ff06 .dw $ff06
-00085a 6572
-00085b 6576
-00085c 6c61 .db "reveal"
-00085d 084f .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-00085e 3800 .dw DO_COLON
- PFA_REVEAL:
- .endif
-00085f 06ef
-000860 3c8f
-000861 3878 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-000862 38b8
-000863 3835 .DW XT_QDUP,XT_DOCONDBRANCH
-000864 0869 DEST(REVEAL1)
-000865 06ef
-000866 3878
-000867 38c3
-000868 3b3a .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-000869 381f .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-00086a 0005 .dw $0005
-00086b 6f64
-00086c 7365
-00086d 003e .db "does>",0
-00086e 0859 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-00086f 3800 .dw DO_COLON
- PFA_DOES:
-000870 0721 .dw XT_COMPILE
-000871 0882 .dw XT_DODOES
-000872 0721 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-000873 940e .dw $940e ; the address of this compiled
-000874 0721 .dw XT_COMPILE ; code will replace the XT of the
-000875 0877 .dw DO_DODOES ; word that CREATE created
-000876 381f .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-000877 939a
-000878 938a savetos
-000879 01cb movw tosl, wl
-00087a 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-00087b 917f pop wh
-00087c 916f pop wl
-
-00087d 93bf push XH
-00087e 93af push XL
-00087f 01db movw XL, wl
-000880 940c 3804 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-000882 3800 .dw DO_COLON
- PFA_DODOES:
-000883 38f5 .dw XT_R_FROM
-000884 06ef .dw XT_NEWEST
-000885 3c8f .dw XT_CELLPLUS
-000886 3878 .dw XT_FETCH
-000887 3b5e .dw XT_FETCHE
-000888 06c6 .dw XT_NFA2CFA
-000889 3b72 .dw XT_STOREI
-00088a 381f .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-00088b ff01 .dw $ff01
-00088c 003a .db ":",0
-00088d 086a .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-00088e 3800 .dw DO_COLON
- PFA_COLON:
- .endif
-00088f 06fe .dw XT_DOCREATE
-000890 0899 .dw XT_COLONNONAME
-000891 38d8 .dw XT_DROP
-000892 381f .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-000893 ff07 .dw $ff07
-000894 6e3a
-000895 6e6f
-000896 6d61
-000897 0065 .db ":noname",0
-000898 088b .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-000899 3800 .dw DO_COLON
- PFA_COLONNONAME:
-00089a 3f11 .dw XT_DP
-00089b 38b0 .dw XT_DUP
-00089c 06f6 .dw XT_LATEST
-00089d 3880 .dw XT_STORE
-
-00089e 0721 .dw XT_COMPILE
-00089f 3800 .dw DO_COLON
-
-0008a0 08ae .dw XT_RBRACKET
-0008a1 381f .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-0008a2 0001 .dw $0001
-0008a3 003b .db $3b,0
-0008a4 0893 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-0008a5 3800 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-0008a6 0721 .dw XT_COMPILE
-0008a7 381f .dw XT_EXIT
-0008a8 08b6 .dw XT_LBRACKET
-0008a9 085e .dw XT_REVEAL
-0008aa 381f .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-0008ab ff01 .dw $ff01
-0008ac 005d .db "]",0
-0008ad 08a2 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-0008ae 3800 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-0008af 3fe5 .dw XT_ONE
-0008b0 3eb6 .dw XT_STATE
-0008b1 3880 .dw XT_STORE
-0008b2 381f .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-0008b3 0001 .dw $0001
-0008b4 005b .db "[",0
-0008b5 08ab .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-0008b6 3800 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-0008b7 3953 .dw XT_ZERO
-0008b8 3eb6 .dw XT_STATE
-0008b9 3880 .dw XT_STORE
-0008ba 381f .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-0008bb ff08 .dw $ff08
-0008bc 6176
-0008bd 6972
-0008be 6261
-0008bf 656c .db "variable"
-0008c0 08b3 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-0008c1 3800 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-0008c2 3f22 .dw XT_HERE
-0008c3 08cd .dw XT_CONSTANT
-0008c4 3fea .dw XT_TWO
-0008c5 3f2b .dw XT_ALLOT
-0008c6 381f .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-0008c7 ff08 .dw $ff08
-0008c8 6f63
-0008c9 736e
-0008ca 6174
-0008cb 746e .db "constant"
-0008cc 08bb .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-0008cd 3800 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-0008ce 06fe .dw XT_DOCREATE
-0008cf 085e .dw XT_REVEAL
-0008d0 0721 .dw XT_COMPILE
-0008d1 3847 .dw PFA_DOVARIABLE
-0008d2 072c .dw XT_COMMA
-0008d3 381f .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-0008d4 ff04 .dw $ff04
-0008d5 7375
-0008d6 7265 .db "user"
-0008d7 08c7 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-0008d8 3800 .dw DO_COLON
- PFA_USER:
-0008d9 06fe .dw XT_DOCREATE
-0008da 085e .dw XT_REVEAL
-
-0008db 0721 .dw XT_COMPILE
-0008dc 3857 .dw PFA_DOUSER
-0008dd 072c .dw XT_COMMA
-0008de 381f .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-0008df 0007 .dw $0007
-0008e0 6572
-0008e1 7563
-0008e2 7372
-0008e3 0065 .db "recurse",0
-0008e4 08d4 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-0008e5 3800 .dw DO_COLON
- PFA_RECURSE:
- .endif
-0008e6 06f6 .dw XT_LATEST
-0008e7 3878 .dw XT_FETCH
-0008e8 072c .dw XT_COMMA
-0008e9 381f .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-0008ea ff09 .dw $ff09
-0008eb 6d69
-0008ec 656d
-0008ed 6964
-0008ee 7461
-0008ef 0065 .db "immediate",0
-0008f0 08df .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-0008f1 3800 .dw DO_COLON
- PFA_IMMEDIATE:
-0008f2 0993 .dw XT_GET_CURRENT
-0008f3 3b5e .dw XT_FETCHE
-0008f4 38b0 .dw XT_DUP
-0008f5 3bca .dw XT_FETCHI
-0008f6 383c .dw XT_DOLITERAL
-0008f7 7fff .dw $7fff
-0008f8 3a12 .dw XT_AND
-0008f9 38c3 .dw XT_SWAP
-0008fa 3b72 .dw XT_STOREI
-0008fb 381f .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-0008fc 0006 .dw $0006
-0008fd 635b
-0008fe 6168
-0008ff 5d72 .db "[char]"
-000900 08ea .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-000901 3800 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-000902 0721 .dw XT_COMPILE
-000903 383c .dw XT_DOLITERAL
-000904 04b6 .dw XT_CHAR
-000905 072c .dw XT_COMMA
-000906 381f .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-000907 0006 .dw $0006
-000908 6261
-000909 726f
-00090a 2274 .db "abort",'"'
-00090b 08fc .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-00090c 3800 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-00090d 3e89 .dw XT_SQUOTE
-00090e 0721 .dw XT_COMPILE
-00090f 091e .dw XT_QABORT
-000910 381f .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-000911 ff05 .dw $ff05
-000912 6261
-000913 726f
-000914 0074 .db "abort",0
-000915 0907 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000916 3800 .dw DO_COLON
- PFA_ABORT:
- .endif
-000917 394a .dw XT_TRUE
-000918 3d85 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-000919 ff06 .dw $ff06
-00091a 613f
-00091b 6f62
-00091c 7472 .db "?abort"
-00091d 0911 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-00091e 3800 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-00091f 38e0
-000920 3835 .DW XT_ROT,XT_DOCONDBRANCH
-000921 0924 DEST(QABO1)
-000922 03c8
-000923 0916 .DW XT_ITYPE,XT_ABORT
-000924 3ed1
-000925 381f QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000926 ff09 .dw $ff09
-000927 6567
-000928 2d74
-000929 7473
-00092a 6361
-00092b 006b .db "get-stack",0
-00092c 0919 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-00092d 3800 .dw DO_COLON
- .endif
-00092e 38b0 .dw XT_DUP
-00092f 3c8f .dw XT_CELLPLUS
-000930 38c3 .dw XT_SWAP
-000931 3b5e .dw XT_FETCHE
-000932 38b0 .dw XT_DUP
-000933 38fe .dw XT_TO_R
-000934 3953 .dw XT_ZERO
-000935 38c3 .dw XT_SWAP ; go from bigger to smaller addresses
-000936 07eb .dw XT_QDOCHECK
-000937 3835 .dw XT_DOCONDBRANCH
-000938 0944 DEST(PFA_N_FETCH_E2)
-000939 3a9a .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-00093a 3aab .dw XT_I
-00093b 3a34 .dw XT_1MINUS
-00093c 3ec3 .dw XT_CELLS ; ( -- ee-addr i*2 )
-00093d 38ce .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-00093e 399c .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-00093f 3b5e .dw XT_FETCHE ;( -- ee-addr item_i )
-000940 38c3 .dw XT_SWAP ;( -- item_i ee-addr )
-000941 394a .dw XT_TRUE ; shortcut for -1
-000942 3ab9 .dw XT_DOPLUSLOOP
-000943 093a DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-000944 3ed1 .dw XT_2DROP
-000945 38f5 .dw XT_R_FROM
-000946 381f .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-000947 ff09 .dw $ff09
-000948 6573
-000949 2d74
-00094a 7473
-00094b 6361
-00094c 006b .db "set-stack",0
-00094d 0926 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-00094e 3800 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-00094f 38ce .dw XT_OVER
-000950 3920 .dw XT_ZEROLESS
-000951 3835 .dw XT_DOCONDBRANCH
-000952 0956 DEST(PFA_SET_STACK0)
-000953 383c .dw XT_DOLITERAL
-000954 fffc .dw -4
-000955 3d85 .dw XT_THROW
- PFA_SET_STACK0:
-000956 3ec8 .dw XT_2DUP
-000957 3b3a .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000958 38c3 .dw XT_SWAP
-000959 3953 .dw XT_ZERO
-00095a 07eb .dw XT_QDOCHECK
-00095b 3835 .dw XT_DOCONDBRANCH
-00095c 0963 DEST(PFA_SET_STACK2)
-00095d 3a9a .dw XT_DODO
- PFA_SET_STACK1:
-00095e 3c8f .dw XT_CELLPLUS ; ( -- i_x e-addr )
-00095f 3ed9 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-000960 3b3a .dw XT_STOREE
-000961 3ac8 .dw XT_DOLOOP
-000962 095e DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-000963 38d8 .dw XT_DROP
-000964 381f .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-000965 ff09 .dw $ff09
-000966 616d
-000967 2d70
-000968 7473
-000969 6361
-00096a 006b .db "map-stack",0
-00096b 0947 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-00096c 3800 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-00096d 38b0 .dw XT_DUP
-00096e 3c8f .dw XT_CELLPLUS
-00096f 38c3 .dw XT_SWAP
-000970 3b5e .dw XT_FETCHE
-000971 3ec3 .dw XT_CELLS
-000972 3f98 .dw XT_BOUNDS
-000973 07eb .dw XT_QDOCHECK
-000974 3835 .dw XT_DOCONDBRANCH
-000975 0988 DEST(PFA_MAPSTACK3)
-000976 3a9a .dw XT_DODO
- PFA_MAPSTACK1:
-000977 3aab .dw XT_I
-000978 3b5e .dw XT_FETCHE ; -- i*x XT id
-000979 38c3 .dw XT_SWAP
-00097a 38fe .dw XT_TO_R
-00097b 3907 .dw XT_R_FETCH
-00097c 3829 .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-00097d 38b8 .dw XT_QDUP
-00097e 3835 .dw XT_DOCONDBRANCH
-00097f 0984 DEST(PFA_MAPSTACK2)
-000980 38f5 .dw XT_R_FROM
-000981 38d8 .dw XT_DROP
-000982 3ad3 .dw XT_UNLOOP
-000983 381f .dw XT_EXIT
- PFA_MAPSTACK2:
-000984 38f5 .dw XT_R_FROM
-000985 3fea .dw XT_TWO
-000986 3ab9 .dw XT_DOPLUSLOOP
-000987 0977 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-000988 38d8 .dw XT_DROP
-000989 3953 .dw XT_ZERO
-00098a 381f .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-00098b ff0b .dw $ff0b
-00098c 6567
-00098d 2d74
-00098e 7563
-00098f 7272
-000990 6e65
-000991 0074 .db "get-current",0
-000992 0965 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-000993 3800 .dw DO_COLON
- PFA_GET_CURRENT:
-000994 383c .dw XT_DOLITERAL
-000995 0046 .dw CFG_CURRENT
-000996 3b5e .dw XT_FETCHE
-000997 381f .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-000998 ff09 .dw $ff09
-000999 6567
-00099a 2d74
-00099b 726f
-00099c 6564
-00099d 0072 .db "get-order",0
-00099e 098b .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-00099f 3800 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-0009a0 383c .dw XT_DOLITERAL
-0009a1 004a .dw CFG_ORDERLISTLEN
-0009a2 092d .dw XT_GET_STACK
-0009a3 381f .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-0009a4 ff09 .dw $ff09
-0009a5 6663
-0009a6 2d67
-0009a7 726f
-0009a8 6564
-0009a9 0072 .db "cfg-order",0
-0009aa 0998 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-0009ab 3847 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-0009ac 004a .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-0009ad ff07 .dw $ff07
-0009ae 6f63
-0009af 706d
-0009b0 7261
-0009b1 0065 .db "compare",0
-0009b2 09a4 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-0009b3 09b4 .dw PFA_COMPARE
- PFA_COMPARE:
-0009b4 93bf push xh
-0009b5 93af push xl
-0009b6 018c movw temp0, tosl
-0009b7 9189
-0009b8 9199 loadtos
-0009b9 01dc movw xl, tosl
-0009ba 9189
-0009bb 9199 loadtos
-0009bc 019c movw temp2, tosl
-0009bd 9189
-0009be 9199 loadtos
-0009bf 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-0009c0 90ed ld temp4, X+
-0009c1 90f1 ld temp5, Z+
-0009c2 14ef cp temp4, temp5
-0009c3 f451 brne PFA_COMPARE_NOTEQUAL
-0009c4 950a dec temp0
-0009c5 f019 breq PFA_COMPARE_ENDREACHED2
-0009c6 952a dec temp2
-0009c7 f7c1 brne PFA_COMPARE_LOOP
-0009c8 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-0009c9 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-0009ca 2b02 or temp0, temp2
-0009cb f411 brne PFA_COMPARE_CHECKLASTCHAR
-0009cc 2788 clr tosl
-0009cd c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-0009ce ef8f ser tosl
-0009cf c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-0009d0 2f98 mov tosh, tosl
-0009d1 91af pop xl
-0009d2 91bf pop xh
-0009d3 940c 3804 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-0009d5 ff07 .dw $ff07
-0009d6 666e
-0009d7 3e61
-0009d8 666c
-0009d9 0061 .db "nfa>lfa",0
-0009da 09ad .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-0009db 3800 .dw DO_COLON
- PFA_NFA2LFA:
-0009dc 06ba .dw XT_NAME2STRING
-0009dd 3a2e .dw XT_1PLUS
-0009de 3a03 .dw XT_2SLASH
-0009df 399c .dw XT_PLUS
-0009e0 381f .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
-
- .include "dict/compiler2.inc" ; additional words for the compiler
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-0009e1 ff0b .dw $ff0b
-0009e2 6573
-0009e3 2d74
-0009e4 7563
-0009e5 7272
-0009e6 6e65
-0009e7 0074 .db "set-current",0
-0009e8 09d5 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-0009e9 3800 .dw DO_COLON
- PFA_SET_CURRENT:
-0009ea 383c .dw XT_DOLITERAL
-0009eb 0046 .dw CFG_CURRENT
-0009ec 3b3a .dw XT_STOREE
-0009ed 381f .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-0009ee ff08 .dw $ff08
-0009ef 6f77
-0009f0 6472
-0009f1 696c
-0009f2 7473 .db "wordlist"
-0009f3 09e1 .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-0009f4 3800 .dw DO_COLON
- PFA_WORDLIST:
-0009f5 3f1a .dw XT_EHERE
-0009f6 3953 .dw XT_ZERO
-0009f7 38ce .dw XT_OVER
-0009f8 3b3a .dw XT_STOREE
-0009f9 38b0 .dw XT_DUP
-0009fa 3c8f .dw XT_CELLPLUS
-0009fb 0173 .dw XT_DOTO
-0009fc 3f1b .dw PFA_EHERE
-0009fd 381f .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-0009fe ff0e .dw $ff0e
-0009ff 6f66
-000a00 7472
-000a01 2d68
-000a02 6f77
-000a03 6472
-000a04 696c
-000a05 7473 .db "forth-wordlist"
-000a06 09ee .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000a07 3847 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000a08 0048 .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000a09 ff09 .dw $ff09
-000a0a 6573
-000a0b 2d74
-000a0c 726f
-000a0d 6564
-000a0e 0072 .db "set-order",0
-000a0f 09fe .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000a10 3800 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000a11 383c .dw XT_DOLITERAL
-000a12 004a .dw CFG_ORDERLISTLEN
-000a13 094e .dw XT_SET_STACK
-000a14 381f .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000a15 ff0f .dw $ff0f
-000a16 6573
-000a17 2d74
-000a18 6572
-000a19 6f63
-000a1a 6e67
-000a1b 7a69
-000a1c 7265
-000a1d 0073 .db "set-recognizers",0
-000a1e 0a09 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000a1f 3800 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000a20 383c .dw XT_DOLITERAL
-000a21 005c .dw CFG_RECOGNIZERLISTLEN
-000a22 094e .dw XT_SET_STACK
-000a23 381f .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000a24 ff0f .dw $ff0f
-000a25 6567
-000a26 2d74
-000a27 6572
-000a28 6f63
-000a29 6e67
-000a2a 7a69
-000a2b 7265
-000a2c 0073 .db "get-recognizers",0
-000a2d 0a15 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000a2e 3800 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000a2f 383c .dw XT_DOLITERAL
-000a30 005c .dw CFG_RECOGNIZERLISTLEN
-000a31 092d .dw XT_GET_STACK
-000a32 381f .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000a33 ff04 .dw $ff04
-000a34 6f63
-000a35 6564 .db "code"
-000a36 0a24 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000a37 3800 .dw DO_COLON
- PFA_CODE:
-000a38 06fe .dw XT_DOCREATE
-000a39 085e .dw XT_REVEAL
-000a3a 3f11 .dw XT_DP
-000a3b 0185 .dw XT_ICELLPLUS
-000a3c 072c .dw XT_COMMA
-000a3d 381f .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000a3e ff08 .dw $ff08
-000a3f 6e65
-000a40 2d64
-000a41 6f63
-000a42 6564 .db "end-code"
-000a43 0a33 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000a44 3800 .dw DO_COLON
- PFA_ENDCODE:
-000a45 0721 .dw XT_COMPILE
-000a46 940c .dw $940c
-000a47 0721 .dw XT_COMPILE
-000a48 3804 .dw DO_NEXT
-000a49 381f .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000a4a ff08 .dw $ff08
-000a4b 6d28
-000a4c 7261
-000a4d 656b
-000a4e 2972 .db "(marker)"
-000a4f 0a3e .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-000a50 386e .dw PFA_DOVALUE1
- PFA_MARKER:
-000a51 0068 .dw EE_MARKER
-000a52 3d9f .dw XT_EDEFERFETCH
-000a53 3da9 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000a54 0008 .dw $0008
-000a55 6f70
-000a56 7473
-000a57 6f70
-000a58 656e .db "postpone"
-000a59 0a4a .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000a5a 3800 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000a5b 0580 .dw XT_PARSENAME
-000a5c 05c3 .dw XT_FORTHRECOGNIZER
-000a5d 05ce .dw XT_RECOGNIZE
-000a5e 38b0 .dw XT_DUP
-000a5f 38fe .dw XT_TO_R
-000a60 0185 .dw XT_ICELLPLUS
-000a61 0185 .dw XT_ICELLPLUS
-000a62 3bca .dw XT_FETCHI
-000a63 3829 .dw XT_EXECUTE
-000a64 38f5 .dw XT_R_FROM
-000a65 0185 .dw XT_ICELLPLUS
-000a66 3bca .dw XT_FETCHI
-000a67 072c .dw XT_COMMA
-000a68 381f .dw XT_EXIT
- .endif
-
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000a69 ff0b .dw $ff0b
-000a6a 7061
-000a6b 6c70
-000a6c 7574
-000a6d 6e72
-000a6e 656b
-000a6f 0079 .db "applturnkey",0
-000a70 0a54 .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000a71 3800 .dw DO_COLON
- PFA_APPLTURNKEY:
-000a72 00c7 .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-000a73 3c96 .dw XT_INTON
- .endif
-
-000a74 013e .dw XT_DOT_VER
-000a75 3fad .dw XT_SPACE
-000a76 0395 .dw XT_DOSLITERAL
-000a77 000a .dw 10
-000a78 6f46
-000a79 7472
-000a7a 6468
-000a7b 6975
-000a7c 6f6e .db "Forthduino"
-000a7d 03c8 .dw XT_ITYPE
-
-000a7e 381f .dw XT_EXIT
-
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-003800 93bf push XH
-003801 93af push XL ; PUSH IP
-003802 01db movw XL, wl
-003803 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-003804 14b2 cp isrflag, zerol
-003805 f469 brne DO_INTERRUPT
- .endif
-003806 01fd movw zl, XL ; READ IP
-003807 0fee
-003808 1fff
-003809 9165
-00380a 9175 readflashcell wl, wh
-00380b 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00380c 01fb movw zl, wl
-00380d 0fee
-00380e 1fff
-00380f 9105
-003810 9115 readflashcell temp0,temp1
-003811 01f8 movw zl, temp0
-003812 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-003813 939a
-003814 938a savetos
-003815 2d8b mov tosl, isrflag
-003816 2799 clr tosh
-003817 24bb clr isrflag
-003818 eb6f ldi wl, LOW(XT_ISREXEC)
-003819 e37c ldi wh, HIGH(XT_ISREXEC)
-00381a cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00381b ff04 .dw $ff04
-00381c 7865
-00381d 7469 .db "exit"
-00381e 0a69 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-00381f 3820 .dw PFA_EXIT
- PFA_EXIT:
-003820 91af pop XL
-003821 91bf pop XH
-003822 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-003823 ff07 .dw $ff07
-003824 7865
-003825 6365
-003826 7475
-003827 0065 .db "execute",0
-003828 381b .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-003829 382a .dw PFA_EXECUTE
- PFA_EXECUTE:
-00382a 01bc movw wl, tosl
-00382b 9189
-00382c 9199 loadtos
-00382d cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00382e 382f .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-00382f 01fd movw zl, XL
-003830 0fee
-003831 1fff
-003832 91a5
-003833 91b5 readflashcell XL,XH
-003834 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-003835 3836 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-003836 2b98 or tosh, tosl
-003837 9189
-003838 9199 loadtos
-003839 f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00383a 9611 adiw XL, 1
-00383b cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00383c 383d .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00383d 939a
-00383e 938a savetos
-00383f 01fd movw zl, xl
-003840 0fee
-003841 1fff
-003842 9185
-003843 9195 readflashcell tosl,tosh
-003844 9611 adiw xl, 1
-003845 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-003846 3847 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-003847 939a
-003848 938a savetos
-003849 01fb movw zl, wl
-00384a 9631 adiw zl,1
-00384b 0fee
-00384c 1fff
-00384d 9185
-00384e 9195 readflashcell tosl,tosh
-00384f cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-003850 3851 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-003851 939a
-003852 938a savetos
-003853 01cb movw tosl, wl
-003854 9601 adiw tosl, 1
-003855 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-003856 3857 .dw PFA_DOUSER
- PFA_DOUSER:
-003857 939a
-003858 938a savetos
-003859 01fb movw zl, wl
-00385a 9631 adiw zl, 1
-00385b 0fee
-00385c 1fff
-00385d 9185
-00385e 9195 readflashcell tosl,tosh
-00385f 0d84 add tosl, upl
-003860 1d95 adc tosh, uph
-003861 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-003862 ff07 .dw $ff07
-003863 7628
-003864 6c61
-003865 6575
-003866 0029 .db "(value)", 0
-003867 3823 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-003868 3800 .dw DO_COLON
- PFA_DOVALUE:
-003869 06fe .dw XT_DOCREATE
-00386a 085e .dw XT_REVEAL
-00386b 0721 .dw XT_COMPILE
-00386c 386e .dw PFA_DOVALUE1
-00386d 381f .dw XT_EXIT
- PFA_DOVALUE1:
-00386e 940e 0877 call_ DO_DODOES
-003870 38b0 .dw XT_DUP
-003871 0185 .dw XT_ICELLPLUS
-003872 3bca .dw XT_FETCHI
-003873 3829 .dw XT_EXECUTE
-003874 381f .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-003875 ff01 .dw $ff01
-003876 0040 .db "@",0
-003877 3862 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-003878 3879 .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-003879 01fc movw zl, tosl
- ; low byte is read before the high byte
-00387a 9181 ld tosl, z+
-00387b 9191 ld tosh, z+
-00387c cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00387d ff01 .dw $ff01
-00387e 0021 .db "!",0
-00387f 3875 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-003880 3881 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-003881 01fc movw zl, tosl
-003882 9189
-003883 9199 loadtos
- ; the high byte is written before the low byte
-003884 8391 std Z+1, tosh
-003885 8380 std Z+0, tosl
-003886 9189
-003887 9199 loadtos
-003888 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-003889 ff02 .dw $ff02
-00388a 2163 .db "c!"
-00388b 387d .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00388c 388d .dw PFA_CSTORE
- PFA_CSTORE:
-00388d 01fc movw zl, tosl
-00388e 9189
-00388f 9199 loadtos
-003890 8380 st Z, tosl
-003891 9189
-003892 9199 loadtos
-003893 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-003894 ff02 .dw $ff02
-003895 4063 .db "c@"
-003896 3889 .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-003897 3898 .dw PFA_CFETCH
- PFA_CFETCH:
-003898 01fc movw zl, tosl
-003899 2799 clr tosh
-00389a 8180 ld tosl, Z
-00389b cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00389c ff02 .dw $ff02
-00389d 7540 .db "@u"
-00389e 3894 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-00389f 3800 .dw DO_COLON
- PFA_FETCHU:
-0038a0 3b01 .dw XT_UP_FETCH
-0038a1 399c .dw XT_PLUS
-0038a2 3878 .dw XT_FETCH
-0038a3 381f .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-0038a4 ff02 .dw $ff02
-0038a5 7521 .db "!u"
-0038a6 389c .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-0038a7 3800 .dw DO_COLON
- PFA_STOREU:
-0038a8 3b01 .dw XT_UP_FETCH
-0038a9 399c .dw XT_PLUS
-0038aa 3880 .dw XT_STORE
-0038ab 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-0038ac ff03 .dw $ff03
-0038ad 7564
-0038ae 0070 .db "dup",0
-0038af 38a4 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-0038b0 38b1 .dw PFA_DUP
- PFA_DUP:
-0038b1 939a
-0038b2 938a savetos
-0038b3 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-0038b4 ff04 .dw $ff04
-0038b5 643f
-0038b6 7075 .db "?dup"
-0038b7 38ac .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-0038b8 38b9 .dw PFA_QDUP
- PFA_QDUP:
-0038b9 2f08 mov temp0, tosl
-0038ba 2b09 or temp0, tosh
-0038bb f011 breq PFA_QDUP1
-0038bc 939a
-0038bd 938a savetos
- PFA_QDUP1:
-0038be cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-0038bf ff04 .dw $ff04
-0038c0 7773
-0038c1 7061 .db "swap"
-0038c2 38b4 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-0038c3 38c4 .dw PFA_SWAP
- PFA_SWAP:
-0038c4 018c movw temp0, tosl
-0038c5 9189
-0038c6 9199 loadtos
-0038c7 931a st -Y, temp1
-0038c8 930a st -Y, temp0
-0038c9 cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-0038ca ff04 .dw $ff04
-0038cb 766f
-0038cc 7265 .db "over"
-0038cd 38bf .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-0038ce 38cf .dw PFA_OVER
- PFA_OVER:
-0038cf 939a
-0038d0 938a savetos
-0038d1 818a ldd tosl, Y+2
-0038d2 819b ldd tosh, Y+3
-
-0038d3 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-0038d4 ff04 .dw $ff04
-0038d5 7264
-0038d6 706f .db "drop"
-0038d7 38ca .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-0038d8 38d9 .dw PFA_DROP
- PFA_DROP:
-0038d9 9189
-0038da 9199 loadtos
-0038db cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-0038dc ff03 .dw $ff03
-0038dd 6f72
-0038de 0074 .db "rot",0
-0038df 38d4 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-0038e0 38e1 .dw PFA_ROT
- PFA_ROT:
-0038e1 018c movw temp0, tosl
-0038e2 9129 ld temp2, Y+
-0038e3 9139 ld temp3, Y+
-0038e4 9189
-0038e5 9199 loadtos
-
-0038e6 933a st -Y, temp3
-0038e7 932a st -Y, temp2
-0038e8 931a st -Y, temp1
-0038e9 930a st -Y, temp0
-
-0038ea cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-0038eb ff03 .dw $ff03
-0038ec 696e
-0038ed 0070 .db "nip",0
-0038ee 38dc .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-0038ef 38f0 .dw PFA_NIP
- PFA_NIP:
-0038f0 9622 adiw yl, 2
-0038f1 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-0038f2 ff02 .dw $ff02
-0038f3 3e72 .db "r>"
-0038f4 38eb .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-0038f5 38f6 .dw PFA_R_FROM
- PFA_R_FROM:
-0038f6 939a
-0038f7 938a savetos
-0038f8 918f pop tosl
-0038f9 919f pop tosh
-0038fa cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-0038fb ff02 .dw $ff02
-0038fc 723e .db ">r"
-0038fd 38f2 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-0038fe 38ff .dw PFA_TO_R
- PFA_TO_R:
-0038ff 939f push tosh
-003900 938f push tosl
-003901 9189
-003902 9199 loadtos
-003903 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-003904 ff02 .dw $ff02
-003905 4072 .db "r@"
-003906 38fb .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-003907 3908 .dw PFA_R_FETCH
- PFA_R_FETCH:
-003908 939a
-003909 938a savetos
-00390a 918f pop tosl
-00390b 919f pop tosh
-00390c 939f push tosh
-00390d 938f push tosl
-00390e cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-00390f ff02 .dw $ff02
-003910 3e3c .db "<>"
-003911 3904 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-003912 3800 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-003913 3fde
-003914 3919
-003915 381f .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-003916 ff02 .dw $ff02
-003917 3d30 .db "0="
-003918 390f .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-003919 391a .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00391a 2b98 or tosh, tosl
-00391b f5d1 brne PFA_ZERO1
-00391c c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00391d ff02 .dw $ff02
-00391e 3c30 .db "0<"
-00391f 3916 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-003920 3921 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-003921 fd97 sbrc tosh,7
-003922 c02a rjmp PFA_TRUE1
-003923 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-003924 ff02 .dw $ff02
-003925 3e30 .db "0>"
-003926 391d .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-003927 3928 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-003928 1582 cp tosl, zerol
-003929 0593 cpc tosh, zeroh
-00392a f15c brlt PFA_ZERO1
-00392b f151 brbs 1, PFA_ZERO1
-00392c c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00392d ff03 .dw $ff03
-00392e 3064
-00392f 003e .db "d0>",0
-003930 3924 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-003931 3932 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-003932 1582 cp tosl, zerol
-003933 0593 cpc tosh, zeroh
-003934 9189
-003935 9199 loadtos
-003936 0582 cpc tosl, zerol
-003937 0593 cpc tosh, zeroh
-003938 f0ec brlt PFA_ZERO1
-003939 f0e1 brbs 1, PFA_ZERO1
-00393a c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00393b ff03 .dw $ff03
-00393c 3064
-00393d 003c .db "d0<",0
-00393e 392d .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-00393f 3940 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-003940 9622 adiw Y,2
-003941 fd97 sbrc tosh,7
-003942 940c 394d jmp PFA_TRUE1
-003944 940c 3956 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-003946 ff04 .dw $ff04
-003947 7274
-003948 6575 .db "true"
-003949 393b .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00394a 394b .dw PFA_TRUE
- PFA_TRUE:
-00394b 939a
-00394c 938a savetos
- PFA_TRUE1:
-00394d ef8f ser tosl
-00394e ef9f ser tosh
-00394f ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-003950 ff01 .dw $ff01
-003951 0030 .db "0",0
-003952 3946 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-003953 3954 .dw PFA_ZERO
- PFA_ZERO:
-003954 939a
-003955 938a savetos
- PFA_ZERO1:
-003956 01c1 movw tosl, zerol
-003957 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-003958 ff02 .dw $ff02
-003959 3c75 .db "u<"
-00395a 3950 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00395b 395c .dw PFA_ULESS
- PFA_ULESS:
-00395c 9129 ld temp2, Y+
-00395d 9139 ld temp3, Y+
-00395e 1782 cp tosl, temp2
-00395f 0793 cpc tosh, temp3
-003960 f3a8 brlo PFA_ZERO1
-003961 f3a1 brbs 1, PFA_ZERO1
-003962 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-003963 ff02 .dw $ff02
-003964 3e75 .db "u>"
-003965 3958 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-003966 3800 .dw DO_COLON
- PFA_UGREATER:
- .endif
-003967 38c3 .DW XT_SWAP
-003968 395b .dw XT_ULESS
-003969 381f .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00396a ff01 .dw $ff01
-00396b 003c .db "<",0
-00396c 3963 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00396d 396e .dw PFA_LESS
- PFA_LESS:
-00396e 9129 ld temp2, Y+
-00396f 9139 ld temp3, Y+
-003970 1728 cp temp2, tosl
-003971 0739 cpc temp3, tosh
- PFA_LESSDONE:
-003972 f71c brge PFA_ZERO1
-003973 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-003974 ff01 .dw $ff01
-003975 003e .db ">",0
-003976 396a .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-003977 3978 .dw PFA_GREATER
- PFA_GREATER:
-003978 9129 ld temp2, Y+
-003979 9139 ld temp3, Y+
-00397a 1728 cp temp2, tosl
-00397b 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00397c f2cc brlt PFA_ZERO1
-00397d f2c1 brbs 1, PFA_ZERO1
-00397e cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-00397f ff04 .dw $ff04
-003980 6f6c
-003981 3267 .db "log2"
-003982 3974 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-003983 3984 .dw PFA_LOG2
- PFA_LOG2:
-003984 01fc movw zl, tosl
-003985 2799 clr tosh
-003986 e180 ldi tosl, 16
- PFA_LOG2_1:
-003987 958a dec tosl
-003988 f022 brmi PFA_LOG2_2 ; wrong data
-003989 0fee lsl zl
-00398a 1fff rol zh
-00398b f7d8 brcc PFA_LOG2_1
-00398c ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00398d 959a dec tosh
-00398e ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-00398f ff01 .dw $ff01
-003990 002d .db "-",0
-003991 397f .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-003992 3993 .dw PFA_MINUS
- PFA_MINUS:
-003993 9109 ld temp0, Y+
-003994 9119 ld temp1, Y+
-003995 1b08 sub temp0, tosl
-003996 0b19 sbc temp1, tosh
-003997 01c8 movw tosl, temp0
-003998 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-003999 ff01 .dw $ff01
-00399a 002b .db "+",0
-00399b 398f .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00399c 399d .dw PFA_PLUS
- PFA_PLUS:
-00399d 9109 ld temp0, Y+
-00399e 9119 ld temp1, Y+
-00399f 0f80 add tosl, temp0
-0039a0 1f91 adc tosh, temp1
-0039a1 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-0039a2 ff02 .dw $ff02
-0039a3 2a6d .db "m*"
-0039a4 3999 .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-0039a5 39a6 .dw PFA_MSTAR
- PFA_MSTAR:
-0039a6 018c movw temp0, tosl
-0039a7 9189
-0039a8 9199 loadtos
-0039a9 019c movw temp2, tosl
- ; high cell ah*bh
-0039aa 0231 muls temp3, temp1
-0039ab 0170 movw temp4, r0
- ; low cell al*bl
-0039ac 9f20 mul temp2, temp0
-0039ad 01c0 movw tosl, r0
- ; signed ah*bl
-0039ae 0330 mulsu temp3, temp0
-0039af 08f3 sbc temp5, zeroh
-0039b0 0d90 add tosh, r0
-0039b1 1ce1 adc temp4, r1
-0039b2 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-0039b3 0312 mulsu temp1, temp2
-0039b4 08f3 sbc temp5, zeroh
-0039b5 0d90 add tosh, r0
-0039b6 1ce1 adc temp4, r1
-0039b7 1cf3 adc temp5, zeroh
-
-0039b8 939a
-0039b9 938a savetos
-0039ba 01c7 movw tosl, temp4
-0039bb ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-0039bc ff06 .dw $ff06
-0039bd 6d75
-0039be 6d2f
-0039bf 646f .db "um/mod"
-0039c0 39a2 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-0039c1 39c2 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-0039c2 017c movw temp4, tosl
-
-0039c3 9129 ld temp2, Y+
-0039c4 9139 ld temp3, Y+
-
-0039c5 9109 ld temp0, Y+
-0039c6 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-0039c7 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-0039c8 2755 clr temp7
-0039c9 0f00 lsl temp0
-0039ca 1f11 rol temp1
-0039cb 1f22 rol temp2
-0039cc 1f33 rol temp3
-0039cd 1f55 rol temp7
-
- ; try subtracting divisor
-0039ce 152e cp temp2, temp4
-0039cf 053f cpc temp3, temp5
-0039d0 0552 cpc temp7,zerol
-
-0039d1 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-0039d2 9503 inc temp0
-0039d3 192e sub temp2, temp4
-0039d4 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-0039d5 954a dec temp6
-0039d6 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-0039d7 933a st -Y,temp3
-0039d8 932a st -Y,temp2
-
- ; put quotient on stack
-0039d9 01c8 movw tosl, temp0
-0039da ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-0039db ff03 .dw $ff03
-0039dc 6d75
-0039dd 002a .db "um*",0
-0039de 39bc .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-0039df 39e0 .dw PFA_UMSTAR
- PFA_UMSTAR:
-0039e0 018c movw temp0, tosl
-0039e1 9189
-0039e2 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-0039e3 9f80 mul tosl,temp0
-0039e4 01f0 movw zl, r0
-0039e5 2722 clr temp2
-0039e6 2733 clr temp3
- ; middle bytes
-0039e7 9f90 mul tosh, temp0
-0039e8 0df0 add zh, r0
-0039e9 1d21 adc temp2, r1
-0039ea 1d33 adc temp3, zeroh
-
-0039eb 9f81 mul tosl, temp1
-0039ec 0df0 add zh, r0
-0039ed 1d21 adc temp2, r1
-0039ee 1d33 adc temp3, zeroh
-
-0039ef 9f91 mul tosh, temp1
-0039f0 0d20 add temp2, r0
-0039f1 1d31 adc temp3, r1
-0039f2 01cf movw tosl, zl
-0039f3 939a
-0039f4 938a savetos
-0039f5 01c9 movw tosl, temp2
-0039f6 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-0039f7 ff06 .dw $ff06
-0039f8 6e69
-0039f9 6576
-0039fa 7472 .db "invert"
-0039fb 39db .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-0039fc 39fd .dw PFA_INVERT
- PFA_INVERT:
-0039fd 9580 com tosl
-0039fe 9590 com tosh
-0039ff ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-003a00 ff02 .dw $ff02
-003a01 2f32 .db "2/"
-003a02 39f7 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-003a03 3a04 .dw PFA_2SLASH
- PFA_2SLASH:
-003a04 9595 asr tosh
-003a05 9587 ror tosl
-003a06 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-003a07 ff02 .dw $ff02
-003a08 2a32 .db "2*"
-003a09 3a00 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-003a0a 3a0b .dw PFA_2STAR
- PFA_2STAR:
-003a0b 0f88 lsl tosl
-003a0c 1f99 rol tosh
-003a0d cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-003a0e ff03 .dw $ff03
-003a0f 6e61
-003a10 0064 .db "and",0
-003a11 3a07 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-003a12 3a13 .dw PFA_AND
- PFA_AND:
-003a13 9109 ld temp0, Y+
-003a14 9119 ld temp1, Y+
-003a15 2380 and tosl, temp0
-003a16 2391 and tosh, temp1
-003a17 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-003a18 ff02 .dw $ff02
-003a19 726f .db "or"
-003a1a 3a0e .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-003a1b 3a1c .dw PFA_OR
- PFA_OR:
-003a1c 9109 ld temp0, Y+
-003a1d 9119 ld temp1, Y+
-003a1e 2b80 or tosl, temp0
-003a1f 2b91 or tosh, temp1
-003a20 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-003a21 ff03 .dw $ff03
-003a22 6f78
-003a23 0072 .db "xor",0
-003a24 3a18 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-003a25 3a26 .dw PFA_XOR
- PFA_XOR:
-003a26 9109 ld temp0, Y+
-003a27 9119 ld temp1, Y+
-003a28 2780 eor tosl, temp0
-003a29 2791 eor tosh, temp1
-003a2a cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-003a2b ff02 .dw $ff02
-003a2c 2b31 .db "1+"
-003a2d 3a21 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-003a2e 3a2f .dw PFA_1PLUS
- PFA_1PLUS:
-003a2f 9601 adiw tosl,1
-003a30 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-003a31 ff02 .dw $ff02
-003a32 2d31 .db "1-"
-003a33 3a2b .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-003a34 3a35 .dw PFA_1MINUS
- PFA_1MINUS:
-003a35 9701 sbiw tosl, 1
-003a36 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-003a37 ff07 .dw $ff07
-003a38 6e3f
-003a39 6765
-003a3a 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-003a3b 0065 .db "?negate"
-003a3c 3a31 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-003a3d 3800 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-003a3e 3920
-003a3f 3835 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-003a40 3a42 DEST(QNEG1)
-003a41 3e26 .DW XT_NEGATE
-003a42 381f QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-003a43 ff06 .dw $ff06
-003a44 736c
-003a45 6968
-003a46 7466 .db "lshift"
-003a47 3a37 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-003a48 3a49 .dw PFA_LSHIFT
- PFA_LSHIFT:
-003a49 01fc movw zl, tosl
-003a4a 9189
-003a4b 9199 loadtos
- PFA_LSHIFT1:
-003a4c 9731 sbiw zl, 1
-003a4d f01a brmi PFA_LSHIFT2
-003a4e 0f88 lsl tosl
-003a4f 1f99 rol tosh
-003a50 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-003a51 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-003a52 ff06 .dw $ff06
-003a53 7372
-003a54 6968
-003a55 7466 .db "rshift"
-003a56 3a43 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-003a57 3a58 .dw PFA_RSHIFT
- PFA_RSHIFT:
-003a58 01fc movw zl, tosl
-003a59 9189
-003a5a 9199 loadtos
- PFA_RSHIFT1:
-003a5b 9731 sbiw zl, 1
-003a5c f01a brmi PFA_RSHIFT2
-003a5d 9596 lsr tosh
-003a5e 9587 ror tosl
-003a5f cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-003a60 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-003a61 ff02 .dw $ff02
-003a62 212b .db "+!"
-003a63 3a52 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-003a64 3a65 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-003a65 01fc movw zl, tosl
-003a66 9189
-003a67 9199 loadtos
-003a68 8120 ldd temp2, Z+0
-003a69 8131 ldd temp3, Z+1
-003a6a 0f82 add tosl, temp2
-003a6b 1f93 adc tosh, temp3
-003a6c 8380 std Z+0, tosl
-003a6d 8391 std Z+1, tosh
-003a6e 9189
-003a6f 9199 loadtos
-003a70 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-003a71 ff03 .dw $ff03
-003a72 7072
-003a73 0040 .db "rp@",0
-003a74 3a61 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-003a75 3a76 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-003a76 939a
-003a77 938a savetos
-003a78 b78d in tosl, SPL
-003a79 b79e in tosh, SPH
-003a7a cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-003a7b ff03 .dw $ff03
-003a7c 7072
-003a7d 0021 .db "rp!",0
-003a7e 3a71 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-003a7f 3a80 .dw PFA_RP_STORE
- PFA_RP_STORE:
-003a80 b72f in temp2, SREG
-003a81 94f8 cli
-003a82 bf8d out SPL, tosl
-003a83 bf9e out SPH, tosh
-003a84 bf2f out SREG, temp2
-003a85 9189
-003a86 9199 loadtos
-003a87 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-003a88 ff03 .dw $ff03
-003a89 7073
-003a8a 0040 .db "sp@",0
-003a8b 3a7b .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-003a8c 3a8d .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-003a8d 939a
-003a8e 938a savetos
-003a8f 01ce movw tosl, yl
-003a90 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-003a91 ff03 .dw $ff03
-003a92 7073
-003a93 0021 .db "sp!",0
-003a94 3a88 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-003a95 3a96 .dw PFA_SP_STORE
- PFA_SP_STORE:
-003a96 01ec movw yl, tosl
-003a97 9189
-003a98 9199 loadtos
-003a99 cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-003a9a 3a9b .dw PFA_DODO
- PFA_DODO:
-003a9b 9129 ld temp2, Y+
-003a9c 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-003a9d e8e0 ldi zl, $80
-003a9e 0f3e add temp3, zl
-003a9f 1b82 sub tosl, temp2
-003aa0 0b93 sbc tosh, temp3
-
-003aa1 933f push temp3
-003aa2 932f push temp2 ; limit ( --> limit + $8000)
-003aa3 939f push tosh
-003aa4 938f push tosl ; start -> index ( --> index - (limit - $8000)
-003aa5 9189
-003aa6 9199 loadtos
-003aa7 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-003aa8 ff01 .dw $FF01
-003aa9 0069 .db "i",0
-003aaa 3a91 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-003aab 3aac .dw PFA_I
- PFA_I:
-003aac 939a
-003aad 938a savetos
-003aae 918f pop tosl
-003aaf 919f pop tosh ; index
-003ab0 91ef pop zl
-003ab1 91ff pop zh ; limit
-003ab2 93ff push zh
-003ab3 93ef push zl
-003ab4 939f push tosh
-003ab5 938f push tosl
-003ab6 0f8e add tosl, zl
-003ab7 1f9f adc tosh, zh
-003ab8 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-003ab9 3aba .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-003aba 91ef pop zl
-003abb 91ff pop zh
-003abc 0fe8 add zl, tosl
-003abd 1ff9 adc zh, tosh
-003abe 9189
-003abf 9199 loadtos
-003ac0 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-003ac1 93ff push zh
-003ac2 93ef push zl
-003ac3 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-003ac4 910f pop temp0
-003ac5 911f pop temp1 ; remove limit
-003ac6 9611 adiw xl, 1 ; skip branch-back address
-003ac7 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-003ac8 3ac9 .dw PFA_DOLOOP
- PFA_DOLOOP:
-003ac9 91ef pop zl
-003aca 91ff pop zh
-003acb 9631 adiw zl,1
-003acc f3bb brvs PFA_DOPLUSLOOP_LEAVE
-003acd cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-003ace ff06 .dw $ff06
-003acf 6e75
-003ad0 6f6c
-003ad1 706f .db "unloop"
-003ad2 3aa8 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-003ad3 3ad4 .dw PFA_UNLOOP
- PFA_UNLOOP:
-003ad4 911f pop temp1
-003ad5 910f pop temp0
-003ad6 911f pop temp1
-003ad7 910f pop temp0
-003ad8 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-003ad9 ff06 .dw $ff06
-003ada 6d63
-003adb 766f
-003adc 3e65 .db "cmove>"
-003add 3ace .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-003ade 3adf .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-003adf 93bf push xh
-003ae0 93af push xl
-003ae1 91e9 ld zl, Y+
-003ae2 91f9 ld zh, Y+ ; addr-to
-003ae3 91a9 ld xl, Y+
-003ae4 91b9 ld xh, Y+ ; addr-from
-003ae5 2f09 mov temp0, tosh
-003ae6 2b08 or temp0, tosl
-003ae7 f041 brbs 1, PFA_CMOVE_G1
-003ae8 0fe8 add zl, tosl
-003ae9 1ff9 adc zh, tosh
-003aea 0fa8 add xl, tosl
-003aeb 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-003aec 911e ld temp1, -X
-003aed 9312 st -Z, temp1
-003aee 9701 sbiw tosl, 1
-003aef f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-003af0 91af pop xl
-003af1 91bf pop xh
-003af2 9189
-003af3 9199 loadtos
-003af4 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-003af5 ff02 .dw $ff02
-003af6 3c3e .db "><"
-003af7 3ad9 .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-003af8 3af9 .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-003af9 2f09 mov temp0, tosh
-003afa 2f98 mov tosh, tosl
-003afb 2f80 mov tosl, temp0
-003afc cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-003afd ff03 .dw $ff03
-003afe 7075
-003aff 0040 .db "up@",0
-003b00 3af5 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-003b01 3b02 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-003b02 939a
-003b03 938a savetos
-003b04 01c2 movw tosl, upl
-003b05 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-003b06 ff03 .dw $ff03
-003b07 7075
-003b08 0021 .db "up!",0
-003b09 3afd .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-003b0a 3b0b .dw PFA_UP_STORE
- PFA_UP_STORE:
-003b0b 012c movw upl, tosl
-003b0c 9189
-003b0d 9199 loadtos
-003b0e ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-003b0f ff03 .dw $ff03
-003b10 6d31
-003b11 0073 .db "1ms",0
-003b12 3b06 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-003b13 3b14 .dw PFA_1MS
- PFA_1MS:
-003b14 eae0
-003b15 e0ff
-003b16 9731
-003b17 f7f1 delay 1000
-003b18 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-003b19 ff03 .dw $ff03
-003b1a 3e32
-003b1b 0072 .db "2>r",0
-003b1c 3b0f .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-003b1d 3b1e .dw PFA_2TO_R
- PFA_2TO_R:
-003b1e 01fc movw zl, tosl
-003b1f 9189
-003b20 9199 loadtos
-003b21 939f push tosh
-003b22 938f push tosl
-003b23 93ff push zh
-003b24 93ef push zl
-003b25 9189
-003b26 9199 loadtos
-003b27 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-003b28 ff03 .dw $ff03
-003b29 7232
-003b2a 003e .db "2r>",0
-003b2b 3b19 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-003b2c 3b2d .dw PFA_2R_FROM
- PFA_2R_FROM:
-003b2d 939a
-003b2e 938a savetos
-003b2f 91ef pop zl
-003b30 91ff pop zh
-003b31 918f pop tosl
-003b32 919f pop tosh
-003b33 939a
-003b34 938a savetos
-003b35 01cf movw tosl, zl
-003b36 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-003b37 ff02 .dw $ff02
-003b38 6521 .db "!e"
-003b39 3b28 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-003b3a 3b3b .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-003b3b 01fc movw zl, tosl
-003b3c 9189
-003b3d 9199 loadtos
-003b3e b72f in_ temp2, SREG
-003b3f 94f8 cli
-003b40 d028 rcall PFA_FETCHE2
-003b41 b500 in_ temp0, EEDR
-003b42 1708 cp temp0,tosl
-003b43 f009 breq PFA_STOREE3
-003b44 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-003b45 9631 adiw zl,1
-003b46 d022 rcall PFA_FETCHE2
-003b47 b500 in_ temp0, EEDR
-003b48 1709 cp temp0,tosh
-003b49 f011 breq PFA_STOREE4
-003b4a 2f89 mov tosl, tosh
-003b4b d004 rcall PFA_STOREE1
- PFA_STOREE4:
-003b4c bf2f out_ SREG, temp2
-003b4d 9189
-003b4e 9199 loadtos
-003b4f ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-003b50 99f9 sbic EECR, EEPE
-003b51 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-003b52 b707 in_ temp0, SPMCSR
-003b53 fd00 sbrc temp0,SPMEN
-003b54 cffd rjmp PFA_STOREE2
-
-003b55 bdf2 out_ EEARH,zh
-003b56 bde1 out_ EEARL,zl
-003b57 bd80 out_ EEDR, tosl
-003b58 9afa sbi EECR,EEMPE
-003b59 9af9 sbi EECR,EEPE
-
-003b5a 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-003b5b ff02 .dw $ff02
-003b5c 6540 .db "@e"
-003b5d 3b37 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-003b5e 3b5f .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-003b5f b72f in_ temp2, SREG
-003b60 94f8 cli
-003b61 01fc movw zl, tosl
-003b62 d006 rcall PFA_FETCHE2
-003b63 b580 in_ tosl, EEDR
-
-003b64 9631 adiw zl,1
-
-003b65 d003 rcall PFA_FETCHE2
-003b66 b590 in_ tosh, EEDR
-003b67 bf2f out_ SREG, temp2
-003b68 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-003b69 99f9 sbic EECR, EEPE
-003b6a cffe rjmp PFA_FETCHE2
-
-003b6b bdf2 out_ EEARH,zh
-003b6c bde1 out_ EEARL,zl
-
-003b6d 9af8 sbi EECR,EERE
-003b6e 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-003b6f ff02 .dw $ff02
-003b70 6921 .db "!i"
-003b71 3b5b .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-003b72 3dfe .dw PFA_DODEFER1
- PFA_STOREI:
-003b73 0066 .dw EE_STOREI
-003b74 3d9f .dw XT_EDEFERFETCH
-003b75 3da9 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-003b76 ff09 .dw $ff09
-003b77 2128
-003b78 2d69
-003b79 726e
-003b7a 7777
-003b7b 0029 .db "(!i-nrww)",0
-003b7c 3b6f .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-003b7d 3b7e .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-003b7e b71f in temp1,SREG
-003b7f 931f push temp1
-003b80 94f8 cli
-
-003b81 019c movw temp2, tosl ; save the (word) address
-003b82 9189
-003b83 9199 loadtos ; get the new value for the flash cell
-003b84 93af push xl
-003b85 93bf push xh
-003b86 93cf push yl
-003b87 93df push yh
-003b88 d009 rcall DO_STOREI_atmega
-003b89 91df pop yh
-003b8a 91cf pop yl
-003b8b 91bf pop xh
-003b8c 91af pop xl
- ; finally clear the stack
-003b8d 9189
-003b8e 9199 loadtos
-003b8f 911f pop temp1
- ; restore status register (and interrupt enable flag)
-003b90 bf1f out SREG,temp1
-
-003b91 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-003b92 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-003b93 94e0 com temp4
-003b94 94f0 com temp5
-003b95 218e and tosl, temp4
-003b96 219f and tosh, temp5
-003b97 2b98 or tosh, tosl
-003b98 f019 breq DO_STOREI_writepage
-003b99 01f9 movw zl, temp2
-003b9a e002 ldi temp0,(1<<PGERS)
-003b9b d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-003b9c 01f9 movw zl, temp2
-003b9d e004 ldi temp0,(1<<PGWRT)
-003b9e d01d rcall dospm
-
- ; reenable RWW section
-003b9f 01f9 movw zl, temp2
-003ba0 e100 ldi temp0,(1<<RWWSRE)
-003ba1 d01a rcall dospm
-003ba2 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-003ba3 01f9 movw zl, temp2
- ; get the beginning of page
-003ba4 7ce0 andi zl,low(pagemask)
-003ba5 7fff andi zh,high(pagemask)
-003ba6 01ef movw y, z
- ; loop counter (in words)
-003ba7 e4a0 ldi xl,low(pagesize)
-003ba8 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-003ba9 01fe movw z, y
-003baa 0fee
-003bab 1fff
-003bac 9145
-003bad 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-003bae 01fe movw z, y
-003baf 17e2 cp zl, temp2
-003bb0 07f3 cpc zh, temp3
-003bb1 f011 breq pageload_newdata
-003bb2 010a movw r0, temp6
-003bb3 c002 rjmp pageload_cont
- pageload_newdata:
-003bb4 017a movw temp4, temp6
-003bb5 010c movw r0, tosl
- pageload_cont:
-003bb6 2700 clr temp0
-003bb7 d004 rcall dospm
-003bb8 9621 adiw y, 1
-003bb9 9711 sbiw x, 1
-003bba f771 brne pageload_loop
-
- pageload_done:
-003bbb 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-003bbc 99f9 sbic EECR, EEPE
-003bbd cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-003bbe b717 in_ temp1, SPMCSR
-003bbf fd10 sbrc temp1, SPMEN
-003bc0 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-003bc1 0fee
-003bc2 1fff writeflashcell
- ; execute spm
-003bc3 6001 ori temp0, (1<<SPMEN)
-003bc4 bf07 out_ SPMCSR,temp0
-003bc5 95e8 spm
-003bc6 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-003bc7 ff02 .dw $ff02
-003bc8 6940 .db "@i"
-003bc9 3b76 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-003bca 3bcb .dw PFA_FETCHI
- PFA_FETCHI:
-003bcb 01fc movw zl, tosl
-003bcc 0fee
-003bcd 1fff
-003bce 9185
-003bcf 9195 readflashcell tosl,tosh
-003bd0 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .elif AMFORTH_NRWW_SIZE>4000
- .include "dict/core_4k.inc"
-
- ; in a short distance to DO_NEXT
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-003bd1 ff03 .dw $ff03
-003bd2 3e6e
-003bd3 0072 .db "n>r",0
-003bd4 3bc7 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-003bd5 3bd6 .dw PFA_N_TO_R
- PFA_N_TO_R:
-003bd6 01fc movw zl, tosl
-003bd7 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-003bd8 9189
-003bd9 9199 loadtos
-003bda 939f push tosh
-003bdb 938f push tosl
-003bdc 950a dec temp0
-003bdd f7d1 brne PFA_N_TO_R1
-003bde 93ef push zl
-003bdf 93ff push zh
-003be0 9189
-003be1 9199 loadtos
-003be2 cc21 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-003be3 ff03 .dw $ff03
-003be4 726e
-003be5 003e .db "nr>",0
-003be6 3bd1 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-003be7 3be8 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-003be8 939a
-003be9 938a savetos
-003bea 91ff pop zh
-003beb 91ef pop zl
-003bec 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-003bed 918f pop tosl
-003bee 919f pop tosh
-003bef 939a
-003bf0 938a savetos
-003bf1 950a dec temp0
-003bf2 f7d1 brne PFA_N_R_FROM1
-003bf3 01cf movw tosl, zl
-003bf4 cc0f jmp_ DO_NEXT
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-003bf5 ff03 .dw $ff03
-003bf6 3264
-003bf7 002a .db "d2*",0
-003bf8 3be3 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-003bf9 3bfa .dw PFA_D2STAR
- PFA_D2STAR:
-003bfa 9109 ld temp0, Y+
-003bfb 9119 ld temp1, Y+
-003bfc 0f00 lsl temp0
-003bfd 1f11 rol temp1
-003bfe 1f88 rol tosl
-003bff 1f99 rol tosh
-003c00 931a st -Y, temp1
-003c01 930a st -Y, temp0
-003c02 cc01 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-003c03 ff03 .dw $ff03
-003c04 3264
-003c05 002f .db "d2/",0
-003c06 3bf5 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-003c07 3c08 .dw PFA_D2SLASH
- PFA_D2SLASH:
-003c08 9109 ld temp0, Y+
-003c09 9119 ld temp1, Y+
-003c0a 9595 asr tosh
-003c0b 9587 ror tosl
-003c0c 9517 ror temp1
-003c0d 9507 ror temp0
-003c0e 931a st -Y, temp1
-003c0f 930a st -Y, temp0
-003c10 cbf3 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-003c11 ff02 .dw $ff02
-003c12 2b64 .db "d+"
-003c13 3c03 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-003c14 3c15 .dw PFA_DPLUS
- PFA_DPLUS:
-003c15 9129 ld temp2, Y+
-003c16 9139 ld temp3, Y+
-
-003c17 90e9 ld temp4, Y+
-003c18 90f9 ld temp5, Y+
-003c19 9149 ld temp6, Y+
-003c1a 9159 ld temp7, Y+
-
-003c1b 0f24 add temp2, temp6
-003c1c 1f35 adc temp3, temp7
-003c1d 1d8e adc tosl, temp4
-003c1e 1d9f adc tosh, temp5
-
-003c1f 933a st -Y, temp3
-003c20 932a st -Y, temp2
-003c21 cbe2 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-003c22 ff02 .dw $ff02
-003c23 2d64 .db "d-"
-003c24 3c11 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-003c25 3c26 .dw PFA_DMINUS
- PFA_DMINUS:
-003c26 9129 ld temp2, Y+
-003c27 9139 ld temp3, Y+
-
-003c28 90e9 ld temp4, Y+
-003c29 90f9 ld temp5, Y+
-003c2a 9149 ld temp6, Y+
-003c2b 9159 ld temp7, Y+
-
-003c2c 1b42 sub temp6, temp2
-003c2d 0b53 sbc temp7, temp3
-003c2e 0ae8 sbc temp4, tosl
-003c2f 0af9 sbc temp5, tosh
-
-003c30 935a st -Y, temp7
-003c31 934a st -Y, temp6
-003c32 01c7 movw tosl, temp4
-003c33 cbd0 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-003c34 ff07 .dw $ff07
-003c35 6964
-003c36 766e
-003c37 7265
-003c38 0074 .db "dinvert",0
-003c39 3c22 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-003c3a 3c3b .dw PFA_DINVERT
- PFA_DINVERT:
-003c3b 9109 ld temp0, Y+
-003c3c 9119 ld temp1, Y+
-003c3d 9580 com tosl
-003c3e 9590 com tosh
-003c3f 9500 com temp0
-003c40 9510 com temp1
-003c41 931a st -Y, temp1
-003c42 930a st -Y, temp0
-003c43 cbc0 jmp_ DO_NEXT
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-003c44 ff04 .dw $ff04
-003c45 6d2f
-003c46 646f .db "/mod"
-003c47 3c34 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-003c48 3c49 .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-003c49 019c movw temp2, tosl
-
-003c4a 9109 ld temp0, Y+
-003c4b 9119 ld temp1, Y+
-
-003c4c 2f41 mov temp6,temp1 ;move dividend High to sign register
-003c4d 2743 eor temp6,temp3 ;xor divisor High with sign register
-003c4e ff17 sbrs temp1,7 ;if MSB in dividend set
-003c4f c004 rjmp PFA_SLASHMOD_1
-003c50 9510 com temp1 ; change sign of dividend
-003c51 9500 com temp0
-003c52 5f0f subi temp0,low(-1)
-003c53 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-003c54 ff37 sbrs temp3,7 ;if MSB in divisor set
-003c55 c004 rjmp PFA_SLASHMOD_2
-003c56 9530 com temp3 ; change sign of divisor
-003c57 9520 com temp2
-003c58 5f2f subi temp2,low(-1)
-003c59 4f3f sbci temp3,high(-1)
-003c5a 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-003c5b 18ff sub temp5,temp5;clear remainder High byte and carry
-003c5c e151 ldi temp7,17 ;init loop counter
-
-003c5d 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-003c5e 1f11 rol temp1
-003c5f 955a dec temp7 ;decrement counter
-003c60 f439 brne PFA_SLASHMOD_5 ;if done
-003c61 ff47 sbrs temp6,7 ; if MSB in sign register set
-003c62 c004 rjmp PFA_SLASHMOD_4
-003c63 9510 com temp1 ; change sign of result
-003c64 9500 com temp0
-003c65 5f0f subi temp0,low(-1)
-003c66 4f1f sbci temp1,high(-1)
-003c67 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-003c68 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-003c69 1cff rol temp5
-003c6a 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-003c6b 0af3 sbc temp5,temp3 ;
-003c6c f420 brcc PFA_SLASHMOD_6 ;if result negative
-003c6d 0ee2 add temp4,temp2 ; restore remainder
-003c6e 1ef3 adc temp5,temp3
-003c6f 9488 clc ; clear carry to be shifted into result
-003c70 cfec rjmp PFA_SLASHMOD_3 ;else
-003c71 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-003c72 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-003c73 92fa st -Y,temp5
-003c74 92ea st -Y,temp4
-
- ; put quotient on stack
-003c75 01c8 movw tosl, temp0
-003c76 cb8d jmp_ DO_NEXT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-003c77 ff03 .dw $ff03
-003c78 6261
-003c79 0073 .db "abs",0
-003c7a 3c44 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-003c7b 3800 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-003c7c 38b0
-003c7d 3a3d
-003c7e 381f .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-003c7f ff04 .dw $ff04
-003c80 6970
-003c81 6b63 .db "pick"
-003c82 3c77 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-003c83 3800 .dw DO_COLON
- PFA_PICK:
- .endif
-003c84 3a2e .dw XT_1PLUS
-003c85 3ec3 .dw XT_CELLS
-003c86 3a8c .dw XT_SP_FETCH
-003c87 399c .dw XT_PLUS
-003c88 3878 .dw XT_FETCH
-003c89 381f .dw XT_EXIT
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-003c8a ff05 .dw $ff05
-003c8b 6563
-003c8c 6c6c
-003c8d 002b .db "cell+",0
-003c8e 3c7f .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-003c8f 3c90 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-003c90 9602 adiw tosl, CELLSIZE
-003c91 cb72 jmp_ DO_NEXT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-003c92 ff04 .dw $ff04
-003c93 692b
-003c94 746e .db "+int"
-003c95 3c8a .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-003c96 3c97 .dw PFA_INTON
- PFA_INTON:
-003c97 9478 sei
-003c98 cb6b jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-003c99 ff04 .dw $ff04
-003c9a 692d
-003c9b 746e .db "-int"
-003c9c 3c92 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-003c9d 3c9e .dw PFA_INTOFF
- PFA_INTOFF:
-003c9e 94f8 cli
-003c9f cb64 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-003ca0 ff04 .dw $ff04
-003ca1 6e69
-003ca2 2174 .db "int!"
-003ca3 3c99 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-003ca4 3800 .dw DO_COLON
- PFA_INTSTORE:
-003ca5 383c .dw XT_DOLITERAL
-003ca6 0000 .dw intvec
-003ca7 399c .dw XT_PLUS
-003ca8 3b3a .dw XT_STOREE
-003ca9 381f .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-003caa ff04 .dw $ff04
-003cab 6e69
-003cac 4074 .db "int@"
-003cad 3ca0 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-003cae 3800 .dw DO_COLON
- PFA_INTFETCH:
-003caf 383c .dw XT_DOLITERAL
-003cb0 0000 .dw intvec
-003cb1 399c .dw XT_PLUS
-003cb2 3b5e .dw XT_FETCHE
-003cb3 381f .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-003cb4 ff08 .dw $ff08
-003cb5 6e69
-003cb6 2d74
-003cb7 7274
-003cb8 7061 .db "int-trap"
-003cb9 3caa .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-003cba 3cbb .dw PFA_INTTRAP
- PFA_INTTRAP:
-003cbb 2eb8 mov isrflag, tosl
-003cbc 9189
-003cbd 9199 loadtos
-003cbe cb45 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-003cbf 3800 .dw DO_COLON
- PFA_ISREXEC:
-003cc0 3cae .dw XT_INTFETCH
-003cc1 3829 .dw XT_EXECUTE
-003cc2 3cc4 .dw XT_ISREND
-003cc3 381f .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-003cc4 3cc5 .dw PFA_ISREND
- PFA_ISREND:
-003cc5 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-003cc6 cb3d jmp_ DO_NEXT
- PFA_ISREND1:
-003cc7 9518 reti
- .endif
-
- ; now the relocatable colon words
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-003cc8 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-003cc9 0395 .dw XT_DOSLITERAL
-003cca 0003 .dw 3
-003ccb 6f20
-003ccc 006b .db " ok",0
- .endif
-003ccd 03c8 .dw XT_ITYPE
-003cce 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-003ccf ff03 .dw $FF03
-003cd0 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-003cd1 006b .db ".ok"
-003cd2 3cb4 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-003cd3 3dfe .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-003cd4 001c .dw USER_P_OK
-003cd5 3dc7 .dw XT_UDEFERFETCH
-003cd6 3dd3 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-003cd7 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-003cd8 0395 .dw XT_DOSLITERAL
-003cd9 0002 .dw 2
-003cda 203e .db "> "
- .endif
-003cdb 3fa0 .dw XT_CR
-003cdc 03c8 .dw XT_ITYPE
-003cdd 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-003cde ff06 .dw $FF06
-003cdf 722e
-003ce0 6165
-003ce1 7964 .db ".ready"
-003ce2 3ccf .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-003ce3 3dfe .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-003ce4 0020 .dw USER_P_RDY
-003ce5 3dc7 .dw XT_UDEFERFETCH
-003ce6 3dd3 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-003ce7 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-003ce8 0395 .dw XT_DOSLITERAL
-003ce9 0004 .dw 4
-003cea 3f20
-003ceb 203f .db " ?? "
- .endif
-003cec 03c8 .dw XT_ITYPE
-003ced 3ebc .dw XT_BASE
-003cee 3878 .dw XT_FETCH
-003cef 38fe .dw XT_TO_R
-003cf0 3f40 .dw XT_DECIMAL
-003cf1 034a .dw XT_DOT
-003cf2 3ee1 .dw XT_TO_IN
-003cf3 3878 .dw XT_FETCH
-003cf4 034a .dw XT_DOT
-003cf5 38f5 .dw XT_R_FROM
-003cf6 3ebc .dw XT_BASE
-003cf7 3880 .dw XT_STORE
-003cf8 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-003cf9 ff06 .dw $FF06
-003cfa 652e
-003cfb 7272
-003cfc 726f .db ".error"
-003cfd 3cde .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-003cfe 3dfe .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-003cff 001e .dw USER_P_ERR
-003d00 3dc7 .dw XT_UDEFERFETCH
-003d01 3dd3 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-003d02 ff04 .dw $ff04
-003d03 7571
-003d04 7469 .db "quit"
-003d05 3cf9 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-003d06 3800 .dw DO_COLON
- .endif
- PFA_QUIT:
-003d07 0821
-003d08 0828
-003d09 3880 .dw XT_LP0,XT_LP,XT_STORE
-003d0a 059a .dw XT_SP0
-003d0b 3a95 .dw XT_SP_STORE
-003d0c 05a7 .dw XT_RP0
-003d0d 3a7f .dw XT_RP_STORE
-003d0e 08b6 .dw XT_LBRACKET
-
- PFA_QUIT2:
-003d0f 3eb6 .dw XT_STATE
-003d10 3878 .dw XT_FETCH
-003d11 3919 .dw XT_ZEROEQUAL
-003d12 3835 .dw XT_DOCONDBRANCH
-003d13 3d15 DEST(PFA_QUIT4)
-003d14 3ce3 .dw XT_PROMPTREADY
- PFA_QUIT4:
-003d15 04ae .dw XT_REFILL
-003d16 3835 .dw XT_DOCONDBRANCH
-003d17 3d27 DEST(PFA_QUIT3)
-003d18 383c .dw XT_DOLITERAL
-003d19 05f5 .dw XT_INTERPRET
-003d1a 3d6f .dw XT_CATCH
-003d1b 38b8 .dw XT_QDUP
-003d1c 3835 .dw XT_DOCONDBRANCH
-003d1d 3d27 DEST(PFA_QUIT3)
-003d1e 38b0 .dw XT_DUP
-003d1f 383c .dw XT_DOLITERAL
-003d20 fffe .dw -2
-003d21 396d .dw XT_LESS
-003d22 3835 .dw XT_DOCONDBRANCH
-003d23 3d25 DEST(PFA_QUIT5)
-003d24 3cfe .dw XT_PROMPTERROR
- PFA_QUIT5:
-003d25 382e .dw XT_DOBRANCH
-003d26 3d07 DEST(PFA_QUIT)
- PFA_QUIT3:
-003d27 3cd3 .dw XT_PROMPTOK
-003d28 382e .dw XT_DOBRANCH
-003d29 3d0f DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-003d2a ff05 .dw $ff05
-003d2b 6170
-003d2c 7375
-003d2d 0065 .db "pause",0
-003d2e 3d02 .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-003d2f 3dfe .dw PFA_DODEFER1
- PFA_PAUSE:
-003d30 0192 .dw ram_pause
-003d31 3db3 .dw XT_RDEFERFETCH
-003d32 3dbd .dw XT_RDEFERSTORE
-
- .dseg
-000192 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-003d33 ff04 .dw $ff04
-003d34 6f63
-003d35 646c .db "cold"
-003d36 3d2a .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-003d37 3d38 .dw PFA_COLD
- PFA_COLD:
-003d38 b6a4 in_ mcu_boot, MCUSR
-003d39 2422 clr zerol
-003d3a 2433 clr zeroh
-003d3b 24bb clr isrflag
-003d3c be24 out_ MCUSR, zerol
- ; clear RAM
-003d3d e0e0 ldi zl, low(ramstart)
-003d3e e0f1 ldi zh, high(ramstart)
- clearloop:
-003d3f 9221 st Z+, zerol
-003d40 30e0 cpi zl, low(sram_size+ramstart)
-003d41 f7e9 brne clearloop
-003d42 30f9 cpi zh, high(sram_size+ramstart)
-003d43 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000194 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-003d44 e9e4 ldi zl, low(ram_user1)
-003d45 e0f1 ldi zh, high(ram_user1)
-003d46 012f movw upl, zl
- ; init return stack pointer
-003d47 ef0f ldi temp0,low(rstackstart)
-003d48 bf0d out_ SPL,temp0
-003d49 8304 std Z+4, temp0
-003d4a e018 ldi temp1,high(rstackstart)
-003d4b bf1e out_ SPH,temp1
-003d4c 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-003d4d eacf ldi yl,low(stackstart)
-003d4e 83c6 std Z+6, yl
-003d4f e0d8 ldi yh,high(stackstart)
-003d50 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-003d51 e5a9 ldi XL, low(PFA_WARM)
-003d52 e3bd ldi XH, high(PFA_WARM)
- ; its a far jump...
-003d53 cab0 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-003d54 ff04 .dw $ff04
-003d55 6177
-003d56 6d72 .db "warm"
-003d57 3d33 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-003d58 3800 .dw DO_COLON
- PFA_WARM:
- .endif
-003d59 0267 .dw XT_INIT_RAM
-003d5a 383c .dw XT_DOLITERAL
-003d5b 0159 .dw XT_NOOP
-003d5c 383c .dw XT_DOLITERAL
-003d5d 3d2f .dw XT_PAUSE
-003d5e 3dde .dw XT_DEFERSTORE
-003d5f 08b6 .dw XT_LBRACKET
-003d60 3f5b .dw XT_TURNKEY
-003d61 3d06 .dw XT_QUIT ; never returns
-
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-003d62 ff07 .dw $ff07
-003d63 6168
-003d64 646e
-003d65 656c
-003d66 0072 .db "handler",0
-003d67 3d54 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-003d68 3857 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-003d69 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-003d6a ff05 .dw $ff05
-003d6b 6163
-003d6c 6374
-003d6d 0068 .db "catch",0
-003d6e 3d62 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-003d6f 3800 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-003d70 3a8c .dw XT_SP_FETCH
-003d71 38fe .dw XT_TO_R
- ; handler @ >r
-003d72 3d68 .dw XT_HANDLER
-003d73 3878 .dw XT_FETCH
-003d74 38fe .dw XT_TO_R
- ; rp@ handler !
-003d75 3a75 .dw XT_RP_FETCH
-003d76 3d68 .dw XT_HANDLER
-003d77 3880 .dw XT_STORE
-003d78 3829 .dw XT_EXECUTE
- ; r> handler !
-003d79 38f5 .dw XT_R_FROM
-003d7a 3d68 .dw XT_HANDLER
-003d7b 3880 .dw XT_STORE
-003d7c 38f5 .dw XT_R_FROM
-003d7d 38d8 .dw XT_DROP
-003d7e 3953 .dw XT_ZERO
-003d7f 381f .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-003d80 ff05 .dw $ff05
-003d81 6874
-003d82 6f72
-003d83 0077 .db "throw",0
-003d84 3d6a .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-003d85 3800 .dw DO_COLON
- PFA_THROW:
- .endif
-003d86 38b0 .dw XT_DUP
-003d87 3919 .dw XT_ZEROEQUAL
-003d88 3835 .dw XT_DOCONDBRANCH
-003d89 3d8c DEST(PFA_THROW1)
-003d8a 38d8 .dw XT_DROP
-003d8b 381f .dw XT_EXIT
- PFA_THROW1:
-003d8c 3d68 .dw XT_HANDLER
-003d8d 3878 .dw XT_FETCH
-003d8e 3a7f .dw XT_RP_STORE
-003d8f 38f5 .dw XT_R_FROM
-003d90 3d68 .dw XT_HANDLER
-003d91 3880 .dw XT_STORE
-003d92 38f5 .dw XT_R_FROM
-003d93 38c3 .dw XT_SWAP
-003d94 38fe .dw XT_TO_R
-003d95 3a95 .dw XT_SP_STORE
-003d96 38d8 .dw XT_DROP
-003d97 38f5 .dw XT_R_FROM
-003d98 381f .dw XT_EXIT
-
-
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-003d99 ff07 .dw $ff07
-003d9a 6445
-003d9b 6665
-003d9c 7265
-003d9d 0040 .db "Edefer@",0
-003d9e 3d80 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-003d9f 3800 .dw DO_COLON
- PFA_EDEFERFETCH:
-003da0 3bca .dw XT_FETCHI
-003da1 3b5e .dw XT_FETCHE
-003da2 381f .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-003da3 ff07 .dw $ff07
-003da4 6445
-003da5 6665
-003da6 7265
-003da7 0021 .db "Edefer!",0
-003da8 3d99 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-003da9 3800 .dw DO_COLON
- PFA_EDEFERSTORE:
-003daa 3bca .dw XT_FETCHI
-003dab 3b3a .dw XT_STOREE
-003dac 381f .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-003dad ff07 .dw $ff07
-003dae 6452
-003daf 6665
-003db0 7265
-003db1 0040 .db "Rdefer@",0
-003db2 3da3 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-003db3 3800 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-003db4 3bca .dw XT_FETCHI
-003db5 3878 .dw XT_FETCH
-003db6 381f .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-003db7 ff07 .dw $ff07
-003db8 6452
-003db9 6665
-003dba 7265
-003dbb 0021 .db "Rdefer!",0
-003dbc 3dad .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-003dbd 3800 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-003dbe 3bca .dw XT_FETCHI
-003dbf 3880 .dw XT_STORE
-003dc0 381f .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-003dc1 ff07 .dw $ff07
-003dc2 6455
-003dc3 6665
-003dc4 7265
-003dc5 0040 .db "Udefer@",0
-003dc6 3db7 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-003dc7 3800 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-003dc8 3bca .dw XT_FETCHI
-003dc9 3b01 .dw XT_UP_FETCH
-003dca 399c .dw XT_PLUS
-003dcb 3878 .dw XT_FETCH
-003dcc 381f .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-003dcd ff07 .dw $ff07
-003dce 6455
-003dcf 6665
-003dd0 7265
-003dd1 0021 .db "Udefer!",0
-003dd2 3dc1 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-003dd3 3800 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-003dd4 3bca .dw XT_FETCHI
-003dd5 3b01 .dw XT_UP_FETCH
-003dd6 399c .dw XT_PLUS
-003dd7 3880 .dw XT_STORE
-003dd8 381f .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-003dd9 ff06 .dw $ff06
-003dda 6564
-003ddb 6566
-003ddc 2172 .db "defer!"
-003ddd 3dcd .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-003dde 3800 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-003ddf 3fcf .dw XT_TO_BODY
-003de0 38b0 .dw XT_DUP
-003de1 0185 .dw XT_ICELLPLUS
-003de2 0185 .dw XT_ICELLPLUS
-003de3 3bca .dw XT_FETCHI
-003de4 3829 .dw XT_EXECUTE
-003de5 381f .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-003de6 ff06 .dw $ff06
-003de7 6564
-003de8 6566
-003de9 4072 .db "defer@"
-003dea 3dd9 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-003deb 3800 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-003dec 3fcf .dw XT_TO_BODY
-003ded 38b0 .dw XT_DUP
-003dee 0185 .dw XT_ICELLPLUS
-003def 3bca .dw XT_FETCHI
-003df0 3829 .dw XT_EXECUTE
-003df1 381f .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-003df2 ff07 .dw $ff07
-003df3 6428
-003df4 6665
-003df5 7265
-003df6 0029 .db "(defer)", 0
-003df7 3de6 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-003df8 3800 .dw DO_COLON
- PFA_DODEFER:
-003df9 06fe .dw XT_DOCREATE
-003dfa 085e .dw XT_REVEAL
-003dfb 0721 .dw XT_COMPILE
-003dfc 3dfe .dw PFA_DODEFER1
-003dfd 381f .dw XT_EXIT
- PFA_DODEFER1:
-003dfe 940e 0877 call_ DO_DODOES
-003e00 38b0 .dw XT_DUP
-003e01 0185 .dw XT_ICELLPLUS
-003e02 3bca .dw XT_FETCHI
-003e03 3829 .dw XT_EXECUTE
-003e04 3829 .dw XT_EXECUTE
-003e05 381f .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-003e06 ff02 .dw $ff02
-003e07 2e75 .db "u."
-003e08 3df2 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-003e09 3800 .dw DO_COLON
- PFA_UDOT:
- .endif
-003e0a 3953 .dw XT_ZERO
-003e0b 0352 .dw XT_UDDOT
-003e0c 381f .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-003e0d ff03 .dw $ff03
-003e0e 2e75
-003e0f 0072 .db "u.r",0
-003e10 3e06 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-003e11 3800 .dw DO_COLON
- PFA_UDOTR:
- .endif
-003e12 3953 .dw XT_ZERO
-003e13 38c3 .dw XT_SWAP
-003e14 035b .dw XT_UDDOTR
-003e15 381f .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-003e16 ff05 .dw $ff05
-003e17 2f75
-003e18 6f6d
-003e19 0064 .db "u/mod",0
-003e1a 3e0d .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-003e1b 3800 .dw DO_COLON
- PFA_USLASHMOD:
-003e1c 38fe .dw XT_TO_R
-003e1d 3953 .dw XT_ZERO
-003e1e 38f5 .dw XT_R_FROM
-003e1f 39c1 .dw XT_UMSLASHMOD
-003e20 381f .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-003e21 ff06 .dw $ff06
-003e22 656e
-003e23 6167
-003e24 6574 .db "negate"
-003e25 3e16 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-003e26 3800 .dw DO_COLON
- PFA_NEGATE:
-003e27 39fc .dw XT_INVERT
-003e28 3a2e .dw XT_1PLUS
-003e29 381f .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-003e2a ff01 .dw $ff01
-003e2b 002f .db "/",0
-003e2c 3e21 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-003e2d 3800 .dw DO_COLON
- PFA_SLASH:
- .endif
-003e2e 3c48 .dw XT_SLASHMOD
-003e2f 38ef .dw XT_NIP
-003e30 381f .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-003e31 ff03 .dw $ff03
-003e32 6f6d
-003e33 0064 .db "mod",0
-003e34 3e2a .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-003e35 3800 .dw DO_COLON
- PFA_MOD:
- .endif
-003e36 3c48 .dw XT_SLASHMOD
-003e37 38d8 .dw XT_DROP
-003e38 381f .dw XT_EXIT
-
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-003e39 ff03 .dw $ff03
-003e3a 696d
-003e3b 006e .db "min",0
-003e3c 3e31 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-003e3d 3800 .dw DO_COLON
- PFA_MIN:
- .endif
-003e3e 3ec8 .dw XT_2DUP
-003e3f 3977 .dw XT_GREATER
-003e40 3835 .dw XT_DOCONDBRANCH
-003e41 3e43 DEST(PFA_MIN1)
-003e42 38c3 .dw XT_SWAP
- PFA_MIN1:
-003e43 38d8 .dw XT_DROP
-003e44 381f .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-003e45 ff03 .dw $ff03
-003e46 616d
-003e47 0078 .db "max",0
-003e48 3e39 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-003e49 3800 .dw DO_COLON
- PFA_MAX:
-
- .endif
-003e4a 3ec8 .dw XT_2DUP
-003e4b 396d .dw XT_LESS
-003e4c 3835 .dw XT_DOCONDBRANCH
-003e4d 3e4f DEST(PFA_MAX1)
-003e4e 38c3 .dw XT_SWAP
- PFA_MAX1:
-003e4f 38d8 .dw XT_DROP
-003e50 381f .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-003e51 ff06 .dw $ff06
-003e52 6977
-003e53 6874
-003e54 6e69 .db "within"
-003e55 3e45 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-003e56 3800 .dw DO_COLON
- PFA_WITHIN:
- .endif
-003e57 38ce .dw XT_OVER
-003e58 3992 .dw XT_MINUS
-003e59 38fe .dw XT_TO_R
-003e5a 3992 .dw XT_MINUS
-003e5b 38f5 .dw XT_R_FROM
-003e5c 395b .dw XT_ULESS
-003e5d 381f .dw XT_EXIT
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-003e5e ff0d .dw $ff0d
-003e5f 6873
-003e60 776f
-003e61 772d
-003e62 726f
-003e63 6c64
-003e64 7369
-003e65 0074 .db "show-wordlist",0
-003e66 3e51 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-003e67 3800 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-003e68 383c .dw XT_DOLITERAL
-003e69 3e6d .dw XT_SHOWWORD
-003e6a 38c3 .dw XT_SWAP
-003e6b 069f .dw XT_TRAVERSEWORDLIST
-003e6c 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-003e6d 3800 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-003e6e 06ba .dw XT_NAME2STRING
-003e6f 03c8 .dw XT_ITYPE
-003e70 3fad .dw XT_SPACE ; ( -- addr n)
-003e71 394a .dw XT_TRUE
-003e72 381f .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-003e73 ff05 .dw $ff05
-003e74 6f77
-003e75 6472
-003e76 0073 .db "words",0
-003e77 3e5e .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-003e78 3800 .dw DO_COLON
- PFA_WORDS:
- .endif
-003e79 383c .dw XT_DOLITERAL
-003e7a 004c .dw CFG_ORDERLISTLEN+2
-003e7b 3b5e .dw XT_FETCHE
-003e7c 3e67 .dw XT_SHOWWORDLIST
-003e7d 381f .dw XT_EXIT
-
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-003e7e 0002 .dw $0002
-003e7f 222e .db ".",$22
-003e80 3e73 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-003e81 3800 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-003e82 3e89 .dw XT_SQUOTE
-003e83 0721 .dw XT_COMPILE
-003e84 03c8 .dw XT_ITYPE
-003e85 381f .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-003e86 0002 .dw $0002
-003e87 2273 .db "s",$22
-003e88 3e7e .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-003e89 3800 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-003e8a 383c .dw XT_DOLITERAL
-003e8b 0022 .dw 34 ; 0x22
-003e8c 0553 .dw XT_PARSE ; ( -- addr n)
-003e8d 3eb6 .dw XT_STATE
-003e8e 3878 .dw XT_FETCH
-003e8f 3835 .dw XT_DOCONDBRANCH
-003e90 3e92 DEST(PFA_SQUOTE1)
-003e91 074d .dw XT_SLITERAL
- PFA_SQUOTE1:
-003e92 381f .dw XT_EXIT
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-003e93 ff04 .dw $ff04
-003e94 6966
-003e95 6c6c .db "fill"
-003e96 3e86 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-003e97 3800 .dw DO_COLON
- PFA_FILL:
-003e98 38e0 .dw XT_ROT
-003e99 38e0 .dw XT_ROT
-003e9a 38b8
-003e9b 3835 .dw XT_QDUP,XT_DOCONDBRANCH
-003e9c 3ea4 DEST(PFA_FILL2)
-003e9d 3f98 .dw XT_BOUNDS
-003e9e 3a9a .dw XT_DODO
- PFA_FILL1:
-003e9f 38b0 .dw XT_DUP
-003ea0 3aab .dw XT_I
-003ea1 388c .dw XT_CSTORE ; ( -- c c-addr)
-003ea2 3ac8 .dw XT_DOLOOP
-003ea3 3e9f .dw PFA_FILL1
- PFA_FILL2:
-003ea4 38d8 .dw XT_DROP
-003ea5 381f .dw XT_EXIT
-
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-003ea6 ff05 .dw $ff05
-003ea7 5f66
-003ea8 7063
-003ea9 0075 .db "f_cpu",0
-003eaa 3e93 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-003eab 3800 .dw DO_COLON
- PFA_F_CPU:
- .endif
-003eac 383c .dw XT_DOLITERAL
-003ead 2400 .dw (F_CPU % 65536)
-003eae 383c .dw XT_DOLITERAL
-003eaf 00f4 .dw (F_CPU / 65536)
-003eb0 381f .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-003eb1 ff05 .dw $ff05
-003eb2 7473
-003eb3 7461
-003eb4 0065 .db "state",0
-003eb5 3ea6 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-003eb6 3847 .dw PFA_DOVARIABLE
- PFA_STATE:
-003eb7 01c0 .dw ram_state
-
- .dseg
-0001c0 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-003eb8 ff04 .dw $ff04
-003eb9 6162
-003eba 6573 .db "base"
-003ebb 3eb1 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-003ebc 3857 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-003ebd 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-003ebe ff05 .dw $ff05
-003ebf 6563
-003ec0 6c6c
-003ec1 0073 .db "cells",0
-003ec2 3eb8 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-003ec3 3a0b .dw PFA_2STAR
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-003ec4 ff04 .dw $ff04
-003ec5 6432
-003ec6 7075 .db "2dup"
-003ec7 3ebe .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-003ec8 3800 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-003ec9 38ce .dw XT_OVER
-003eca 38ce .dw XT_OVER
-003ecb 381f .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-003ecc ff05 .dw $ff05
-003ecd 6432
-003ece 6f72
-003ecf 0070 .db "2drop",0
-003ed0 3ec4 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-003ed1 3800 .dw DO_COLON
- PFA_2DROP:
- .endif
-003ed2 38d8 .dw XT_DROP
-003ed3 38d8 .dw XT_DROP
-003ed4 381f .dw XT_EXIT
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-003ed5 ff04 .dw $ff04
-003ed6 7574
-003ed7 6b63 .db "tuck"
-003ed8 3ecc .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-003ed9 3800 .dw DO_COLON
- PFA_TUCK:
- .endif
-003eda 38c3 .dw XT_SWAP
-003edb 38ce .dw XT_OVER
-003edc 381f .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-003edd ff03 .dw $ff03
-003ede 693e
-003edf 006e .db ">in",0
-003ee0 3ed5 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-003ee1 3857 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-003ee2 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-003ee3 ff03 .dw $ff03
-003ee4 6170
-003ee5 0064 .db "pad",0
-003ee6 3edd .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-003ee7 3800 .dw DO_COLON
- PFA_PAD:
- .endif
-003ee8 3f22 .dw XT_HERE
-003ee9 383c .dw XT_DOLITERAL
-003eea 0028 .dw 40
-003eeb 399c .dw XT_PLUS
-003eec 381f .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-003eed ff04 .dw $ff04
-003eee 6d65
-003eef 7469 .db "emit"
-003ef0 3ee3 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-003ef1 3dfe .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-003ef2 000e .dw USER_EMIT
-003ef3 3dc7 .dw XT_UDEFERFETCH
-003ef4 3dd3 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-003ef5 ff05 .dw $ff05
-003ef6 6d65
-003ef7 7469
-003ef8 003f .db "emit?",0
-003ef9 3eed .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-003efa 3dfe .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-003efb 0010 .dw USER_EMITQ
-003efc 3dc7 .dw XT_UDEFERFETCH
-003efd 3dd3 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-003efe ff03 .dw $ff03
-003eff 656b
-003f00 0079 .db "key",0
-003f01 3ef5 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-003f02 3dfe .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-003f03 0012 .dw USER_KEY
-003f04 3dc7 .dw XT_UDEFERFETCH
-003f05 3dd3 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-003f06 ff04 .dw $ff04
-003f07 656b
-003f08 3f79 .db "key?"
-003f09 3efe .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-003f0a 3dfe .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-003f0b 0014 .dw USER_KEYQ
-003f0c 3dc7 .dw XT_UDEFERFETCH
-003f0d 3dd3 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-003f0e ff02 .dw $ff02
-003f0f 7064 .db "dp"
-003f10 3f06 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-003f11 386e .dw PFA_DOVALUE1
- PFA_DP:
-003f12 0036 .dw CFG_DP
-003f13 3d9f .dw XT_EDEFERFETCH
-003f14 3da9 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-003f15 ff05 .dw $ff05
-003f16 6865
-003f17 7265
-003f18 0065 .db "ehere",0
-003f19 3f0e .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-003f1a 386e .dw PFA_DOVALUE1
- PFA_EHERE:
-003f1b 003a .dw EE_EHERE
-003f1c 3d9f .dw XT_EDEFERFETCH
-003f1d 3da9 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-003f1e ff04 .dw $ff04
-003f1f 6568
-003f20 6572 .db "here"
-003f21 3f15 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-003f22 386e .dw PFA_DOVALUE1
- PFA_HERE:
-003f23 0038 .dw EE_HERE
-003f24 3d9f .dw XT_EDEFERFETCH
-003f25 3da9 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-003f26 ff05 .dw $ff05
-003f27 6c61
-003f28 6f6c
-003f29 0074 .db "allot",0
-003f2a 3f1e .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-003f2b 3800 .dw DO_COLON
- PFA_ALLOT:
-003f2c 3f22 .dw XT_HERE
-003f2d 399c .dw XT_PLUS
-003f2e 0173 .dw XT_DOTO
-003f2f 3f23 .dw PFA_HERE
-003f30 381f .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-003f31 ff03 .dw $ff03
-003f32 6962
-003f33 006e .db "bin",0
-003f34 3f26 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-003f35 3800 .dw DO_COLON
- PFA_BIN:
- .endif
-003f36 3fea .dw XT_TWO
-003f37 3ebc .dw XT_BASE
-003f38 3880 .dw XT_STORE
-003f39 381f .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-003f3a ff07 .dw $ff07
-003f3b 6564
-003f3c 6963
-003f3d 616d
-003f3e 006c .db "decimal",0
-003f3f 3f31 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-003f40 3800 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-003f41 383c .dw XT_DOLITERAL
-003f42 000a .dw 10
-003f43 3ebc .dw XT_BASE
-003f44 3880 .dw XT_STORE
-003f45 381f .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-003f46 ff03 .dw $ff03
-003f47 6568
-003f48 0078 .db "hex",0
-003f49 3f3a .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-003f4a 3800 .dw DO_COLON
- PFA_HEX:
- .endif
-003f4b 383c .dw XT_DOLITERAL
-003f4c 0010 .dw 16
-003f4d 3ebc .dw XT_BASE
-003f4e 3880 .dw XT_STORE
-003f4f 381f .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-003f50 ff02 .dw $ff02
-003f51 6c62 .db "bl"
-003f52 3f46 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-003f53 3847 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-003f54 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-003f55 ff07 .dw $ff07
-003f56 7574
-003f57 6e72
-003f58 656b
-003f59 0079 .db "turnkey",0
-003f5a 3f50 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-003f5b 3dfe .dw PFA_DODEFER1
- PFA_TURNKEY:
-003f5c 0042 .dw CFG_TURNKEY
-003f5d 3d9f .dw XT_EDEFERFETCH
-003f5e 3da9 .dw XT_EDEFERSTORE
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-003f5f ff07 .dw $ff07
-003f60 6f74
-003f61 7075
-003f62 6570
-003f63 0072 .db "toupper",0
-003f64 3f55 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-003f65 3800 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-003f66 38b0 .dw XT_DUP
-003f67 383c .dw XT_DOLITERAL
-003f68 0061 .dw 'a'
-003f69 383c .dw XT_DOLITERAL
-003f6a 007b .dw 'z'+1
-003f6b 3e56 .dw XT_WITHIN
-003f6c 3835 .dw XT_DOCONDBRANCH
-003f6d 3f71 DEST(PFA_TOUPPER0)
-003f6e 383c .dw XT_DOLITERAL
-003f6f 00df .dw 223 ; inverse of 0x20: 0xdf
-003f70 3a12 .dw XT_AND
- PFA_TOUPPER0:
-003f71 381f .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-003f72 ff07 .dw $ff07
-003f73 6f74
-003f74 6f6c
-003f75 6577
-003f76 0072 .db "tolower",0
-003f77 3f5f .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-003f78 3800 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-003f79 38b0 .dw XT_DUP
-003f7a 383c .dw XT_DOLITERAL
-003f7b 0041 .dw 'A'
-003f7c 383c .dw XT_DOLITERAL
-003f7d 005b .dw 'Z'+1
-003f7e 3e56 .dw XT_WITHIN
-003f7f 3835 .dw XT_DOCONDBRANCH
-003f80 3f84 DEST(PFA_TOLOWER0)
-003f81 383c .dw XT_DOLITERAL
-003f82 0020 .dw 32
-003f83 3a1b .dw XT_OR
- PFA_TOLOWER0:
-003f84 381f .dw XT_EXIT
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-003f85 ff06 .dw $ff06
-003f86 733f
-003f87 6174
-003f88 6b63 .db "?stack"
-003f89 3f72 .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-003f8a 3800 .dw DO_COLON
- PFA_QSTACK:
- .endif
-003f8b 05b2 .dw XT_DEPTH
-003f8c 3920 .dw XT_ZEROLESS
-003f8d 3835 .dw XT_DOCONDBRANCH
-003f8e 3f92 DEST(PFA_QSTACK1)
-003f8f 383c .dw XT_DOLITERAL
-003f90 fffc .dw -4
-003f91 3d85 .dw XT_THROW
- PFA_QSTACK1:
-003f92 381f .dw XT_EXIT
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-003f93 ff06 .dw $ff06
-003f94 6f62
-003f95 6e75
-003f96 7364 .db "bounds"
-003f97 3f85 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-003f98 3800 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-003f99 38ce .dw XT_OVER
-003f9a 399c .dw XT_PLUS
-003f9b 38c3 .dw XT_SWAP
-003f9c 381f .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-003f9d ff02 .dw 0xff02
-003f9e 7263 .db "cr"
-003f9f 3f93 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-003fa0 3800 .dw DO_COLON
- PFA_CR:
- .endif
-
-003fa1 383c .dw XT_DOLITERAL
-003fa2 000d .dw 13
-003fa3 3ef1 .dw XT_EMIT
-003fa4 383c .dw XT_DOLITERAL
-003fa5 000a .dw 10
-003fa6 3ef1 .dw XT_EMIT
-003fa7 381f .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-003fa8 ff05 .dw $ff05
-003fa9 7073
-003faa 6361
-003fab 0065 .db "space",0
-003fac 3f9d .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-003fad 3800 .dw DO_COLON
- PFA_SPACE:
- .endif
-003fae 3f53 .dw XT_BL
-003faf 3ef1 .dw XT_EMIT
-003fb0 381f .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-003fb1 ff06 .dw $ff06
-003fb2 7073
-003fb3 6361
-003fb4 7365 .db "spaces"
-003fb5 3fa8 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-003fb6 3800 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-003fb7 3953
-003fb8 3e49 .DW XT_ZERO, XT_MAX
-003fb9 38b0
-003fba 3835 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-003fbb 3fc0 DEST(SPCS2)
-003fbc 3fad
-003fbd 3a34
-003fbe 382e .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-003fbf 3fb9 DEST(SPCS1)
-003fc0 38d8
-003fc1 381f SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-003fc2 ff03 .dw $ff03
-003fc3 3e73
-003fc4 0064 .db "s>d",0
-003fc5 3fb1 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-003fc6 3800 .dw DO_COLON
- PFA_S2D:
- .endif
-003fc7 38b0 .dw XT_DUP
-003fc8 3920 .dw XT_ZEROLESS
-003fc9 381f .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-003fca ff05 .dw $ff05
-003fcb 623e
-003fcc 646f
-003fcd 0079 .db ">body",0
-003fce 3fc2 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-003fcf 3a2f .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-003fd0 0008 .dw $0008
-003fd1 6c32
-003fd2 7469
-003fd3 7265
-003fd4 6c61 .db "2literal"
-003fd5 3fca .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-003fd6 3800 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-003fd7 38c3 .dw XT_SWAP
-003fd8 0742 .dw XT_LITERAL
-003fd9 0742 .dw XT_LITERAL
-003fda 381f .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-003fdb ff01 .dw $ff01
-003fdc 003d .db "=",0
-003fdd 3fd0 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-003fde 3800 .dw DO_COLON
- PFA_EQUAL:
-003fdf 3992 .dw XT_MINUS
-003fe0 3919 .dw XT_ZEROEQUAL
-003fe1 381f .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-003fe2 ff01 .dw $ff01
-003fe3 0031 .db "1",0
-003fe4 3fdb .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-003fe5 3847 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-003fe6 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-003fe7 ff01 .dw $ff01
-003fe8 0032 .db "2",0
-003fe9 3fe2 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-003fea 3847 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-003feb 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-003fec ff02 .dw $ff02
-003fed 312d .db "-1"
-003fee 3fe7 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-003fef 3847 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-003ff0 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000034 ff ff
- ; some configs
-000036 7f 0a CFG_DP: .dw DPSTART ; Dictionary Pointer
-000038 c2 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00003a 8e 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00003c 93 09 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-00003e 5c 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000040 b0 08 CFG_LP0: .dw stackstart+1
-000042 71 0a CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000044 c4 02 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000046 48 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-000048 ec 3f CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00004a 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00004c 48 00 .dw CFG_FORTHWORDLIST ; get/set-order
-00004e .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00005c 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-00005e 35 06 .dw XT_REC_FIND
-000060 21 06 .dw XT_REC_NUM
-000062 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-000066 7d 3b .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-000068 68 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00006a 00 00 .dw 0 ; USER_STATE
-00006c 00 00 .dw 0 ; USER_FOLLOWER
-00006e ff 08 .dw rstackstart ; USER_RP
-000070 af 08 .dw stackstart ; USER_SP0
-000072 af 08 .dw stackstart ; USER_SP
-
-000074 00 00 .dw 0 ; USER_HANDLER
-000076 0a 00 .dw 10 ; USER_BASE
-
-000078 a3 00 .dw XT_TX ; USER_EMIT
-00007a b1 00 .dw XT_TXQ ; USER_EMITQ
-00007c 78 00 .dw XT_RX ; USER_KEY
-00007e 93 00 .dw XT_RXQ ; USER_KEYQ
-000080 3c 02 .dw XT_SOURCETIB ; USER_SOURCE
-000082 00 00 .dw 0 ; USER_G_IN
-000084 29 02 .dw XT_REFILLTIB ; USER_REFILL
-000086 c8 3c .dw XT_DEFAULT_PROMPTOK
-000088 e7 3c .dw XT_DEFAULT_PROMPTERROR
-00008a d7 3c .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-00008c 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega328P" register use summary:
-r0 : 25 r1 : 5 r2 : 9 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 78 r17: 57 r18: 52 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 187 r25: 133 r26: 28 r27: 17 r28: 7 r29: 4 r30: 78 r31: 40
-x : 4 y : 203 z : 41
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega328P" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 2 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 13 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 0 cbr : 0
-clc : 1 clh : 0 cli : 5 cln : 0 clr : 13 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 14 inc : 3 jmp : 7
-ld : 136 ldd : 4 ldi : 27 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 15 movw : 65 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 1 out : 16 pop : 45
-push : 39 rcall : 38 ret : 6 reti : 1 rjmp : 103 rol : 23
-ror : 5 sbc : 9 sbci : 3 sbi : 3 sbic : 3 sbis : 0
-sbiw : 7 sbr : 0 sbrc : 4 sbrs : 3 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 3 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 74 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 70 out of 113 (61.9%)
-
-"ATmega328P" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x007fe2 1834 11624 13458 32768 41.1%
-[.dseg] 0x000100 0x0001c2 0 194 194 2048 9.5%
-[.eseg] 0x000000 0x00008e 0 142 142 1024 13.9%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/arduino/duemilanove.map b/amforth-6.5/appl/arduino/duemilanove.map
deleted file mode 100644
index 0184ed7..0000000
--- a/amforth-6.5/appl/arduino/duemilanove.map
+++ /dev/null
@@ -1,2021 +0,0 @@
-
-AVRASM ver. 2.1.52 duemilanove.asm Sun Apr 30 20:10:13 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000095
-EQU SIGNATURE_002 0000000f
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK1 0000006c
-EQU PCMSK2 0000006d
-EQU PCMSK0 0000006b
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU WGM11 00000001
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU PSRSYNC 00000000
-EQU TSM 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ACME 00000006
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSR10 00000000
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SELFPRGEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU BODSE 00000005
-EQU BODS 00000006
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU EXTREF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU DWEN 00000006
-EQU RSTDISBL 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00003fff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00000800
-EQU RAMEND 000008ff
-EQU XRAMEND 00000000
-EQU E2END 000003ff
-EQU EEPROMEND 000003ff
-EQU EEADRBITS 0000000a
-EQU NRWW_START_ADDR 00003800
-EQU NRWW_STOP_ADDR 00003fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 000037ff
-EQU PAGESIZE 00000040
-EQU FIRSTBOOTSTART 00003f00
-EQU SECONDBOOTSTART 00003e00
-EQU THIRDBOOTSTART 00003c00
-EQU FOURTHBOOTSTART 00003800
-EQU SMALLBOOTSTART 00003f00
-EQU LARGEBOOTSTART 00003800
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU PCI0addr 00000006
-EQU PCI1addr 00000008
-EQU PCI2addr 0000000a
-EQU WDTaddr 0000000c
-EQU OC2Aaddr 0000000e
-EQU OC2Baddr 00000010
-EQU OVF2addr 00000012
-EQU ICP1addr 00000014
-EQU OC1Aaddr 00000016
-EQU OC1Baddr 00000018
-EQU OVF1addr 0000001a
-EQU OC0Aaddr 0000001c
-EQU OC0Baddr 0000001e
-EQU OVF0addr 00000020
-EQU SPIaddr 00000022
-EQU URXCaddr 00000024
-EQU UDREaddr 00000026
-EQU UTXCaddr 00000028
-EQU ADCCaddr 0000002a
-EQU ERDYaddr 0000002c
-EQU ACIaddr 0000002e
-EQU TWIaddr 00000030
-EQU SPMRaddr 00000032
-EQU INT_VECTORS_SIZE 00000034
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_USART0 00000000
-SET WANT_TWI 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_SPI 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_CPU 00000000
-SET WANT_EEPROM 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 000000dd
-EQU INTVECTORS 0000001a
-EQU SPMEN 00000000
-CSEG mcu_info 00000033
-CSEG mcu_ramsize 00000033
-CSEG mcu_eepromsize 00000034
-CSEG mcu_maxdp 00000035
-CSEG mcu_numints 00000036
-CSEG mcu_name 00000037
-SET codestart 0000003d
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000001
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000008ff
-SET stackstart 000008af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000000a
-SET VE_HEAD 00003fec
-SET VE_ENVHEAD 000002c4
-SET AMFORTH_RO_SEG 00003800
-EQU F_CPU 00f42400
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 0000003d
-CSEG XT_TO_RXBUF 00000043
-CSEG PFA_rx_tobuf 00000044
-CSEG DO_NEXT 00003804
-CSEG VE_ISR_RX 00000054
-CSEG XT_ISR_RX 00000059
-CSEG DO_COLON 00003800
-CSEG usart_rx_isr 0000005a
-CSEG XT_DOLITERAL 0000383c
-CSEG XT_CFETCH 00003897
-CSEG XT_DUP 000038b0
-CSEG XT_EQUAL 00003fde
-CSEG XT_DOCONDBRANCH 00003835
-CSEG usart_rx_isr1 00000064
-CSEG XT_COLD 00003d37
-CSEG XT_EXIT 0000381f
-CSEG XT_USART_INIT_RX_BUFFER 00000066
-CSEG PFA_USART_INIT_RX_BUFFER 00000067
-CSEG XT_INTSTORE 00003ca4
-CSEG XT_ZERO 00003953
-CSEG XT_FILL 00003e97
-CSEG VE_RX_BUFFER 00000073
-CSEG XT_RX_BUFFER 00000078
-CSEG PFA_RX_BUFFER 00000079
-CSEG XT_RXQ_BUFFER 00000093
-CSEG XT_PLUS 0000399c
-CSEG XT_SWAP 000038c3
-CSEG XT_1PLUS 00003a2e
-CSEG XT_AND 00003a12
-CSEG XT_CSTORE 0000388c
-CSEG VE_RXQ_BUFFER 0000008d
-CSEG PFA_RXQ_BUFFER 00000094
-CSEG XT_PAUSE 00003d2f
-CSEG XT_NOTEQUAL 00003912
-SET XT_RX 00000078
-SET XT_RXQ 00000093
-SET XT_USART_INIT_RX 00000066
-CSEG VE_TX_POLL 0000009d
-CSEG XT_TX_POLL 000000a3
-CSEG PFA_TX_POLL 000000a4
-CSEG XT_TXQ_POLL 000000b1
-CSEG VE_TXQ_POLL 000000ab
-CSEG PFA_TXQ_POLL 000000b2
-SET XT_TX 000000a3
-SET XT_TXQ 000000b1
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000ba
-CSEG XT_UBRR 000000be
-CSEG PFA_DOVALUE1 0000386e
-CSEG PFA_UBRR 000000bf
-ESEG EE_UBRRVAL 0000008c
-CSEG XT_EDEFERFETCH 00003d9f
-CSEG XT_EDEFERSTORE 00003da9
-CSEG VE_USART 000000c2
-CSEG XT_USART 000000c7
-CSEG PFA_USART 000000c8
-CSEG XT_BYTESWAP 00003af8
-SET AMFORTH_NRWW_SIZE 00000ffe
-SET corepc 000000dd
-CSEG PFA_COLD 00003d38
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 000000f4
-CSEG XT_MPLUS 000000f7
-CSEG PFA_MPLUS 000000f8
-CSEG XT_S2D 00003fc6
-CSEG XT_DPLUS 00003c14
-CSEG VE_UDSTAR 000000fb
-CSEG XT_UDSTAR 000000ff
-CSEG PFA_UDSTAR 00000100
-CSEG XT_TO_R 000038fe
-CSEG XT_UMSTAR 000039df
-CSEG XT_DROP 000038d8
-CSEG XT_R_FROM 000038f5
-CSEG XT_ROT 000038e0
-CSEG VE_UMAX 0000010a
-CSEG XT_UMAX 0000010e
-CSEG PFA_UMAX 0000010f
-CSEG XT_2DUP 00003ec8
-CSEG XT_ULESS 0000395b
-CSEG UMAX1 00000114
-CSEG VE_UMIN 00000116
-CSEG XT_UMIN 0000011a
-CSEG PFA_UMIN 0000011b
-CSEG XT_UGREATER 00003966
-CSEG UMIN1 00000120
-CSEG XT_IMMEDIATEQ 00000122
-CSEG PFA_IMMEDIATEQ 00000123
-CSEG XT_ZEROEQUAL 00003919
-CSEG IMMEDIATEQ1 0000012b
-CSEG XT_ONE 00003fe5
-CSEG XT_TRUE 0000394a
-CSEG VE_NAME2FLAGS 0000012d
-CSEG XT_NAME2FLAGS 00000134
-CSEG PFA_NAME2FLAGS 00000135
-CSEG XT_FETCHI 00003bca
-CSEG VE_DOT_VER 0000013a
-CSEG XT_DOT_VER 0000013e
-CSEG PFA_DOT_VER 0000013f
-CSEG XT_ENV_FORTHNAME 0000029f
-CSEG XT_ITYPE 000003c8
-CSEG XT_SPACE 00003fad
-CSEG XT_BASE 00003ebc
-CSEG XT_FETCH 00003878
-CSEG XT_ENV_FORTHVERSION 000002ad
-CSEG XT_DECIMAL 00003f40
-CSEG XT_L_SHARP 000002e6
-CSEG XT_SHARP 000002ee
-CSEG XT_HOLD 000002d7
-CSEG XT_SHARP_S 00000304
-CSEG XT_SHARP_G 0000030f
-CSEG XT_TYPE 000003fe
-CSEG XT_STORE 00003880
-CSEG XT_ENV_CPU 000002b5
-CSEG VE_NOOP 00000155
-CSEG XT_NOOP 00000159
-CSEG PFA_NOOP 0000015a
-CSEG VE_UNUSED 0000015b
-CSEG XT_UNUSED 00000160
-CSEG PFA_UNUSED 00000161
-CSEG XT_SP_FETCH 00003a8c
-CSEG XT_HERE 00003f22
-CSEG XT_MINUS 00003992
-CSEG VE_TO 00000165
-CSEG XT_TO 00000168
-CSEG PFA_TO 00000169
-CSEG XT_TICK 0000040d
-CSEG XT_TO_BODY 00003fcf
-CSEG XT_STATE 00003eb6
-CSEG PFA_TO1 00000179
-CSEG XT_COMPILE 00000721
-CSEG XT_DOTO 00000173
-CSEG XT_COMMA 0000072c
-CSEG PFA_DOTO 00000174
-CSEG XT_ICELLPLUS 00000185
-CSEG XT_EXECUTE 00003829
-CSEG VE_ICELLPLUS 0000017f
-CSEG PFA_ICELLPLUS 00000186
-CSEG VE_ICOMPARE 00000188
-CSEG XT_ICOMPARE 0000018e
-CSEG PFA_ICOMPARE 0000018f
-CSEG XT_OVER 000038ce
-CSEG PFA_ICOMPARE_SAMELEN 00000199
-CSEG XT_2DROP 00003ed1
-CSEG XT_QDOCHECK 000007eb
-CSEG PFA_ICOMPARE_DONE 000001be
-CSEG XT_DODO 00003a9a
-CSEG PFA_ICOMPARE_LOOP 0000019f
-CSEG XT_ICOMPARE_LC 000001c1
-CSEG PFA_ICOMPARE_LASTCELL 000001af
-CSEG PFA_ICOMPARE_NEXTLOOP 000001b6
-CSEG XT_UNLOOP 00003ad3
-CSEG XT_CELLPLUS 00003c8f
-CSEG XT_DOPLUSLOOP 00003ab9
-CSEG PFA_ICOMPARE_LC 000001c2
-CSEG XT_TOLOWER 00003f78
-CSEG XT_OR 00003a1b
-CSEG VE_STAR 000001d0
-CSEG XT_STAR 000001d3
-CSEG PFA_STAR 000001d4
-CSEG XT_MSTAR 000039a5
-CSEG VE_J 000001d7
-CSEG XT_J 000001da
-CSEG PFA_J 000001db
-CSEG XT_RP_FETCH 00003a75
-CSEG VE_DABS 000001e7
-CSEG XT_DABS 000001eb
-CSEG PFA_DABS 000001ec
-CSEG XT_ZEROLESS 00003920
-CSEG PFA_DABS1 000001f1
-CSEG XT_DNEGATE 000001f8
-CSEG VE_DNEGATE 000001f2
-CSEG PFA_DNEGATE 000001f9
-CSEG XT_DINVERT 00003c3a
-CSEG VE_CMOVE 000001fe
-CSEG XT_CMOVE 00000203
-CSEG PFA_CMOVE 00000204
-CSEG PFA_CMOVE1 00000211
-CSEG PFA_CMOVE2 0000020d
-CSEG VE_2SWAP 00000217
-CSEG XT_2SWAP 0000021c
-CSEG PFA_2SWAP 0000021d
-CSEG VE_REFILLTIB 00000222
-CSEG XT_REFILLTIB 00000229
-CSEG PFA_REFILLTIB 0000022a
-CSEG XT_TIB 00000245
-CSEG XT_ACCEPT 0000045d
-CSEG XT_NUMBERTIB 0000024b
-CSEG XT_TO_IN 00003ee1
-CSEG VE_SOURCETIB 00000235
-CSEG XT_SOURCETIB 0000023c
-CSEG PFA_SOURCETIB 0000023d
-CSEG VE_TIB 00000241
-CSEG PFA_DOVARIABLE 00003847
-CSEG PFA_TIB 00000246
-DSEG ram_tib 0000012c
-CSEG VE_NUMBERTIB 00000247
-CSEG PFA_NUMBERTIB 0000024c
-DSEG ram_sharptib 00000186
-CSEG VE_EE2RAM 0000024d
-CSEG XT_EE2RAM 00000252
-CSEG PFA_EE2RAM 00000253
-CSEG PFA_EE2RAM_1 00000255
-CSEG XT_FETCHE 00003b5e
-CSEG XT_DOLOOP 00003ac8
-CSEG PFA_EE2RAM_2 0000025f
-CSEG VE_INIT_RAM 00000261
-CSEG XT_INIT_RAM 00000267
-CSEG PFA_INI_RAM 00000268
-ESEG EE_INITUSER 0000006a
-CSEG XT_UP_FETCH 00003b01
-CSEG XT_2SLASH 00003a03
-CSEG VE_ENVIRONMENT 00000270
-CSEG XT_ENVIRONMENT 00000278
-CSEG PFA_ENVIRONMENT 00000279
-ESEG CFG_ENVIRONMENT 00000044
-CSEG VE_ENVWORDLISTS 0000027a
-CSEG XT_ENVWORDLISTS 00000281
-CSEG PFA_ENVWORDLISTS 00000282
-CSEG VE_ENVSLASHPAD 00000285
-CSEG XT_ENVSLASHPAD 00000289
-CSEG PFA_ENVSLASHPAD 0000028a
-CSEG XT_PAD 00003ee7
-CSEG VE_ENVSLASHHOLD 0000028e
-CSEG XT_ENVSLASHHOLD 00000293
-CSEG PFA_ENVSLASHHOLD 00000294
-CSEG VE_ENV_FORTHNAME 00000298
-CSEG PFA_EN_FORTHNAME 000002a0
-CSEG XT_DOSLITERAL 00000395
-CSEG VE_ENV_FORTHVERSION 000002a7
-CSEG PFA_EN_FORTHVERSION 000002ae
-CSEG VE_ENV_CPU 000002b1
-CSEG PFA_EN_CPU 000002b6
-CSEG XT_ICOUNT 000003f4
-CSEG VE_ENV_MCUINFO 000002ba
-CSEG XT_ENV_MCUINFO 000002c0
-CSEG PFA_EN_MCUINFO 000002c1
-CSEG VE_ENVUSERSIZE 000002c4
-CSEG XT_ENVUSERSIZE 000002c9
-CSEG PFA_ENVUSERSIZE 000002ca
-CSEG VE_HLD 000002cd
-CSEG XT_HLD 000002d1
-CSEG PFA_HLD 000002d2
-DSEG ram_hld 00000188
-CSEG VE_HOLD 000002d3
-CSEG PFA_HOLD 000002d8
-CSEG XT_1MINUS 00003a34
-CSEG VE_L_SHARP 000002e3
-CSEG PFA_L_SHARP 000002e7
-CSEG VE_SHARP 000002eb
-CSEG PFA_SHARP 000002ef
-CSEG XT_UDSLASHMOD 0000036b
-CSEG XT_LESS 0000396d
-CSEG PFA_SHARP1 000002fc
-CSEG VE_SHARP_S 00000301
-CSEG PFA_SHARP_S 00000305
-CSEG NUMS1 00000305
-CSEG VE_SHARP_G 0000030c
-CSEG PFA_SHARP_G 00000310
-CSEG VE_SIGN 00000317
-CSEG XT_SIGN 0000031b
-CSEG PFA_SIGN 0000031c
-CSEG PFA_SIGN1 00000322
-CSEG VE_DDOTR 00000323
-CSEG XT_DDOTR 00000327
-CSEG PFA_DDOTR 00000328
-CSEG XT_TUCK 00003ed9
-CSEG XT_SPACES 00003fb6
-CSEG VE_DOTR 00000336
-CSEG XT_DOTR 00000339
-CSEG PFA_DOTR 0000033a
-CSEG VE_DDOT 0000033f
-CSEG XT_DDOT 00000342
-CSEG PFA_DDOT 00000343
-CSEG VE_DOT 00000347
-CSEG XT_DOT 0000034a
-CSEG PFA_DOT 0000034b
-CSEG VE_UDDOT 0000034e
-CSEG XT_UDDOT 00000352
-CSEG PFA_UDDOT 00000353
-CSEG XT_UDDOTR 0000035b
-CSEG VE_UDDOTR 00000357
-CSEG PFA_UDDOTR 0000035c
-CSEG VE_UDSLASHMOD 00000366
-CSEG PFA_UDSLASHMOD 0000036c
-CSEG XT_R_FETCH 00003907
-CSEG XT_UMSLASHMOD 000039c1
-CSEG VE_DIGITQ 00000376
-CSEG XT_DIGITQ 0000037b
-CSEG PFA_DIGITQ 0000037c
-CSEG XT_TOUPPER 00003f65
-CSEG XT_GREATER 00003977
-CSEG PFA_DOSLITERAL 00000396
-CSEG VE_SCOMMA 000003a0
-CSEG XT_SCOMMA 000003a3
-CSEG PFA_SCOMMA 000003a4
-CSEG XT_DOSCOMMA 000003a7
-CSEG PFA_DOSCOMMA 000003a8
-CSEG XT_2STAR 00003a0a
-CSEG PFA_SCOMMA2 000003ba
-CSEG PFA_SCOMMA1 000003b4
-CSEG XT_GREATERZERO 00003927
-CSEG PFA_SCOMMA3 000003c1
-CSEG VE_ITYPE 000003c3
-CSEG PFA_ITYPE 000003c9
-CSEG PFA_ITYPE2 000003dc
-CSEG PFA_ITYPE1 000003d4
-CSEG XT_LOWEMIT 000003e9
-CSEG XT_HIEMIT 000003e5
-CSEG PFA_ITYPE3 000003e3
-CSEG PFA_HIEMIT 000003e6
-CSEG PFA_LOWEMIT 000003ea
-CSEG XT_EMIT 00003ef1
-CSEG VE_ICOUNT 000003ef
-CSEG PFA_ICOUNT 000003f5
-CSEG VE_TYPE 000003fa
-CSEG PFA_TYPE 000003ff
-CSEG XT_BOUNDS 00003f98
-CSEG PFA_TYPE2 00000409
-CSEG PFA_TYPE1 00000404
-CSEG XT_I 00003aab
-CSEG VE_TICK 0000040a
-CSEG PFA_TICK 0000040e
-CSEG XT_PARSENAME 00000580
-CSEG XT_FORTHRECOGNIZER 000005c3
-CSEG XT_RECOGNIZE 000005ce
-CSEG XT_DT_NULL 0000065b
-CSEG PFA_TICK1 0000041f
-CSEG XT_THROW 00003d85
-CSEG VE_CSKIP 00000421
-CSEG XT_CSKIP 00000426
-CSEG PFA_CSKIP 00000427
-CSEG PFA_CSKIP1 00000428
-CSEG PFA_CSKIP2 00000435
-CSEG XT_SLASHSTRING 00000571
-CSEG XT_DOBRANCH 0000382e
-CSEG VE_CSCAN 00000438
-CSEG XT_CSCAN 0000043d
-CSEG PFA_CSCAN 0000043e
-CSEG PFA_CSCAN1 00000440
-CSEG PFA_CSCAN2 00000452
-CSEG XT_NIP 000038ef
-CSEG VE_ACCEPT 00000458
-CSEG PFA_ACCEPT 0000045e
-CSEG ACC1 00000462
-CSEG XT_KEY 00003f02
-CSEG XT_CRLFQ 0000049e
-CSEG ACC5 00000490
-CSEG ACC3 00000480
-CSEG ACC6 0000047e
-CSEG XT_BS 00000496
-CSEG ACC4 0000048e
-CSEG XT_BL 00003f53
-CSEG PFA_ACCEPT6 00000487
-CSEG XT_CR 00003fa0
-CSEG VE_REFILL 000004a9
-CSEG XT_REFILL 000004ae
-CSEG PFA_DODEFER1 00003dfe
-CSEG PFA_REFILL 000004af
-CSEG XT_UDEFERFETCH 00003dc7
-CSEG XT_UDEFERSTORE 00003dd3
-CSEG VE_CHAR 000004b2
-CSEG XT_CHAR 000004b6
-CSEG PFA_CHAR 000004b7
-CSEG VE_NUMBER 000004bb
-CSEG XT_NUMBER 000004c0
-CSEG PFA_NUMBER 000004c1
-CSEG XT_QSIGN 00000504
-CSEG XT_SET_BASE 00000517
-CSEG PFA_NUMBER0 000004d7
-CSEG XT_2TO_R 00003b1d
-CSEG XT_2R_FROM 00003b2c
-CSEG XT_TO_NUMBER 00000535
-CSEG XT_QDUP 000038b8
-CSEG PFA_NUMBER1 000004f9
-CSEG PFA_NUMBER2 000004f0
-CSEG PFA_NUMBER6 000004f1
-CSEG PFA_NUMBER3 000004ed
-CSEG XT_TWO 00003fea
-CSEG PFA_NUMBER5 000004ff
-CSEG PFA_NUMBER4 000004fe
-CSEG XT_NEGATE 00003e26
-CSEG PFA_QSIGN 00000505
-CSEG PFA_NUMBERSIGN_DONE 00000510
-CSEG XT_BASES 00000512
-CSEG PFA_DOCONSTANT 00003851
-CSEG PFA_SET_BASE 00000518
-CSEG XT_WITHIN 00003e56
-CSEG SET_BASE1 0000052d
-CSEG SET_BASE2 0000052e
-CSEG VE_TO_NUMBER 0000052f
-CSEG TONUM1 00000536
-CSEG TONUM3 0000054d
-CSEG TONUM2 00000541
-CSEG VE_PARSE 0000054e
-CSEG XT_PARSE 00000553
-CSEG PFA_PARSE 00000554
-CSEG XT_SOURCE 00000567
-CSEG XT_PLUSSTORE 00003a64
-CSEG VE_SOURCE 00000562
-CSEG PFA_SOURCE 00000568
-CSEG VE_SLASHSTRING 0000056b
-CSEG PFA_SLASHSTRING 00000572
-CSEG VE_PARSENAME 00000579
-CSEG PFA_PARSENAME 00000581
-CSEG XT_SKIPSCANCHAR 00000584
-CSEG PFA_SKIPSCANCHAR 00000585
-CSEG VE_SP0 00000596
-CSEG XT_SP0 0000059a
-CSEG PFA_SP0 0000059b
-CSEG VE_SP 0000059e
-CSEG XT_SP 000005a1
-CSEG PFA_DOUSER 00003857
-CSEG PFA_SP 000005a2
-CSEG VE_RP0 000005a3
-CSEG XT_RP0 000005a7
-CSEG PFA_RP0 000005a8
-CSEG XT_DORP0 000005ab
-CSEG PFA_DORP0 000005ac
-CSEG VE_DEPTH 000005ad
-CSEG XT_DEPTH 000005b2
-CSEG PFA_DEPTH 000005b3
-CSEG VE_FORTHRECOGNIZER 000005b9
-CSEG PFA_FORTHRECOGNIZER 000005c4
-ESEG CFG_FORTHRECOGNIZER 0000003e
-CSEG VE_RECOGNIZE 000005c7
-CSEG PFA_RECOGNIZE 000005cf
-CSEG XT_RECOGNIZE_A 000005d9
-CSEG XT_MAPSTACK 0000096c
-CSEG PFA_RECOGNIZE1 000005d8
-CSEG PFA_RECOGNIZE_A 000005da
-CSEG PFA_RECOGNIZE_A1 000005ea
-CSEG VE_INTERPRET 000005ee
-CSEG XT_INTERPRET 000005f5
-CSEG PFA_INTERPRET 000005f6
-CSEG PFA_INTERPRET2 00000606
-CSEG PFA_INTERPRET1 00000601
-CSEG XT_QSTACK 00003f8a
-CSEG VE_DT_NUM 00000608
-CSEG XT_DT_NUM 0000060d
-CSEG PFA_DT_NUM 0000060e
-CSEG XT_LITERAL 00000742
-CSEG VE_DT_DNUM 00000611
-CSEG XT_DT_DNUM 00000617
-CSEG PFA_DT_DNUM 00000618
-CSEG XT_2LITERAL 00003fd6
-CSEG VE_REC_NUM 0000061b
-CSEG XT_REC_NUM 00000621
-CSEG PFA_REC_NUM 00000622
-CSEG PFA_REC_NONUMBER 0000062d
-CSEG PFA_REC_INTNUM2 0000062b
-CSEG VE_REC_FIND 0000062f
-CSEG XT_REC_FIND 00000635
-CSEG PFA_REC_FIND 00000636
-CSEG XT_FINDXT 000006d0
-CSEG PFA_REC_WORD_FOUND 0000063e
-CSEG XT_DT_XT 00000645
-CSEG VE_DT_XT 00000640
-CSEG PFA_DT_XT 00000646
-CSEG XT_R_WORD_INTERPRET 00000649
-CSEG XT_R_WORD_COMPILE 0000064d
-CSEG PFA_R_WORD_INTERPRET 0000064a
-CSEG PFA_R_WORD_COMPILE 0000064e
-CSEG PFA_R_WORD_COMPILE1 00000653
-CSEG VE_DT_NULL 00000655
-CSEG PFA_DT_NULL 0000065c
-CSEG XT_FAIL 0000065f
-CSEG PFA_FAIL 00000660
-CSEG VE_SEARCH_WORDLIST 00000663
-CSEG XT_SEARCH_WORDLIST 0000066d
-CSEG PFA_SEARCH_WORDLIST 0000066e
-CSEG XT_ISWORD 00000682
-CSEG XT_TRAVERSEWORDLIST 0000069f
-CSEG PFA_SEARCH_WORDLIST1 0000067c
-CSEG XT_NFA2CFA 000006c6
-CSEG PFA_ISWORD 00000683
-CSEG XT_NAME2STRING 000006ba
-CSEG PFA_ISWORD3 00000690
-CSEG VE_TRAVERSEWORDLIST 00000694
-CSEG PFA_TRAVERSEWORDLIST 000006a0
-CSEG PFA_TRAVERSEWORDLIST1 000006a1
-CSEG PFA_TRAVERSEWORDLIST2 000006b0
-CSEG XT_NFA2LFA 000009db
-CSEG VE_NAME2STRING 000006b2
-CSEG PFA_NAME2STRING 000006bb
-CSEG VE_NFA2CFA 000006c0
-CSEG PFA_NFA2CFA 000006c7
-CSEG VE_FINDXT 000006ca
-CSEG PFA_FINDXT 000006d1
-CSEG XT_FINDXTA 000006dc
-ESEG CFG_ORDERLISTLEN 0000004a
-CSEG PFA_FINDXT1 000006db
-CSEG PFA_FINDXTA 000006dd
-CSEG PFA_FINDXTA1 000006e9
-CSEG VE_NEWEST 000006ea
-CSEG XT_NEWEST 000006ef
-CSEG PFA_NEWEST 000006f0
-DSEG ram_newest 0000018a
-CSEG VE_LATEST 000006f1
-CSEG XT_LATEST 000006f6
-CSEG PFA_LATEST 000006f7
-DSEG ram_latest 0000018e
-CSEG VE_DOCREATE 000006f8
-CSEG XT_DOCREATE 000006fe
-CSEG PFA_DOCREATE 000006ff
-CSEG XT_WLSCOPE 00000855
-CSEG XT_HEADER 0000083a
-CSEG VE_BACKSLASH 00000709
-CSEG XT_BACKSLASH 0000070c
-CSEG PFA_BACKSLASH 0000070d
-CSEG VE_LPAREN 00000712
-CSEG XT_LPAREN 00000715
-CSEG PFA_LPAREN 00000716
-CSEG VE_COMPILE 0000071b
-CSEG PFA_COMPILE 00000722
-CSEG VE_COMMA 00000729
-CSEG PFA_COMMA 0000072d
-CSEG XT_DP 00003f11
-CSEG XT_STOREI 00003b72
-CSEG PFA_DP 00003f12
-CSEG VE_BRACKETTICK 00000734
-CSEG XT_BRACKETTICK 00000738
-CSEG PFA_BRACKETTICK 00000739
-CSEG VE_LITERAL 0000073c
-CSEG PFA_LITERAL 00000743
-CSEG VE_SLITERAL 00000747
-CSEG XT_SLITERAL 0000074d
-CSEG PFA_SLITERAL 0000074e
-CSEG XT_GMARK 00000752
-CSEG PFA_GMARK 00000753
-CSEG XT_GRESOLVE 00000757
-CSEG PFA_GRESOLVE 00000758
-CSEG XT_LMARK 0000075d
-CSEG PFA_LMARK 0000075e
-CSEG XT_LRESOLVE 00000760
-CSEG PFA_LRESOLVE 00000761
-CSEG VE_AHEAD 00000764
-CSEG XT_AHEAD 00000769
-CSEG PFA_AHEAD 0000076a
-CSEG VE_IF 0000076e
-CSEG XT_IF 00000771
-CSEG PFA_IF 00000772
-CSEG VE_ELSE 00000776
-CSEG XT_ELSE 0000077a
-CSEG PFA_ELSE 0000077b
-CSEG VE_THEN 00000781
-CSEG XT_THEN 00000785
-CSEG PFA_THEN 00000786
-CSEG VE_BEGIN 00000788
-CSEG XT_BEGIN 0000078d
-CSEG PFA_BEGIN 0000078e
-CSEG VE_WHILE 00000790
-CSEG XT_WHILE 00000795
-CSEG PFA_WHILE 00000796
-CSEG VE_REPEAT 00000799
-CSEG XT_REPEAT 0000079e
-CSEG PFA_REPEAT 0000079f
-CSEG XT_AGAIN 000007b2
-CSEG VE_UNTIL 000007a2
-CSEG XT_UNTIL 000007a7
-CSEG PFA_UNTIL 000007a8
-CSEG VE_AGAIN 000007ad
-CSEG PFA_AGAIN 000007b3
-CSEG VE_DO 000007b7
-CSEG XT_DO 000007ba
-CSEG PFA_DO 000007bb
-CSEG XT_TO_L 00000815
-CSEG VE_LOOP 000007c1
-CSEG XT_LOOP 000007c5
-CSEG PFA_LOOP 000007c6
-CSEG XT_ENDLOOP 000007fc
-CSEG VE_PLUSLOOP 000007ca
-CSEG XT_PLUSLOOP 000007cf
-CSEG PFA_PLUSLOOP 000007d0
-CSEG VE_LEAVE 000007d4
-CSEG XT_LEAVE 000007d9
-CSEG PFA_LEAVE 000007da
-CSEG VE_QDO 000007df
-CSEG XT_QDO 000007e3
-CSEG PFA_QDO 000007e4
-CSEG PFA_QDOCHECK 000007ec
-CSEG PFA_QDOCHECK1 000007f3
-CSEG XT_INVERT 000039fc
-CSEG VE_ENDLOOP 000007f6
-CSEG PFA_ENDLOOP 000007fd
-CSEG LOOP1 000007fe
-CSEG XT_L_FROM 00000809
-CSEG LOOP2 00000805
-CSEG VE_L_FROM 00000806
-CSEG PFA_L_FROM 0000080a
-CSEG XT_LP 00000828
-CSEG VE_TO_L 00000812
-CSEG PFA_TO_L 00000816
-CSEG VE_LP0 0000081d
-CSEG XT_LP0 00000821
-CSEG PFA_LP0 00000822
-ESEG CFG_LP0 00000040
-CSEG VE_LP 00000825
-CSEG PFA_LP 00000829
-DSEG ram_lp 00000190
-CSEG VE_CREATE 0000082a
-CSEG XT_CREATE 0000082f
-CSEG PFA_CREATE 00000830
-CSEG XT_REVEAL 0000085e
-CSEG VE_HEADER 00000835
-CSEG PFA_HEADER 0000083b
-CSEG PFA_HEADER1 0000084c
-CSEG VE_WLSCOPE 0000084f
-CSEG PFA_WLSCOPE 00000856
-ESEG CFG_WLSCOPE 0000003c
-CSEG VE_REVEAL 00000859
-CSEG PFA_REVEAL 0000085f
-CSEG REVEAL1 00000869
-CSEG XT_STOREE 00003b3a
-CSEG VE_DOES 0000086a
-CSEG XT_DOES 0000086f
-CSEG PFA_DOES 00000870
-CSEG XT_DODOES 00000882
-CSEG DO_DODOES 00000877
-CSEG PFA_DODOES 00000883
-CSEG VE_COLON 0000088b
-CSEG XT_COLON 0000088e
-CSEG PFA_COLON 0000088f
-CSEG XT_COLONNONAME 00000899
-CSEG VE_COLONNONAME 00000893
-CSEG PFA_COLONNONAME 0000089a
-CSEG XT_RBRACKET 000008ae
-CSEG VE_SEMICOLON 000008a2
-CSEG XT_SEMICOLON 000008a5
-CSEG PFA_SEMICOLON 000008a6
-CSEG XT_LBRACKET 000008b6
-CSEG VE_RBRACKET 000008ab
-CSEG PFA_RBRACKET 000008af
-CSEG VE_LBRACKET 000008b3
-CSEG PFA_LBRACKET 000008b7
-CSEG VE_VARIABLE 000008bb
-CSEG XT_VARIABLE 000008c1
-CSEG PFA_VARIABLE 000008c2
-CSEG XT_CONSTANT 000008cd
-CSEG XT_ALLOT 00003f2b
-CSEG VE_CONSTANT 000008c7
-CSEG PFA_CONSTANT 000008ce
-CSEG VE_USER 000008d4
-CSEG XT_USER 000008d8
-CSEG PFA_USER 000008d9
-CSEG VE_RECURSE 000008df
-CSEG XT_RECURSE 000008e5
-CSEG PFA_RECURSE 000008e6
-CSEG VE_IMMEDIATE 000008ea
-CSEG XT_IMMEDIATE 000008f1
-CSEG PFA_IMMEDIATE 000008f2
-CSEG XT_GET_CURRENT 00000993
-CSEG VE_BRACKETCHAR 000008fc
-CSEG XT_BRACKETCHAR 00000901
-CSEG PFA_BRACKETCHAR 00000902
-CSEG VE_ABORTQUOTE 00000907
-CSEG XT_ABORTQUOTE 0000090c
-CSEG PFA_ABORTQUOTE 0000090d
-CSEG XT_SQUOTE 00003e89
-CSEG XT_QABORT 0000091e
-CSEG VE_ABORT 00000911
-CSEG XT_ABORT 00000916
-CSEG PFA_ABORT 00000917
-CSEG VE_QABORT 00000919
-CSEG PFA_QABORT 0000091f
-CSEG QABO1 00000924
-CSEG VE_GET_STACK 00000926
-CSEG XT_GET_STACK 0000092d
-CSEG PFA_N_FETCH_E2 00000944
-CSEG PFA_N_FETCH_E1 0000093a
-CSEG XT_CELLS 00003ec3
-CSEG VE_SET_STACK 00000947
-CSEG XT_SET_STACK 0000094e
-CSEG PFA_SET_STACK 0000094f
-CSEG PFA_SET_STACK0 00000956
-CSEG PFA_SET_STACK2 00000963
-CSEG PFA_SET_STACK1 0000095e
-CSEG VE_MAPSTACK 00000965
-CSEG PFA_MAPSTACK 0000096d
-CSEG PFA_MAPSTACK3 00000988
-CSEG PFA_MAPSTACK1 00000977
-CSEG PFA_MAPSTACK2 00000984
-CSEG VE_GET_CURRENT 0000098b
-CSEG PFA_GET_CURRENT 00000994
-ESEG CFG_CURRENT 00000046
-CSEG VE_GET_ORDER 00000998
-CSEG XT_GET_ORDER 0000099f
-CSEG PFA_GET_ORDER 000009a0
-CSEG VE_CFG_ORDER 000009a4
-CSEG XT_CFG_ORDER 000009ab
-CSEG PFA_CFG_ORDER 000009ac
-CSEG VE_COMPARE 000009ad
-CSEG XT_COMPARE 000009b3
-CSEG PFA_COMPARE 000009b4
-CSEG PFA_COMPARE_LOOP 000009c0
-CSEG PFA_COMPARE_NOTEQUAL 000009ce
-CSEG PFA_COMPARE_ENDREACHED2 000009c9
-CSEG PFA_COMPARE_ENDREACHED 000009ca
-CSEG PFA_COMPARE_CHECKLASTCHAR 000009ce
-CSEG PFA_COMPARE_DONE 000009d0
-CSEG VE_NFA2LFA 000009d5
-CSEG PFA_NFA2LFA 000009dc
-CSEG VE_SET_CURRENT 000009e1
-CSEG XT_SET_CURRENT 000009e9
-CSEG PFA_SET_CURRENT 000009ea
-CSEG VE_WORDLIST 000009ee
-CSEG XT_WORDLIST 000009f4
-CSEG PFA_WORDLIST 000009f5
-CSEG XT_EHERE 00003f1a
-CSEG PFA_EHERE 00003f1b
-CSEG VE_FORTHWORDLIST 000009fe
-CSEG XT_FORTHWORDLIST 00000a07
-CSEG PFA_FORTHWORDLIST 00000a08
-ESEG CFG_FORTHWORDLIST 00000048
-CSEG VE_SET_ORDER 00000a09
-CSEG XT_SET_ORDER 00000a10
-CSEG PFA_SET_ORDER 00000a11
-CSEG VE_SET_RECOGNIZERS 00000a15
-CSEG XT_SET_RECOGNIZERS 00000a1f
-CSEG PFA_SET_RECOGNIZERS 00000a20
-ESEG CFG_RECOGNIZERLISTLEN 0000005c
-CSEG VE_GET_RECOGNIZERS 00000a24
-CSEG XT_GET_RECOGNIZERS 00000a2e
-CSEG PFA_GET_RECOGNIZERS 00000a2f
-CSEG VE_CODE 00000a33
-CSEG XT_CODE 00000a37
-CSEG PFA_CODE 00000a38
-CSEG VE_ENDCODE 00000a3e
-CSEG XT_ENDCODE 00000a44
-CSEG PFA_ENDCODE 00000a45
-CSEG VE_MARKER 00000a4a
-CSEG XT_MARKER 00000a50
-CSEG PFA_MARKER 00000a51
-ESEG EE_MARKER 00000068
-CSEG VE_POSTPONE 00000a54
-CSEG XT_POSTPONE 00000a5a
-CSEG PFA_POSTPONE 00000a5b
-CSEG VE_APPLTURNKEY 00000a69
-CSEG XT_APPLTURNKEY 00000a71
-CSEG PFA_APPLTURNKEY 00000a72
-CSEG XT_INTON 00003c96
-SET DPSTART 00000a7f
-CSEG DO_INTERRUPT 00003813
-CSEG DO_EXECUTE 0000380c
-CSEG XT_ISREXEC 00003cbf
-CSEG VE_EXIT 0000381b
-CSEG PFA_EXIT 00003820
-CSEG VE_EXECUTE 00003823
-CSEG PFA_EXECUTE 0000382a
-CSEG PFA_DOBRANCH 0000382f
-CSEG PFA_DOCONDBRANCH 00003836
-CSEG PFA_DOLITERAL 0000383d
-CSEG XT_DOVARIABLE 00003846
-CSEG XT_DOCONSTANT 00003850
-CSEG XT_DOUSER 00003856
-CSEG VE_DOVALUE 00003862
-CSEG XT_DOVALUE 00003868
-CSEG PFA_DOVALUE 00003869
-CSEG VE_FETCH 00003875
-CSEG PFA_FETCH 00003879
-CSEG PFA_FETCHRAM 00003879
-CSEG VE_STORE 0000387d
-CSEG PFA_STORE 00003881
-CSEG PFA_STORERAM 00003881
-CSEG VE_CSTORE 00003889
-CSEG PFA_CSTORE 0000388d
-CSEG VE_CFETCH 00003894
-CSEG PFA_CFETCH 00003898
-CSEG VE_FETCHU 0000389c
-CSEG XT_FETCHU 0000389f
-CSEG PFA_FETCHU 000038a0
-CSEG VE_STOREU 000038a4
-CSEG XT_STOREU 000038a7
-CSEG PFA_STOREU 000038a8
-CSEG VE_DUP 000038ac
-CSEG PFA_DUP 000038b1
-CSEG VE_QDUP 000038b4
-CSEG PFA_QDUP 000038b9
-CSEG PFA_QDUP1 000038be
-CSEG VE_SWAP 000038bf
-CSEG PFA_SWAP 000038c4
-CSEG VE_OVER 000038ca
-CSEG PFA_OVER 000038cf
-CSEG VE_DROP 000038d4
-CSEG PFA_DROP 000038d9
-CSEG VE_ROT 000038dc
-CSEG PFA_ROT 000038e1
-CSEG VE_NIP 000038eb
-CSEG PFA_NIP 000038f0
-CSEG VE_R_FROM 000038f2
-CSEG PFA_R_FROM 000038f6
-CSEG VE_TO_R 000038fb
-CSEG PFA_TO_R 000038ff
-CSEG VE_R_FETCH 00003904
-CSEG PFA_R_FETCH 00003908
-CSEG VE_NOTEQUAL 0000390f
-CSEG PFA_NOTEQUAL 00003913
-CSEG VE_ZEROEQUAL 00003916
-CSEG PFA_ZEROEQUAL 0000391a
-CSEG PFA_ZERO1 00003956
-CSEG PFA_TRUE1 0000394d
-CSEG VE_ZEROLESS 0000391d
-CSEG PFA_ZEROLESS 00003921
-CSEG VE_GREATERZERO 00003924
-CSEG PFA_GREATERZERO 00003928
-CSEG VE_DGREATERZERO 0000392d
-CSEG XT_DGREATERZERO 00003931
-CSEG PFA_DGREATERZERO 00003932
-CSEG VE_DXT_ZEROLESS 0000393b
-CSEG XT_DXT_ZEROLESS 0000393f
-CSEG PFA_DXT_ZEROLESS 00003940
-CSEG VE_TRUE 00003946
-CSEG PFA_TRUE 0000394b
-CSEG VE_ZERO 00003950
-CSEG PFA_ZERO 00003954
-CSEG VE_ULESS 00003958
-CSEG PFA_ULESS 0000395c
-CSEG VE_UGREATER 00003963
-CSEG PFA_UGREATER 00003967
-CSEG VE_LESS 0000396a
-CSEG PFA_LESS 0000396e
-CSEG PFA_LESSDONE 00003972
-CSEG VE_GREATER 00003974
-CSEG PFA_GREATER 00003978
-CSEG PFA_GREATERDONE 0000397c
-CSEG VE_LOG2 0000397f
-CSEG XT_LOG2 00003983
-CSEG PFA_LOG2 00003984
-CSEG PFA_LOG2_1 00003987
-CSEG PFA_LOG2_2 0000398d
-CSEG VE_MINUS 0000398f
-CSEG PFA_MINUS 00003993
-CSEG VE_PLUS 00003999
-CSEG PFA_PLUS 0000399d
-CSEG VE_MSTAR 000039a2
-CSEG PFA_MSTAR 000039a6
-CSEG VE_UMSLASHMOD 000039bc
-CSEG PFA_UMSLASHMOD 000039c2
-CSEG PFA_UMSLASHMODmod 000039c7
-CSEG PFA_UMSLASHMODmod_loop 000039c8
-CSEG PFA_UMSLASHMODmod_loop_control 000039d5
-CSEG PFA_UMSLASHMODmod_subtract 000039d2
-CSEG PFA_UMSLASHMODmod_done 000039d7
-CSEG VE_UMSTAR 000039db
-CSEG PFA_UMSTAR 000039e0
-CSEG VE_INVERT 000039f7
-CSEG PFA_INVERT 000039fd
-CSEG VE_2SLASH 00003a00
-CSEG PFA_2SLASH 00003a04
-CSEG VE_2STAR 00003a07
-CSEG PFA_2STAR 00003a0b
-CSEG VE_AND 00003a0e
-CSEG PFA_AND 00003a13
-CSEG VE_OR 00003a18
-CSEG PFA_OR 00003a1c
-CSEG VE_XOR 00003a21
-CSEG XT_XOR 00003a25
-CSEG PFA_XOR 00003a26
-CSEG VE_1PLUS 00003a2b
-CSEG PFA_1PLUS 00003a2f
-CSEG VE_1MINUS 00003a31
-CSEG PFA_1MINUS 00003a35
-CSEG VE_QNEGATE 00003a37
-CSEG XT_QNEGATE 00003a3d
-CSEG PFA_QNEGATE 00003a3e
-CSEG QNEG1 00003a42
-CSEG VE_LSHIFT 00003a43
-CSEG XT_LSHIFT 00003a48
-CSEG PFA_LSHIFT 00003a49
-CSEG PFA_LSHIFT1 00003a4c
-CSEG PFA_LSHIFT2 00003a51
-CSEG VE_RSHIFT 00003a52
-CSEG XT_RSHIFT 00003a57
-CSEG PFA_RSHIFT 00003a58
-CSEG PFA_RSHIFT1 00003a5b
-CSEG PFA_RSHIFT2 00003a60
-CSEG VE_PLUSSTORE 00003a61
-CSEG PFA_PLUSSTORE 00003a65
-CSEG VE_RP_FETCH 00003a71
-CSEG PFA_RP_FETCH 00003a76
-CSEG VE_RP_STORE 00003a7b
-CSEG XT_RP_STORE 00003a7f
-CSEG PFA_RP_STORE 00003a80
-CSEG VE_SP_FETCH 00003a88
-CSEG PFA_SP_FETCH 00003a8d
-CSEG VE_SP_STORE 00003a91
-CSEG XT_SP_STORE 00003a95
-CSEG PFA_SP_STORE 00003a96
-CSEG PFA_DODO 00003a9b
-CSEG PFA_DODO1 00003a9d
-CSEG VE_I 00003aa8
-CSEG PFA_I 00003aac
-CSEG PFA_DOPLUSLOOP 00003aba
-CSEG PFA_DOPLUSLOOP_LEAVE 00003ac4
-CSEG PFA_DOPLUSLOOP_NEXT 00003ac1
-CSEG PFA_DOLOOP 00003ac9
-CSEG VE_UNLOOP 00003ace
-CSEG PFA_UNLOOP 00003ad4
-CSEG VE_CMOVE_G 00003ad9
-CSEG XT_CMOVE_G 00003ade
-CSEG PFA_CMOVE_G 00003adf
-CSEG PFA_CMOVE_G1 00003af0
-CSEG PFA_CMOVE_G2 00003aec
-CSEG VE_BYTESWAP 00003af5
-CSEG PFA_BYTESWAP 00003af9
-CSEG VE_UP_FETCH 00003afd
-CSEG PFA_UP_FETCH 00003b02
-CSEG VE_UP_STORE 00003b06
-CSEG XT_UP_STORE 00003b0a
-CSEG PFA_UP_STORE 00003b0b
-CSEG VE_1MS 00003b0f
-CSEG XT_1MS 00003b13
-CSEG PFA_1MS 00003b14
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_2TO_R 00003b19
-CSEG PFA_2TO_R 00003b1e
-CSEG VE_2R_FROM 00003b28
-CSEG PFA_2R_FROM 00003b2d
-CSEG VE_STOREE 00003b37
-CSEG PFA_STOREE 00003b3b
-CSEG PFA_STOREE0 00003b3b
-CSEG PFA_FETCHE2 00003b69
-CSEG PFA_STOREE3 00003b45
-CSEG PFA_STOREE1 00003b50
-CSEG PFA_STOREE4 00003b4c
-CSEG PFA_STOREE2 00003b52
-CSEG VE_FETCHE 00003b5b
-CSEG PFA_FETCHE 00003b5f
-CSEG PFA_FETCHE1 00003b5f
-CSEG VE_STOREI 00003b6f
-CSEG PFA_STOREI 00003b73
-ESEG EE_STOREI 00000066
-CSEG VE_DO_STOREI_NRWW 00003b76
-CSEG XT_DO_STOREI 00003b7d
-CSEG PFA_DO_STOREI_NRWW 00003b7e
-CSEG DO_STOREI_atmega 00003b92
-CSEG pageload 00003ba3
-CSEG DO_STOREI_writepage 00003b9c
-CSEG dospm 00003bbc
-EQU pagemask ffffffc0
-CSEG pageload_loop 00003ba9
-CSEG pageload_newdata 00003bb4
-CSEG pageload_cont 00003bb6
-CSEG pageload_done 00003bbb
-CSEG dospm_wait_ee 00003bbc
-CSEG dospm_wait_spm 00003bbe
-CSEG VE_FETCHI 00003bc7
-CSEG PFA_FETCHI 00003bcb
-CSEG VE_N_TO_R 00003bd1
-CSEG XT_N_TO_R 00003bd5
-CSEG PFA_N_TO_R 00003bd6
-CSEG PFA_N_TO_R1 00003bd8
-CSEG VE_N_R_FROM 00003be3
-CSEG XT_N_R_FROM 00003be7
-CSEG PFA_N_R_FROM 00003be8
-CSEG PFA_N_R_FROM1 00003bed
-CSEG VE_D2STAR 00003bf5
-CSEG XT_D2STAR 00003bf9
-CSEG PFA_D2STAR 00003bfa
-CSEG VE_D2SLASH 00003c03
-CSEG XT_D2SLASH 00003c07
-CSEG PFA_D2SLASH 00003c08
-CSEG VE_DPLUS 00003c11
-CSEG PFA_DPLUS 00003c15
-CSEG VE_DMINUS 00003c22
-CSEG XT_DMINUS 00003c25
-CSEG PFA_DMINUS 00003c26
-CSEG VE_DINVERT 00003c34
-CSEG PFA_DINVERT 00003c3b
-CSEG VE_SLASHMOD 00003c44
-CSEG XT_SLASHMOD 00003c48
-CSEG PFA_SLASHMOD 00003c49
-CSEG PFA_SLASHMOD_1 00003c54
-CSEG PFA_SLASHMOD_2 00003c5a
-CSEG PFA_SLASHMOD_3 00003c5d
-CSEG PFA_SLASHMOD_5 00003c68
-CSEG PFA_SLASHMOD_4 00003c67
-CSEG PFA_SLASHMODmod_done 00003c73
-CSEG PFA_SLASHMOD_6 00003c71
-CSEG VE_ABS 00003c77
-CSEG XT_ABS 00003c7b
-CSEG PFA_ABS 00003c7c
-CSEG VE_PICK 00003c7f
-CSEG XT_PICK 00003c83
-CSEG PFA_PICK 00003c84
-CSEG VE_CELLPLUS 00003c8a
-CSEG PFA_CELLPLUS 00003c90
-CSEG VE_INTON 00003c92
-CSEG PFA_INTON 00003c97
-CSEG VE_INTOFF 00003c99
-CSEG XT_INTOFF 00003c9d
-CSEG PFA_INTOFF 00003c9e
-CSEG VE_INTSTORE 00003ca0
-CSEG PFA_INTSTORE 00003ca5
-CSEG VE_INTFETCH 00003caa
-CSEG XT_INTFETCH 00003cae
-CSEG PFA_INTFETCH 00003caf
-CSEG VE_INTTRAP 00003cb4
-CSEG XT_INTTRAP 00003cba
-CSEG PFA_INTTRAP 00003cbb
-CSEG PFA_ISREXEC 00003cc0
-CSEG XT_ISREND 00003cc4
-CSEG PFA_ISREND 00003cc5
-CSEG PFA_ISREND1 00003cc7
-CSEG XT_DEFAULT_PROMPTOK 00003cc8
-CSEG PFA_DEFAULT_PROMPTOK 00003cc9
-CSEG VE_PROMPTOK 00003ccf
-CSEG XT_PROMPTOK 00003cd3
-CSEG PFA_PROMPTOK 00003cd4
-CSEG XT_DEFAULT_PROMPTREADY 00003cd7
-CSEG PFA_DEFAULT_PROMPTREADY 00003cd8
-CSEG VE_PROMPTREADY 00003cde
-CSEG XT_PROMPTREADY 00003ce3
-CSEG PFA_PROMPTREADY 00003ce4
-CSEG XT_DEFAULT_PROMPTERROR 00003ce7
-CSEG PFA_DEFAULT_PROMPTERROR 00003ce8
-CSEG VE_PROMPTERROR 00003cf9
-CSEG XT_PROMPTERROR 00003cfe
-CSEG PFA_PROMPTERROR 00003cff
-CSEG VE_QUIT 00003d02
-CSEG XT_QUIT 00003d06
-CSEG PFA_QUIT 00003d07
-CSEG PFA_QUIT2 00003d0f
-CSEG PFA_QUIT4 00003d15
-CSEG PFA_QUIT3 00003d27
-CSEG XT_CATCH 00003d6f
-CSEG PFA_QUIT5 00003d25
-CSEG VE_PAUSE 00003d2a
-CSEG PFA_PAUSE 00003d30
-DSEG ram_pause 00000192
-CSEG XT_RDEFERFETCH 00003db3
-CSEG XT_RDEFERSTORE 00003dbd
-CSEG VE_COLD 00003d33
-CSEG clearloop 00003d3f
-DSEG ram_user1 00000194
-CSEG PFA_WARM 00003d59
-CSEG VE_WARM 00003d54
-CSEG XT_WARM 00003d58
-CSEG XT_DEFERSTORE 00003dde
-CSEG XT_TURNKEY 00003f5b
-CSEG VE_HANDLER 00003d62
-CSEG XT_HANDLER 00003d68
-CSEG PFA_HANDLER 00003d69
-CSEG VE_CATCH 00003d6a
-CSEG PFA_CATCH 00003d70
-CSEG VE_THROW 00003d80
-CSEG PFA_THROW 00003d86
-CSEG PFA_THROW1 00003d8c
-CSEG VE_EDEFERFETCH 00003d99
-CSEG PFA_EDEFERFETCH 00003da0
-CSEG VE_EDEFERSTORE 00003da3
-CSEG PFA_EDEFERSTORE 00003daa
-CSEG VE_RDEFERFETCH 00003dad
-CSEG PFA_RDEFERFETCH 00003db4
-CSEG VE_RDEFERSTORE 00003db7
-CSEG PFA_RDEFERSTORE 00003dbe
-CSEG VE_UDEFERFETCH 00003dc1
-CSEG PFA_UDEFERFETCH 00003dc8
-CSEG VE_UDEFERSTORE 00003dcd
-CSEG PFA_UDEFERSTORE 00003dd4
-CSEG VE_DEFERSTORE 00003dd9
-CSEG PFA_DEFERSTORE 00003ddf
-CSEG VE_DEFERFETCH 00003de6
-CSEG XT_DEFERFETCH 00003deb
-CSEG PFA_DEFERFETCH 00003dec
-CSEG VE_DODEFER 00003df2
-CSEG XT_DODEFER 00003df8
-CSEG PFA_DODEFER 00003df9
-CSEG VE_UDOT 00003e06
-CSEG XT_UDOT 00003e09
-CSEG PFA_UDOT 00003e0a
-CSEG VE_UDOTR 00003e0d
-CSEG XT_UDOTR 00003e11
-CSEG PFA_UDOTR 00003e12
-CSEG VE_USLASHMOD 00003e16
-CSEG XT_USLASHMOD 00003e1b
-CSEG PFA_USLASHMOD 00003e1c
-CSEG VE_NEGATE 00003e21
-CSEG PFA_NEGATE 00003e27
-CSEG VE_SLASH 00003e2a
-CSEG XT_SLASH 00003e2d
-CSEG PFA_SLASH 00003e2e
-CSEG VE_MOD 00003e31
-CSEG XT_MOD 00003e35
-CSEG PFA_MOD 00003e36
-CSEG VE_MIN 00003e39
-CSEG XT_MIN 00003e3d
-CSEG PFA_MIN 00003e3e
-CSEG PFA_MIN1 00003e43
-CSEG VE_MAX 00003e45
-CSEG XT_MAX 00003e49
-CSEG PFA_MAX 00003e4a
-CSEG PFA_MAX1 00003e4f
-CSEG VE_WITHIN 00003e51
-CSEG PFA_WITHIN 00003e57
-CSEG VE_SHOWWORDLIST 00003e5e
-CSEG XT_SHOWWORDLIST 00003e67
-CSEG PFA_SHOWWORDLIST 00003e68
-CSEG XT_SHOWWORD 00003e6d
-CSEG PFA_SHOWWORD 00003e6e
-CSEG VE_WORDS 00003e73
-CSEG XT_WORDS 00003e78
-CSEG PFA_WORDS 00003e79
-CSEG VE_DOTSTRING 00003e7e
-CSEG XT_DOTSTRING 00003e81
-CSEG PFA_DOTSTRING 00003e82
-CSEG VE_SQUOTE 00003e86
-CSEG PFA_SQUOTE 00003e8a
-CSEG PFA_SQUOTE1 00003e92
-CSEG VE_FILL 00003e93
-CSEG PFA_FILL 00003e98
-CSEG PFA_FILL2 00003ea4
-CSEG PFA_FILL1 00003e9f
-CSEG VE_F_CPU 00003ea6
-CSEG XT_F_CPU 00003eab
-CSEG PFA_F_CPU 00003eac
-CSEG VE_STATE 00003eb1
-CSEG PFA_STATE 00003eb7
-DSEG ram_state 000001c0
-CSEG VE_BASE 00003eb8
-CSEG PFA_BASE 00003ebd
-CSEG VE_CELLS 00003ebe
-CSEG VE_2DUP 00003ec4
-CSEG PFA_2DUP 00003ec9
-CSEG VE_2DROP 00003ecc
-CSEG PFA_2DROP 00003ed2
-CSEG VE_TUCK 00003ed5
-CSEG PFA_TUCK 00003eda
-CSEG VE_TO_IN 00003edd
-CSEG PFA_TO_IN 00003ee2
-CSEG VE_PAD 00003ee3
-CSEG PFA_PAD 00003ee8
-CSEG VE_EMIT 00003eed
-CSEG PFA_EMIT 00003ef2
-CSEG VE_EMITQ 00003ef5
-CSEG XT_EMITQ 00003efa
-CSEG PFA_EMITQ 00003efb
-CSEG VE_KEY 00003efe
-CSEG PFA_KEY 00003f03
-CSEG VE_KEYQ 00003f06
-CSEG XT_KEYQ 00003f0a
-CSEG PFA_KEYQ 00003f0b
-CSEG VE_DP 00003f0e
-ESEG CFG_DP 00000036
-CSEG VE_EHERE 00003f15
-ESEG EE_EHERE 0000003a
-CSEG VE_HERE 00003f1e
-CSEG PFA_HERE 00003f23
-ESEG EE_HERE 00000038
-CSEG VE_ALLOT 00003f26
-CSEG PFA_ALLOT 00003f2c
-CSEG VE_BIN 00003f31
-CSEG XT_BIN 00003f35
-CSEG PFA_BIN 00003f36
-CSEG VE_DECIMAL 00003f3a
-CSEG PFA_DECIMAL 00003f41
-CSEG VE_HEX 00003f46
-CSEG XT_HEX 00003f4a
-CSEG PFA_HEX 00003f4b
-CSEG VE_BL 00003f50
-CSEG PFA_BL 00003f54
-CSEG VE_TURNKEY 00003f55
-CSEG PFA_TURNKEY 00003f5c
-ESEG CFG_TURNKEY 00000042
-CSEG VE_TOUPPER 00003f5f
-CSEG PFA_TOUPPER 00003f66
-CSEG PFA_TOUPPER0 00003f71
-CSEG VE_TOLOWER 00003f72
-CSEG PFA_TOLOWER 00003f79
-CSEG PFA_TOLOWER0 00003f84
-CSEG VE_QSTACK 00003f85
-CSEG PFA_QSTACK 00003f8b
-CSEG PFA_QSTACK1 00003f92
-CSEG VE_BOUNDS 00003f93
-CSEG PFA_BOUNDS 00003f99
-CSEG VE_CR 00003f9d
-CSEG PFA_CR 00003fa1
-CSEG VE_SPACE 00003fa8
-CSEG PFA_SPACE 00003fae
-CSEG VE_SPACES 00003fb1
-CSEG PFA_SPACES 00003fb7
-CSEG SPCS1 00003fb9
-CSEG SPCS2 00003fc0
-CSEG VE_S2D 00003fc2
-CSEG PFA_S2D 00003fc7
-CSEG VE_TO_BODY 00003fca
-CSEG VE_2LITERAL 00003fd0
-CSEG PFA_2LITERAL 00003fd7
-CSEG VE_EQUAL 00003fdb
-CSEG PFA_EQUAL 00003fdf
-CSEG VE_ONE 00003fe2
-CSEG PFA_ONE 00003fe6
-CSEG VE_TWO 00003fe7
-CSEG PFA_TWO 00003feb
-CSEG VE_MINUSONE 00003fec
-CSEG XT_MINUSONE 00003fef
-CSEG PFA_MINUSONE 00003ff0
-SET flashlast 00003ff1
-DSEG HERESTART 000001c2
-ESEG EHERESTART 0000008e
-ESEG CFG_ORDERLIST 0000004c
-ESEG CFG_RECOGNIZERLIST 0000005e
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/arduino/leonardo.asm b/amforth-6.5/appl/arduino/leonardo.asm
deleted file mode 100644
index d915dec..0000000
--- a/amforth-6.5/appl/arduino/leonardo.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; for a description, what can be done in this
-; file see ../template/template.asm. You may want to
-; copy that file to this one and edit it afterwards.
-
-.include "preamble.inc"
-
-; letters the same. Set to 0 if you do not want it
-.set WANT_IGNORECASE = 1
-
-; cpu clock in hertz
-.equ F_CPU = 16000000
-
-.include "drivers/usart_1.asm"
-
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/arduino/leonardo.eep.hex b/amforth-6.5/appl/arduino/leonardo.eep.hex
deleted file mode 100644
index 9449707..0000000
--- a/amforth-6.5/appl/arduino/leonardo.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10005600FFFFA10AD301B000B5097E00B00A930ADA
-:0A006600E6026A00EC3F01006A00A8
-:06007E00020057064306D4
-:100088007D3B8A0000000000FF0AAF0AAF0A0000AB
-:100098000A00C500D3009A00B5005E0200004B02BA
-:0800A800C83CE73CD73C1900FD
-:00000001FF
diff --git a/amforth-6.5/appl/arduino/leonardo.hex b/amforth-6.5/appl/arduino/leonardo.hex
deleted file mode 100644
index 2b1ad5e..0000000
--- a/amforth-6.5/appl/arduino/leonardo.hex
+++ /dev/null
@@ -1,630 +0,0 @@
-:020000020000FC
-:02000400FCD02E
-:02000800FAD02C
-:02000C00F8D02A
-:02001000F6D028
-:02001400F4D026
-:02001800F2D024
-:02001C00F0D022
-:02002000EED020
-:02002400ECD01E
-:02002800EAD01C
-:02002C00E8D01A
-:02003000E6D018
-:02003400E4D016
-:02003800E2D014
-:02003C00E0D012
-:02004000DED010
-:02004400DCD00E
-:02004800DAD00C
-:02004C00D8D00A
-:02005000D6D008
-:02005400D4D006
-:02005800D2D004
-:02005C00D0D002
-:02006000CED000
-:02006400CCD0FE
-:02006800CAD0FC
-:02006C00C8D0FA
-:02007000C6D0F8
-:02007400C4D0F6
-:02007800C2D0F4
-:02007C00C0D0F2
-:02008000BED0F0
-:02008400BCD0EE
-:02008800BAD0EC
-:02008C00B8D0EA
-:02009000B6D0E8
-:02009400B4D0E6
-:02009800B2D0E4
-:02009C00B0D0E2
-:0200A000AED0E0
-:0200A400ACD0DE
-:1000A800AAD0000A000400702B000A0041546D65B4
-:1000B80067613332553407FF3E72782D62756600EA
-:1000C80000006600082F10911001E0E0F1E0E10F58
-:1000D800F31D008313951F70109310018991999156
-:1000E8000C94043806FF6973722D72785F0000382B
-:1000F8003C38CE009738B0383C380300DE3F3538FE
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diff --git a/amforth-6.5/appl/arduino/leonardo.lst b/amforth-6.5/appl/arduino/leonardo.lst
deleted file mode 100644
index f90efff..0000000
--- a/amforth-6.5/appl/arduino/leonardo.lst
+++ /dev/null
@@ -1,10136 +0,0 @@
-
-AVRASM ver. 2.1.52 leonardo.asm Sun Apr 30 20:10:13 2017
-
-leonardo.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega32u4\device.asm'
-../../avr8/devices/atmega32u4\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m32U4def.inc'
-leonardo.asm(13): Including file '../../avr8\drivers/usart_1.asm'
-../../avr8\drivers/usart_1.asm(31): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-leonardo.asm(15): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(11): Including file '../../avr8\dict/appl_4k.inc'
-../../avr8\dict/appl_4k.inc(1): Including file '../../common\words/ver.asm'
-../../avr8\dict/appl_4k.inc(4): Including file '../../common\words/noop.asm'
-../../avr8\dict/appl_4k.inc(5): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/appl_4k.inc(6): Including file '../../common\words/to.asm'
-../../avr8\dict/appl_4k.inc(7): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/appl_4k.inc(8): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/appl_4k.inc(9): Including file '../../common\words/star.asm'
-../../avr8\dict/appl_4k.inc(10): Including file '../../avr8\words/j.asm'
-../../avr8\dict/appl_4k.inc(11): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/appl_4k.inc(12): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/appl_4k.inc(13): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/appl_4k.inc(14): Including file '../../common\words/2swap.asm'
-../../avr8\dict/appl_4k.inc(15): Including file '../../common\words/tib.asm'
-../../avr8\dict/appl_4k.inc(16): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/appl_4k.inc(20): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/appl_4k.inc(21): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/appl_4k.inc(22): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/appl_4k.inc(23): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/appl_4k.inc(24): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/appl_4k.inc(25): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/appl_4k.inc(26): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/appl_4k.inc(27): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/appl_4k.inc(28): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/appl_4k.inc(30): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/appl_4k.inc(31): Including file '../../common\words/hold.asm'
-../../avr8\dict/appl_4k.inc(32): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/appl_4k.inc(33): Including file '../../common\words/sharp.asm'
-../../avr8\dict/appl_4k.inc(34): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/appl_4k.inc(35): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/appl_4k.inc(36): Including file '../../common\words/sign.asm'
-../../avr8\dict/appl_4k.inc(37): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/appl_4k.inc(38): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/appl_4k.inc(39): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/appl_4k.inc(40): Including file '../../common\words/dot.asm'
-../../avr8\dict/appl_4k.inc(41): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/appl_4k.inc(42): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/appl_4k.inc(43): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/appl_4k.inc(44): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/appl_4k.inc(46): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/appl_4k.inc(47): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/appl_4k.inc(48): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/appl_4k.inc(49): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/appl_4k.inc(50): Including file '../../common\words/type.asm'
-../../avr8\dict/appl_4k.inc(51): Including file '../../common\words/tick.asm'
-../../avr8\dict/appl_4k.inc(53): Including file '../../common\words/cskip.asm'
-../../avr8\dict/appl_4k.inc(54): Including file '../../common\words/cscan.asm'
-../../avr8\dict/appl_4k.inc(55): Including file '../../common\words/accept.asm'
-../../avr8\dict/appl_4k.inc(56): Including file '../../common\words/refill.asm'
-../../avr8\dict/appl_4k.inc(57): Including file '../../common\words/char.asm'
-../../avr8\dict/appl_4k.inc(58): Including file '../../common\words/number.asm'
-../../avr8\dict/appl_4k.inc(59): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/appl_4k.inc(60): Including file '../../common\words/set-base.asm'
-../../avr8\dict/appl_4k.inc(61): Including file '../../common\words/to-number.asm'
-../../avr8\dict/appl_4k.inc(62): Including file '../../common\words/parse.asm'
-../../avr8\dict/appl_4k.inc(63): Including file '../../common\words/source.asm'
-../../avr8\dict/appl_4k.inc(64): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/appl_4k.inc(65): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/appl_4k.inc(66): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/appl_4k.inc(67): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/appl_4k.inc(68): Including file '../../common\words/depth.asm'
-../../avr8\dict/appl_4k.inc(69): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/appl_4k.inc(70): Including file '../../common\words/recognize.asm'
-../../avr8\dict/appl_4k.inc(71): Including file '../../common\words/interpret.asm'
-../../avr8\dict/appl_4k.inc(72): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/appl_4k.inc(73): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/appl_4k.inc(74): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/appl_4k.inc(75): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/appl_4k.inc(76): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/appl_4k.inc(77): Including file '../../common\words/name2string.asm'
-../../avr8\dict/appl_4k.inc(78): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/appl_4k.inc(79): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/appl_4k.inc(81): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(4): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(104): Including file '../../avr8\dict/core_4k.inc'
-../../avr8\dict/core_4k.inc(3): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_4k.inc(4): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_4k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_4k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_4k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_4k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_4k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_4k.inc(10): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_4k.inc(11): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_4k.inc(12): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_4k.inc(13): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_4k.inc(14): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_4k.inc(17): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_4k.inc(18): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_4k.inc(19): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_4k.inc(21): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_4k.inc(22): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_4k.inc(23): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_4k.inc(24): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_4k.inc(26): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_4k.inc(27): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_4k.inc(28): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_4k.inc(31): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_4k.inc(32): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_4k.inc(33): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_4k.inc(34): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_4k.inc(35): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_4k.inc(36): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_4k.inc(37): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_4k.inc(38): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_4k.inc(39): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_4k.inc(41): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_4k.inc(42): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_4k.inc(45): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_4k.inc(46): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_4k.inc(47): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_4k.inc(48): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_4k.inc(50): Including file '../../common\words/min.asm'
-../../avr8\dict/core_4k.inc(51): Including file '../../common\words/max.asm'
-../../avr8\dict/core_4k.inc(52): Including file '../../common\words/within.asm'
-../../avr8\dict/core_4k.inc(54): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_4k.inc(55): Including file '../../common\words/words.asm'
-../../avr8\dict/core_4k.inc(57): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_4k.inc(58): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_4k.inc(59): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_4k.inc(61): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_4k.inc(62): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_4k.inc(63): Including file '../../common\words/base.asm'
-../../avr8\dict/core_4k.inc(65): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_4k.inc(67): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_4k.inc(68): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_4k.inc(69): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_4k.inc(71): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_4k.inc(72): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_4k.inc(73): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_4k.inc(74): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_4k.inc(75): Including file '../../common\words/key.asm'
-../../avr8\dict/core_4k.inc(76): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_4k.inc(78): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_4k.inc(79): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_4k.inc(80): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_4k.inc(81): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_4k.inc(83): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_4k.inc(84): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_4k.inc(85): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_4k.inc(86): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_4k.inc(88): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_4k.inc(89): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_4k.inc(90): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_4k.inc(92): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_4k.inc(93): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_4k.inc(94): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_4k.inc(95): Including file '../../common\words/space.asm'
-../../avr8\dict/core_4k.inc(96): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_4k.inc(97): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_4k.inc(98): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_WATCHDOG = 0
- .set WANT_PORTD = 0
- .set WANT_SPI = 0
- .set WANT_USART1 = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_EEPROM = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_3 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_JTAG = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_TIMER_COUNTER_4 = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTE = 0
- .set WANT_PORTF = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_CPU = 0
- .set WANT_PLL = 0
- .set WANT_USB_DEVICE = 0
- .equ intvecsize = 2 ; please verify; flash size: 32768 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d0fc rcall isr ; External Interrupt Request 0
- .org 4
-000004 d0fa rcall isr ; External Interrupt Request 1
- .org 6
-000006 d0f8 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d0f6 rcall isr ; External Interrupt Request 3
- .org 10
-00000a d0f4 rcall isr ; Reserved1
- .org 12
-00000c d0f2 rcall isr ; Reserved2
- .org 14
-00000e d0f0 rcall isr ; External Interrupt Request 6
- .org 16
-000010 d0ee rcall isr ; Reserved3
- .org 18
-000012 d0ec rcall isr ; Pin Change Interrupt Request 0
- .org 20
-000014 d0ea rcall isr ; USB General Interrupt Request
- .org 22
-000016 d0e8 rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
- .org 24
-000018 d0e6 rcall isr ; Watchdog Time-out Interrupt
- .org 26
-00001a d0e4 rcall isr ; Reserved4
- .org 28
-00001c d0e2 rcall isr ; Reserved5
- .org 30
-00001e d0e0 rcall isr ; Reserved6
- .org 32
-000020 d0de rcall isr ; Timer/Counter1 Capture Event
- .org 34
-000022 d0dc rcall isr ; Timer/Counter1 Compare Match A
- .org 36
-000024 d0da rcall isr ; Timer/Counter1 Compare Match B
- .org 38
-000026 d0d8 rcall isr ; Timer/Counter1 Compare Match C
- .org 40
-000028 d0d6 rcall isr ; Timer/Counter1 Overflow
- .org 42
-00002a d0d4 rcall isr ; Timer/Counter0 Compare Match A
- .org 44
-00002c d0d2 rcall isr ; Timer/Counter0 Compare Match B
- .org 46
-00002e d0d0 rcall isr ; Timer/Counter0 Overflow
- .org 48
-000030 d0ce rcall isr ; SPI Serial Transfer Complete
- .org 50
-000032 d0cc rcall isr ; USART1, Rx Complete
- .org 52
-000034 d0ca rcall isr ; USART1 Data register Empty
- .org 54
-000036 d0c8 rcall isr ; USART1, Tx Complete
- .org 56
-000038 d0c6 rcall isr ; Analog Comparator
- .org 58
-00003a d0c4 rcall isr ; ADC Conversion Complete
- .org 60
-00003c d0c2 rcall isr ; EEPROM Ready
- .org 62
-00003e d0c0 rcall isr ; Timer/Counter3 Capture Event
- .org 64
-000040 d0be rcall isr ; Timer/Counter3 Compare Match A
- .org 66
-000042 d0bc rcall isr ; Timer/Counter3 Compare Match B
- .org 68
-000044 d0ba rcall isr ; Timer/Counter3 Compare Match C
- .org 70
-000046 d0b8 rcall isr ; Timer/Counter3 Overflow
- .org 72
-000048 d0b6 rcall isr ; 2-wire Serial Interface
- .org 74
-00004a d0b4 rcall isr ; Store Program Memory Read
- .org 76
-00004c d0b2 rcall isr ; Timer/Counter4 Compare Match A
- .org 78
-00004e d0b0 rcall isr ; Timer/Counter4 Compare Match B
- .org 80
-000050 d0ae rcall isr ; Timer/Counter4 Compare Match D
- .org 82
-000052 d0ac rcall isr ; Timer/Counter4 Overflow
- .org 84
-000054 d0aa rcall isr ; Timer/Counter4 Fault Protection Interrupt
- .equ INTVECTORS = 43
- .nooverlap
-
- ; compatability layer (maybe empty)
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000055 0a00 .dw 2560
- mcu_eepromsize:
-000056 0400 .dw 1024
- mcu_maxdp:
-000057 7000 .dw 28672
- mcu_numints:
-000058 002b .dw 43
- mcu_name:
-000059 000a .dw 10
-00005a 5441
-00005b 656d
-00005c 6167
-00005d 3233
-00005e 3455 .db "ATmega32U4"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- ; letters the same. Set to 0 if you do not want it
- .set WANT_IGNORECASE = 1
-
- ; cpu clock in hertz
- .equ F_CPU = 16000000
-
- .include "drivers/usart_1.asm"
-
- .equ BAUDRATE_HIGH = UBRR1H
- .equ USART_C = UCSR1C
- .equ USART_B = UCSR1B
- .equ USART_A = UCSR1A
- .equ USART_DATA = UDR1
-
- .equ URXCaddr = URXC1addr
- .equ UDREaddr = UDRE1addr
-
- .equ bm_USART_RXRD = 1 << RXC1
- .equ bm_USART_TXRD = 1 << UDRE1
- .equ bm_ENABLE_TX = 1 << TXEN1
- .equ bm_ENABLE_RX = 1 << RXEN1
- .equ bm_ENABLE_INT_RX = 1<<RXCIE1
- .equ bm_ENABLE_INT_TX = 1<<UDRIE1
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-00005f ff07 .dw $ff07
-000060 723e
-000061 2d78
-000062 7562
-000063 0066 .db ">rx-buf",0
-000064 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000065 0066 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000066 2f08 mov temp0, tosl
-000067 9110 0110 lds temp1, usart_rx_in
-000069 e0e0 ldi zl, low(usart_rx_data)
-00006a e0f1 ldi zh, high(usart_rx_data)
-00006b 0fe1 add zl, temp1
-00006c 1df3 adc zh, zeroh
-00006d 8300 st Z, temp0
-00006e 9513 inc temp1
-00006f 701f andi temp1,usart_rx_mask
-000070 9310 0110 sts usart_rx_in, temp1
-000072 9189
-000073 9199 loadtos
-000074 940c 3804 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000076 ff06 .dw $ff06
-000077 7369
-000078 2d72
-000079 7872 .db "isr-rx"
-00007a 005f .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-00007b 3800 .dw DO_COLON
- usart_rx_isr:
-00007c 383c .dw XT_DOLITERAL
-00007d 00ce .dw usart_data
-00007e 3897 .dw XT_CFETCH
-00007f 38b0 .dw XT_DUP
-000080 383c .dw XT_DOLITERAL
-000081 0003 .dw 3
-000082 3fde .dw XT_EQUAL
-000083 3835 .dw XT_DOCONDBRANCH
-000084 0086 .dw usart_rx_isr1
-000085 3d37 .dw XT_COLD
- usart_rx_isr1:
-000086 0065 .dw XT_TO_RXBUF
-000087 381f .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-000088 3800 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-000089 383c
-00008a 007b .dw XT_DOLITERAL, XT_ISR_RX
-00008b 383c
-00008c 0032 .dw XT_DOLITERAL, URXCaddr
-00008d 3ca4 .dw XT_INTSTORE
-
-00008e 383c .dw XT_DOLITERAL
-00008f 0100 .dw usart_rx_data
-000090 383c .dw XT_DOLITERAL
-000091 0016 .dw usart_rx_size + 6
-000092 3953 .dw XT_ZERO
-000093 3e97 .dw XT_FILL
-000094 381f .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000095 ff06 .dw $ff06
-000096 7872
-000097 622d
-000098 6675 .db "rx-buf"
-000099 0076 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-00009a 3800 .dw DO_COLON
- PFA_RX_BUFFER:
-00009b 00b5 .dw XT_RXQ_BUFFER
-00009c 3835 .dw XT_DOCONDBRANCH
-00009d 009b .dw PFA_RX_BUFFER
-00009e 383c .dw XT_DOLITERAL
-00009f 0111 .dw usart_rx_out
-0000a0 3897 .dw XT_CFETCH
-0000a1 38b0 .dw XT_DUP
-0000a2 383c .dw XT_DOLITERAL
-0000a3 0100 .dw usart_rx_data
-0000a4 399c .dw XT_PLUS
-0000a5 3897 .dw XT_CFETCH
-0000a6 38c3 .dw XT_SWAP
-0000a7 3a2e .dw XT_1PLUS
-0000a8 383c .dw XT_DOLITERAL
-0000a9 000f .dw usart_rx_mask
-0000aa 3a12 .dw XT_AND
-0000ab 383c .dw XT_DOLITERAL
-0000ac 0111 .dw usart_rx_out
-0000ad 388c .dw XT_CSTORE
-0000ae 381f .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-0000af ff07 .dw $ff07
-0000b0 7872
-0000b1 2d3f
-0000b2 7562
-0000b3 0066 .db "rx?-buf",0
-0000b4 0095 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-0000b5 3800 .dw DO_COLON
- PFA_RXQ_BUFFER:
-0000b6 3d2f .dw XT_PAUSE
-0000b7 383c .dw XT_DOLITERAL
-0000b8 0111 .dw usart_rx_out
-0000b9 3897 .dw XT_CFETCH
-0000ba 383c .dw XT_DOLITERAL
-0000bb 0110 .dw usart_rx_in
-0000bc 3897 .dw XT_CFETCH
-0000bd 3912 .dw XT_NOTEQUAL
-0000be 381f .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-0000bf ff07 .dw $ff07
-0000c0 7874
-0000c1 702d
-0000c2 6c6f
-0000c3 006c .db "tx-poll",0
-0000c4 00af .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000c5 3800 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000c6 00d3 .dw XT_TXQ_POLL
-0000c7 3835 .dw XT_DOCONDBRANCH
-0000c8 00c6 .dw PFA_TX_POLL
- ; send to usart
-0000c9 383c .dw XT_DOLITERAL
-0000ca 00ce .dw USART_DATA
-0000cb 388c .dw XT_CSTORE
-0000cc 381f .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000cd ff08 .dw $ff08
-0000ce 7874
-0000cf 2d3f
-0000d0 6f70
-0000d1 6c6c .db "tx?-poll"
-0000d2 00bf .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000d3 3800 .dw DO_COLON
- PFA_TXQ_POLL:
-0000d4 3d2f .dw XT_PAUSE
-0000d5 383c .dw XT_DOLITERAL
-0000d6 00c8 .dw USART_A
-0000d7 3897 .dw XT_CFETCH
-0000d8 383c .dw XT_DOLITERAL
-0000d9 0020 .dw bm_USART_TXRD
-0000da 3a12 .dw XT_AND
-0000db 381f .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000dc ff04 .dw $ff04
-0000dd 6275
-0000de 7272 .db "ubrr"
-0000df 00cd .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000e0 386e .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000e1 00ae .dw EE_UBRRVAL
-0000e2 3d9f .dw XT_EDEFERFETCH
-0000e3 3da9 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000e4 ff06 .dw $ff06
-0000e5 752b
-0000e6 6173
-0000e7 7472 .db "+usart"
-0000e8 00dc .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000e9 3800 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000ea 383c .dw XT_DOLITERAL
-0000eb 0098 .dw USART_B_VALUE
-0000ec 383c .dw XT_DOLITERAL
-0000ed 00c9 .dw USART_B
-0000ee 388c .dw XT_CSTORE
-
-0000ef 383c .dw XT_DOLITERAL
-0000f0 0006 .dw USART_C_VALUE
-0000f1 383c .dw XT_DOLITERAL
-0000f2 00ca .dw USART_C | bm_USARTC_en
-0000f3 388c .dw XT_CSTORE
-
-0000f4 00e0 .dw XT_UBRR
-0000f5 38b0 .dw XT_DUP
-0000f6 3af8 .dw XT_BYTESWAP
-0000f7 383c .dw XT_DOLITERAL
-0000f8 00cd .dw BAUDRATE_HIGH
-0000f9 388c .dw XT_CSTORE
-0000fa 383c .dw XT_DOLITERAL
-0000fb 00cc .dw BAUDRATE_LOW
-0000fc 388c .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000fd 0088 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000fe 381f .dw XT_EXIT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 3d38 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-0000ff 920a st -Y, r0
-000100 b60f in r0, SREG
-000101 920a st -Y, r0
- .if (pclen==3)
- .endif
-000102 900f pop r0
-000103 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-000104 940a dec r0
- .if intvecsize == 1 ;
- .endif
-000105 2cb0 mov isrflag, r0
-000106 93ff push zh
-000107 93ef push zl
-000108 e1e2 ldi zl, low(intcnt)
-000109 e0f1 ldi zh, high(intcnt)
-00010a 9406 lsr r0 ; we use byte addresses in the counter array, not words
-00010b 0de0 add zl, r0
-00010c 1df3 adc zh, zeroh
-00010d 8000 ld r0, Z
-00010e 9403 inc r0
-00010f 8200 st Z, r0
-000110 91ef pop zl
-000111 91ff pop zh
-
-000112 9009 ld r0, Y+
-000113 be0f out SREG, r0
-000114 9009 ld r0, Y+
-000115 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000116 ff02 .dw $ff02
-000117 2b6d .db "m+"
-000118 00e4 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000119 3800 .dw DO_COLON
- PFA_MPLUS:
-00011a 3fc6 .dw XT_S2D
-00011b 3c14 .dw XT_DPLUS
-00011c 381f .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00011d ff03 .dw $ff03
-00011e 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-00011f 002a .db "ud*"
-000120 0116 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-000121 3800 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000122 38b0
-000123 38fe
-000124 39df
-000125 38d8 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000126 38c3
-000127 38f5
-000128 39df
-000129 38e0
-00012a 399c
-00012b 381f .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00012c ff04 .dw $ff04
-00012d 6d75
-00012e 7861 .db "umax"
-00012f 011d .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-000130 3800 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-000131 3ec8
-000132 395b .DW XT_2DUP,XT_ULESS
-000133 3835 .dw XT_DOCONDBRANCH
-000134 0136 DEST(UMAX1)
-000135 38c3 .DW XT_SWAP
-000136 38d8 UMAX1: .DW XT_DROP
-000137 381f .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000138 ff04 .dw $ff04
-000139 6d75
-00013a 6e69 .db "umin"
-00013b 012c .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00013c 3800 .dw DO_COLON
- PFA_UMIN:
- .endif
-00013d 3ec8
-00013e 3966 .DW XT_2DUP,XT_UGREATER
-00013f 3835 .dw XT_DOCONDBRANCH
-000140 0142 DEST(UMIN1)
-000141 38c3 .DW XT_SWAP
-000142 38d8 UMIN1: .DW XT_DROP
-000143 381f .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000144 3800 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000145 383c .dw XT_DOLITERAL
-000146 8000 .dw $8000
-000147 3a12 .dw XT_AND
-000148 3919 .dw XT_ZEROEQUAL
-000149 3835 .dw XT_DOCONDBRANCH
-00014a 014d DEST(IMMEDIATEQ1)
-00014b 3fe5 .dw XT_ONE
-00014c 381f .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00014d 394a .dw XT_TRUE
-00014e 381f .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00014f ff0a .dw $ff0a
-000150 616e
-000151 656d
-000152 663e
-000153 616c
-000154 7367 .db "name>flags"
-000155 0138 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000156 3800 .dw DO_COLON
- PFA_NAME2FLAGS:
-000157 3bca .dw XT_FETCHI ; skip to link field
-000158 383c .dw XT_DOLITERAL
-000159 ff00 .dw $ff00
-00015a 3a12 .dw XT_AND
-00015b 381f .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .elif AMFORTH_NRWW_SIZE > 4000
- .include "dict/appl_4k.inc"
-
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-00015c ff03 .dw $ff03
-00015d 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-00015e 0072 .db "ver"
-00015f 014f .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-000160 3800 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-000161 02c1 .dw XT_ENV_FORTHNAME
-000162 03ea .dw XT_ITYPE
-000163 3fad .dw XT_SPACE
-000164 3ebc .dw XT_BASE
-000165 3878 .dw XT_FETCH
-
-000166 02cf .dw XT_ENV_FORTHVERSION
-000167 3f40 .dw XT_DECIMAL
-000168 3fc6 .dw XT_S2D
-000169 0308 .dw XT_L_SHARP
-00016a 0310 .dw XT_SHARP
-00016b 383c .dw XT_DOLITERAL
-00016c 002e .dw '.'
-00016d 02f9 .dw XT_HOLD
-00016e 0326 .dw XT_SHARP_S
-00016f 0331 .dw XT_SHARP_G
-000170 0420 .dw XT_TYPE
-000171 3ebc .dw XT_BASE
-000172 3880 .dw XT_STORE
-000173 3fad .dw XT_SPACE
-000174 02d7 .dw XT_ENV_CPU
-000175 03ea .dw XT_ITYPE
-
-000176 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-000177 ff04 .dw $ff04
-000178 6f6e
-000179 706f .db "noop"
-00017a 015c .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-00017b 3800 .dw DO_COLON
- PFA_NOOP:
- .endif
-00017c 381f .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-00017d ff06 .dw $ff06
-00017e 6e75
-00017f 7375
-000180 6465 .db "unused"
-000181 0177 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-000182 3800 .dw DO_COLON
- PFA_UNUSED:
-000183 3a8c .dw XT_SP_FETCH
-000184 3f22 .dw XT_HERE
-000185 3992 .dw XT_MINUS
-000186 381f .dw XT_EXIT
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-000187 0002 .dw $0002
-000188 6f74 .db "to"
-000189 017d .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-00018a 3800 .dw DO_COLON
- PFA_TO:
- .endif
-00018b 042f .dw XT_TICK
-00018c 3fcf .dw XT_TO_BODY
-00018d 3eb6 .dw XT_STATE
-00018e 3878 .dw XT_FETCH
-00018f 3835 .dw XT_DOCONDBRANCH
-000190 019b DEST(PFA_TO1)
-000191 0743 .dw XT_COMPILE
-000192 0195 .dw XT_DOTO
-000193 074e .dw XT_COMMA
-000194 381f .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-000195 3800 .dw DO_COLON
- PFA_DOTO:
- .endif
-000196 38f5 .dw XT_R_FROM
-000197 38b0 .dw XT_DUP
-000198 01a7 .dw XT_ICELLPLUS
-000199 38fe .dw XT_TO_R
-00019a 3bca .dw XT_FETCHI
- PFA_TO1:
-00019b 38b0 .dw XT_DUP
-00019c 01a7 .dw XT_ICELLPLUS
-00019d 01a7 .dw XT_ICELLPLUS
-00019e 3bca .dw XT_FETCHI
-00019f 3829 .dw XT_EXECUTE
-0001a0 381f .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-0001a1 ff07 .dw $FF07
-0001a2 2d69
-0001a3 6563
-0001a4 6c6c
-0001a5 002b .db "i-cell+",0
-0001a6 0187 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-0001a7 3800 .dw DO_COLON
- PFA_ICELLPLUS:
-0001a8 3a2e .dw XT_1PLUS
-0001a9 381f .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-0001aa ff08 .dw $ff08
-0001ab 6369
-0001ac 6d6f
-0001ad 6170
-0001ae 6572 .db "icompare"
-0001af 01a1 .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-0001b0 3800 .dw DO_COLON
- PFA_ICOMPARE:
-0001b1 38fe .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-0001b2 38ce .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-0001b3 38f5 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-0001b4 3912 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-0001b5 3835 .dw XT_DOCONDBRANCH
-0001b6 01bb .dw PFA_ICOMPARE_SAMELEN
-0001b7 3ed1 .dw XT_2DROP
-0001b8 38d8 .dw XT_DROP
-0001b9 394a .dw XT_TRUE
-0001ba 381f .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-0001bb 38c3 .dw XT_SWAP ; ( -- r-addr f-addr len )
-0001bc 3953 .dw XT_ZERO
-0001bd 080d .dw XT_QDOCHECK
-0001be 3835 .dw XT_DOCONDBRANCH
-0001bf 01e0 .dw PFA_ICOMPARE_DONE
-0001c0 3a9a .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-0001c1 38ce .dw XT_OVER
-0001c2 3878 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
-0001c3 01e3 .dw XT_ICOMPARE_LC
- .endif
-0001c4 38ce .dw XT_OVER
-0001c5 3bca .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
-0001c6 01e3 .dw XT_ICOMPARE_LC
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-0001c7 38b0 .dw XT_DUP
- ;.dw XT_BYTESWAP
-0001c8 383c .dw XT_DOLITERAL
-0001c9 0100 .dw $100
-0001ca 395b .dw XT_ULESS
-0001cb 3835 .dw XT_DOCONDBRANCH
-0001cc 01d1 .dw PFA_ICOMPARE_LASTCELL
-0001cd 38c3 .dw XT_SWAP
-0001ce 383c .dw XT_DOLITERAL
-0001cf 00ff .dw $00FF
-0001d0 3a12 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-0001d1 3912 .dw XT_NOTEQUAL
-0001d2 3835 .dw XT_DOCONDBRANCH
-0001d3 01d8 .dw PFA_ICOMPARE_NEXTLOOP
-0001d4 3ed1 .dw XT_2DROP
-0001d5 394a .dw XT_TRUE
-0001d6 3ad3 .dw XT_UNLOOP
-0001d7 381f .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-0001d8 3a2e .dw XT_1PLUS
-0001d9 38c3 .dw XT_SWAP
-0001da 3c8f .dw XT_CELLPLUS
-0001db 38c3 .dw XT_SWAP
-0001dc 383c .dw XT_DOLITERAL
-0001dd 0002 .dw 2
-0001de 3ab9 .dw XT_DOPLUSLOOP
-0001df 01c1 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-0001e0 3ed1 .dw XT_2DROP
-0001e1 3953 .dw XT_ZERO
-0001e2 381f .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- ; ( cc1 cc2 -- f)
- ; Tools
- ; compares two packed characters
- ;VE_ICOMPARELC:
- ; .dw $ff08
- ; .db "icompare-lower"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ICOMPARELC
- XT_ICOMPARE_LC:
-0001e3 3800 .dw DO_COLON
- PFA_ICOMPARE_LC:
-0001e4 38b0 .dw XT_DUP
-0001e5 383c .dw XT_DOLITERAL
-0001e6 00ff .dw $00ff
-0001e7 3a12 .dw XT_AND
-0001e8 3f78 .dw XT_TOLOWER
-0001e9 38c3 .dw XT_SWAP
-0001ea 3af8 .dw XT_BYTESWAP
-0001eb 383c .dw XT_DOLITERAL
-0001ec 00ff .dw $00ff
-0001ed 3a12 .dw XT_AND
-0001ee 3f78 .dw XT_TOLOWER
-0001ef 3af8 .dw XT_BYTESWAP
-0001f0 3a1b .dw XT_OR
-0001f1 381f .dw XT_EXIT
- .endif
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-0001f2 ff01 .dw $ff01
-0001f3 002a .db "*",0
-0001f4 01aa .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-0001f5 3800 .dw DO_COLON
- PFA_STAR:
- .endif
-
-0001f6 39a5 .dw XT_MSTAR
-0001f7 38d8 .dw XT_DROP
-0001f8 381f .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-0001f9 ff01 .dw $FF01
-0001fa 006a .db "j",0
-0001fb 01f2 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-0001fc 3800 .dw DO_COLON
- PFA_J:
-0001fd 3a75 .dw XT_RP_FETCH
-0001fe 383c .dw XT_DOLITERAL
-0001ff 0007 .dw 7
-000200 399c .dw XT_PLUS
-000201 3878 .dw XT_FETCH
-000202 3a75 .dw XT_RP_FETCH
-000203 383c .dw XT_DOLITERAL
-000204 0009 .dw 9
-000205 399c .dw XT_PLUS
-000206 3878 .dw XT_FETCH
-000207 399c .dw XT_PLUS
-000208 381f .dw XT_EXIT
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-000209 ff04 .dw $ff04
-00020a 6164
-00020b 7362 .db "dabs"
-00020c 01f9 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-00020d 3800 .dw DO_COLON
- PFA_DABS:
-00020e 38b0 .dw XT_DUP
-00020f 3920 .dw XT_ZEROLESS
-000210 3835 .dw XT_DOCONDBRANCH
-000211 0213 .dw PFA_DABS1
-000212 021a .dw XT_DNEGATE
- PFA_DABS1:
-000213 381f .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-000214 ff07 .dw $ff07
-000215 6e64
-000216 6765
-000217 7461
-000218 0065 .db "dnegate",0
-000219 0209 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-00021a 3800 .dw DO_COLON
- PFA_DNEGATE:
-00021b 3c3a .dw XT_DINVERT
-00021c 3fe5 .dw XT_ONE
-00021d 3953 .dw XT_ZERO
-00021e 3c14 .dw XT_DPLUS
-00021f 381f .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-000220 ff05 .dw $ff05
-000221 6d63
-000222 766f
-000223 0065 .db "cmove",0
-000224 0214 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-000225 0226 .dw PFA_CMOVE
- PFA_CMOVE:
-000226 93bf push xh
-000227 93af push xl
-000228 91e9 ld zl, Y+
-000229 91f9 ld zh, Y+ ; addr-to
-00022a 91a9 ld xl, Y+
-00022b 91b9 ld xh, Y+ ; addr-from
-00022c 2f09 mov temp0, tosh
-00022d 2b08 or temp0, tosl
-00022e f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00022f 911d ld temp1, X+
-000230 9311 st Z+, temp1
-000231 9701 sbiw tosl, 1
-000232 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-000233 91af pop xl
-000234 91bf pop xh
-000235 9189
-000236 9199 loadtos
-000237 940c 3804 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-000239 ff05 .dw $ff05
-00023a 7332
-00023b 6177
-00023c 0070 .db "2swap",0
-00023d 0220 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00023e 3800 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00023f 38e0 .dw XT_ROT
-000240 38fe .dw XT_TO_R
-000241 38e0 .dw XT_ROT
-000242 38f5 .dw XT_R_FROM
-000243 381f .dw XT_EXIT
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-000244 ff0a .dw $ff0a
-000245 6572
-000246 6966
-000247 6c6c
-000248 742d
-000249 6269 .db "refill-tib"
-00024a 0239 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-00024b 3800 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-00024c 0267 .dw XT_TIB
-00024d 383c .dw XT_DOLITERAL
-00024e 005a .dw TIB_SIZE
-00024f 047f .dw XT_ACCEPT
-000250 026d .dw XT_NUMBERTIB
-000251 3880 .dw XT_STORE
-000252 3953 .dw XT_ZERO
-000253 3ee1 .dw XT_TO_IN
-000254 3880 .dw XT_STORE
-000255 394a .dw XT_TRUE ; -1
-000256 381f .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-000257 ff0a .dw $FF0A
-000258 6f73
-000259 7275
-00025a 6563
-00025b 742d
-00025c 6269 .db "source-tib"
-00025d 0244 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00025e 3800 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00025f 0267 .dw XT_TIB
-000260 026d .dw XT_NUMBERTIB
-000261 3878 .dw XT_FETCH
-000262 381f .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-000263 ff03 .dw $ff03
-000264 6974
-000265 0062 .db "tib",0
-000266 0257 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-000267 3847 .dw PFA_DOVARIABLE
- PFA_TIB:
-000268 013d .dw ram_tib
- .dseg
-00013d ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-000269 ff04 .dw $ff04
-00026a 7423
-00026b 6269 .db "#tib"
-00026c 0263 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00026d 3847 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00026e 0197 .dw ram_sharptib
- .dseg
-000197 ram_sharptib: .byte 2
- .cseg
- .endif
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00026f ff06 .dw $ff06
-000270 6565
-000271 723e
-000272 6d61 .db "ee>ram"
-000273 0269 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-000274 3800 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-000275 3953 .dw XT_ZERO
-000276 3a9a .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-000277 38ce .dw XT_OVER
-000278 3b5e .dw XT_FETCHE
-000279 38ce .dw XT_OVER
-00027a 3880 .dw XT_STORE
-00027b 3c8f .dw XT_CELLPLUS
-00027c 38c3 .dw XT_SWAP
-00027d 3c8f .dw XT_CELLPLUS
-00027e 38c3 .dw XT_SWAP
-00027f 3ac8 .dw XT_DOLOOP
-000280 0277 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-000281 3ed1 .dw XT_2DROP
-000282 381f .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-000283 ff08 .dw $ff08
-000284 6e69
-000285 7469
-000286 722d
-000287 6d61 .db "init-ram"
-000288 026f .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-000289 3800 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-00028a 383c .dw XT_DOLITERAL
-00028b 008c .dw EE_INITUSER
-00028c 3b01 .dw XT_UP_FETCH
-00028d 383c .dw XT_DOLITERAL
-00028e 0022 .dw SYSUSERSIZE
-00028f 3a03 .dw XT_2SLASH
-000290 0274 .dw XT_EE2RAM
-000291 381f .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-000292 ff0b .dw $ff0b
-000293 6e65
-000294 6976
-000295 6f72
-000296 6d6e
-000297 6e65
-000298 0074 .db "environment",0
-000299 0283 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-00029a 3847 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-00029b 0066 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00029c ff09 .dw $ff09
-00029d 6f77
-00029e 6472
-00029f 696c
-0002a0 7473
-0002a1 0073 .db "wordlists",0
-0002a2 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-0002a3 3800 .dw DO_COLON
- PFA_ENVWORDLISTS:
-0002a4 383c .dw XT_DOLITERAL
-0002a5 0008 .dw NUMWORDLISTS
-0002a6 381f .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-0002a7 ff04 .dw $ff04
-0002a8 702f
-0002a9 6461 .db "/pad"
-0002aa 029c .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-0002ab 3800 .dw DO_COLON
- PFA_ENVSLASHPAD:
-0002ac 3a8c .dw XT_SP_FETCH
-0002ad 3ee7 .dw XT_PAD
-0002ae 3992 .dw XT_MINUS
-0002af 381f .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-0002b0 ff05 .dw $ff05
-0002b1 682f
-0002b2 6c6f
-0002b3 0064 .db "/hold",0
-0002b4 02a7 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-0002b5 3800 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-0002b6 3ee7 .dw XT_PAD
-0002b7 3f22 .dw XT_HERE
-0002b8 3992 .dw XT_MINUS
-0002b9 381f .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-0002ba ff0a .dw $ff0a
-0002bb 6f66
-0002bc 7472
-0002bd 2d68
-0002be 616e
-0002bf 656d .db "forth-name"
-0002c0 02b0 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-0002c1 3800 .dw DO_COLON
- PFA_EN_FORTHNAME:
-0002c2 03b7 .dw XT_DOSLITERAL
-0002c3 0007 .dw 7
- .endif
-0002c4 6d61
-0002c5 6f66
-0002c6 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-0002c7 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-0002c8 381f .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-0002c9 ff07 .dw $ff07
-0002ca 6576
-0002cb 7372
-0002cc 6f69
-0002cd 006e .db "version",0
-0002ce 02ba .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-0002cf 3800 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-0002d0 383c .dw XT_DOLITERAL
-0002d1 0041 .dw 65
-0002d2 381f .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-0002d3 ff03 .dw $ff03
-0002d4 7063
-0002d5 0075 .db "cpu",0
-0002d6 02c9 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-0002d7 3800 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-0002d8 383c .dw XT_DOLITERAL
-0002d9 0059 .dw mcu_name
-0002da 0416 .dw XT_ICOUNT
-0002db 381f .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-0002dc ff08 .dw $ff08
-0002dd 636d
-0002de 2d75
-0002df 6e69
-0002e0 6f66 .db "mcu-info"
-0002e1 02d3 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-0002e2 3800 .dw DO_COLON
- PFA_EN_MCUINFO:
-0002e3 383c .dw XT_DOLITERAL
-0002e4 0055 .dw mcu_info
-0002e5 381f .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-0002e6 ff05 .dw $ff05
-0002e7 752f
-0002e8 6573
-0002e9 0072 .db "/user",0
-0002ea 02dc .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-0002eb 3800 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-0002ec 383c .dw XT_DOLITERAL
-0002ed 002c .dw SYSUSERSIZE + APPUSERSIZE
-0002ee 381f .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-0002ef ff03 .dw $ff03
-0002f0 6c68
-0002f1 0064 .db "hld",0
-0002f2 0292 .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-0002f3 3847 .dw PFA_DOVARIABLE
- PFA_HLD:
-0002f4 0199 .dw ram_hld
-
- .dseg
-000199 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-0002f5 ff04 .dw $ff04
-0002f6 6f68
-0002f7 646c .db "hold"
-0002f8 02ef .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-0002f9 3800 .dw DO_COLON
- PFA_HOLD:
- .endif
-0002fa 02f3 .dw XT_HLD
-0002fb 38b0 .dw XT_DUP
-0002fc 3878 .dw XT_FETCH
-0002fd 3a34 .dw XT_1MINUS
-0002fe 38b0 .dw XT_DUP
-0002ff 38fe .dw XT_TO_R
-000300 38c3 .dw XT_SWAP
-000301 3880 .dw XT_STORE
-000302 38f5 .dw XT_R_FROM
-000303 388c .dw XT_CSTORE
-000304 381f .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-000305 ff02 .dw $ff02
-000306 233c .db "<#"
-000307 02f5 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-000308 3800 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-000309 3ee7 .dw XT_PAD
-00030a 02f3 .dw XT_HLD
-00030b 3880 .dw XT_STORE
-00030c 381f .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-00030d ff01 .dw $ff01
-00030e 0023 .db "#",0
-00030f 0305 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-000310 3800 .dw DO_COLON
- PFA_SHARP:
- .endif
-000311 3ebc .dw XT_BASE
-000312 3878 .dw XT_FETCH
-000313 038d .dw XT_UDSLASHMOD
-000314 38e0 .dw XT_ROT
-000315 383c .dw XT_DOLITERAL
-000316 0009 .dw 9
-000317 38ce .dw XT_OVER
-000318 396d .dw XT_LESS
-000319 3835 .dw XT_DOCONDBRANCH
-00031a 031e DEST(PFA_SHARP1)
-00031b 383c .dw XT_DOLITERAL
-00031c 0007 .dw 7
-00031d 399c .dw XT_PLUS
- PFA_SHARP1:
-00031e 383c .dw XT_DOLITERAL
-00031f 0030 .dw 48 ; ASCII 0
-000320 399c .dw XT_PLUS
-000321 02f9 .dw XT_HOLD
-000322 381f .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-000323 ff02 .dw $ff02
-000324 7323 .db "#s"
-000325 030d .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-000326 3800 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000327 0310 .dw XT_SHARP
-000328 3ec8 .dw XT_2DUP
-000329 3a1b .dw XT_OR
-00032a 3919 .dw XT_ZEROEQUAL
-00032b 3835 .dw XT_DOCONDBRANCH
-00032c 0327 DEST(NUMS1) ; PFA_SHARP_S
-00032d 381f .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00032e ff02 .dw $ff02
-00032f 3e23 .db "#>"
-000330 0323 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-000331 3800 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-000332 3ed1 .dw XT_2DROP
-000333 02f3 .dw XT_HLD
-000334 3878 .dw XT_FETCH
-000335 3ee7 .dw XT_PAD
-000336 38ce .dw XT_OVER
-000337 3992 .dw XT_MINUS
-000338 381f .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000339 ff04 .dw $ff04
-00033a 6973
-00033b 6e67 .db "sign"
-00033c 032e .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00033d 3800 .dw DO_COLON
- PFA_SIGN:
- .endif
-00033e 3920 .dw XT_ZEROLESS
-00033f 3835 .dw XT_DOCONDBRANCH
-000340 0344 DEST(PFA_SIGN1)
-000341 383c .dw XT_DOLITERAL
-000342 002d .dw 45 ; ascii -
-000343 02f9 .dw XT_HOLD
- PFA_SIGN1:
-000344 381f .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-000345 ff03 .dw $ff03
-000346 2e64
-000347 0072 .db "d.r",0
-000348 0339 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000349 3800 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-00034a 38fe .dw XT_TO_R
-00034b 3ed9 .dw XT_TUCK
-00034c 020d .dw XT_DABS
-00034d 0308 .dw XT_L_SHARP
-00034e 0326 .dw XT_SHARP_S
-00034f 38e0 .dw XT_ROT
-000350 033d .dw XT_SIGN
-000351 0331 .dw XT_SHARP_G
-000352 38f5 .dw XT_R_FROM
-000353 38ce .dw XT_OVER
-000354 3992 .dw XT_MINUS
-000355 3fb6 .dw XT_SPACES
-000356 0420 .dw XT_TYPE
-000357 381f .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000358 ff02 .dw $ff02
-000359 722e .db ".r"
-00035a 0345 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-00035b 3800 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-00035c 38fe .dw XT_TO_R
-00035d 3fc6 .dw XT_S2D
-00035e 38f5 .dw XT_R_FROM
-00035f 0349 .dw XT_DDOTR
-000360 381f .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-000361 ff02 .dw $ff02
-000362 2e64 .db "d."
-000363 0358 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-000364 3800 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-000365 3953 .dw XT_ZERO
-000366 0349 .dw XT_DDOTR
-000367 3fad .dw XT_SPACE
-000368 381f .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-000369 ff01 .dw $ff01
-00036a 002e .db ".",0
-00036b 0361 .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-00036c 3800 .dw DO_COLON
- PFA_DOT:
- .endif
-00036d 3fc6 .dw XT_S2D
-00036e 0364 .dw XT_DDOT
-00036f 381f .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-000370 ff03 .dw $ff03
-000371 6475
-000372 002e .db "ud.",0
-000373 0369 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-000374 3800 .dw DO_COLON
- PFA_UDDOT:
- .endif
-000375 3953 .dw XT_ZERO
-000376 037d .dw XT_UDDOTR
-000377 3fad .dw XT_SPACE
-000378 381f .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-000379 ff04 .dw $ff04
-00037a 6475
-00037b 722e .db "ud.r"
-00037c 0370 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-00037d 3800 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-00037e 38fe .dw XT_TO_R
-00037f 0308 .dw XT_L_SHARP
-000380 0326 .dw XT_SHARP_S
-000381 0331 .dw XT_SHARP_G
-000382 38f5 .dw XT_R_FROM
-000383 38ce .dw XT_OVER
-000384 3992 .dw XT_MINUS
-000385 3fb6 .dw XT_SPACES
-000386 0420 .dw XT_TYPE
-000387 381f .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-000388 ff06 .dw $ff06
-000389 6475
-00038a 6d2f
-00038b 646f .db "ud/mod"
-00038c 0379 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-00038d 3800 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-00038e 38fe .dw XT_TO_R
-00038f 3953 .dw XT_ZERO
-000390 3907 .dw XT_R_FETCH
-000391 39c1 .dw XT_UMSLASHMOD
-000392 38f5 .dw XT_R_FROM
-000393 38c3 .dw XT_SWAP
-000394 38fe .dw XT_TO_R
-000395 39c1 .dw XT_UMSLASHMOD
-000396 38f5 .dw XT_R_FROM
-000397 381f .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-000398 ff06 .dw $ff06
-000399 6964
-00039a 6967
-00039b 3f74 .db "digit?"
-00039c 0388 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-00039d 3800 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-00039e 3f65 .dw XT_TOUPPER
-00039f 38b0
-0003a0 383c
-0003a1 0039
-0003a2 3977
-0003a3 383c
-0003a4 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-0003a5 3a12
-0003a6 399c
-0003a7 38b0
-0003a8 383c
-0003a9 0140
-0003aa 3977 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-0003ab 383c
-0003ac 0107
-0003ad 3a12
-0003ae 3992
-0003af 383c
-0003b0 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-0003b1 3992
-0003b2 38b0
-0003b3 3ebc
-0003b4 3878
-0003b5 395b .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-0003b6 381f .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-0003b7 3800 .dw DO_COLON
- PFA_DOSLITERAL:
-0003b8 3907 .dw XT_R_FETCH ; ( -- addr )
-0003b9 0416 .dw XT_ICOUNT
-0003ba 38f5 .dw XT_R_FROM
-0003bb 38ce .dw XT_OVER ; ( -- addr' n addr n)
-0003bc 3a2e .dw XT_1PLUS
-0003bd 3a03 .dw XT_2SLASH ; ( -- addr' n addr k )
-0003be 399c .dw XT_PLUS ; ( -- addr' n addr'' )
-0003bf 3a2e .dw XT_1PLUS
-0003c0 38fe .dw XT_TO_R ; ( -- )
-0003c1 381f .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-0003c2 ff02 .dw $ff02
-0003c3 2c73 .db "s",$2c
-0003c4 0398 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-0003c5 3800 .dw DO_COLON
- PFA_SCOMMA:
-0003c6 38b0 .dw XT_DUP
-0003c7 03c9 .dw XT_DOSCOMMA
-0003c8 381f .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-0003c9 3800 .dw DO_COLON
- PFA_DOSCOMMA:
-0003ca 074e .dw XT_COMMA
-0003cb 38b0 .dw XT_DUP ; ( --addr len len)
-0003cc 3a03 .dw XT_2SLASH ; ( -- addr len len/2
-0003cd 3ed9 .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003ce 3a0a .dw XT_2STAR ; ( -- addr len/2 len len'
-0003cf 3992 .dw XT_MINUS ; ( -- addr len/2 rem
-0003d0 38fe .dw XT_TO_R
-0003d1 3953 .dw XT_ZERO
-0003d2 080d .dw XT_QDOCHECK
-0003d3 3835 .dw XT_DOCONDBRANCH
-0003d4 03dc .dw PFA_SCOMMA2
-0003d5 3a9a .dw XT_DODO
- PFA_SCOMMA1:
-0003d6 38b0 .dw XT_DUP ; ( -- addr addr )
-0003d7 3878 .dw XT_FETCH ; ( -- addr c1c2 )
-0003d8 074e .dw XT_COMMA ; ( -- addr )
-0003d9 3c8f .dw XT_CELLPLUS ; ( -- addr+cell )
-0003da 3ac8 .dw XT_DOLOOP
-0003db 03d6 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-0003dc 38f5 .dw XT_R_FROM
-0003dd 3927 .dw XT_GREATERZERO
-0003de 3835 .dw XT_DOCONDBRANCH
-0003df 03e3 .dw PFA_SCOMMA3
-0003e0 38b0 .dw XT_DUP ; well, tricky
-0003e1 3897 .dw XT_CFETCH
-0003e2 074e .dw XT_COMMA
- PFA_SCOMMA3:
-0003e3 38d8 .dw XT_DROP ; ( -- )
-0003e4 381f .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-0003e5 ff05 .dw $ff05
-0003e6 7469
-0003e7 7079
-0003e8 0065 .db "itype",0
-0003e9 03c2 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-0003ea 3800 .dw DO_COLON
- PFA_ITYPE:
-0003eb 38b0 .dw XT_DUP ; ( --addr len len)
-0003ec 3a03 .dw XT_2SLASH ; ( -- addr len len/2
-0003ed 3ed9 .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003ee 3a0a .dw XT_2STAR ; ( -- addr len/2 len len'
-0003ef 3992 .dw XT_MINUS ; ( -- addr len/2 rem
-0003f0 38fe .dw XT_TO_R
-0003f1 3953 .dw XT_ZERO
-0003f2 080d .dw XT_QDOCHECK
-0003f3 3835 .dw XT_DOCONDBRANCH
-0003f4 03fe .dw PFA_ITYPE2
-0003f5 3a9a .dw XT_DODO
- PFA_ITYPE1:
-0003f6 38b0 .dw XT_DUP ; ( -- addr addr )
-0003f7 3bca .dw XT_FETCHI ; ( -- addr c1c2 )
-0003f8 38b0 .dw XT_DUP
-0003f9 040b .dw XT_LOWEMIT
-0003fa 0407 .dw XT_HIEMIT
-0003fb 3a2e .dw XT_1PLUS ; ( -- addr+cell )
-0003fc 3ac8 .dw XT_DOLOOP
-0003fd 03f6 .dw PFA_ITYPE1
- PFA_ITYPE2:
-0003fe 38f5 .dw XT_R_FROM
-0003ff 3927 .dw XT_GREATERZERO
-000400 3835 .dw XT_DOCONDBRANCH
-000401 0405 .dw PFA_ITYPE3
-000402 38b0 .dw XT_DUP ; make sure the drop below has always something to do
-000403 3bca .dw XT_FETCHI
-000404 040b .dw XT_LOWEMIT
- PFA_ITYPE3:
-000405 38d8 .dw XT_DROP
-000406 381f .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-000407 3800 .dw DO_COLON
- PFA_HIEMIT:
-000408 3af8 .dw XT_BYTESWAP
-000409 040b .dw XT_LOWEMIT
-00040a 381f .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-00040b 3800 .dw DO_COLON
- PFA_LOWEMIT:
-00040c 383c .dw XT_DOLITERAL
-00040d 00ff .dw $00ff
-00040e 3a12 .dw XT_AND
-00040f 3ef1 .dw XT_EMIT
-000410 381f .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-000411 ff06 .dw $ff06
-000412 6369
-000413 756f
-000414 746e .db "icount"
-000415 03e5 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-000416 3800 .dw DO_COLON
- PFA_ICOUNT:
-000417 38b0 .dw XT_DUP
-000418 3a2e .dw XT_1PLUS
-000419 38c3 .dw XT_SWAP
-00041a 3bca .dw XT_FETCHI
-00041b 381f .dw XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-00041c ff04 .dw $ff04
-00041d 7974
-00041e 6570 .db "type"
-00041f 0411 .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-000420 3800 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-000421 3f98 .dw XT_BOUNDS
-000422 080d .dw XT_QDOCHECK
-000423 3835 .dw XT_DOCONDBRANCH
-000424 042b DEST(PFA_TYPE2)
-000425 3a9a .dw XT_DODO
- PFA_TYPE1:
-000426 3aab .dw XT_I
-000427 3897 .dw XT_CFETCH
-000428 3ef1 .dw XT_EMIT
-000429 3ac8 .dw XT_DOLOOP
-00042a 0426 DEST(PFA_TYPE1)
- PFA_TYPE2:
-00042b 381f .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00042c ff01 .dw $ff01
-00042d 0027 .db "'",0
-00042e 041c .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00042f 3800 .dw DO_COLON
- PFA_TICK:
- .endif
-000430 05a2 .dw XT_PARSENAME
-000431 05e5 .dw XT_FORTHRECOGNIZER
-000432 05f0 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-000433 38b0 .dw XT_DUP
-000434 067d .dw XT_DT_NULL
-000435 3fde .dw XT_EQUAL
-000436 38c3 .dw XT_SWAP
-000437 3bca .dw XT_FETCHI
-000438 383c .dw XT_DOLITERAL
-000439 017b .dw XT_NOOP
-00043a 3fde .dw XT_EQUAL
-00043b 3a1b .dw XT_OR
-00043c 3835 .dw XT_DOCONDBRANCH
-00043d 0441 DEST(PFA_TICK1)
-00043e 383c .dw XT_DOLITERAL
-00043f fff3 .dw -13
-000440 3d85 .dw XT_THROW
- PFA_TICK1:
-000441 38d8 .dw XT_DROP
-000442 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-000443 ff05 .dw $ff05
-000444 7363
-000445 696b
-000446 0070 .db "cskip",0
-000447 042c .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-000448 3800 .dw DO_COLON
- PFA_CSKIP:
- .endif
-000449 38fe .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-00044a 38b0 .dw XT_DUP ; ( -- addr' n' n' )
-00044b 3835 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00044c 0457 DEST(PFA_CSKIP2)
-00044d 38ce .dw XT_OVER ; ( -- addr' n' addr' )
-00044e 3897 .dw XT_CFETCH ; ( -- addr' n' c' )
-00044f 3907 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-000450 3fde .dw XT_EQUAL ; ( -- addr' n' f )
-000451 3835 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000452 0457 DEST(PFA_CSKIP2)
-000453 3fe5 .dw XT_ONE
-000454 0593 .dw XT_SLASHSTRING
-000455 382e .dw XT_DOBRANCH
-000456 044a DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-000457 38f5 .dw XT_R_FROM
-000458 38d8 .dw XT_DROP ; ( -- addr2 n2)
-000459 381f .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-00045a ff05 .dw $ff05
-00045b 7363
-00045c 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00045d 006e .db "cscan"
-00045e 0443 .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-00045f 3800 .dw DO_COLON
- PFA_CSCAN:
- .endif
-000460 38fe .dw XT_TO_R
-000461 38ce .dw XT_OVER
- PFA_CSCAN1:
-000462 38b0 .dw XT_DUP
-000463 3897 .dw XT_CFETCH
-000464 3907 .dw XT_R_FETCH
-000465 3fde .dw XT_EQUAL
-000466 3919 .dw XT_ZEROEQUAL
-000467 3835 .dw XT_DOCONDBRANCH
-000468 0474 DEST(PFA_CSCAN2)
-000469 38c3 .dw XT_SWAP
-00046a 3a34 .dw XT_1MINUS
-00046b 38c3 .dw XT_SWAP
-00046c 38ce .dw XT_OVER
-00046d 3920 .dw XT_ZEROLESS ; not negative
-00046e 3919 .dw XT_ZEROEQUAL
-00046f 3835 .dw XT_DOCONDBRANCH
-000470 0474 DEST(PFA_CSCAN2)
-000471 3a2e .dw XT_1PLUS
-000472 382e .dw XT_DOBRANCH
-000473 0462 DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-000474 38ef .dw XT_NIP
-000475 38ce .dw XT_OVER
-000476 3992 .dw XT_MINUS
-000477 38f5 .dw XT_R_FROM
-000478 38d8 .dw XT_DROP
-000479 381f .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-00047a ff06 .dw $ff06
-00047b 6361
-00047c 6563
-00047d 7470 .db "accept"
-00047e 045a .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-00047f 3800 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-000480 38ce
-000481 399c
-000482 3a34
-000483 38ce .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-000484 3f02
-000485 38b0
-000486 04c0
-000487 3919
-000488 3835 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-000489 04b2 DEST(ACC5)
-00048a 38b0
-00048b 383c
-00048c 0008
-00048d 3fde
-00048e 3835 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-00048f 04a2 DEST(ACC3)
-000490 38d8
-000491 38e0
-000492 3ec8
-000493 3977
-000494 38fe
-000495 38e0
-000496 38e0
-000497 38f5
-000498 3835 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-000499 04a0 DEST(ACC6)
-00049a 04b8
-00049b 3a34
-00049c 38fe
-00049d 38ce
-00049e 38f5
-00049f 0130 .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-0004a0 382e ACC6: .DW XT_DOBRANCH
-0004a1 04b0 DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-0004a2 38b0 .dw XT_DUP ; ( -- addr k k )
-0004a3 3f53 .dw XT_BL
-0004a4 396d .dw XT_LESS
-0004a5 3835 .dw XT_DOCONDBRANCH
-0004a6 04a9 DEST(PFA_ACCEPT6)
-0004a7 38d8 .dw XT_DROP
-0004a8 3f53 .dw XT_BL
- PFA_ACCEPT6:
-0004a9 38b0
-0004aa 3ef1
-0004ab 38ce
-0004ac 388c
-0004ad 3a2e
-0004ae 38ce
-0004af 013c .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-0004b0 382e ACC4: .DW XT_DOBRANCH
-0004b1 0484 DEST(ACC1)
-0004b2 38d8
-0004b3 38ef
-0004b4 38c3
-0004b5 3992
-0004b6 3fa0
-0004b7 381f ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-0004b8 3800 .dw DO_COLON
- .endif
-0004b9 383c .dw XT_DOLITERAL
-0004ba 0008 .dw 8
-0004bb 38b0 .dw XT_DUP
-0004bc 3ef1 .dw XT_EMIT
-0004bd 3fad .dw XT_SPACE
-0004be 3ef1 .dw XT_EMIT
-0004bf 381f .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-0004c0 3800 .dw DO_COLON
- .endif
-0004c1 38b0 .dw XT_DUP
-0004c2 383c .dw XT_DOLITERAL
-0004c3 000d .dw 13
-0004c4 3fde .dw XT_EQUAL
-0004c5 38c3 .dw XT_SWAP
-0004c6 383c .dw XT_DOLITERAL
-0004c7 000a .dw 10
-0004c8 3fde .dw XT_EQUAL
-0004c9 3a1b .dw XT_OR
-0004ca 381f .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-0004cb ff06 .dw $ff06
-0004cc 6572
-0004cd 6966
-0004ce 6c6c .db "refill"
-0004cf 047a .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-0004d0 3dfe .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-0004d1 001a .dw USER_REFILL
-0004d2 3dc7 .dw XT_UDEFERFETCH
-0004d3 3dd3 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-0004d4 ff04 .dw $ff04
-0004d5 6863
-0004d6 7261 .db "char"
-0004d7 04cb .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-0004d8 3800 .dw DO_COLON
- PFA_CHAR:
- .endif
-0004d9 05a2 .dw XT_PARSENAME
-0004da 38d8 .dw XT_DROP
-0004db 3897 .dw XT_CFETCH
-0004dc 381f .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-0004dd ff06 .dw $ff06
-0004de 756e
-0004df 626d
-0004e0 7265 .db "number"
-0004e1 04d4 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-0004e2 3800 .dw DO_COLON
- PFA_NUMBER:
- .endif
-0004e3 3ebc .dw XT_BASE
-0004e4 3878 .dw XT_FETCH
-0004e5 38fe .dw XT_TO_R
-0004e6 0526 .dw XT_QSIGN
-0004e7 38fe .dw XT_TO_R
-0004e8 0539 .dw XT_SET_BASE
-0004e9 0526 .dw XT_QSIGN
-0004ea 38f5 .dw XT_R_FROM
-0004eb 3a1b .dw XT_OR
-0004ec 38fe .dw XT_TO_R
- ; check whether something is left
-0004ed 38b0 .dw XT_DUP
-0004ee 3919 .dw XT_ZEROEQUAL
-0004ef 3835 .dw XT_DOCONDBRANCH
-0004f0 04f9 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-0004f1 3ed1 .dw XT_2DROP
-0004f2 38f5 .dw XT_R_FROM
-0004f3 38d8 .dw XT_DROP
-0004f4 38f5 .dw XT_R_FROM
-0004f5 3ebc .dw XT_BASE
-0004f6 3880 .dw XT_STORE
-0004f7 3953 .dw XT_ZERO
-0004f8 381f .dw XT_EXIT
- PFA_NUMBER0:
-0004f9 3b1d .dw XT_2TO_R
-0004fa 3953 .dw XT_ZERO ; starting value
-0004fb 3953 .dw XT_ZERO
-0004fc 3b2c .dw XT_2R_FROM
-0004fd 0557 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-0004fe 38b8 .dw XT_QDUP
-0004ff 3835 .dw XT_DOCONDBRANCH
-000500 051b DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-000501 3fe5 .dw XT_ONE
-000502 3fde .dw XT_EQUAL
-000503 3835 .dw XT_DOCONDBRANCH
-000504 0512 DEST(PFA_NUMBER2)
- ; excatly one character is left
-000505 3897 .dw XT_CFETCH
-000506 383c .dw XT_DOLITERAL
-000507 002e .dw 46 ; .
-000508 3fde .dw XT_EQUAL
-000509 3835 .dw XT_DOCONDBRANCH
-00050a 0513 DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-00050b 38f5 .dw XT_R_FROM
-00050c 3835 .dw XT_DOCONDBRANCH
-00050d 050f DEST(PFA_NUMBER3)
-00050e 021a .dw XT_DNEGATE
- PFA_NUMBER3:
-00050f 3fea .dw XT_TWO
-000510 382e .dw XT_DOBRANCH
-000511 0521 DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-000512 38d8 .dw XT_DROP
- PFA_NUMBER6:
-000513 3ed1 .dw XT_2DROP
-000514 38f5 .dw XT_R_FROM
-000515 38d8 .dw XT_DROP
-000516 38f5 .dw XT_R_FROM
-000517 3ebc .dw XT_BASE
-000518 3880 .dw XT_STORE
-000519 3953 .dw XT_ZERO
-00051a 381f .dw XT_EXIT
- PFA_NUMBER1:
-00051b 3ed1 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-00051c 38f5 .dw XT_R_FROM
-00051d 3835 .dw XT_DOCONDBRANCH
-00051e 0520 DEST(PFA_NUMBER4)
-00051f 3e26 .dw XT_NEGATE
- PFA_NUMBER4:
-000520 3fe5 .dw XT_ONE
- PFA_NUMBER5:
-000521 38f5 .dw XT_R_FROM
-000522 3ebc .dw XT_BASE
-000523 3880 .dw XT_STORE
-000524 394a .dw XT_TRUE
-000525 381f .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-000526 3800 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-000527 38ce .dw XT_OVER ; ( -- addr len addr )
-000528 3897 .dw XT_CFETCH
-000529 383c .dw XT_DOLITERAL
-00052a 002d .dw '-'
-00052b 3fde .dw XT_EQUAL ; ( -- addr len flag )
-00052c 38b0 .dw XT_DUP
-00052d 38fe .dw XT_TO_R
-00052e 3835 .dw XT_DOCONDBRANCH
-00052f 0532 DEST(PFA_NUMBERSIGN_DONE)
-000530 3fe5 .dw XT_ONE ; skip sign character
-000531 0593 .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-000532 38f5 .dw XT_R_FROM
-000533 381f .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-000534 3851 .dw PFA_DOCONSTANT
- .endif
-000535 000a
-000536 0010
-000537 0002
-000538 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-000539 3800 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-00053a 38ce .dw XT_OVER
-00053b 3897 .dw XT_CFETCH
-00053c 383c .dw XT_DOLITERAL
-00053d 0023 .dw 35
-00053e 3992 .dw XT_MINUS
-00053f 38b0 .dw XT_DUP
-000540 3953 .dw XT_ZERO
-000541 383c .dw XT_DOLITERAL
-000542 0004 .dw 4
-000543 3e56 .dw XT_WITHIN
-000544 3835 .dw XT_DOCONDBRANCH
-000545 054f DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-000546 0534 .dw XT_BASES
-000547 399c .dw XT_PLUS
-000548 3bca .dw XT_FETCHI
-000549 3ebc .dw XT_BASE
-00054a 3880 .dw XT_STORE
-00054b 3fe5 .dw XT_ONE
-00054c 0593 .dw XT_SLASHSTRING
-00054d 382e .dw XT_DOBRANCH
-00054e 0550 DEST(SET_BASE2)
- SET_BASE1:
-00054f 38d8 .dw XT_DROP
- SET_BASE2:
-000550 381f .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-000551 ff07 .dw $ff07
-000552 6e3e
-000553 6d75
-000554 6562
-000555 0072 .db ">number",0
-000556 04dd .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-000557 3800 .dw DO_COLON
-
- .endif
-
-000558 38b0
-000559 3835 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-00055a 056f DEST(TONUM3)
-00055b 38ce
-00055c 3897
-00055d 039d .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-00055e 3919
-00055f 3835 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-000560 0563 DEST(TONUM2)
-000561 38d8
-000562 381f .DW XT_DROP,XT_EXIT
-000563 38fe
-000564 023e
-000565 3ebc
-000566 3878
-000567 0121 TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000568 38f5
-000569 0119
-00056a 023e .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-00056b 3fe5
-00056c 0593
-00056d 382e .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-00056e 0558 DEST(TONUM1)
-00056f 381f TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-000570 ff05 .dw $ff05
-000571 6170
-000572 7372
-000573 0065 .db "parse",0
-000574 0551 .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-000575 3800 .dw DO_COLON
- PFA_PARSE:
- .endif
-000576 38fe .dw XT_TO_R ; ( -- )
-000577 0589 .dw XT_SOURCE ; ( -- addr len)
-000578 3ee1 .dw XT_TO_IN ; ( -- addr len >in)
-000579 3878 .dw XT_FETCH
-00057a 0593 .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-00057b 38f5 .dw XT_R_FROM ; ( -- addr' len' c)
-00057c 045f .dw XT_CSCAN ; ( -- addr' len'')
-00057d 38b0 .dw XT_DUP ; ( -- addr' len'' len'')
-00057e 3a2e .dw XT_1PLUS
-00057f 3ee1 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-000580 3a64 .dw XT_PLUSSTORE ; ( -- addr' len')
-000581 3fe5 .dw XT_ONE
-000582 0593 .dw XT_SLASHSTRING
-000583 381f .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-000584 ff06 .dw $FF06
-000585 6f73
-000586 7275
-000587 6563 .db "source"
-000588 0570 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-000589 3dfe .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-00058a 0016 .dw USER_SOURCE
-00058b 3dc7 .dw XT_UDEFERFETCH
-00058c 3dd3 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00058d ff07 .dw $ff07
-00058e 732f
-00058f 7274
-000590 6e69
-000591 0067 .db "/string",0
-000592 0584 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-000593 3800 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-000594 38e0 .dw XT_ROT
-000595 38ce .dw XT_OVER
-000596 399c .dw XT_PLUS
-000597 38e0 .dw XT_ROT
-000598 38e0 .dw XT_ROT
-000599 3992 .dw XT_MINUS
-00059a 381f .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-00059b ff0a .dw $FF0A
-00059c 6170
-00059d 7372
-00059e 2d65
-00059f 616e
-0005a0 656d .db "parse-name"
-0005a1 058d .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-0005a2 3800 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-0005a3 3f53 .dw XT_BL
-0005a4 05a6 .dw XT_SKIPSCANCHAR
-0005a5 381f .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-0005a6 3800 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-0005a7 38fe .dw XT_TO_R
-0005a8 0589 .dw XT_SOURCE
-0005a9 3ee1 .dw XT_TO_IN
-0005aa 3878 .dw XT_FETCH
-0005ab 0593 .dw XT_SLASHSTRING
-
-0005ac 3907 .dw XT_R_FETCH
-0005ad 0448 .dw XT_CSKIP
-0005ae 38f5 .dw XT_R_FROM
-0005af 045f .dw XT_CSCAN
-
- ; adjust >IN
-0005b0 3ec8 .dw XT_2DUP
-0005b1 399c .dw XT_PLUS
-0005b2 0589 .dw XT_SOURCE
-0005b3 38d8 .dw XT_DROP
-0005b4 3992 .dw XT_MINUS
-0005b5 3ee1 .dw XT_TO_IN
-0005b6 3880 .dw XT_STORE
-0005b7 381f .dw XT_EXIT
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-0005b8 ff03 .dw $ff03
-0005b9 7073
-0005ba 0030 .db "sp0",0
-0005bb 059b .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-0005bc 386e .dw PFA_DOVALUE1
- PFA_SP0:
-0005bd 0006 .dw USER_SP0
-0005be 3dc7 .dw XT_UDEFERFETCH
-0005bf 3dd3 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-0005c0 ff02 .dw $ff02
-0005c1 7073 .db "sp"
-0005c2 05b8 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-0005c3 3857 .dw PFA_DOUSER
- PFA_SP:
-0005c4 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-0005c5 ff03 .dw $ff03
-0005c6 7072
-0005c7 0030 .db "rp0",0
-0005c8 05c0 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-0005c9 3800 .dw DO_COLON
- PFA_RP0:
-0005ca 05cd .dw XT_DORP0
-0005cb 3878 .dw XT_FETCH
-0005cc 381f .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-0005cd 3857 .dw PFA_DOUSER
- PFA_DORP0:
-0005ce 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-0005cf ff05 .dw $ff05
-0005d0 6564
-0005d1 7470
-0005d2 0068 .db "depth",0
-0005d3 05c5 .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-0005d4 3800 .dw DO_COLON
- PFA_DEPTH:
- .endif
-0005d5 05bc .dw XT_SP0
-0005d6 3a8c .dw XT_SP_FETCH
-0005d7 3992 .dw XT_MINUS
-0005d8 3a03 .dw XT_2SLASH
-0005d9 3a34 .dw XT_1MINUS
-0005da 381f .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-0005db ff10 .dw $ff10
-0005dc 6f66
-0005dd 7472
-0005de 2d68
-0005df 6572
-0005e0 6f63
-0005e1 6e67
-0005e2 7a69
-0005e3 7265 .db "forth-recognizer"
-0005e4 05cf .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-0005e5 386e .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-0005e6 0060 .dw CFG_FORTHRECOGNIZER
-0005e7 3d9f .dw XT_EDEFERFETCH
-0005e8 3da9 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-0005e9 ff09 .dw $ff09
-0005ea 6572
-0005eb 6f63
-0005ec 6e67
-0005ed 7a69
-0005ee 0065 .db "recognize",0
-0005ef 05db .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-0005f0 3800 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-0005f1 383c .dw XT_DOLITERAL
-0005f2 05fb .dw XT_RECOGNIZE_A
-0005f3 38c3 .dw XT_SWAP
-0005f4 098e .dw XT_MAPSTACK
-0005f5 3919 .dw XT_ZEROEQUAL
-0005f6 3835 .dw XT_DOCONDBRANCH
-0005f7 05fa DEST(PFA_RECOGNIZE1)
-0005f8 3ed1 .dw XT_2DROP
-0005f9 067d .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-0005fa 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-0005fb 3800 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-0005fc 38e0 .dw XT_ROT ; -- len xt addr
-0005fd 38e0 .dw XT_ROT ; -- xt addr len
-0005fe 3ec8 .dw XT_2DUP
-0005ff 3b1d .dw XT_2TO_R
-000600 38e0 .dw XT_ROT ; -- addr len xt
-000601 3829 .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-000602 3b2c .dw XT_2R_FROM
-000603 38e0 .dw XT_ROT
-000604 38b0 .dw XT_DUP
-000605 067d .dw XT_DT_NULL
-000606 3fde .dw XT_EQUAL
-000607 3835 .dw XT_DOCONDBRANCH
-000608 060c DEST(PFA_RECOGNIZE_A1)
-000609 38d8 .dw XT_DROP
-00060a 3953 .dw XT_ZERO
-00060b 381f .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-00060c 38ef .dw XT_NIP
-00060d 38ef .dw XT_NIP
-00060e 394a .dw XT_TRUE
-00060f 381f .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-000610 ff09 .dw $ff09
-000611 6e69
-000612 6574
-000613 7072
-000614 6572
-000615 0074 .db "interpret",0
-000616 05e9 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-000617 3800 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-000618 05a2 .dw XT_PARSENAME ; ( -- addr len )
-000619 38b0 .dw XT_DUP ; ( -- addr len flag)
-00061a 3835 .dw XT_DOCONDBRANCH
-00061b 0628 DEST(PFA_INTERPRET2)
-00061c 05e5 .dw XT_FORTHRECOGNIZER
-00061d 05f0 .dw XT_RECOGNIZE
-00061e 3eb6 .dw XT_STATE
-00061f 3878 .dw XT_FETCH
-000620 3835 .dw XT_DOCONDBRANCH
-000621 0623 DEST(PFA_INTERPRET1)
-000622 01a7 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-000623 3bca .dw XT_FETCHI
-000624 3829 .dw XT_EXECUTE
-000625 3f8a .dw XT_QSTACK
-000626 382e .dw XT_DOBRANCH
-000627 0618 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000628 3ed1 .dw XT_2DROP
-000629 381f .dw XT_EXIT
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-00062a ff06 .dw $ff06
-00062b 7464
-00062c 6e3a
-00062d 6d75 .db "dt:num"
-00062e 0610 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-00062f 3851 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-000630 017b .dw XT_NOOP ; interpret
-000631 0764 .dw XT_LITERAL ; compile
-000632 0764 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-000633 ff07 .dw $ff07
-000634 7464
-000635 643a
-000636 756e
-000637 006d .db "dt:dnum",0
-000638 062a .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000639 3851 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-00063a 017b .dw XT_NOOP ; interpret
-00063b 3fd6 .dw XT_2LITERAL ; compile
-00063c 3fd6 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-00063d ff07 .dw $ff07
-00063e 6572
-00063f 3a63
-000640 756e
-000641 006d .db "rec:num",0
-000642 0633 .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-000643 3800 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-000644 04e2 .dw XT_NUMBER
-000645 3835 .dw XT_DOCONDBRANCH
-000646 064f DEST(PFA_REC_NONUMBER)
-000647 3fe5 .dw XT_ONE
-000648 3fde .dw XT_EQUAL
-000649 3835 .dw XT_DOCONDBRANCH
-00064a 064d DEST(PFA_REC_INTNUM2)
-00064b 062f .dw XT_DT_NUM
-00064c 381f .dw XT_EXIT
- PFA_REC_INTNUM2:
-00064d 0639 .dw XT_DT_DNUM
-00064e 381f .dw XT_EXIT
- PFA_REC_NONUMBER:
-00064f 067d .dw XT_DT_NULL
-000650 381f .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-000651 ff08 .dw $ff08
-000652 6572
-000653 3a63
-000654 6966
-000655 646e .db "rec:find"
-000656 063d .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000657 3800 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000658 06f2 .DW XT_FINDXT
-000659 38b0 .dw XT_DUP
-00065a 3919 .dw XT_ZEROEQUAL
-00065b 3835 .dw XT_DOCONDBRANCH
-00065c 0660 DEST(PFA_REC_WORD_FOUND)
-00065d 38d8 .dw XT_DROP
-00065e 067d .dw XT_DT_NULL
-00065f 381f .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-000660 0667 .dw XT_DT_XT
-
-000661 381f .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-000662 ff05 .dw $ff05
-000663 7464
-000664 783a
-000665 0074 .db "dt:xt",0
-000666 0651 .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000667 3851 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000668 066b .dw XT_R_WORD_INTERPRET
-000669 066f .dw XT_R_WORD_COMPILE
-00066a 3fd6 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-00066b 3800 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-00066c 38d8 .dw XT_DROP ; the flags are in the way
-00066d 3829 .dw XT_EXECUTE
-00066e 381f .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-00066f 3800 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-000670 3920 .dw XT_ZEROLESS
-000671 3835 .dw XT_DOCONDBRANCH
-000672 0675 DEST(PFA_R_WORD_COMPILE1)
-000673 074e .dw XT_COMMA
-000674 381f .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-000675 3829 .dw XT_EXECUTE
-000676 381f .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000677 ff07 .dw $ff07
-000678 7464
-000679 6e3a
-00067a 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-00067b 006c .db "dt:null"
-00067c 0662 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-00067d 3851 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-00067e 0681 .dw XT_FAIL ; interpret
-00067f 0681 .dw XT_FAIL ; compile
-000680 0681 .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-000681 3800 .dw DO_COLON
- PFA_FAIL:
- .endif
-000682 383c .dw XT_DOLITERAL
-000683 fff3 .dw -13
-000684 3d85 .dw XT_THROW
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-000685 ff0f .dw $ff0f
-000686 6573
-000687 7261
-000688 6863
-000689 772d
-00068a 726f
-00068b 6c64
-00068c 7369
-00068d 0074 .db "search-wordlist",0
-00068e 0677 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00068f 3800 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-000690 38fe .dw XT_TO_R
-000691 3953 .dw XT_ZERO
-000692 383c .dw XT_DOLITERAL
-000693 06a4 .dw XT_ISWORD
-000694 38f5 .dw XT_R_FROM
-000695 06c1 .dw XT_TRAVERSEWORDLIST
-000696 38b0 .dw XT_DUP
-000697 3919 .dw XT_ZEROEQUAL
-000698 3835 .dw XT_DOCONDBRANCH
-000699 069e DEST(PFA_SEARCH_WORDLIST1)
-00069a 3ed1 .dw XT_2DROP
-00069b 38d8 .dw XT_DROP
-00069c 3953 .dw XT_ZERO
-00069d 381f .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-00069e 38b0 .dw XT_DUP
-00069f 06e8 .dw XT_NFA2CFA
- ; .. and get the header flag
-0006a0 38c3 .dw XT_SWAP
-0006a1 0156 .dw XT_NAME2FLAGS
-0006a2 0144 .dw XT_IMMEDIATEQ
-0006a3 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-0006a4 3800 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-0006a5 38fe .dw XT_TO_R
-0006a6 38d8 .dw XT_DROP
-0006a7 3ec8 .dw XT_2DUP
-0006a8 3907 .dw XT_R_FETCH ; -- addr len addr len nt
-0006a9 06dc .dw XT_NAME2STRING
-0006aa 01b0 .dw XT_ICOMPARE ; (-- addr len f )
-0006ab 3835 .dw XT_DOCONDBRANCH
-0006ac 06b2 DEST(PFA_ISWORD3)
- ; not now
-0006ad 38f5 .dw XT_R_FROM
-0006ae 38d8 .dw XT_DROP
-0006af 3953 .dw XT_ZERO
-0006b0 394a .dw XT_TRUE ; maybe next word
-0006b1 381f .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-0006b2 3ed1 .dw XT_2DROP
-0006b3 38f5 .dw XT_R_FROM
-0006b4 3953 .dw XT_ZERO ; finish traverse-wordlist
-0006b5 381f .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-0006b6 ff11 .dw $ff11
-0006b7 7274
-0006b8 7661
-0006b9 7265
-0006ba 6573
-0006bb 772d
-0006bc 726f
-0006bd 6c64
-0006be 7369
-0006bf 0074 .db "traverse-wordlist",0
-0006c0 0685 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-0006c1 3800 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-0006c2 3b5e .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-0006c3 38b0 .dw XT_DUP ; ( -- xt nt nt )
-0006c4 3835 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-0006c5 06d2 DEST(PFA_TRAVERSEWORDLIST2)
-0006c6 3ec8 .dw XT_2DUP
-0006c7 3b1d .dw XT_2TO_R
-0006c8 38c3 .dw XT_SWAP
-0006c9 3829 .dw XT_EXECUTE
-0006ca 3b2c .dw XT_2R_FROM
-0006cb 38e0 .dw XT_ROT
-0006cc 3835 .dw XT_DOCONDBRANCH
-0006cd 06d2 DEST(PFA_TRAVERSEWORDLIST2)
-0006ce 09fd .dw XT_NFA2LFA
-0006cf 3bca .dw XT_FETCHI
-0006d0 382e .dw XT_DOBRANCH ; ( -- addr )
-0006d1 06c3 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-0006d2 3ed1 .dw XT_2DROP
-0006d3 381f .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-0006d4 ff0b .dw $ff0b
-0006d5 616e
-0006d6 656d
-0006d7 733e
-0006d8 7274
-0006d9 6e69
-0006da 0067 .db "name>string",0
-0006db 06b6 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-0006dc 3800 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-0006dd 0416 .dw XT_ICOUNT ; ( -- addr n )
-0006de 383c .dw XT_DOLITERAL
-0006df 00ff .dw 255
-0006e0 3a12 .dw XT_AND ; mask immediate bit
-0006e1 381f .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-0006e2 ff07 .dw $ff07
-0006e3 666e
-0006e4 3e61
-0006e5 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-0006e6 0061 .db "nfa>cfa"
-0006e7 06d4 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-0006e8 3800 .dw DO_COLON
- PFA_NFA2CFA:
-0006e9 09fd .dw XT_NFA2LFA ; skip to link field
-0006ea 3a2e .dw XT_1PLUS ; next is the execution token
-0006eb 381f .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-0006ec ff07 .dw $ff07
-0006ed 6966
-0006ee 646e
-0006ef 782d
-0006f0 0074 .db "find-xt",0
-0006f1 06e2 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-0006f2 3800 .dw DO_COLON
- PFA_FINDXT:
- .endif
-0006f3 383c .dw XT_DOLITERAL
-0006f4 06fe .dw XT_FINDXTA
-0006f5 383c .dw XT_DOLITERAL
-0006f6 006c .dw CFG_ORDERLISTLEN
-0006f7 098e .dw XT_MAPSTACK
-0006f8 3919 .dw XT_ZEROEQUAL
-0006f9 3835 .dw XT_DOCONDBRANCH
-0006fa 06fd DEST(PFA_FINDXT1)
-0006fb 3ed1 .dw XT_2DROP
-0006fc 3953 .dw XT_ZERO
- PFA_FINDXT1:
-0006fd 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-0006fe 3800 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-0006ff 38fe .dw XT_TO_R
-000700 3ec8 .dw XT_2DUP
-000701 38f5 .dw XT_R_FROM
-000702 068f .dw XT_SEARCH_WORDLIST
-000703 38b0 .dw XT_DUP
-000704 3835 .dw XT_DOCONDBRANCH
-000705 070b DEST(PFA_FINDXTA1)
-000706 38fe .dw XT_TO_R
-000707 38ef .dw XT_NIP
-000708 38ef .dw XT_NIP
-000709 38f5 .dw XT_R_FROM
-00070a 394a .dw XT_TRUE
- PFA_FINDXTA1:
-00070b 381f .dw XT_EXIT
-
- .include "dict/compiler1.inc"
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-00070c ff06 .dw $ff06
-00070d 656e
-00070e 6577
-00070f 7473 .db "newest"
-000710 06ec .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-000711 3847 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-000712 019b .dw ram_newest
-
- .dseg
-00019b ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-000713 ff06 .dw $ff06
-000714 616c
-000715 6574
-000716 7473 .db "latest"
-000717 070c .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000718 3847 .dw PFA_DOVARIABLE
- PFA_LATEST:
-000719 019f .dw ram_latest
-
- .dseg
-00019f ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-00071a ff08 .dw $ff08
-00071b 6328
-00071c 6572
-00071d 7461
-00071e 2965 .db "(create)"
-00071f 0713 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-000720 3800 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-000721 05a2
-000722 0877 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-000723 38b0
-000724 0711
-000725 3c8f
-000726 3880 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000727 085c
-000728 0711
-000729 3880 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-00072a 381f .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-00072b 0001 .dw $0001
-00072c 005c .db $5c,0
-00072d 071a .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-00072e 3800 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-00072f 0589 .dw XT_SOURCE
-000730 38ef .dw XT_NIP
-000731 3ee1 .dw XT_TO_IN
-000732 3880 .dw XT_STORE
-000733 381f .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-000734 0001 .dw $0001
-000735 0028 .db "(" ,0
-000736 072b .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000737 3800 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000738 383c .dw XT_DOLITERAL
-000739 0029 .dw ')'
-00073a 0575 .dw XT_PARSE
-00073b 3ed1 .dw XT_2DROP
-00073c 381f .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-00073d ff07 .dw $ff07
-00073e 6f63
-00073f 706d
-000740 6c69
-000741 0065 .db "compile",0
-000742 0734 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-000743 3800 .dw DO_COLON
- PFA_COMPILE:
- .endif
-000744 38f5 .dw XT_R_FROM
-000745 38b0 .dw XT_DUP
-000746 01a7 .dw XT_ICELLPLUS
-000747 38fe .dw XT_TO_R
-000748 3bca .dw XT_FETCHI
-000749 074e .dw XT_COMMA
-00074a 381f .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-00074b ff01 .dw $ff01
-00074c 002c .db ',',0 ; ,
-00074d 073d .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-00074e 3800 .dw DO_COLON
- PFA_COMMA:
-00074f 3f11 .dw XT_DP
-000750 3b72 .dw XT_STOREI
-000751 3f11 .dw XT_DP
-000752 3a2e .dw XT_1PLUS
-000753 0195 .dw XT_DOTO
-000754 3f12 .dw PFA_DP
-000755 381f .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-000756 0003 .dw $0003
-000757 275b
-000758 005d .db "[']",0
-000759 074b .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-00075a 3800 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-00075b 042f .dw XT_TICK
-00075c 0764 .dw XT_LITERAL
-00075d 381f .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-00075e 0007 .dw $0007
-00075f 696c
-000760 6574
-000761 6172
-000762 006c .db "literal",0
-000763 0756 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-000764 3800 .dw DO_COLON
- PFA_LITERAL:
- .endif
-000765 0743 .DW XT_COMPILE
-000766 383c .DW XT_DOLITERAL
-000767 074e .DW XT_COMMA
-000768 381f .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-000769 0008 .dw $0008
-00076a 6c73
-00076b 7469
-00076c 7265
-00076d 6c61 .db "sliteral"
-00076e 075e .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-00076f 3800 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-000770 0743 .dw XT_COMPILE
-000771 03b7 .dw XT_DOSLITERAL ; ( -- addr n)
-000772 03c5 .dw XT_SCOMMA
-000773 381f .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-000774 3800 .dw DO_COLON
- PFA_GMARK:
-000775 3f11 .dw XT_DP
-000776 0743 .dw XT_COMPILE
-000777 ffff .dw -1 ; ffff does not erase flash
-000778 381f .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000779 3800 .dw DO_COLON
- PFA_GRESOLVE:
-00077a 3f8a .dw XT_QSTACK
-00077b 3f11 .dw XT_DP
-00077c 38c3 .dw XT_SWAP
-00077d 3b72 .dw XT_STOREI
-00077e 381f .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-00077f 3800 .dw DO_COLON
- PFA_LMARK:
-000780 3f11 .dw XT_DP
-000781 381f .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-000782 3800 .dw DO_COLON
- PFA_LRESOLVE:
-000783 3f8a .dw XT_QSTACK
-000784 074e .dw XT_COMMA
-000785 381f .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-000786 0005 .dw $0005
-000787 6861
-000788 6165
-000789 0064 .db "ahead",0
-00078a 0769 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-00078b 3800 .dw DO_COLON
- PFA_AHEAD:
- .endif
-00078c 0743 .dw XT_COMPILE
-00078d 382e .dw XT_DOBRANCH
-00078e 0774 .dw XT_GMARK
-00078f 381f .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-000790 0002 .dw $0002
-000791 6669 .db "if"
-000792 0786 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-000793 3800 .dw DO_COLON
- PFA_IF:
- .endif
-000794 0743 .dw XT_COMPILE
-000795 3835 .dw XT_DOCONDBRANCH
-000796 0774 .dw XT_GMARK
-000797 381f .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-000798 0004 .dw $0004
-000799 6c65
-00079a 6573 .db "else"
-00079b 0790 .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-00079c 3800 .dw DO_COLON
- PFA_ELSE:
- .endif
-00079d 0743 .dw XT_COMPILE
-00079e 382e .dw XT_DOBRANCH
-00079f 0774 .dw XT_GMARK
-0007a0 38c3 .dw XT_SWAP
-0007a1 0779 .dw XT_GRESOLVE
-0007a2 381f .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-0007a3 0004 .dw $0004
-0007a4 6874
-0007a5 6e65 .db "then"
-0007a6 0798 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-0007a7 3800 .dw DO_COLON
- PFA_THEN:
- .endif
-0007a8 0779 .dw XT_GRESOLVE
-0007a9 381f .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-0007aa 0005 .dw $0005
-0007ab 6562
-0007ac 6967
-0007ad 006e .db "begin",0
-0007ae 07a3 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-0007af 3800 .dw DO_COLON
- PFA_BEGIN:
- .endif
-0007b0 077f .dw XT_LMARK
-0007b1 381f .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-0007b2 0005 .dw $0005
-0007b3 6877
-0007b4 6c69
-0007b5 0065 .db "while",0
-0007b6 07aa .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-0007b7 3800 .dw DO_COLON
- PFA_WHILE:
- .endif
-0007b8 0793 .dw XT_IF
-0007b9 38c3 .dw XT_SWAP
-0007ba 381f .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-0007bb 0006 .dw $0006
-0007bc 6572
-0007bd 6570
-0007be 7461 .db "repeat"
-0007bf 07b2 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-0007c0 3800 .dw DO_COLON
- PFA_REPEAT:
- .endif
-0007c1 07d4 .dw XT_AGAIN
-0007c2 07a7 .dw XT_THEN
-0007c3 381f .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-0007c4 0005 .dw $0005
-0007c5 6e75
-0007c6 6974
-0007c7 006c .db "until",0
-0007c8 07bb .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-0007c9 3800 .dw DO_COLON
- PFA_UNTIL:
- .endif
-0007ca 383c .dw XT_DOLITERAL
-0007cb 3835 .dw XT_DOCONDBRANCH
-0007cc 074e .dw XT_COMMA
-
-0007cd 0782 .dw XT_LRESOLVE
-0007ce 381f .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-0007cf 0005 .dw $0005
-0007d0 6761
-0007d1 6961
-0007d2 006e .db "again",0
-0007d3 07c4 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-0007d4 3800 .dw DO_COLON
- PFA_AGAIN:
- .endif
-0007d5 0743 .dw XT_COMPILE
-0007d6 382e .dw XT_DOBRANCH
-0007d7 0782 .dw XT_LRESOLVE
-0007d8 381f .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-0007d9 0002 .dw $0002
-0007da 6f64 .db "do"
-0007db 07cf .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-0007dc 3800 .dw DO_COLON
- PFA_DO:
-
- .endif
-0007dd 0743 .dw XT_COMPILE
-0007de 3a9a .dw XT_DODO
-0007df 077f .dw XT_LMARK
-0007e0 3953 .dw XT_ZERO
-0007e1 0837 .dw XT_TO_L
-0007e2 381f .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-0007e3 0004 .dw $0004
-0007e4 6f6c
-0007e5 706f .db "loop"
-0007e6 07d9 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-0007e7 3800 .dw DO_COLON
- PFA_LOOP:
- .endif
-0007e8 0743 .dw XT_COMPILE
-0007e9 3ac8 .dw XT_DOLOOP
-0007ea 081e .dw XT_ENDLOOP
-0007eb 381f .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-0007ec 0005 .dw $0005
-0007ed 6c2b
-0007ee 6f6f
-0007ef 0070 .db "+loop",0
-0007f0 07e3 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-0007f1 3800 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-0007f2 0743 .dw XT_COMPILE
-0007f3 3ab9 .dw XT_DOPLUSLOOP
-0007f4 081e .dw XT_ENDLOOP
-0007f5 381f .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-0007f6 0005 .dw $0005
-0007f7 656c
-0007f8 7661
-0007f9 0065 .db "leave",0
-0007fa 07ec .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-0007fb 3800 .dw DO_COLON
- PFA_LEAVE:
- .endif
-0007fc 0743
-0007fd 3ad3 .DW XT_COMPILE,XT_UNLOOP
-0007fe 078b
-0007ff 0837
-000800 381f .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-000801 0003 .dw $0003
-000802 643f
-000803 006f .db "?do",0
-000804 07f6 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000805 3800 .dw DO_COLON
- PFA_QDO:
- .endif
-000806 0743 .dw XT_COMPILE
-000807 080d .dw XT_QDOCHECK
-000808 0793 .dw XT_IF
-000809 07dc .dw XT_DO
-00080a 38c3 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-00080b 0837 .dw XT_TO_L ; then follows at the end.
-00080c 381f .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00080d 3800 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00080e 3ec8 .dw XT_2DUP
-00080f 3fde .dw XT_EQUAL
-000810 38b0 .dw XT_DUP
-000811 38fe .dw XT_TO_R
-000812 3835 .dw XT_DOCONDBRANCH
-000813 0815 DEST(PFA_QDOCHECK1)
-000814 3ed1 .dw XT_2DROP
- PFA_QDOCHECK1:
-000815 38f5 .dw XT_R_FROM
-000816 39fc .dw XT_INVERT
-000817 381f .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000818 ff07 .dw $ff07
-000819 6e65
-00081a 6c64
-00081b 6f6f
-00081c 0070 .db "endloop",0
-00081d 0801 .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-00081e 3800 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-00081f 0782 .DW XT_LRESOLVE
-000820 082b
-000821 38b8
-000822 3835 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-000823 0827 DEST(LOOP2)
-000824 07a7 .DW XT_THEN
-000825 382e .dw XT_DOBRANCH
-000826 0820 DEST(LOOP1)
-000827 381f LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000828 ff02 .dw $ff02
-000829 3e6c .db "l>"
-00082a 0818 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-00082b 3800 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-00082c 084a .dw XT_LP
-00082d 3878 .dw XT_FETCH
-00082e 3878 .dw XT_FETCH
-00082f 383c .dw XT_DOLITERAL
-000830 fffe .dw -2
-000831 084a .dw XT_LP
-000832 3a64 .dw XT_PLUSSTORE
-000833 381f .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-000834 ff02 .dw $ff02
-000835 6c3e .db ">l"
-000836 0828 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000837 3800 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000838 3fea .dw XT_TWO
-000839 084a .dw XT_LP
-00083a 3a64 .dw XT_PLUSSTORE
-00083b 084a .dw XT_LP
-00083c 3878 .dw XT_FETCH
-00083d 3880 .dw XT_STORE
-00083e 381f .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-00083f ff03 .dw $ff03
-000840 706c
-000841 0030 .db "lp0",0
-000842 0834 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-000843 386e .dw PFA_DOVALUE1
- PFA_LP0:
-000844 0062 .dw CFG_LP0
-000845 3d9f .dw XT_EDEFERFETCH
-000846 3da9 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-000847 ff02 .dw $ff02
-000848 706c .db "lp"
-000849 083f .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-00084a 3847 .dw PFA_DOVARIABLE
- PFA_LP:
-00084b 01a1 .dw ram_lp
-
- .dseg
-0001a1 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-00084c ff06 .dw $ff06
-00084d 7263
-00084e 6165
-00084f 6574 .db "create"
-000850 0847 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-000851 3800 .dw DO_COLON
- PFA_CREATE:
- .endif
-000852 0720 .dw XT_DOCREATE
-000853 0880 .dw XT_REVEAL
-000854 0743 .dw XT_COMPILE
-000855 3851 .dw PFA_DOCONSTANT
-000856 381f .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-000857 ff06 .dw $ff06
-000858 6568
-000859 6461
-00085a 7265 .db "header"
-00085b 084c .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-00085c 3800 .dw DO_COLON
- PFA_HEADER:
-00085d 3f11 .dw XT_DP ; the new Name Field
-00085e 38fe .dw XT_TO_R
-00085f 38fe .dw XT_TO_R ; ( R: NFA WID )
-000860 38b0 .dw XT_DUP
-000861 3927 .dw XT_GREATERZERO
-000862 3835 .dw XT_DOCONDBRANCH
-000863 086e .dw PFA_HEADER1
-000864 38b0 .dw XT_DUP
-000865 383c .dw XT_DOLITERAL
-000866 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-000867 3a1b .dw XT_OR
-000868 03c9 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-000869 38f5 .dw XT_R_FROM
-00086a 3b5e .dw XT_FETCHE
-00086b 074e .dw XT_COMMA
-00086c 38f5 .dw XT_R_FROM
-00086d 381f .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-00086e 383c .dw XT_DOLITERAL
-00086f fff0 .dw -16
-000870 3d85 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-000871 ff07 .dw $ff07
-000872 6c77
-000873 6373
-000874 706f
-000875 0065 .db "wlscope",0
-000876 0857 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000877 3dfe .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000878 005e .dw CFG_WLSCOPE
-000879 3d9f .dw XT_EDEFERFETCH
-00087a 3da9 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-00087b ff06 .dw $ff06
-00087c 6572
-00087d 6576
-00087e 6c61 .db "reveal"
-00087f 0871 .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-000880 3800 .dw DO_COLON
- PFA_REVEAL:
- .endif
-000881 0711
-000882 3c8f
-000883 3878 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-000884 38b8
-000885 3835 .DW XT_QDUP,XT_DOCONDBRANCH
-000886 088b DEST(REVEAL1)
-000887 0711
-000888 3878
-000889 38c3
-00088a 3b3a .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-00088b 381f .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-00088c 0005 .dw $0005
-00088d 6f64
-00088e 7365
-00088f 003e .db "does>",0
-000890 087b .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-000891 3800 .dw DO_COLON
- PFA_DOES:
-000892 0743 .dw XT_COMPILE
-000893 08a4 .dw XT_DODOES
-000894 0743 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-000895 940e .dw $940e ; the address of this compiled
-000896 0743 .dw XT_COMPILE ; code will replace the XT of the
-000897 0899 .dw DO_DODOES ; word that CREATE created
-000898 381f .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-000899 939a
-00089a 938a savetos
-00089b 01cb movw tosl, wl
-00089c 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-00089d 917f pop wh
-00089e 916f pop wl
-
-00089f 93bf push XH
-0008a0 93af push XL
-0008a1 01db movw XL, wl
-0008a2 940c 3804 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-0008a4 3800 .dw DO_COLON
- PFA_DODOES:
-0008a5 38f5 .dw XT_R_FROM
-0008a6 0711 .dw XT_NEWEST
-0008a7 3c8f .dw XT_CELLPLUS
-0008a8 3878 .dw XT_FETCH
-0008a9 3b5e .dw XT_FETCHE
-0008aa 06e8 .dw XT_NFA2CFA
-0008ab 3b72 .dw XT_STOREI
-0008ac 381f .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-0008ad ff01 .dw $ff01
-0008ae 003a .db ":",0
-0008af 088c .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-0008b0 3800 .dw DO_COLON
- PFA_COLON:
- .endif
-0008b1 0720 .dw XT_DOCREATE
-0008b2 08bb .dw XT_COLONNONAME
-0008b3 38d8 .dw XT_DROP
-0008b4 381f .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-0008b5 ff07 .dw $ff07
-0008b6 6e3a
-0008b7 6e6f
-0008b8 6d61
-0008b9 0065 .db ":noname",0
-0008ba 08ad .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-0008bb 3800 .dw DO_COLON
- PFA_COLONNONAME:
-0008bc 3f11 .dw XT_DP
-0008bd 38b0 .dw XT_DUP
-0008be 0718 .dw XT_LATEST
-0008bf 3880 .dw XT_STORE
-
-0008c0 0743 .dw XT_COMPILE
-0008c1 3800 .dw DO_COLON
-
-0008c2 08d0 .dw XT_RBRACKET
-0008c3 381f .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-0008c4 0001 .dw $0001
-0008c5 003b .db $3b,0
-0008c6 08b5 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-0008c7 3800 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-0008c8 0743 .dw XT_COMPILE
-0008c9 381f .dw XT_EXIT
-0008ca 08d8 .dw XT_LBRACKET
-0008cb 0880 .dw XT_REVEAL
-0008cc 381f .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-0008cd ff01 .dw $ff01
-0008ce 005d .db "]",0
-0008cf 08c4 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-0008d0 3800 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-0008d1 3fe5 .dw XT_ONE
-0008d2 3eb6 .dw XT_STATE
-0008d3 3880 .dw XT_STORE
-0008d4 381f .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-0008d5 0001 .dw $0001
-0008d6 005b .db "[",0
-0008d7 08cd .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-0008d8 3800 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-0008d9 3953 .dw XT_ZERO
-0008da 3eb6 .dw XT_STATE
-0008db 3880 .dw XT_STORE
-0008dc 381f .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-0008dd ff08 .dw $ff08
-0008de 6176
-0008df 6972
-0008e0 6261
-0008e1 656c .db "variable"
-0008e2 08d5 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-0008e3 3800 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-0008e4 3f22 .dw XT_HERE
-0008e5 08ef .dw XT_CONSTANT
-0008e6 3fea .dw XT_TWO
-0008e7 3f2b .dw XT_ALLOT
-0008e8 381f .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-0008e9 ff08 .dw $ff08
-0008ea 6f63
-0008eb 736e
-0008ec 6174
-0008ed 746e .db "constant"
-0008ee 08dd .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-0008ef 3800 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-0008f0 0720 .dw XT_DOCREATE
-0008f1 0880 .dw XT_REVEAL
-0008f2 0743 .dw XT_COMPILE
-0008f3 3847 .dw PFA_DOVARIABLE
-0008f4 074e .dw XT_COMMA
-0008f5 381f .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-0008f6 ff04 .dw $ff04
-0008f7 7375
-0008f8 7265 .db "user"
-0008f9 08e9 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-0008fa 3800 .dw DO_COLON
- PFA_USER:
-0008fb 0720 .dw XT_DOCREATE
-0008fc 0880 .dw XT_REVEAL
-
-0008fd 0743 .dw XT_COMPILE
-0008fe 3857 .dw PFA_DOUSER
-0008ff 074e .dw XT_COMMA
-000900 381f .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-000901 0007 .dw $0007
-000902 6572
-000903 7563
-000904 7372
-000905 0065 .db "recurse",0
-000906 08f6 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000907 3800 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000908 0718 .dw XT_LATEST
-000909 3878 .dw XT_FETCH
-00090a 074e .dw XT_COMMA
-00090b 381f .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-00090c ff09 .dw $ff09
-00090d 6d69
-00090e 656d
-00090f 6964
-000910 7461
-000911 0065 .db "immediate",0
-000912 0901 .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-000913 3800 .dw DO_COLON
- PFA_IMMEDIATE:
-000914 09b5 .dw XT_GET_CURRENT
-000915 3b5e .dw XT_FETCHE
-000916 38b0 .dw XT_DUP
-000917 3bca .dw XT_FETCHI
-000918 383c .dw XT_DOLITERAL
-000919 7fff .dw $7fff
-00091a 3a12 .dw XT_AND
-00091b 38c3 .dw XT_SWAP
-00091c 3b72 .dw XT_STOREI
-00091d 381f .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-00091e 0006 .dw $0006
-00091f 635b
-000920 6168
-000921 5d72 .db "[char]"
-000922 090c .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-000923 3800 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-000924 0743 .dw XT_COMPILE
-000925 383c .dw XT_DOLITERAL
-000926 04d8 .dw XT_CHAR
-000927 074e .dw XT_COMMA
-000928 381f .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-000929 0006 .dw $0006
-00092a 6261
-00092b 726f
-00092c 2274 .db "abort",'"'
-00092d 091e .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-00092e 3800 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-00092f 3e89 .dw XT_SQUOTE
-000930 0743 .dw XT_COMPILE
-000931 0940 .dw XT_QABORT
-000932 381f .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-000933 ff05 .dw $ff05
-000934 6261
-000935 726f
-000936 0074 .db "abort",0
-000937 0929 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000938 3800 .dw DO_COLON
- PFA_ABORT:
- .endif
-000939 394a .dw XT_TRUE
-00093a 3d85 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-00093b ff06 .dw $ff06
-00093c 613f
-00093d 6f62
-00093e 7472 .db "?abort"
-00093f 0933 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-000940 3800 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-000941 38e0
-000942 3835 .DW XT_ROT,XT_DOCONDBRANCH
-000943 0946 DEST(QABO1)
-000944 03ea
-000945 0938 .DW XT_ITYPE,XT_ABORT
-000946 3ed1
-000947 381f QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000948 ff09 .dw $ff09
-000949 6567
-00094a 2d74
-00094b 7473
-00094c 6361
-00094d 006b .db "get-stack",0
-00094e 093b .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-00094f 3800 .dw DO_COLON
- .endif
-000950 38b0 .dw XT_DUP
-000951 3c8f .dw XT_CELLPLUS
-000952 38c3 .dw XT_SWAP
-000953 3b5e .dw XT_FETCHE
-000954 38b0 .dw XT_DUP
-000955 38fe .dw XT_TO_R
-000956 3953 .dw XT_ZERO
-000957 38c3 .dw XT_SWAP ; go from bigger to smaller addresses
-000958 080d .dw XT_QDOCHECK
-000959 3835 .dw XT_DOCONDBRANCH
-00095a 0966 DEST(PFA_N_FETCH_E2)
-00095b 3a9a .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-00095c 3aab .dw XT_I
-00095d 3a34 .dw XT_1MINUS
-00095e 3ec3 .dw XT_CELLS ; ( -- ee-addr i*2 )
-00095f 38ce .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-000960 399c .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-000961 3b5e .dw XT_FETCHE ;( -- ee-addr item_i )
-000962 38c3 .dw XT_SWAP ;( -- item_i ee-addr )
-000963 394a .dw XT_TRUE ; shortcut for -1
-000964 3ab9 .dw XT_DOPLUSLOOP
-000965 095c DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-000966 3ed1 .dw XT_2DROP
-000967 38f5 .dw XT_R_FROM
-000968 381f .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-000969 ff09 .dw $ff09
-00096a 6573
-00096b 2d74
-00096c 7473
-00096d 6361
-00096e 006b .db "set-stack",0
-00096f 0948 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-000970 3800 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-000971 38ce .dw XT_OVER
-000972 3920 .dw XT_ZEROLESS
-000973 3835 .dw XT_DOCONDBRANCH
-000974 0978 DEST(PFA_SET_STACK0)
-000975 383c .dw XT_DOLITERAL
-000976 fffc .dw -4
-000977 3d85 .dw XT_THROW
- PFA_SET_STACK0:
-000978 3ec8 .dw XT_2DUP
-000979 3b3a .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-00097a 38c3 .dw XT_SWAP
-00097b 3953 .dw XT_ZERO
-00097c 080d .dw XT_QDOCHECK
-00097d 3835 .dw XT_DOCONDBRANCH
-00097e 0985 DEST(PFA_SET_STACK2)
-00097f 3a9a .dw XT_DODO
- PFA_SET_STACK1:
-000980 3c8f .dw XT_CELLPLUS ; ( -- i_x e-addr )
-000981 3ed9 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-000982 3b3a .dw XT_STOREE
-000983 3ac8 .dw XT_DOLOOP
-000984 0980 DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-000985 38d8 .dw XT_DROP
-000986 381f .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-000987 ff09 .dw $ff09
-000988 616d
-000989 2d70
-00098a 7473
-00098b 6361
-00098c 006b .db "map-stack",0
-00098d 0969 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-00098e 3800 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-00098f 38b0 .dw XT_DUP
-000990 3c8f .dw XT_CELLPLUS
-000991 38c3 .dw XT_SWAP
-000992 3b5e .dw XT_FETCHE
-000993 3ec3 .dw XT_CELLS
-000994 3f98 .dw XT_BOUNDS
-000995 080d .dw XT_QDOCHECK
-000996 3835 .dw XT_DOCONDBRANCH
-000997 09aa DEST(PFA_MAPSTACK3)
-000998 3a9a .dw XT_DODO
- PFA_MAPSTACK1:
-000999 3aab .dw XT_I
-00099a 3b5e .dw XT_FETCHE ; -- i*x XT id
-00099b 38c3 .dw XT_SWAP
-00099c 38fe .dw XT_TO_R
-00099d 3907 .dw XT_R_FETCH
-00099e 3829 .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-00099f 38b8 .dw XT_QDUP
-0009a0 3835 .dw XT_DOCONDBRANCH
-0009a1 09a6 DEST(PFA_MAPSTACK2)
-0009a2 38f5 .dw XT_R_FROM
-0009a3 38d8 .dw XT_DROP
-0009a4 3ad3 .dw XT_UNLOOP
-0009a5 381f .dw XT_EXIT
- PFA_MAPSTACK2:
-0009a6 38f5 .dw XT_R_FROM
-0009a7 3fea .dw XT_TWO
-0009a8 3ab9 .dw XT_DOPLUSLOOP
-0009a9 0999 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-0009aa 38d8 .dw XT_DROP
-0009ab 3953 .dw XT_ZERO
-0009ac 381f .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-0009ad ff0b .dw $ff0b
-0009ae 6567
-0009af 2d74
-0009b0 7563
-0009b1 7272
-0009b2 6e65
-0009b3 0074 .db "get-current",0
-0009b4 0987 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-0009b5 3800 .dw DO_COLON
- PFA_GET_CURRENT:
-0009b6 383c .dw XT_DOLITERAL
-0009b7 0068 .dw CFG_CURRENT
-0009b8 3b5e .dw XT_FETCHE
-0009b9 381f .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-0009ba ff09 .dw $ff09
-0009bb 6567
-0009bc 2d74
-0009bd 726f
-0009be 6564
-0009bf 0072 .db "get-order",0
-0009c0 09ad .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-0009c1 3800 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-0009c2 383c .dw XT_DOLITERAL
-0009c3 006c .dw CFG_ORDERLISTLEN
-0009c4 094f .dw XT_GET_STACK
-0009c5 381f .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-0009c6 ff09 .dw $ff09
-0009c7 6663
-0009c8 2d67
-0009c9 726f
-0009ca 6564
-0009cb 0072 .db "cfg-order",0
-0009cc 09ba .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-0009cd 3847 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-0009ce 006c .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-0009cf ff07 .dw $ff07
-0009d0 6f63
-0009d1 706d
-0009d2 7261
-0009d3 0065 .db "compare",0
-0009d4 09c6 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-0009d5 09d6 .dw PFA_COMPARE
- PFA_COMPARE:
-0009d6 93bf push xh
-0009d7 93af push xl
-0009d8 018c movw temp0, tosl
-0009d9 9189
-0009da 9199 loadtos
-0009db 01dc movw xl, tosl
-0009dc 9189
-0009dd 9199 loadtos
-0009de 019c movw temp2, tosl
-0009df 9189
-0009e0 9199 loadtos
-0009e1 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-0009e2 90ed ld temp4, X+
-0009e3 90f1 ld temp5, Z+
-0009e4 14ef cp temp4, temp5
-0009e5 f451 brne PFA_COMPARE_NOTEQUAL
-0009e6 950a dec temp0
-0009e7 f019 breq PFA_COMPARE_ENDREACHED2
-0009e8 952a dec temp2
-0009e9 f7c1 brne PFA_COMPARE_LOOP
-0009ea c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-0009eb 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-0009ec 2b02 or temp0, temp2
-0009ed f411 brne PFA_COMPARE_CHECKLASTCHAR
-0009ee 2788 clr tosl
-0009ef c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-0009f0 ef8f ser tosl
-0009f1 c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-0009f2 2f98 mov tosh, tosl
-0009f3 91af pop xl
-0009f4 91bf pop xh
-0009f5 940c 3804 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-0009f7 ff07 .dw $ff07
-0009f8 666e
-0009f9 3e61
-0009fa 666c
-0009fb 0061 .db "nfa>lfa",0
-0009fc 09cf .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-0009fd 3800 .dw DO_COLON
- PFA_NFA2LFA:
-0009fe 06dc .dw XT_NAME2STRING
-0009ff 3a2e .dw XT_1PLUS
-000a00 3a03 .dw XT_2SLASH
-000a01 399c .dw XT_PLUS
-000a02 381f .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
-
- .include "dict/compiler2.inc" ; additional words for the compiler
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-000a03 ff0b .dw $ff0b
-000a04 6573
-000a05 2d74
-000a06 7563
-000a07 7272
-000a08 6e65
-000a09 0074 .db "set-current",0
-000a0a 09f7 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-000a0b 3800 .dw DO_COLON
- PFA_SET_CURRENT:
-000a0c 383c .dw XT_DOLITERAL
-000a0d 0068 .dw CFG_CURRENT
-000a0e 3b3a .dw XT_STOREE
-000a0f 381f .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-000a10 ff08 .dw $ff08
-000a11 6f77
-000a12 6472
-000a13 696c
-000a14 7473 .db "wordlist"
-000a15 0a03 .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000a16 3800 .dw DO_COLON
- PFA_WORDLIST:
-000a17 3f1a .dw XT_EHERE
-000a18 3953 .dw XT_ZERO
-000a19 38ce .dw XT_OVER
-000a1a 3b3a .dw XT_STOREE
-000a1b 38b0 .dw XT_DUP
-000a1c 3c8f .dw XT_CELLPLUS
-000a1d 0195 .dw XT_DOTO
-000a1e 3f1b .dw PFA_EHERE
-000a1f 381f .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-000a20 ff0e .dw $ff0e
-000a21 6f66
-000a22 7472
-000a23 2d68
-000a24 6f77
-000a25 6472
-000a26 696c
-000a27 7473 .db "forth-wordlist"
-000a28 0a10 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000a29 3847 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000a2a 006a .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000a2b ff09 .dw $ff09
-000a2c 6573
-000a2d 2d74
-000a2e 726f
-000a2f 6564
-000a30 0072 .db "set-order",0
-000a31 0a20 .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000a32 3800 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000a33 383c .dw XT_DOLITERAL
-000a34 006c .dw CFG_ORDERLISTLEN
-000a35 0970 .dw XT_SET_STACK
-000a36 381f .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000a37 ff0f .dw $ff0f
-000a38 6573
-000a39 2d74
-000a3a 6572
-000a3b 6f63
-000a3c 6e67
-000a3d 7a69
-000a3e 7265
-000a3f 0073 .db "set-recognizers",0
-000a40 0a2b .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000a41 3800 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000a42 383c .dw XT_DOLITERAL
-000a43 007e .dw CFG_RECOGNIZERLISTLEN
-000a44 0970 .dw XT_SET_STACK
-000a45 381f .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000a46 ff0f .dw $ff0f
-000a47 6567
-000a48 2d74
-000a49 6572
-000a4a 6f63
-000a4b 6e67
-000a4c 7a69
-000a4d 7265
-000a4e 0073 .db "get-recognizers",0
-000a4f 0a37 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000a50 3800 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000a51 383c .dw XT_DOLITERAL
-000a52 007e .dw CFG_RECOGNIZERLISTLEN
-000a53 094f .dw XT_GET_STACK
-000a54 381f .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000a55 ff04 .dw $ff04
-000a56 6f63
-000a57 6564 .db "code"
-000a58 0a46 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000a59 3800 .dw DO_COLON
- PFA_CODE:
-000a5a 0720 .dw XT_DOCREATE
-000a5b 0880 .dw XT_REVEAL
-000a5c 3f11 .dw XT_DP
-000a5d 01a7 .dw XT_ICELLPLUS
-000a5e 074e .dw XT_COMMA
-000a5f 381f .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000a60 ff08 .dw $ff08
-000a61 6e65
-000a62 2d64
-000a63 6f63
-000a64 6564 .db "end-code"
-000a65 0a55 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000a66 3800 .dw DO_COLON
- PFA_ENDCODE:
-000a67 0743 .dw XT_COMPILE
-000a68 940c .dw $940c
-000a69 0743 .dw XT_COMPILE
-000a6a 3804 .dw DO_NEXT
-000a6b 381f .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000a6c ff08 .dw $ff08
-000a6d 6d28
-000a6e 7261
-000a6f 656b
-000a70 2972 .db "(marker)"
-000a71 0a60 .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-000a72 386e .dw PFA_DOVALUE1
- PFA_MARKER:
-000a73 008a .dw EE_MARKER
-000a74 3d9f .dw XT_EDEFERFETCH
-000a75 3da9 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000a76 0008 .dw $0008
-000a77 6f70
-000a78 7473
-000a79 6f70
-000a7a 656e .db "postpone"
-000a7b 0a6c .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000a7c 3800 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000a7d 05a2 .dw XT_PARSENAME
-000a7e 05e5 .dw XT_FORTHRECOGNIZER
-000a7f 05f0 .dw XT_RECOGNIZE
-000a80 38b0 .dw XT_DUP
-000a81 38fe .dw XT_TO_R
-000a82 01a7 .dw XT_ICELLPLUS
-000a83 01a7 .dw XT_ICELLPLUS
-000a84 3bca .dw XT_FETCHI
-000a85 3829 .dw XT_EXECUTE
-000a86 38f5 .dw XT_R_FROM
-000a87 01a7 .dw XT_ICELLPLUS
-000a88 3bca .dw XT_FETCHI
-000a89 074e .dw XT_COMMA
-000a8a 381f .dw XT_EXIT
- .endif
-
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000a8b ff0b .dw $ff0b
-000a8c 7061
-000a8d 6c70
-000a8e 7574
-000a8f 6e72
-000a90 656b
-000a91 0079 .db "applturnkey",0
-000a92 0a76 .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000a93 3800 .dw DO_COLON
- PFA_APPLTURNKEY:
-000a94 00e9 .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-000a95 3c96 .dw XT_INTON
- .endif
-
-000a96 0160 .dw XT_DOT_VER
-000a97 3fad .dw XT_SPACE
-000a98 03b7 .dw XT_DOSLITERAL
-000a99 000a .dw 10
-000a9a 6f46
-000a9b 7472
-000a9c 6468
-000a9d 6975
-000a9e 6f6e .db "Forthduino"
-000a9f 03ea .dw XT_ITYPE
-
-000aa0 381f .dw XT_EXIT
-
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-003800 93bf push XH
-003801 93af push XL ; PUSH IP
-003802 01db movw XL, wl
-003803 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-003804 14b2 cp isrflag, zerol
-003805 f469 brne DO_INTERRUPT
- .endif
-003806 01fd movw zl, XL ; READ IP
-003807 0fee
-003808 1fff
-003809 9165
-00380a 9175 readflashcell wl, wh
-00380b 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00380c 01fb movw zl, wl
-00380d 0fee
-00380e 1fff
-00380f 9105
-003810 9115 readflashcell temp0,temp1
-003811 01f8 movw zl, temp0
-003812 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-003813 939a
-003814 938a savetos
-003815 2d8b mov tosl, isrflag
-003816 2799 clr tosh
-003817 24bb clr isrflag
-003818 eb6f ldi wl, LOW(XT_ISREXEC)
-003819 e37c ldi wh, HIGH(XT_ISREXEC)
-00381a cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00381b ff04 .dw $ff04
-00381c 7865
-00381d 7469 .db "exit"
-00381e 0a8b .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-00381f 3820 .dw PFA_EXIT
- PFA_EXIT:
-003820 91af pop XL
-003821 91bf pop XH
-003822 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-003823 ff07 .dw $ff07
-003824 7865
-003825 6365
-003826 7475
-003827 0065 .db "execute",0
-003828 381b .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-003829 382a .dw PFA_EXECUTE
- PFA_EXECUTE:
-00382a 01bc movw wl, tosl
-00382b 9189
-00382c 9199 loadtos
-00382d cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00382e 382f .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-00382f 01fd movw zl, XL
-003830 0fee
-003831 1fff
-003832 91a5
-003833 91b5 readflashcell XL,XH
-003834 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-003835 3836 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-003836 2b98 or tosh, tosl
-003837 9189
-003838 9199 loadtos
-003839 f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00383a 9611 adiw XL, 1
-00383b cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00383c 383d .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00383d 939a
-00383e 938a savetos
-00383f 01fd movw zl, xl
-003840 0fee
-003841 1fff
-003842 9185
-003843 9195 readflashcell tosl,tosh
-003844 9611 adiw xl, 1
-003845 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-003846 3847 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-003847 939a
-003848 938a savetos
-003849 01fb movw zl, wl
-00384a 9631 adiw zl,1
-00384b 0fee
-00384c 1fff
-00384d 9185
-00384e 9195 readflashcell tosl,tosh
-00384f cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-003850 3851 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-003851 939a
-003852 938a savetos
-003853 01cb movw tosl, wl
-003854 9601 adiw tosl, 1
-003855 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-003856 3857 .dw PFA_DOUSER
- PFA_DOUSER:
-003857 939a
-003858 938a savetos
-003859 01fb movw zl, wl
-00385a 9631 adiw zl, 1
-00385b 0fee
-00385c 1fff
-00385d 9185
-00385e 9195 readflashcell tosl,tosh
-00385f 0d84 add tosl, upl
-003860 1d95 adc tosh, uph
-003861 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-003862 ff07 .dw $ff07
-003863 7628
-003864 6c61
-003865 6575
-003866 0029 .db "(value)", 0
-003867 3823 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-003868 3800 .dw DO_COLON
- PFA_DOVALUE:
-003869 0720 .dw XT_DOCREATE
-00386a 0880 .dw XT_REVEAL
-00386b 0743 .dw XT_COMPILE
-00386c 386e .dw PFA_DOVALUE1
-00386d 381f .dw XT_EXIT
- PFA_DOVALUE1:
-00386e 940e 0899 call_ DO_DODOES
-003870 38b0 .dw XT_DUP
-003871 01a7 .dw XT_ICELLPLUS
-003872 3bca .dw XT_FETCHI
-003873 3829 .dw XT_EXECUTE
-003874 381f .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-003875 ff01 .dw $ff01
-003876 0040 .db "@",0
-003877 3862 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-003878 3879 .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-003879 01fc movw zl, tosl
- ; low byte is read before the high byte
-00387a 9181 ld tosl, z+
-00387b 9191 ld tosh, z+
-00387c cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00387d ff01 .dw $ff01
-00387e 0021 .db "!",0
-00387f 3875 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-003880 3881 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-003881 01fc movw zl, tosl
-003882 9189
-003883 9199 loadtos
- ; the high byte is written before the low byte
-003884 8391 std Z+1, tosh
-003885 8380 std Z+0, tosl
-003886 9189
-003887 9199 loadtos
-003888 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-003889 ff02 .dw $ff02
-00388a 2163 .db "c!"
-00388b 387d .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00388c 388d .dw PFA_CSTORE
- PFA_CSTORE:
-00388d 01fc movw zl, tosl
-00388e 9189
-00388f 9199 loadtos
-003890 8380 st Z, tosl
-003891 9189
-003892 9199 loadtos
-003893 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-003894 ff02 .dw $ff02
-003895 4063 .db "c@"
-003896 3889 .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-003897 3898 .dw PFA_CFETCH
- PFA_CFETCH:
-003898 01fc movw zl, tosl
-003899 2799 clr tosh
-00389a 8180 ld tosl, Z
-00389b cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00389c ff02 .dw $ff02
-00389d 7540 .db "@u"
-00389e 3894 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-00389f 3800 .dw DO_COLON
- PFA_FETCHU:
-0038a0 3b01 .dw XT_UP_FETCH
-0038a1 399c .dw XT_PLUS
-0038a2 3878 .dw XT_FETCH
-0038a3 381f .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-0038a4 ff02 .dw $ff02
-0038a5 7521 .db "!u"
-0038a6 389c .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-0038a7 3800 .dw DO_COLON
- PFA_STOREU:
-0038a8 3b01 .dw XT_UP_FETCH
-0038a9 399c .dw XT_PLUS
-0038aa 3880 .dw XT_STORE
-0038ab 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-0038ac ff03 .dw $ff03
-0038ad 7564
-0038ae 0070 .db "dup",0
-0038af 38a4 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-0038b0 38b1 .dw PFA_DUP
- PFA_DUP:
-0038b1 939a
-0038b2 938a savetos
-0038b3 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-0038b4 ff04 .dw $ff04
-0038b5 643f
-0038b6 7075 .db "?dup"
-0038b7 38ac .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-0038b8 38b9 .dw PFA_QDUP
- PFA_QDUP:
-0038b9 2f08 mov temp0, tosl
-0038ba 2b09 or temp0, tosh
-0038bb f011 breq PFA_QDUP1
-0038bc 939a
-0038bd 938a savetos
- PFA_QDUP1:
-0038be cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-0038bf ff04 .dw $ff04
-0038c0 7773
-0038c1 7061 .db "swap"
-0038c2 38b4 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-0038c3 38c4 .dw PFA_SWAP
- PFA_SWAP:
-0038c4 018c movw temp0, tosl
-0038c5 9189
-0038c6 9199 loadtos
-0038c7 931a st -Y, temp1
-0038c8 930a st -Y, temp0
-0038c9 cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-0038ca ff04 .dw $ff04
-0038cb 766f
-0038cc 7265 .db "over"
-0038cd 38bf .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-0038ce 38cf .dw PFA_OVER
- PFA_OVER:
-0038cf 939a
-0038d0 938a savetos
-0038d1 818a ldd tosl, Y+2
-0038d2 819b ldd tosh, Y+3
-
-0038d3 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-0038d4 ff04 .dw $ff04
-0038d5 7264
-0038d6 706f .db "drop"
-0038d7 38ca .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-0038d8 38d9 .dw PFA_DROP
- PFA_DROP:
-0038d9 9189
-0038da 9199 loadtos
-0038db cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-0038dc ff03 .dw $ff03
-0038dd 6f72
-0038de 0074 .db "rot",0
-0038df 38d4 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-0038e0 38e1 .dw PFA_ROT
- PFA_ROT:
-0038e1 018c movw temp0, tosl
-0038e2 9129 ld temp2, Y+
-0038e3 9139 ld temp3, Y+
-0038e4 9189
-0038e5 9199 loadtos
-
-0038e6 933a st -Y, temp3
-0038e7 932a st -Y, temp2
-0038e8 931a st -Y, temp1
-0038e9 930a st -Y, temp0
-
-0038ea cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-0038eb ff03 .dw $ff03
-0038ec 696e
-0038ed 0070 .db "nip",0
-0038ee 38dc .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-0038ef 38f0 .dw PFA_NIP
- PFA_NIP:
-0038f0 9622 adiw yl, 2
-0038f1 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-0038f2 ff02 .dw $ff02
-0038f3 3e72 .db "r>"
-0038f4 38eb .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-0038f5 38f6 .dw PFA_R_FROM
- PFA_R_FROM:
-0038f6 939a
-0038f7 938a savetos
-0038f8 918f pop tosl
-0038f9 919f pop tosh
-0038fa cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-0038fb ff02 .dw $ff02
-0038fc 723e .db ">r"
-0038fd 38f2 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-0038fe 38ff .dw PFA_TO_R
- PFA_TO_R:
-0038ff 939f push tosh
-003900 938f push tosl
-003901 9189
-003902 9199 loadtos
-003903 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-003904 ff02 .dw $ff02
-003905 4072 .db "r@"
-003906 38fb .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-003907 3908 .dw PFA_R_FETCH
- PFA_R_FETCH:
-003908 939a
-003909 938a savetos
-00390a 918f pop tosl
-00390b 919f pop tosh
-00390c 939f push tosh
-00390d 938f push tosl
-00390e cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-00390f ff02 .dw $ff02
-003910 3e3c .db "<>"
-003911 3904 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-003912 3800 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-003913 3fde
-003914 3919
-003915 381f .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-003916 ff02 .dw $ff02
-003917 3d30 .db "0="
-003918 390f .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-003919 391a .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00391a 2b98 or tosh, tosl
-00391b f5d1 brne PFA_ZERO1
-00391c c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00391d ff02 .dw $ff02
-00391e 3c30 .db "0<"
-00391f 3916 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-003920 3921 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-003921 fd97 sbrc tosh,7
-003922 c02a rjmp PFA_TRUE1
-003923 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-003924 ff02 .dw $ff02
-003925 3e30 .db "0>"
-003926 391d .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-003927 3928 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-003928 1582 cp tosl, zerol
-003929 0593 cpc tosh, zeroh
-00392a f15c brlt PFA_ZERO1
-00392b f151 brbs 1, PFA_ZERO1
-00392c c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00392d ff03 .dw $ff03
-00392e 3064
-00392f 003e .db "d0>",0
-003930 3924 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-003931 3932 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-003932 1582 cp tosl, zerol
-003933 0593 cpc tosh, zeroh
-003934 9189
-003935 9199 loadtos
-003936 0582 cpc tosl, zerol
-003937 0593 cpc tosh, zeroh
-003938 f0ec brlt PFA_ZERO1
-003939 f0e1 brbs 1, PFA_ZERO1
-00393a c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00393b ff03 .dw $ff03
-00393c 3064
-00393d 003c .db "d0<",0
-00393e 392d .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-00393f 3940 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-003940 9622 adiw Y,2
-003941 fd97 sbrc tosh,7
-003942 940c 394d jmp PFA_TRUE1
-003944 940c 3956 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-003946 ff04 .dw $ff04
-003947 7274
-003948 6575 .db "true"
-003949 393b .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00394a 394b .dw PFA_TRUE
- PFA_TRUE:
-00394b 939a
-00394c 938a savetos
- PFA_TRUE1:
-00394d ef8f ser tosl
-00394e ef9f ser tosh
-00394f ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-003950 ff01 .dw $ff01
-003951 0030 .db "0",0
-003952 3946 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-003953 3954 .dw PFA_ZERO
- PFA_ZERO:
-003954 939a
-003955 938a savetos
- PFA_ZERO1:
-003956 01c1 movw tosl, zerol
-003957 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-003958 ff02 .dw $ff02
-003959 3c75 .db "u<"
-00395a 3950 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00395b 395c .dw PFA_ULESS
- PFA_ULESS:
-00395c 9129 ld temp2, Y+
-00395d 9139 ld temp3, Y+
-00395e 1782 cp tosl, temp2
-00395f 0793 cpc tosh, temp3
-003960 f3a8 brlo PFA_ZERO1
-003961 f3a1 brbs 1, PFA_ZERO1
-003962 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-003963 ff02 .dw $ff02
-003964 3e75 .db "u>"
-003965 3958 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-003966 3800 .dw DO_COLON
- PFA_UGREATER:
- .endif
-003967 38c3 .DW XT_SWAP
-003968 395b .dw XT_ULESS
-003969 381f .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00396a ff01 .dw $ff01
-00396b 003c .db "<",0
-00396c 3963 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00396d 396e .dw PFA_LESS
- PFA_LESS:
-00396e 9129 ld temp2, Y+
-00396f 9139 ld temp3, Y+
-003970 1728 cp temp2, tosl
-003971 0739 cpc temp3, tosh
- PFA_LESSDONE:
-003972 f71c brge PFA_ZERO1
-003973 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-003974 ff01 .dw $ff01
-003975 003e .db ">",0
-003976 396a .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-003977 3978 .dw PFA_GREATER
- PFA_GREATER:
-003978 9129 ld temp2, Y+
-003979 9139 ld temp3, Y+
-00397a 1728 cp temp2, tosl
-00397b 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00397c f2cc brlt PFA_ZERO1
-00397d f2c1 brbs 1, PFA_ZERO1
-00397e cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-00397f ff04 .dw $ff04
-003980 6f6c
-003981 3267 .db "log2"
-003982 3974 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-003983 3984 .dw PFA_LOG2
- PFA_LOG2:
-003984 01fc movw zl, tosl
-003985 2799 clr tosh
-003986 e180 ldi tosl, 16
- PFA_LOG2_1:
-003987 958a dec tosl
-003988 f022 brmi PFA_LOG2_2 ; wrong data
-003989 0fee lsl zl
-00398a 1fff rol zh
-00398b f7d8 brcc PFA_LOG2_1
-00398c ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00398d 959a dec tosh
-00398e ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-00398f ff01 .dw $ff01
-003990 002d .db "-",0
-003991 397f .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-003992 3993 .dw PFA_MINUS
- PFA_MINUS:
-003993 9109 ld temp0, Y+
-003994 9119 ld temp1, Y+
-003995 1b08 sub temp0, tosl
-003996 0b19 sbc temp1, tosh
-003997 01c8 movw tosl, temp0
-003998 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-003999 ff01 .dw $ff01
-00399a 002b .db "+",0
-00399b 398f .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00399c 399d .dw PFA_PLUS
- PFA_PLUS:
-00399d 9109 ld temp0, Y+
-00399e 9119 ld temp1, Y+
-00399f 0f80 add tosl, temp0
-0039a0 1f91 adc tosh, temp1
-0039a1 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-0039a2 ff02 .dw $ff02
-0039a3 2a6d .db "m*"
-0039a4 3999 .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-0039a5 39a6 .dw PFA_MSTAR
- PFA_MSTAR:
-0039a6 018c movw temp0, tosl
-0039a7 9189
-0039a8 9199 loadtos
-0039a9 019c movw temp2, tosl
- ; high cell ah*bh
-0039aa 0231 muls temp3, temp1
-0039ab 0170 movw temp4, r0
- ; low cell al*bl
-0039ac 9f20 mul temp2, temp0
-0039ad 01c0 movw tosl, r0
- ; signed ah*bl
-0039ae 0330 mulsu temp3, temp0
-0039af 08f3 sbc temp5, zeroh
-0039b0 0d90 add tosh, r0
-0039b1 1ce1 adc temp4, r1
-0039b2 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-0039b3 0312 mulsu temp1, temp2
-0039b4 08f3 sbc temp5, zeroh
-0039b5 0d90 add tosh, r0
-0039b6 1ce1 adc temp4, r1
-0039b7 1cf3 adc temp5, zeroh
-
-0039b8 939a
-0039b9 938a savetos
-0039ba 01c7 movw tosl, temp4
-0039bb ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-0039bc ff06 .dw $ff06
-0039bd 6d75
-0039be 6d2f
-0039bf 646f .db "um/mod"
-0039c0 39a2 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-0039c1 39c2 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-0039c2 017c movw temp4, tosl
-
-0039c3 9129 ld temp2, Y+
-0039c4 9139 ld temp3, Y+
-
-0039c5 9109 ld temp0, Y+
-0039c6 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-0039c7 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-0039c8 2755 clr temp7
-0039c9 0f00 lsl temp0
-0039ca 1f11 rol temp1
-0039cb 1f22 rol temp2
-0039cc 1f33 rol temp3
-0039cd 1f55 rol temp7
-
- ; try subtracting divisor
-0039ce 152e cp temp2, temp4
-0039cf 053f cpc temp3, temp5
-0039d0 0552 cpc temp7,zerol
-
-0039d1 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-0039d2 9503 inc temp0
-0039d3 192e sub temp2, temp4
-0039d4 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-0039d5 954a dec temp6
-0039d6 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-0039d7 933a st -Y,temp3
-0039d8 932a st -Y,temp2
-
- ; put quotient on stack
-0039d9 01c8 movw tosl, temp0
-0039da ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-0039db ff03 .dw $ff03
-0039dc 6d75
-0039dd 002a .db "um*",0
-0039de 39bc .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-0039df 39e0 .dw PFA_UMSTAR
- PFA_UMSTAR:
-0039e0 018c movw temp0, tosl
-0039e1 9189
-0039e2 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-0039e3 9f80 mul tosl,temp0
-0039e4 01f0 movw zl, r0
-0039e5 2722 clr temp2
-0039e6 2733 clr temp3
- ; middle bytes
-0039e7 9f90 mul tosh, temp0
-0039e8 0df0 add zh, r0
-0039e9 1d21 adc temp2, r1
-0039ea 1d33 adc temp3, zeroh
-
-0039eb 9f81 mul tosl, temp1
-0039ec 0df0 add zh, r0
-0039ed 1d21 adc temp2, r1
-0039ee 1d33 adc temp3, zeroh
-
-0039ef 9f91 mul tosh, temp1
-0039f0 0d20 add temp2, r0
-0039f1 1d31 adc temp3, r1
-0039f2 01cf movw tosl, zl
-0039f3 939a
-0039f4 938a savetos
-0039f5 01c9 movw tosl, temp2
-0039f6 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-0039f7 ff06 .dw $ff06
-0039f8 6e69
-0039f9 6576
-0039fa 7472 .db "invert"
-0039fb 39db .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-0039fc 39fd .dw PFA_INVERT
- PFA_INVERT:
-0039fd 9580 com tosl
-0039fe 9590 com tosh
-0039ff ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-003a00 ff02 .dw $ff02
-003a01 2f32 .db "2/"
-003a02 39f7 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-003a03 3a04 .dw PFA_2SLASH
- PFA_2SLASH:
-003a04 9595 asr tosh
-003a05 9587 ror tosl
-003a06 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-003a07 ff02 .dw $ff02
-003a08 2a32 .db "2*"
-003a09 3a00 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-003a0a 3a0b .dw PFA_2STAR
- PFA_2STAR:
-003a0b 0f88 lsl tosl
-003a0c 1f99 rol tosh
-003a0d cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-003a0e ff03 .dw $ff03
-003a0f 6e61
-003a10 0064 .db "and",0
-003a11 3a07 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-003a12 3a13 .dw PFA_AND
- PFA_AND:
-003a13 9109 ld temp0, Y+
-003a14 9119 ld temp1, Y+
-003a15 2380 and tosl, temp0
-003a16 2391 and tosh, temp1
-003a17 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-003a18 ff02 .dw $ff02
-003a19 726f .db "or"
-003a1a 3a0e .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-003a1b 3a1c .dw PFA_OR
- PFA_OR:
-003a1c 9109 ld temp0, Y+
-003a1d 9119 ld temp1, Y+
-003a1e 2b80 or tosl, temp0
-003a1f 2b91 or tosh, temp1
-003a20 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-003a21 ff03 .dw $ff03
-003a22 6f78
-003a23 0072 .db "xor",0
-003a24 3a18 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-003a25 3a26 .dw PFA_XOR
- PFA_XOR:
-003a26 9109 ld temp0, Y+
-003a27 9119 ld temp1, Y+
-003a28 2780 eor tosl, temp0
-003a29 2791 eor tosh, temp1
-003a2a cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-003a2b ff02 .dw $ff02
-003a2c 2b31 .db "1+"
-003a2d 3a21 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-003a2e 3a2f .dw PFA_1PLUS
- PFA_1PLUS:
-003a2f 9601 adiw tosl,1
-003a30 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-003a31 ff02 .dw $ff02
-003a32 2d31 .db "1-"
-003a33 3a2b .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-003a34 3a35 .dw PFA_1MINUS
- PFA_1MINUS:
-003a35 9701 sbiw tosl, 1
-003a36 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-003a37 ff07 .dw $ff07
-003a38 6e3f
-003a39 6765
-003a3a 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-003a3b 0065 .db "?negate"
-003a3c 3a31 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-003a3d 3800 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-003a3e 3920
-003a3f 3835 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-003a40 3a42 DEST(QNEG1)
-003a41 3e26 .DW XT_NEGATE
-003a42 381f QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-003a43 ff06 .dw $ff06
-003a44 736c
-003a45 6968
-003a46 7466 .db "lshift"
-003a47 3a37 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-003a48 3a49 .dw PFA_LSHIFT
- PFA_LSHIFT:
-003a49 01fc movw zl, tosl
-003a4a 9189
-003a4b 9199 loadtos
- PFA_LSHIFT1:
-003a4c 9731 sbiw zl, 1
-003a4d f01a brmi PFA_LSHIFT2
-003a4e 0f88 lsl tosl
-003a4f 1f99 rol tosh
-003a50 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-003a51 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-003a52 ff06 .dw $ff06
-003a53 7372
-003a54 6968
-003a55 7466 .db "rshift"
-003a56 3a43 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-003a57 3a58 .dw PFA_RSHIFT
- PFA_RSHIFT:
-003a58 01fc movw zl, tosl
-003a59 9189
-003a5a 9199 loadtos
- PFA_RSHIFT1:
-003a5b 9731 sbiw zl, 1
-003a5c f01a brmi PFA_RSHIFT2
-003a5d 9596 lsr tosh
-003a5e 9587 ror tosl
-003a5f cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-003a60 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-003a61 ff02 .dw $ff02
-003a62 212b .db "+!"
-003a63 3a52 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-003a64 3a65 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-003a65 01fc movw zl, tosl
-003a66 9189
-003a67 9199 loadtos
-003a68 8120 ldd temp2, Z+0
-003a69 8131 ldd temp3, Z+1
-003a6a 0f82 add tosl, temp2
-003a6b 1f93 adc tosh, temp3
-003a6c 8380 std Z+0, tosl
-003a6d 8391 std Z+1, tosh
-003a6e 9189
-003a6f 9199 loadtos
-003a70 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-003a71 ff03 .dw $ff03
-003a72 7072
-003a73 0040 .db "rp@",0
-003a74 3a61 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-003a75 3a76 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-003a76 939a
-003a77 938a savetos
-003a78 b78d in tosl, SPL
-003a79 b79e in tosh, SPH
-003a7a cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-003a7b ff03 .dw $ff03
-003a7c 7072
-003a7d 0021 .db "rp!",0
-003a7e 3a71 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-003a7f 3a80 .dw PFA_RP_STORE
- PFA_RP_STORE:
-003a80 b72f in temp2, SREG
-003a81 94f8 cli
-003a82 bf8d out SPL, tosl
-003a83 bf9e out SPH, tosh
-003a84 bf2f out SREG, temp2
-003a85 9189
-003a86 9199 loadtos
-003a87 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-003a88 ff03 .dw $ff03
-003a89 7073
-003a8a 0040 .db "sp@",0
-003a8b 3a7b .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-003a8c 3a8d .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-003a8d 939a
-003a8e 938a savetos
-003a8f 01ce movw tosl, yl
-003a90 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-003a91 ff03 .dw $ff03
-003a92 7073
-003a93 0021 .db "sp!",0
-003a94 3a88 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-003a95 3a96 .dw PFA_SP_STORE
- PFA_SP_STORE:
-003a96 01ec movw yl, tosl
-003a97 9189
-003a98 9199 loadtos
-003a99 cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-003a9a 3a9b .dw PFA_DODO
- PFA_DODO:
-003a9b 9129 ld temp2, Y+
-003a9c 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-003a9d e8e0 ldi zl, $80
-003a9e 0f3e add temp3, zl
-003a9f 1b82 sub tosl, temp2
-003aa0 0b93 sbc tosh, temp3
-
-003aa1 933f push temp3
-003aa2 932f push temp2 ; limit ( --> limit + $8000)
-003aa3 939f push tosh
-003aa4 938f push tosl ; start -> index ( --> index - (limit - $8000)
-003aa5 9189
-003aa6 9199 loadtos
-003aa7 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-003aa8 ff01 .dw $FF01
-003aa9 0069 .db "i",0
-003aaa 3a91 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-003aab 3aac .dw PFA_I
- PFA_I:
-003aac 939a
-003aad 938a savetos
-003aae 918f pop tosl
-003aaf 919f pop tosh ; index
-003ab0 91ef pop zl
-003ab1 91ff pop zh ; limit
-003ab2 93ff push zh
-003ab3 93ef push zl
-003ab4 939f push tosh
-003ab5 938f push tosl
-003ab6 0f8e add tosl, zl
-003ab7 1f9f adc tosh, zh
-003ab8 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-003ab9 3aba .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-003aba 91ef pop zl
-003abb 91ff pop zh
-003abc 0fe8 add zl, tosl
-003abd 1ff9 adc zh, tosh
-003abe 9189
-003abf 9199 loadtos
-003ac0 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-003ac1 93ff push zh
-003ac2 93ef push zl
-003ac3 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-003ac4 910f pop temp0
-003ac5 911f pop temp1 ; remove limit
-003ac6 9611 adiw xl, 1 ; skip branch-back address
-003ac7 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-003ac8 3ac9 .dw PFA_DOLOOP
- PFA_DOLOOP:
-003ac9 91ef pop zl
-003aca 91ff pop zh
-003acb 9631 adiw zl,1
-003acc f3bb brvs PFA_DOPLUSLOOP_LEAVE
-003acd cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-003ace ff06 .dw $ff06
-003acf 6e75
-003ad0 6f6c
-003ad1 706f .db "unloop"
-003ad2 3aa8 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-003ad3 3ad4 .dw PFA_UNLOOP
- PFA_UNLOOP:
-003ad4 911f pop temp1
-003ad5 910f pop temp0
-003ad6 911f pop temp1
-003ad7 910f pop temp0
-003ad8 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-003ad9 ff06 .dw $ff06
-003ada 6d63
-003adb 766f
-003adc 3e65 .db "cmove>"
-003add 3ace .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-003ade 3adf .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-003adf 93bf push xh
-003ae0 93af push xl
-003ae1 91e9 ld zl, Y+
-003ae2 91f9 ld zh, Y+ ; addr-to
-003ae3 91a9 ld xl, Y+
-003ae4 91b9 ld xh, Y+ ; addr-from
-003ae5 2f09 mov temp0, tosh
-003ae6 2b08 or temp0, tosl
-003ae7 f041 brbs 1, PFA_CMOVE_G1
-003ae8 0fe8 add zl, tosl
-003ae9 1ff9 adc zh, tosh
-003aea 0fa8 add xl, tosl
-003aeb 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-003aec 911e ld temp1, -X
-003aed 9312 st -Z, temp1
-003aee 9701 sbiw tosl, 1
-003aef f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-003af0 91af pop xl
-003af1 91bf pop xh
-003af2 9189
-003af3 9199 loadtos
-003af4 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-003af5 ff02 .dw $ff02
-003af6 3c3e .db "><"
-003af7 3ad9 .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-003af8 3af9 .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-003af9 2f09 mov temp0, tosh
-003afa 2f98 mov tosh, tosl
-003afb 2f80 mov tosl, temp0
-003afc cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-003afd ff03 .dw $ff03
-003afe 7075
-003aff 0040 .db "up@",0
-003b00 3af5 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-003b01 3b02 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-003b02 939a
-003b03 938a savetos
-003b04 01c2 movw tosl, upl
-003b05 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-003b06 ff03 .dw $ff03
-003b07 7075
-003b08 0021 .db "up!",0
-003b09 3afd .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-003b0a 3b0b .dw PFA_UP_STORE
- PFA_UP_STORE:
-003b0b 012c movw upl, tosl
-003b0c 9189
-003b0d 9199 loadtos
-003b0e ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-003b0f ff03 .dw $ff03
-003b10 6d31
-003b11 0073 .db "1ms",0
-003b12 3b06 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-003b13 3b14 .dw PFA_1MS
- PFA_1MS:
-003b14 eae0
-003b15 e0ff
-003b16 9731
-003b17 f7f1 delay 1000
-003b18 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-003b19 ff03 .dw $ff03
-003b1a 3e32
-003b1b 0072 .db "2>r",0
-003b1c 3b0f .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-003b1d 3b1e .dw PFA_2TO_R
- PFA_2TO_R:
-003b1e 01fc movw zl, tosl
-003b1f 9189
-003b20 9199 loadtos
-003b21 939f push tosh
-003b22 938f push tosl
-003b23 93ff push zh
-003b24 93ef push zl
-003b25 9189
-003b26 9199 loadtos
-003b27 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-003b28 ff03 .dw $ff03
-003b29 7232
-003b2a 003e .db "2r>",0
-003b2b 3b19 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-003b2c 3b2d .dw PFA_2R_FROM
- PFA_2R_FROM:
-003b2d 939a
-003b2e 938a savetos
-003b2f 91ef pop zl
-003b30 91ff pop zh
-003b31 918f pop tosl
-003b32 919f pop tosh
-003b33 939a
-003b34 938a savetos
-003b35 01cf movw tosl, zl
-003b36 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-003b37 ff02 .dw $ff02
-003b38 6521 .db "!e"
-003b39 3b28 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-003b3a 3b3b .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-003b3b 01fc movw zl, tosl
-003b3c 9189
-003b3d 9199 loadtos
-003b3e b72f in_ temp2, SREG
-003b3f 94f8 cli
-003b40 d028 rcall PFA_FETCHE2
-003b41 b500 in_ temp0, EEDR
-003b42 1708 cp temp0,tosl
-003b43 f009 breq PFA_STOREE3
-003b44 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-003b45 9631 adiw zl,1
-003b46 d022 rcall PFA_FETCHE2
-003b47 b500 in_ temp0, EEDR
-003b48 1709 cp temp0,tosh
-003b49 f011 breq PFA_STOREE4
-003b4a 2f89 mov tosl, tosh
-003b4b d004 rcall PFA_STOREE1
- PFA_STOREE4:
-003b4c bf2f out_ SREG, temp2
-003b4d 9189
-003b4e 9199 loadtos
-003b4f ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-003b50 99f9 sbic EECR, EEPE
-003b51 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-003b52 b707 in_ temp0, SPMCSR
-003b53 fd00 sbrc temp0,SPMEN
-003b54 cffd rjmp PFA_STOREE2
-
-003b55 bdf2 out_ EEARH,zh
-003b56 bde1 out_ EEARL,zl
-003b57 bd80 out_ EEDR, tosl
-003b58 9afa sbi EECR,EEMPE
-003b59 9af9 sbi EECR,EEPE
-
-003b5a 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-003b5b ff02 .dw $ff02
-003b5c 6540 .db "@e"
-003b5d 3b37 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-003b5e 3b5f .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-003b5f b72f in_ temp2, SREG
-003b60 94f8 cli
-003b61 01fc movw zl, tosl
-003b62 d006 rcall PFA_FETCHE2
-003b63 b580 in_ tosl, EEDR
-
-003b64 9631 adiw zl,1
-
-003b65 d003 rcall PFA_FETCHE2
-003b66 b590 in_ tosh, EEDR
-003b67 bf2f out_ SREG, temp2
-003b68 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-003b69 99f9 sbic EECR, EEPE
-003b6a cffe rjmp PFA_FETCHE2
-
-003b6b bdf2 out_ EEARH,zh
-003b6c bde1 out_ EEARL,zl
-
-003b6d 9af8 sbi EECR,EERE
-003b6e 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-003b6f ff02 .dw $ff02
-003b70 6921 .db "!i"
-003b71 3b5b .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-003b72 3dfe .dw PFA_DODEFER1
- PFA_STOREI:
-003b73 0088 .dw EE_STOREI
-003b74 3d9f .dw XT_EDEFERFETCH
-003b75 3da9 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-003b76 ff09 .dw $ff09
-003b77 2128
-003b78 2d69
-003b79 726e
-003b7a 7777
-003b7b 0029 .db "(!i-nrww)",0
-003b7c 3b6f .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-003b7d 3b7e .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-003b7e b71f in temp1,SREG
-003b7f 931f push temp1
-003b80 94f8 cli
-
-003b81 019c movw temp2, tosl ; save the (word) address
-003b82 9189
-003b83 9199 loadtos ; get the new value for the flash cell
-003b84 93af push xl
-003b85 93bf push xh
-003b86 93cf push yl
-003b87 93df push yh
-003b88 d009 rcall DO_STOREI_atmega
-003b89 91df pop yh
-003b8a 91cf pop yl
-003b8b 91bf pop xh
-003b8c 91af pop xl
- ; finally clear the stack
-003b8d 9189
-003b8e 9199 loadtos
-003b8f 911f pop temp1
- ; restore status register (and interrupt enable flag)
-003b90 bf1f out SREG,temp1
-
-003b91 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-003b92 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-003b93 94e0 com temp4
-003b94 94f0 com temp5
-003b95 218e and tosl, temp4
-003b96 219f and tosh, temp5
-003b97 2b98 or tosh, tosl
-003b98 f019 breq DO_STOREI_writepage
-003b99 01f9 movw zl, temp2
-003b9a e002 ldi temp0,(1<<PGERS)
-003b9b d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-003b9c 01f9 movw zl, temp2
-003b9d e004 ldi temp0,(1<<PGWRT)
-003b9e d01d rcall dospm
-
- ; reenable RWW section
-003b9f 01f9 movw zl, temp2
-003ba0 e100 ldi temp0,(1<<RWWSRE)
-003ba1 d01a rcall dospm
-003ba2 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-003ba3 01f9 movw zl, temp2
- ; get the beginning of page
-003ba4 7ce0 andi zl,low(pagemask)
-003ba5 7fff andi zh,high(pagemask)
-003ba6 01ef movw y, z
- ; loop counter (in words)
-003ba7 e4a0 ldi xl,low(pagesize)
-003ba8 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-003ba9 01fe movw z, y
-003baa 0fee
-003bab 1fff
-003bac 9145
-003bad 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-003bae 01fe movw z, y
-003baf 17e2 cp zl, temp2
-003bb0 07f3 cpc zh, temp3
-003bb1 f011 breq pageload_newdata
-003bb2 010a movw r0, temp6
-003bb3 c002 rjmp pageload_cont
- pageload_newdata:
-003bb4 017a movw temp4, temp6
-003bb5 010c movw r0, tosl
- pageload_cont:
-003bb6 2700 clr temp0
-003bb7 d004 rcall dospm
-003bb8 9621 adiw y, 1
-003bb9 9711 sbiw x, 1
-003bba f771 brne pageload_loop
-
- pageload_done:
-003bbb 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-003bbc 99f9 sbic EECR, EEPE
-003bbd cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-003bbe b717 in_ temp1, SPMCSR
-003bbf fd10 sbrc temp1, SPMEN
-003bc0 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-003bc1 0fee
-003bc2 1fff writeflashcell
- ; execute spm
-003bc3 6001 ori temp0, (1<<SPMEN)
-003bc4 bf07 out_ SPMCSR,temp0
-003bc5 95e8 spm
-003bc6 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-003bc7 ff02 .dw $ff02
-003bc8 6940 .db "@i"
-003bc9 3b76 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-003bca 3bcb .dw PFA_FETCHI
- PFA_FETCHI:
-003bcb 01fc movw zl, tosl
-003bcc 0fee
-003bcd 1fff
-003bce 9185
-003bcf 9195 readflashcell tosl,tosh
-003bd0 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .elif AMFORTH_NRWW_SIZE>4000
- .include "dict/core_4k.inc"
-
- ; in a short distance to DO_NEXT
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-003bd1 ff03 .dw $ff03
-003bd2 3e6e
-003bd3 0072 .db "n>r",0
-003bd4 3bc7 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-003bd5 3bd6 .dw PFA_N_TO_R
- PFA_N_TO_R:
-003bd6 01fc movw zl, tosl
-003bd7 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-003bd8 9189
-003bd9 9199 loadtos
-003bda 939f push tosh
-003bdb 938f push tosl
-003bdc 950a dec temp0
-003bdd f7d1 brne PFA_N_TO_R1
-003bde 93ef push zl
-003bdf 93ff push zh
-003be0 9189
-003be1 9199 loadtos
-003be2 cc21 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-003be3 ff03 .dw $ff03
-003be4 726e
-003be5 003e .db "nr>",0
-003be6 3bd1 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-003be7 3be8 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-003be8 939a
-003be9 938a savetos
-003bea 91ff pop zh
-003beb 91ef pop zl
-003bec 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-003bed 918f pop tosl
-003bee 919f pop tosh
-003bef 939a
-003bf0 938a savetos
-003bf1 950a dec temp0
-003bf2 f7d1 brne PFA_N_R_FROM1
-003bf3 01cf movw tosl, zl
-003bf4 cc0f jmp_ DO_NEXT
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-003bf5 ff03 .dw $ff03
-003bf6 3264
-003bf7 002a .db "d2*",0
-003bf8 3be3 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-003bf9 3bfa .dw PFA_D2STAR
- PFA_D2STAR:
-003bfa 9109 ld temp0, Y+
-003bfb 9119 ld temp1, Y+
-003bfc 0f00 lsl temp0
-003bfd 1f11 rol temp1
-003bfe 1f88 rol tosl
-003bff 1f99 rol tosh
-003c00 931a st -Y, temp1
-003c01 930a st -Y, temp0
-003c02 cc01 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-003c03 ff03 .dw $ff03
-003c04 3264
-003c05 002f .db "d2/",0
-003c06 3bf5 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-003c07 3c08 .dw PFA_D2SLASH
- PFA_D2SLASH:
-003c08 9109 ld temp0, Y+
-003c09 9119 ld temp1, Y+
-003c0a 9595 asr tosh
-003c0b 9587 ror tosl
-003c0c 9517 ror temp1
-003c0d 9507 ror temp0
-003c0e 931a st -Y, temp1
-003c0f 930a st -Y, temp0
-003c10 cbf3 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-003c11 ff02 .dw $ff02
-003c12 2b64 .db "d+"
-003c13 3c03 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-003c14 3c15 .dw PFA_DPLUS
- PFA_DPLUS:
-003c15 9129 ld temp2, Y+
-003c16 9139 ld temp3, Y+
-
-003c17 90e9 ld temp4, Y+
-003c18 90f9 ld temp5, Y+
-003c19 9149 ld temp6, Y+
-003c1a 9159 ld temp7, Y+
-
-003c1b 0f24 add temp2, temp6
-003c1c 1f35 adc temp3, temp7
-003c1d 1d8e adc tosl, temp4
-003c1e 1d9f adc tosh, temp5
-
-003c1f 933a st -Y, temp3
-003c20 932a st -Y, temp2
-003c21 cbe2 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-003c22 ff02 .dw $ff02
-003c23 2d64 .db "d-"
-003c24 3c11 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-003c25 3c26 .dw PFA_DMINUS
- PFA_DMINUS:
-003c26 9129 ld temp2, Y+
-003c27 9139 ld temp3, Y+
-
-003c28 90e9 ld temp4, Y+
-003c29 90f9 ld temp5, Y+
-003c2a 9149 ld temp6, Y+
-003c2b 9159 ld temp7, Y+
-
-003c2c 1b42 sub temp6, temp2
-003c2d 0b53 sbc temp7, temp3
-003c2e 0ae8 sbc temp4, tosl
-003c2f 0af9 sbc temp5, tosh
-
-003c30 935a st -Y, temp7
-003c31 934a st -Y, temp6
-003c32 01c7 movw tosl, temp4
-003c33 cbd0 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-003c34 ff07 .dw $ff07
-003c35 6964
-003c36 766e
-003c37 7265
-003c38 0074 .db "dinvert",0
-003c39 3c22 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-003c3a 3c3b .dw PFA_DINVERT
- PFA_DINVERT:
-003c3b 9109 ld temp0, Y+
-003c3c 9119 ld temp1, Y+
-003c3d 9580 com tosl
-003c3e 9590 com tosh
-003c3f 9500 com temp0
-003c40 9510 com temp1
-003c41 931a st -Y, temp1
-003c42 930a st -Y, temp0
-003c43 cbc0 jmp_ DO_NEXT
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-003c44 ff04 .dw $ff04
-003c45 6d2f
-003c46 646f .db "/mod"
-003c47 3c34 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-003c48 3c49 .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-003c49 019c movw temp2, tosl
-
-003c4a 9109 ld temp0, Y+
-003c4b 9119 ld temp1, Y+
-
-003c4c 2f41 mov temp6,temp1 ;move dividend High to sign register
-003c4d 2743 eor temp6,temp3 ;xor divisor High with sign register
-003c4e ff17 sbrs temp1,7 ;if MSB in dividend set
-003c4f c004 rjmp PFA_SLASHMOD_1
-003c50 9510 com temp1 ; change sign of dividend
-003c51 9500 com temp0
-003c52 5f0f subi temp0,low(-1)
-003c53 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-003c54 ff37 sbrs temp3,7 ;if MSB in divisor set
-003c55 c004 rjmp PFA_SLASHMOD_2
-003c56 9530 com temp3 ; change sign of divisor
-003c57 9520 com temp2
-003c58 5f2f subi temp2,low(-1)
-003c59 4f3f sbci temp3,high(-1)
-003c5a 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-003c5b 18ff sub temp5,temp5;clear remainder High byte and carry
-003c5c e151 ldi temp7,17 ;init loop counter
-
-003c5d 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-003c5e 1f11 rol temp1
-003c5f 955a dec temp7 ;decrement counter
-003c60 f439 brne PFA_SLASHMOD_5 ;if done
-003c61 ff47 sbrs temp6,7 ; if MSB in sign register set
-003c62 c004 rjmp PFA_SLASHMOD_4
-003c63 9510 com temp1 ; change sign of result
-003c64 9500 com temp0
-003c65 5f0f subi temp0,low(-1)
-003c66 4f1f sbci temp1,high(-1)
-003c67 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-003c68 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-003c69 1cff rol temp5
-003c6a 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-003c6b 0af3 sbc temp5,temp3 ;
-003c6c f420 brcc PFA_SLASHMOD_6 ;if result negative
-003c6d 0ee2 add temp4,temp2 ; restore remainder
-003c6e 1ef3 adc temp5,temp3
-003c6f 9488 clc ; clear carry to be shifted into result
-003c70 cfec rjmp PFA_SLASHMOD_3 ;else
-003c71 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-003c72 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-003c73 92fa st -Y,temp5
-003c74 92ea st -Y,temp4
-
- ; put quotient on stack
-003c75 01c8 movw tosl, temp0
-003c76 cb8d jmp_ DO_NEXT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-003c77 ff03 .dw $ff03
-003c78 6261
-003c79 0073 .db "abs",0
-003c7a 3c44 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-003c7b 3800 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-003c7c 38b0
-003c7d 3a3d
-003c7e 381f .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-003c7f ff04 .dw $ff04
-003c80 6970
-003c81 6b63 .db "pick"
-003c82 3c77 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-003c83 3800 .dw DO_COLON
- PFA_PICK:
- .endif
-003c84 3a2e .dw XT_1PLUS
-003c85 3ec3 .dw XT_CELLS
-003c86 3a8c .dw XT_SP_FETCH
-003c87 399c .dw XT_PLUS
-003c88 3878 .dw XT_FETCH
-003c89 381f .dw XT_EXIT
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-003c8a ff05 .dw $ff05
-003c8b 6563
-003c8c 6c6c
-003c8d 002b .db "cell+",0
-003c8e 3c7f .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-003c8f 3c90 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-003c90 9602 adiw tosl, CELLSIZE
-003c91 cb72 jmp_ DO_NEXT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-003c92 ff04 .dw $ff04
-003c93 692b
-003c94 746e .db "+int"
-003c95 3c8a .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-003c96 3c97 .dw PFA_INTON
- PFA_INTON:
-003c97 9478 sei
-003c98 cb6b jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-003c99 ff04 .dw $ff04
-003c9a 692d
-003c9b 746e .db "-int"
-003c9c 3c92 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-003c9d 3c9e .dw PFA_INTOFF
- PFA_INTOFF:
-003c9e 94f8 cli
-003c9f cb64 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-003ca0 ff04 .dw $ff04
-003ca1 6e69
-003ca2 2174 .db "int!"
-003ca3 3c99 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-003ca4 3800 .dw DO_COLON
- PFA_INTSTORE:
-003ca5 383c .dw XT_DOLITERAL
-003ca6 0000 .dw intvec
-003ca7 399c .dw XT_PLUS
-003ca8 3b3a .dw XT_STOREE
-003ca9 381f .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-003caa ff04 .dw $ff04
-003cab 6e69
-003cac 4074 .db "int@"
-003cad 3ca0 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-003cae 3800 .dw DO_COLON
- PFA_INTFETCH:
-003caf 383c .dw XT_DOLITERAL
-003cb0 0000 .dw intvec
-003cb1 399c .dw XT_PLUS
-003cb2 3b5e .dw XT_FETCHE
-003cb3 381f .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-003cb4 ff08 .dw $ff08
-003cb5 6e69
-003cb6 2d74
-003cb7 7274
-003cb8 7061 .db "int-trap"
-003cb9 3caa .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-003cba 3cbb .dw PFA_INTTRAP
- PFA_INTTRAP:
-003cbb 2eb8 mov isrflag, tosl
-003cbc 9189
-003cbd 9199 loadtos
-003cbe cb45 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-003cbf 3800 .dw DO_COLON
- PFA_ISREXEC:
-003cc0 3cae .dw XT_INTFETCH
-003cc1 3829 .dw XT_EXECUTE
-003cc2 3cc4 .dw XT_ISREND
-003cc3 381f .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-003cc4 3cc5 .dw PFA_ISREND
- PFA_ISREND:
-003cc5 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-003cc6 cb3d jmp_ DO_NEXT
- PFA_ISREND1:
-003cc7 9518 reti
- .endif
-
- ; now the relocatable colon words
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-003cc8 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-003cc9 03b7 .dw XT_DOSLITERAL
-003cca 0003 .dw 3
-003ccb 6f20
-003ccc 006b .db " ok",0
- .endif
-003ccd 03ea .dw XT_ITYPE
-003cce 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-003ccf ff03 .dw $FF03
-003cd0 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-003cd1 006b .db ".ok"
-003cd2 3cb4 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-003cd3 3dfe .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-003cd4 001c .dw USER_P_OK
-003cd5 3dc7 .dw XT_UDEFERFETCH
-003cd6 3dd3 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-003cd7 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-003cd8 03b7 .dw XT_DOSLITERAL
-003cd9 0002 .dw 2
-003cda 203e .db "> "
- .endif
-003cdb 3fa0 .dw XT_CR
-003cdc 03ea .dw XT_ITYPE
-003cdd 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-003cde ff06 .dw $FF06
-003cdf 722e
-003ce0 6165
-003ce1 7964 .db ".ready"
-003ce2 3ccf .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-003ce3 3dfe .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-003ce4 0020 .dw USER_P_RDY
-003ce5 3dc7 .dw XT_UDEFERFETCH
-003ce6 3dd3 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-003ce7 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-003ce8 03b7 .dw XT_DOSLITERAL
-003ce9 0004 .dw 4
-003cea 3f20
-003ceb 203f .db " ?? "
- .endif
-003cec 03ea .dw XT_ITYPE
-003ced 3ebc .dw XT_BASE
-003cee 3878 .dw XT_FETCH
-003cef 38fe .dw XT_TO_R
-003cf0 3f40 .dw XT_DECIMAL
-003cf1 036c .dw XT_DOT
-003cf2 3ee1 .dw XT_TO_IN
-003cf3 3878 .dw XT_FETCH
-003cf4 036c .dw XT_DOT
-003cf5 38f5 .dw XT_R_FROM
-003cf6 3ebc .dw XT_BASE
-003cf7 3880 .dw XT_STORE
-003cf8 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-003cf9 ff06 .dw $FF06
-003cfa 652e
-003cfb 7272
-003cfc 726f .db ".error"
-003cfd 3cde .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-003cfe 3dfe .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-003cff 001e .dw USER_P_ERR
-003d00 3dc7 .dw XT_UDEFERFETCH
-003d01 3dd3 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-003d02 ff04 .dw $ff04
-003d03 7571
-003d04 7469 .db "quit"
-003d05 3cf9 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-003d06 3800 .dw DO_COLON
- .endif
- PFA_QUIT:
-003d07 0843
-003d08 084a
-003d09 3880 .dw XT_LP0,XT_LP,XT_STORE
-003d0a 05bc .dw XT_SP0
-003d0b 3a95 .dw XT_SP_STORE
-003d0c 05c9 .dw XT_RP0
-003d0d 3a7f .dw XT_RP_STORE
-003d0e 08d8 .dw XT_LBRACKET
-
- PFA_QUIT2:
-003d0f 3eb6 .dw XT_STATE
-003d10 3878 .dw XT_FETCH
-003d11 3919 .dw XT_ZEROEQUAL
-003d12 3835 .dw XT_DOCONDBRANCH
-003d13 3d15 DEST(PFA_QUIT4)
-003d14 3ce3 .dw XT_PROMPTREADY
- PFA_QUIT4:
-003d15 04d0 .dw XT_REFILL
-003d16 3835 .dw XT_DOCONDBRANCH
-003d17 3d27 DEST(PFA_QUIT3)
-003d18 383c .dw XT_DOLITERAL
-003d19 0617 .dw XT_INTERPRET
-003d1a 3d6f .dw XT_CATCH
-003d1b 38b8 .dw XT_QDUP
-003d1c 3835 .dw XT_DOCONDBRANCH
-003d1d 3d27 DEST(PFA_QUIT3)
-003d1e 38b0 .dw XT_DUP
-003d1f 383c .dw XT_DOLITERAL
-003d20 fffe .dw -2
-003d21 396d .dw XT_LESS
-003d22 3835 .dw XT_DOCONDBRANCH
-003d23 3d25 DEST(PFA_QUIT5)
-003d24 3cfe .dw XT_PROMPTERROR
- PFA_QUIT5:
-003d25 382e .dw XT_DOBRANCH
-003d26 3d07 DEST(PFA_QUIT)
- PFA_QUIT3:
-003d27 3cd3 .dw XT_PROMPTOK
-003d28 382e .dw XT_DOBRANCH
-003d29 3d0f DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-003d2a ff05 .dw $ff05
-003d2b 6170
-003d2c 7375
-003d2d 0065 .db "pause",0
-003d2e 3d02 .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-003d2f 3dfe .dw PFA_DODEFER1
- PFA_PAUSE:
-003d30 01a3 .dw ram_pause
-003d31 3db3 .dw XT_RDEFERFETCH
-003d32 3dbd .dw XT_RDEFERSTORE
-
- .dseg
-0001a3 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-003d33 ff04 .dw $ff04
-003d34 6f63
-003d35 646c .db "cold"
-003d36 3d2a .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-003d37 3d38 .dw PFA_COLD
- PFA_COLD:
-003d38 b6a4 in_ mcu_boot, MCUSR
-003d39 2422 clr zerol
-003d3a 2433 clr zeroh
-003d3b 24bb clr isrflag
-003d3c be24 out_ MCUSR, zerol
- ; clear RAM
-003d3d e0e0 ldi zl, low(ramstart)
-003d3e e0f1 ldi zh, high(ramstart)
- clearloop:
-003d3f 9221 st Z+, zerol
-003d40 30e0 cpi zl, low(sram_size+ramstart)
-003d41 f7e9 brne clearloop
-003d42 30fb cpi zh, high(sram_size+ramstart)
-003d43 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-0001a5 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-003d44 eae5 ldi zl, low(ram_user1)
-003d45 e0f1 ldi zh, high(ram_user1)
-003d46 012f movw upl, zl
- ; init return stack pointer
-003d47 ef0f ldi temp0,low(rstackstart)
-003d48 bf0d out_ SPL,temp0
-003d49 8304 std Z+4, temp0
-003d4a e01a ldi temp1,high(rstackstart)
-003d4b bf1e out_ SPH,temp1
-003d4c 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-003d4d eacf ldi yl,low(stackstart)
-003d4e 83c6 std Z+6, yl
-003d4f e0da ldi yh,high(stackstart)
-003d50 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-003d51 e5a9 ldi XL, low(PFA_WARM)
-003d52 e3bd ldi XH, high(PFA_WARM)
- ; its a far jump...
-003d53 cab0 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-003d54 ff04 .dw $ff04
-003d55 6177
-003d56 6d72 .db "warm"
-003d57 3d33 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-003d58 3800 .dw DO_COLON
- PFA_WARM:
- .endif
-003d59 0289 .dw XT_INIT_RAM
-003d5a 383c .dw XT_DOLITERAL
-003d5b 017b .dw XT_NOOP
-003d5c 383c .dw XT_DOLITERAL
-003d5d 3d2f .dw XT_PAUSE
-003d5e 3dde .dw XT_DEFERSTORE
-003d5f 08d8 .dw XT_LBRACKET
-003d60 3f5b .dw XT_TURNKEY
-003d61 3d06 .dw XT_QUIT ; never returns
-
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-003d62 ff07 .dw $ff07
-003d63 6168
-003d64 646e
-003d65 656c
-003d66 0072 .db "handler",0
-003d67 3d54 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-003d68 3857 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-003d69 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-003d6a ff05 .dw $ff05
-003d6b 6163
-003d6c 6374
-003d6d 0068 .db "catch",0
-003d6e 3d62 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-003d6f 3800 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-003d70 3a8c .dw XT_SP_FETCH
-003d71 38fe .dw XT_TO_R
- ; handler @ >r
-003d72 3d68 .dw XT_HANDLER
-003d73 3878 .dw XT_FETCH
-003d74 38fe .dw XT_TO_R
- ; rp@ handler !
-003d75 3a75 .dw XT_RP_FETCH
-003d76 3d68 .dw XT_HANDLER
-003d77 3880 .dw XT_STORE
-003d78 3829 .dw XT_EXECUTE
- ; r> handler !
-003d79 38f5 .dw XT_R_FROM
-003d7a 3d68 .dw XT_HANDLER
-003d7b 3880 .dw XT_STORE
-003d7c 38f5 .dw XT_R_FROM
-003d7d 38d8 .dw XT_DROP
-003d7e 3953 .dw XT_ZERO
-003d7f 381f .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-003d80 ff05 .dw $ff05
-003d81 6874
-003d82 6f72
-003d83 0077 .db "throw",0
-003d84 3d6a .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-003d85 3800 .dw DO_COLON
- PFA_THROW:
- .endif
-003d86 38b0 .dw XT_DUP
-003d87 3919 .dw XT_ZEROEQUAL
-003d88 3835 .dw XT_DOCONDBRANCH
-003d89 3d8c DEST(PFA_THROW1)
-003d8a 38d8 .dw XT_DROP
-003d8b 381f .dw XT_EXIT
- PFA_THROW1:
-003d8c 3d68 .dw XT_HANDLER
-003d8d 3878 .dw XT_FETCH
-003d8e 3a7f .dw XT_RP_STORE
-003d8f 38f5 .dw XT_R_FROM
-003d90 3d68 .dw XT_HANDLER
-003d91 3880 .dw XT_STORE
-003d92 38f5 .dw XT_R_FROM
-003d93 38c3 .dw XT_SWAP
-003d94 38fe .dw XT_TO_R
-003d95 3a95 .dw XT_SP_STORE
-003d96 38d8 .dw XT_DROP
-003d97 38f5 .dw XT_R_FROM
-003d98 381f .dw XT_EXIT
-
-
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-003d99 ff07 .dw $ff07
-003d9a 6445
-003d9b 6665
-003d9c 7265
-003d9d 0040 .db "Edefer@",0
-003d9e 3d80 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-003d9f 3800 .dw DO_COLON
- PFA_EDEFERFETCH:
-003da0 3bca .dw XT_FETCHI
-003da1 3b5e .dw XT_FETCHE
-003da2 381f .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-003da3 ff07 .dw $ff07
-003da4 6445
-003da5 6665
-003da6 7265
-003da7 0021 .db "Edefer!",0
-003da8 3d99 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-003da9 3800 .dw DO_COLON
- PFA_EDEFERSTORE:
-003daa 3bca .dw XT_FETCHI
-003dab 3b3a .dw XT_STOREE
-003dac 381f .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-003dad ff07 .dw $ff07
-003dae 6452
-003daf 6665
-003db0 7265
-003db1 0040 .db "Rdefer@",0
-003db2 3da3 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-003db3 3800 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-003db4 3bca .dw XT_FETCHI
-003db5 3878 .dw XT_FETCH
-003db6 381f .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-003db7 ff07 .dw $ff07
-003db8 6452
-003db9 6665
-003dba 7265
-003dbb 0021 .db "Rdefer!",0
-003dbc 3dad .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-003dbd 3800 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-003dbe 3bca .dw XT_FETCHI
-003dbf 3880 .dw XT_STORE
-003dc0 381f .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-003dc1 ff07 .dw $ff07
-003dc2 6455
-003dc3 6665
-003dc4 7265
-003dc5 0040 .db "Udefer@",0
-003dc6 3db7 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-003dc7 3800 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-003dc8 3bca .dw XT_FETCHI
-003dc9 3b01 .dw XT_UP_FETCH
-003dca 399c .dw XT_PLUS
-003dcb 3878 .dw XT_FETCH
-003dcc 381f .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-003dcd ff07 .dw $ff07
-003dce 6455
-003dcf 6665
-003dd0 7265
-003dd1 0021 .db "Udefer!",0
-003dd2 3dc1 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-003dd3 3800 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-003dd4 3bca .dw XT_FETCHI
-003dd5 3b01 .dw XT_UP_FETCH
-003dd6 399c .dw XT_PLUS
-003dd7 3880 .dw XT_STORE
-003dd8 381f .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-003dd9 ff06 .dw $ff06
-003dda 6564
-003ddb 6566
-003ddc 2172 .db "defer!"
-003ddd 3dcd .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-003dde 3800 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-003ddf 3fcf .dw XT_TO_BODY
-003de0 38b0 .dw XT_DUP
-003de1 01a7 .dw XT_ICELLPLUS
-003de2 01a7 .dw XT_ICELLPLUS
-003de3 3bca .dw XT_FETCHI
-003de4 3829 .dw XT_EXECUTE
-003de5 381f .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-003de6 ff06 .dw $ff06
-003de7 6564
-003de8 6566
-003de9 4072 .db "defer@"
-003dea 3dd9 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-003deb 3800 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-003dec 3fcf .dw XT_TO_BODY
-003ded 38b0 .dw XT_DUP
-003dee 01a7 .dw XT_ICELLPLUS
-003def 3bca .dw XT_FETCHI
-003df0 3829 .dw XT_EXECUTE
-003df1 381f .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-003df2 ff07 .dw $ff07
-003df3 6428
-003df4 6665
-003df5 7265
-003df6 0029 .db "(defer)", 0
-003df7 3de6 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-003df8 3800 .dw DO_COLON
- PFA_DODEFER:
-003df9 0720 .dw XT_DOCREATE
-003dfa 0880 .dw XT_REVEAL
-003dfb 0743 .dw XT_COMPILE
-003dfc 3dfe .dw PFA_DODEFER1
-003dfd 381f .dw XT_EXIT
- PFA_DODEFER1:
-003dfe 940e 0899 call_ DO_DODOES
-003e00 38b0 .dw XT_DUP
-003e01 01a7 .dw XT_ICELLPLUS
-003e02 3bca .dw XT_FETCHI
-003e03 3829 .dw XT_EXECUTE
-003e04 3829 .dw XT_EXECUTE
-003e05 381f .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-003e06 ff02 .dw $ff02
-003e07 2e75 .db "u."
-003e08 3df2 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-003e09 3800 .dw DO_COLON
- PFA_UDOT:
- .endif
-003e0a 3953 .dw XT_ZERO
-003e0b 0374 .dw XT_UDDOT
-003e0c 381f .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-003e0d ff03 .dw $ff03
-003e0e 2e75
-003e0f 0072 .db "u.r",0
-003e10 3e06 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-003e11 3800 .dw DO_COLON
- PFA_UDOTR:
- .endif
-003e12 3953 .dw XT_ZERO
-003e13 38c3 .dw XT_SWAP
-003e14 037d .dw XT_UDDOTR
-003e15 381f .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-003e16 ff05 .dw $ff05
-003e17 2f75
-003e18 6f6d
-003e19 0064 .db "u/mod",0
-003e1a 3e0d .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-003e1b 3800 .dw DO_COLON
- PFA_USLASHMOD:
-003e1c 38fe .dw XT_TO_R
-003e1d 3953 .dw XT_ZERO
-003e1e 38f5 .dw XT_R_FROM
-003e1f 39c1 .dw XT_UMSLASHMOD
-003e20 381f .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-003e21 ff06 .dw $ff06
-003e22 656e
-003e23 6167
-003e24 6574 .db "negate"
-003e25 3e16 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-003e26 3800 .dw DO_COLON
- PFA_NEGATE:
-003e27 39fc .dw XT_INVERT
-003e28 3a2e .dw XT_1PLUS
-003e29 381f .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-003e2a ff01 .dw $ff01
-003e2b 002f .db "/",0
-003e2c 3e21 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-003e2d 3800 .dw DO_COLON
- PFA_SLASH:
- .endif
-003e2e 3c48 .dw XT_SLASHMOD
-003e2f 38ef .dw XT_NIP
-003e30 381f .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-003e31 ff03 .dw $ff03
-003e32 6f6d
-003e33 0064 .db "mod",0
-003e34 3e2a .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-003e35 3800 .dw DO_COLON
- PFA_MOD:
- .endif
-003e36 3c48 .dw XT_SLASHMOD
-003e37 38d8 .dw XT_DROP
-003e38 381f .dw XT_EXIT
-
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-003e39 ff03 .dw $ff03
-003e3a 696d
-003e3b 006e .db "min",0
-003e3c 3e31 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-003e3d 3800 .dw DO_COLON
- PFA_MIN:
- .endif
-003e3e 3ec8 .dw XT_2DUP
-003e3f 3977 .dw XT_GREATER
-003e40 3835 .dw XT_DOCONDBRANCH
-003e41 3e43 DEST(PFA_MIN1)
-003e42 38c3 .dw XT_SWAP
- PFA_MIN1:
-003e43 38d8 .dw XT_DROP
-003e44 381f .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-003e45 ff03 .dw $ff03
-003e46 616d
-003e47 0078 .db "max",0
-003e48 3e39 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-003e49 3800 .dw DO_COLON
- PFA_MAX:
-
- .endif
-003e4a 3ec8 .dw XT_2DUP
-003e4b 396d .dw XT_LESS
-003e4c 3835 .dw XT_DOCONDBRANCH
-003e4d 3e4f DEST(PFA_MAX1)
-003e4e 38c3 .dw XT_SWAP
- PFA_MAX1:
-003e4f 38d8 .dw XT_DROP
-003e50 381f .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-003e51 ff06 .dw $ff06
-003e52 6977
-003e53 6874
-003e54 6e69 .db "within"
-003e55 3e45 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-003e56 3800 .dw DO_COLON
- PFA_WITHIN:
- .endif
-003e57 38ce .dw XT_OVER
-003e58 3992 .dw XT_MINUS
-003e59 38fe .dw XT_TO_R
-003e5a 3992 .dw XT_MINUS
-003e5b 38f5 .dw XT_R_FROM
-003e5c 395b .dw XT_ULESS
-003e5d 381f .dw XT_EXIT
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-003e5e ff0d .dw $ff0d
-003e5f 6873
-003e60 776f
-003e61 772d
-003e62 726f
-003e63 6c64
-003e64 7369
-003e65 0074 .db "show-wordlist",0
-003e66 3e51 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-003e67 3800 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-003e68 383c .dw XT_DOLITERAL
-003e69 3e6d .dw XT_SHOWWORD
-003e6a 38c3 .dw XT_SWAP
-003e6b 06c1 .dw XT_TRAVERSEWORDLIST
-003e6c 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-003e6d 3800 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-003e6e 06dc .dw XT_NAME2STRING
-003e6f 03ea .dw XT_ITYPE
-003e70 3fad .dw XT_SPACE ; ( -- addr n)
-003e71 394a .dw XT_TRUE
-003e72 381f .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-003e73 ff05 .dw $ff05
-003e74 6f77
-003e75 6472
-003e76 0073 .db "words",0
-003e77 3e5e .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-003e78 3800 .dw DO_COLON
- PFA_WORDS:
- .endif
-003e79 383c .dw XT_DOLITERAL
-003e7a 006e .dw CFG_ORDERLISTLEN+2
-003e7b 3b5e .dw XT_FETCHE
-003e7c 3e67 .dw XT_SHOWWORDLIST
-003e7d 381f .dw XT_EXIT
-
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-003e7e 0002 .dw $0002
-003e7f 222e .db ".",$22
-003e80 3e73 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-003e81 3800 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-003e82 3e89 .dw XT_SQUOTE
-003e83 0743 .dw XT_COMPILE
-003e84 03ea .dw XT_ITYPE
-003e85 381f .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-003e86 0002 .dw $0002
-003e87 2273 .db "s",$22
-003e88 3e7e .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-003e89 3800 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-003e8a 383c .dw XT_DOLITERAL
-003e8b 0022 .dw 34 ; 0x22
-003e8c 0575 .dw XT_PARSE ; ( -- addr n)
-003e8d 3eb6 .dw XT_STATE
-003e8e 3878 .dw XT_FETCH
-003e8f 3835 .dw XT_DOCONDBRANCH
-003e90 3e92 DEST(PFA_SQUOTE1)
-003e91 076f .dw XT_SLITERAL
- PFA_SQUOTE1:
-003e92 381f .dw XT_EXIT
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-003e93 ff04 .dw $ff04
-003e94 6966
-003e95 6c6c .db "fill"
-003e96 3e86 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-003e97 3800 .dw DO_COLON
- PFA_FILL:
-003e98 38e0 .dw XT_ROT
-003e99 38e0 .dw XT_ROT
-003e9a 38b8
-003e9b 3835 .dw XT_QDUP,XT_DOCONDBRANCH
-003e9c 3ea4 DEST(PFA_FILL2)
-003e9d 3f98 .dw XT_BOUNDS
-003e9e 3a9a .dw XT_DODO
- PFA_FILL1:
-003e9f 38b0 .dw XT_DUP
-003ea0 3aab .dw XT_I
-003ea1 388c .dw XT_CSTORE ; ( -- c c-addr)
-003ea2 3ac8 .dw XT_DOLOOP
-003ea3 3e9f .dw PFA_FILL1
- PFA_FILL2:
-003ea4 38d8 .dw XT_DROP
-003ea5 381f .dw XT_EXIT
-
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-003ea6 ff05 .dw $ff05
-003ea7 5f66
-003ea8 7063
-003ea9 0075 .db "f_cpu",0
-003eaa 3e93 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-003eab 3800 .dw DO_COLON
- PFA_F_CPU:
- .endif
-003eac 383c .dw XT_DOLITERAL
-003ead 2400 .dw (F_CPU % 65536)
-003eae 383c .dw XT_DOLITERAL
-003eaf 00f4 .dw (F_CPU / 65536)
-003eb0 381f .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-003eb1 ff05 .dw $ff05
-003eb2 7473
-003eb3 7461
-003eb4 0065 .db "state",0
-003eb5 3ea6 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-003eb6 3847 .dw PFA_DOVARIABLE
- PFA_STATE:
-003eb7 01d1 .dw ram_state
-
- .dseg
-0001d1 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-003eb8 ff04 .dw $ff04
-003eb9 6162
-003eba 6573 .db "base"
-003ebb 3eb1 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-003ebc 3857 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-003ebd 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-003ebe ff05 .dw $ff05
-003ebf 6563
-003ec0 6c6c
-003ec1 0073 .db "cells",0
-003ec2 3eb8 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-003ec3 3a0b .dw PFA_2STAR
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-003ec4 ff04 .dw $ff04
-003ec5 6432
-003ec6 7075 .db "2dup"
-003ec7 3ebe .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-003ec8 3800 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-003ec9 38ce .dw XT_OVER
-003eca 38ce .dw XT_OVER
-003ecb 381f .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-003ecc ff05 .dw $ff05
-003ecd 6432
-003ece 6f72
-003ecf 0070 .db "2drop",0
-003ed0 3ec4 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-003ed1 3800 .dw DO_COLON
- PFA_2DROP:
- .endif
-003ed2 38d8 .dw XT_DROP
-003ed3 38d8 .dw XT_DROP
-003ed4 381f .dw XT_EXIT
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-003ed5 ff04 .dw $ff04
-003ed6 7574
-003ed7 6b63 .db "tuck"
-003ed8 3ecc .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-003ed9 3800 .dw DO_COLON
- PFA_TUCK:
- .endif
-003eda 38c3 .dw XT_SWAP
-003edb 38ce .dw XT_OVER
-003edc 381f .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-003edd ff03 .dw $ff03
-003ede 693e
-003edf 006e .db ">in",0
-003ee0 3ed5 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-003ee1 3857 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-003ee2 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-003ee3 ff03 .dw $ff03
-003ee4 6170
-003ee5 0064 .db "pad",0
-003ee6 3edd .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-003ee7 3800 .dw DO_COLON
- PFA_PAD:
- .endif
-003ee8 3f22 .dw XT_HERE
-003ee9 383c .dw XT_DOLITERAL
-003eea 0028 .dw 40
-003eeb 399c .dw XT_PLUS
-003eec 381f .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-003eed ff04 .dw $ff04
-003eee 6d65
-003eef 7469 .db "emit"
-003ef0 3ee3 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-003ef1 3dfe .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-003ef2 000e .dw USER_EMIT
-003ef3 3dc7 .dw XT_UDEFERFETCH
-003ef4 3dd3 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-003ef5 ff05 .dw $ff05
-003ef6 6d65
-003ef7 7469
-003ef8 003f .db "emit?",0
-003ef9 3eed .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-003efa 3dfe .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-003efb 0010 .dw USER_EMITQ
-003efc 3dc7 .dw XT_UDEFERFETCH
-003efd 3dd3 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-003efe ff03 .dw $ff03
-003eff 656b
-003f00 0079 .db "key",0
-003f01 3ef5 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-003f02 3dfe .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-003f03 0012 .dw USER_KEY
-003f04 3dc7 .dw XT_UDEFERFETCH
-003f05 3dd3 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-003f06 ff04 .dw $ff04
-003f07 656b
-003f08 3f79 .db "key?"
-003f09 3efe .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-003f0a 3dfe .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-003f0b 0014 .dw USER_KEYQ
-003f0c 3dc7 .dw XT_UDEFERFETCH
-003f0d 3dd3 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-003f0e ff02 .dw $ff02
-003f0f 7064 .db "dp"
-003f10 3f06 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-003f11 386e .dw PFA_DOVALUE1
- PFA_DP:
-003f12 0058 .dw CFG_DP
-003f13 3d9f .dw XT_EDEFERFETCH
-003f14 3da9 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-003f15 ff05 .dw $ff05
-003f16 6865
-003f17 7265
-003f18 0065 .db "ehere",0
-003f19 3f0e .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-003f1a 386e .dw PFA_DOVALUE1
- PFA_EHERE:
-003f1b 005c .dw EE_EHERE
-003f1c 3d9f .dw XT_EDEFERFETCH
-003f1d 3da9 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-003f1e ff04 .dw $ff04
-003f1f 6568
-003f20 6572 .db "here"
-003f21 3f15 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-003f22 386e .dw PFA_DOVALUE1
- PFA_HERE:
-003f23 005a .dw EE_HERE
-003f24 3d9f .dw XT_EDEFERFETCH
-003f25 3da9 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-003f26 ff05 .dw $ff05
-003f27 6c61
-003f28 6f6c
-003f29 0074 .db "allot",0
-003f2a 3f1e .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-003f2b 3800 .dw DO_COLON
- PFA_ALLOT:
-003f2c 3f22 .dw XT_HERE
-003f2d 399c .dw XT_PLUS
-003f2e 0195 .dw XT_DOTO
-003f2f 3f23 .dw PFA_HERE
-003f30 381f .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-003f31 ff03 .dw $ff03
-003f32 6962
-003f33 006e .db "bin",0
-003f34 3f26 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-003f35 3800 .dw DO_COLON
- PFA_BIN:
- .endif
-003f36 3fea .dw XT_TWO
-003f37 3ebc .dw XT_BASE
-003f38 3880 .dw XT_STORE
-003f39 381f .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-003f3a ff07 .dw $ff07
-003f3b 6564
-003f3c 6963
-003f3d 616d
-003f3e 006c .db "decimal",0
-003f3f 3f31 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-003f40 3800 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-003f41 383c .dw XT_DOLITERAL
-003f42 000a .dw 10
-003f43 3ebc .dw XT_BASE
-003f44 3880 .dw XT_STORE
-003f45 381f .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-003f46 ff03 .dw $ff03
-003f47 6568
-003f48 0078 .db "hex",0
-003f49 3f3a .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-003f4a 3800 .dw DO_COLON
- PFA_HEX:
- .endif
-003f4b 383c .dw XT_DOLITERAL
-003f4c 0010 .dw 16
-003f4d 3ebc .dw XT_BASE
-003f4e 3880 .dw XT_STORE
-003f4f 381f .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-003f50 ff02 .dw $ff02
-003f51 6c62 .db "bl"
-003f52 3f46 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-003f53 3847 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-003f54 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-003f55 ff07 .dw $ff07
-003f56 7574
-003f57 6e72
-003f58 656b
-003f59 0079 .db "turnkey",0
-003f5a 3f50 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-003f5b 3dfe .dw PFA_DODEFER1
- PFA_TURNKEY:
-003f5c 0064 .dw CFG_TURNKEY
-003f5d 3d9f .dw XT_EDEFERFETCH
-003f5e 3da9 .dw XT_EDEFERSTORE
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-003f5f ff07 .dw $ff07
-003f60 6f74
-003f61 7075
-003f62 6570
-003f63 0072 .db "toupper",0
-003f64 3f55 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-003f65 3800 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-003f66 38b0 .dw XT_DUP
-003f67 383c .dw XT_DOLITERAL
-003f68 0061 .dw 'a'
-003f69 383c .dw XT_DOLITERAL
-003f6a 007b .dw 'z'+1
-003f6b 3e56 .dw XT_WITHIN
-003f6c 3835 .dw XT_DOCONDBRANCH
-003f6d 3f71 DEST(PFA_TOUPPER0)
-003f6e 383c .dw XT_DOLITERAL
-003f6f 00df .dw 223 ; inverse of 0x20: 0xdf
-003f70 3a12 .dw XT_AND
- PFA_TOUPPER0:
-003f71 381f .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-003f72 ff07 .dw $ff07
-003f73 6f74
-003f74 6f6c
-003f75 6577
-003f76 0072 .db "tolower",0
-003f77 3f5f .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-003f78 3800 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-003f79 38b0 .dw XT_DUP
-003f7a 383c .dw XT_DOLITERAL
-003f7b 0041 .dw 'A'
-003f7c 383c .dw XT_DOLITERAL
-003f7d 005b .dw 'Z'+1
-003f7e 3e56 .dw XT_WITHIN
-003f7f 3835 .dw XT_DOCONDBRANCH
-003f80 3f84 DEST(PFA_TOLOWER0)
-003f81 383c .dw XT_DOLITERAL
-003f82 0020 .dw 32
-003f83 3a1b .dw XT_OR
- PFA_TOLOWER0:
-003f84 381f .dw XT_EXIT
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-003f85 ff06 .dw $ff06
-003f86 733f
-003f87 6174
-003f88 6b63 .db "?stack"
-003f89 3f72 .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-003f8a 3800 .dw DO_COLON
- PFA_QSTACK:
- .endif
-003f8b 05d4 .dw XT_DEPTH
-003f8c 3920 .dw XT_ZEROLESS
-003f8d 3835 .dw XT_DOCONDBRANCH
-003f8e 3f92 DEST(PFA_QSTACK1)
-003f8f 383c .dw XT_DOLITERAL
-003f90 fffc .dw -4
-003f91 3d85 .dw XT_THROW
- PFA_QSTACK1:
-003f92 381f .dw XT_EXIT
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-003f93 ff06 .dw $ff06
-003f94 6f62
-003f95 6e75
-003f96 7364 .db "bounds"
-003f97 3f85 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-003f98 3800 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-003f99 38ce .dw XT_OVER
-003f9a 399c .dw XT_PLUS
-003f9b 38c3 .dw XT_SWAP
-003f9c 381f .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-003f9d ff02 .dw 0xff02
-003f9e 7263 .db "cr"
-003f9f 3f93 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-003fa0 3800 .dw DO_COLON
- PFA_CR:
- .endif
-
-003fa1 383c .dw XT_DOLITERAL
-003fa2 000d .dw 13
-003fa3 3ef1 .dw XT_EMIT
-003fa4 383c .dw XT_DOLITERAL
-003fa5 000a .dw 10
-003fa6 3ef1 .dw XT_EMIT
-003fa7 381f .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-003fa8 ff05 .dw $ff05
-003fa9 7073
-003faa 6361
-003fab 0065 .db "space",0
-003fac 3f9d .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-003fad 3800 .dw DO_COLON
- PFA_SPACE:
- .endif
-003fae 3f53 .dw XT_BL
-003faf 3ef1 .dw XT_EMIT
-003fb0 381f .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-003fb1 ff06 .dw $ff06
-003fb2 7073
-003fb3 6361
-003fb4 7365 .db "spaces"
-003fb5 3fa8 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-003fb6 3800 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-003fb7 3953
-003fb8 3e49 .DW XT_ZERO, XT_MAX
-003fb9 38b0
-003fba 3835 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-003fbb 3fc0 DEST(SPCS2)
-003fbc 3fad
-003fbd 3a34
-003fbe 382e .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-003fbf 3fb9 DEST(SPCS1)
-003fc0 38d8
-003fc1 381f SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-003fc2 ff03 .dw $ff03
-003fc3 3e73
-003fc4 0064 .db "s>d",0
-003fc5 3fb1 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-003fc6 3800 .dw DO_COLON
- PFA_S2D:
- .endif
-003fc7 38b0 .dw XT_DUP
-003fc8 3920 .dw XT_ZEROLESS
-003fc9 381f .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-003fca ff05 .dw $ff05
-003fcb 623e
-003fcc 646f
-003fcd 0079 .db ">body",0
-003fce 3fc2 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-003fcf 3a2f .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-003fd0 0008 .dw $0008
-003fd1 6c32
-003fd2 7469
-003fd3 7265
-003fd4 6c61 .db "2literal"
-003fd5 3fca .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-003fd6 3800 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-003fd7 38c3 .dw XT_SWAP
-003fd8 0764 .dw XT_LITERAL
-003fd9 0764 .dw XT_LITERAL
-003fda 381f .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-003fdb ff01 .dw $ff01
-003fdc 003d .db "=",0
-003fdd 3fd0 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-003fde 3800 .dw DO_COLON
- PFA_EQUAL:
-003fdf 3992 .dw XT_MINUS
-003fe0 3919 .dw XT_ZEROEQUAL
-003fe1 381f .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-003fe2 ff01 .dw $ff01
-003fe3 0031 .db "1",0
-003fe4 3fdb .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-003fe5 3847 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-003fe6 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-003fe7 ff01 .dw $ff01
-003fe8 0032 .db "2",0
-003fe9 3fe2 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-003fea 3847 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-003feb 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-003fec ff02 .dw $ff02
-003fed 312d .db "-1"
-003fee 3fe7 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-003fef 3847 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-003ff0 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000056 ff ff
- ; some configs
-000058 a1 0a CFG_DP: .dw DPSTART ; Dictionary Pointer
-00005a d3 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00005c b0 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00005e b5 09 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-000060 7e 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000062 b0 0a CFG_LP0: .dw stackstart+1
-000064 93 0a CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000066 e6 02 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000068 6a 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-00006a ec 3f CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00006c 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00006e 6a 00 .dw CFG_FORTHWORDLIST ; get/set-order
-000070 .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00007e 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-000080 57 06 .dw XT_REC_FIND
-000082 43 06 .dw XT_REC_NUM
-000084 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-000088 7d 3b .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-00008a 8a 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00008c 00 00 .dw 0 ; USER_STATE
-00008e 00 00 .dw 0 ; USER_FOLLOWER
-000090 ff 0a .dw rstackstart ; USER_RP
-000092 af 0a .dw stackstart ; USER_SP0
-000094 af 0a .dw stackstart ; USER_SP
-
-000096 00 00 .dw 0 ; USER_HANDLER
-000098 0a 00 .dw 10 ; USER_BASE
-
-00009a c5 00 .dw XT_TX ; USER_EMIT
-00009c d3 00 .dw XT_TXQ ; USER_EMITQ
-00009e 9a 00 .dw XT_RX ; USER_KEY
-0000a0 b5 00 .dw XT_RXQ ; USER_KEYQ
-0000a2 5e 02 .dw XT_SOURCETIB ; USER_SOURCE
-0000a4 00 00 .dw 0 ; USER_G_IN
-0000a6 4b 02 .dw XT_REFILLTIB ; USER_REFILL
-0000a8 c8 3c .dw XT_DEFAULT_PROMPTOK
-0000aa e7 3c .dw XT_DEFAULT_PROMPTERROR
-0000ac d7 3c .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-0000ae 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega32U4" register use summary:
-r0 : 25 r1 : 5 r2 : 9 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 78 r17: 57 r18: 52 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 187 r25: 133 r26: 28 r27: 17 r28: 7 r29: 4 r30: 78 r31: 40
-x : 4 y : 203 z : 41
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega32U4" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 2 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 13 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 0 cbr : 0
-clc : 1 clh : 0 cli : 5 cln : 0 clr : 13 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 14 inc : 3 jmp : 7
-ld : 136 ldd : 4 ldi : 27 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 15 movw : 65 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 1 out : 16 pop : 45
-push : 39 rcall : 55 ret : 6 reti : 1 rjmp : 103 rol : 23
-ror : 5 sbc : 9 sbci : 3 sbi : 3 sbic : 3 sbis : 0
-sbiw : 7 sbr : 0 sbrc : 4 sbrs : 3 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 3 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 74 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 70 out of 113 (61.9%)
-
-"ATmega32U4" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x007fe2 1868 11624 13492 32768 41.2%
-[.dseg] 0x000100 0x0001d3 0 211 211 2560 8.2%
-[.eseg] 0x000000 0x0000b0 0 176 176 1024 17.2%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/arduino/leonardo.map b/amforth-6.5/appl/arduino/leonardo.map
deleted file mode 100644
index 621045c..0000000
--- a/amforth-6.5/appl/arduino/leonardo.map
+++ /dev/null
@@ -1,2333 +0,0 @@
-
-AVRASM ver. 2.1.52 leonardo.asm Sun Apr 30 20:10:13 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000095
-EQU SIGNATURE_002 00000087
-EQU PLLCSR 00000029
-EQU PLLFRQ 00000032
-EQU UEINT 000000f4
-EQU UEBCHX 000000f3
-EQU UEBCLX 000000f2
-EQU UEDATX 000000f1
-EQU UEIENX 000000f0
-EQU UESTA1X 000000ef
-EQU UESTA0X 000000ee
-EQU UECFG1X 000000ed
-EQU UECFG0X 000000ec
-EQU UECONX 000000eb
-EQU UERST 000000ea
-EQU UENUM 000000e9
-EQU UEINTX 000000e8
-EQU UDMFN 000000e6
-EQU UDFNUMH 000000e5
-EQU UDFNUML 000000e4
-EQU UDADDR 000000e3
-EQU UDIEN 000000e2
-EQU UDINT 000000e1
-EQU UDCON 000000e0
-EQU USBINT 000000da
-EQU USBSTA 000000d9
-EQU USBCON 000000d8
-EQU UHWCON 000000d7
-EQU UDR1 000000ce
-EQU UBRR1L 000000cc
-EQU UBRR1H 000000cd
-EQU UCSR1C 000000ca
-EQU UCSR1B 000000c9
-EQU UCSR1A 000000c8
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU OCR3CL 0000009c
-EQU OCR3CH 0000009d
-EQU OCR3BL 0000009a
-EQU OCR3BH 0000009b
-EQU OCR3AL 00000098
-EQU OCR3AH 00000099
-EQU ICR3L 00000096
-EQU ICR3H 00000097
-EQU TCNT3L 00000094
-EQU TCNT3H 00000095
-EQU TCCR3C 00000092
-EQU TCCR3B 00000091
-EQU TCCR3A 00000090
-EQU OCR1CL 0000008c
-EQU OCR1CH 0000008d
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU DIDR2 0000007d
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU TIMSK4 00000072
-EQU TIMSK3 00000071
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK0 0000006b
-EQU EICRB 0000006a
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU RCCTRL 00000067
-EQU PRR1 00000065
-EQU PRR0 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU EIND 0000003c
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU OCDR 00000031
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR4 00000019
-EQU TIFR3 00000018
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTF 00000011
-EQU DDRF 00000010
-EQU PINF 0000000f
-EQU PORTE 0000000e
-EQU DDRE 0000000d
-EQU PINE 0000000c
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU DT4 000000d4
-EQU OCR4D 000000d2
-EQU OCR4C 000000d1
-EQU OCR4B 000000d0
-EQU OCR4A 000000cf
-EQU TCCR4E 000000c4
-EQU TCCR4D 000000c3
-EQU TCCR4C 000000c2
-EQU TCCR4B 000000c1
-EQU TCCR4A 000000c0
-EQU TC4H 000000bf
-EQU TCNT4 000000be
-EQU CLKSEL1 000000c6
-EQU CLKSEL0 000000c5
-EQU CLKSTA 000000c7
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU UDR1_0 00000000
-EQU UDR1_1 00000001
-EQU UDR1_2 00000002
-EQU UDR1_3 00000003
-EQU UDR1_4 00000004
-EQU UDR1_5 00000005
-EQU UDR1_6 00000006
-EQU UDR1_7 00000007
-EQU MPCM1 00000000
-EQU U2X1 00000001
-EQU UPE1 00000002
-EQU DOR1 00000003
-EQU FE1 00000004
-EQU UDRE1 00000005
-EQU TXC1 00000006
-EQU RXC1 00000007
-EQU TXB81 00000000
-EQU RXB81 00000001
-EQU UCSZ12 00000002
-EQU TXEN1 00000003
-EQU RXEN1 00000004
-EQU UDRIE1 00000005
-EQU TXCIE1 00000006
-EQU RXCIE1 00000007
-EQU UCPOL1 00000000
-EQU UCSZ10 00000001
-EQU UCPHA1 00000001
-EQU UCSZ11 00000002
-EQU UDORD1 00000002
-EQU USBS1 00000003
-EQU UPM10 00000004
-EQU UPM11 00000005
-EQU UMSEL10 00000006
-EQU UMSEL11 00000007
-EQU UBRR_8 00000000
-EQU UBRR_9 00000001
-EQU UBRR_10 00000002
-EQU UBRR_11 00000003
-EQU UBRR_0 00000000
-EQU UBRR_1 00000001
-EQU UBRR_2 00000002
-EQU UBRR_3 00000003
-EQU UBRR_4 00000004
-EQU UBRR_5 00000005
-EQU UBRR_6 00000006
-EQU UBRR_7 00000007
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU SIGRD 00000005
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEAR10 00000002
-EQU EEAR11 00000003
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSRSYNC 00000000
-EQU PSR10 00000000
-EQU TSM 00000007
-EQU TOIE3 00000000
-EQU OCIE3A 00000001
-EQU OCIE3B 00000002
-EQU OCIE3C 00000003
-EQU ICIE3 00000005
-EQU TOV3 00000000
-EQU OCF3A 00000001
-EQU OCF3B 00000002
-EQU OCF3C 00000003
-EQU ICF3 00000005
-EQU WGM30 00000000
-EQU WGM31 00000001
-EQU COM3C0 00000002
-EQU COM3C1 00000003
-EQU COM3B0 00000004
-EQU COM3B1 00000005
-EQU COM3A0 00000006
-EQU COM3A1 00000007
-EQU CS30 00000000
-EQU CS31 00000001
-EQU CS32 00000002
-EQU WGM32 00000003
-EQU WGM33 00000004
-EQU ICES3 00000006
-EQU ICNC3 00000007
-EQU FOC3C 00000005
-EQU FOC3B 00000006
-EQU FOC3A 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU OCIE1C 00000003
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU OCF1C 00000003
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU WGM11 00000001
-EQU COM1C0 00000002
-EQU COM1C1 00000003
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1C 00000005
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU JTD 00000007
-EQU JTRF 00000004
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC20 00000004
-EQU ISC21 00000005
-EQU ISC30 00000006
-EQU ISC31 00000007
-EQU ISC40 00000000
-EQU ISC41 00000001
-EQU ISC50 00000002
-EQU ISC51 00000003
-EQU ISC60 00000004
-EQU ISC61 00000005
-EQU ISC70 00000006
-EQU ISC71 00000007
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INT2 00000002
-EQU INT3 00000003
-EQU INT4 00000004
-EQU INT5 00000005
-EQU INT6 00000006
-EQU INT7 00000007
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU INTF2 00000002
-EQU INTF3 00000003
-EQU INTF4 00000004
-EQU INTF5 00000005
-EQU INTF6 00000006
-EQU INTF7 00000007
-EQU PCIE0 00000000
-EQU PCIF0 00000000
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU DT4L0 00000000
-EQU DT4L1 00000001
-EQU DT4L2 00000002
-EQU DT4L3 00000003
-EQU DT4L4 00000004
-EQU DT4L5 00000005
-EQU DT4L6 00000006
-EQU DT4L7 00000007
-EQU TOV4 00000002
-EQU OCF4B 00000005
-EQU OCF4A 00000006
-EQU OCF4D 00000007
-EQU TOIE4 00000002
-EQU OCIE4B 00000005
-EQU OCIE4A 00000006
-EQU OCIE4D 00000007
-EQU OCR4D0 00000000
-EQU OCR4D1 00000001
-EQU OCR4D2 00000002
-EQU OCR4D3 00000003
-EQU OCR4D4 00000004
-EQU OCR4D5 00000005
-EQU OCR4D6 00000006
-EQU OCR4D7 00000007
-EQU OCR4C0 00000000
-EQU OCR4C1 00000001
-EQU OCR4C2 00000002
-EQU OCR4C3 00000003
-EQU OCR4C4 00000004
-EQU OCR4C5 00000005
-EQU OCR4C6 00000006
-EQU OCR4C7 00000007
-EQU OCR4B0 00000000
-EQU OCR4B1 00000001
-EQU OCR4B2 00000002
-EQU OCR4B3 00000003
-EQU OCR4B4 00000004
-EQU OCR4B5 00000005
-EQU OCR4B6 00000006
-EQU OCR4B7 00000007
-EQU OCR4A0 00000000
-EQU OCR4A1 00000001
-EQU OCR4A2 00000002
-EQU OCR4A3 00000003
-EQU OCR4A4 00000004
-EQU OCR4A5 00000005
-EQU OCR4A6 00000006
-EQU OCR4A7 00000007
-EQU TC48 00000000
-EQU TC49 00000001
-EQU TC410 00000002
-EQU TC40 00000000
-EQU TC41 00000001
-EQU TC42 00000002
-EQU TC43 00000003
-EQU TC44 00000004
-EQU TC45 00000005
-EQU TC46 00000006
-EQU TC47 00000007
-EQU OC4OE0 00000000
-EQU OC4OE1 00000001
-EQU OC4OE2 00000002
-EQU OC4OE3 00000003
-EQU OC4OE4 00000004
-EQU OC4OE5 00000005
-EQU ENHC4 00000006
-EQU TLOCK4 00000007
-EQU WGM40 00000000
-EQU WGM41 00000001
-EQU FPF4 00000002
-EQU FPAC4 00000003
-EQU FPES4 00000004
-EQU FPNC4 00000005
-EQU FPEN4 00000006
-EQU FPIE4 00000007
-EQU PWM4D 00000000
-EQU FOC4D 00000001
-EQU COM4D0 00000002
-EQU COM4D1 00000003
-EQU COM4B0S 00000004
-EQU COM4B1S 00000005
-EQU COM4A0S 00000006
-EQU COM4A1S 00000007
-EQU CS40 00000000
-EQU CS41 00000001
-EQU CS42 00000002
-EQU CS43 00000003
-EQU DTPS40 00000004
-EQU DTPS41 00000005
-EQU PSR4 00000006
-EQU PWM4X 00000007
-EQU PWM4B 00000000
-EQU PWM4A 00000001
-EQU FOC4B 00000002
-EQU FOC4A 00000003
-EQU COM4B0 00000004
-EQU COM4B1 00000005
-EQU COM4A0 00000006
-EQU COM4A1 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTE2 00000002
-EQU PE2 00000002
-EQU PORTE6 00000006
-EQU PE6 00000006
-EQU DDE2 00000002
-EQU DDE6 00000006
-EQU PINE2 00000002
-EQU PINE6 00000006
-EQU PORTF0 00000000
-EQU PF0 00000000
-EQU PORTF1 00000001
-EQU PF1 00000001
-EQU PORTF4 00000004
-EQU PF4 00000004
-EQU PORTF5 00000005
-EQU PF5 00000005
-EQU PORTF6 00000006
-EQU PF6 00000006
-EQU PORTF7 00000007
-EQU PF7 00000007
-EQU DDF0 00000000
-EQU DDF1 00000001
-EQU DDF4 00000004
-EQU DDF5 00000005
-EQU DDF6 00000006
-EQU DDF7 00000007
-EQU PINF0 00000000
-EQU PINF1 00000001
-EQU PINF4 00000004
-EQU PINF5 00000005
-EQU PINF6 00000006
-EQU PINF7 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ADTS3 00000004
-EQU MUX5 00000005
-EQU ADHSM 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ADC6D 00000006
-EQU ADC7D 00000007
-EQU ADC8D 00000000
-EQU ADC9D 00000001
-EQU ADC10D 00000002
-EQU ADC11D 00000003
-EQU ADC12D 00000004
-EQU ADC13D 00000005
-EQU ACME 00000006
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU RCFREQ 00000000
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU EIND0 00000000
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRUSART1 00000000
-EQU PRTIM3 00000003
-EQU PRUSB 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU EXTON 00000000
-EQU RCON 00000001
-EQU CLKS 00000000
-EQU EXTE 00000002
-EQU RCE 00000003
-EQU EXSUT0 00000004
-EQU EXSUT1 00000005
-EQU RCSUT0 00000006
-EQU RCSUT1 00000007
-EQU EXCKSEL0 00000000
-EQU EXCKSEL1 00000001
-EQU EXCKSEL2 00000002
-EQU EXCKSEL3 00000003
-EQU RCCKSEL0 00000004
-EQU RCCKSEL1 00000005
-EQU RCCKSEL2 00000006
-EQU RCCKSEL3 00000007
-EQU PLOCK 00000000
-EQU PLLE 00000001
-EQU PINDIV 00000004
-EQU PDIV0 00000000
-EQU PDIV1 00000001
-EQU PDIV2 00000002
-EQU PDIV3 00000003
-EQU PLLTM0 00000004
-EQU PLLTM1 00000005
-EQU PLLUSB 00000006
-EQU PINMUX 00000007
-EQU VBUSTE 00000000
-EQU OTGPADE 00000004
-EQU FRZCLK 00000005
-EQU USBE 00000007
-EQU DETACH 00000000
-EQU RMWKUP 00000001
-EQU LSM 00000002
-EQU RSTCPU 00000003
-EQU SUSPI 00000000
-EQU SOFI 00000002
-EQU EORSTI 00000003
-EQU WAKEUPI 00000004
-EQU EORSMI 00000005
-EQU UPRSMI 00000006
-EQU SUSPE 00000000
-EQU SOFE 00000002
-EQU EORSTE 00000003
-EQU WAKEUPE 00000004
-EQU EORSME 00000005
-EQU UPRSME 00000006
-EQU UADD0 00000000
-EQU UADD1 00000001
-EQU UADD2 00000002
-EQU UADD3 00000003
-EQU UADD4 00000004
-EQU UADD5 00000005
-EQU UADD6 00000006
-EQU ADDEN 00000007
-EQU FNUM0 00000000
-EQU FNUM1 00000001
-EQU FNUM2 00000002
-EQU FNUM3 00000003
-EQU FNUM4 00000004
-EQU FNUM5 00000005
-EQU FNUM6 00000006
-EQU FNUM7 00000007
-EQU FNUM8 00000000
-EQU FNUM9 00000001
-EQU FNUM10 00000002
-EQU FNCERR 00000004
-EQU TXINI 00000000
-EQU STALLEDI 00000001
-EQU RXOUTI 00000002
-EQU RXSTPI 00000003
-EQU NAKOUTI 00000004
-EQU RWAL 00000005
-EQU NAKINI 00000006
-EQU FIFOCON 00000007
-EQU UENUM_0 00000000
-EQU UENUM_1 00000001
-EQU UENUM_2 00000002
-EQU EPRST0 00000000
-EQU EPRST1 00000001
-EQU EPRST2 00000002
-EQU EPRST3 00000003
-EQU EPRST4 00000004
-EQU EPRST5 00000005
-EQU EPRST6 00000006
-EQU EPEN 00000000
-EQU RSTDT 00000003
-EQU STALLRQC 00000004
-EQU STALLRQ 00000005
-EQU EPDIR 00000000
-EQU EPTYPE0 00000006
-EQU EPTYPE1 00000007
-EQU ALLOC 00000001
-EQU EPBK0 00000002
-EQU EPBK1 00000003
-EQU EPSIZE0 00000004
-EQU EPSIZE1 00000005
-EQU EPSIZE2 00000006
-EQU NBUSYBK0 00000000
-EQU NBUSYBK1 00000001
-EQU DTSEQ0 00000002
-EQU DTSEQ1 00000003
-EQU UNDERFI 00000005
-EQU OVERFI 00000006
-EQU CFGOK 00000007
-EQU CURRBK0 00000000
-EQU CURRBK1 00000001
-EQU CTRLDIR 00000002
-EQU TXINE 00000000
-EQU STALLEDE 00000001
-EQU RXOUTE 00000002
-EQU RXSTPE 00000003
-EQU NAKOUTE 00000004
-EQU NAKINE 00000006
-EQU FLERRE 00000007
-EQU DAT0 00000000
-EQU DAT1 00000001
-EQU DAT2 00000002
-EQU DAT3 00000003
-EQU DAT4 00000004
-EQU DAT5 00000005
-EQU DAT6 00000006
-EQU DAT7 00000007
-EQU BYCT0 00000000
-EQU BYCT1 00000001
-EQU BYCT2 00000002
-EQU BYCT3 00000003
-EQU BYCT4 00000004
-EQU BYCT5 00000005
-EQU BYCT6 00000006
-EQU BYCT7 00000007
-EQU EPINT0 00000000
-EQU EPINT1 00000001
-EQU EPINT2 00000002
-EQU EPINT3 00000003
-EQU EPINT4 00000004
-EQU EPINT5 00000005
-EQU EPINT6 00000006
-EQU VBUSTI 00000000
-EQU VBUS 00000000
-EQU SPEED 00000003
-EQU UVREGE 00000000
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWGCE 00000000
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-EQU HWBE 00000003
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00003fff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00000a00
-EQU RAMEND 00000aff
-EQU XRAMEND 00000000
-EQU E2END 000003ff
-EQU EEPROMEND 000003ff
-EQU EEADRBITS 0000000a
-EQU NRWW_START_ADDR 00003800
-EQU NRWW_STOP_ADDR 00003fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 000037ff
-EQU PAGESIZE 00000040
-EQU FIRSTBOOTSTART 00003f00
-EQU SECONDBOOTSTART 00003e00
-EQU THIRDBOOTSTART 00003c00
-EQU FOURTHBOOTSTART 00003800
-EQU SMALLBOOTSTART 00003f00
-EQU LARGEBOOTSTART 00003800
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU INT3addr 00000008
-EQU Reserved1addr 0000000a
-EQU Reserved2addr 0000000c
-EQU INT6addr 0000000e
-EQU Reserved3addr 00000010
-EQU PCI0addr 00000012
-EQU USB_GENaddr 00000014
-EQU USB_COMaddr 00000016
-EQU WDTaddr 00000018
-EQU Reserved4addr 0000001a
-EQU Reserved5addr 0000001c
-EQU Reserved6addr 0000001e
-EQU ICP1addr 00000020
-EQU OC1Aaddr 00000022
-EQU OC1Baddr 00000024
-EQU OC1Caddr 00000026
-EQU OVF1addr 00000028
-EQU OC0Aaddr 0000002a
-EQU OC0Baddr 0000002c
-EQU OVF0addr 0000002e
-EQU SPIaddr 00000030
-EQU URXC1addr 00000032
-EQU UDRE1addr 00000034
-EQU UTXC1addr 00000036
-EQU ACIaddr 00000038
-EQU ADCCaddr 0000003a
-EQU ERDYaddr 0000003c
-EQU ICP3addr 0000003e
-EQU OC3Aaddr 00000040
-EQU OC3Baddr 00000042
-EQU OC3Caddr 00000044
-EQU OVF3addr 00000046
-EQU TWIaddr 00000048
-EQU SPMRaddr 0000004a
-EQU OC4Aaddr 0000004c
-EQU OC4Baddr 0000004e
-EQU OC4Daddr 00000050
-EQU OVF4addr 00000052
-EQU TIMER4_FPFaddr 00000054
-EQU INT_VECTORS_SIZE 00000056
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_WATCHDOG 00000000
-SET WANT_PORTD 00000000
-SET WANT_SPI 00000000
-SET WANT_USART1 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_EEPROM 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_3 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_JTAG 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_TIMER_COUNTER_4 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTE 00000000
-SET WANT_PORTF 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_CPU 00000000
-SET WANT_PLL 00000000
-SET WANT_USB_DEVICE 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 000000ff
-EQU INTVECTORS 0000002b
-CSEG mcu_info 00000055
-CSEG mcu_ramsize 00000055
-CSEG mcu_eepromsize 00000056
-CSEG mcu_maxdp 00000057
-CSEG mcu_numints 00000058
-CSEG mcu_name 00000059
-SET codestart 0000005f
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000001
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 00000aff
-SET stackstart 00000aaf
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000000a
-SET VE_HEAD 00003fec
-SET VE_ENVHEAD 000002e6
-SET AMFORTH_RO_SEG 00003800
-EQU F_CPU 00f42400
-EQU BAUDRATE_LOW 000000cc
-EQU BAUDRATE_HIGH 000000cd
-EQU USART_C 000000ca
-EQU USART_B 000000c9
-EQU USART_A 000000c8
-EQU USART_DATA 000000ce
-EQU URXCaddr 00000032
-EQU UDREaddr 00000034
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 0000005f
-CSEG XT_TO_RXBUF 00000065
-CSEG PFA_rx_tobuf 00000066
-CSEG DO_NEXT 00003804
-CSEG VE_ISR_RX 00000076
-CSEG XT_ISR_RX 0000007b
-CSEG DO_COLON 00003800
-CSEG usart_rx_isr 0000007c
-CSEG XT_DOLITERAL 0000383c
-CSEG XT_CFETCH 00003897
-CSEG XT_DUP 000038b0
-CSEG XT_EQUAL 00003fde
-CSEG XT_DOCONDBRANCH 00003835
-CSEG usart_rx_isr1 00000086
-CSEG XT_COLD 00003d37
-CSEG XT_EXIT 0000381f
-CSEG XT_USART_INIT_RX_BUFFER 00000088
-CSEG PFA_USART_INIT_RX_BUFFER 00000089
-CSEG XT_INTSTORE 00003ca4
-CSEG XT_ZERO 00003953
-CSEG XT_FILL 00003e97
-CSEG VE_RX_BUFFER 00000095
-CSEG XT_RX_BUFFER 0000009a
-CSEG PFA_RX_BUFFER 0000009b
-CSEG XT_RXQ_BUFFER 000000b5
-CSEG XT_PLUS 0000399c
-CSEG XT_SWAP 000038c3
-CSEG XT_1PLUS 00003a2e
-CSEG XT_AND 00003a12
-CSEG XT_CSTORE 0000388c
-CSEG VE_RXQ_BUFFER 000000af
-CSEG PFA_RXQ_BUFFER 000000b6
-CSEG XT_PAUSE 00003d2f
-CSEG XT_NOTEQUAL 00003912
-SET XT_RX 0000009a
-SET XT_RXQ 000000b5
-SET XT_USART_INIT_RX 00000088
-CSEG VE_TX_POLL 000000bf
-CSEG XT_TX_POLL 000000c5
-CSEG PFA_TX_POLL 000000c6
-CSEG XT_TXQ_POLL 000000d3
-CSEG VE_TXQ_POLL 000000cd
-CSEG PFA_TXQ_POLL 000000d4
-SET XT_TX 000000c5
-SET XT_TXQ 000000d3
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000dc
-CSEG XT_UBRR 000000e0
-CSEG PFA_DOVALUE1 0000386e
-CSEG PFA_UBRR 000000e1
-ESEG EE_UBRRVAL 000000ae
-CSEG XT_EDEFERFETCH 00003d9f
-CSEG XT_EDEFERSTORE 00003da9
-CSEG VE_USART 000000e4
-CSEG XT_USART 000000e9
-CSEG PFA_USART 000000ea
-CSEG XT_BYTESWAP 00003af8
-SET AMFORTH_NRWW_SIZE 00000ffe
-SET corepc 000000ff
-CSEG PFA_COLD 00003d38
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 00000116
-CSEG XT_MPLUS 00000119
-CSEG PFA_MPLUS 0000011a
-CSEG XT_S2D 00003fc6
-CSEG XT_DPLUS 00003c14
-CSEG VE_UDSTAR 0000011d
-CSEG XT_UDSTAR 00000121
-CSEG PFA_UDSTAR 00000122
-CSEG XT_TO_R 000038fe
-CSEG XT_UMSTAR 000039df
-CSEG XT_DROP 000038d8
-CSEG XT_R_FROM 000038f5
-CSEG XT_ROT 000038e0
-CSEG VE_UMAX 0000012c
-CSEG XT_UMAX 00000130
-CSEG PFA_UMAX 00000131
-CSEG XT_2DUP 00003ec8
-CSEG XT_ULESS 0000395b
-CSEG UMAX1 00000136
-CSEG VE_UMIN 00000138
-CSEG XT_UMIN 0000013c
-CSEG PFA_UMIN 0000013d
-CSEG XT_UGREATER 00003966
-CSEG UMIN1 00000142
-CSEG XT_IMMEDIATEQ 00000144
-CSEG PFA_IMMEDIATEQ 00000145
-CSEG XT_ZEROEQUAL 00003919
-CSEG IMMEDIATEQ1 0000014d
-CSEG XT_ONE 00003fe5
-CSEG XT_TRUE 0000394a
-CSEG VE_NAME2FLAGS 0000014f
-CSEG XT_NAME2FLAGS 00000156
-CSEG PFA_NAME2FLAGS 00000157
-CSEG XT_FETCHI 00003bca
-CSEG VE_DOT_VER 0000015c
-CSEG XT_DOT_VER 00000160
-CSEG PFA_DOT_VER 00000161
-CSEG XT_ENV_FORTHNAME 000002c1
-CSEG XT_ITYPE 000003ea
-CSEG XT_SPACE 00003fad
-CSEG XT_BASE 00003ebc
-CSEG XT_FETCH 00003878
-CSEG XT_ENV_FORTHVERSION 000002cf
-CSEG XT_DECIMAL 00003f40
-CSEG XT_L_SHARP 00000308
-CSEG XT_SHARP 00000310
-CSEG XT_HOLD 000002f9
-CSEG XT_SHARP_S 00000326
-CSEG XT_SHARP_G 00000331
-CSEG XT_TYPE 00000420
-CSEG XT_STORE 00003880
-CSEG XT_ENV_CPU 000002d7
-CSEG VE_NOOP 00000177
-CSEG XT_NOOP 0000017b
-CSEG PFA_NOOP 0000017c
-CSEG VE_UNUSED 0000017d
-CSEG XT_UNUSED 00000182
-CSEG PFA_UNUSED 00000183
-CSEG XT_SP_FETCH 00003a8c
-CSEG XT_HERE 00003f22
-CSEG XT_MINUS 00003992
-CSEG VE_TO 00000187
-CSEG XT_TO 0000018a
-CSEG PFA_TO 0000018b
-CSEG XT_TICK 0000042f
-CSEG XT_TO_BODY 00003fcf
-CSEG XT_STATE 00003eb6
-CSEG PFA_TO1 0000019b
-CSEG XT_COMPILE 00000743
-CSEG XT_DOTO 00000195
-CSEG XT_COMMA 0000074e
-CSEG PFA_DOTO 00000196
-CSEG XT_ICELLPLUS 000001a7
-CSEG XT_EXECUTE 00003829
-CSEG VE_ICELLPLUS 000001a1
-CSEG PFA_ICELLPLUS 000001a8
-CSEG VE_ICOMPARE 000001aa
-CSEG XT_ICOMPARE 000001b0
-CSEG PFA_ICOMPARE 000001b1
-CSEG XT_OVER 000038ce
-CSEG PFA_ICOMPARE_SAMELEN 000001bb
-CSEG XT_2DROP 00003ed1
-CSEG XT_QDOCHECK 0000080d
-CSEG PFA_ICOMPARE_DONE 000001e0
-CSEG XT_DODO 00003a9a
-CSEG PFA_ICOMPARE_LOOP 000001c1
-CSEG XT_ICOMPARE_LC 000001e3
-CSEG PFA_ICOMPARE_LASTCELL 000001d1
-CSEG PFA_ICOMPARE_NEXTLOOP 000001d8
-CSEG XT_UNLOOP 00003ad3
-CSEG XT_CELLPLUS 00003c8f
-CSEG XT_DOPLUSLOOP 00003ab9
-CSEG PFA_ICOMPARE_LC 000001e4
-CSEG XT_TOLOWER 00003f78
-CSEG XT_OR 00003a1b
-CSEG VE_STAR 000001f2
-CSEG XT_STAR 000001f5
-CSEG PFA_STAR 000001f6
-CSEG XT_MSTAR 000039a5
-CSEG VE_J 000001f9
-CSEG XT_J 000001fc
-CSEG PFA_J 000001fd
-CSEG XT_RP_FETCH 00003a75
-CSEG VE_DABS 00000209
-CSEG XT_DABS 0000020d
-CSEG PFA_DABS 0000020e
-CSEG XT_ZEROLESS 00003920
-CSEG PFA_DABS1 00000213
-CSEG XT_DNEGATE 0000021a
-CSEG VE_DNEGATE 00000214
-CSEG PFA_DNEGATE 0000021b
-CSEG XT_DINVERT 00003c3a
-CSEG VE_CMOVE 00000220
-CSEG XT_CMOVE 00000225
-CSEG PFA_CMOVE 00000226
-CSEG PFA_CMOVE1 00000233
-CSEG PFA_CMOVE2 0000022f
-CSEG VE_2SWAP 00000239
-CSEG XT_2SWAP 0000023e
-CSEG PFA_2SWAP 0000023f
-CSEG VE_REFILLTIB 00000244
-CSEG XT_REFILLTIB 0000024b
-CSEG PFA_REFILLTIB 0000024c
-CSEG XT_TIB 00000267
-CSEG XT_ACCEPT 0000047f
-CSEG XT_NUMBERTIB 0000026d
-CSEG XT_TO_IN 00003ee1
-CSEG VE_SOURCETIB 00000257
-CSEG XT_SOURCETIB 0000025e
-CSEG PFA_SOURCETIB 0000025f
-CSEG VE_TIB 00000263
-CSEG PFA_DOVARIABLE 00003847
-CSEG PFA_TIB 00000268
-DSEG ram_tib 0000013d
-CSEG VE_NUMBERTIB 00000269
-CSEG PFA_NUMBERTIB 0000026e
-DSEG ram_sharptib 00000197
-CSEG VE_EE2RAM 0000026f
-CSEG XT_EE2RAM 00000274
-CSEG PFA_EE2RAM 00000275
-CSEG PFA_EE2RAM_1 00000277
-CSEG XT_FETCHE 00003b5e
-CSEG XT_DOLOOP 00003ac8
-CSEG PFA_EE2RAM_2 00000281
-CSEG VE_INIT_RAM 00000283
-CSEG XT_INIT_RAM 00000289
-CSEG PFA_INI_RAM 0000028a
-ESEG EE_INITUSER 0000008c
-CSEG XT_UP_FETCH 00003b01
-CSEG XT_2SLASH 00003a03
-CSEG VE_ENVIRONMENT 00000292
-CSEG XT_ENVIRONMENT 0000029a
-CSEG PFA_ENVIRONMENT 0000029b
-ESEG CFG_ENVIRONMENT 00000066
-CSEG VE_ENVWORDLISTS 0000029c
-CSEG XT_ENVWORDLISTS 000002a3
-CSEG PFA_ENVWORDLISTS 000002a4
-CSEG VE_ENVSLASHPAD 000002a7
-CSEG XT_ENVSLASHPAD 000002ab
-CSEG PFA_ENVSLASHPAD 000002ac
-CSEG XT_PAD 00003ee7
-CSEG VE_ENVSLASHHOLD 000002b0
-CSEG XT_ENVSLASHHOLD 000002b5
-CSEG PFA_ENVSLASHHOLD 000002b6
-CSEG VE_ENV_FORTHNAME 000002ba
-CSEG PFA_EN_FORTHNAME 000002c2
-CSEG XT_DOSLITERAL 000003b7
-CSEG VE_ENV_FORTHVERSION 000002c9
-CSEG PFA_EN_FORTHVERSION 000002d0
-CSEG VE_ENV_CPU 000002d3
-CSEG PFA_EN_CPU 000002d8
-CSEG XT_ICOUNT 00000416
-CSEG VE_ENV_MCUINFO 000002dc
-CSEG XT_ENV_MCUINFO 000002e2
-CSEG PFA_EN_MCUINFO 000002e3
-CSEG VE_ENVUSERSIZE 000002e6
-CSEG XT_ENVUSERSIZE 000002eb
-CSEG PFA_ENVUSERSIZE 000002ec
-CSEG VE_HLD 000002ef
-CSEG XT_HLD 000002f3
-CSEG PFA_HLD 000002f4
-DSEG ram_hld 00000199
-CSEG VE_HOLD 000002f5
-CSEG PFA_HOLD 000002fa
-CSEG XT_1MINUS 00003a34
-CSEG VE_L_SHARP 00000305
-CSEG PFA_L_SHARP 00000309
-CSEG VE_SHARP 0000030d
-CSEG PFA_SHARP 00000311
-CSEG XT_UDSLASHMOD 0000038d
-CSEG XT_LESS 0000396d
-CSEG PFA_SHARP1 0000031e
-CSEG VE_SHARP_S 00000323
-CSEG PFA_SHARP_S 00000327
-CSEG NUMS1 00000327
-CSEG VE_SHARP_G 0000032e
-CSEG PFA_SHARP_G 00000332
-CSEG VE_SIGN 00000339
-CSEG XT_SIGN 0000033d
-CSEG PFA_SIGN 0000033e
-CSEG PFA_SIGN1 00000344
-CSEG VE_DDOTR 00000345
-CSEG XT_DDOTR 00000349
-CSEG PFA_DDOTR 0000034a
-CSEG XT_TUCK 00003ed9
-CSEG XT_SPACES 00003fb6
-CSEG VE_DOTR 00000358
-CSEG XT_DOTR 0000035b
-CSEG PFA_DOTR 0000035c
-CSEG VE_DDOT 00000361
-CSEG XT_DDOT 00000364
-CSEG PFA_DDOT 00000365
-CSEG VE_DOT 00000369
-CSEG XT_DOT 0000036c
-CSEG PFA_DOT 0000036d
-CSEG VE_UDDOT 00000370
-CSEG XT_UDDOT 00000374
-CSEG PFA_UDDOT 00000375
-CSEG XT_UDDOTR 0000037d
-CSEG VE_UDDOTR 00000379
-CSEG PFA_UDDOTR 0000037e
-CSEG VE_UDSLASHMOD 00000388
-CSEG PFA_UDSLASHMOD 0000038e
-CSEG XT_R_FETCH 00003907
-CSEG XT_UMSLASHMOD 000039c1
-CSEG VE_DIGITQ 00000398
-CSEG XT_DIGITQ 0000039d
-CSEG PFA_DIGITQ 0000039e
-CSEG XT_TOUPPER 00003f65
-CSEG XT_GREATER 00003977
-CSEG PFA_DOSLITERAL 000003b8
-CSEG VE_SCOMMA 000003c2
-CSEG XT_SCOMMA 000003c5
-CSEG PFA_SCOMMA 000003c6
-CSEG XT_DOSCOMMA 000003c9
-CSEG PFA_DOSCOMMA 000003ca
-CSEG XT_2STAR 00003a0a
-CSEG PFA_SCOMMA2 000003dc
-CSEG PFA_SCOMMA1 000003d6
-CSEG XT_GREATERZERO 00003927
-CSEG PFA_SCOMMA3 000003e3
-CSEG VE_ITYPE 000003e5
-CSEG PFA_ITYPE 000003eb
-CSEG PFA_ITYPE2 000003fe
-CSEG PFA_ITYPE1 000003f6
-CSEG XT_LOWEMIT 0000040b
-CSEG XT_HIEMIT 00000407
-CSEG PFA_ITYPE3 00000405
-CSEG PFA_HIEMIT 00000408
-CSEG PFA_LOWEMIT 0000040c
-CSEG XT_EMIT 00003ef1
-CSEG VE_ICOUNT 00000411
-CSEG PFA_ICOUNT 00000417
-CSEG VE_TYPE 0000041c
-CSEG PFA_TYPE 00000421
-CSEG XT_BOUNDS 00003f98
-CSEG PFA_TYPE2 0000042b
-CSEG PFA_TYPE1 00000426
-CSEG XT_I 00003aab
-CSEG VE_TICK 0000042c
-CSEG PFA_TICK 00000430
-CSEG XT_PARSENAME 000005a2
-CSEG XT_FORTHRECOGNIZER 000005e5
-CSEG XT_RECOGNIZE 000005f0
-CSEG XT_DT_NULL 0000067d
-CSEG PFA_TICK1 00000441
-CSEG XT_THROW 00003d85
-CSEG VE_CSKIP 00000443
-CSEG XT_CSKIP 00000448
-CSEG PFA_CSKIP 00000449
-CSEG PFA_CSKIP1 0000044a
-CSEG PFA_CSKIP2 00000457
-CSEG XT_SLASHSTRING 00000593
-CSEG XT_DOBRANCH 0000382e
-CSEG VE_CSCAN 0000045a
-CSEG XT_CSCAN 0000045f
-CSEG PFA_CSCAN 00000460
-CSEG PFA_CSCAN1 00000462
-CSEG PFA_CSCAN2 00000474
-CSEG XT_NIP 000038ef
-CSEG VE_ACCEPT 0000047a
-CSEG PFA_ACCEPT 00000480
-CSEG ACC1 00000484
-CSEG XT_KEY 00003f02
-CSEG XT_CRLFQ 000004c0
-CSEG ACC5 000004b2
-CSEG ACC3 000004a2
-CSEG ACC6 000004a0
-CSEG XT_BS 000004b8
-CSEG ACC4 000004b0
-CSEG XT_BL 00003f53
-CSEG PFA_ACCEPT6 000004a9
-CSEG XT_CR 00003fa0
-CSEG VE_REFILL 000004cb
-CSEG XT_REFILL 000004d0
-CSEG PFA_DODEFER1 00003dfe
-CSEG PFA_REFILL 000004d1
-CSEG XT_UDEFERFETCH 00003dc7
-CSEG XT_UDEFERSTORE 00003dd3
-CSEG VE_CHAR 000004d4
-CSEG XT_CHAR 000004d8
-CSEG PFA_CHAR 000004d9
-CSEG VE_NUMBER 000004dd
-CSEG XT_NUMBER 000004e2
-CSEG PFA_NUMBER 000004e3
-CSEG XT_QSIGN 00000526
-CSEG XT_SET_BASE 00000539
-CSEG PFA_NUMBER0 000004f9
-CSEG XT_2TO_R 00003b1d
-CSEG XT_2R_FROM 00003b2c
-CSEG XT_TO_NUMBER 00000557
-CSEG XT_QDUP 000038b8
-CSEG PFA_NUMBER1 0000051b
-CSEG PFA_NUMBER2 00000512
-CSEG PFA_NUMBER6 00000513
-CSEG PFA_NUMBER3 0000050f
-CSEG XT_TWO 00003fea
-CSEG PFA_NUMBER5 00000521
-CSEG PFA_NUMBER4 00000520
-CSEG XT_NEGATE 00003e26
-CSEG PFA_QSIGN 00000527
-CSEG PFA_NUMBERSIGN_DONE 00000532
-CSEG XT_BASES 00000534
-CSEG PFA_DOCONSTANT 00003851
-CSEG PFA_SET_BASE 0000053a
-CSEG XT_WITHIN 00003e56
-CSEG SET_BASE1 0000054f
-CSEG SET_BASE2 00000550
-CSEG VE_TO_NUMBER 00000551
-CSEG TONUM1 00000558
-CSEG TONUM3 0000056f
-CSEG TONUM2 00000563
-CSEG VE_PARSE 00000570
-CSEG XT_PARSE 00000575
-CSEG PFA_PARSE 00000576
-CSEG XT_SOURCE 00000589
-CSEG XT_PLUSSTORE 00003a64
-CSEG VE_SOURCE 00000584
-CSEG PFA_SOURCE 0000058a
-CSEG VE_SLASHSTRING 0000058d
-CSEG PFA_SLASHSTRING 00000594
-CSEG VE_PARSENAME 0000059b
-CSEG PFA_PARSENAME 000005a3
-CSEG XT_SKIPSCANCHAR 000005a6
-CSEG PFA_SKIPSCANCHAR 000005a7
-CSEG VE_SP0 000005b8
-CSEG XT_SP0 000005bc
-CSEG PFA_SP0 000005bd
-CSEG VE_SP 000005c0
-CSEG XT_SP 000005c3
-CSEG PFA_DOUSER 00003857
-CSEG PFA_SP 000005c4
-CSEG VE_RP0 000005c5
-CSEG XT_RP0 000005c9
-CSEG PFA_RP0 000005ca
-CSEG XT_DORP0 000005cd
-CSEG PFA_DORP0 000005ce
-CSEG VE_DEPTH 000005cf
-CSEG XT_DEPTH 000005d4
-CSEG PFA_DEPTH 000005d5
-CSEG VE_FORTHRECOGNIZER 000005db
-CSEG PFA_FORTHRECOGNIZER 000005e6
-ESEG CFG_FORTHRECOGNIZER 00000060
-CSEG VE_RECOGNIZE 000005e9
-CSEG PFA_RECOGNIZE 000005f1
-CSEG XT_RECOGNIZE_A 000005fb
-CSEG XT_MAPSTACK 0000098e
-CSEG PFA_RECOGNIZE1 000005fa
-CSEG PFA_RECOGNIZE_A 000005fc
-CSEG PFA_RECOGNIZE_A1 0000060c
-CSEG VE_INTERPRET 00000610
-CSEG XT_INTERPRET 00000617
-CSEG PFA_INTERPRET 00000618
-CSEG PFA_INTERPRET2 00000628
-CSEG PFA_INTERPRET1 00000623
-CSEG XT_QSTACK 00003f8a
-CSEG VE_DT_NUM 0000062a
-CSEG XT_DT_NUM 0000062f
-CSEG PFA_DT_NUM 00000630
-CSEG XT_LITERAL 00000764
-CSEG VE_DT_DNUM 00000633
-CSEG XT_DT_DNUM 00000639
-CSEG PFA_DT_DNUM 0000063a
-CSEG XT_2LITERAL 00003fd6
-CSEG VE_REC_NUM 0000063d
-CSEG XT_REC_NUM 00000643
-CSEG PFA_REC_NUM 00000644
-CSEG PFA_REC_NONUMBER 0000064f
-CSEG PFA_REC_INTNUM2 0000064d
-CSEG VE_REC_FIND 00000651
-CSEG XT_REC_FIND 00000657
-CSEG PFA_REC_FIND 00000658
-CSEG XT_FINDXT 000006f2
-CSEG PFA_REC_WORD_FOUND 00000660
-CSEG XT_DT_XT 00000667
-CSEG VE_DT_XT 00000662
-CSEG PFA_DT_XT 00000668
-CSEG XT_R_WORD_INTERPRET 0000066b
-CSEG XT_R_WORD_COMPILE 0000066f
-CSEG PFA_R_WORD_INTERPRET 0000066c
-CSEG PFA_R_WORD_COMPILE 00000670
-CSEG PFA_R_WORD_COMPILE1 00000675
-CSEG VE_DT_NULL 00000677
-CSEG PFA_DT_NULL 0000067e
-CSEG XT_FAIL 00000681
-CSEG PFA_FAIL 00000682
-CSEG VE_SEARCH_WORDLIST 00000685
-CSEG XT_SEARCH_WORDLIST 0000068f
-CSEG PFA_SEARCH_WORDLIST 00000690
-CSEG XT_ISWORD 000006a4
-CSEG XT_TRAVERSEWORDLIST 000006c1
-CSEG PFA_SEARCH_WORDLIST1 0000069e
-CSEG XT_NFA2CFA 000006e8
-CSEG PFA_ISWORD 000006a5
-CSEG XT_NAME2STRING 000006dc
-CSEG PFA_ISWORD3 000006b2
-CSEG VE_TRAVERSEWORDLIST 000006b6
-CSEG PFA_TRAVERSEWORDLIST 000006c2
-CSEG PFA_TRAVERSEWORDLIST1 000006c3
-CSEG PFA_TRAVERSEWORDLIST2 000006d2
-CSEG XT_NFA2LFA 000009fd
-CSEG VE_NAME2STRING 000006d4
-CSEG PFA_NAME2STRING 000006dd
-CSEG VE_NFA2CFA 000006e2
-CSEG PFA_NFA2CFA 000006e9
-CSEG VE_FINDXT 000006ec
-CSEG PFA_FINDXT 000006f3
-CSEG XT_FINDXTA 000006fe
-ESEG CFG_ORDERLISTLEN 0000006c
-CSEG PFA_FINDXT1 000006fd
-CSEG PFA_FINDXTA 000006ff
-CSEG PFA_FINDXTA1 0000070b
-CSEG VE_NEWEST 0000070c
-CSEG XT_NEWEST 00000711
-CSEG PFA_NEWEST 00000712
-DSEG ram_newest 0000019b
-CSEG VE_LATEST 00000713
-CSEG XT_LATEST 00000718
-CSEG PFA_LATEST 00000719
-DSEG ram_latest 0000019f
-CSEG VE_DOCREATE 0000071a
-CSEG XT_DOCREATE 00000720
-CSEG PFA_DOCREATE 00000721
-CSEG XT_WLSCOPE 00000877
-CSEG XT_HEADER 0000085c
-CSEG VE_BACKSLASH 0000072b
-CSEG XT_BACKSLASH 0000072e
-CSEG PFA_BACKSLASH 0000072f
-CSEG VE_LPAREN 00000734
-CSEG XT_LPAREN 00000737
-CSEG PFA_LPAREN 00000738
-CSEG VE_COMPILE 0000073d
-CSEG PFA_COMPILE 00000744
-CSEG VE_COMMA 0000074b
-CSEG PFA_COMMA 0000074f
-CSEG XT_DP 00003f11
-CSEG XT_STOREI 00003b72
-CSEG PFA_DP 00003f12
-CSEG VE_BRACKETTICK 00000756
-CSEG XT_BRACKETTICK 0000075a
-CSEG PFA_BRACKETTICK 0000075b
-CSEG VE_LITERAL 0000075e
-CSEG PFA_LITERAL 00000765
-CSEG VE_SLITERAL 00000769
-CSEG XT_SLITERAL 0000076f
-CSEG PFA_SLITERAL 00000770
-CSEG XT_GMARK 00000774
-CSEG PFA_GMARK 00000775
-CSEG XT_GRESOLVE 00000779
-CSEG PFA_GRESOLVE 0000077a
-CSEG XT_LMARK 0000077f
-CSEG PFA_LMARK 00000780
-CSEG XT_LRESOLVE 00000782
-CSEG PFA_LRESOLVE 00000783
-CSEG VE_AHEAD 00000786
-CSEG XT_AHEAD 0000078b
-CSEG PFA_AHEAD 0000078c
-CSEG VE_IF 00000790
-CSEG XT_IF 00000793
-CSEG PFA_IF 00000794
-CSEG VE_ELSE 00000798
-CSEG XT_ELSE 0000079c
-CSEG PFA_ELSE 0000079d
-CSEG VE_THEN 000007a3
-CSEG XT_THEN 000007a7
-CSEG PFA_THEN 000007a8
-CSEG VE_BEGIN 000007aa
-CSEG XT_BEGIN 000007af
-CSEG PFA_BEGIN 000007b0
-CSEG VE_WHILE 000007b2
-CSEG XT_WHILE 000007b7
-CSEG PFA_WHILE 000007b8
-CSEG VE_REPEAT 000007bb
-CSEG XT_REPEAT 000007c0
-CSEG PFA_REPEAT 000007c1
-CSEG XT_AGAIN 000007d4
-CSEG VE_UNTIL 000007c4
-CSEG XT_UNTIL 000007c9
-CSEG PFA_UNTIL 000007ca
-CSEG VE_AGAIN 000007cf
-CSEG PFA_AGAIN 000007d5
-CSEG VE_DO 000007d9
-CSEG XT_DO 000007dc
-CSEG PFA_DO 000007dd
-CSEG XT_TO_L 00000837
-CSEG VE_LOOP 000007e3
-CSEG XT_LOOP 000007e7
-CSEG PFA_LOOP 000007e8
-CSEG XT_ENDLOOP 0000081e
-CSEG VE_PLUSLOOP 000007ec
-CSEG XT_PLUSLOOP 000007f1
-CSEG PFA_PLUSLOOP 000007f2
-CSEG VE_LEAVE 000007f6
-CSEG XT_LEAVE 000007fb
-CSEG PFA_LEAVE 000007fc
-CSEG VE_QDO 00000801
-CSEG XT_QDO 00000805
-CSEG PFA_QDO 00000806
-CSEG PFA_QDOCHECK 0000080e
-CSEG PFA_QDOCHECK1 00000815
-CSEG XT_INVERT 000039fc
-CSEG VE_ENDLOOP 00000818
-CSEG PFA_ENDLOOP 0000081f
-CSEG LOOP1 00000820
-CSEG XT_L_FROM 0000082b
-CSEG LOOP2 00000827
-CSEG VE_L_FROM 00000828
-CSEG PFA_L_FROM 0000082c
-CSEG XT_LP 0000084a
-CSEG VE_TO_L 00000834
-CSEG PFA_TO_L 00000838
-CSEG VE_LP0 0000083f
-CSEG XT_LP0 00000843
-CSEG PFA_LP0 00000844
-ESEG CFG_LP0 00000062
-CSEG VE_LP 00000847
-CSEG PFA_LP 0000084b
-DSEG ram_lp 000001a1
-CSEG VE_CREATE 0000084c
-CSEG XT_CREATE 00000851
-CSEG PFA_CREATE 00000852
-CSEG XT_REVEAL 00000880
-CSEG VE_HEADER 00000857
-CSEG PFA_HEADER 0000085d
-CSEG PFA_HEADER1 0000086e
-CSEG VE_WLSCOPE 00000871
-CSEG PFA_WLSCOPE 00000878
-ESEG CFG_WLSCOPE 0000005e
-CSEG VE_REVEAL 0000087b
-CSEG PFA_REVEAL 00000881
-CSEG REVEAL1 0000088b
-CSEG XT_STOREE 00003b3a
-CSEG VE_DOES 0000088c
-CSEG XT_DOES 00000891
-CSEG PFA_DOES 00000892
-CSEG XT_DODOES 000008a4
-CSEG DO_DODOES 00000899
-CSEG PFA_DODOES 000008a5
-CSEG VE_COLON 000008ad
-CSEG XT_COLON 000008b0
-CSEG PFA_COLON 000008b1
-CSEG XT_COLONNONAME 000008bb
-CSEG VE_COLONNONAME 000008b5
-CSEG PFA_COLONNONAME 000008bc
-CSEG XT_RBRACKET 000008d0
-CSEG VE_SEMICOLON 000008c4
-CSEG XT_SEMICOLON 000008c7
-CSEG PFA_SEMICOLON 000008c8
-CSEG XT_LBRACKET 000008d8
-CSEG VE_RBRACKET 000008cd
-CSEG PFA_RBRACKET 000008d1
-CSEG VE_LBRACKET 000008d5
-CSEG PFA_LBRACKET 000008d9
-CSEG VE_VARIABLE 000008dd
-CSEG XT_VARIABLE 000008e3
-CSEG PFA_VARIABLE 000008e4
-CSEG XT_CONSTANT 000008ef
-CSEG XT_ALLOT 00003f2b
-CSEG VE_CONSTANT 000008e9
-CSEG PFA_CONSTANT 000008f0
-CSEG VE_USER 000008f6
-CSEG XT_USER 000008fa
-CSEG PFA_USER 000008fb
-CSEG VE_RECURSE 00000901
-CSEG XT_RECURSE 00000907
-CSEG PFA_RECURSE 00000908
-CSEG VE_IMMEDIATE 0000090c
-CSEG XT_IMMEDIATE 00000913
-CSEG PFA_IMMEDIATE 00000914
-CSEG XT_GET_CURRENT 000009b5
-CSEG VE_BRACKETCHAR 0000091e
-CSEG XT_BRACKETCHAR 00000923
-CSEG PFA_BRACKETCHAR 00000924
-CSEG VE_ABORTQUOTE 00000929
-CSEG XT_ABORTQUOTE 0000092e
-CSEG PFA_ABORTQUOTE 0000092f
-CSEG XT_SQUOTE 00003e89
-CSEG XT_QABORT 00000940
-CSEG VE_ABORT 00000933
-CSEG XT_ABORT 00000938
-CSEG PFA_ABORT 00000939
-CSEG VE_QABORT 0000093b
-CSEG PFA_QABORT 00000941
-CSEG QABO1 00000946
-CSEG VE_GET_STACK 00000948
-CSEG XT_GET_STACK 0000094f
-CSEG PFA_N_FETCH_E2 00000966
-CSEG PFA_N_FETCH_E1 0000095c
-CSEG XT_CELLS 00003ec3
-CSEG VE_SET_STACK 00000969
-CSEG XT_SET_STACK 00000970
-CSEG PFA_SET_STACK 00000971
-CSEG PFA_SET_STACK0 00000978
-CSEG PFA_SET_STACK2 00000985
-CSEG PFA_SET_STACK1 00000980
-CSEG VE_MAPSTACK 00000987
-CSEG PFA_MAPSTACK 0000098f
-CSEG PFA_MAPSTACK3 000009aa
-CSEG PFA_MAPSTACK1 00000999
-CSEG PFA_MAPSTACK2 000009a6
-CSEG VE_GET_CURRENT 000009ad
-CSEG PFA_GET_CURRENT 000009b6
-ESEG CFG_CURRENT 00000068
-CSEG VE_GET_ORDER 000009ba
-CSEG XT_GET_ORDER 000009c1
-CSEG PFA_GET_ORDER 000009c2
-CSEG VE_CFG_ORDER 000009c6
-CSEG XT_CFG_ORDER 000009cd
-CSEG PFA_CFG_ORDER 000009ce
-CSEG VE_COMPARE 000009cf
-CSEG XT_COMPARE 000009d5
-CSEG PFA_COMPARE 000009d6
-CSEG PFA_COMPARE_LOOP 000009e2
-CSEG PFA_COMPARE_NOTEQUAL 000009f0
-CSEG PFA_COMPARE_ENDREACHED2 000009eb
-CSEG PFA_COMPARE_ENDREACHED 000009ec
-CSEG PFA_COMPARE_CHECKLASTCHAR 000009f0
-CSEG PFA_COMPARE_DONE 000009f2
-CSEG VE_NFA2LFA 000009f7
-CSEG PFA_NFA2LFA 000009fe
-CSEG VE_SET_CURRENT 00000a03
-CSEG XT_SET_CURRENT 00000a0b
-CSEG PFA_SET_CURRENT 00000a0c
-CSEG VE_WORDLIST 00000a10
-CSEG XT_WORDLIST 00000a16
-CSEG PFA_WORDLIST 00000a17
-CSEG XT_EHERE 00003f1a
-CSEG PFA_EHERE 00003f1b
-CSEG VE_FORTHWORDLIST 00000a20
-CSEG XT_FORTHWORDLIST 00000a29
-CSEG PFA_FORTHWORDLIST 00000a2a
-ESEG CFG_FORTHWORDLIST 0000006a
-CSEG VE_SET_ORDER 00000a2b
-CSEG XT_SET_ORDER 00000a32
-CSEG PFA_SET_ORDER 00000a33
-CSEG VE_SET_RECOGNIZERS 00000a37
-CSEG XT_SET_RECOGNIZERS 00000a41
-CSEG PFA_SET_RECOGNIZERS 00000a42
-ESEG CFG_RECOGNIZERLISTLEN 0000007e
-CSEG VE_GET_RECOGNIZERS 00000a46
-CSEG XT_GET_RECOGNIZERS 00000a50
-CSEG PFA_GET_RECOGNIZERS 00000a51
-CSEG VE_CODE 00000a55
-CSEG XT_CODE 00000a59
-CSEG PFA_CODE 00000a5a
-CSEG VE_ENDCODE 00000a60
-CSEG XT_ENDCODE 00000a66
-CSEG PFA_ENDCODE 00000a67
-CSEG VE_MARKER 00000a6c
-CSEG XT_MARKER 00000a72
-CSEG PFA_MARKER 00000a73
-ESEG EE_MARKER 0000008a
-CSEG VE_POSTPONE 00000a76
-CSEG XT_POSTPONE 00000a7c
-CSEG PFA_POSTPONE 00000a7d
-CSEG VE_APPLTURNKEY 00000a8b
-CSEG XT_APPLTURNKEY 00000a93
-CSEG PFA_APPLTURNKEY 00000a94
-CSEG XT_INTON 00003c96
-SET DPSTART 00000aa1
-CSEG DO_INTERRUPT 00003813
-CSEG DO_EXECUTE 0000380c
-CSEG XT_ISREXEC 00003cbf
-CSEG VE_EXIT 0000381b
-CSEG PFA_EXIT 00003820
-CSEG VE_EXECUTE 00003823
-CSEG PFA_EXECUTE 0000382a
-CSEG PFA_DOBRANCH 0000382f
-CSEG PFA_DOCONDBRANCH 00003836
-CSEG PFA_DOLITERAL 0000383d
-CSEG XT_DOVARIABLE 00003846
-CSEG XT_DOCONSTANT 00003850
-CSEG XT_DOUSER 00003856
-CSEG VE_DOVALUE 00003862
-CSEG XT_DOVALUE 00003868
-CSEG PFA_DOVALUE 00003869
-CSEG VE_FETCH 00003875
-CSEG PFA_FETCH 00003879
-CSEG PFA_FETCHRAM 00003879
-CSEG VE_STORE 0000387d
-CSEG PFA_STORE 00003881
-CSEG PFA_STORERAM 00003881
-CSEG VE_CSTORE 00003889
-CSEG PFA_CSTORE 0000388d
-CSEG VE_CFETCH 00003894
-CSEG PFA_CFETCH 00003898
-CSEG VE_FETCHU 0000389c
-CSEG XT_FETCHU 0000389f
-CSEG PFA_FETCHU 000038a0
-CSEG VE_STOREU 000038a4
-CSEG XT_STOREU 000038a7
-CSEG PFA_STOREU 000038a8
-CSEG VE_DUP 000038ac
-CSEG PFA_DUP 000038b1
-CSEG VE_QDUP 000038b4
-CSEG PFA_QDUP 000038b9
-CSEG PFA_QDUP1 000038be
-CSEG VE_SWAP 000038bf
-CSEG PFA_SWAP 000038c4
-CSEG VE_OVER 000038ca
-CSEG PFA_OVER 000038cf
-CSEG VE_DROP 000038d4
-CSEG PFA_DROP 000038d9
-CSEG VE_ROT 000038dc
-CSEG PFA_ROT 000038e1
-CSEG VE_NIP 000038eb
-CSEG PFA_NIP 000038f0
-CSEG VE_R_FROM 000038f2
-CSEG PFA_R_FROM 000038f6
-CSEG VE_TO_R 000038fb
-CSEG PFA_TO_R 000038ff
-CSEG VE_R_FETCH 00003904
-CSEG PFA_R_FETCH 00003908
-CSEG VE_NOTEQUAL 0000390f
-CSEG PFA_NOTEQUAL 00003913
-CSEG VE_ZEROEQUAL 00003916
-CSEG PFA_ZEROEQUAL 0000391a
-CSEG PFA_ZERO1 00003956
-CSEG PFA_TRUE1 0000394d
-CSEG VE_ZEROLESS 0000391d
-CSEG PFA_ZEROLESS 00003921
-CSEG VE_GREATERZERO 00003924
-CSEG PFA_GREATERZERO 00003928
-CSEG VE_DGREATERZERO 0000392d
-CSEG XT_DGREATERZERO 00003931
-CSEG PFA_DGREATERZERO 00003932
-CSEG VE_DXT_ZEROLESS 0000393b
-CSEG XT_DXT_ZEROLESS 0000393f
-CSEG PFA_DXT_ZEROLESS 00003940
-CSEG VE_TRUE 00003946
-CSEG PFA_TRUE 0000394b
-CSEG VE_ZERO 00003950
-CSEG PFA_ZERO 00003954
-CSEG VE_ULESS 00003958
-CSEG PFA_ULESS 0000395c
-CSEG VE_UGREATER 00003963
-CSEG PFA_UGREATER 00003967
-CSEG VE_LESS 0000396a
-CSEG PFA_LESS 0000396e
-CSEG PFA_LESSDONE 00003972
-CSEG VE_GREATER 00003974
-CSEG PFA_GREATER 00003978
-CSEG PFA_GREATERDONE 0000397c
-CSEG VE_LOG2 0000397f
-CSEG XT_LOG2 00003983
-CSEG PFA_LOG2 00003984
-CSEG PFA_LOG2_1 00003987
-CSEG PFA_LOG2_2 0000398d
-CSEG VE_MINUS 0000398f
-CSEG PFA_MINUS 00003993
-CSEG VE_PLUS 00003999
-CSEG PFA_PLUS 0000399d
-CSEG VE_MSTAR 000039a2
-CSEG PFA_MSTAR 000039a6
-CSEG VE_UMSLASHMOD 000039bc
-CSEG PFA_UMSLASHMOD 000039c2
-CSEG PFA_UMSLASHMODmod 000039c7
-CSEG PFA_UMSLASHMODmod_loop 000039c8
-CSEG PFA_UMSLASHMODmod_loop_control 000039d5
-CSEG PFA_UMSLASHMODmod_subtract 000039d2
-CSEG PFA_UMSLASHMODmod_done 000039d7
-CSEG VE_UMSTAR 000039db
-CSEG PFA_UMSTAR 000039e0
-CSEG VE_INVERT 000039f7
-CSEG PFA_INVERT 000039fd
-CSEG VE_2SLASH 00003a00
-CSEG PFA_2SLASH 00003a04
-CSEG VE_2STAR 00003a07
-CSEG PFA_2STAR 00003a0b
-CSEG VE_AND 00003a0e
-CSEG PFA_AND 00003a13
-CSEG VE_OR 00003a18
-CSEG PFA_OR 00003a1c
-CSEG VE_XOR 00003a21
-CSEG XT_XOR 00003a25
-CSEG PFA_XOR 00003a26
-CSEG VE_1PLUS 00003a2b
-CSEG PFA_1PLUS 00003a2f
-CSEG VE_1MINUS 00003a31
-CSEG PFA_1MINUS 00003a35
-CSEG VE_QNEGATE 00003a37
-CSEG XT_QNEGATE 00003a3d
-CSEG PFA_QNEGATE 00003a3e
-CSEG QNEG1 00003a42
-CSEG VE_LSHIFT 00003a43
-CSEG XT_LSHIFT 00003a48
-CSEG PFA_LSHIFT 00003a49
-CSEG PFA_LSHIFT1 00003a4c
-CSEG PFA_LSHIFT2 00003a51
-CSEG VE_RSHIFT 00003a52
-CSEG XT_RSHIFT 00003a57
-CSEG PFA_RSHIFT 00003a58
-CSEG PFA_RSHIFT1 00003a5b
-CSEG PFA_RSHIFT2 00003a60
-CSEG VE_PLUSSTORE 00003a61
-CSEG PFA_PLUSSTORE 00003a65
-CSEG VE_RP_FETCH 00003a71
-CSEG PFA_RP_FETCH 00003a76
-CSEG VE_RP_STORE 00003a7b
-CSEG XT_RP_STORE 00003a7f
-CSEG PFA_RP_STORE 00003a80
-CSEG VE_SP_FETCH 00003a88
-CSEG PFA_SP_FETCH 00003a8d
-CSEG VE_SP_STORE 00003a91
-CSEG XT_SP_STORE 00003a95
-CSEG PFA_SP_STORE 00003a96
-CSEG PFA_DODO 00003a9b
-CSEG PFA_DODO1 00003a9d
-CSEG VE_I 00003aa8
-CSEG PFA_I 00003aac
-CSEG PFA_DOPLUSLOOP 00003aba
-CSEG PFA_DOPLUSLOOP_LEAVE 00003ac4
-CSEG PFA_DOPLUSLOOP_NEXT 00003ac1
-CSEG PFA_DOLOOP 00003ac9
-CSEG VE_UNLOOP 00003ace
-CSEG PFA_UNLOOP 00003ad4
-CSEG VE_CMOVE_G 00003ad9
-CSEG XT_CMOVE_G 00003ade
-CSEG PFA_CMOVE_G 00003adf
-CSEG PFA_CMOVE_G1 00003af0
-CSEG PFA_CMOVE_G2 00003aec
-CSEG VE_BYTESWAP 00003af5
-CSEG PFA_BYTESWAP 00003af9
-CSEG VE_UP_FETCH 00003afd
-CSEG PFA_UP_FETCH 00003b02
-CSEG VE_UP_STORE 00003b06
-CSEG XT_UP_STORE 00003b0a
-CSEG PFA_UP_STORE 00003b0b
-CSEG VE_1MS 00003b0f
-CSEG XT_1MS 00003b13
-CSEG PFA_1MS 00003b14
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_2TO_R 00003b19
-CSEG PFA_2TO_R 00003b1e
-CSEG VE_2R_FROM 00003b28
-CSEG PFA_2R_FROM 00003b2d
-CSEG VE_STOREE 00003b37
-CSEG PFA_STOREE 00003b3b
-CSEG PFA_STOREE0 00003b3b
-CSEG PFA_FETCHE2 00003b69
-CSEG PFA_STOREE3 00003b45
-CSEG PFA_STOREE1 00003b50
-CSEG PFA_STOREE4 00003b4c
-CSEG PFA_STOREE2 00003b52
-CSEG VE_FETCHE 00003b5b
-CSEG PFA_FETCHE 00003b5f
-CSEG PFA_FETCHE1 00003b5f
-CSEG VE_STOREI 00003b6f
-CSEG PFA_STOREI 00003b73
-ESEG EE_STOREI 00000088
-CSEG VE_DO_STOREI_NRWW 00003b76
-CSEG XT_DO_STOREI 00003b7d
-CSEG PFA_DO_STOREI_NRWW 00003b7e
-CSEG DO_STOREI_atmega 00003b92
-CSEG pageload 00003ba3
-CSEG DO_STOREI_writepage 00003b9c
-CSEG dospm 00003bbc
-EQU pagemask ffffffc0
-CSEG pageload_loop 00003ba9
-CSEG pageload_newdata 00003bb4
-CSEG pageload_cont 00003bb6
-CSEG pageload_done 00003bbb
-CSEG dospm_wait_ee 00003bbc
-CSEG dospm_wait_spm 00003bbe
-CSEG VE_FETCHI 00003bc7
-CSEG PFA_FETCHI 00003bcb
-CSEG VE_N_TO_R 00003bd1
-CSEG XT_N_TO_R 00003bd5
-CSEG PFA_N_TO_R 00003bd6
-CSEG PFA_N_TO_R1 00003bd8
-CSEG VE_N_R_FROM 00003be3
-CSEG XT_N_R_FROM 00003be7
-CSEG PFA_N_R_FROM 00003be8
-CSEG PFA_N_R_FROM1 00003bed
-CSEG VE_D2STAR 00003bf5
-CSEG XT_D2STAR 00003bf9
-CSEG PFA_D2STAR 00003bfa
-CSEG VE_D2SLASH 00003c03
-CSEG XT_D2SLASH 00003c07
-CSEG PFA_D2SLASH 00003c08
-CSEG VE_DPLUS 00003c11
-CSEG PFA_DPLUS 00003c15
-CSEG VE_DMINUS 00003c22
-CSEG XT_DMINUS 00003c25
-CSEG PFA_DMINUS 00003c26
-CSEG VE_DINVERT 00003c34
-CSEG PFA_DINVERT 00003c3b
-CSEG VE_SLASHMOD 00003c44
-CSEG XT_SLASHMOD 00003c48
-CSEG PFA_SLASHMOD 00003c49
-CSEG PFA_SLASHMOD_1 00003c54
-CSEG PFA_SLASHMOD_2 00003c5a
-CSEG PFA_SLASHMOD_3 00003c5d
-CSEG PFA_SLASHMOD_5 00003c68
-CSEG PFA_SLASHMOD_4 00003c67
-CSEG PFA_SLASHMODmod_done 00003c73
-CSEG PFA_SLASHMOD_6 00003c71
-CSEG VE_ABS 00003c77
-CSEG XT_ABS 00003c7b
-CSEG PFA_ABS 00003c7c
-CSEG VE_PICK 00003c7f
-CSEG XT_PICK 00003c83
-CSEG PFA_PICK 00003c84
-CSEG VE_CELLPLUS 00003c8a
-CSEG PFA_CELLPLUS 00003c90
-CSEG VE_INTON 00003c92
-CSEG PFA_INTON 00003c97
-CSEG VE_INTOFF 00003c99
-CSEG XT_INTOFF 00003c9d
-CSEG PFA_INTOFF 00003c9e
-CSEG VE_INTSTORE 00003ca0
-CSEG PFA_INTSTORE 00003ca5
-CSEG VE_INTFETCH 00003caa
-CSEG XT_INTFETCH 00003cae
-CSEG PFA_INTFETCH 00003caf
-CSEG VE_INTTRAP 00003cb4
-CSEG XT_INTTRAP 00003cba
-CSEG PFA_INTTRAP 00003cbb
-CSEG PFA_ISREXEC 00003cc0
-CSEG XT_ISREND 00003cc4
-CSEG PFA_ISREND 00003cc5
-CSEG PFA_ISREND1 00003cc7
-CSEG XT_DEFAULT_PROMPTOK 00003cc8
-CSEG PFA_DEFAULT_PROMPTOK 00003cc9
-CSEG VE_PROMPTOK 00003ccf
-CSEG XT_PROMPTOK 00003cd3
-CSEG PFA_PROMPTOK 00003cd4
-CSEG XT_DEFAULT_PROMPTREADY 00003cd7
-CSEG PFA_DEFAULT_PROMPTREADY 00003cd8
-CSEG VE_PROMPTREADY 00003cde
-CSEG XT_PROMPTREADY 00003ce3
-CSEG PFA_PROMPTREADY 00003ce4
-CSEG XT_DEFAULT_PROMPTERROR 00003ce7
-CSEG PFA_DEFAULT_PROMPTERROR 00003ce8
-CSEG VE_PROMPTERROR 00003cf9
-CSEG XT_PROMPTERROR 00003cfe
-CSEG PFA_PROMPTERROR 00003cff
-CSEG VE_QUIT 00003d02
-CSEG XT_QUIT 00003d06
-CSEG PFA_QUIT 00003d07
-CSEG PFA_QUIT2 00003d0f
-CSEG PFA_QUIT4 00003d15
-CSEG PFA_QUIT3 00003d27
-CSEG XT_CATCH 00003d6f
-CSEG PFA_QUIT5 00003d25
-CSEG VE_PAUSE 00003d2a
-CSEG PFA_PAUSE 00003d30
-DSEG ram_pause 000001a3
-CSEG XT_RDEFERFETCH 00003db3
-CSEG XT_RDEFERSTORE 00003dbd
-CSEG VE_COLD 00003d33
-CSEG clearloop 00003d3f
-DSEG ram_user1 000001a5
-CSEG PFA_WARM 00003d59
-CSEG VE_WARM 00003d54
-CSEG XT_WARM 00003d58
-CSEG XT_DEFERSTORE 00003dde
-CSEG XT_TURNKEY 00003f5b
-CSEG VE_HANDLER 00003d62
-CSEG XT_HANDLER 00003d68
-CSEG PFA_HANDLER 00003d69
-CSEG VE_CATCH 00003d6a
-CSEG PFA_CATCH 00003d70
-CSEG VE_THROW 00003d80
-CSEG PFA_THROW 00003d86
-CSEG PFA_THROW1 00003d8c
-CSEG VE_EDEFERFETCH 00003d99
-CSEG PFA_EDEFERFETCH 00003da0
-CSEG VE_EDEFERSTORE 00003da3
-CSEG PFA_EDEFERSTORE 00003daa
-CSEG VE_RDEFERFETCH 00003dad
-CSEG PFA_RDEFERFETCH 00003db4
-CSEG VE_RDEFERSTORE 00003db7
-CSEG PFA_RDEFERSTORE 00003dbe
-CSEG VE_UDEFERFETCH 00003dc1
-CSEG PFA_UDEFERFETCH 00003dc8
-CSEG VE_UDEFERSTORE 00003dcd
-CSEG PFA_UDEFERSTORE 00003dd4
-CSEG VE_DEFERSTORE 00003dd9
-CSEG PFA_DEFERSTORE 00003ddf
-CSEG VE_DEFERFETCH 00003de6
-CSEG XT_DEFERFETCH 00003deb
-CSEG PFA_DEFERFETCH 00003dec
-CSEG VE_DODEFER 00003df2
-CSEG XT_DODEFER 00003df8
-CSEG PFA_DODEFER 00003df9
-CSEG VE_UDOT 00003e06
-CSEG XT_UDOT 00003e09
-CSEG PFA_UDOT 00003e0a
-CSEG VE_UDOTR 00003e0d
-CSEG XT_UDOTR 00003e11
-CSEG PFA_UDOTR 00003e12
-CSEG VE_USLASHMOD 00003e16
-CSEG XT_USLASHMOD 00003e1b
-CSEG PFA_USLASHMOD 00003e1c
-CSEG VE_NEGATE 00003e21
-CSEG PFA_NEGATE 00003e27
-CSEG VE_SLASH 00003e2a
-CSEG XT_SLASH 00003e2d
-CSEG PFA_SLASH 00003e2e
-CSEG VE_MOD 00003e31
-CSEG XT_MOD 00003e35
-CSEG PFA_MOD 00003e36
-CSEG VE_MIN 00003e39
-CSEG XT_MIN 00003e3d
-CSEG PFA_MIN 00003e3e
-CSEG PFA_MIN1 00003e43
-CSEG VE_MAX 00003e45
-CSEG XT_MAX 00003e49
-CSEG PFA_MAX 00003e4a
-CSEG PFA_MAX1 00003e4f
-CSEG VE_WITHIN 00003e51
-CSEG PFA_WITHIN 00003e57
-CSEG VE_SHOWWORDLIST 00003e5e
-CSEG XT_SHOWWORDLIST 00003e67
-CSEG PFA_SHOWWORDLIST 00003e68
-CSEG XT_SHOWWORD 00003e6d
-CSEG PFA_SHOWWORD 00003e6e
-CSEG VE_WORDS 00003e73
-CSEG XT_WORDS 00003e78
-CSEG PFA_WORDS 00003e79
-CSEG VE_DOTSTRING 00003e7e
-CSEG XT_DOTSTRING 00003e81
-CSEG PFA_DOTSTRING 00003e82
-CSEG VE_SQUOTE 00003e86
-CSEG PFA_SQUOTE 00003e8a
-CSEG PFA_SQUOTE1 00003e92
-CSEG VE_FILL 00003e93
-CSEG PFA_FILL 00003e98
-CSEG PFA_FILL2 00003ea4
-CSEG PFA_FILL1 00003e9f
-CSEG VE_F_CPU 00003ea6
-CSEG XT_F_CPU 00003eab
-CSEG PFA_F_CPU 00003eac
-CSEG VE_STATE 00003eb1
-CSEG PFA_STATE 00003eb7
-DSEG ram_state 000001d1
-CSEG VE_BASE 00003eb8
-CSEG PFA_BASE 00003ebd
-CSEG VE_CELLS 00003ebe
-CSEG VE_2DUP 00003ec4
-CSEG PFA_2DUP 00003ec9
-CSEG VE_2DROP 00003ecc
-CSEG PFA_2DROP 00003ed2
-CSEG VE_TUCK 00003ed5
-CSEG PFA_TUCK 00003eda
-CSEG VE_TO_IN 00003edd
-CSEG PFA_TO_IN 00003ee2
-CSEG VE_PAD 00003ee3
-CSEG PFA_PAD 00003ee8
-CSEG VE_EMIT 00003eed
-CSEG PFA_EMIT 00003ef2
-CSEG VE_EMITQ 00003ef5
-CSEG XT_EMITQ 00003efa
-CSEG PFA_EMITQ 00003efb
-CSEG VE_KEY 00003efe
-CSEG PFA_KEY 00003f03
-CSEG VE_KEYQ 00003f06
-CSEG XT_KEYQ 00003f0a
-CSEG PFA_KEYQ 00003f0b
-CSEG VE_DP 00003f0e
-ESEG CFG_DP 00000058
-CSEG VE_EHERE 00003f15
-ESEG EE_EHERE 0000005c
-CSEG VE_HERE 00003f1e
-CSEG PFA_HERE 00003f23
-ESEG EE_HERE 0000005a
-CSEG VE_ALLOT 00003f26
-CSEG PFA_ALLOT 00003f2c
-CSEG VE_BIN 00003f31
-CSEG XT_BIN 00003f35
-CSEG PFA_BIN 00003f36
-CSEG VE_DECIMAL 00003f3a
-CSEG PFA_DECIMAL 00003f41
-CSEG VE_HEX 00003f46
-CSEG XT_HEX 00003f4a
-CSEG PFA_HEX 00003f4b
-CSEG VE_BL 00003f50
-CSEG PFA_BL 00003f54
-CSEG VE_TURNKEY 00003f55
-CSEG PFA_TURNKEY 00003f5c
-ESEG CFG_TURNKEY 00000064
-CSEG VE_TOUPPER 00003f5f
-CSEG PFA_TOUPPER 00003f66
-CSEG PFA_TOUPPER0 00003f71
-CSEG VE_TOLOWER 00003f72
-CSEG PFA_TOLOWER 00003f79
-CSEG PFA_TOLOWER0 00003f84
-CSEG VE_QSTACK 00003f85
-CSEG PFA_QSTACK 00003f8b
-CSEG PFA_QSTACK1 00003f92
-CSEG VE_BOUNDS 00003f93
-CSEG PFA_BOUNDS 00003f99
-CSEG VE_CR 00003f9d
-CSEG PFA_CR 00003fa1
-CSEG VE_SPACE 00003fa8
-CSEG PFA_SPACE 00003fae
-CSEG VE_SPACES 00003fb1
-CSEG PFA_SPACES 00003fb7
-CSEG SPCS1 00003fb9
-CSEG SPCS2 00003fc0
-CSEG VE_S2D 00003fc2
-CSEG PFA_S2D 00003fc7
-CSEG VE_TO_BODY 00003fca
-CSEG VE_2LITERAL 00003fd0
-CSEG PFA_2LITERAL 00003fd7
-CSEG VE_EQUAL 00003fdb
-CSEG PFA_EQUAL 00003fdf
-CSEG VE_ONE 00003fe2
-CSEG PFA_ONE 00003fe6
-CSEG VE_TWO 00003fe7
-CSEG PFA_TWO 00003feb
-CSEG VE_MINUSONE 00003fec
-CSEG XT_MINUSONE 00003fef
-CSEG PFA_MINUSONE 00003ff0
-SET flashlast 00003ff1
-DSEG HERESTART 000001d3
-ESEG EHERESTART 000000b0
-ESEG CFG_ORDERLIST 0000006e
-ESEG CFG_RECOGNIZERLIST 00000080
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/arduino/mega128.asm b/amforth-6.5/appl/arduino/mega128.asm
deleted file mode 100644
index 4b8dc0e..0000000
--- a/amforth-6.5/appl/arduino/mega128.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; for a description, what can be done in this
-; file see ../template/template.asm. You may want to
-; copy that file to this one and edit it afterwards.
-
-.include "preamble.inc"
-
-.set WANT_IGNORECASE = 1
-
-.equ F_CPU = 16000000
-.include "drivers/usart_0.asm"
-
-; settings for 1wire interface, if desired
-.equ OW_PORT=PORTE
-.EQU OW_BIT=4
-.include "drivers/1wire.asm"
-
-; include the whole source tree.
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/arduino/mega128.eep.hex b/amforth-6.5/appl/arduino/mega128.eep.hex
deleted file mode 100644
index 1ecf1c5..0000000
--- a/amforth-6.5/appl/arduino/mega128.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10007200FFFF5905E102CC006D049A00B0214B0547
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-:1000B4000A00E100EF00B600D10050FD00003DFD54
-:0800C40004FA23FA13FA1900F3
-:00000001FF
diff --git a/amforth-6.5/appl/arduino/mega128.hex b/amforth-6.5/appl/arduino/mega128.hex
deleted file mode 100644
index 1f30b38..0000000
--- a/amforth-6.5/appl/arduino/mega128.hex
+++ /dev/null
@@ -1,657 +0,0 @@
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diff --git a/amforth-6.5/appl/arduino/mega128.lst b/amforth-6.5/appl/arduino/mega128.lst
deleted file mode 100644
index 9166a69..0000000
--- a/amforth-6.5/appl/arduino/mega128.lst
+++ /dev/null
@@ -1,10415 +0,0 @@
-
-AVRASM ver. 2.1.52 mega128.asm Sun Apr 30 20:10:13 2017
-
-mega128.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega1280\device.asm'
-../../avr8/devices/atmega1280\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m1280def.inc'
-mega128.asm(10): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-mega128.asm(15): Including file '../../avr8\drivers/1wire.asm'
-mega128.asm(18): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(9): Including file '../../avr8\dict/appl_8k.inc'
-../../avr8\dict/appl_8k.inc(1): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(4): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(102): Including file '../../avr8\dict/core_8k.inc'
-../../avr8\dict/core_8k.inc(2): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_8k.inc(3): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_8k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_8k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_8k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_8k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_8k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_8k.inc(10): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_8k.inc(11): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_8k.inc(13): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_8k.inc(14): Including file '../../common\words/words.asm'
-../../avr8\dict/core_8k.inc(15): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_8k.inc(17): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_8k.inc(18): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_8k.inc(19): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_8k.inc(21): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_8k.inc(23): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/core_8k.inc(24): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/core_8k.inc(25): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/core_8k.inc(26): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/core_8k.inc(27): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/core_8k.inc(28): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/core_8k.inc(29): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/core_8k.inc(30): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/core_8k.inc(31): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/core_8k.inc(33): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_8k.inc(34): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_8k.inc(35): Including file '../../common\words/base.asm'
-../../avr8\dict/core_8k.inc(37): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_8k.inc(38): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_8k.inc(40): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_8k.inc(41): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_8k.inc(43): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_8k.inc(45): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_8k.inc(46): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_8k.inc(47): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_8k.inc(48): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_8k.inc(49): Including file '../../common\words/key.asm'
-../../avr8\dict/core_8k.inc(50): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_8k.inc(52): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_8k.inc(53): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_8k.inc(54): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_8k.inc(55): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_8k.inc(57): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_8k.inc(58): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_8k.inc(59): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_8k.inc(60): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_8k.inc(62): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_8k.inc(64): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_8k.inc(65): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_8k.inc(66): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_8k.inc(67): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_8k.inc(68): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_8k.inc(69): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_8k.inc(70): Including file '../../common\words/min.asm'
-../../avr8\dict/core_8k.inc(71): Including file '../../common\words/max.asm'
-../../avr8\dict/core_8k.inc(72): Including file '../../common\words/within.asm'
-../../avr8\dict/core_8k.inc(74): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_8k.inc(75): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_8k.inc(77): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/core_8k.inc(78): Including file '../../common\words/hold.asm'
-../../avr8\dict/core_8k.inc(79): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/core_8k.inc(80): Including file '../../common\words/sharp.asm'
-../../avr8\dict/core_8k.inc(81): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/core_8k.inc(82): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/core_8k.inc(83): Including file '../../common\words/sign.asm'
-../../avr8\dict/core_8k.inc(84): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/core_8k.inc(85): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/core_8k.inc(86): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/core_8k.inc(87): Including file '../../common\words/dot.asm'
-../../avr8\dict/core_8k.inc(88): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/core_8k.inc(89): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/core_8k.inc(90): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/core_8k.inc(91): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/core_8k.inc(93): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/core_8k.inc(94): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/core_8k.inc(95): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/core_8k.inc(96): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/core_8k.inc(97): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_8k.inc(98): Including file '../../common\words/space.asm'
-../../avr8\dict/core_8k.inc(99): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_8k.inc(100): Including file '../../common\words/type.asm'
-../../avr8\dict/core_8k.inc(101): Including file '../../common\words/tick.asm'
-../../avr8\dict/core_8k.inc(103): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_8k.inc(104): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_8k.inc(105): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_8k.inc(107): Including file '../../common\words/cskip.asm'
-../../avr8\dict/core_8k.inc(108): Including file '../../common\words/cscan.asm'
-../../avr8\dict/core_8k.inc(109): Including file '../../common\words/accept.asm'
-../../avr8\dict/core_8k.inc(110): Including file '../../common\words/refill.asm'
-../../avr8\dict/core_8k.inc(111): Including file '../../common\words/char.asm'
-../../avr8\dict/core_8k.inc(112): Including file '../../common\words/number.asm'
-../../avr8\dict/core_8k.inc(113): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/core_8k.inc(114): Including file '../../common\words/set-base.asm'
-../../avr8\dict/core_8k.inc(115): Including file '../../common\words/to-number.asm'
-../../avr8\dict/core_8k.inc(116): Including file '../../common\words/parse.asm'
-../../avr8\dict/core_8k.inc(117): Including file '../../common\words/source.asm'
-../../avr8\dict/core_8k.inc(118): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/core_8k.inc(119): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/core_8k.inc(120): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/core_8k.inc(122): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_8k.inc(123): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_8k.inc(124): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_8k.inc(126): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_8k.inc(127): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_8k.inc(128): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_8k.inc(129): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_8k.inc(131): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/core_8k.inc(132): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/core_8k.inc(133): Including file '../../common\words/depth.asm'
-../../avr8\dict/core_8k.inc(134): Including file '../../common\words/interpret.asm'
-../../avr8\dict/core_8k.inc(135): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/core_8k.inc(136): Including file '../../common\words/recognize.asm'
-../../avr8\dict/core_8k.inc(137): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/core_8k.inc(138): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/core_8k.inc(139): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/core_8k.inc(141): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_8k.inc(142): Including file '../../common\words/ver.asm'
-../../avr8\dict/core_8k.inc(144): Including file '../../common\words/noop.asm'
-../../avr8\dict/core_8k.inc(145): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/core_8k.inc(147): Including file '../../common\words/to.asm'
-../../avr8\dict/core_8k.inc(148): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/core_8k.inc(150): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_8k.inc(151): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_8k.inc(152): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_8k.inc(153): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_8k.inc(154): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_8k.inc(155): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_8k.inc(156): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_8k.inc(157): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_8k.inc(158): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_8k.inc(160): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/core_8k.inc(161): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/core_8k.inc(162): Including file '../../common\words/name2string.asm'
-../../avr8\dict/core_8k.inc(163): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/core_8k.inc(164): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/core_8k.inc(166): Including file '../../common\words/star.asm'
-../../avr8\dict/core_8k.inc(167): Including file '../../avr8\words/j.asm'
-../../avr8\dict/core_8k.inc(169): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/core_8k.inc(170): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/core_8k.inc(171): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/core_8k.inc(172): Including file '../../common\words/2swap.asm'
-../../avr8\dict/core_8k.inc(174): Including file '../../common\words/tib.asm'
-../../avr8\dict/core_8k.inc(176): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/core_8k.inc(177): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/core_8k.inc(178): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_8k.inc(179): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_8k.inc(180): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 512
- .equ CELLSIZE = 2
- .macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
- .endmacro
- .macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- .endmacro
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_USART0 = 0
- .set WANT_TWI = 0
- .set WANT_SPI = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_PORTE = 0
- .set WANT_PORTF = 0
- .set WANT_PORTG = 0
- .set WANT_PORTH = 0
- .set WANT_PORTJ = 0
- .set WANT_PORTK = 0
- .set WANT_PORTL = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_WATCHDOG = 0
- .set WANT_USART1 = 0
- .set WANT_EEPROM = 0
- .set WANT_TIMER_COUNTER_5 = 0
- .set WANT_TIMER_COUNTER_4 = 0
- .set WANT_TIMER_COUNTER_3 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_JTAG = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_CPU = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_USART2 = 0
- .set WANT_USART3 = 0
- .equ intvecsize = 2 ; please verify; flash size: 131072 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d164 rcall isr ; External Interrupt Request 0
- .org 4
-000004 d162 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d160 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d15e rcall isr ; External Interrupt Request 3
- .org 10
-00000a d15c rcall isr ; External Interrupt Request 4
- .org 12
-00000c d15a rcall isr ; External Interrupt Request 5
- .org 14
-00000e d158 rcall isr ; External Interrupt Request 6
- .org 16
-000010 d156 rcall isr ; External Interrupt Request 7
- .org 18
-000012 d154 rcall isr ; Pin Change Interrupt Request 0
- .org 20
-000014 d152 rcall isr ; Pin Change Interrupt Request 1
- .org 22
-000016 d150 rcall isr ; Pin Change Interrupt Request 2
- .org 24
-000018 d14e rcall isr ; Watchdog Time-out Interrupt
- .org 26
-00001a d14c rcall isr ; Timer/Counter2 Compare Match A
- .org 28
-00001c d14a rcall isr ; Timer/Counter2 Compare Match B
- .org 30
-00001e d148 rcall isr ; Timer/Counter2 Overflow
- .org 32
-000020 d146 rcall isr ; Timer/Counter1 Capture Event
- .org 34
-000022 d144 rcall isr ; Timer/Counter1 Compare Match A
- .org 36
-000024 d142 rcall isr ; Timer/Counter1 Compare Match B
- .org 38
-000026 d140 rcall isr ; Timer/Counter1 Compare Match C
- .org 40
-000028 d13e rcall isr ; Timer/Counter1 Overflow
- .org 42
-00002a d13c rcall isr ; Timer/Counter0 Compare Match A
- .org 44
-00002c d13a rcall isr ; Timer/Counter0 Compare Match B
- .org 46
-00002e d138 rcall isr ; Timer/Counter0 Overflow
- .org 48
-000030 d136 rcall isr ; SPI Serial Transfer Complete
- .org 50
-000032 d134 rcall isr ; USART0, Rx Complete
- .org 52
-000034 d132 rcall isr ; USART0 Data register Empty
- .org 54
-000036 d130 rcall isr ; USART0, Tx Complete
- .org 56
-000038 d12e rcall isr ; Analog Comparator
- .org 58
-00003a d12c rcall isr ; ADC Conversion Complete
- .org 60
-00003c d12a rcall isr ; EEPROM Ready
- .org 62
-00003e d128 rcall isr ; Timer/Counter3 Capture Event
- .org 64
-000040 d126 rcall isr ; Timer/Counter3 Compare Match A
- .org 66
-000042 d124 rcall isr ; Timer/Counter3 Compare Match B
- .org 68
-000044 d122 rcall isr ; Timer/Counter3 Compare Match C
- .org 70
-000046 d120 rcall isr ; Timer/Counter3 Overflow
- .org 72
-000048 d11e rcall isr ; USART1, Rx Complete
- .org 74
-00004a d11c rcall isr ; USART1 Data register Empty
- .org 76
-00004c d11a rcall isr ; USART1, Tx Complete
- .org 78
-00004e d118 rcall isr ; 2-wire Serial Interface
- .org 80
-000050 d116 rcall isr ; Store Program Memory Read
- .org 82
-000052 d114 rcall isr ; Timer/Counter4 Capture Event
- .org 84
-000054 d112 rcall isr ; Timer/Counter4 Compare Match A
- .org 86
-000056 d110 rcall isr ; Timer/Counter4 Compare Match B
- .org 88
-000058 d10e rcall isr ; Timer/Counter4 Compare Match C
- .org 90
-00005a d10c rcall isr ; Timer/Counter4 Overflow
- .org 92
-00005c d10a rcall isr ; Timer/Counter5 Capture Event
- .org 94
-00005e d108 rcall isr ; Timer/Counter5 Compare Match A
- .org 96
-000060 d106 rcall isr ; Timer/Counter5 Compare Match B
- .org 98
-000062 d104 rcall isr ; Timer/Counter5 Compare Match C
- .org 100
-000064 d102 rcall isr ; Timer/Counter5 Overflow
- .org 102
-000066 d100 rcall isr ; USART2, Rx Complete
- .org 104
-000068 d0fe rcall isr ; USART2 Data register Empty
- .org 106
-00006a d0fc rcall isr ; USART2, Tx Complete
- .org 108
-00006c d0fa rcall isr ; USART3, Rx Complete
- .org 110
-00006e d0f8 rcall isr ; USART3 Data register Empty
- .org 112
-000070 d0f6 rcall isr ; USART3, Tx Complete
- .equ INTVECTORS = 57
- .nooverlap
-
- ; compatability layer (maybe empty)
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000071 2000 .dw 8192
- mcu_eepromsize:
-000072 1000 .dw 4096
- mcu_maxdp:
-000073 ffff .dw 65535
- mcu_numints:
-000074 0039 .dw 57
- mcu_name:
-000075 000a .dw 10
-000076 5441
-000077 656d
-000078 6167
-000079 3231
-00007a 3038 .db "ATmega1280"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set WANT_IGNORECASE = 1
-
- .equ F_CPU = 16000000
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .equ URXCaddr = URXC0addr
- .equ UDREaddr = UDRE0addr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000200 usart_rx_data: .byte usart_rx_size
-000210 usart_rx_in: .byte 1
-000211 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-00007b ff07 .dw $ff07
-00007c 723e
-00007d 2d78
-00007e 7562
-00007f 0066 .db ">rx-buf",0
-000080 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000081 0082 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000082 2f08 mov temp0, tosl
-000083 9110 0210 lds temp1, usart_rx_in
-000085 e0e0 ldi zl, low(usart_rx_data)
-000086 e0f2 ldi zh, high(usart_rx_data)
-000087 0fe1 add zl, temp1
-000088 1df3 adc zh, zeroh
-000089 8300 st Z, temp0
-00008a 9513 inc temp1
-00008b 701f andi temp1,usart_rx_mask
-00008c 9310 0210 sts usart_rx_in, temp1
-00008e 9189
-00008f 9199 loadtos
-000090 940c f004 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000092 ff06 .dw $ff06
-000093 7369
-000094 2d72
-000095 7872 .db "isr-rx"
-000096 007b .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-000097 f000 .dw DO_COLON
- usart_rx_isr:
-000098 f045 .dw XT_DOLITERAL
-000099 00c6 .dw usart_data
-00009a f0a9 .dw XT_CFETCH
-00009b f0c2 .dw XT_DUP
-00009c f045 .dw XT_DOLITERAL
-00009d 0003 .dw 3
-00009e fdaa .dw XT_EQUAL
-00009f f03e .dw XT_DOCONDBRANCH
-0000a0 00a2 .dw usart_rx_isr1
-0000a1 fa73 .dw XT_COLD
- usart_rx_isr1:
-0000a2 0081 .dw XT_TO_RXBUF
-0000a3 f025 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-0000a4 f000 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-0000a5 f045
-0000a6 0097 .dw XT_DOLITERAL, XT_ISR_RX
-0000a7 f045
-0000a8 0032 .dw XT_DOLITERAL, URXCaddr
-0000a9 f4a1 .dw XT_INTSTORE
-
-0000aa f045 .dw XT_DOLITERAL
-0000ab 0200 .dw usart_rx_data
-0000ac f045 .dw XT_DOLITERAL
-0000ad 0016 .dw usart_rx_size + 6
-0000ae f165 .dw XT_ZERO
-0000af f4e9 .dw XT_FILL
-0000b0 f025 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-0000b1 ff06 .dw $ff06
-0000b2 7872
-0000b3 622d
-0000b4 6675 .db "rx-buf"
-0000b5 0092 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-0000b6 f000 .dw DO_COLON
- PFA_RX_BUFFER:
-0000b7 00d1 .dw XT_RXQ_BUFFER
-0000b8 f03e .dw XT_DOCONDBRANCH
-0000b9 00b7 .dw PFA_RX_BUFFER
-0000ba f045 .dw XT_DOLITERAL
-0000bb 0211 .dw usart_rx_out
-0000bc f0a9 .dw XT_CFETCH
-0000bd f0c2 .dw XT_DUP
-0000be f045 .dw XT_DOLITERAL
-0000bf 0200 .dw usart_rx_data
-0000c0 f1ae .dw XT_PLUS
-0000c1 f0a9 .dw XT_CFETCH
-0000c2 f0d5 .dw XT_SWAP
-0000c3 f240 .dw XT_1PLUS
-0000c4 f045 .dw XT_DOLITERAL
-0000c5 000f .dw usart_rx_mask
-0000c6 f224 .dw XT_AND
-0000c7 f045 .dw XT_DOLITERAL
-0000c8 0211 .dw usart_rx_out
-0000c9 f09e .dw XT_CSTORE
-0000ca f025 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-0000cb ff07 .dw $ff07
-0000cc 7872
-0000cd 2d3f
-0000ce 7562
-0000cf 0066 .db "rx?-buf",0
-0000d0 00b1 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-0000d1 f000 .dw DO_COLON
- PFA_RXQ_BUFFER:
-0000d2 fa6b .dw XT_PAUSE
-0000d3 f045 .dw XT_DOLITERAL
-0000d4 0211 .dw usart_rx_out
-0000d5 f0a9 .dw XT_CFETCH
-0000d6 f045 .dw XT_DOLITERAL
-0000d7 0210 .dw usart_rx_in
-0000d8 f0a9 .dw XT_CFETCH
-0000d9 f124 .dw XT_NOTEQUAL
-0000da f025 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-0000db ff07 .dw $ff07
-0000dc 7874
-0000dd 702d
-0000de 6c6f
-0000df 006c .db "tx-poll",0
-0000e0 00cb .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000e1 f000 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000e2 00ef .dw XT_TXQ_POLL
-0000e3 f03e .dw XT_DOCONDBRANCH
-0000e4 00e2 .dw PFA_TX_POLL
- ; send to usart
-0000e5 f045 .dw XT_DOLITERAL
-0000e6 00c6 .dw USART_DATA
-0000e7 f09e .dw XT_CSTORE
-0000e8 f025 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000e9 ff08 .dw $ff08
-0000ea 7874
-0000eb 2d3f
-0000ec 6f70
-0000ed 6c6c .db "tx?-poll"
-0000ee 00db .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000ef f000 .dw DO_COLON
- PFA_TXQ_POLL:
-0000f0 fa6b .dw XT_PAUSE
-0000f1 f045 .dw XT_DOLITERAL
-0000f2 00c0 .dw USART_A
-0000f3 f0a9 .dw XT_CFETCH
-0000f4 f045 .dw XT_DOLITERAL
-0000f5 0020 .dw bm_USART_TXRD
-0000f6 f224 .dw XT_AND
-0000f7 f025 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000f8 ff04 .dw $ff04
-0000f9 6275
-0000fa 7272 .db "ubrr"
-0000fb 00e9 .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000fc f080 .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000fd 00ca .dw EE_UBRRVAL
-0000fe fbce .dw XT_EDEFERFETCH
-0000ff fbd8 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-000100 ff06 .dw $ff06
-000101 752b
-000102 6173
-000103 7472 .db "+usart"
-000104 00f8 .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-000105 f000 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-000106 f045 .dw XT_DOLITERAL
-000107 0098 .dw USART_B_VALUE
-000108 f045 .dw XT_DOLITERAL
-000109 00c1 .dw USART_B
-00010a f09e .dw XT_CSTORE
-
-00010b f045 .dw XT_DOLITERAL
-00010c 0006 .dw USART_C_VALUE
-00010d f045 .dw XT_DOLITERAL
-00010e 00c2 .dw USART_C | bm_USARTC_en
-00010f f09e .dw XT_CSTORE
-
-000110 00fc .dw XT_UBRR
-000111 f0c2 .dw XT_DUP
-000112 f30a .dw XT_BYTESWAP
-000113 f045 .dw XT_DOLITERAL
-000114 00c5 .dw BAUDRATE_HIGH
-000115 f09e .dw XT_CSTORE
-000116 f045 .dw XT_DOLITERAL
-000117 00c4 .dw BAUDRATE_LOW
-000118 f09e .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-000119 00a4 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-00011a f025 .dw XT_EXIT
-
- ; settings for 1wire interface, if desired
- .equ OW_PORT=PORTE
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-00011b ff08 .dw $ff08
-00011c 7731
-00011d 722e
-00011e 7365
-00011f 7465 .db "1w.reset"
-000120 0100 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-000121 0122 .dw PFA_OW_RESET
- PFA_OW_RESET:
-000122 939a
-000123 938a savetos
- ; setup to output
-000124 9a6c sbi OW_DDR, OW_BIT
- ; Pull output low
-000125 9874 cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-000126 e8e0
-000127 e0f7
-000128 9731
-000129 f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-00012a b71f in temp1, SREG
-00012b 94f8 cli
- ; Pull output high
-00012c 9a74 sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-00012d 986c cbi OW_DDR, OW_BIT
-00012e e0e0
-00012f e0f1
-000130 9731
-000131 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-000132 b18c in tosl, OW_PIN
-000133 ff84 sbrs tosl, OW_BIT
-000134 ef9f ser tosh
- ; End critical timing period, enable interrupts
-000135 bf1f out SREG, temp1
- ; release bus
-000136 986c cbi OW_DDR, OW_BIT
-000137 9874 cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-000138 e8e0
-000139 e0f6
-00013a 9731
-00013b f7f1 DELAY 416
- ; we now have the result flag in TOS
-00013c 2f89 mov tosl, tosh
-00013d 940c f004 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-00013f ff07 .dw $ff07
-000140 7731
-000141 732e
-000142 6f6c
-000143 0074 .db "1w.slot",0
-000144 011b .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-000145 0146 .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-000146 9874 cbi OW_PORT, OW_BIT
-000147 9a6c sbi OW_DDR, OW_BIT
- ; disable interrupts
-000148 b71f in temp1, SREG
-000149 94f8 cli
-00014a e1e8
-00014b e0f0
-00014c 9731
-00014d f7f1 DELAY 6 ; DELAY A
- ; check bit
-00014e 9488 clc
-00014f 9587 ror tosl
-000150 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000151 9a74 sbi OW_PORT, OW_BIT
-000152 986c cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-000153 e2e4
-000154 e0f0
-000155 9731
-000156 f7f1 DELAY 9 ; wait DELAY E to sample
-000157 b10c in temp0, OW_PIN
-000158 fd04 sbrc temp0, OW_BIT
-000159 6880 ori tosl, $80
-
-00015a ecec
-00015b e0f0
-00015c 9731
-00015d f7f1 DELAY 51 ; DELAY B
-00015e 9a74 sbi OW_PORT, OW_BIT ; release bus
-00015f 986c cbi OW_DDR, OW_BIT
-000160 e0e8
-000161 e0f0
-000162 9731
-000163 f7f1 delay 2
- ; re-enable interrupts
-000164 bf1f out SREG, temp1
-000165 940c f004 jmp_ DO_NEXT
-
- ; include the whole source tree.
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c fa74 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000212 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-000167 920a st -Y, r0
-000168 b60f in r0, SREG
-000169 920a st -Y, r0
- .if (pclen==3)
- .endif
-00016a 900f pop r0
-00016b 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-00016c 940a dec r0
- .if intvecsize == 1 ;
- .endif
-00016d 2cb0 mov isrflag, r0
-00016e 93ff push zh
-00016f 93ef push zl
-000170 e1e2 ldi zl, low(intcnt)
-000171 e0f2 ldi zh, high(intcnt)
-000172 9406 lsr r0 ; we use byte addresses in the counter array, not words
-000173 0de0 add zl, r0
-000174 1df3 adc zh, zeroh
-000175 8000 ld r0, Z
-000176 9403 inc r0
-000177 8200 st Z, r0
-000178 91ef pop zl
-000179 91ff pop zh
-
-00017a 9009 ld r0, Y+
-00017b be0f out SREG, r0
-00017c 9009 ld r0, Y+
-00017d 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-00017e ff02 .dw $ff02
-00017f 2b6d .db "m+"
-000180 013f .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000181 f000 .dw DO_COLON
- PFA_MPLUS:
-000182 fd92 .dw XT_S2D
-000183 f42f .dw XT_DPLUS
-000184 f025 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-000185 ff03 .dw $ff03
-000186 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-000187 002a .db "ud*"
-000188 017e .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-000189 f000 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-00018a f0c2
-00018b f110
-00018c f1f1
-00018d f0ea .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-00018e f0d5
-00018f f107
-000190 f1f1
-000191 f0f2
-000192 f1ae
-000193 f025 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-000194 ff04 .dw $ff04
-000195 6d75
-000196 7861 .db "umax"
-000197 0185 .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-000198 f000 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-000199 f57f
-00019a f16d .DW XT_2DUP,XT_ULESS
-00019b f03e .dw XT_DOCONDBRANCH
-00019c 019e DEST(UMAX1)
-00019d f0d5 .DW XT_SWAP
-00019e f0ea UMAX1: .DW XT_DROP
-00019f f025 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-0001a0 ff04 .dw $ff04
-0001a1 6d75
-0001a2 6e69 .db "umin"
-0001a3 0194 .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-0001a4 f000 .dw DO_COLON
- PFA_UMIN:
- .endif
-0001a5 f57f
-0001a6 f178 .DW XT_2DUP,XT_UGREATER
-0001a7 f03e .dw XT_DOCONDBRANCH
-0001a8 01aa DEST(UMIN1)
-0001a9 f0d5 .DW XT_SWAP
-0001aa f0ea UMIN1: .DW XT_DROP
-0001ab f025 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-0001ac f000 .dw DO_COLON
- PFA_IMMEDIATEQ:
-0001ad f045 .dw XT_DOLITERAL
-0001ae 8000 .dw $8000
-0001af f224 .dw XT_AND
-0001b0 f12b .dw XT_ZEROEQUAL
-0001b1 f03e .dw XT_DOCONDBRANCH
-0001b2 01b5 DEST(IMMEDIATEQ1)
-0001b3 fdb1 .dw XT_ONE
-0001b4 f025 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-0001b5 f15c .dw XT_TRUE
-0001b6 f025 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-0001b7 ff0a .dw $ff0a
-0001b8 616e
-0001b9 656d
-0001ba 663e
-0001bb 616c
-0001bc 7367 .db "name>flags"
-0001bd 01a0 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-0001be f000 .dw DO_COLON
- PFA_NAME2FLAGS:
-0001bf f3e2 .dw XT_FETCHI ; skip to link field
-0001c0 f045 .dw XT_DOLITERAL
-0001c1 ff00 .dw $ff00
-0001c2 f224 .dw XT_AND
-0001c3 f025 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .include "dict/appl_8k.inc"
-
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-0001c4 ff06 .dw $ff06
-0001c5 656e
-0001c6 6577
-0001c7 7473 .db "newest"
-0001c8 01b7 .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-0001c9 f053 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-0001ca 024b .dw ram_newest
-
- .dseg
-00024b ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-0001cb ff06 .dw $ff06
-0001cc 616c
-0001cd 6574
-0001ce 7473 .db "latest"
-0001cf 01c4 .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-0001d0 f053 .dw PFA_DOVARIABLE
- PFA_LATEST:
-0001d1 024f .dw ram_latest
-
- .dseg
-00024f ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-0001d2 ff08 .dw $ff08
-0001d3 6328
-0001d4 6572
-0001d5 7461
-0001d6 2965 .db "(create)"
-0001d7 01cb .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-0001d8 f000 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-0001d9 f9ce
-0001da 032f .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-0001db f0c2
-0001dc 01c9
-0001dd f578
-0001de f092 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-0001df 0314
-0001e0 01c9
-0001e1 f092 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-0001e2 f025 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-0001e3 0001 .dw $0001
-0001e4 005c .db $5c,0
-0001e5 01d2 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-0001e6 f000 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-0001e7 f9b5 .dw XT_SOURCE
-0001e8 f101 .dw XT_NIP
-0001e9 f598 .dw XT_TO_IN
-0001ea f092 .dw XT_STORE
-0001eb f025 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-0001ec 0001 .dw $0001
-0001ed 0028 .db "(" ,0
-0001ee 01e3 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-0001ef f000 .dw DO_COLON
- PFA_LPAREN:
- .endif
-0001f0 f045 .dw XT_DOLITERAL
-0001f1 0029 .dw ')'
-0001f2 f9a1 .dw XT_PARSE
-0001f3 f588 .dw XT_2DROP
-0001f4 f025 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-0001f5 ff07 .dw $ff07
-0001f6 6f63
-0001f7 706d
-0001f8 6c69
-0001f9 0065 .db "compile",0
-0001fa 01ec .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-0001fb f000 .dw DO_COLON
- PFA_COMPILE:
- .endif
-0001fc f107 .dw XT_R_FROM
-0001fd f0c2 .dw XT_DUP
-0001fe fbc5 .dw XT_ICELLPLUS
-0001ff f110 .dw XT_TO_R
-000200 f3e2 .dw XT_FETCHI
-000201 0206 .dw XT_COMMA
-000202 f025 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-000203 ff01 .dw $ff01
-000204 002c .db ',',0 ; ,
-000205 01f5 .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-000206 f000 .dw DO_COLON
- PFA_COMMA:
-000207 f5c8 .dw XT_DP
-000208 f384 .dw XT_STOREI
-000209 f5c8 .dw XT_DP
-00020a f240 .dw XT_1PLUS
-00020b fbb3 .dw XT_DOTO
-00020c f5c9 .dw PFA_DP
-00020d f025 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-00020e 0003 .dw $0003
-00020f 275b
-000210 005d .db "[']",0
-000211 0203 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-000212 f000 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-000213 f824 .dw XT_TICK
-000214 021c .dw XT_LITERAL
-000215 f025 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-000216 0007 .dw $0007
-000217 696c
-000218 6574
-000219 6172
-00021a 006c .db "literal",0
-00021b 020e .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-00021c f000 .dw DO_COLON
- PFA_LITERAL:
- .endif
-00021d 01fb .DW XT_COMPILE
-00021e f045 .DW XT_DOLITERAL
-00021f 0206 .DW XT_COMMA
-000220 f025 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-000221 0008 .dw $0008
-000222 6c73
-000223 7469
-000224 7265
-000225 6c61 .db "sliteral"
-000226 0216 .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-000227 f000 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-000228 01fb .dw XT_COMPILE
-000229 f787 .dw XT_DOSLITERAL ; ( -- addr n)
-00022a f795 .dw XT_SCOMMA
-00022b f025 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-00022c f000 .dw DO_COLON
- PFA_GMARK:
-00022d f5c8 .dw XT_DP
-00022e 01fb .dw XT_COMPILE
-00022f ffff .dw -1 ; ffff does not erase flash
-000230 f025 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000231 f000 .dw DO_COLON
- PFA_GRESOLVE:
-000232 fb71 .dw XT_QSTACK
-000233 f5c8 .dw XT_DP
-000234 f0d5 .dw XT_SWAP
-000235 f384 .dw XT_STOREI
-000236 f025 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-000237 f000 .dw DO_COLON
- PFA_LMARK:
-000238 f5c8 .dw XT_DP
-000239 f025 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-00023a f000 .dw DO_COLON
- PFA_LRESOLVE:
-00023b fb71 .dw XT_QSTACK
-00023c 0206 .dw XT_COMMA
-00023d f025 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-00023e 0005 .dw $0005
-00023f 6861
-000240 6165
-000241 0064 .db "ahead",0
-000242 0221 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-000243 f000 .dw DO_COLON
- PFA_AHEAD:
- .endif
-000244 01fb .dw XT_COMPILE
-000245 f034 .dw XT_DOBRANCH
-000246 022c .dw XT_GMARK
-000247 f025 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-000248 0002 .dw $0002
-000249 6669 .db "if"
-00024a 023e .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-00024b f000 .dw DO_COLON
- PFA_IF:
- .endif
-00024c 01fb .dw XT_COMPILE
-00024d f03e .dw XT_DOCONDBRANCH
-00024e 022c .dw XT_GMARK
-00024f f025 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-000250 0004 .dw $0004
-000251 6c65
-000252 6573 .db "else"
-000253 0248 .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-000254 f000 .dw DO_COLON
- PFA_ELSE:
- .endif
-000255 01fb .dw XT_COMPILE
-000256 f034 .dw XT_DOBRANCH
-000257 022c .dw XT_GMARK
-000258 f0d5 .dw XT_SWAP
-000259 0231 .dw XT_GRESOLVE
-00025a f025 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-00025b 0004 .dw $0004
-00025c 6874
-00025d 6e65 .db "then"
-00025e 0250 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-00025f f000 .dw DO_COLON
- PFA_THEN:
- .endif
-000260 0231 .dw XT_GRESOLVE
-000261 f025 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-000262 0005 .dw $0005
-000263 6562
-000264 6967
-000265 006e .db "begin",0
-000266 025b .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-000267 f000 .dw DO_COLON
- PFA_BEGIN:
- .endif
-000268 0237 .dw XT_LMARK
-000269 f025 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-00026a 0005 .dw $0005
-00026b 6877
-00026c 6c69
-00026d 0065 .db "while",0
-00026e 0262 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-00026f f000 .dw DO_COLON
- PFA_WHILE:
- .endif
-000270 024b .dw XT_IF
-000271 f0d5 .dw XT_SWAP
-000272 f025 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-000273 0006 .dw $0006
-000274 6572
-000275 6570
-000276 7461 .db "repeat"
-000277 026a .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-000278 f000 .dw DO_COLON
- PFA_REPEAT:
- .endif
-000279 028c .dw XT_AGAIN
-00027a 025f .dw XT_THEN
-00027b f025 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-00027c 0005 .dw $0005
-00027d 6e75
-00027e 6974
-00027f 006c .db "until",0
-000280 0273 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-000281 f000 .dw DO_COLON
- PFA_UNTIL:
- .endif
-000282 f045 .dw XT_DOLITERAL
-000283 f03e .dw XT_DOCONDBRANCH
-000284 0206 .dw XT_COMMA
-
-000285 023a .dw XT_LRESOLVE
-000286 f025 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-000287 0005 .dw $0005
-000288 6761
-000289 6961
-00028a 006e .db "again",0
-00028b 027c .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-00028c f000 .dw DO_COLON
- PFA_AGAIN:
- .endif
-00028d 01fb .dw XT_COMPILE
-00028e f034 .dw XT_DOBRANCH
-00028f 023a .dw XT_LRESOLVE
-000290 f025 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-000291 0002 .dw $0002
-000292 6f64 .db "do"
-000293 0287 .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-000294 f000 .dw DO_COLON
- PFA_DO:
-
- .endif
-000295 01fb .dw XT_COMPILE
-000296 f2ac .dw XT_DODO
-000297 0237 .dw XT_LMARK
-000298 f165 .dw XT_ZERO
-000299 02ef .dw XT_TO_L
-00029a f025 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-00029b 0004 .dw $0004
-00029c 6f6c
-00029d 706f .db "loop"
-00029e 0291 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-00029f f000 .dw DO_COLON
- PFA_LOOP:
- .endif
-0002a0 01fb .dw XT_COMPILE
-0002a1 f2da .dw XT_DOLOOP
-0002a2 02d6 .dw XT_ENDLOOP
-0002a3 f025 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-0002a4 0005 .dw $0005
-0002a5 6c2b
-0002a6 6f6f
-0002a7 0070 .db "+loop",0
-0002a8 029b .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-0002a9 f000 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-0002aa 01fb .dw XT_COMPILE
-0002ab f2cb .dw XT_DOPLUSLOOP
-0002ac 02d6 .dw XT_ENDLOOP
-0002ad f025 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-0002ae 0005 .dw $0005
-0002af 656c
-0002b0 7661
-0002b1 0065 .db "leave",0
-0002b2 02a4 .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-0002b3 f000 .dw DO_COLON
- PFA_LEAVE:
- .endif
-0002b4 01fb
-0002b5 f2e5 .DW XT_COMPILE,XT_UNLOOP
-0002b6 0243
-0002b7 02ef
-0002b8 f025 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-0002b9 0003 .dw $0003
-0002ba 643f
-0002bb 006f .db "?do",0
-0002bc 02ae .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-0002bd f000 .dw DO_COLON
- PFA_QDO:
- .endif
-0002be 01fb .dw XT_COMPILE
-0002bf 02c5 .dw XT_QDOCHECK
-0002c0 024b .dw XT_IF
-0002c1 0294 .dw XT_DO
-0002c2 f0d5 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-0002c3 02ef .dw XT_TO_L ; then follows at the end.
-0002c4 f025 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-0002c5 f000 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-0002c6 f57f .dw XT_2DUP
-0002c7 fdaa .dw XT_EQUAL
-0002c8 f0c2 .dw XT_DUP
-0002c9 f110 .dw XT_TO_R
-0002ca f03e .dw XT_DOCONDBRANCH
-0002cb 02cd DEST(PFA_QDOCHECK1)
-0002cc f588 .dw XT_2DROP
- PFA_QDOCHECK1:
-0002cd f107 .dw XT_R_FROM
-0002ce f20e .dw XT_INVERT
-0002cf f025 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-0002d0 ff07 .dw $ff07
-0002d1 6e65
-0002d2 6c64
-0002d3 6f6f
-0002d4 0070 .db "endloop",0
-0002d5 02b9 .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-0002d6 f000 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-0002d7 023a .DW XT_LRESOLVE
-0002d8 02e3
-0002d9 f0ca
-0002da f03e LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-0002db 02df DEST(LOOP2)
-0002dc 025f .DW XT_THEN
-0002dd f034 .dw XT_DOBRANCH
-0002de 02d8 DEST(LOOP1)
-0002df f025 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-0002e0 ff02 .dw $ff02
-0002e1 3e6c .db "l>"
-0002e2 02d0 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-0002e3 f000 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-0002e4 0302 .dw XT_LP
-0002e5 f08a .dw XT_FETCH
-0002e6 f08a .dw XT_FETCH
-0002e7 f045 .dw XT_DOLITERAL
-0002e8 fffe .dw -2
-0002e9 0302 .dw XT_LP
-0002ea f276 .dw XT_PLUSSTORE
-0002eb f025 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-0002ec ff02 .dw $ff02
-0002ed 6c3e .db ">l"
-0002ee 02e0 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-0002ef f000 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-0002f0 fdb6 .dw XT_TWO
-0002f1 0302 .dw XT_LP
-0002f2 f276 .dw XT_PLUSSTORE
-0002f3 0302 .dw XT_LP
-0002f4 f08a .dw XT_FETCH
-0002f5 f092 .dw XT_STORE
-0002f6 f025 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-0002f7 ff03 .dw $ff03
-0002f8 706c
-0002f9 0030 .db "lp0",0
-0002fa 02ec .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-0002fb f080 .dw PFA_DOVALUE1
- PFA_LP0:
-0002fc 007e .dw CFG_LP0
-0002fd fbce .dw XT_EDEFERFETCH
-0002fe fbd8 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-0002ff ff02 .dw $ff02
-000300 706c .db "lp"
-000301 02f7 .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-000302 f053 .dw PFA_DOVARIABLE
- PFA_LP:
-000303 0251 .dw ram_lp
-
- .dseg
-000251 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-000304 ff06 .dw $ff06
-000305 7263
-000306 6165
-000307 6574 .db "create"
-000308 02ff .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-000309 f000 .dw DO_COLON
- PFA_CREATE:
- .endif
-00030a 01d8 .dw XT_DOCREATE
-00030b 0338 .dw XT_REVEAL
-00030c 01fb .dw XT_COMPILE
-00030d f060 .dw PFA_DOCONSTANT
-00030e f025 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-00030f ff06 .dw $ff06
-000310 6568
-000311 6461
-000312 7265 .db "header"
-000313 0304 .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-000314 f000 .dw DO_COLON
- PFA_HEADER:
-000315 f5c8 .dw XT_DP ; the new Name Field
-000316 f110 .dw XT_TO_R
-000317 f110 .dw XT_TO_R ; ( R: NFA WID )
-000318 f0c2 .dw XT_DUP
-000319 f139 .dw XT_GREATERZERO
-00031a f03e .dw XT_DOCONDBRANCH
-00031b 0326 .dw PFA_HEADER1
-00031c f0c2 .dw XT_DUP
-00031d f045 .dw XT_DOLITERAL
-00031e ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-00031f f22d .dw XT_OR
-000320 f799 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-000321 f107 .dw XT_R_FROM
-000322 f370 .dw XT_FETCHE
-000323 0206 .dw XT_COMMA
-000324 f107 .dw XT_R_FROM
-000325 f025 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-000326 f045 .dw XT_DOLITERAL
-000327 fff0 .dw -16
-000328 f85b .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-000329 ff07 .dw $ff07
-00032a 6c77
-00032b 6373
-00032c 706f
-00032d 0065 .db "wlscope",0
-00032e 030f .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-00032f fc2d .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000330 007a .dw CFG_WLSCOPE
-000331 fbce .dw XT_EDEFERFETCH
-000332 fbd8 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000333 ff06 .dw $ff06
-000334 6572
-000335 6576
-000336 6c61 .db "reveal"
-000337 0329 .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-000338 f000 .dw DO_COLON
- PFA_REVEAL:
- .endif
-000339 01c9
-00033a f578
-00033b f08a .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-00033c f0ca
-00033d f03e .DW XT_QDUP,XT_DOCONDBRANCH
-00033e 0343 DEST(REVEAL1)
-00033f 01c9
-000340 f08a
-000341 f0d5
-000342 f34c .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-000343 f025 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-000344 0005 .dw $0005
-000345 6f64
-000346 7365
-000347 003e .db "does>",0
-000348 0333 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-000349 f000 .dw DO_COLON
- PFA_DOES:
-00034a 01fb .dw XT_COMPILE
-00034b 035c .dw XT_DODOES
-00034c 01fb .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-00034d 940e .dw $940e ; the address of this compiled
-00034e 01fb .dw XT_COMPILE ; code will replace the XT of the
-00034f 0351 .dw DO_DODOES ; word that CREATE created
-000350 f025 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-000351 939a
-000352 938a savetos
-000353 01cb movw tosl, wl
-000354 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-000355 917f pop wh
-000356 916f pop wl
-
-000357 93bf push XH
-000358 93af push XL
-000359 01db movw XL, wl
-00035a 940c f004 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-00035c f000 .dw DO_COLON
- PFA_DODOES:
-00035d f107 .dw XT_R_FROM
-00035e 01c9 .dw XT_NEWEST
-00035f f578 .dw XT_CELLPLUS
-000360 f08a .dw XT_FETCH
-000361 f370 .dw XT_FETCHE
-000362 fc98 .dw XT_NFA2CFA
-000363 f384 .dw XT_STOREI
-000364 f025 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-000365 ff01 .dw $ff01
-000366 003a .db ":",0
-000367 0344 .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-000368 f000 .dw DO_COLON
- PFA_COLON:
- .endif
-000369 01d8 .dw XT_DOCREATE
-00036a 0373 .dw XT_COLONNONAME
-00036b f0ea .dw XT_DROP
-00036c f025 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-00036d ff07 .dw $ff07
-00036e 6e3a
-00036f 6e6f
-000370 6d61
-000371 0065 .db ":noname",0
-000372 0365 .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-000373 f000 .dw DO_COLON
- PFA_COLONNONAME:
-000374 f5c8 .dw XT_DP
-000375 f0c2 .dw XT_DUP
-000376 01d0 .dw XT_LATEST
-000377 f092 .dw XT_STORE
-
-000378 01fb .dw XT_COMPILE
-000379 f000 .dw DO_COLON
-
-00037a 0388 .dw XT_RBRACKET
-00037b f025 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-00037c 0001 .dw $0001
-00037d 003b .db $3b,0
-00037e 036d .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-00037f f000 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-000380 01fb .dw XT_COMPILE
-000381 f025 .dw XT_EXIT
-000382 0390 .dw XT_LBRACKET
-000383 0338 .dw XT_REVEAL
-000384 f025 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-000385 ff01 .dw $ff01
-000386 005d .db "]",0
-000387 037c .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-000388 f000 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-000389 fdb1 .dw XT_ONE
-00038a f565 .dw XT_STATE
-00038b f092 .dw XT_STORE
-00038c f025 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-00038d 0001 .dw $0001
-00038e 005b .db "[",0
-00038f 0385 .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-000390 f000 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-000391 f165 .dw XT_ZERO
-000392 f565 .dw XT_STATE
-000393 f092 .dw XT_STORE
-000394 f025 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-000395 ff08 .dw $ff08
-000396 6176
-000397 6972
-000398 6261
-000399 656c .db "variable"
-00039a 038d .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-00039b f000 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-00039c f5d9 .dw XT_HERE
-00039d 03a7 .dw XT_CONSTANT
-00039e fdb6 .dw XT_TWO
-00039f f5e2 .dw XT_ALLOT
-0003a0 f025 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-0003a1 ff08 .dw $ff08
-0003a2 6f63
-0003a3 736e
-0003a4 6174
-0003a5 746e .db "constant"
-0003a6 0395 .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-0003a7 f000 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-0003a8 01d8 .dw XT_DOCREATE
-0003a9 0338 .dw XT_REVEAL
-0003aa 01fb .dw XT_COMPILE
-0003ab f053 .dw PFA_DOVARIABLE
-0003ac 0206 .dw XT_COMMA
-0003ad f025 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-0003ae ff04 .dw $ff04
-0003af 7375
-0003b0 7265 .db "user"
-0003b1 03a1 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-0003b2 f000 .dw DO_COLON
- PFA_USER:
-0003b3 01d8 .dw XT_DOCREATE
-0003b4 0338 .dw XT_REVEAL
-
-0003b5 01fb .dw XT_COMPILE
-0003b6 f066 .dw PFA_DOUSER
-0003b7 0206 .dw XT_COMMA
-0003b8 f025 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-0003b9 0007 .dw $0007
-0003ba 6572
-0003bb 7563
-0003bc 7372
-0003bd 0065 .db "recurse",0
-0003be 03ae .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-0003bf f000 .dw DO_COLON
- PFA_RECURSE:
- .endif
-0003c0 01d0 .dw XT_LATEST
-0003c1 f08a .dw XT_FETCH
-0003c2 0206 .dw XT_COMMA
-0003c3 f025 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-0003c4 ff09 .dw $ff09
-0003c5 6d69
-0003c6 656d
-0003c7 6964
-0003c8 7461
-0003c9 0065 .db "immediate",0
-0003ca 03b9 .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-0003cb f000 .dw DO_COLON
- PFA_IMMEDIATE:
-0003cc 046d .dw XT_GET_CURRENT
-0003cd f370 .dw XT_FETCHE
-0003ce f0c2 .dw XT_DUP
-0003cf f3e2 .dw XT_FETCHI
-0003d0 f045 .dw XT_DOLITERAL
-0003d1 7fff .dw $7fff
-0003d2 f224 .dw XT_AND
-0003d3 f0d5 .dw XT_SWAP
-0003d4 f384 .dw XT_STOREI
-0003d5 f025 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-0003d6 0006 .dw $0006
-0003d7 635b
-0003d8 6168
-0003d9 5d72 .db "[char]"
-0003da 03c4 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-0003db f000 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-0003dc 01fb .dw XT_COMPILE
-0003dd f045 .dw XT_DOLITERAL
-0003de f904 .dw XT_CHAR
-0003df 0206 .dw XT_COMMA
-0003e0 f025 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-0003e1 0006 .dw $0006
-0003e2 6261
-0003e3 726f
-0003e4 2274 .db "abort",'"'
-0003e5 03d6 .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-0003e6 f000 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-0003e7 f4db .dw XT_SQUOTE
-0003e8 01fb .dw XT_COMPILE
-0003e9 03f8 .dw XT_QABORT
-0003ea f025 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-0003eb ff05 .dw $ff05
-0003ec 6261
-0003ed 726f
-0003ee 0074 .db "abort",0
-0003ef 03e1 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-0003f0 f000 .dw DO_COLON
- PFA_ABORT:
- .endif
-0003f1 f15c .dw XT_TRUE
-0003f2 f85b .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-0003f3 ff06 .dw $ff06
-0003f4 613f
-0003f5 6f62
-0003f6 7472 .db "?abort"
-0003f7 03eb .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-0003f8 f000 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-0003f9 f0f2
-0003fa f03e .DW XT_ROT,XT_DOCONDBRANCH
-0003fb 03fe DEST(QABO1)
-0003fc f7ba
-0003fd 03f0 .DW XT_ITYPE,XT_ABORT
-0003fe f588
-0003ff f025 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000400 ff09 .dw $ff09
-000401 6567
-000402 2d74
-000403 7473
-000404 6361
-000405 006b .db "get-stack",0
-000406 03f3 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-000407 f000 .dw DO_COLON
- .endif
-000408 f0c2 .dw XT_DUP
-000409 f578 .dw XT_CELLPLUS
-00040a f0d5 .dw XT_SWAP
-00040b f370 .dw XT_FETCHE
-00040c f0c2 .dw XT_DUP
-00040d f110 .dw XT_TO_R
-00040e f165 .dw XT_ZERO
-00040f f0d5 .dw XT_SWAP ; go from bigger to smaller addresses
-000410 02c5 .dw XT_QDOCHECK
-000411 f03e .dw XT_DOCONDBRANCH
-000412 041e DEST(PFA_N_FETCH_E2)
-000413 f2ac .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-000414 f2bd .dw XT_I
-000415 f246 .dw XT_1MINUS
-000416 f572 .dw XT_CELLS ; ( -- ee-addr i*2 )
-000417 f0e0 .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-000418 f1ae .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-000419 f370 .dw XT_FETCHE ;( -- ee-addr item_i )
-00041a f0d5 .dw XT_SWAP ;( -- item_i ee-addr )
-00041b f15c .dw XT_TRUE ; shortcut for -1
-00041c f2cb .dw XT_DOPLUSLOOP
-00041d 0414 DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-00041e f588 .dw XT_2DROP
-00041f f107 .dw XT_R_FROM
-000420 f025 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-000421 ff09 .dw $ff09
-000422 6573
-000423 2d74
-000424 7473
-000425 6361
-000426 006b .db "set-stack",0
-000427 0400 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-000428 f000 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-000429 f0e0 .dw XT_OVER
-00042a f132 .dw XT_ZEROLESS
-00042b f03e .dw XT_DOCONDBRANCH
-00042c 0430 DEST(PFA_SET_STACK0)
-00042d f045 .dw XT_DOLITERAL
-00042e fffc .dw -4
-00042f f85b .dw XT_THROW
- PFA_SET_STACK0:
-000430 f57f .dw XT_2DUP
-000431 f34c .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000432 f0d5 .dw XT_SWAP
-000433 f165 .dw XT_ZERO
-000434 02c5 .dw XT_QDOCHECK
-000435 f03e .dw XT_DOCONDBRANCH
-000436 043d DEST(PFA_SET_STACK2)
-000437 f2ac .dw XT_DODO
- PFA_SET_STACK1:
-000438 f578 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-000439 f590 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-00043a f34c .dw XT_STOREE
-00043b f2da .dw XT_DOLOOP
-00043c 0438 DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-00043d f0ea .dw XT_DROP
-00043e f025 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-00043f ff09 .dw $ff09
-000440 616d
-000441 2d70
-000442 7473
-000443 6361
-000444 006b .db "map-stack",0
-000445 0421 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-000446 f000 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-000447 f0c2 .dw XT_DUP
-000448 f578 .dw XT_CELLPLUS
-000449 f0d5 .dw XT_SWAP
-00044a f370 .dw XT_FETCHE
-00044b f572 .dw XT_CELLS
-00044c fd89 .dw XT_BOUNDS
-00044d 02c5 .dw XT_QDOCHECK
-00044e f03e .dw XT_DOCONDBRANCH
-00044f 0462 DEST(PFA_MAPSTACK3)
-000450 f2ac .dw XT_DODO
- PFA_MAPSTACK1:
-000451 f2bd .dw XT_I
-000452 f370 .dw XT_FETCHE ; -- i*x XT id
-000453 f0d5 .dw XT_SWAP
-000454 f110 .dw XT_TO_R
-000455 f119 .dw XT_R_FETCH
-000456 f02f .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-000457 f0ca .dw XT_QDUP
-000458 f03e .dw XT_DOCONDBRANCH
-000459 045e DEST(PFA_MAPSTACK2)
-00045a f107 .dw XT_R_FROM
-00045b f0ea .dw XT_DROP
-00045c f2e5 .dw XT_UNLOOP
-00045d f025 .dw XT_EXIT
- PFA_MAPSTACK2:
-00045e f107 .dw XT_R_FROM
-00045f fdb6 .dw XT_TWO
-000460 f2cb .dw XT_DOPLUSLOOP
-000461 0451 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-000462 f0ea .dw XT_DROP
-000463 f165 .dw XT_ZERO
-000464 f025 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-000465 ff0b .dw $ff0b
-000466 6567
-000467 2d74
-000468 7563
-000469 7272
-00046a 6e65
-00046b 0074 .db "get-current",0
-00046c 043f .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-00046d f000 .dw DO_COLON
- PFA_GET_CURRENT:
-00046e f045 .dw XT_DOLITERAL
-00046f 0084 .dw CFG_CURRENT
-000470 f370 .dw XT_FETCHE
-000471 f025 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-000472 ff09 .dw $ff09
-000473 6567
-000474 2d74
-000475 726f
-000476 6564
-000477 0072 .db "get-order",0
-000478 0465 .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-000479 f000 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-00047a f045 .dw XT_DOLITERAL
-00047b 0088 .dw CFG_ORDERLISTLEN
-00047c 0407 .dw XT_GET_STACK
-00047d f025 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-00047e ff09 .dw $ff09
-00047f 6663
-000480 2d67
-000481 726f
-000482 6564
-000483 0072 .db "cfg-order",0
-000484 0472 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-000485 f053 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-000486 0088 .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-000487 ff07 .dw $ff07
-000488 6f63
-000489 706d
-00048a 7261
-00048b 0065 .db "compare",0
-00048c 047e .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-00048d 048e .dw PFA_COMPARE
- PFA_COMPARE:
-00048e 93bf push xh
-00048f 93af push xl
-000490 018c movw temp0, tosl
-000491 9189
-000492 9199 loadtos
-000493 01dc movw xl, tosl
-000494 9189
-000495 9199 loadtos
-000496 019c movw temp2, tosl
-000497 9189
-000498 9199 loadtos
-000499 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-00049a 90ed ld temp4, X+
-00049b 90f1 ld temp5, Z+
-00049c 14ef cp temp4, temp5
-00049d f451 brne PFA_COMPARE_NOTEQUAL
-00049e 950a dec temp0
-00049f f019 breq PFA_COMPARE_ENDREACHED2
-0004a0 952a dec temp2
-0004a1 f7c1 brne PFA_COMPARE_LOOP
-0004a2 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-0004a3 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-0004a4 2b02 or temp0, temp2
-0004a5 f411 brne PFA_COMPARE_CHECKLASTCHAR
-0004a6 2788 clr tosl
-0004a7 c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-0004a8 ef8f ser tosl
-0004a9 c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-0004aa 2f98 mov tosh, tosl
-0004ab 91af pop xl
-0004ac 91bf pop xh
-0004ad 940c f004 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-0004af ff07 .dw $ff07
-0004b0 666e
-0004b1 3e61
-0004b2 666c
-0004b3 0061 .db "nfa>lfa",0
-0004b4 0487 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-0004b5 f000 .dw DO_COLON
- PFA_NFA2LFA:
-0004b6 fc8c .dw XT_NAME2STRING
-0004b7 f240 .dw XT_1PLUS
-0004b8 f215 .dw XT_2SLASH
-0004b9 f1ae .dw XT_PLUS
-0004ba f025 .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 4000
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
-
- .include "dict/compiler2.inc" ; additional words for the compiler
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-0004bb ff0b .dw $ff0b
-0004bc 6573
-0004bd 2d74
-0004be 7563
-0004bf 7272
-0004c0 6e65
-0004c1 0074 .db "set-current",0
-0004c2 04af .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-0004c3 f000 .dw DO_COLON
- PFA_SET_CURRENT:
-0004c4 f045 .dw XT_DOLITERAL
-0004c5 0084 .dw CFG_CURRENT
-0004c6 f34c .dw XT_STOREE
-0004c7 f025 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-0004c8 ff08 .dw $ff08
-0004c9 6f77
-0004ca 6472
-0004cb 696c
-0004cc 7473 .db "wordlist"
-0004cd 04bb .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-0004ce f000 .dw DO_COLON
- PFA_WORDLIST:
-0004cf f5d1 .dw XT_EHERE
-0004d0 f165 .dw XT_ZERO
-0004d1 f0e0 .dw XT_OVER
-0004d2 f34c .dw XT_STOREE
-0004d3 f0c2 .dw XT_DUP
-0004d4 f578 .dw XT_CELLPLUS
-0004d5 fbb3 .dw XT_DOTO
-0004d6 f5d2 .dw PFA_EHERE
-0004d7 f025 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-0004d8 ff0e .dw $ff0e
-0004d9 6f66
-0004da 7472
-0004db 2d68
-0004dc 6f77
-0004dd 6472
-0004de 696c
-0004df 7473 .db "forth-wordlist"
-0004e0 04c8 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-0004e1 f053 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-0004e2 0086 .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-0004e3 ff09 .dw $ff09
-0004e4 6573
-0004e5 2d74
-0004e6 726f
-0004e7 6564
-0004e8 0072 .db "set-order",0
-0004e9 04d8 .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-0004ea f000 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-0004eb f045 .dw XT_DOLITERAL
-0004ec 0088 .dw CFG_ORDERLISTLEN
-0004ed 0428 .dw XT_SET_STACK
-0004ee f025 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-0004ef ff0f .dw $ff0f
-0004f0 6573
-0004f1 2d74
-0004f2 6572
-0004f3 6f63
-0004f4 6e67
-0004f5 7a69
-0004f6 7265
-0004f7 0073 .db "set-recognizers",0
-0004f8 04e3 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-0004f9 f000 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-0004fa f045 .dw XT_DOLITERAL
-0004fb 009a .dw CFG_RECOGNIZERLISTLEN
-0004fc 0428 .dw XT_SET_STACK
-0004fd f025 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-0004fe ff0f .dw $ff0f
-0004ff 6567
-000500 2d74
-000501 6572
-000502 6f63
-000503 6e67
-000504 7a69
-000505 7265
-000506 0073 .db "get-recognizers",0
-000507 04ef .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000508 f000 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000509 f045 .dw XT_DOLITERAL
-00050a 009a .dw CFG_RECOGNIZERLISTLEN
-00050b 0407 .dw XT_GET_STACK
-00050c f025 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-00050d ff04 .dw $ff04
-00050e 6f63
-00050f 6564 .db "code"
-000510 04fe .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000511 f000 .dw DO_COLON
- PFA_CODE:
-000512 01d8 .dw XT_DOCREATE
-000513 0338 .dw XT_REVEAL
-000514 f5c8 .dw XT_DP
-000515 fbc5 .dw XT_ICELLPLUS
-000516 0206 .dw XT_COMMA
-000517 f025 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000518 ff08 .dw $ff08
-000519 6e65
-00051a 2d64
-00051b 6f63
-00051c 6564 .db "end-code"
-00051d 050d .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-00051e f000 .dw DO_COLON
- PFA_ENDCODE:
-00051f 01fb .dw XT_COMPILE
-000520 940c .dw $940c
-000521 01fb .dw XT_COMPILE
-000522 f004 .dw DO_NEXT
-000523 f025 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000524 ff08 .dw $ff08
-000525 6d28
-000526 7261
-000527 656b
-000528 2972 .db "(marker)"
-000529 0518 .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-00052a f080 .dw PFA_DOVALUE1
- PFA_MARKER:
-00052b 00a6 .dw EE_MARKER
-00052c fbce .dw XT_EDEFERFETCH
-00052d fbd8 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-00052e 0008 .dw $0008
-00052f 6f70
-000530 7473
-000531 6f70
-000532 656e .db "postpone"
-000533 0524 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000534 f000 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000535 f9ce .dw XT_PARSENAME
-000536 fae6 .dw XT_FORTHRECOGNIZER
-000537 faf1 .dw XT_RECOGNIZE
-000538 f0c2 .dw XT_DUP
-000539 f110 .dw XT_TO_R
-00053a fbc5 .dw XT_ICELLPLUS
-00053b fbc5 .dw XT_ICELLPLUS
-00053c f3e2 .dw XT_FETCHI
-00053d f02f .dw XT_EXECUTE
-00053e f107 .dw XT_R_FROM
-00053f fbc5 .dw XT_ICELLPLUS
-000540 f3e2 .dw XT_FETCHI
-000541 0206 .dw XT_COMMA
-000542 f025 .dw XT_EXIT
- .endif
-
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000543 ff0b .dw $ff0b
-000544 7061
-000545 6c70
-000546 7574
-000547 6e72
-000548 656b
-000549 0079 .db "applturnkey",0
-00054a 052e .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-00054b f000 .dw DO_COLON
- PFA_APPLTURNKEY:
-00054c 0105 .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-00054d f493 .dw XT_INTON
- .endif
-
-00054e fb7e .dw XT_DOT_VER
-00054f f7fc .dw XT_SPACE
-000550 f787 .dw XT_DOSLITERAL
-000551 000a .dw 10
-000552 6f46
-000553 7472
-000554 6468
-000555 6975
-000556 6f6e .db "Forthduino"
-000557 f7ba .dw XT_ITYPE
-
-000558 f025 .dw XT_EXIT
-
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-00f000 93bf push XH
-00f001 93af push XL ; PUSH IP
-00f002 01db movw XL, wl
-00f003 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-00f004 14b2 cp isrflag, zerol
-00f005 f499 brne DO_INTERRUPT
- .endif
-00f006 01fd movw zl, XL ; READ IP
-00f007 2755
-00f008 0fee
-00f009 1fff
-00f00a 1f55
-00f00b bf5b
-00f00c 9167
-00f00d 9177 readflashcell wl, wh
-00f00e 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00f00f 01fb movw zl, wl
-00f010 2755
-00f011 0fee
-00f012 1fff
-00f013 1f55
-00f014 bf5b
-00f015 9107
-00f016 9117 readflashcell temp0,temp1
-00f017 01f8 movw zl, temp0
-00f018 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-00f019 939a
-00f01a 938a savetos
-00f01b 2d8b mov tosl, isrflag
-00f01c 2799 clr tosh
-00f01d 24bb clr isrflag
-00f01e eb6c ldi wl, LOW(XT_ISREXEC)
-00f01f ef74 ldi wh, HIGH(XT_ISREXEC)
-00f020 cfee rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00f021 ff04 .dw $ff04
-00f022 7865
-00f023 7469 .db "exit"
-00f024 0543 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-00f025 f026 .dw PFA_EXIT
- PFA_EXIT:
-00f026 91af pop XL
-00f027 91bf pop XH
-00f028 cfdb jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-00f029 ff07 .dw $ff07
-00f02a 7865
-00f02b 6365
-00f02c 7475
-00f02d 0065 .db "execute",0
-00f02e f021 .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-00f02f f030 .dw PFA_EXECUTE
- PFA_EXECUTE:
-00f030 01bc movw wl, tosl
-00f031 9189
-00f032 9199 loadtos
-00f033 cfdb jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00f034 f035 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-00f035 01fd movw zl, XL
-00f036 2755
-00f037 0fee
-00f038 1fff
-00f039 1f55
-00f03a bf5b
-00f03b 91a7
-00f03c 91b7 readflashcell XL,XH
-00f03d cfc6 jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-00f03e f03f .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-00f03f 2b98 or tosh, tosl
-00f040 9189
-00f041 9199 loadtos
-00f042 f391 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00f043 9611 adiw XL, 1
-00f044 cfbf jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00f045 f046 .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00f046 939a
-00f047 938a savetos
-00f048 01fd movw zl, xl
-00f049 2755
-00f04a 0fee
-00f04b 1fff
-00f04c 1f55
-00f04d bf5b
-00f04e 9187
-00f04f 9197 readflashcell tosl,tosh
-00f050 9611 adiw xl, 1
-00f051 cfb2 jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-00f052 f053 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-00f053 939a
-00f054 938a savetos
-00f055 01fb movw zl, wl
-00f056 9631 adiw zl,1
-00f057 2755
-00f058 0fee
-00f059 1fff
-00f05a 1f55
-00f05b bf5b
-00f05c 9187
-00f05d 9197 readflashcell tosl,tosh
-00f05e cfa5 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-00f05f f060 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-00f060 939a
-00f061 938a savetos
-00f062 01cb movw tosl, wl
-00f063 9601 adiw tosl, 1
-00f064 cf9f jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-00f065 f066 .dw PFA_DOUSER
- PFA_DOUSER:
-00f066 939a
-00f067 938a savetos
-00f068 01fb movw zl, wl
-00f069 9631 adiw zl, 1
-00f06a 2755
-00f06b 0fee
-00f06c 1fff
-00f06d 1f55
-00f06e bf5b
-00f06f 9187
-00f070 9197 readflashcell tosl,tosh
-00f071 0d84 add tosl, upl
-00f072 1d95 adc tosh, uph
-00f073 cf90 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-00f074 ff07 .dw $ff07
-00f075 7628
-00f076 6c61
-00f077 6575
-00f078 0029 .db "(value)", 0
-00f079 f029 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-00f07a f000 .dw DO_COLON
- PFA_DOVALUE:
-00f07b 01d8 .dw XT_DOCREATE
-00f07c 0338 .dw XT_REVEAL
-00f07d 01fb .dw XT_COMPILE
-00f07e f080 .dw PFA_DOVALUE1
-00f07f f025 .dw XT_EXIT
- PFA_DOVALUE1:
-00f080 940e 0351 call_ DO_DODOES
-00f082 f0c2 .dw XT_DUP
-00f083 fbc5 .dw XT_ICELLPLUS
-00f084 f3e2 .dw XT_FETCHI
-00f085 f02f .dw XT_EXECUTE
-00f086 f025 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-00f087 ff01 .dw $ff01
-00f088 0040 .db "@",0
-00f089 f074 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-00f08a f08b .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-00f08b 01fc movw zl, tosl
- ; low byte is read before the high byte
-00f08c 9181 ld tosl, z+
-00f08d 9191 ld tosh, z+
-00f08e cf75 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00f08f ff01 .dw $ff01
-00f090 0021 .db "!",0
-00f091 f087 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-00f092 f093 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-00f093 01fc movw zl, tosl
-00f094 9189
-00f095 9199 loadtos
- ; the high byte is written before the low byte
-00f096 8391 std Z+1, tosh
-00f097 8380 std Z+0, tosl
-00f098 9189
-00f099 9199 loadtos
-00f09a cf69 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-00f09b ff02 .dw $ff02
-00f09c 2163 .db "c!"
-00f09d f08f .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00f09e f09f .dw PFA_CSTORE
- PFA_CSTORE:
-00f09f 01fc movw zl, tosl
-00f0a0 9189
-00f0a1 9199 loadtos
-00f0a2 8380 st Z, tosl
-00f0a3 9189
-00f0a4 9199 loadtos
-00f0a5 cf5e jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-00f0a6 ff02 .dw $ff02
-00f0a7 4063 .db "c@"
-00f0a8 f09b .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-00f0a9 f0aa .dw PFA_CFETCH
- PFA_CFETCH:
-00f0aa 01fc movw zl, tosl
-00f0ab 2799 clr tosh
-00f0ac 8180 ld tosl, Z
-00f0ad cf56 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00f0ae ff02 .dw $ff02
-00f0af 7540 .db "@u"
-00f0b0 f0a6 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-00f0b1 f000 .dw DO_COLON
- PFA_FETCHU:
-00f0b2 f313 .dw XT_UP_FETCH
-00f0b3 f1ae .dw XT_PLUS
-00f0b4 f08a .dw XT_FETCH
-00f0b5 f025 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-00f0b6 ff02 .dw $ff02
-00f0b7 7521 .db "!u"
-00f0b8 f0ae .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-00f0b9 f000 .dw DO_COLON
- PFA_STOREU:
-00f0ba f313 .dw XT_UP_FETCH
-00f0bb f1ae .dw XT_PLUS
-00f0bc f092 .dw XT_STORE
-00f0bd f025 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-00f0be ff03 .dw $ff03
-00f0bf 7564
-00f0c0 0070 .db "dup",0
-00f0c1 f0b6 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-00f0c2 f0c3 .dw PFA_DUP
- PFA_DUP:
-00f0c3 939a
-00f0c4 938a savetos
-00f0c5 cf3e jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-00f0c6 ff04 .dw $ff04
-00f0c7 643f
-00f0c8 7075 .db "?dup"
-00f0c9 f0be .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-00f0ca f0cb .dw PFA_QDUP
- PFA_QDUP:
-00f0cb 2f08 mov temp0, tosl
-00f0cc 2b09 or temp0, tosh
-00f0cd f011 breq PFA_QDUP1
-00f0ce 939a
-00f0cf 938a savetos
- PFA_QDUP1:
-00f0d0 cf33 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-00f0d1 ff04 .dw $ff04
-00f0d2 7773
-00f0d3 7061 .db "swap"
-00f0d4 f0c6 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-00f0d5 f0d6 .dw PFA_SWAP
- PFA_SWAP:
-00f0d6 018c movw temp0, tosl
-00f0d7 9189
-00f0d8 9199 loadtos
-00f0d9 931a st -Y, temp1
-00f0da 930a st -Y, temp0
-00f0db cf28 jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-00f0dc ff04 .dw $ff04
-00f0dd 766f
-00f0de 7265 .db "over"
-00f0df f0d1 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-00f0e0 f0e1 .dw PFA_OVER
- PFA_OVER:
-00f0e1 939a
-00f0e2 938a savetos
-00f0e3 818a ldd tosl, Y+2
-00f0e4 819b ldd tosh, Y+3
-
-00f0e5 cf1e jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-00f0e6 ff04 .dw $ff04
-00f0e7 7264
-00f0e8 706f .db "drop"
-00f0e9 f0dc .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-00f0ea f0eb .dw PFA_DROP
- PFA_DROP:
-00f0eb 9189
-00f0ec 9199 loadtos
-00f0ed cf16 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-00f0ee ff03 .dw $ff03
-00f0ef 6f72
-00f0f0 0074 .db "rot",0
-00f0f1 f0e6 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-00f0f2 f0f3 .dw PFA_ROT
- PFA_ROT:
-00f0f3 018c movw temp0, tosl
-00f0f4 9129 ld temp2, Y+
-00f0f5 9139 ld temp3, Y+
-00f0f6 9189
-00f0f7 9199 loadtos
-
-00f0f8 933a st -Y, temp3
-00f0f9 932a st -Y, temp2
-00f0fa 931a st -Y, temp1
-00f0fb 930a st -Y, temp0
-
-00f0fc cf07 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-00f0fd ff03 .dw $ff03
-00f0fe 696e
-00f0ff 0070 .db "nip",0
-00f100 f0ee .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-00f101 f102 .dw PFA_NIP
- PFA_NIP:
-00f102 9622 adiw yl, 2
-00f103 cf00 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-00f104 ff02 .dw $ff02
-00f105 3e72 .db "r>"
-00f106 f0fd .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-00f107 f108 .dw PFA_R_FROM
- PFA_R_FROM:
-00f108 939a
-00f109 938a savetos
-00f10a 918f pop tosl
-00f10b 919f pop tosh
-00f10c cef7 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-00f10d ff02 .dw $ff02
-00f10e 723e .db ">r"
-00f10f f104 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-00f110 f111 .dw PFA_TO_R
- PFA_TO_R:
-00f111 939f push tosh
-00f112 938f push tosl
-00f113 9189
-00f114 9199 loadtos
-00f115 ceee jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-00f116 ff02 .dw $ff02
-00f117 4072 .db "r@"
-00f118 f10d .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-00f119 f11a .dw PFA_R_FETCH
- PFA_R_FETCH:
-00f11a 939a
-00f11b 938a savetos
-00f11c 918f pop tosl
-00f11d 919f pop tosh
-00f11e 939f push tosh
-00f11f 938f push tosl
-00f120 cee3 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-00f121 ff02 .dw $ff02
-00f122 3e3c .db "<>"
-00f123 f116 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-00f124 f000 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-00f125 fdaa
-00f126 f12b
-00f127 f025 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-00f128 ff02 .dw $ff02
-00f129 3d30 .db "0="
-00f12a f121 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-00f12b f12c .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00f12c 2b98 or tosh, tosl
-00f12d f5d1 brne PFA_ZERO1
-00f12e c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00f12f ff02 .dw $ff02
-00f130 3c30 .db "0<"
-00f131 f128 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-00f132 f133 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-00f133 fd97 sbrc tosh,7
-00f134 c02a rjmp PFA_TRUE1
-00f135 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-00f136 ff02 .dw $ff02
-00f137 3e30 .db "0>"
-00f138 f12f .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-00f139 f13a .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-00f13a 1582 cp tosl, zerol
-00f13b 0593 cpc tosh, zeroh
-00f13c f15c brlt PFA_ZERO1
-00f13d f151 brbs 1, PFA_ZERO1
-00f13e c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00f13f ff03 .dw $ff03
-00f140 3064
-00f141 003e .db "d0>",0
-00f142 f136 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-00f143 f144 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-00f144 1582 cp tosl, zerol
-00f145 0593 cpc tosh, zeroh
-00f146 9189
-00f147 9199 loadtos
-00f148 0582 cpc tosl, zerol
-00f149 0593 cpc tosh, zeroh
-00f14a f0ec brlt PFA_ZERO1
-00f14b f0e1 brbs 1, PFA_ZERO1
-00f14c c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00f14d ff03 .dw $ff03
-00f14e 3064
-00f14f 003c .db "d0<",0
-00f150 f13f .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-00f151 f152 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-00f152 9622 adiw Y,2
-00f153 fd97 sbrc tosh,7
-00f154 940c f15f jmp PFA_TRUE1
-00f156 940c f168 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-00f158 ff04 .dw $ff04
-00f159 7274
-00f15a 6575 .db "true"
-00f15b f14d .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00f15c f15d .dw PFA_TRUE
- PFA_TRUE:
-00f15d 939a
-00f15e 938a savetos
- PFA_TRUE1:
-00f15f ef8f ser tosl
-00f160 ef9f ser tosh
-00f161 cea2 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-00f162 ff01 .dw $ff01
-00f163 0030 .db "0",0
-00f164 f158 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-00f165 f166 .dw PFA_ZERO
- PFA_ZERO:
-00f166 939a
-00f167 938a savetos
- PFA_ZERO1:
-00f168 01c1 movw tosl, zerol
-00f169 ce9a jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-00f16a ff02 .dw $ff02
-00f16b 3c75 .db "u<"
-00f16c f162 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00f16d f16e .dw PFA_ULESS
- PFA_ULESS:
-00f16e 9129 ld temp2, Y+
-00f16f 9139 ld temp3, Y+
-00f170 1782 cp tosl, temp2
-00f171 0793 cpc tosh, temp3
-00f172 f3a8 brlo PFA_ZERO1
-00f173 f3a1 brbs 1, PFA_ZERO1
-00f174 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-00f175 ff02 .dw $ff02
-00f176 3e75 .db "u>"
-00f177 f16a .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-00f178 f000 .dw DO_COLON
- PFA_UGREATER:
- .endif
-00f179 f0d5 .DW XT_SWAP
-00f17a f16d .dw XT_ULESS
-00f17b f025 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00f17c ff01 .dw $ff01
-00f17d 003c .db "<",0
-00f17e f175 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00f17f f180 .dw PFA_LESS
- PFA_LESS:
-00f180 9129 ld temp2, Y+
-00f181 9139 ld temp3, Y+
-00f182 1728 cp temp2, tosl
-00f183 0739 cpc temp3, tosh
- PFA_LESSDONE:
-00f184 f71c brge PFA_ZERO1
-00f185 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-00f186 ff01 .dw $ff01
-00f187 003e .db ">",0
-00f188 f17c .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-00f189 f18a .dw PFA_GREATER
- PFA_GREATER:
-00f18a 9129 ld temp2, Y+
-00f18b 9139 ld temp3, Y+
-00f18c 1728 cp temp2, tosl
-00f18d 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00f18e f2cc brlt PFA_ZERO1
-00f18f f2c1 brbs 1, PFA_ZERO1
-00f190 cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-00f191 ff04 .dw $ff04
-00f192 6f6c
-00f193 3267 .db "log2"
-00f194 f186 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-00f195 f196 .dw PFA_LOG2
- PFA_LOG2:
-00f196 01fc movw zl, tosl
-00f197 2799 clr tosh
-00f198 e180 ldi tosl, 16
- PFA_LOG2_1:
-00f199 958a dec tosl
-00f19a f022 brmi PFA_LOG2_2 ; wrong data
-00f19b 0fee lsl zl
-00f19c 1fff rol zh
-00f19d f7d8 brcc PFA_LOG2_1
-00f19e ce65 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00f19f 959a dec tosh
-00f1a0 ce63 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-00f1a1 ff01 .dw $ff01
-00f1a2 002d .db "-",0
-00f1a3 f191 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-00f1a4 f1a5 .dw PFA_MINUS
- PFA_MINUS:
-00f1a5 9109 ld temp0, Y+
-00f1a6 9119 ld temp1, Y+
-00f1a7 1b08 sub temp0, tosl
-00f1a8 0b19 sbc temp1, tosh
-00f1a9 01c8 movw tosl, temp0
-00f1aa ce59 jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-00f1ab ff01 .dw $ff01
-00f1ac 002b .db "+",0
-00f1ad f1a1 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00f1ae f1af .dw PFA_PLUS
- PFA_PLUS:
-00f1af 9109 ld temp0, Y+
-00f1b0 9119 ld temp1, Y+
-00f1b1 0f80 add tosl, temp0
-00f1b2 1f91 adc tosh, temp1
-00f1b3 ce50 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-00f1b4 ff02 .dw $ff02
-00f1b5 2a6d .db "m*"
-00f1b6 f1ab .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-00f1b7 f1b8 .dw PFA_MSTAR
- PFA_MSTAR:
-00f1b8 018c movw temp0, tosl
-00f1b9 9189
-00f1ba 9199 loadtos
-00f1bb 019c movw temp2, tosl
- ; high cell ah*bh
-00f1bc 0231 muls temp3, temp1
-00f1bd 0170 movw temp4, r0
- ; low cell al*bl
-00f1be 9f20 mul temp2, temp0
-00f1bf 01c0 movw tosl, r0
- ; signed ah*bl
-00f1c0 0330 mulsu temp3, temp0
-00f1c1 08f3 sbc temp5, zeroh
-00f1c2 0d90 add tosh, r0
-00f1c3 1ce1 adc temp4, r1
-00f1c4 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-00f1c5 0312 mulsu temp1, temp2
-00f1c6 08f3 sbc temp5, zeroh
-00f1c7 0d90 add tosh, r0
-00f1c8 1ce1 adc temp4, r1
-00f1c9 1cf3 adc temp5, zeroh
-
-00f1ca 939a
-00f1cb 938a savetos
-00f1cc 01c7 movw tosl, temp4
-00f1cd ce36 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-00f1ce ff06 .dw $ff06
-00f1cf 6d75
-00f1d0 6d2f
-00f1d1 646f .db "um/mod"
-00f1d2 f1b4 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-00f1d3 f1d4 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-00f1d4 017c movw temp4, tosl
-
-00f1d5 9129 ld temp2, Y+
-00f1d6 9139 ld temp3, Y+
-
-00f1d7 9109 ld temp0, Y+
-00f1d8 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-00f1d9 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-00f1da 2755 clr temp7
-00f1db 0f00 lsl temp0
-00f1dc 1f11 rol temp1
-00f1dd 1f22 rol temp2
-00f1de 1f33 rol temp3
-00f1df 1f55 rol temp7
-
- ; try subtracting divisor
-00f1e0 152e cp temp2, temp4
-00f1e1 053f cpc temp3, temp5
-00f1e2 0552 cpc temp7,zerol
-
-00f1e3 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-00f1e4 9503 inc temp0
-00f1e5 192e sub temp2, temp4
-00f1e6 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-00f1e7 954a dec temp6
-00f1e8 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-00f1e9 933a st -Y,temp3
-00f1ea 932a st -Y,temp2
-
- ; put quotient on stack
-00f1eb 01c8 movw tosl, temp0
-00f1ec ce17 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-00f1ed ff03 .dw $ff03
-00f1ee 6d75
-00f1ef 002a .db "um*",0
-00f1f0 f1ce .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-00f1f1 f1f2 .dw PFA_UMSTAR
- PFA_UMSTAR:
-00f1f2 018c movw temp0, tosl
-00f1f3 9189
-00f1f4 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-00f1f5 9f80 mul tosl,temp0
-00f1f6 01f0 movw zl, r0
-00f1f7 2722 clr temp2
-00f1f8 2733 clr temp3
- ; middle bytes
-00f1f9 9f90 mul tosh, temp0
-00f1fa 0df0 add zh, r0
-00f1fb 1d21 adc temp2, r1
-00f1fc 1d33 adc temp3, zeroh
-
-00f1fd 9f81 mul tosl, temp1
-00f1fe 0df0 add zh, r0
-00f1ff 1d21 adc temp2, r1
-00f200 1d33 adc temp3, zeroh
-
-00f201 9f91 mul tosh, temp1
-00f202 0d20 add temp2, r0
-00f203 1d31 adc temp3, r1
-00f204 01cf movw tosl, zl
-00f205 939a
-00f206 938a savetos
-00f207 01c9 movw tosl, temp2
-00f208 cdfb jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-00f209 ff06 .dw $ff06
-00f20a 6e69
-00f20b 6576
-00f20c 7472 .db "invert"
-00f20d f1ed .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-00f20e f20f .dw PFA_INVERT
- PFA_INVERT:
-00f20f 9580 com tosl
-00f210 9590 com tosh
-00f211 cdf2 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-00f212 ff02 .dw $ff02
-00f213 2f32 .db "2/"
-00f214 f209 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-00f215 f216 .dw PFA_2SLASH
- PFA_2SLASH:
-00f216 9595 asr tosh
-00f217 9587 ror tosl
-00f218 cdeb jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-00f219 ff02 .dw $ff02
-00f21a 2a32 .db "2*"
-00f21b f212 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-00f21c f21d .dw PFA_2STAR
- PFA_2STAR:
-00f21d 0f88 lsl tosl
-00f21e 1f99 rol tosh
-00f21f cde4 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-00f220 ff03 .dw $ff03
-00f221 6e61
-00f222 0064 .db "and",0
-00f223 f219 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-00f224 f225 .dw PFA_AND
- PFA_AND:
-00f225 9109 ld temp0, Y+
-00f226 9119 ld temp1, Y+
-00f227 2380 and tosl, temp0
-00f228 2391 and tosh, temp1
-00f229 cdda jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-00f22a ff02 .dw $ff02
-00f22b 726f .db "or"
-00f22c f220 .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-00f22d f22e .dw PFA_OR
- PFA_OR:
-00f22e 9109 ld temp0, Y+
-00f22f 9119 ld temp1, Y+
-00f230 2b80 or tosl, temp0
-00f231 2b91 or tosh, temp1
-00f232 cdd1 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-00f233 ff03 .dw $ff03
-00f234 6f78
-00f235 0072 .db "xor",0
-00f236 f22a .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-00f237 f238 .dw PFA_XOR
- PFA_XOR:
-00f238 9109 ld temp0, Y+
-00f239 9119 ld temp1, Y+
-00f23a 2780 eor tosl, temp0
-00f23b 2791 eor tosh, temp1
-00f23c cdc7 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-00f23d ff02 .dw $ff02
-00f23e 2b31 .db "1+"
-00f23f f233 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-00f240 f241 .dw PFA_1PLUS
- PFA_1PLUS:
-00f241 9601 adiw tosl,1
-00f242 cdc1 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-00f243 ff02 .dw $ff02
-00f244 2d31 .db "1-"
-00f245 f23d .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-00f246 f247 .dw PFA_1MINUS
- PFA_1MINUS:
-00f247 9701 sbiw tosl, 1
-00f248 cdbb jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-00f249 ff07 .dw $ff07
-00f24a 6e3f
-00f24b 6765
-00f24c 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-00f24d 0065 .db "?negate"
-00f24e f243 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-00f24f f000 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-00f250 f132
-00f251 f03e .DW XT_ZEROLESS,XT_DOCONDBRANCH
-00f252 f254 DEST(QNEG1)
-00f253 f659 .DW XT_NEGATE
-00f254 f025 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-00f255 ff06 .dw $ff06
-00f256 736c
-00f257 6968
-00f258 7466 .db "lshift"
-00f259 f249 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-00f25a f25b .dw PFA_LSHIFT
- PFA_LSHIFT:
-00f25b 01fc movw zl, tosl
-00f25c 9189
-00f25d 9199 loadtos
- PFA_LSHIFT1:
-00f25e 9731 sbiw zl, 1
-00f25f f01a brmi PFA_LSHIFT2
-00f260 0f88 lsl tosl
-00f261 1f99 rol tosh
-00f262 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-00f263 cda0 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-00f264 ff06 .dw $ff06
-00f265 7372
-00f266 6968
-00f267 7466 .db "rshift"
-00f268 f255 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-00f269 f26a .dw PFA_RSHIFT
- PFA_RSHIFT:
-00f26a 01fc movw zl, tosl
-00f26b 9189
-00f26c 9199 loadtos
- PFA_RSHIFT1:
-00f26d 9731 sbiw zl, 1
-00f26e f01a brmi PFA_RSHIFT2
-00f26f 9596 lsr tosh
-00f270 9587 ror tosl
-00f271 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-00f272 cd91 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-00f273 ff02 .dw $ff02
-00f274 212b .db "+!"
-00f275 f264 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-00f276 f277 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-00f277 01fc movw zl, tosl
-00f278 9189
-00f279 9199 loadtos
-00f27a 8120 ldd temp2, Z+0
-00f27b 8131 ldd temp3, Z+1
-00f27c 0f82 add tosl, temp2
-00f27d 1f93 adc tosh, temp3
-00f27e 8380 std Z+0, tosl
-00f27f 8391 std Z+1, tosh
-00f280 9189
-00f281 9199 loadtos
-00f282 cd81 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-00f283 ff03 .dw $ff03
-00f284 7072
-00f285 0040 .db "rp@",0
-00f286 f273 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-00f287 f288 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-00f288 939a
-00f289 938a savetos
-00f28a b78d in tosl, SPL
-00f28b b79e in tosh, SPH
-00f28c cd77 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-00f28d ff03 .dw $ff03
-00f28e 7072
-00f28f 0021 .db "rp!",0
-00f290 f283 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-00f291 f292 .dw PFA_RP_STORE
- PFA_RP_STORE:
-00f292 b72f in temp2, SREG
-00f293 94f8 cli
-00f294 bf8d out SPL, tosl
-00f295 bf9e out SPH, tosh
-00f296 bf2f out SREG, temp2
-00f297 9189
-00f298 9199 loadtos
-00f299 cd6a jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-00f29a ff03 .dw $ff03
-00f29b 7073
-00f29c 0040 .db "sp@",0
-00f29d f28d .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-00f29e f29f .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-00f29f 939a
-00f2a0 938a savetos
-00f2a1 01ce movw tosl, yl
-00f2a2 cd61 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-00f2a3 ff03 .dw $ff03
-00f2a4 7073
-00f2a5 0021 .db "sp!",0
-00f2a6 f29a .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-00f2a7 f2a8 .dw PFA_SP_STORE
- PFA_SP_STORE:
-00f2a8 01ec movw yl, tosl
-00f2a9 9189
-00f2aa 9199 loadtos
-00f2ab cd58 jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-00f2ac f2ad .dw PFA_DODO
- PFA_DODO:
-00f2ad 9129 ld temp2, Y+
-00f2ae 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-00f2af e8e0 ldi zl, $80
-00f2b0 0f3e add temp3, zl
-00f2b1 1b82 sub tosl, temp2
-00f2b2 0b93 sbc tosh, temp3
-
-00f2b3 933f push temp3
-00f2b4 932f push temp2 ; limit ( --> limit + $8000)
-00f2b5 939f push tosh
-00f2b6 938f push tosl ; start -> index ( --> index - (limit - $8000)
-00f2b7 9189
-00f2b8 9199 loadtos
-00f2b9 cd4a jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-00f2ba ff01 .dw $FF01
-00f2bb 0069 .db "i",0
-00f2bc f2a3 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-00f2bd f2be .dw PFA_I
- PFA_I:
-00f2be 939a
-00f2bf 938a savetos
-00f2c0 918f pop tosl
-00f2c1 919f pop tosh ; index
-00f2c2 91ef pop zl
-00f2c3 91ff pop zh ; limit
-00f2c4 93ff push zh
-00f2c5 93ef push zl
-00f2c6 939f push tosh
-00f2c7 938f push tosl
-00f2c8 0f8e add tosl, zl
-00f2c9 1f9f adc tosh, zh
-00f2ca cd39 jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-00f2cb f2cc .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-00f2cc 91ef pop zl
-00f2cd 91ff pop zh
-00f2ce 0fe8 add zl, tosl
-00f2cf 1ff9 adc zh, tosh
-00f2d0 9189
-00f2d1 9199 loadtos
-00f2d2 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-00f2d3 93ff push zh
-00f2d4 93ef push zl
-00f2d5 cd5f rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-00f2d6 910f pop temp0
-00f2d7 911f pop temp1 ; remove limit
-00f2d8 9611 adiw xl, 1 ; skip branch-back address
-00f2d9 cd2a jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-00f2da f2db .dw PFA_DOLOOP
- PFA_DOLOOP:
-00f2db 91ef pop zl
-00f2dc 91ff pop zh
-00f2dd 9631 adiw zl,1
-00f2de f3bb brvs PFA_DOPLUSLOOP_LEAVE
-00f2df cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-00f2e0 ff06 .dw $ff06
-00f2e1 6e75
-00f2e2 6f6c
-00f2e3 706f .db "unloop"
-00f2e4 f2ba .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-00f2e5 f2e6 .dw PFA_UNLOOP
- PFA_UNLOOP:
-00f2e6 911f pop temp1
-00f2e7 910f pop temp0
-00f2e8 911f pop temp1
-00f2e9 910f pop temp0
-00f2ea cd19 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-00f2eb ff06 .dw $ff06
-00f2ec 6d63
-00f2ed 766f
-00f2ee 3e65 .db "cmove>"
-00f2ef f2e0 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-00f2f0 f2f1 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-00f2f1 93bf push xh
-00f2f2 93af push xl
-00f2f3 91e9 ld zl, Y+
-00f2f4 91f9 ld zh, Y+ ; addr-to
-00f2f5 91a9 ld xl, Y+
-00f2f6 91b9 ld xh, Y+ ; addr-from
-00f2f7 2f09 mov temp0, tosh
-00f2f8 2b08 or temp0, tosl
-00f2f9 f041 brbs 1, PFA_CMOVE_G1
-00f2fa 0fe8 add zl, tosl
-00f2fb 1ff9 adc zh, tosh
-00f2fc 0fa8 add xl, tosl
-00f2fd 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-00f2fe 911e ld temp1, -X
-00f2ff 9312 st -Z, temp1
-00f300 9701 sbiw tosl, 1
-00f301 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-00f302 91af pop xl
-00f303 91bf pop xh
-00f304 9189
-00f305 9199 loadtos
-00f306 ccfd jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-00f307 ff02 .dw $ff02
-00f308 3c3e .db "><"
-00f309 f2eb .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-00f30a f30b .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-00f30b 2f09 mov temp0, tosh
-00f30c 2f98 mov tosh, tosl
-00f30d 2f80 mov tosl, temp0
-00f30e ccf5 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-00f30f ff03 .dw $ff03
-00f310 7075
-00f311 0040 .db "up@",0
-00f312 f307 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-00f313 f314 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-00f314 939a
-00f315 938a savetos
-00f316 01c2 movw tosl, upl
-00f317 ccec jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-00f318 ff03 .dw $ff03
-00f319 7075
-00f31a 0021 .db "up!",0
-00f31b f30f .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-00f31c f31d .dw PFA_UP_STORE
- PFA_UP_STORE:
-00f31d 012c movw upl, tosl
-00f31e 9189
-00f31f 9199 loadtos
-00f320 cce3 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-00f321 ff03 .dw $ff03
-00f322 6d31
-00f323 0073 .db "1ms",0
-00f324 f318 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-00f325 f326 .dw PFA_1MS
- PFA_1MS:
-00f326 eae0
-00f327 e0ff
-00f328 9731
-00f329 f7f1 delay 1000
-00f32a ccd9 jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-00f32b ff03 .dw $ff03
-00f32c 3e32
-00f32d 0072 .db "2>r",0
-00f32e f321 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-00f32f f330 .dw PFA_2TO_R
- PFA_2TO_R:
-00f330 01fc movw zl, tosl
-00f331 9189
-00f332 9199 loadtos
-00f333 939f push tosh
-00f334 938f push tosl
-00f335 93ff push zh
-00f336 93ef push zl
-00f337 9189
-00f338 9199 loadtos
-00f339 ccca jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-00f33a ff03 .dw $ff03
-00f33b 7232
-00f33c 003e .db "2r>",0
-00f33d f32b .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-00f33e f33f .dw PFA_2R_FROM
- PFA_2R_FROM:
-00f33f 939a
-00f340 938a savetos
-00f341 91ef pop zl
-00f342 91ff pop zh
-00f343 918f pop tosl
-00f344 919f pop tosh
-00f345 939a
-00f346 938a savetos
-00f347 01cf movw tosl, zl
-00f348 ccbb jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-00f349 ff02 .dw $ff02
-00f34a 6521 .db "!e"
-00f34b f33a .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-00f34c f34d .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-00f34d 01fc movw zl, tosl
-00f34e 9189
-00f34f 9199 loadtos
-00f350 b72f in_ temp2, SREG
-00f351 94f8 cli
-00f352 d028 rcall PFA_FETCHE2
-00f353 b500 in_ temp0, EEDR
-00f354 1708 cp temp0,tosl
-00f355 f009 breq PFA_STOREE3
-00f356 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-00f357 9631 adiw zl,1
-00f358 d022 rcall PFA_FETCHE2
-00f359 b500 in_ temp0, EEDR
-00f35a 1709 cp temp0,tosh
-00f35b f011 breq PFA_STOREE4
-00f35c 2f89 mov tosl, tosh
-00f35d d004 rcall PFA_STOREE1
- PFA_STOREE4:
-00f35e bf2f out_ SREG, temp2
-00f35f 9189
-00f360 9199 loadtos
-00f361 cca2 jmp_ DO_NEXT
-
- PFA_STOREE1:
-00f362 99f9 sbic EECR, EEPE
-00f363 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-00f364 b707 in_ temp0, SPMCSR
-00f365 fd00 sbrc temp0,SPMEN
-00f366 cffd rjmp PFA_STOREE2
-
-00f367 bdf2 out_ EEARH,zh
-00f368 bde1 out_ EEARL,zl
-00f369 bd80 out_ EEDR, tosl
-00f36a 9afa sbi EECR,EEMPE
-00f36b 9af9 sbi EECR,EEPE
-
-00f36c 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-00f36d ff02 .dw $ff02
-00f36e 6540 .db "@e"
-00f36f f349 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-00f370 f371 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-00f371 b72f in_ temp2, SREG
-00f372 94f8 cli
-00f373 01fc movw zl, tosl
-00f374 d006 rcall PFA_FETCHE2
-00f375 b580 in_ tosl, EEDR
-
-00f376 9631 adiw zl,1
-
-00f377 d003 rcall PFA_FETCHE2
-00f378 b590 in_ tosh, EEDR
-00f379 bf2f out_ SREG, temp2
-00f37a cc89 jmp_ DO_NEXT
-
- PFA_FETCHE2:
-00f37b 99f9 sbic EECR, EEPE
-00f37c cffe rjmp PFA_FETCHE2
-
-00f37d bdf2 out_ EEARH,zh
-00f37e bde1 out_ EEARL,zl
-
-00f37f 9af8 sbi EECR,EERE
-00f380 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-00f381 ff02 .dw $ff02
-00f382 6921 .db "!i"
-00f383 f36d .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-00f384 fc2d .dw PFA_DODEFER1
- PFA_STOREI:
-00f385 00a4 .dw EE_STOREI
-00f386 fbce .dw XT_EDEFERFETCH
-00f387 fbd8 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-00f388 ff09 .dw $ff09
-00f389 2128
-00f38a 2d69
-00f38b 726e
-00f38c 7777
-00f38d 0029 .db "(!i-nrww)",0
-00f38e f381 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-00f38f f390 .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-00f390 b71f in temp1,SREG
-00f391 931f push temp1
-00f392 94f8 cli
-
-00f393 019c movw temp2, tosl ; save the (word) address
-00f394 9189
-00f395 9199 loadtos ; get the new value for the flash cell
-00f396 93af push xl
-00f397 93bf push xh
-00f398 93cf push yl
-00f399 93df push yh
-00f39a d009 rcall DO_STOREI_atmega
-00f39b 91df pop yh
-00f39c 91cf pop yl
-00f39d 91bf pop xh
-00f39e 91af pop xl
- ; finally clear the stack
-00f39f 9189
-00f3a0 9199 loadtos
-00f3a1 911f pop temp1
- ; restore status register (and interrupt enable flag)
-00f3a2 bf1f out SREG,temp1
-
-00f3a3 cc60 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-00f3a4 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-00f3a5 94e0 com temp4
-00f3a6 94f0 com temp5
-00f3a7 218e and tosl, temp4
-00f3a8 219f and tosh, temp5
-00f3a9 2b98 or tosh, tosl
-00f3aa f019 breq DO_STOREI_writepage
-00f3ab 01f9 movw zl, temp2
-00f3ac e002 ldi temp0,(1<<PGERS)
-00f3ad d023 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-00f3ae 01f9 movw zl, temp2
-00f3af e004 ldi temp0,(1<<PGWRT)
-00f3b0 d020 rcall dospm
-
- ; reenable RWW section
-00f3b1 01f9 movw zl, temp2
-00f3b2 e100 ldi temp0,(1<<RWWSRE)
-00f3b3 d01d rcall dospm
-00f3b4 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-00f3b5 01f9 movw zl, temp2
- ; get the beginning of page
-00f3b6 78e0 andi zl,low(pagemask)
-00f3b7 7fff andi zh,high(pagemask)
-00f3b8 01ef movw y, z
- ; loop counter (in words)
-00f3b9 e8a0 ldi xl,low(pagesize)
-00f3ba e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-00f3bb 01fe movw z, y
-00f3bc 2755
-00f3bd 0fee
-00f3be 1fff
-00f3bf 1f55
-00f3c0 bf5b
-00f3c1 9147
-00f3c2 9157 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-00f3c3 01fe movw z, y
-00f3c4 17e2 cp zl, temp2
-00f3c5 07f3 cpc zh, temp3
-00f3c6 f011 breq pageload_newdata
-00f3c7 010a movw r0, temp6
-00f3c8 c002 rjmp pageload_cont
- pageload_newdata:
-00f3c9 017a movw temp4, temp6
-00f3ca 010c movw r0, tosl
- pageload_cont:
-00f3cb 2700 clr temp0
-00f3cc d004 rcall dospm
-00f3cd 9621 adiw y, 1
-00f3ce 9711 sbiw x, 1
-00f3cf f759 brne pageload_loop
-
- pageload_done:
-00f3d0 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-00f3d1 99f9 sbic EECR, EEPE
-00f3d2 cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-00f3d3 b717 in_ temp1, SPMCSR
-00f3d4 fd10 sbrc temp1, SPMEN
-00f3d5 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-00f3d6 2755
-00f3d7 0fee
-00f3d8 1fff
-00f3d9 1f55
-00f3da bf5b writeflashcell
- ; execute spm
-00f3db 6001 ori temp0, (1<<SPMEN)
-00f3dc bf07 out_ SPMCSR,temp0
-00f3dd 95e8 spm
-00f3de 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-00f3df ff02 .dw $ff02
-00f3e0 6940 .db "@i"
-00f3e1 f388 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-00f3e2 f3e3 .dw PFA_FETCHI
- PFA_FETCHI:
-00f3e3 01fc movw zl, tosl
-00f3e4 2755
-00f3e5 0fee
-00f3e6 1fff
-00f3e7 1f55
-00f3e8 bf5b
-00f3e9 9187
-00f3ea 9197 readflashcell tosl,tosh
-00f3eb cc18 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .include "dict/core_8k.inc"
-
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-00f3ec ff03 .dw $ff03
-00f3ed 3e6e
-00f3ee 0072 .db "n>r",0
-00f3ef f3df .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-00f3f0 f3f1 .dw PFA_N_TO_R
- PFA_N_TO_R:
-00f3f1 01fc movw zl, tosl
-00f3f2 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-00f3f3 9189
-00f3f4 9199 loadtos
-00f3f5 939f push tosh
-00f3f6 938f push tosl
-00f3f7 950a dec temp0
-00f3f8 f7d1 brne PFA_N_TO_R1
-00f3f9 93ef push zl
-00f3fa 93ff push zh
-00f3fb 9189
-00f3fc 9199 loadtos
-00f3fd cc06 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-00f3fe ff03 .dw $ff03
-00f3ff 726e
-00f400 003e .db "nr>",0
-00f401 f3ec .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-00f402 f403 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-00f403 939a
-00f404 938a savetos
-00f405 91ff pop zh
-00f406 91ef pop zl
-00f407 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-00f408 918f pop tosl
-00f409 919f pop tosh
-00f40a 939a
-00f40b 938a savetos
-00f40c 950a dec temp0
-00f40d f7d1 brne PFA_N_R_FROM1
-00f40e 01cf movw tosl, zl
-00f40f cbf4 jmp_ DO_NEXT
-
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-00f410 ff03 .dw $ff03
-00f411 3264
-00f412 002a .db "d2*",0
-00f413 f3fe .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-00f414 f415 .dw PFA_D2STAR
- PFA_D2STAR:
-00f415 9109 ld temp0, Y+
-00f416 9119 ld temp1, Y+
-00f417 0f00 lsl temp0
-00f418 1f11 rol temp1
-00f419 1f88 rol tosl
-00f41a 1f99 rol tosh
-00f41b 931a st -Y, temp1
-00f41c 930a st -Y, temp0
-00f41d cbe6 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-00f41e ff03 .dw $ff03
-00f41f 3264
-00f420 002f .db "d2/",0
-00f421 f410 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-00f422 f423 .dw PFA_D2SLASH
- PFA_D2SLASH:
-00f423 9109 ld temp0, Y+
-00f424 9119 ld temp1, Y+
-00f425 9595 asr tosh
-00f426 9587 ror tosl
-00f427 9517 ror temp1
-00f428 9507 ror temp0
-00f429 931a st -Y, temp1
-00f42a 930a st -Y, temp0
-00f42b cbd8 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-00f42c ff02 .dw $ff02
-00f42d 2b64 .db "d+"
-00f42e f41e .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-00f42f f430 .dw PFA_DPLUS
- PFA_DPLUS:
-00f430 9129 ld temp2, Y+
-00f431 9139 ld temp3, Y+
-
-00f432 90e9 ld temp4, Y+
-00f433 90f9 ld temp5, Y+
-00f434 9149 ld temp6, Y+
-00f435 9159 ld temp7, Y+
-
-00f436 0f24 add temp2, temp6
-00f437 1f35 adc temp3, temp7
-00f438 1d8e adc tosl, temp4
-00f439 1d9f adc tosh, temp5
-
-00f43a 933a st -Y, temp3
-00f43b 932a st -Y, temp2
-00f43c cbc7 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-00f43d ff02 .dw $ff02
-00f43e 2d64 .db "d-"
-00f43f f42c .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-00f440 f441 .dw PFA_DMINUS
- PFA_DMINUS:
-00f441 9129 ld temp2, Y+
-00f442 9139 ld temp3, Y+
-
-00f443 90e9 ld temp4, Y+
-00f444 90f9 ld temp5, Y+
-00f445 9149 ld temp6, Y+
-00f446 9159 ld temp7, Y+
-
-00f447 1b42 sub temp6, temp2
-00f448 0b53 sbc temp7, temp3
-00f449 0ae8 sbc temp4, tosl
-00f44a 0af9 sbc temp5, tosh
-
-00f44b 935a st -Y, temp7
-00f44c 934a st -Y, temp6
-00f44d 01c7 movw tosl, temp4
-00f44e cbb5 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-00f44f ff07 .dw $ff07
-00f450 6964
-00f451 766e
-00f452 7265
-00f453 0074 .db "dinvert",0
-00f454 f43d .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-00f455 f456 .dw PFA_DINVERT
- PFA_DINVERT:
-00f456 9109 ld temp0, Y+
-00f457 9119 ld temp1, Y+
-00f458 9580 com tosl
-00f459 9590 com tosh
-00f45a 9500 com temp0
-00f45b 9510 com temp1
-00f45c 931a st -Y, temp1
-00f45d 930a st -Y, temp0
-00f45e cba5 jmp_ DO_NEXT
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-00f45f ff02 .dw $ff02
-00f460 2e75 .db "u."
-00f461 f44f .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-00f462 f000 .dw DO_COLON
- PFA_UDOT:
- .endif
-00f463 f165 .dw XT_ZERO
-00f464 f744 .dw XT_UDDOT
-00f465 f025 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-00f466 ff03 .dw $ff03
-00f467 2e75
-00f468 0072 .db "u.r",0
-00f469 f45f .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-00f46a f000 .dw DO_COLON
- PFA_UDOTR:
- .endif
-00f46b f165 .dw XT_ZERO
-00f46c f0d5 .dw XT_SWAP
-00f46d f74d .dw XT_UDDOTR
-00f46e f025 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-00f46f ff0d .dw $ff0d
-00f470 6873
-00f471 776f
-00f472 772d
-00f473 726f
-00f474 6c64
-00f475 7369
-00f476 0074 .db "show-wordlist",0
-00f477 f466 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-00f478 f000 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-00f479 f045 .dw XT_DOLITERAL
-00f47a f47e .dw XT_SHOWWORD
-00f47b f0d5 .dw XT_SWAP
-00f47c fc71 .dw XT_TRAVERSEWORDLIST
-00f47d f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-00f47e f000 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-00f47f fc8c .dw XT_NAME2STRING
-00f480 f7ba .dw XT_ITYPE
-00f481 f7fc .dw XT_SPACE ; ( -- addr n)
-00f482 f15c .dw XT_TRUE
-00f483 f025 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-00f484 ff05 .dw $ff05
-00f485 6f77
-00f486 6472
-00f487 0073 .db "words",0
-00f488 f46f .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-00f489 f000 .dw DO_COLON
- PFA_WORDS:
- .endif
-00f48a f045 .dw XT_DOLITERAL
-00f48b 008a .dw CFG_ORDERLISTLEN+2
-00f48c f370 .dw XT_FETCHE
-00f48d f478 .dw XT_SHOWWORDLIST
-00f48e f025 .dw XT_EXIT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-00f48f ff04 .dw $ff04
-00f490 692b
-00f491 746e .db "+int"
-00f492 f484 .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-00f493 f494 .dw PFA_INTON
- PFA_INTON:
-00f494 9478 sei
-00f495 cb6e jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-00f496 ff04 .dw $ff04
-00f497 692d
-00f498 746e .db "-int"
-00f499 f48f .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-00f49a f49b .dw PFA_INTOFF
- PFA_INTOFF:
-00f49b 94f8 cli
-00f49c cb67 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-00f49d ff04 .dw $ff04
-00f49e 6e69
-00f49f 2174 .db "int!"
-00f4a0 f496 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-00f4a1 f000 .dw DO_COLON
- PFA_INTSTORE:
-00f4a2 f045 .dw XT_DOLITERAL
-00f4a3 0000 .dw intvec
-00f4a4 f1ae .dw XT_PLUS
-00f4a5 f34c .dw XT_STOREE
-00f4a6 f025 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-00f4a7 ff04 .dw $ff04
-00f4a8 6e69
-00f4a9 4074 .db "int@"
-00f4aa f49d .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-00f4ab f000 .dw DO_COLON
- PFA_INTFETCH:
-00f4ac f045 .dw XT_DOLITERAL
-00f4ad 0000 .dw intvec
-00f4ae f1ae .dw XT_PLUS
-00f4af f370 .dw XT_FETCHE
-00f4b0 f025 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-00f4b1 ff08 .dw $ff08
-00f4b2 6e69
-00f4b3 2d74
-00f4b4 7274
-00f4b5 7061 .db "int-trap"
-00f4b6 f4a7 .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-00f4b7 f4b8 .dw PFA_INTTRAP
- PFA_INTTRAP:
-00f4b8 2eb8 mov isrflag, tosl
-00f4b9 9189
-00f4ba 9199 loadtos
-00f4bb cb48 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-00f4bc f000 .dw DO_COLON
- PFA_ISREXEC:
-00f4bd f4ab .dw XT_INTFETCH
-00f4be f02f .dw XT_EXECUTE
-00f4bf f4c1 .dw XT_ISREND
-00f4c0 f025 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-00f4c1 f4c2 .dw PFA_ISREND
- PFA_ISREND:
-00f4c2 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-00f4c3 cb40 jmp_ DO_NEXT
- PFA_ISREND1:
-00f4c4 9518 reti
- .endif
-
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-00f4c5 ff04 .dw $ff04
-00f4c6 6970
-00f4c7 6b63 .db "pick"
-00f4c8 f4b1 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-00f4c9 f000 .dw DO_COLON
- PFA_PICK:
- .endif
-00f4ca f240 .dw XT_1PLUS
-00f4cb f572 .dw XT_CELLS
-00f4cc f29e .dw XT_SP_FETCH
-00f4cd f1ae .dw XT_PLUS
-00f4ce f08a .dw XT_FETCH
-00f4cf f025 .dw XT_EXIT
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-00f4d0 0002 .dw $0002
-00f4d1 222e .db ".",$22
-00f4d2 f4c5 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-00f4d3 f000 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-00f4d4 f4db .dw XT_SQUOTE
-00f4d5 01fb .dw XT_COMPILE
-00f4d6 f7ba .dw XT_ITYPE
-00f4d7 f025 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-00f4d8 0002 .dw $0002
-00f4d9 2273 .db "s",$22
-00f4da f4d0 .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-00f4db f000 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-00f4dc f045 .dw XT_DOLITERAL
-00f4dd 0022 .dw 34 ; 0x22
-00f4de f9a1 .dw XT_PARSE ; ( -- addr n)
-00f4df f565 .dw XT_STATE
-00f4e0 f08a .dw XT_FETCH
-00f4e1 f03e .dw XT_DOCONDBRANCH
-00f4e2 f4e4 DEST(PFA_SQUOTE1)
-00f4e3 0227 .dw XT_SLITERAL
- PFA_SQUOTE1:
-00f4e4 f025 .dw XT_EXIT
-
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-00f4e5 ff04 .dw $ff04
-00f4e6 6966
-00f4e7 6c6c .db "fill"
-00f4e8 f4d8 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-00f4e9 f000 .dw DO_COLON
- PFA_FILL:
-00f4ea f0f2 .dw XT_ROT
-00f4eb f0f2 .dw XT_ROT
-00f4ec f0ca
-00f4ed f03e .dw XT_QDUP,XT_DOCONDBRANCH
-00f4ee f4f6 DEST(PFA_FILL2)
-00f4ef fd89 .dw XT_BOUNDS
-00f4f0 f2ac .dw XT_DODO
- PFA_FILL1:
-00f4f1 f0c2 .dw XT_DUP
-00f4f2 f2bd .dw XT_I
-00f4f3 f09e .dw XT_CSTORE ; ( -- c c-addr)
-00f4f4 f2da .dw XT_DOLOOP
-00f4f5 f4f1 .dw PFA_FILL1
- PFA_FILL2:
-00f4f6 f0ea .dw XT_DROP
-00f4f7 f025 .dw XT_EXIT
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-00f4f8 ff0b .dw $ff0b
-00f4f9 6e65
-00f4fa 6976
-00f4fb 6f72
-00f4fc 6d6e
-00f4fd 6e65
-00f4fe 0074 .db "environment",0
-00f4ff f4e5 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-00f500 f053 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-00f501 0082 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00f502 ff09 .dw $ff09
-00f503 6f77
-00f504 6472
-00f505 696c
-00f506 7473
-00f507 0073 .db "wordlists",0
-00f508 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-00f509 f000 .dw DO_COLON
- PFA_ENVWORDLISTS:
-00f50a f045 .dw XT_DOLITERAL
-00f50b 0008 .dw NUMWORDLISTS
-00f50c f025 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-00f50d ff04 .dw $ff04
-00f50e 702f
-00f50f 6461 .db "/pad"
-00f510 f502 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-00f511 f000 .dw DO_COLON
- PFA_ENVSLASHPAD:
-00f512 f29e .dw XT_SP_FETCH
-00f513 f59e .dw XT_PAD
-00f514 f1a4 .dw XT_MINUS
-00f515 f025 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-00f516 ff05 .dw $ff05
-00f517 682f
-00f518 6c6f
-00f519 0064 .db "/hold",0
-00f51a f50d .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-00f51b f000 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-00f51c f59e .dw XT_PAD
-00f51d f5d9 .dw XT_HERE
-00f51e f1a4 .dw XT_MINUS
-00f51f f025 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-00f520 ff0a .dw $ff0a
-00f521 6f66
-00f522 7472
-00f523 2d68
-00f524 616e
-00f525 656d .db "forth-name"
-00f526 f516 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-00f527 f000 .dw DO_COLON
- PFA_EN_FORTHNAME:
-00f528 f787 .dw XT_DOSLITERAL
-00f529 0007 .dw 7
- .endif
-00f52a 6d61
-00f52b 6f66
-00f52c 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-00f52d 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-00f52e f025 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-00f52f ff07 .dw $ff07
-00f530 6576
-00f531 7372
-00f532 6f69
-00f533 006e .db "version",0
-00f534 f520 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-00f535 f000 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-00f536 f045 .dw XT_DOLITERAL
-00f537 0041 .dw 65
-00f538 f025 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-00f539 ff03 .dw $ff03
-00f53a 7063
-00f53b 0075 .db "cpu",0
-00f53c f52f .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-00f53d f000 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-00f53e f045 .dw XT_DOLITERAL
-00f53f 0075 .dw mcu_name
-00f540 f7e6 .dw XT_ICOUNT
-00f541 f025 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-00f542 ff08 .dw $ff08
-00f543 636d
-00f544 2d75
-00f545 6e69
-00f546 6f66 .db "mcu-info"
-00f547 f539 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-00f548 f000 .dw DO_COLON
- PFA_EN_MCUINFO:
-00f549 f045 .dw XT_DOLITERAL
-00f54a 0071 .dw mcu_info
-00f54b f025 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-00f54c ff05 .dw $ff05
-00f54d 752f
-00f54e 6573
-00f54f 0072 .db "/user",0
-00f550 f542 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-00f551 f000 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-00f552 f045 .dw XT_DOLITERAL
-00f553 002c .dw SYSUSERSIZE + APPUSERSIZE
-00f554 f025 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-00f555 ff05 .dw $ff05
-00f556 5f66
-00f557 7063
-00f558 0075 .db "f_cpu",0
-00f559 f4f8 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-00f55a f000 .dw DO_COLON
- PFA_F_CPU:
- .endif
-00f55b f045 .dw XT_DOLITERAL
-00f55c 2400 .dw (F_CPU % 65536)
-00f55d f045 .dw XT_DOLITERAL
-00f55e 00f4 .dw (F_CPU / 65536)
-00f55f f025 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-00f560 ff05 .dw $ff05
-00f561 7473
-00f562 7461
-00f563 0065 .db "state",0
-00f564 f555 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-00f565 f053 .dw PFA_DOVARIABLE
- PFA_STATE:
-00f566 0253 .dw ram_state
-
- .dseg
-000253 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-00f567 ff04 .dw $ff04
-00f568 6162
-00f569 6573 .db "base"
-00f56a f560 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-00f56b f066 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-00f56c 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-00f56d ff05 .dw $ff05
-00f56e 6563
-00f56f 6c6c
-00f570 0073 .db "cells",0
-00f571 f567 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-00f572 f21d .dw PFA_2STAR
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-00f573 ff05 .dw $ff05
-00f574 6563
-00f575 6c6c
-00f576 002b .db "cell+",0
-00f577 f56d .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-00f578 f579 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-00f579 9602 adiw tosl, CELLSIZE
-00f57a ca89 jmp_ DO_NEXT
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-00f57b ff04 .dw $ff04
-00f57c 6432
-00f57d 7075 .db "2dup"
-00f57e f573 .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-00f57f f000 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-00f580 f0e0 .dw XT_OVER
-00f581 f0e0 .dw XT_OVER
-00f582 f025 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-00f583 ff05 .dw $ff05
-00f584 6432
-00f585 6f72
-00f586 0070 .db "2drop",0
-00f587 f57b .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-00f588 f000 .dw DO_COLON
- PFA_2DROP:
- .endif
-00f589 f0ea .dw XT_DROP
-00f58a f0ea .dw XT_DROP
-00f58b f025 .dw XT_EXIT
-
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-00f58c ff04 .dw $ff04
-00f58d 7574
-00f58e 6b63 .db "tuck"
-00f58f f583 .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-00f590 f000 .dw DO_COLON
- PFA_TUCK:
- .endif
-00f591 f0d5 .dw XT_SWAP
-00f592 f0e0 .dw XT_OVER
-00f593 f025 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-00f594 ff03 .dw $ff03
-00f595 693e
-00f596 006e .db ">in",0
-00f597 f58c .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-00f598 f066 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-00f599 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-00f59a ff03 .dw $ff03
-00f59b 6170
-00f59c 0064 .db "pad",0
-00f59d f594 .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-00f59e f000 .dw DO_COLON
- PFA_PAD:
- .endif
-00f59f f5d9 .dw XT_HERE
-00f5a0 f045 .dw XT_DOLITERAL
-00f5a1 0028 .dw 40
-00f5a2 f1ae .dw XT_PLUS
-00f5a3 f025 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-00f5a4 ff04 .dw $ff04
-00f5a5 6d65
-00f5a6 7469 .db "emit"
-00f5a7 f59a .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-00f5a8 fc2d .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-00f5a9 000e .dw USER_EMIT
-00f5aa fbf6 .dw XT_UDEFERFETCH
-00f5ab fc02 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-00f5ac ff05 .dw $ff05
-00f5ad 6d65
-00f5ae 7469
-00f5af 003f .db "emit?",0
-00f5b0 f5a4 .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-00f5b1 fc2d .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-00f5b2 0010 .dw USER_EMITQ
-00f5b3 fbf6 .dw XT_UDEFERFETCH
-00f5b4 fc02 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-00f5b5 ff03 .dw $ff03
-00f5b6 656b
-00f5b7 0079 .db "key",0
-00f5b8 f5ac .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-00f5b9 fc2d .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-00f5ba 0012 .dw USER_KEY
-00f5bb fbf6 .dw XT_UDEFERFETCH
-00f5bc fc02 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-00f5bd ff04 .dw $ff04
-00f5be 656b
-00f5bf 3f79 .db "key?"
-00f5c0 f5b5 .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-00f5c1 fc2d .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-00f5c2 0014 .dw USER_KEYQ
-00f5c3 fbf6 .dw XT_UDEFERFETCH
-00f5c4 fc02 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-00f5c5 ff02 .dw $ff02
-00f5c6 7064 .db "dp"
-00f5c7 f5bd .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-00f5c8 f080 .dw PFA_DOVALUE1
- PFA_DP:
-00f5c9 0074 .dw CFG_DP
-00f5ca fbce .dw XT_EDEFERFETCH
-00f5cb fbd8 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-00f5cc ff05 .dw $ff05
-00f5cd 6865
-00f5ce 7265
-00f5cf 0065 .db "ehere",0
-00f5d0 f5c5 .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-00f5d1 f080 .dw PFA_DOVALUE1
- PFA_EHERE:
-00f5d2 0078 .dw EE_EHERE
-00f5d3 fbce .dw XT_EDEFERFETCH
-00f5d4 fbd8 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-00f5d5 ff04 .dw $ff04
-00f5d6 6568
-00f5d7 6572 .db "here"
-00f5d8 f5cc .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-00f5d9 f080 .dw PFA_DOVALUE1
- PFA_HERE:
-00f5da 0076 .dw EE_HERE
-00f5db fbce .dw XT_EDEFERFETCH
-00f5dc fbd8 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-00f5dd ff05 .dw $ff05
-00f5de 6c61
-00f5df 6f6c
-00f5e0 0074 .db "allot",0
-00f5e1 f5d5 .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-00f5e2 f000 .dw DO_COLON
- PFA_ALLOT:
-00f5e3 f5d9 .dw XT_HERE
-00f5e4 f1ae .dw XT_PLUS
-00f5e5 fbb3 .dw XT_DOTO
-00f5e6 f5da .dw PFA_HERE
-00f5e7 f025 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-00f5e8 ff03 .dw $ff03
-00f5e9 6962
-00f5ea 006e .db "bin",0
-00f5eb f5dd .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-00f5ec f000 .dw DO_COLON
- PFA_BIN:
- .endif
-00f5ed fdb6 .dw XT_TWO
-00f5ee f56b .dw XT_BASE
-00f5ef f092 .dw XT_STORE
-00f5f0 f025 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-00f5f1 ff07 .dw $ff07
-00f5f2 6564
-00f5f3 6963
-00f5f4 616d
-00f5f5 006c .db "decimal",0
-00f5f6 f5e8 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-00f5f7 f000 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-00f5f8 f045 .dw XT_DOLITERAL
-00f5f9 000a .dw 10
-00f5fa f56b .dw XT_BASE
-00f5fb f092 .dw XT_STORE
-00f5fc f025 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-00f5fd ff03 .dw $ff03
-00f5fe 6568
-00f5ff 0078 .db "hex",0
-00f600 f5f1 .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-00f601 f000 .dw DO_COLON
- PFA_HEX:
- .endif
-00f602 f045 .dw XT_DOLITERAL
-00f603 0010 .dw 16
-00f604 f56b .dw XT_BASE
-00f605 f092 .dw XT_STORE
-00f606 f025 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-00f607 ff02 .dw $ff02
-00f608 6c62 .db "bl"
-00f609 f5fd .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-00f60a f053 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-00f60b 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-00f60c ff07 .dw $ff07
-00f60d 7574
-00f60e 6e72
-00f60f 656b
-00f610 0079 .db "turnkey",0
-00f611 f607 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-00f612 fc2d .dw PFA_DODEFER1
- PFA_TURNKEY:
-00f613 0080 .dw CFG_TURNKEY
-00f614 fbce .dw XT_EDEFERFETCH
-00f615 fbd8 .dw XT_EDEFERSTORE
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-00f616 ff04 .dw $ff04
-00f617 6d2f
-00f618 646f .db "/mod"
-00f619 f60c .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-00f61a f61b .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-00f61b 019c movw temp2, tosl
-
-00f61c 9109 ld temp0, Y+
-00f61d 9119 ld temp1, Y+
-
-00f61e 2f41 mov temp6,temp1 ;move dividend High to sign register
-00f61f 2743 eor temp6,temp3 ;xor divisor High with sign register
-00f620 ff17 sbrs temp1,7 ;if MSB in dividend set
-00f621 c004 rjmp PFA_SLASHMOD_1
-00f622 9510 com temp1 ; change sign of dividend
-00f623 9500 com temp0
-00f624 5f0f subi temp0,low(-1)
-00f625 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-00f626 ff37 sbrs temp3,7 ;if MSB in divisor set
-00f627 c004 rjmp PFA_SLASHMOD_2
-00f628 9530 com temp3 ; change sign of divisor
-00f629 9520 com temp2
-00f62a 5f2f subi temp2,low(-1)
-00f62b 4f3f sbci temp3,high(-1)
-00f62c 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-00f62d 18ff sub temp5,temp5;clear remainder High byte and carry
-00f62e e151 ldi temp7,17 ;init loop counter
-
-00f62f 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-00f630 1f11 rol temp1
-00f631 955a dec temp7 ;decrement counter
-00f632 f439 brne PFA_SLASHMOD_5 ;if done
-00f633 ff47 sbrs temp6,7 ; if MSB in sign register set
-00f634 c004 rjmp PFA_SLASHMOD_4
-00f635 9510 com temp1 ; change sign of result
-00f636 9500 com temp0
-00f637 5f0f subi temp0,low(-1)
-00f638 4f1f sbci temp1,high(-1)
-00f639 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-00f63a 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-00f63b 1cff rol temp5
-00f63c 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-00f63d 0af3 sbc temp5,temp3 ;
-00f63e f420 brcc PFA_SLASHMOD_6 ;if result negative
-00f63f 0ee2 add temp4,temp2 ; restore remainder
-00f640 1ef3 adc temp5,temp3
-00f641 9488 clc ; clear carry to be shifted into result
-00f642 cfec rjmp PFA_SLASHMOD_3 ;else
-00f643 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-00f644 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-00f645 92fa st -Y,temp5
-00f646 92ea st -Y,temp4
-
- ; put quotient on stack
-00f647 01c8 movw tosl, temp0
-00f648 c9bb jmp_ DO_NEXT
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-00f649 ff05 .dw $ff05
-00f64a 2f75
-00f64b 6f6d
-00f64c 0064 .db "u/mod",0
-00f64d f616 .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-00f64e f000 .dw DO_COLON
- PFA_USLASHMOD:
-00f64f f110 .dw XT_TO_R
-00f650 f165 .dw XT_ZERO
-00f651 f107 .dw XT_R_FROM
-00f652 f1d3 .dw XT_UMSLASHMOD
-00f653 f025 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-00f654 ff06 .dw $ff06
-00f655 656e
-00f656 6167
-00f657 6574 .db "negate"
-00f658 f649 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-00f659 f000 .dw DO_COLON
- PFA_NEGATE:
-00f65a f20e .dw XT_INVERT
-00f65b f240 .dw XT_1PLUS
-00f65c f025 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-00f65d ff01 .dw $ff01
-00f65e 002f .db "/",0
-00f65f f654 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-00f660 f000 .dw DO_COLON
- PFA_SLASH:
- .endif
-00f661 f61a .dw XT_SLASHMOD
-00f662 f101 .dw XT_NIP
-00f663 f025 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-00f664 ff03 .dw $ff03
-00f665 6f6d
-00f666 0064 .db "mod",0
-00f667 f65d .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-00f668 f000 .dw DO_COLON
- PFA_MOD:
- .endif
-00f669 f61a .dw XT_SLASHMOD
-00f66a f0ea .dw XT_DROP
-00f66b f025 .dw XT_EXIT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-00f66c ff03 .dw $ff03
-00f66d 6261
-00f66e 0073 .db "abs",0
-00f66f f664 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-00f670 f000 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-00f671 f0c2
-00f672 f24f
-00f673 f025 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-00f674 ff03 .dw $ff03
-00f675 696d
-00f676 006e .db "min",0
-00f677 f66c .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-00f678 f000 .dw DO_COLON
- PFA_MIN:
- .endif
-00f679 f57f .dw XT_2DUP
-00f67a f189 .dw XT_GREATER
-00f67b f03e .dw XT_DOCONDBRANCH
-00f67c f67e DEST(PFA_MIN1)
-00f67d f0d5 .dw XT_SWAP
- PFA_MIN1:
-00f67e f0ea .dw XT_DROP
-00f67f f025 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-00f680 ff03 .dw $ff03
-00f681 616d
-00f682 0078 .db "max",0
-00f683 f674 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-00f684 f000 .dw DO_COLON
- PFA_MAX:
-
- .endif
-00f685 f57f .dw XT_2DUP
-00f686 f17f .dw XT_LESS
-00f687 f03e .dw XT_DOCONDBRANCH
-00f688 f68a DEST(PFA_MAX1)
-00f689 f0d5 .dw XT_SWAP
- PFA_MAX1:
-00f68a f0ea .dw XT_DROP
-00f68b f025 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-00f68c ff06 .dw $ff06
-00f68d 6977
-00f68e 6874
-00f68f 6e69 .db "within"
-00f690 f680 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-00f691 f000 .dw DO_COLON
- PFA_WITHIN:
- .endif
-00f692 f0e0 .dw XT_OVER
-00f693 f1a4 .dw XT_MINUS
-00f694 f110 .dw XT_TO_R
-00f695 f1a4 .dw XT_MINUS
-00f696 f107 .dw XT_R_FROM
-00f697 f16d .dw XT_ULESS
-00f698 f025 .dw XT_EXIT
-
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-00f699 ff07 .dw $ff07
-00f69a 6f74
-00f69b 7075
-00f69c 6570
-00f69d 0072 .db "toupper",0
-00f69e f68c .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-00f69f f000 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-00f6a0 f0c2 .dw XT_DUP
-00f6a1 f045 .dw XT_DOLITERAL
-00f6a2 0061 .dw 'a'
-00f6a3 f045 .dw XT_DOLITERAL
-00f6a4 007b .dw 'z'+1
-00f6a5 f691 .dw XT_WITHIN
-00f6a6 f03e .dw XT_DOCONDBRANCH
-00f6a7 f6ab DEST(PFA_TOUPPER0)
-00f6a8 f045 .dw XT_DOLITERAL
-00f6a9 00df .dw 223 ; inverse of 0x20: 0xdf
-00f6aa f224 .dw XT_AND
- PFA_TOUPPER0:
-00f6ab f025 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-00f6ac ff07 .dw $ff07
-00f6ad 6f74
-00f6ae 6f6c
-00f6af 6577
-00f6b0 0072 .db "tolower",0
-00f6b1 f699 .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-00f6b2 f000 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-00f6b3 f0c2 .dw XT_DUP
-00f6b4 f045 .dw XT_DOLITERAL
-00f6b5 0041 .dw 'A'
-00f6b6 f045 .dw XT_DOLITERAL
-00f6b7 005b .dw 'Z'+1
-00f6b8 f691 .dw XT_WITHIN
-00f6b9 f03e .dw XT_DOCONDBRANCH
-00f6ba f6be DEST(PFA_TOLOWER0)
-00f6bb f045 .dw XT_DOLITERAL
-00f6bc 0020 .dw 32
-00f6bd f22d .dw XT_OR
- PFA_TOLOWER0:
-00f6be f025 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-00f6bf ff03 .dw $ff03
-00f6c0 6c68
-00f6c1 0064 .db "hld",0
-00f6c2 f6ac .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-00f6c3 f053 .dw PFA_DOVARIABLE
- PFA_HLD:
-00f6c4 0255 .dw ram_hld
-
- .dseg
-000255 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-00f6c5 ff04 .dw $ff04
-00f6c6 6f68
-00f6c7 646c .db "hold"
-00f6c8 f6bf .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-00f6c9 f000 .dw DO_COLON
- PFA_HOLD:
- .endif
-00f6ca f6c3 .dw XT_HLD
-00f6cb f0c2 .dw XT_DUP
-00f6cc f08a .dw XT_FETCH
-00f6cd f246 .dw XT_1MINUS
-00f6ce f0c2 .dw XT_DUP
-00f6cf f110 .dw XT_TO_R
-00f6d0 f0d5 .dw XT_SWAP
-00f6d1 f092 .dw XT_STORE
-00f6d2 f107 .dw XT_R_FROM
-00f6d3 f09e .dw XT_CSTORE
-00f6d4 f025 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-00f6d5 ff02 .dw $ff02
-00f6d6 233c .db "<#"
-00f6d7 f6c5 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-00f6d8 f000 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-00f6d9 f59e .dw XT_PAD
-00f6da f6c3 .dw XT_HLD
-00f6db f092 .dw XT_STORE
-00f6dc f025 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-00f6dd ff01 .dw $ff01
-00f6de 0023 .db "#",0
-00f6df f6d5 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-00f6e0 f000 .dw DO_COLON
- PFA_SHARP:
- .endif
-00f6e1 f56b .dw XT_BASE
-00f6e2 f08a .dw XT_FETCH
-00f6e3 f75d .dw XT_UDSLASHMOD
-00f6e4 f0f2 .dw XT_ROT
-00f6e5 f045 .dw XT_DOLITERAL
-00f6e6 0009 .dw 9
-00f6e7 f0e0 .dw XT_OVER
-00f6e8 f17f .dw XT_LESS
-00f6e9 f03e .dw XT_DOCONDBRANCH
-00f6ea f6ee DEST(PFA_SHARP1)
-00f6eb f045 .dw XT_DOLITERAL
-00f6ec 0007 .dw 7
-00f6ed f1ae .dw XT_PLUS
- PFA_SHARP1:
-00f6ee f045 .dw XT_DOLITERAL
-00f6ef 0030 .dw 48 ; ASCII 0
-00f6f0 f1ae .dw XT_PLUS
-00f6f1 f6c9 .dw XT_HOLD
-00f6f2 f025 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-00f6f3 ff02 .dw $ff02
-00f6f4 7323 .db "#s"
-00f6f5 f6dd .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-00f6f6 f000 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-00f6f7 f6e0 .dw XT_SHARP
-00f6f8 f57f .dw XT_2DUP
-00f6f9 f22d .dw XT_OR
-00f6fa f12b .dw XT_ZEROEQUAL
-00f6fb f03e .dw XT_DOCONDBRANCH
-00f6fc f6f7 DEST(NUMS1) ; PFA_SHARP_S
-00f6fd f025 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00f6fe ff02 .dw $ff02
-00f6ff 3e23 .db "#>"
-00f700 f6f3 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00f701 f000 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-00f702 f588 .dw XT_2DROP
-00f703 f6c3 .dw XT_HLD
-00f704 f08a .dw XT_FETCH
-00f705 f59e .dw XT_PAD
-00f706 f0e0 .dw XT_OVER
-00f707 f1a4 .dw XT_MINUS
-00f708 f025 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-00f709 ff04 .dw $ff04
-00f70a 6973
-00f70b 6e67 .db "sign"
-00f70c f6fe .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00f70d f000 .dw DO_COLON
- PFA_SIGN:
- .endif
-00f70e f132 .dw XT_ZEROLESS
-00f70f f03e .dw XT_DOCONDBRANCH
-00f710 f714 DEST(PFA_SIGN1)
-00f711 f045 .dw XT_DOLITERAL
-00f712 002d .dw 45 ; ascii -
-00f713 f6c9 .dw XT_HOLD
- PFA_SIGN1:
-00f714 f025 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-00f715 ff03 .dw $ff03
-00f716 2e64
-00f717 0072 .db "d.r",0
-00f718 f709 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-00f719 f000 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-00f71a f110 .dw XT_TO_R
-00f71b f590 .dw XT_TUCK
-00f71c fcff .dw XT_DABS
-00f71d f6d8 .dw XT_L_SHARP
-00f71e f6f6 .dw XT_SHARP_S
-00f71f f0f2 .dw XT_ROT
-00f720 f70d .dw XT_SIGN
-00f721 f701 .dw XT_SHARP_G
-00f722 f107 .dw XT_R_FROM
-00f723 f0e0 .dw XT_OVER
-00f724 f1a4 .dw XT_MINUS
-00f725 f805 .dw XT_SPACES
-00f726 f815 .dw XT_TYPE
-00f727 f025 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-00f728 ff02 .dw $ff02
-00f729 722e .db ".r"
-00f72a f715 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-00f72b f000 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-00f72c f110 .dw XT_TO_R
-00f72d fd92 .dw XT_S2D
-00f72e f107 .dw XT_R_FROM
-00f72f f719 .dw XT_DDOTR
-00f730 f025 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00f731 ff02 .dw $ff02
-00f732 2e64 .db "d."
-00f733 f728 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-00f734 f000 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-00f735 f165 .dw XT_ZERO
-00f736 f719 .dw XT_DDOTR
-00f737 f7fc .dw XT_SPACE
-00f738 f025 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-00f739 ff01 .dw $ff01
-00f73a 002e .db ".",0
-00f73b f731 .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-00f73c f000 .dw DO_COLON
- PFA_DOT:
- .endif
-00f73d fd92 .dw XT_S2D
-00f73e f734 .dw XT_DDOT
-00f73f f025 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-00f740 ff03 .dw $ff03
-00f741 6475
-00f742 002e .db "ud.",0
-00f743 f739 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-00f744 f000 .dw DO_COLON
- PFA_UDDOT:
- .endif
-00f745 f165 .dw XT_ZERO
-00f746 f74d .dw XT_UDDOTR
-00f747 f7fc .dw XT_SPACE
-00f748 f025 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-00f749 ff04 .dw $ff04
-00f74a 6475
-00f74b 722e .db "ud.r"
-00f74c f740 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-00f74d f000 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-00f74e f110 .dw XT_TO_R
-00f74f f6d8 .dw XT_L_SHARP
-00f750 f6f6 .dw XT_SHARP_S
-00f751 f701 .dw XT_SHARP_G
-00f752 f107 .dw XT_R_FROM
-00f753 f0e0 .dw XT_OVER
-00f754 f1a4 .dw XT_MINUS
-00f755 f805 .dw XT_SPACES
-00f756 f815 .dw XT_TYPE
-00f757 f025 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-00f758 ff06 .dw $ff06
-00f759 6475
-00f75a 6d2f
-00f75b 646f .db "ud/mod"
-00f75c f749 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-00f75d f000 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-00f75e f110 .dw XT_TO_R
-00f75f f165 .dw XT_ZERO
-00f760 f119 .dw XT_R_FETCH
-00f761 f1d3 .dw XT_UMSLASHMOD
-00f762 f107 .dw XT_R_FROM
-00f763 f0d5 .dw XT_SWAP
-00f764 f110 .dw XT_TO_R
-00f765 f1d3 .dw XT_UMSLASHMOD
-00f766 f107 .dw XT_R_FROM
-00f767 f025 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-00f768 ff06 .dw $ff06
-00f769 6964
-00f76a 6967
-00f76b 3f74 .db "digit?"
-00f76c f758 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-00f76d f000 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-00f76e f69f .dw XT_TOUPPER
-00f76f f0c2
-00f770 f045
-00f771 0039
-00f772 f189
-00f773 f045
-00f774 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-00f775 f224
-00f776 f1ae
-00f777 f0c2
-00f778 f045
-00f779 0140
-00f77a f189 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-00f77b f045
-00f77c 0107
-00f77d f224
-00f77e f1a4
-00f77f f045
-00f780 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-00f781 f1a4
-00f782 f0c2
-00f783 f56b
-00f784 f08a
-00f785 f16d .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-00f786 f025 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-00f787 f000 .dw DO_COLON
- PFA_DOSLITERAL:
-00f788 f119 .dw XT_R_FETCH ; ( -- addr )
-00f789 f7e6 .dw XT_ICOUNT
-00f78a f107 .dw XT_R_FROM
-00f78b f0e0 .dw XT_OVER ; ( -- addr' n addr n)
-00f78c f240 .dw XT_1PLUS
-00f78d f215 .dw XT_2SLASH ; ( -- addr' n addr k )
-00f78e f1ae .dw XT_PLUS ; ( -- addr' n addr'' )
-00f78f f240 .dw XT_1PLUS
-00f790 f110 .dw XT_TO_R ; ( -- )
-00f791 f025 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-00f792 ff02 .dw $ff02
-00f793 2c73 .db "s",$2c
-00f794 f768 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-00f795 f000 .dw DO_COLON
- PFA_SCOMMA:
-00f796 f0c2 .dw XT_DUP
-00f797 f799 .dw XT_DOSCOMMA
-00f798 f025 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-00f799 f000 .dw DO_COLON
- PFA_DOSCOMMA:
-00f79a 0206 .dw XT_COMMA
-00f79b f0c2 .dw XT_DUP ; ( --addr len len)
-00f79c f215 .dw XT_2SLASH ; ( -- addr len len/2
-00f79d f590 .dw XT_TUCK ; ( -- addr len/2 len len/2
-00f79e f21c .dw XT_2STAR ; ( -- addr len/2 len len'
-00f79f f1a4 .dw XT_MINUS ; ( -- addr len/2 rem
-00f7a0 f110 .dw XT_TO_R
-00f7a1 f165 .dw XT_ZERO
-00f7a2 02c5 .dw XT_QDOCHECK
-00f7a3 f03e .dw XT_DOCONDBRANCH
-00f7a4 f7ac .dw PFA_SCOMMA2
-00f7a5 f2ac .dw XT_DODO
- PFA_SCOMMA1:
-00f7a6 f0c2 .dw XT_DUP ; ( -- addr addr )
-00f7a7 f08a .dw XT_FETCH ; ( -- addr c1c2 )
-00f7a8 0206 .dw XT_COMMA ; ( -- addr )
-00f7a9 f578 .dw XT_CELLPLUS ; ( -- addr+cell )
-00f7aa f2da .dw XT_DOLOOP
-00f7ab f7a6 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-00f7ac f107 .dw XT_R_FROM
-00f7ad f139 .dw XT_GREATERZERO
-00f7ae f03e .dw XT_DOCONDBRANCH
-00f7af f7b3 .dw PFA_SCOMMA3
-00f7b0 f0c2 .dw XT_DUP ; well, tricky
-00f7b1 f0a9 .dw XT_CFETCH
-00f7b2 0206 .dw XT_COMMA
- PFA_SCOMMA3:
-00f7b3 f0ea .dw XT_DROP ; ( -- )
-00f7b4 f025 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-00f7b5 ff05 .dw $ff05
-00f7b6 7469
-00f7b7 7079
-00f7b8 0065 .db "itype",0
-00f7b9 f792 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-00f7ba f000 .dw DO_COLON
- PFA_ITYPE:
-00f7bb f0c2 .dw XT_DUP ; ( --addr len len)
-00f7bc f215 .dw XT_2SLASH ; ( -- addr len len/2
-00f7bd f590 .dw XT_TUCK ; ( -- addr len/2 len len/2
-00f7be f21c .dw XT_2STAR ; ( -- addr len/2 len len'
-00f7bf f1a4 .dw XT_MINUS ; ( -- addr len/2 rem
-00f7c0 f110 .dw XT_TO_R
-00f7c1 f165 .dw XT_ZERO
-00f7c2 02c5 .dw XT_QDOCHECK
-00f7c3 f03e .dw XT_DOCONDBRANCH
-00f7c4 f7ce .dw PFA_ITYPE2
-00f7c5 f2ac .dw XT_DODO
- PFA_ITYPE1:
-00f7c6 f0c2 .dw XT_DUP ; ( -- addr addr )
-00f7c7 f3e2 .dw XT_FETCHI ; ( -- addr c1c2 )
-00f7c8 f0c2 .dw XT_DUP
-00f7c9 f7db .dw XT_LOWEMIT
-00f7ca f7d7 .dw XT_HIEMIT
-00f7cb f240 .dw XT_1PLUS ; ( -- addr+cell )
-00f7cc f2da .dw XT_DOLOOP
-00f7cd f7c6 .dw PFA_ITYPE1
- PFA_ITYPE2:
-00f7ce f107 .dw XT_R_FROM
-00f7cf f139 .dw XT_GREATERZERO
-00f7d0 f03e .dw XT_DOCONDBRANCH
-00f7d1 f7d5 .dw PFA_ITYPE3
-00f7d2 f0c2 .dw XT_DUP ; make sure the drop below has always something to do
-00f7d3 f3e2 .dw XT_FETCHI
-00f7d4 f7db .dw XT_LOWEMIT
- PFA_ITYPE3:
-00f7d5 f0ea .dw XT_DROP
-00f7d6 f025 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-00f7d7 f000 .dw DO_COLON
- PFA_HIEMIT:
-00f7d8 f30a .dw XT_BYTESWAP
-00f7d9 f7db .dw XT_LOWEMIT
-00f7da f025 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-00f7db f000 .dw DO_COLON
- PFA_LOWEMIT:
-00f7dc f045 .dw XT_DOLITERAL
-00f7dd 00ff .dw $00ff
-00f7de f224 .dw XT_AND
-00f7df f5a8 .dw XT_EMIT
-00f7e0 f025 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00f7e1 ff06 .dw $ff06
-00f7e2 6369
-00f7e3 756f
-00f7e4 746e .db "icount"
-00f7e5 f7b5 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-00f7e6 f000 .dw DO_COLON
- PFA_ICOUNT:
-00f7e7 f0c2 .dw XT_DUP
-00f7e8 f240 .dw XT_1PLUS
-00f7e9 f0d5 .dw XT_SWAP
-00f7ea f3e2 .dw XT_FETCHI
-00f7eb f025 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-00f7ec ff02 .dw 0xff02
-00f7ed 7263 .db "cr"
-00f7ee f7e1 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-00f7ef f000 .dw DO_COLON
- PFA_CR:
- .endif
-
-00f7f0 f045 .dw XT_DOLITERAL
-00f7f1 000d .dw 13
-00f7f2 f5a8 .dw XT_EMIT
-00f7f3 f045 .dw XT_DOLITERAL
-00f7f4 000a .dw 10
-00f7f5 f5a8 .dw XT_EMIT
-00f7f6 f025 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-00f7f7 ff05 .dw $ff05
-00f7f8 7073
-00f7f9 6361
-00f7fa 0065 .db "space",0
-00f7fb f7ec .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-00f7fc f000 .dw DO_COLON
- PFA_SPACE:
- .endif
-00f7fd f60a .dw XT_BL
-00f7fe f5a8 .dw XT_EMIT
-00f7ff f025 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-00f800 ff06 .dw $ff06
-00f801 7073
-00f802 6361
-00f803 7365 .db "spaces"
-00f804 f7f7 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-00f805 f000 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-00f806 f165
-00f807 f684 .DW XT_ZERO, XT_MAX
-00f808 f0c2
-00f809 f03e SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-00f80a f80f DEST(SPCS2)
-00f80b f7fc
-00f80c f246
-00f80d f034 .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-00f80e f808 DEST(SPCS1)
-00f80f f0ea
-00f810 f025 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-00f811 ff04 .dw $ff04
-00f812 7974
-00f813 6570 .db "type"
-00f814 f800 .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-00f815 f000 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-00f816 fd89 .dw XT_BOUNDS
-00f817 02c5 .dw XT_QDOCHECK
-00f818 f03e .dw XT_DOCONDBRANCH
-00f819 f820 DEST(PFA_TYPE2)
-00f81a f2ac .dw XT_DODO
- PFA_TYPE1:
-00f81b f2bd .dw XT_I
-00f81c f0a9 .dw XT_CFETCH
-00f81d f5a8 .dw XT_EMIT
-00f81e f2da .dw XT_DOLOOP
-00f81f f81b DEST(PFA_TYPE1)
- PFA_TYPE2:
-00f820 f025 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00f821 ff01 .dw $ff01
-00f822 0027 .db "'",0
-00f823 f811 .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00f824 f000 .dw DO_COLON
- PFA_TICK:
- .endif
-00f825 f9ce .dw XT_PARSENAME
-00f826 fae6 .dw XT_FORTHRECOGNIZER
-00f827 faf1 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-00f828 f0c2 .dw XT_DUP
-00f829 fb64 .dw XT_DT_NULL
-00f82a fdaa .dw XT_EQUAL
-00f82b f0d5 .dw XT_SWAP
-00f82c f3e2 .dw XT_FETCHI
-00f82d f045 .dw XT_DOLITERAL
-00f82e fb99 .dw XT_NOOP
-00f82f fdaa .dw XT_EQUAL
-00f830 f22d .dw XT_OR
-00f831 f03e .dw XT_DOCONDBRANCH
-00f832 f836 DEST(PFA_TICK1)
-00f833 f045 .dw XT_DOLITERAL
-00f834 fff3 .dw -13
-00f835 f85b .dw XT_THROW
- PFA_TICK1:
-00f836 f0ea .dw XT_DROP
-00f837 f025 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-00f838 ff07 .dw $ff07
-00f839 6168
-00f83a 646e
-00f83b 656c
-00f83c 0072 .db "handler",0
-00f83d f821 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-00f83e f066 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-00f83f 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-00f840 ff05 .dw $ff05
-00f841 6163
-00f842 6374
-00f843 0068 .db "catch",0
-00f844 f838 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-00f845 f000 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-00f846 f29e .dw XT_SP_FETCH
-00f847 f110 .dw XT_TO_R
- ; handler @ >r
-00f848 f83e .dw XT_HANDLER
-00f849 f08a .dw XT_FETCH
-00f84a f110 .dw XT_TO_R
- ; rp@ handler !
-00f84b f287 .dw XT_RP_FETCH
-00f84c f83e .dw XT_HANDLER
-00f84d f092 .dw XT_STORE
-00f84e f02f .dw XT_EXECUTE
- ; r> handler !
-00f84f f107 .dw XT_R_FROM
-00f850 f83e .dw XT_HANDLER
-00f851 f092 .dw XT_STORE
-00f852 f107 .dw XT_R_FROM
-00f853 f0ea .dw XT_DROP
-00f854 f165 .dw XT_ZERO
-00f855 f025 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-00f856 ff05 .dw $ff05
-00f857 6874
-00f858 6f72
-00f859 0077 .db "throw",0
-00f85a f840 .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-00f85b f000 .dw DO_COLON
- PFA_THROW:
- .endif
-00f85c f0c2 .dw XT_DUP
-00f85d f12b .dw XT_ZEROEQUAL
-00f85e f03e .dw XT_DOCONDBRANCH
-00f85f f862 DEST(PFA_THROW1)
-00f860 f0ea .dw XT_DROP
-00f861 f025 .dw XT_EXIT
- PFA_THROW1:
-00f862 f83e .dw XT_HANDLER
-00f863 f08a .dw XT_FETCH
-00f864 f291 .dw XT_RP_STORE
-00f865 f107 .dw XT_R_FROM
-00f866 f83e .dw XT_HANDLER
-00f867 f092 .dw XT_STORE
-00f868 f107 .dw XT_R_FROM
-00f869 f0d5 .dw XT_SWAP
-00f86a f110 .dw XT_TO_R
-00f86b f2a7 .dw XT_SP_STORE
-00f86c f0ea .dw XT_DROP
-00f86d f107 .dw XT_R_FROM
-00f86e f025 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-00f86f ff05 .dw $ff05
-00f870 7363
-00f871 696b
-00f872 0070 .db "cskip",0
-00f873 f856 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-00f874 f000 .dw DO_COLON
- PFA_CSKIP:
- .endif
-00f875 f110 .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-00f876 f0c2 .dw XT_DUP ; ( -- addr' n' n' )
-00f877 f03e .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00f878 f883 DEST(PFA_CSKIP2)
-00f879 f0e0 .dw XT_OVER ; ( -- addr' n' addr' )
-00f87a f0a9 .dw XT_CFETCH ; ( -- addr' n' c' )
-00f87b f119 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-00f87c fdaa .dw XT_EQUAL ; ( -- addr' n' f )
-00f87d f03e .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00f87e f883 DEST(PFA_CSKIP2)
-00f87f fdb1 .dw XT_ONE
-00f880 f9bf .dw XT_SLASHSTRING
-00f881 f034 .dw XT_DOBRANCH
-00f882 f876 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-00f883 f107 .dw XT_R_FROM
-00f884 f0ea .dw XT_DROP ; ( -- addr2 n2)
-00f885 f025 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-00f886 ff05 .dw $ff05
-00f887 7363
-00f888 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00f889 006e .db "cscan"
-00f88a f86f .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-00f88b f000 .dw DO_COLON
- PFA_CSCAN:
- .endif
-00f88c f110 .dw XT_TO_R
-00f88d f0e0 .dw XT_OVER
- PFA_CSCAN1:
-00f88e f0c2 .dw XT_DUP
-00f88f f0a9 .dw XT_CFETCH
-00f890 f119 .dw XT_R_FETCH
-00f891 fdaa .dw XT_EQUAL
-00f892 f12b .dw XT_ZEROEQUAL
-00f893 f03e .dw XT_DOCONDBRANCH
-00f894 f8a0 DEST(PFA_CSCAN2)
-00f895 f0d5 .dw XT_SWAP
-00f896 f246 .dw XT_1MINUS
-00f897 f0d5 .dw XT_SWAP
-00f898 f0e0 .dw XT_OVER
-00f899 f132 .dw XT_ZEROLESS ; not negative
-00f89a f12b .dw XT_ZEROEQUAL
-00f89b f03e .dw XT_DOCONDBRANCH
-00f89c f8a0 DEST(PFA_CSCAN2)
-00f89d f240 .dw XT_1PLUS
-00f89e f034 .dw XT_DOBRANCH
-00f89f f88e DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-00f8a0 f101 .dw XT_NIP
-00f8a1 f0e0 .dw XT_OVER
-00f8a2 f1a4 .dw XT_MINUS
-00f8a3 f107 .dw XT_R_FROM
-00f8a4 f0ea .dw XT_DROP
-00f8a5 f025 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-00f8a6 ff06 .dw $ff06
-00f8a7 6361
-00f8a8 6563
-00f8a9 7470 .db "accept"
-00f8aa f886 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-00f8ab f000 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-00f8ac f0e0
-00f8ad f1ae
-00f8ae f246
-00f8af f0e0 .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-00f8b0 f5b9
-00f8b1 f0c2
-00f8b2 f8ec
-00f8b3 f12b
-00f8b4 f03e ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-00f8b5 f8de DEST(ACC5)
-00f8b6 f0c2
-00f8b7 f045
-00f8b8 0008
-00f8b9 fdaa
-00f8ba f03e .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-00f8bb f8ce DEST(ACC3)
-00f8bc f0ea
-00f8bd f0f2
-00f8be f57f
-00f8bf f189
-00f8c0 f110
-00f8c1 f0f2
-00f8c2 f0f2
-00f8c3 f107
-00f8c4 f03e .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-00f8c5 f8cc DEST(ACC6)
-00f8c6 f8e4
-00f8c7 f246
-00f8c8 f110
-00f8c9 f0e0
-00f8ca f107
-00f8cb 0198 .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-00f8cc f034 ACC6: .DW XT_DOBRANCH
-00f8cd f8dc DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-00f8ce f0c2 .dw XT_DUP ; ( -- addr k k )
-00f8cf f60a .dw XT_BL
-00f8d0 f17f .dw XT_LESS
-00f8d1 f03e .dw XT_DOCONDBRANCH
-00f8d2 f8d5 DEST(PFA_ACCEPT6)
-00f8d3 f0ea .dw XT_DROP
-00f8d4 f60a .dw XT_BL
- PFA_ACCEPT6:
-00f8d5 f0c2
-00f8d6 f5a8
-00f8d7 f0e0
-00f8d8 f09e
-00f8d9 f240
-00f8da f0e0
-00f8db 01a4 .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-00f8dc f034 ACC4: .DW XT_DOBRANCH
-00f8dd f8b0 DEST(ACC1)
-00f8de f0ea
-00f8df f101
-00f8e0 f0d5
-00f8e1 f1a4
-00f8e2 f7ef
-00f8e3 f025 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-00f8e4 f000 .dw DO_COLON
- .endif
-00f8e5 f045 .dw XT_DOLITERAL
-00f8e6 0008 .dw 8
-00f8e7 f0c2 .dw XT_DUP
-00f8e8 f5a8 .dw XT_EMIT
-00f8e9 f7fc .dw XT_SPACE
-00f8ea f5a8 .dw XT_EMIT
-00f8eb f025 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-00f8ec f000 .dw DO_COLON
- .endif
-00f8ed f0c2 .dw XT_DUP
-00f8ee f045 .dw XT_DOLITERAL
-00f8ef 000d .dw 13
-00f8f0 fdaa .dw XT_EQUAL
-00f8f1 f0d5 .dw XT_SWAP
-00f8f2 f045 .dw XT_DOLITERAL
-00f8f3 000a .dw 10
-00f8f4 fdaa .dw XT_EQUAL
-00f8f5 f22d .dw XT_OR
-00f8f6 f025 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-00f8f7 ff06 .dw $ff06
-00f8f8 6572
-00f8f9 6966
-00f8fa 6c6c .db "refill"
-00f8fb f8a6 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-00f8fc fc2d .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-00f8fd 001a .dw USER_REFILL
-00f8fe fbf6 .dw XT_UDEFERFETCH
-00f8ff fc02 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-00f900 ff04 .dw $ff04
-00f901 6863
-00f902 7261 .db "char"
-00f903 f8f7 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-00f904 f000 .dw DO_COLON
- PFA_CHAR:
- .endif
-00f905 f9ce .dw XT_PARSENAME
-00f906 f0ea .dw XT_DROP
-00f907 f0a9 .dw XT_CFETCH
-00f908 f025 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-00f909 ff06 .dw $ff06
-00f90a 756e
-00f90b 626d
-00f90c 7265 .db "number"
-00f90d f900 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-00f90e f000 .dw DO_COLON
- PFA_NUMBER:
- .endif
-00f90f f56b .dw XT_BASE
-00f910 f08a .dw XT_FETCH
-00f911 f110 .dw XT_TO_R
-00f912 f952 .dw XT_QSIGN
-00f913 f110 .dw XT_TO_R
-00f914 f965 .dw XT_SET_BASE
-00f915 f952 .dw XT_QSIGN
-00f916 f107 .dw XT_R_FROM
-00f917 f22d .dw XT_OR
-00f918 f110 .dw XT_TO_R
- ; check whether something is left
-00f919 f0c2 .dw XT_DUP
-00f91a f12b .dw XT_ZEROEQUAL
-00f91b f03e .dw XT_DOCONDBRANCH
-00f91c f925 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-00f91d f588 .dw XT_2DROP
-00f91e f107 .dw XT_R_FROM
-00f91f f0ea .dw XT_DROP
-00f920 f107 .dw XT_R_FROM
-00f921 f56b .dw XT_BASE
-00f922 f092 .dw XT_STORE
-00f923 f165 .dw XT_ZERO
-00f924 f025 .dw XT_EXIT
- PFA_NUMBER0:
-00f925 f32f .dw XT_2TO_R
-00f926 f165 .dw XT_ZERO ; starting value
-00f927 f165 .dw XT_ZERO
-00f928 f33e .dw XT_2R_FROM
-00f929 f983 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-00f92a f0ca .dw XT_QDUP
-00f92b f03e .dw XT_DOCONDBRANCH
-00f92c f947 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00f92d fdb1 .dw XT_ONE
-00f92e fdaa .dw XT_EQUAL
-00f92f f03e .dw XT_DOCONDBRANCH
-00f930 f93e DEST(PFA_NUMBER2)
- ; excatly one character is left
-00f931 f0a9 .dw XT_CFETCH
-00f932 f045 .dw XT_DOLITERAL
-00f933 002e .dw 46 ; .
-00f934 fdaa .dw XT_EQUAL
-00f935 f03e .dw XT_DOCONDBRANCH
-00f936 f93f DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-00f937 f107 .dw XT_R_FROM
-00f938 f03e .dw XT_DOCONDBRANCH
-00f939 f93b DEST(PFA_NUMBER3)
-00f93a fd0c .dw XT_DNEGATE
- PFA_NUMBER3:
-00f93b fdb6 .dw XT_TWO
-00f93c f034 .dw XT_DOBRANCH
-00f93d f94d DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-00f93e f0ea .dw XT_DROP
- PFA_NUMBER6:
-00f93f f588 .dw XT_2DROP
-00f940 f107 .dw XT_R_FROM
-00f941 f0ea .dw XT_DROP
-00f942 f107 .dw XT_R_FROM
-00f943 f56b .dw XT_BASE
-00f944 f092 .dw XT_STORE
-00f945 f165 .dw XT_ZERO
-00f946 f025 .dw XT_EXIT
- PFA_NUMBER1:
-00f947 f588 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-00f948 f107 .dw XT_R_FROM
-00f949 f03e .dw XT_DOCONDBRANCH
-00f94a f94c DEST(PFA_NUMBER4)
-00f94b f659 .dw XT_NEGATE
- PFA_NUMBER4:
-00f94c fdb1 .dw XT_ONE
- PFA_NUMBER5:
-00f94d f107 .dw XT_R_FROM
-00f94e f56b .dw XT_BASE
-00f94f f092 .dw XT_STORE
-00f950 f15c .dw XT_TRUE
-00f951 f025 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-00f952 f000 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-00f953 f0e0 .dw XT_OVER ; ( -- addr len addr )
-00f954 f0a9 .dw XT_CFETCH
-00f955 f045 .dw XT_DOLITERAL
-00f956 002d .dw '-'
-00f957 fdaa .dw XT_EQUAL ; ( -- addr len flag )
-00f958 f0c2 .dw XT_DUP
-00f959 f110 .dw XT_TO_R
-00f95a f03e .dw XT_DOCONDBRANCH
-00f95b f95e DEST(PFA_NUMBERSIGN_DONE)
-00f95c fdb1 .dw XT_ONE ; skip sign character
-00f95d f9bf .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-00f95e f107 .dw XT_R_FROM
-00f95f f025 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-00f960 f060 .dw PFA_DOCONSTANT
- .endif
-00f961 000a
-00f962 0010
-00f963 0002
-00f964 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-00f965 f000 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-00f966 f0e0 .dw XT_OVER
-00f967 f0a9 .dw XT_CFETCH
-00f968 f045 .dw XT_DOLITERAL
-00f969 0023 .dw 35
-00f96a f1a4 .dw XT_MINUS
-00f96b f0c2 .dw XT_DUP
-00f96c f165 .dw XT_ZERO
-00f96d f045 .dw XT_DOLITERAL
-00f96e 0004 .dw 4
-00f96f f691 .dw XT_WITHIN
-00f970 f03e .dw XT_DOCONDBRANCH
-00f971 f97b DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-00f972 f960 .dw XT_BASES
-00f973 f1ae .dw XT_PLUS
-00f974 f3e2 .dw XT_FETCHI
-00f975 f56b .dw XT_BASE
-00f976 f092 .dw XT_STORE
-00f977 fdb1 .dw XT_ONE
-00f978 f9bf .dw XT_SLASHSTRING
-00f979 f034 .dw XT_DOBRANCH
-00f97a f97c DEST(SET_BASE2)
- SET_BASE1:
-00f97b f0ea .dw XT_DROP
- SET_BASE2:
-00f97c f025 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00f97d ff07 .dw $ff07
-00f97e 6e3e
-00f97f 6d75
-00f980 6562
-00f981 0072 .db ">number",0
-00f982 f909 .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-00f983 f000 .dw DO_COLON
-
- .endif
-
-00f984 f0c2
-00f985 f03e TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-00f986 f99b DEST(TONUM3)
-00f987 f0e0
-00f988 f0a9
-00f989 f76d .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-00f98a f12b
-00f98b f03e .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-00f98c f98f DEST(TONUM2)
-00f98d f0ea
-00f98e f025 .DW XT_DROP,XT_EXIT
-00f98f f110
-00f990 fd30
-00f991 f56b
-00f992 f08a
-00f993 0189 TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-00f994 f107
-00f995 0181
-00f996 fd30 .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-00f997 fdb1
-00f998 f9bf
-00f999 f034 .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-00f99a f984 DEST(TONUM1)
-00f99b f025 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-00f99c ff05 .dw $ff05
-00f99d 6170
-00f99e 7372
-00f99f 0065 .db "parse",0
-00f9a0 f97d .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-00f9a1 f000 .dw DO_COLON
- PFA_PARSE:
- .endif
-00f9a2 f110 .dw XT_TO_R ; ( -- )
-00f9a3 f9b5 .dw XT_SOURCE ; ( -- addr len)
-00f9a4 f598 .dw XT_TO_IN ; ( -- addr len >in)
-00f9a5 f08a .dw XT_FETCH
-00f9a6 f9bf .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-00f9a7 f107 .dw XT_R_FROM ; ( -- addr' len' c)
-00f9a8 f88b .dw XT_CSCAN ; ( -- addr' len'')
-00f9a9 f0c2 .dw XT_DUP ; ( -- addr' len'' len'')
-00f9aa f240 .dw XT_1PLUS
-00f9ab f598 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-00f9ac f276 .dw XT_PLUSSTORE ; ( -- addr' len')
-00f9ad fdb1 .dw XT_ONE
-00f9ae f9bf .dw XT_SLASHSTRING
-00f9af f025 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-00f9b0 ff06 .dw $FF06
-00f9b1 6f73
-00f9b2 7275
-00f9b3 6563 .db "source"
-00f9b4 f99c .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-00f9b5 fc2d .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-00f9b6 0016 .dw USER_SOURCE
-00f9b7 fbf6 .dw XT_UDEFERFETCH
-00f9b8 fc02 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00f9b9 ff07 .dw $ff07
-00f9ba 732f
-00f9bb 7274
-00f9bc 6e69
-00f9bd 0067 .db "/string",0
-00f9be f9b0 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-00f9bf f000 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-00f9c0 f0f2 .dw XT_ROT
-00f9c1 f0e0 .dw XT_OVER
-00f9c2 f1ae .dw XT_PLUS
-00f9c3 f0f2 .dw XT_ROT
-00f9c4 f0f2 .dw XT_ROT
-00f9c5 f1a4 .dw XT_MINUS
-00f9c6 f025 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-00f9c7 ff0a .dw $FF0A
-00f9c8 6170
-00f9c9 7372
-00f9ca 2d65
-00f9cb 616e
-00f9cc 656d .db "parse-name"
-00f9cd f9b9 .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-00f9ce f000 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-00f9cf f60a .dw XT_BL
-00f9d0 f9d2 .dw XT_SKIPSCANCHAR
-00f9d1 f025 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-00f9d2 f000 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-00f9d3 f110 .dw XT_TO_R
-00f9d4 f9b5 .dw XT_SOURCE
-00f9d5 f598 .dw XT_TO_IN
-00f9d6 f08a .dw XT_FETCH
-00f9d7 f9bf .dw XT_SLASHSTRING
-
-00f9d8 f119 .dw XT_R_FETCH
-00f9d9 f874 .dw XT_CSKIP
-00f9da f107 .dw XT_R_FROM
-00f9db f88b .dw XT_CSCAN
-
- ; adjust >IN
-00f9dc f57f .dw XT_2DUP
-00f9dd f1ae .dw XT_PLUS
-00f9de f9b5 .dw XT_SOURCE
-00f9df f0ea .dw XT_DROP
-00f9e0 f1a4 .dw XT_MINUS
-00f9e1 f598 .dw XT_TO_IN
-00f9e2 f092 .dw XT_STORE
-00f9e3 f025 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-00f9e4 ff07 .dw $ff07
-00f9e5 6966
-00f9e6 646e
-00f9e7 782d
-00f9e8 0074 .db "find-xt",0
-00f9e9 f9c7 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-00f9ea f000 .dw DO_COLON
- PFA_FINDXT:
- .endif
-00f9eb f045 .dw XT_DOLITERAL
-00f9ec f9f6 .dw XT_FINDXTA
-00f9ed f045 .dw XT_DOLITERAL
-00f9ee 0088 .dw CFG_ORDERLISTLEN
-00f9ef 0446 .dw XT_MAPSTACK
-00f9f0 f12b .dw XT_ZEROEQUAL
-00f9f1 f03e .dw XT_DOCONDBRANCH
-00f9f2 f9f5 DEST(PFA_FINDXT1)
-00f9f3 f588 .dw XT_2DROP
-00f9f4 f165 .dw XT_ZERO
- PFA_FINDXT1:
-00f9f5 f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-00f9f6 f000 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-00f9f7 f110 .dw XT_TO_R
-00f9f8 f57f .dw XT_2DUP
-00f9f9 f107 .dw XT_R_FROM
-00f9fa fc3f .dw XT_SEARCH_WORDLIST
-00f9fb f0c2 .dw XT_DUP
-00f9fc f03e .dw XT_DOCONDBRANCH
-00f9fd fa03 DEST(PFA_FINDXTA1)
-00f9fe f110 .dw XT_TO_R
-00f9ff f101 .dw XT_NIP
-00fa00 f101 .dw XT_NIP
-00fa01 f107 .dw XT_R_FROM
-00fa02 f15c .dw XT_TRUE
- PFA_FINDXTA1:
-00fa03 f025 .dw XT_EXIT
-
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-00fa04 f000 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-00fa05 f787 .dw XT_DOSLITERAL
-00fa06 0003 .dw 3
-00fa07 6f20
-00fa08 006b .db " ok",0
- .endif
-00fa09 f7ba .dw XT_ITYPE
-00fa0a f025 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-00fa0b ff03 .dw $FF03
-00fa0c 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-00fa0d 006b .db ".ok"
-00fa0e f9e4 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-00fa0f fc2d .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-00fa10 001c .dw USER_P_OK
-00fa11 fbf6 .dw XT_UDEFERFETCH
-00fa12 fc02 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-00fa13 f000 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-00fa14 f787 .dw XT_DOSLITERAL
-00fa15 0002 .dw 2
-00fa16 203e .db "> "
- .endif
-00fa17 f7ef .dw XT_CR
-00fa18 f7ba .dw XT_ITYPE
-00fa19 f025 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-00fa1a ff06 .dw $FF06
-00fa1b 722e
-00fa1c 6165
-00fa1d 7964 .db ".ready"
-00fa1e fa0b .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-00fa1f fc2d .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-00fa20 0020 .dw USER_P_RDY
-00fa21 fbf6 .dw XT_UDEFERFETCH
-00fa22 fc02 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-00fa23 f000 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-00fa24 f787 .dw XT_DOSLITERAL
-00fa25 0004 .dw 4
-00fa26 3f20
-00fa27 203f .db " ?? "
- .endif
-00fa28 f7ba .dw XT_ITYPE
-00fa29 f56b .dw XT_BASE
-00fa2a f08a .dw XT_FETCH
-00fa2b f110 .dw XT_TO_R
-00fa2c f5f7 .dw XT_DECIMAL
-00fa2d f73c .dw XT_DOT
-00fa2e f598 .dw XT_TO_IN
-00fa2f f08a .dw XT_FETCH
-00fa30 f73c .dw XT_DOT
-00fa31 f107 .dw XT_R_FROM
-00fa32 f56b .dw XT_BASE
-00fa33 f092 .dw XT_STORE
-00fa34 f025 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-00fa35 ff06 .dw $FF06
-00fa36 652e
-00fa37 7272
-00fa38 726f .db ".error"
-00fa39 fa1a .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-00fa3a fc2d .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-00fa3b 001e .dw USER_P_ERR
-00fa3c fbf6 .dw XT_UDEFERFETCH
-00fa3d fc02 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-00fa3e ff04 .dw $ff04
-00fa3f 7571
-00fa40 7469 .db "quit"
-00fa41 fa35 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-00fa42 f000 .dw DO_COLON
- .endif
- PFA_QUIT:
-00fa43 02fb
-00fa44 0302
-00fa45 f092 .dw XT_LP0,XT_LP,XT_STORE
-00fa46 faa3 .dw XT_SP0
-00fa47 f2a7 .dw XT_SP_STORE
-00fa48 fab0 .dw XT_RP0
-00fa49 f291 .dw XT_RP_STORE
-00fa4a 0390 .dw XT_LBRACKET
-
- PFA_QUIT2:
-00fa4b f565 .dw XT_STATE
-00fa4c f08a .dw XT_FETCH
-00fa4d f12b .dw XT_ZEROEQUAL
-00fa4e f03e .dw XT_DOCONDBRANCH
-00fa4f fa51 DEST(PFA_QUIT4)
-00fa50 fa1f .dw XT_PROMPTREADY
- PFA_QUIT4:
-00fa51 f8fc .dw XT_REFILL
-00fa52 f03e .dw XT_DOCONDBRANCH
-00fa53 fa63 DEST(PFA_QUIT3)
-00fa54 f045 .dw XT_DOLITERAL
-00fa55 fac9 .dw XT_INTERPRET
-00fa56 f845 .dw XT_CATCH
-00fa57 f0ca .dw XT_QDUP
-00fa58 f03e .dw XT_DOCONDBRANCH
-00fa59 fa63 DEST(PFA_QUIT3)
-00fa5a f0c2 .dw XT_DUP
-00fa5b f045 .dw XT_DOLITERAL
-00fa5c fffe .dw -2
-00fa5d f17f .dw XT_LESS
-00fa5e f03e .dw XT_DOCONDBRANCH
-00fa5f fa61 DEST(PFA_QUIT5)
-00fa60 fa3a .dw XT_PROMPTERROR
- PFA_QUIT5:
-00fa61 f034 .dw XT_DOBRANCH
-00fa62 fa43 DEST(PFA_QUIT)
- PFA_QUIT3:
-00fa63 fa0f .dw XT_PROMPTOK
-00fa64 f034 .dw XT_DOBRANCH
-00fa65 fa4b DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-00fa66 ff05 .dw $ff05
-00fa67 6170
-00fa68 7375
-00fa69 0065 .db "pause",0
-00fa6a fa3e .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-00fa6b fc2d .dw PFA_DODEFER1
- PFA_PAUSE:
-00fa6c 0257 .dw ram_pause
-00fa6d fbe2 .dw XT_RDEFERFETCH
-00fa6e fbec .dw XT_RDEFERSTORE
-
- .dseg
-000257 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-00fa6f ff04 .dw $ff04
-00fa70 6f63
-00fa71 646c .db "cold"
-00fa72 fa66 .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-00fa73 fa74 .dw PFA_COLD
- PFA_COLD:
-00fa74 b6a4 in_ mcu_boot, MCUSR
-00fa75 2422 clr zerol
-00fa76 2433 clr zeroh
-00fa77 24bb clr isrflag
-00fa78 be24 out_ MCUSR, zerol
- ; clear RAM
-00fa79 e0e0 ldi zl, low(ramstart)
-00fa7a e0f2 ldi zh, high(ramstart)
- clearloop:
-00fa7b 9221 st Z+, zerol
-00fa7c 30e0 cpi zl, low(sram_size+ramstart)
-00fa7d f7e9 brne clearloop
-00fa7e 32f2 cpi zh, high(sram_size+ramstart)
-00fa7f f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000259 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-00fa80 e5e9 ldi zl, low(ram_user1)
-00fa81 e0f2 ldi zh, high(ram_user1)
-00fa82 012f movw upl, zl
- ; init return stack pointer
-00fa83 ef0f ldi temp0,low(rstackstart)
-00fa84 bf0d out_ SPL,temp0
-00fa85 8304 std Z+4, temp0
-00fa86 e211 ldi temp1,high(rstackstart)
-00fa87 bf1e out_ SPH,temp1
-00fa88 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-00fa89 eacf ldi yl,low(stackstart)
-00fa8a 83c6 std Z+6, yl
-00fa8b e2d1 ldi yh,high(stackstart)
-00fa8c 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-00fa8d e9a6 ldi XL, low(PFA_WARM)
-00fa8e efba ldi XH, high(PFA_WARM)
- ; its a far jump...
-00fa8f 940c f004 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-00fa91 ff04 .dw $ff04
-00fa92 6177
-00fa93 6d72 .db "warm"
-00fa94 fa6f .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-00fa95 f000 .dw DO_COLON
- PFA_WARM:
- .endif
-00fa96 fd7b .dw XT_INIT_RAM
-00fa97 f045 .dw XT_DOLITERAL
-00fa98 fb99 .dw XT_NOOP
-00fa99 f045 .dw XT_DOLITERAL
-00fa9a fa6b .dw XT_PAUSE
-00fa9b fc0d .dw XT_DEFERSTORE
-00fa9c 0390 .dw XT_LBRACKET
-00fa9d f612 .dw XT_TURNKEY
-00fa9e fa42 .dw XT_QUIT ; never returns
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-00fa9f ff03 .dw $ff03
-00faa0 7073
-00faa1 0030 .db "sp0",0
-00faa2 fa91 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-00faa3 f080 .dw PFA_DOVALUE1
- PFA_SP0:
-00faa4 0006 .dw USER_SP0
-00faa5 fbf6 .dw XT_UDEFERFETCH
-00faa6 fc02 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-00faa7 ff02 .dw $ff02
-00faa8 7073 .db "sp"
-00faa9 fa9f .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-00faaa f066 .dw PFA_DOUSER
- PFA_SP:
-00faab 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-00faac ff03 .dw $ff03
-00faad 7072
-00faae 0030 .db "rp0",0
-00faaf faa7 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-00fab0 f000 .dw DO_COLON
- PFA_RP0:
-00fab1 fab4 .dw XT_DORP0
-00fab2 f08a .dw XT_FETCH
-00fab3 f025 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-00fab4 f066 .dw PFA_DOUSER
- PFA_DORP0:
-00fab5 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-00fab6 ff05 .dw $ff05
-00fab7 6564
-00fab8 7470
-00fab9 0068 .db "depth",0
-00faba faac .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-00fabb f000 .dw DO_COLON
- PFA_DEPTH:
- .endif
-00fabc faa3 .dw XT_SP0
-00fabd f29e .dw XT_SP_FETCH
-00fabe f1a4 .dw XT_MINUS
-00fabf f215 .dw XT_2SLASH
-00fac0 f246 .dw XT_1MINUS
-00fac1 f025 .dw XT_EXIT
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-00fac2 ff09 .dw $ff09
-00fac3 6e69
-00fac4 6574
-00fac5 7072
-00fac6 6572
-00fac7 0074 .db "interpret",0
-00fac8 fab6 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-00fac9 f000 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-00faca f9ce .dw XT_PARSENAME ; ( -- addr len )
-00facb f0c2 .dw XT_DUP ; ( -- addr len flag)
-00facc f03e .dw XT_DOCONDBRANCH
-00facd fada DEST(PFA_INTERPRET2)
-00face fae6 .dw XT_FORTHRECOGNIZER
-00facf faf1 .dw XT_RECOGNIZE
-00fad0 f565 .dw XT_STATE
-00fad1 f08a .dw XT_FETCH
-00fad2 f03e .dw XT_DOCONDBRANCH
-00fad3 fad5 DEST(PFA_INTERPRET1)
-00fad4 fbc5 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-00fad5 f3e2 .dw XT_FETCHI
-00fad6 f02f .dw XT_EXECUTE
-00fad7 fb71 .dw XT_QSTACK
-00fad8 f034 .dw XT_DOBRANCH
-00fad9 faca DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-00fada f588 .dw XT_2DROP
-00fadb f025 .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-00fadc ff10 .dw $ff10
-00fadd 6f66
-00fade 7472
-00fadf 2d68
-00fae0 6572
-00fae1 6f63
-00fae2 6e67
-00fae3 7a69
-00fae4 7265 .db "forth-recognizer"
-00fae5 fac2 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-00fae6 f080 .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-00fae7 007c .dw CFG_FORTHRECOGNIZER
-00fae8 fbce .dw XT_EDEFERFETCH
-00fae9 fbd8 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-00faea ff09 .dw $ff09
-00faeb 6572
-00faec 6f63
-00faed 6e67
-00faee 7a69
-00faef 0065 .db "recognize",0
-00faf0 fadc .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-00faf1 f000 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-00faf2 f045 .dw XT_DOLITERAL
-00faf3 fafc .dw XT_RECOGNIZE_A
-00faf4 f0d5 .dw XT_SWAP
-00faf5 0446 .dw XT_MAPSTACK
-00faf6 f12b .dw XT_ZEROEQUAL
-00faf7 f03e .dw XT_DOCONDBRANCH
-00faf8 fafb DEST(PFA_RECOGNIZE1)
-00faf9 f588 .dw XT_2DROP
-00fafa fb64 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-00fafb f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-00fafc f000 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-00fafd f0f2 .dw XT_ROT ; -- len xt addr
-00fafe f0f2 .dw XT_ROT ; -- xt addr len
-00faff f57f .dw XT_2DUP
-00fb00 f32f .dw XT_2TO_R
-00fb01 f0f2 .dw XT_ROT ; -- addr len xt
-00fb02 f02f .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-00fb03 f33e .dw XT_2R_FROM
-00fb04 f0f2 .dw XT_ROT
-00fb05 f0c2 .dw XT_DUP
-00fb06 fb64 .dw XT_DT_NULL
-00fb07 fdaa .dw XT_EQUAL
-00fb08 f03e .dw XT_DOCONDBRANCH
-00fb09 fb0d DEST(PFA_RECOGNIZE_A1)
-00fb0a f0ea .dw XT_DROP
-00fb0b f165 .dw XT_ZERO
-00fb0c f025 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-00fb0d f101 .dw XT_NIP
-00fb0e f101 .dw XT_NIP
-00fb0f f15c .dw XT_TRUE
-00fb10 f025 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-00fb11 ff06 .dw $ff06
-00fb12 7464
-00fb13 6e3a
-00fb14 6d75 .db "dt:num"
-00fb15 faea .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-00fb16 f060 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-00fb17 fb99 .dw XT_NOOP ; interpret
-00fb18 021c .dw XT_LITERAL ; compile
-00fb19 021c .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-00fb1a ff07 .dw $ff07
-00fb1b 7464
-00fb1c 643a
-00fb1d 756e
-00fb1e 006d .db "dt:dnum",0
-00fb1f fb11 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-00fb20 f060 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-00fb21 fb99 .dw XT_NOOP ; interpret
-00fb22 fda2 .dw XT_2LITERAL ; compile
-00fb23 fda2 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-00fb24 ff07 .dw $ff07
-00fb25 6572
-00fb26 3a63
-00fb27 756e
-00fb28 006d .db "rec:num",0
-00fb29 fb1a .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-00fb2a f000 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-00fb2b f90e .dw XT_NUMBER
-00fb2c f03e .dw XT_DOCONDBRANCH
-00fb2d fb36 DEST(PFA_REC_NONUMBER)
-00fb2e fdb1 .dw XT_ONE
-00fb2f fdaa .dw XT_EQUAL
-00fb30 f03e .dw XT_DOCONDBRANCH
-00fb31 fb34 DEST(PFA_REC_INTNUM2)
-00fb32 fb16 .dw XT_DT_NUM
-00fb33 f025 .dw XT_EXIT
- PFA_REC_INTNUM2:
-00fb34 fb20 .dw XT_DT_DNUM
-00fb35 f025 .dw XT_EXIT
- PFA_REC_NONUMBER:
-00fb36 fb64 .dw XT_DT_NULL
-00fb37 f025 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00fb38 ff08 .dw $ff08
-00fb39 6572
-00fb3a 3a63
-00fb3b 6966
-00fb3c 646e .db "rec:find"
-00fb3d fb24 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-00fb3e f000 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-00fb3f f9ea .DW XT_FINDXT
-00fb40 f0c2 .dw XT_DUP
-00fb41 f12b .dw XT_ZEROEQUAL
-00fb42 f03e .dw XT_DOCONDBRANCH
-00fb43 fb47 DEST(PFA_REC_WORD_FOUND)
-00fb44 f0ea .dw XT_DROP
-00fb45 fb64 .dw XT_DT_NULL
-00fb46 f025 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-00fb47 fb4e .dw XT_DT_XT
-
-00fb48 f025 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-00fb49 ff05 .dw $ff05
-00fb4a 7464
-00fb4b 783a
-00fb4c 0074 .db "dt:xt",0
-00fb4d fb38 .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-00fb4e f060 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-00fb4f fb52 .dw XT_R_WORD_INTERPRET
-00fb50 fb56 .dw XT_R_WORD_COMPILE
-00fb51 fda2 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-00fb52 f000 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-00fb53 f0ea .dw XT_DROP ; the flags are in the way
-00fb54 f02f .dw XT_EXECUTE
-00fb55 f025 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-00fb56 f000 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-00fb57 f132 .dw XT_ZEROLESS
-00fb58 f03e .dw XT_DOCONDBRANCH
-00fb59 fb5c DEST(PFA_R_WORD_COMPILE1)
-00fb5a 0206 .dw XT_COMMA
-00fb5b f025 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-00fb5c f02f .dw XT_EXECUTE
-00fb5d f025 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-00fb5e ff07 .dw $ff07
-00fb5f 7464
-00fb60 6e3a
-00fb61 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-00fb62 006c .db "dt:null"
-00fb63 fb49 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-00fb64 f060 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-00fb65 fb68 .dw XT_FAIL ; interpret
-00fb66 fb68 .dw XT_FAIL ; compile
-00fb67 fb68 .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00fb68 f000 .dw DO_COLON
- PFA_FAIL:
- .endif
-00fb69 f045 .dw XT_DOLITERAL
-00fb6a fff3 .dw -13
-00fb6b f85b .dw XT_THROW
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-00fb6c ff06 .dw $ff06
-00fb6d 733f
-00fb6e 6174
-00fb6f 6b63 .db "?stack"
-00fb70 fb5e .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-00fb71 f000 .dw DO_COLON
- PFA_QSTACK:
- .endif
-00fb72 fabb .dw XT_DEPTH
-00fb73 f132 .dw XT_ZEROLESS
-00fb74 f03e .dw XT_DOCONDBRANCH
-00fb75 fb79 DEST(PFA_QSTACK1)
-00fb76 f045 .dw XT_DOLITERAL
-00fb77 fffc .dw -4
-00fb78 f85b .dw XT_THROW
- PFA_QSTACK1:
-00fb79 f025 .dw XT_EXIT
- .include "words/ver.asm"
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-00fb7a ff03 .dw $ff03
-00fb7b 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-00fb7c 0072 .db "ver"
-00fb7d fb6c .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00fb7e f000 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-00fb7f f527 .dw XT_ENV_FORTHNAME
-00fb80 f7ba .dw XT_ITYPE
-00fb81 f7fc .dw XT_SPACE
-00fb82 f56b .dw XT_BASE
-00fb83 f08a .dw XT_FETCH
-
-00fb84 f535 .dw XT_ENV_FORTHVERSION
-00fb85 f5f7 .dw XT_DECIMAL
-00fb86 fd92 .dw XT_S2D
-00fb87 f6d8 .dw XT_L_SHARP
-00fb88 f6e0 .dw XT_SHARP
-00fb89 f045 .dw XT_DOLITERAL
-00fb8a 002e .dw '.'
-00fb8b f6c9 .dw XT_HOLD
-00fb8c f6f6 .dw XT_SHARP_S
-00fb8d f701 .dw XT_SHARP_G
-00fb8e f815 .dw XT_TYPE
-00fb8f f56b .dw XT_BASE
-00fb90 f092 .dw XT_STORE
-00fb91 f7fc .dw XT_SPACE
-00fb92 f53d .dw XT_ENV_CPU
-00fb93 f7ba .dw XT_ITYPE
-
-00fb94 f025 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-00fb95 ff04 .dw $ff04
-00fb96 6f6e
-00fb97 706f .db "noop"
-00fb98 fb7a .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-00fb99 f000 .dw DO_COLON
- PFA_NOOP:
- .endif
-00fb9a f025 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-00fb9b ff06 .dw $ff06
-00fb9c 6e75
-00fb9d 7375
-00fb9e 6465 .db "unused"
-00fb9f fb95 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-00fba0 f000 .dw DO_COLON
- PFA_UNUSED:
-00fba1 f29e .dw XT_SP_FETCH
-00fba2 f5d9 .dw XT_HERE
-00fba3 f1a4 .dw XT_MINUS
-00fba4 f025 .dw XT_EXIT
-
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-00fba5 0002 .dw $0002
-00fba6 6f74 .db "to"
-00fba7 fb9b .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-00fba8 f000 .dw DO_COLON
- PFA_TO:
- .endif
-00fba9 f824 .dw XT_TICK
-00fbaa fd9b .dw XT_TO_BODY
-00fbab f565 .dw XT_STATE
-00fbac f08a .dw XT_FETCH
-00fbad f03e .dw XT_DOCONDBRANCH
-00fbae fbb9 DEST(PFA_TO1)
-00fbaf 01fb .dw XT_COMPILE
-00fbb0 fbb3 .dw XT_DOTO
-00fbb1 0206 .dw XT_COMMA
-00fbb2 f025 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-00fbb3 f000 .dw DO_COLON
- PFA_DOTO:
- .endif
-00fbb4 f107 .dw XT_R_FROM
-00fbb5 f0c2 .dw XT_DUP
-00fbb6 fbc5 .dw XT_ICELLPLUS
-00fbb7 f110 .dw XT_TO_R
-00fbb8 f3e2 .dw XT_FETCHI
- PFA_TO1:
-00fbb9 f0c2 .dw XT_DUP
-00fbba fbc5 .dw XT_ICELLPLUS
-00fbbb fbc5 .dw XT_ICELLPLUS
-00fbbc f3e2 .dw XT_FETCHI
-00fbbd f02f .dw XT_EXECUTE
-00fbbe f025 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-00fbbf ff07 .dw $FF07
-00fbc0 2d69
-00fbc1 6563
-00fbc2 6c6c
-00fbc3 002b .db "i-cell+",0
-00fbc4 fba5 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-00fbc5 f000 .dw DO_COLON
- PFA_ICELLPLUS:
-00fbc6 f240 .dw XT_1PLUS
-00fbc7 f025 .dw XT_EXIT
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-00fbc8 ff07 .dw $ff07
-00fbc9 6445
-00fbca 6665
-00fbcb 7265
-00fbcc 0040 .db "Edefer@",0
-00fbcd fbbf .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-00fbce f000 .dw DO_COLON
- PFA_EDEFERFETCH:
-00fbcf f3e2 .dw XT_FETCHI
-00fbd0 f370 .dw XT_FETCHE
-00fbd1 f025 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-00fbd2 ff07 .dw $ff07
-00fbd3 6445
-00fbd4 6665
-00fbd5 7265
-00fbd6 0021 .db "Edefer!",0
-00fbd7 fbc8 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-00fbd8 f000 .dw DO_COLON
- PFA_EDEFERSTORE:
-00fbd9 f3e2 .dw XT_FETCHI
-00fbda f34c .dw XT_STOREE
-00fbdb f025 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-00fbdc ff07 .dw $ff07
-00fbdd 6452
-00fbde 6665
-00fbdf 7265
-00fbe0 0040 .db "Rdefer@",0
-00fbe1 fbd2 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-00fbe2 f000 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-00fbe3 f3e2 .dw XT_FETCHI
-00fbe4 f08a .dw XT_FETCH
-00fbe5 f025 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-00fbe6 ff07 .dw $ff07
-00fbe7 6452
-00fbe8 6665
-00fbe9 7265
-00fbea 0021 .db "Rdefer!",0
-00fbeb fbdc .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-00fbec f000 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-00fbed f3e2 .dw XT_FETCHI
-00fbee f092 .dw XT_STORE
-00fbef f025 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-00fbf0 ff07 .dw $ff07
-00fbf1 6455
-00fbf2 6665
-00fbf3 7265
-00fbf4 0040 .db "Udefer@",0
-00fbf5 fbe6 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-00fbf6 f000 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-00fbf7 f3e2 .dw XT_FETCHI
-00fbf8 f313 .dw XT_UP_FETCH
-00fbf9 f1ae .dw XT_PLUS
-00fbfa f08a .dw XT_FETCH
-00fbfb f025 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-00fbfc ff07 .dw $ff07
-00fbfd 6455
-00fbfe 6665
-00fbff 7265
-00fc00 0021 .db "Udefer!",0
-00fc01 fbf0 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-00fc02 f000 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-00fc03 f3e2 .dw XT_FETCHI
-00fc04 f313 .dw XT_UP_FETCH
-00fc05 f1ae .dw XT_PLUS
-00fc06 f092 .dw XT_STORE
-00fc07 f025 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-00fc08 ff06 .dw $ff06
-00fc09 6564
-00fc0a 6566
-00fc0b 2172 .db "defer!"
-00fc0c fbfc .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-00fc0d f000 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-00fc0e fd9b .dw XT_TO_BODY
-00fc0f f0c2 .dw XT_DUP
-00fc10 fbc5 .dw XT_ICELLPLUS
-00fc11 fbc5 .dw XT_ICELLPLUS
-00fc12 f3e2 .dw XT_FETCHI
-00fc13 f02f .dw XT_EXECUTE
-00fc14 f025 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-00fc15 ff06 .dw $ff06
-00fc16 6564
-00fc17 6566
-00fc18 4072 .db "defer@"
-00fc19 fc08 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-00fc1a f000 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-00fc1b fd9b .dw XT_TO_BODY
-00fc1c f0c2 .dw XT_DUP
-00fc1d fbc5 .dw XT_ICELLPLUS
-00fc1e f3e2 .dw XT_FETCHI
-00fc1f f02f .dw XT_EXECUTE
-00fc20 f025 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-00fc21 ff07 .dw $ff07
-00fc22 6428
-00fc23 6665
-00fc24 7265
-00fc25 0029 .db "(defer)", 0
-00fc26 fc15 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-00fc27 f000 .dw DO_COLON
- PFA_DODEFER:
-00fc28 01d8 .dw XT_DOCREATE
-00fc29 0338 .dw XT_REVEAL
-00fc2a 01fb .dw XT_COMPILE
-00fc2b fc2d .dw PFA_DODEFER1
-00fc2c f025 .dw XT_EXIT
- PFA_DODEFER1:
-00fc2d 940e 0351 call_ DO_DODOES
-00fc2f f0c2 .dw XT_DUP
-00fc30 fbc5 .dw XT_ICELLPLUS
-00fc31 f3e2 .dw XT_FETCHI
-00fc32 f02f .dw XT_EXECUTE
-00fc33 f02f .dw XT_EXECUTE
-00fc34 f025 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-00fc35 ff0f .dw $ff0f
-00fc36 6573
-00fc37 7261
-00fc38 6863
-00fc39 772d
-00fc3a 726f
-00fc3b 6c64
-00fc3c 7369
-00fc3d 0074 .db "search-wordlist",0
-00fc3e fc21 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00fc3f f000 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-00fc40 f110 .dw XT_TO_R
-00fc41 f165 .dw XT_ZERO
-00fc42 f045 .dw XT_DOLITERAL
-00fc43 fc54 .dw XT_ISWORD
-00fc44 f107 .dw XT_R_FROM
-00fc45 fc71 .dw XT_TRAVERSEWORDLIST
-00fc46 f0c2 .dw XT_DUP
-00fc47 f12b .dw XT_ZEROEQUAL
-00fc48 f03e .dw XT_DOCONDBRANCH
-00fc49 fc4e DEST(PFA_SEARCH_WORDLIST1)
-00fc4a f588 .dw XT_2DROP
-00fc4b f0ea .dw XT_DROP
-00fc4c f165 .dw XT_ZERO
-00fc4d f025 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-00fc4e f0c2 .dw XT_DUP
-00fc4f fc98 .dw XT_NFA2CFA
- ; .. and get the header flag
-00fc50 f0d5 .dw XT_SWAP
-00fc51 01be .dw XT_NAME2FLAGS
-00fc52 01ac .dw XT_IMMEDIATEQ
-00fc53 f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-00fc54 f000 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-00fc55 f110 .dw XT_TO_R
-00fc56 f0ea .dw XT_DROP
-00fc57 f57f .dw XT_2DUP
-00fc58 f119 .dw XT_R_FETCH ; -- addr len addr len nt
-00fc59 fc8c .dw XT_NAME2STRING
-00fc5a fca2 .dw XT_ICOMPARE ; (-- addr len f )
-00fc5b f03e .dw XT_DOCONDBRANCH
-00fc5c fc62 DEST(PFA_ISWORD3)
- ; not now
-00fc5d f107 .dw XT_R_FROM
-00fc5e f0ea .dw XT_DROP
-00fc5f f165 .dw XT_ZERO
-00fc60 f15c .dw XT_TRUE ; maybe next word
-00fc61 f025 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-00fc62 f588 .dw XT_2DROP
-00fc63 f107 .dw XT_R_FROM
-00fc64 f165 .dw XT_ZERO ; finish traverse-wordlist
-00fc65 f025 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-00fc66 ff11 .dw $ff11
-00fc67 7274
-00fc68 7661
-00fc69 7265
-00fc6a 6573
-00fc6b 772d
-00fc6c 726f
-00fc6d 6c64
-00fc6e 7369
-00fc6f 0074 .db "traverse-wordlist",0
-00fc70 fc35 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-00fc71 f000 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-00fc72 f370 .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-00fc73 f0c2 .dw XT_DUP ; ( -- xt nt nt )
-00fc74 f03e .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-00fc75 fc82 DEST(PFA_TRAVERSEWORDLIST2)
-00fc76 f57f .dw XT_2DUP
-00fc77 f32f .dw XT_2TO_R
-00fc78 f0d5 .dw XT_SWAP
-00fc79 f02f .dw XT_EXECUTE
-00fc7a f33e .dw XT_2R_FROM
-00fc7b f0f2 .dw XT_ROT
-00fc7c f03e .dw XT_DOCONDBRANCH
-00fc7d fc82 DEST(PFA_TRAVERSEWORDLIST2)
-00fc7e 04b5 .dw XT_NFA2LFA
-00fc7f f3e2 .dw XT_FETCHI
-00fc80 f034 .dw XT_DOBRANCH ; ( -- addr )
-00fc81 fc73 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-00fc82 f588 .dw XT_2DROP
-00fc83 f025 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-00fc84 ff0b .dw $ff0b
-00fc85 616e
-00fc86 656d
-00fc87 733e
-00fc88 7274
-00fc89 6e69
-00fc8a 0067 .db "name>string",0
-00fc8b fc66 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-00fc8c f000 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-00fc8d f7e6 .dw XT_ICOUNT ; ( -- addr n )
-00fc8e f045 .dw XT_DOLITERAL
-00fc8f 00ff .dw 255
-00fc90 f224 .dw XT_AND ; mask immediate bit
-00fc91 f025 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-00fc92 ff07 .dw $ff07
-00fc93 666e
-00fc94 3e61
-00fc95 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-00fc96 0061 .db "nfa>cfa"
-00fc97 fc84 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-00fc98 f000 .dw DO_COLON
- PFA_NFA2CFA:
-00fc99 04b5 .dw XT_NFA2LFA ; skip to link field
-00fc9a f240 .dw XT_1PLUS ; next is the execution token
-00fc9b f025 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-00fc9c ff08 .dw $ff08
-00fc9d 6369
-00fc9e 6d6f
-00fc9f 6170
-00fca0 6572 .db "icompare"
-00fca1 fc92 .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-00fca2 f000 .dw DO_COLON
- PFA_ICOMPARE:
-00fca3 f110 .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-00fca4 f0e0 .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-00fca5 f107 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-00fca6 f124 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-00fca7 f03e .dw XT_DOCONDBRANCH
-00fca8 fcad .dw PFA_ICOMPARE_SAMELEN
-00fca9 f588 .dw XT_2DROP
-00fcaa f0ea .dw XT_DROP
-00fcab f15c .dw XT_TRUE
-00fcac f025 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-00fcad f0d5 .dw XT_SWAP ; ( -- r-addr f-addr len )
-00fcae f165 .dw XT_ZERO
-00fcaf 02c5 .dw XT_QDOCHECK
-00fcb0 f03e .dw XT_DOCONDBRANCH
-00fcb1 fcd2 .dw PFA_ICOMPARE_DONE
-00fcb2 f2ac .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-00fcb3 f0e0 .dw XT_OVER
-00fcb4 f08a .dw XT_FETCH
- .if WANT_IGNORECASE == 1
-00fcb5 fcd5 .dw XT_ICOMPARE_LC
- .endif
-00fcb6 f0e0 .dw XT_OVER
-00fcb7 f3e2 .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
-00fcb8 fcd5 .dw XT_ICOMPARE_LC
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-00fcb9 f0c2 .dw XT_DUP
- ;.dw XT_BYTESWAP
-00fcba f045 .dw XT_DOLITERAL
-00fcbb 0100 .dw $100
-00fcbc f16d .dw XT_ULESS
-00fcbd f03e .dw XT_DOCONDBRANCH
-00fcbe fcc3 .dw PFA_ICOMPARE_LASTCELL
-00fcbf f0d5 .dw XT_SWAP
-00fcc0 f045 .dw XT_DOLITERAL
-00fcc1 00ff .dw $00FF
-00fcc2 f224 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-00fcc3 f124 .dw XT_NOTEQUAL
-00fcc4 f03e .dw XT_DOCONDBRANCH
-00fcc5 fcca .dw PFA_ICOMPARE_NEXTLOOP
-00fcc6 f588 .dw XT_2DROP
-00fcc7 f15c .dw XT_TRUE
-00fcc8 f2e5 .dw XT_UNLOOP
-00fcc9 f025 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-00fcca f240 .dw XT_1PLUS
-00fccb f0d5 .dw XT_SWAP
-00fccc f578 .dw XT_CELLPLUS
-00fccd f0d5 .dw XT_SWAP
-00fcce f045 .dw XT_DOLITERAL
-00fccf 0002 .dw 2
-00fcd0 f2cb .dw XT_DOPLUSLOOP
-00fcd1 fcb3 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-00fcd2 f588 .dw XT_2DROP
-00fcd3 f165 .dw XT_ZERO
-00fcd4 f025 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- ; ( cc1 cc2 -- f)
- ; Tools
- ; compares two packed characters
- ;VE_ICOMPARELC:
- ; .dw $ff08
- ; .db "icompare-lower"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ICOMPARELC
- XT_ICOMPARE_LC:
-00fcd5 f000 .dw DO_COLON
- PFA_ICOMPARE_LC:
-00fcd6 f0c2 .dw XT_DUP
-00fcd7 f045 .dw XT_DOLITERAL
-00fcd8 00ff .dw $00ff
-00fcd9 f224 .dw XT_AND
-00fcda f6b2 .dw XT_TOLOWER
-00fcdb f0d5 .dw XT_SWAP
-00fcdc f30a .dw XT_BYTESWAP
-00fcdd f045 .dw XT_DOLITERAL
-00fcde 00ff .dw $00ff
-00fcdf f224 .dw XT_AND
-00fce0 f6b2 .dw XT_TOLOWER
-00fce1 f30a .dw XT_BYTESWAP
-00fce2 f22d .dw XT_OR
-00fce3 f025 .dw XT_EXIT
- .endif
-
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-00fce4 ff01 .dw $ff01
-00fce5 002a .db "*",0
-00fce6 fc9c .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-00fce7 f000 .dw DO_COLON
- PFA_STAR:
- .endif
-
-00fce8 f1b7 .dw XT_MSTAR
-00fce9 f0ea .dw XT_DROP
-00fcea f025 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-00fceb ff01 .dw $FF01
-00fcec 006a .db "j",0
-00fced fce4 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-00fcee f000 .dw DO_COLON
- PFA_J:
-00fcef f287 .dw XT_RP_FETCH
-00fcf0 f045 .dw XT_DOLITERAL
-00fcf1 0007 .dw 7
-00fcf2 f1ae .dw XT_PLUS
-00fcf3 f08a .dw XT_FETCH
-00fcf4 f287 .dw XT_RP_FETCH
-00fcf5 f045 .dw XT_DOLITERAL
-00fcf6 0009 .dw 9
-00fcf7 f1ae .dw XT_PLUS
-00fcf8 f08a .dw XT_FETCH
-00fcf9 f1ae .dw XT_PLUS
-00fcfa f025 .dw XT_EXIT
-
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-00fcfb ff04 .dw $ff04
-00fcfc 6164
-00fcfd 7362 .db "dabs"
-00fcfe fceb .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-00fcff f000 .dw DO_COLON
- PFA_DABS:
-00fd00 f0c2 .dw XT_DUP
-00fd01 f132 .dw XT_ZEROLESS
-00fd02 f03e .dw XT_DOCONDBRANCH
-00fd03 fd05 .dw PFA_DABS1
-00fd04 fd0c .dw XT_DNEGATE
- PFA_DABS1:
-00fd05 f025 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-00fd06 ff07 .dw $ff07
-00fd07 6e64
-00fd08 6765
-00fd09 7461
-00fd0a 0065 .db "dnegate",0
-00fd0b fcfb .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-00fd0c f000 .dw DO_COLON
- PFA_DNEGATE:
-00fd0d f455 .dw XT_DINVERT
-00fd0e fdb1 .dw XT_ONE
-00fd0f f165 .dw XT_ZERO
-00fd10 f42f .dw XT_DPLUS
-00fd11 f025 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-00fd12 ff05 .dw $ff05
-00fd13 6d63
-00fd14 766f
-00fd15 0065 .db "cmove",0
-00fd16 fd06 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-00fd17 fd18 .dw PFA_CMOVE
- PFA_CMOVE:
-00fd18 93bf push xh
-00fd19 93af push xl
-00fd1a 91e9 ld zl, Y+
-00fd1b 91f9 ld zh, Y+ ; addr-to
-00fd1c 91a9 ld xl, Y+
-00fd1d 91b9 ld xh, Y+ ; addr-from
-00fd1e 2f09 mov temp0, tosh
-00fd1f 2b08 or temp0, tosl
-00fd20 f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00fd21 911d ld temp1, X+
-00fd22 9311 st Z+, temp1
-00fd23 9701 sbiw tosl, 1
-00fd24 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-00fd25 91af pop xl
-00fd26 91bf pop xh
-00fd27 9189
-00fd28 9199 loadtos
-00fd29 940c f004 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-00fd2b ff05 .dw $ff05
-00fd2c 7332
-00fd2d 6177
-00fd2e 0070 .db "2swap",0
-00fd2f fd12 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00fd30 f000 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00fd31 f0f2 .dw XT_ROT
-00fd32 f110 .dw XT_TO_R
-00fd33 f0f2 .dw XT_ROT
-00fd34 f107 .dw XT_R_FROM
-00fd35 f025 .dw XT_EXIT
-
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-00fd36 ff0a .dw $ff0a
-00fd37 6572
-00fd38 6966
-00fd39 6c6c
-00fd3a 742d
-00fd3b 6269 .db "refill-tib"
-00fd3c fd2b .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-00fd3d f000 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-00fd3e fd59 .dw XT_TIB
-00fd3f f045 .dw XT_DOLITERAL
-00fd40 005a .dw TIB_SIZE
-00fd41 f8ab .dw XT_ACCEPT
-00fd42 fd5f .dw XT_NUMBERTIB
-00fd43 f092 .dw XT_STORE
-00fd44 f165 .dw XT_ZERO
-00fd45 f598 .dw XT_TO_IN
-00fd46 f092 .dw XT_STORE
-00fd47 f15c .dw XT_TRUE ; -1
-00fd48 f025 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-00fd49 ff0a .dw $FF0A
-00fd4a 6f73
-00fd4b 7275
-00fd4c 6563
-00fd4d 742d
-00fd4e 6269 .db "source-tib"
-00fd4f fd36 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00fd50 f000 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00fd51 fd59 .dw XT_TIB
-00fd52 fd5f .dw XT_NUMBERTIB
-00fd53 f08a .dw XT_FETCH
-00fd54 f025 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-00fd55 ff03 .dw $ff03
-00fd56 6974
-00fd57 0062 .db "tib",0
-00fd58 fd49 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-00fd59 f053 .dw PFA_DOVARIABLE
- PFA_TIB:
-00fd5a 0285 .dw ram_tib
- .dseg
-000285 ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-00fd5b ff04 .dw $ff04
-00fd5c 7423
-00fd5d 6269 .db "#tib"
-00fd5e fd55 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00fd5f f053 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00fd60 02df .dw ram_sharptib
- .dseg
-0002df ram_sharptib: .byte 2
- .cseg
- .endif
-
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00fd61 ff06 .dw $ff06
-00fd62 6565
-00fd63 723e
-00fd64 6d61 .db "ee>ram"
-00fd65 fd5b .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-00fd66 f000 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-00fd67 f165 .dw XT_ZERO
-00fd68 f2ac .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-00fd69 f0e0 .dw XT_OVER
-00fd6a f370 .dw XT_FETCHE
-00fd6b f0e0 .dw XT_OVER
-00fd6c f092 .dw XT_STORE
-00fd6d f578 .dw XT_CELLPLUS
-00fd6e f0d5 .dw XT_SWAP
-00fd6f f578 .dw XT_CELLPLUS
-00fd70 f0d5 .dw XT_SWAP
-00fd71 f2da .dw XT_DOLOOP
-00fd72 fd69 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00fd73 f588 .dw XT_2DROP
-00fd74 f025 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-00fd75 ff08 .dw $ff08
-00fd76 6e69
-00fd77 7469
-00fd78 722d
-00fd79 6d61 .db "init-ram"
-00fd7a fd61 .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-00fd7b f000 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-00fd7c f045 .dw XT_DOLITERAL
-00fd7d 00a8 .dw EE_INITUSER
-00fd7e f313 .dw XT_UP_FETCH
-00fd7f f045 .dw XT_DOLITERAL
-00fd80 0022 .dw SYSUSERSIZE
-00fd81 f215 .dw XT_2SLASH
-00fd82 fd66 .dw XT_EE2RAM
-00fd83 f025 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .endif
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-00fd84 ff06 .dw $ff06
-00fd85 6f62
-00fd86 6e75
-00fd87 7364 .db "bounds"
-00fd88 fd75 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-00fd89 f000 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-00fd8a f0e0 .dw XT_OVER
-00fd8b f1ae .dw XT_PLUS
-00fd8c f0d5 .dw XT_SWAP
-00fd8d f025 .dw XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-00fd8e ff03 .dw $ff03
-00fd8f 3e73
-00fd90 0064 .db "s>d",0
-00fd91 fd84 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-00fd92 f000 .dw DO_COLON
- PFA_S2D:
- .endif
-00fd93 f0c2 .dw XT_DUP
-00fd94 f132 .dw XT_ZEROLESS
-00fd95 f025 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-00fd96 ff05 .dw $ff05
-00fd97 623e
-00fd98 646f
-00fd99 0079 .db ">body",0
-00fd9a fd8e .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-00fd9b f241 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>4000
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-00fd9c 0008 .dw $0008
-00fd9d 6c32
-00fd9e 7469
-00fd9f 7265
-00fda0 6c61 .db "2literal"
-00fda1 fd96 .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-00fda2 f000 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-00fda3 f0d5 .dw XT_SWAP
-00fda4 021c .dw XT_LITERAL
-00fda5 021c .dw XT_LITERAL
-00fda6 f025 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-00fda7 ff01 .dw $ff01
-00fda8 003d .db "=",0
-00fda9 fd9c .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-00fdaa f000 .dw DO_COLON
- PFA_EQUAL:
-00fdab f1a4 .dw XT_MINUS
-00fdac f12b .dw XT_ZEROEQUAL
-00fdad f025 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-00fdae ff01 .dw $ff01
-00fdaf 0031 .db "1",0
-00fdb0 fda7 .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-00fdb1 f053 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-00fdb2 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-00fdb3 ff01 .dw $ff01
-00fdb4 0032 .db "2",0
-00fdb5 fdae .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-00fdb6 f053 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-00fdb7 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-00fdb8 ff02 .dw $ff02
-00fdb9 312d .db "-1"
-00fdba fdb3 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-00fdbb f053 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-00fdbc ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000072 ff ff
- ; some configs
-000074 59 05 CFG_DP: .dw DPSTART ; Dictionary Pointer
-000076 e1 02 EE_HERE: .dw HERESTART ; Memory Allocation
-000078 cc 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00007a 6d 04 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-00007c 9a 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-00007e b0 21 CFG_LP0: .dw stackstart+1
-000080 4b 05 CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000082 4c f5 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000084 86 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-000086 b8 fd CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-000088 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00008a 86 00 .dw CFG_FORTHWORDLIST ; get/set-order
-00008c .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00009a 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-00009c 3e fb .dw XT_REC_FIND
-00009e 2a fb .dw XT_REC_NUM
-0000a0 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-0000a4 8f f3 .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-0000a6 a6 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-0000a8 00 00 .dw 0 ; USER_STATE
-0000aa 00 00 .dw 0 ; USER_FOLLOWER
-0000ac ff 21 .dw rstackstart ; USER_RP
-0000ae af 21 .dw stackstart ; USER_SP0
-0000b0 af 21 .dw stackstart ; USER_SP
-
-0000b2 00 00 .dw 0 ; USER_HANDLER
-0000b4 0a 00 .dw 10 ; USER_BASE
-
-0000b6 e1 00 .dw XT_TX ; USER_EMIT
-0000b8 ef 00 .dw XT_TXQ ; USER_EMITQ
-0000ba b6 00 .dw XT_RX ; USER_KEY
-0000bc d1 00 .dw XT_RXQ ; USER_KEYQ
-0000be 50 fd .dw XT_SOURCETIB ; USER_SOURCE
-0000c0 00 00 .dw 0 ; USER_G_IN
-0000c2 3d fd .dw XT_REFILLTIB ; USER_REFILL
-0000c4 04 fa .dw XT_DEFAULT_PROMPTOK
-0000c6 23 fa .dw XT_DEFAULT_PROMPTERROR
-0000c8 13 fa .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-0000ca 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega1280" register use summary:
-r0 : 25 r1 : 5 r2 : 9 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 80 r17: 61 r18: 52 r19: 37 r20: 13 r21: 38 r22: 11 r23: 3
-r24: 193 r25: 136 r26: 28 r27: 17 r28: 7 r29: 4 r30: 85 r31: 47
-x : 4 y : 205 z : 48
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega1280" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 20 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 0
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 22 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 elpm : 16 eor : 3 fmul : 0
-fmuls : 0 fmulsu: 0 icall : 0 ijmp : 1 in : 18 inc : 3
-jmp : 10 ld : 136 ldd : 4 ldi : 41 lds : 1 lpm : 0
-lsl : 14 lsr : 2 mov : 16 movw : 65 mul : 5 muls : 1
-mulsu : 2 neg : 0 nop : 0 or : 9 ori : 2 out : 27
-pop : 45 push : 39 rcall : 69 ret : 6 reti : 1 rjmp : 102
-rol : 32 ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3
-sbis : 0 sbiw : 14 sbr : 0 sbrc : 5 sbrs : 4 sec : 1
-seh : 0 sei : 1 sen : 0 ser : 4 ses : 0 set : 0
-sev : 0 sez : 0 sleep : 0 spm : 2 st : 76 std : 8
-sts : 1 sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-
-Instructions used: 71 out of 114 (62.3%)
-
-"ATmega1280" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x01fb7a 2076 14620 16696 131072 12.7%
-[.dseg] 0x000200 0x0002e1 0 225 225 8192 2.7%
-[.eseg] 0x000000 0x0000cc 0 204 204 4096 5.0%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/arduino/mega128.map b/amforth-6.5/appl/arduino/mega128.map
deleted file mode 100644
index cc31644..0000000
--- a/amforth-6.5/appl/arduino/mega128.map
+++ /dev/null
@@ -1,2715 +0,0 @@
-
-AVRASM ver. 2.1.52 mega128.asm Sun Apr 30 20:10:13 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000097
-EQU SIGNATURE_002 00000003
-EQU UDR3 00000136
-EQU UBRR3L 00000134
-EQU UBRR3H 00000135
-EQU UCSR3C 00000132
-EQU UCSR3B 00000131
-EQU UCSR3A 00000130
-EQU OCR5CL 0000012c
-EQU OCR5CH 0000012d
-EQU OCR5BL 0000012a
-EQU OCR5BH 0000012b
-EQU OCR5AL 00000128
-EQU OCR5AH 00000129
-EQU ICR5H 00000127
-EQU ICR5L 00000126
-EQU TCNT5L 00000124
-EQU TCNT5H 00000125
-EQU TCCR5C 00000122
-EQU TCCR5B 00000121
-EQU TCCR5A 00000120
-EQU PORTL 0000010b
-EQU DDRL 0000010a
-EQU PINL 00000109
-EQU PORTK 00000108
-EQU DDRK 00000107
-EQU PINK 00000106
-EQU PORTJ 00000105
-EQU DDRJ 00000104
-EQU PINJ 00000103
-EQU PORTH 00000102
-EQU DDRH 00000101
-EQU PINH 00000100
-EQU UDR2 000000d6
-EQU UBRR2L 000000d4
-EQU UBRR2H 000000d5
-EQU UCSR2C 000000d2
-EQU UCSR2B 000000d1
-EQU UCSR2A 000000d0
-EQU UDR1 000000ce
-EQU UBRR1L 000000cc
-EQU UBRR1H 000000cd
-EQU UCSR1C 000000ca
-EQU UCSR1B 000000c9
-EQU UCSR1A 000000c8
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR4CL 000000ac
-EQU OCR4CH 000000ad
-EQU OCR4BL 000000aa
-EQU OCR4BH 000000ab
-EQU OCR4AL 000000a8
-EQU OCR4AH 000000a9
-EQU ICR4L 000000a6
-EQU ICR4H 000000a7
-EQU TCNT4L 000000a4
-EQU TCNT4H 000000a5
-EQU TCCR4C 000000a2
-EQU TCCR4B 000000a1
-EQU TCCR4A 000000a0
-EQU OCR3CL 0000009c
-EQU OCR3CH 0000009d
-EQU OCR3BL 0000009a
-EQU OCR3BH 0000009b
-EQU OCR3AL 00000098
-EQU OCR3AH 00000099
-EQU ICR3L 00000096
-EQU ICR3H 00000097
-EQU TCNT3L 00000094
-EQU TCNT3H 00000095
-EQU TCCR3C 00000092
-EQU TCCR3B 00000091
-EQU TCCR3A 00000090
-EQU OCR1CL 0000008c
-EQU OCR1CH 0000008d
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU DIDR2 0000007d
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU XMCRB 00000075
-EQU XMCRA 00000074
-EQU TIMSK5 00000073
-EQU TIMSK4 00000072
-EQU TIMSK3 00000071
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK2 0000006d
-EQU PCMSK1 0000006c
-EQU PCMSK0 0000006b
-EQU EICRB 0000006a
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR1 00000065
-EQU PRR0 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU EIND 0000003c
-EQU RAMPZ 0000003b
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU OCDR 00000031
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR5 0000001a
-EQU TIFR4 00000019
-EQU TIFR3 00000018
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTG 00000014
-EQU DDRG 00000013
-EQU PING 00000012
-EQU PORTF 00000011
-EQU DDRF 00000010
-EQU PINF 0000000f
-EQU PORTE 0000000e
-EQU DDRE 0000000d
-EQU PINE 0000000c
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU PORTA 00000002
-EQU DDRA 00000001
-EQU PINA 00000000
-EQU ACME 00000006
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU PORTE0 00000000
-EQU PE0 00000000
-EQU PORTE1 00000001
-EQU PE1 00000001
-EQU PORTE2 00000002
-EQU PE2 00000002
-EQU PORTE3 00000003
-EQU PE3 00000003
-EQU PORTE4 00000004
-EQU PE4 00000004
-EQU PORTE5 00000005
-EQU PE5 00000005
-EQU PORTE6 00000006
-EQU PE6 00000006
-EQU PORTE7 00000007
-EQU PE7 00000007
-EQU DDE0 00000000
-EQU DDE1 00000001
-EQU DDE2 00000002
-EQU DDE3 00000003
-EQU DDE4 00000004
-EQU DDE5 00000005
-EQU DDE6 00000006
-EQU DDE7 00000007
-EQU PINE0 00000000
-EQU PINE1 00000001
-EQU PINE2 00000002
-EQU PINE3 00000003
-EQU PINE4 00000004
-EQU PINE5 00000005
-EQU PINE6 00000006
-EQU PINE7 00000007
-EQU PORTF0 00000000
-EQU PF0 00000000
-EQU PORTF1 00000001
-EQU PF1 00000001
-EQU PORTF2 00000002
-EQU PF2 00000002
-EQU PORTF3 00000003
-EQU PF3 00000003
-EQU PORTF4 00000004
-EQU PF4 00000004
-EQU PORTF5 00000005
-EQU PF5 00000005
-EQU PORTF6 00000006
-EQU PF6 00000006
-EQU PORTF7 00000007
-EQU PF7 00000007
-EQU DDF0 00000000
-EQU DDF1 00000001
-EQU DDF2 00000002
-EQU DDF3 00000003
-EQU DDF4 00000004
-EQU DDF5 00000005
-EQU DDF6 00000006
-EQU DDF7 00000007
-EQU PINF0 00000000
-EQU PINF1 00000001
-EQU PINF2 00000002
-EQU PINF3 00000003
-EQU PINF4 00000004
-EQU PINF5 00000005
-EQU PINF6 00000006
-EQU PINF7 00000007
-EQU PORTG0 00000000
-EQU PG0 00000000
-EQU PORTG1 00000001
-EQU PG1 00000001
-EQU PORTG2 00000002
-EQU PG2 00000002
-EQU PORTG3 00000003
-EQU PG3 00000003
-EQU PORTG4 00000004
-EQU PG4 00000004
-EQU PORTG5 00000005
-EQU PG5 00000005
-EQU DDG0 00000000
-EQU DDG1 00000001
-EQU DDG2 00000002
-EQU DDG3 00000003
-EQU DDG4 00000004
-EQU DDG5 00000005
-EQU PING0 00000000
-EQU PING1 00000001
-EQU PING2 00000002
-EQU PING3 00000003
-EQU PING4 00000004
-EQU PING5 00000005
-EQU PORTH0 00000000
-EQU PH0 00000000
-EQU PORTH1 00000001
-EQU PH1 00000001
-EQU PORTH2 00000002
-EQU PH2 00000002
-EQU PORTH3 00000003
-EQU PH3 00000003
-EQU PORTH4 00000004
-EQU PH4 00000004
-EQU PORTH5 00000005
-EQU PH5 00000005
-EQU PORTH6 00000006
-EQU PH6 00000006
-EQU PORTH7 00000007
-EQU PH7 00000007
-EQU DDH0 00000000
-EQU DDH1 00000001
-EQU DDH2 00000002
-EQU DDH3 00000003
-EQU DDH4 00000004
-EQU DDH5 00000005
-EQU DDH6 00000006
-EQU DDH7 00000007
-EQU PINH0 00000000
-EQU PINH1 00000001
-EQU PINH2 00000002
-EQU PINH3 00000003
-EQU PINH4 00000004
-EQU PINH5 00000005
-EQU PINH6 00000006
-EQU PINH7 00000007
-EQU PORTJ0 00000000
-EQU PJ0 00000000
-EQU PORTJ1 00000001
-EQU PJ1 00000001
-EQU PORTJ2 00000002
-EQU PJ2 00000002
-EQU PORTJ3 00000003
-EQU PJ3 00000003
-EQU PORTJ4 00000004
-EQU PJ4 00000004
-EQU PORTJ5 00000005
-EQU PJ5 00000005
-EQU PORTJ6 00000006
-EQU PJ6 00000006
-EQU PORTJ7 00000007
-EQU PJ7 00000007
-EQU DDJ0 00000000
-EQU DDJ1 00000001
-EQU DDJ2 00000002
-EQU DDJ3 00000003
-EQU DDJ4 00000004
-EQU DDJ5 00000005
-EQU DDJ6 00000006
-EQU DDJ7 00000007
-EQU PINJ0 00000000
-EQU PINJ1 00000001
-EQU PINJ2 00000002
-EQU PINJ3 00000003
-EQU PINJ4 00000004
-EQU PINJ5 00000005
-EQU PINJ6 00000006
-EQU PINJ7 00000007
-EQU PORTK0 00000000
-EQU PK0 00000000
-EQU PORTK1 00000001
-EQU PK1 00000001
-EQU PORTK2 00000002
-EQU PK2 00000002
-EQU PORTK3 00000003
-EQU PK3 00000003
-EQU PORTK4 00000004
-EQU PK4 00000004
-EQU PORTK5 00000005
-EQU PK5 00000005
-EQU PORTK6 00000006
-EQU PK6 00000006
-EQU PORTK7 00000007
-EQU PK7 00000007
-EQU DDK0 00000000
-EQU DDK1 00000001
-EQU DDK2 00000002
-EQU DDK3 00000003
-EQU DDK4 00000004
-EQU DDK5 00000005
-EQU DDK6 00000006
-EQU DDK7 00000007
-EQU PINK0 00000000
-EQU PINK1 00000001
-EQU PINK2 00000002
-EQU PINK3 00000003
-EQU PINK4 00000004
-EQU PINK5 00000005
-EQU PINK6 00000006
-EQU PINK7 00000007
-EQU PORTL0 00000000
-EQU PL0 00000000
-EQU PORTL1 00000001
-EQU PL1 00000001
-EQU PORTL2 00000002
-EQU PL2 00000002
-EQU PORTL3 00000003
-EQU PL3 00000003
-EQU PORTL4 00000004
-EQU PL4 00000004
-EQU PORTL5 00000005
-EQU PL5 00000005
-EQU PORTL6 00000006
-EQU PL6 00000006
-EQU PORTL7 00000007
-EQU PL7 00000007
-EQU DDL0 00000000
-EQU DDL1 00000001
-EQU DDL2 00000002
-EQU DDL3 00000003
-EQU DDL4 00000004
-EQU DDL5 00000005
-EQU DDL6 00000006
-EQU DDL7 00000007
-EQU PINL0 00000000
-EQU PINL1 00000001
-EQU PINL2 00000002
-EQU PINL3 00000003
-EQU PINL4 00000004
-EQU PINL5 00000005
-EQU PINL6 00000006
-EQU PINL7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSRSYNC 00000000
-EQU PSR10 00000000
-EQU TSM 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU UDR1_0 00000000
-EQU UDR1_1 00000001
-EQU UDR1_2 00000002
-EQU UDR1_3 00000003
-EQU UDR1_4 00000004
-EQU UDR1_5 00000005
-EQU UDR1_6 00000006
-EQU UDR1_7 00000007
-EQU MPCM1 00000000
-EQU U2X1 00000001
-EQU UPE1 00000002
-EQU DOR1 00000003
-EQU FE1 00000004
-EQU UDRE1 00000005
-EQU TXC1 00000006
-EQU RXC1 00000007
-EQU TXB81 00000000
-EQU RXB81 00000001
-EQU UCSZ12 00000002
-EQU TXEN1 00000003
-EQU RXEN1 00000004
-EQU UDRIE1 00000005
-EQU TXCIE1 00000006
-EQU RXCIE1 00000007
-EQU UCPOL1 00000000
-EQU UCSZ10 00000001
-EQU UCPHA1 00000001
-EQU UCSZ11 00000002
-EQU UDORD1 00000002
-EQU USBS1 00000003
-EQU UPM10 00000004
-EQU UPM11 00000005
-EQU UMSEL10 00000006
-EQU UMSEL11 00000007
-EQU UBRR_8 00000000
-EQU UBRR_9 00000001
-EQU UBRR_10 00000002
-EQU UBRR_11 00000003
-EQU UBRR_0 00000000
-EQU UBRR_1 00000001
-EQU UBRR_2 00000002
-EQU UBRR_3 00000003
-EQU UBRR_4 00000004
-EQU UBRR_5 00000005
-EQU UBRR_6 00000006
-EQU UBRR_7 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEAR10 00000002
-EQU EEAR11 00000003
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU TOIE5 00000000
-EQU OCIE5A 00000001
-EQU OCIE5B 00000002
-EQU OCIE5C 00000003
-EQU ICIE5 00000005
-EQU TOV5 00000000
-EQU OCF5A 00000001
-EQU OCF5B 00000002
-EQU OCF5C 00000003
-EQU ICF5 00000005
-EQU WGM50 00000000
-EQU WGM51 00000001
-EQU COM5C0 00000002
-EQU COM5C1 00000003
-EQU COM5B0 00000004
-EQU COM5B1 00000005
-EQU COM5A0 00000006
-EQU COM5A1 00000007
-EQU CS50 00000000
-EQU CS51 00000001
-EQU CS52 00000002
-EQU WGM52 00000003
-EQU WGM53 00000004
-EQU ICES5 00000006
-EQU ICNC5 00000007
-EQU FOC5C 00000005
-EQU FOC5B 00000006
-EQU FOC5A 00000007
-EQU ICR5H0 00000000
-EQU ICR5H1 00000001
-EQU ICR5H2 00000002
-EQU ICR5H3 00000003
-EQU ICR5H4 00000004
-EQU ICR5H5 00000005
-EQU ICR5H6 00000006
-EQU ICR5H7 00000007
-EQU ICR5L0 00000000
-EQU ICR5L1 00000001
-EQU ICR5L2 00000002
-EQU ICR5L3 00000003
-EQU ICR5L4 00000004
-EQU ICR5L5 00000005
-EQU ICR5L6 00000006
-EQU ICR5L7 00000007
-EQU TOIE4 00000000
-EQU OCIE4A 00000001
-EQU OCIE4B 00000002
-EQU OCIE4C 00000003
-EQU ICIE4 00000005
-EQU TOV4 00000000
-EQU OCF4A 00000001
-EQU OCF4B 00000002
-EQU OCF4C 00000003
-EQU ICF4 00000005
-EQU WGM40 00000000
-EQU WGM41 00000001
-EQU COM4C0 00000002
-EQU COM4C1 00000003
-EQU COM4B0 00000004
-EQU COM4B1 00000005
-EQU COM4A0 00000006
-EQU COM4A1 00000007
-EQU CS40 00000000
-EQU CS41 00000001
-EQU CS42 00000002
-EQU WGM42 00000003
-EQU WGM43 00000004
-EQU ICES4 00000006
-EQU ICNC4 00000007
-EQU FOC4C 00000005
-EQU FOC4B 00000006
-EQU FOC4A 00000007
-EQU TOIE3 00000000
-EQU OCIE3A 00000001
-EQU OCIE3B 00000002
-EQU OCIE3C 00000003
-EQU ICIE3 00000005
-EQU TOV3 00000000
-EQU OCF3A 00000001
-EQU OCF3B 00000002
-EQU OCF3C 00000003
-EQU ICF3 00000005
-EQU WGM30 00000000
-EQU WGM31 00000001
-EQU COM3C0 00000002
-EQU COM3C1 00000003
-EQU COM3B0 00000004
-EQU COM3B1 00000005
-EQU COM3A0 00000006
-EQU COM3A1 00000007
-EQU CS30 00000000
-EQU CS31 00000001
-EQU CS32 00000002
-EQU WGM32 00000003
-EQU WGM33 00000004
-EQU ICES3 00000006
-EQU ICNC3 00000007
-EQU FOC3C 00000005
-EQU FOC3B 00000006
-EQU FOC3A 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU OCIE1C 00000003
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU OCF1C 00000003
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU WGM11 00000001
-EQU COM1C0 00000002
-EQU COM1C1 00000003
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1C 00000005
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU JTD 00000007
-EQU JTRF 00000004
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC20 00000004
-EQU ISC21 00000005
-EQU ISC30 00000006
-EQU ISC31 00000007
-EQU ISC40 00000000
-EQU ISC41 00000001
-EQU ISC50 00000002
-EQU ISC51 00000003
-EQU ISC60 00000004
-EQU ISC61 00000005
-EQU ISC70 00000006
-EQU ISC71 00000007
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INT2 00000002
-EQU INT3 00000003
-EQU INT4 00000004
-EQU INT5 00000005
-EQU INT6 00000006
-EQU INT7 00000007
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU INTF2 00000002
-EQU INTF3 00000003
-EQU INTF4 00000004
-EQU INTF5 00000005
-EQU INTF6 00000006
-EQU INTF7 00000007
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT15 00000007
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU SRW00 00000000
-EQU SRW01 00000001
-EQU SRW10 00000002
-EQU SRW11 00000003
-EQU SRL0 00000004
-EQU SRL1 00000005
-EQU SRL2 00000006
-EQU SRE 00000007
-EQU XMM0 00000000
-EQU XMM1 00000001
-EQU XMM2 00000002
-EQU XMBK 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU RAMPZ0 00000000
-EQU RAMPZ1 00000001
-EQU EIND0 00000000
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRUSART1 00000000
-EQU PRUSART2 00000001
-EQU PRUSART3 00000002
-EQU PRTIM3 00000003
-EQU PRTIM4 00000004
-EQU PRTIM5 00000005
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU MUX5 00000003
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ADC6D 00000006
-EQU ADC7D 00000007
-EQU ADC8D 00000000
-EQU ADC9D 00000001
-EQU ADC10D 00000002
-EQU ADC11D 00000003
-EQU ADC12D 00000004
-EQU ADC13D 00000005
-EQU ADC14D 00000006
-EQU ADC15D 00000007
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU SIGRD 00000005
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU UDR2_0 00000000
-EQU UDR2_1 00000001
-EQU UDR2_2 00000002
-EQU UDR2_3 00000003
-EQU UDR2_4 00000004
-EQU UDR2_5 00000005
-EQU UDR2_6 00000006
-EQU UDR2_7 00000007
-EQU MPCM2 00000000
-EQU U2X2 00000001
-EQU UPE2 00000002
-EQU DOR2 00000003
-EQU FE2 00000004
-EQU UDRE2 00000005
-EQU TXC2 00000006
-EQU RXC2 00000007
-EQU TXB82 00000000
-EQU RXB82 00000001
-EQU UCSZ22 00000002
-EQU TXEN2 00000003
-EQU RXEN2 00000004
-EQU UDRIE2 00000005
-EQU TXCIE2 00000006
-EQU RXCIE2 00000007
-EQU UCPOL2 00000000
-EQU UCSZ20 00000001
-EQU UCSZ21 00000002
-EQU USBS2 00000003
-EQU UPM20 00000004
-EQU UPM21 00000005
-EQU UMSEL20 00000006
-EQU UMSEL21 00000007
-EQU UBRR0 00000000
-EQU UBRR1 00000001
-EQU UDR3_0 00000000
-EQU UDR3_1 00000001
-EQU UDR3_2 00000002
-EQU UDR3_3 00000003
-EQU UDR3_4 00000004
-EQU UDR3_5 00000005
-EQU UDR3_6 00000006
-EQU UDR3_7 00000007
-EQU MPCM3 00000000
-EQU U2X3 00000001
-EQU UPE3 00000002
-EQU DOR3 00000003
-EQU FE3 00000004
-EQU UDRE3 00000005
-EQU TXC3 00000006
-EQU RXC3 00000007
-EQU TXB83 00000000
-EQU RXB83 00000001
-EQU UCSZ32 00000002
-EQU TXEN3 00000003
-EQU RXEN3 00000004
-EQU UDRIE3 00000005
-EQU TXCIE3 00000006
-EQU RXCIE3 00000007
-EQU UCPOL3 00000000
-EQU UCSZ30 00000001
-EQU UCSZ31 00000002
-EQU USBS3 00000003
-EQU UPM30 00000004
-EQU UPM31 00000005
-EQU UMSEL30 00000006
-EQU UMSEL31 00000007
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 0000ffff
-EQU IOEND 000001ff
-EQU SRAM_START 00000200
-EQU SRAM_SIZE 00002000
-EQU RAMEND 000021ff
-EQU XRAMEND 0000ffff
-EQU E2END 00000fff
-EQU EEPROMEND 00000fff
-EQU EEADRBITS 0000000c
-EQU NRWW_START_ADDR 0000f000
-EQU NRWW_STOP_ADDR 0000ffff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 0000efff
-EQU PAGESIZE 00000080
-EQU FIRSTBOOTSTART 0000fe00
-EQU SECONDBOOTSTART 0000fc00
-EQU THIRDBOOTSTART 0000f800
-EQU FOURTHBOOTSTART 0000f000
-EQU SMALLBOOTSTART 0000fe00
-EQU LARGEBOOTSTART 0000f000
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU INT3addr 00000008
-EQU INT4addr 0000000a
-EQU INT5addr 0000000c
-EQU INT6addr 0000000e
-EQU INT7addr 00000010
-EQU PCI0addr 00000012
-EQU PCI1addr 00000014
-EQU PCI2addr 00000016
-EQU WDTaddr 00000018
-EQU OC2Aaddr 0000001a
-EQU OC2Baddr 0000001c
-EQU OVF2addr 0000001e
-EQU ICP1addr 00000020
-EQU OC1Aaddr 00000022
-EQU OC1Baddr 00000024
-EQU OC1Caddr 00000026
-EQU OVF1addr 00000028
-EQU OC0Aaddr 0000002a
-EQU OC0Baddr 0000002c
-EQU OVF0addr 0000002e
-EQU SPIaddr 00000030
-EQU URXC0addr 00000032
-EQU UDRE0addr 00000034
-EQU UTXC0addr 00000036
-EQU ACIaddr 00000038
-EQU ADCCaddr 0000003a
-EQU ERDYaddr 0000003c
-EQU ICP3addr 0000003e
-EQU OC3Aaddr 00000040
-EQU OC3Baddr 00000042
-EQU OC3Caddr 00000044
-EQU OVF3addr 00000046
-EQU URXC1addr 00000048
-EQU UDRE1addr 0000004a
-EQU UTXC1addr 0000004c
-EQU TWIaddr 0000004e
-EQU SPMRaddr 00000050
-EQU ICP4addr 00000052
-EQU OC4Aaddr 00000054
-EQU OC4Baddr 00000056
-EQU OC4Caddr 00000058
-EQU OVF4addr 0000005a
-EQU ICP5addr 0000005c
-EQU OC5Aaddr 0000005e
-EQU OC5Baddr 00000060
-EQU OC5Caddr 00000062
-EQU OVF5addr 00000064
-EQU URXC2addr 00000066
-EQU UDRE2addr 00000068
-EQU UTXC2addr 0000006a
-EQU URXC3addr 0000006c
-EQU UDRE3addr 0000006e
-EQU UTXC3addr 00000070
-EQU INT_VECTORS_SIZE 00000072
-EQU ramstart 00000200
-EQU CELLSIZE 00000002
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_USART0 00000000
-SET WANT_TWI 00000000
-SET WANT_SPI 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_PORTE 00000000
-SET WANT_PORTF 00000000
-SET WANT_PORTG 00000000
-SET WANT_PORTH 00000000
-SET WANT_PORTJ 00000000
-SET WANT_PORTK 00000000
-SET WANT_PORTL 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_USART1 00000000
-SET WANT_EEPROM 00000000
-SET WANT_TIMER_COUNTER_5 00000000
-SET WANT_TIMER_COUNTER_4 00000000
-SET WANT_TIMER_COUNTER_3 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_JTAG 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_CPU 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_USART2 00000000
-SET WANT_USART3 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 00000167
-EQU INTVECTORS 00000039
-CSEG mcu_info 00000071
-CSEG mcu_ramsize 00000071
-CSEG mcu_eepromsize 00000072
-CSEG mcu_maxdp 00000073
-CSEG mcu_numints 00000074
-CSEG mcu_name 00000075
-SET codestart 0000007b
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000001
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000021ff
-SET stackstart 000021af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000000a
-SET VE_HEAD 0000fdb8
-SET VE_ENVHEAD 0000f54c
-SET AMFORTH_RO_SEG 0000f000
-EQU F_CPU 00f42400
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU URXCaddr 00000032
-EQU UDREaddr 00000034
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000200
-DSEG usart_rx_in 00000210
-DSEG usart_rx_out 00000211
-CSEG VE_TO_RXBUF 0000007b
-CSEG XT_TO_RXBUF 00000081
-CSEG PFA_rx_tobuf 00000082
-CSEG DO_NEXT 0000f004
-CSEG VE_ISR_RX 00000092
-CSEG XT_ISR_RX 00000097
-CSEG DO_COLON 0000f000
-CSEG usart_rx_isr 00000098
-CSEG XT_DOLITERAL 0000f045
-CSEG XT_CFETCH 0000f0a9
-CSEG XT_DUP 0000f0c2
-CSEG XT_EQUAL 0000fdaa
-CSEG XT_DOCONDBRANCH 0000f03e
-CSEG usart_rx_isr1 000000a2
-CSEG XT_COLD 0000fa73
-CSEG XT_EXIT 0000f025
-CSEG XT_USART_INIT_RX_BUFFER 000000a4
-CSEG PFA_USART_INIT_RX_BUFFER 000000a5
-CSEG XT_INTSTORE 0000f4a1
-CSEG XT_ZERO 0000f165
-CSEG XT_FILL 0000f4e9
-CSEG VE_RX_BUFFER 000000b1
-CSEG XT_RX_BUFFER 000000b6
-CSEG PFA_RX_BUFFER 000000b7
-CSEG XT_RXQ_BUFFER 000000d1
-CSEG XT_PLUS 0000f1ae
-CSEG XT_SWAP 0000f0d5
-CSEG XT_1PLUS 0000f240
-CSEG XT_AND 0000f224
-CSEG XT_CSTORE 0000f09e
-CSEG VE_RXQ_BUFFER 000000cb
-CSEG PFA_RXQ_BUFFER 000000d2
-CSEG XT_PAUSE 0000fa6b
-CSEG XT_NOTEQUAL 0000f124
-SET XT_RX 000000b6
-SET XT_RXQ 000000d1
-SET XT_USART_INIT_RX 000000a4
-CSEG VE_TX_POLL 000000db
-CSEG XT_TX_POLL 000000e1
-CSEG PFA_TX_POLL 000000e2
-CSEG XT_TXQ_POLL 000000ef
-CSEG VE_TXQ_POLL 000000e9
-CSEG PFA_TXQ_POLL 000000f0
-SET XT_TX 000000e1
-SET XT_TXQ 000000ef
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000f8
-CSEG XT_UBRR 000000fc
-CSEG PFA_DOVALUE1 0000f080
-CSEG PFA_UBRR 000000fd
-ESEG EE_UBRRVAL 000000ca
-CSEG XT_EDEFERFETCH 0000fbce
-CSEG XT_EDEFERSTORE 0000fbd8
-CSEG VE_USART 00000100
-CSEG XT_USART 00000105
-CSEG PFA_USART 00000106
-CSEG XT_BYTESWAP 0000f30a
-EQU OW_PORT 0000000e
-EQU OW_BIT 00000004
-SET OW_DDR 0000000d
-SET OW_PIN 0000000c
-CSEG VE_OW_RESET 0000011b
-CSEG XT_OW_RESET 00000121
-CSEG PFA_OW_RESET 00000122
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_OW_SLOT 0000013f
-CSEG XT_OW_SLOT 00000145
-CSEG PFA_OW_SLOT 00000146
-CSEG PFA_OW_SLOT0 00000153
-SET AMFORTH_NRWW_SIZE 00001ffe
-SET corepc 00000167
-CSEG PFA_COLD 0000fa74
-ESEG intvec 00000000
-DSEG intcnt 00000212
-CSEG VE_MPLUS 0000017e
-CSEG XT_MPLUS 00000181
-CSEG PFA_MPLUS 00000182
-CSEG XT_S2D 0000fd92
-CSEG XT_DPLUS 0000f42f
-CSEG VE_UDSTAR 00000185
-CSEG XT_UDSTAR 00000189
-CSEG PFA_UDSTAR 0000018a
-CSEG XT_TO_R 0000f110
-CSEG XT_UMSTAR 0000f1f1
-CSEG XT_DROP 0000f0ea
-CSEG XT_R_FROM 0000f107
-CSEG XT_ROT 0000f0f2
-CSEG VE_UMAX 00000194
-CSEG XT_UMAX 00000198
-CSEG PFA_UMAX 00000199
-CSEG XT_2DUP 0000f57f
-CSEG XT_ULESS 0000f16d
-CSEG UMAX1 0000019e
-CSEG VE_UMIN 000001a0
-CSEG XT_UMIN 000001a4
-CSEG PFA_UMIN 000001a5
-CSEG XT_UGREATER 0000f178
-CSEG UMIN1 000001aa
-CSEG XT_IMMEDIATEQ 000001ac
-CSEG PFA_IMMEDIATEQ 000001ad
-CSEG XT_ZEROEQUAL 0000f12b
-CSEG IMMEDIATEQ1 000001b5
-CSEG XT_ONE 0000fdb1
-CSEG XT_TRUE 0000f15c
-CSEG VE_NAME2FLAGS 000001b7
-CSEG XT_NAME2FLAGS 000001be
-CSEG PFA_NAME2FLAGS 000001bf
-CSEG XT_FETCHI 0000f3e2
-CSEG VE_NEWEST 000001c4
-CSEG XT_NEWEST 000001c9
-CSEG PFA_DOVARIABLE 0000f053
-CSEG PFA_NEWEST 000001ca
-DSEG ram_newest 0000024b
-CSEG VE_LATEST 000001cb
-CSEG XT_LATEST 000001d0
-CSEG PFA_LATEST 000001d1
-DSEG ram_latest 0000024f
-CSEG VE_DOCREATE 000001d2
-CSEG XT_DOCREATE 000001d8
-CSEG PFA_DOCREATE 000001d9
-CSEG XT_PARSENAME 0000f9ce
-CSEG XT_WLSCOPE 0000032f
-CSEG XT_CELLPLUS 0000f578
-CSEG XT_STORE 0000f092
-CSEG XT_HEADER 00000314
-CSEG VE_BACKSLASH 000001e3
-CSEG XT_BACKSLASH 000001e6
-CSEG PFA_BACKSLASH 000001e7
-CSEG XT_SOURCE 0000f9b5
-CSEG XT_NIP 0000f101
-CSEG XT_TO_IN 0000f598
-CSEG VE_LPAREN 000001ec
-CSEG XT_LPAREN 000001ef
-CSEG PFA_LPAREN 000001f0
-CSEG XT_PARSE 0000f9a1
-CSEG XT_2DROP 0000f588
-CSEG VE_COMPILE 000001f5
-CSEG XT_COMPILE 000001fb
-CSEG PFA_COMPILE 000001fc
-CSEG XT_ICELLPLUS 0000fbc5
-CSEG XT_COMMA 00000206
-CSEG VE_COMMA 00000203
-CSEG PFA_COMMA 00000207
-CSEG XT_DP 0000f5c8
-CSEG XT_STOREI 0000f384
-CSEG XT_DOTO 0000fbb3
-CSEG PFA_DP 0000f5c9
-CSEG VE_BRACKETTICK 0000020e
-CSEG XT_BRACKETTICK 00000212
-CSEG PFA_BRACKETTICK 00000213
-CSEG XT_TICK 0000f824
-CSEG XT_LITERAL 0000021c
-CSEG VE_LITERAL 00000216
-CSEG PFA_LITERAL 0000021d
-CSEG VE_SLITERAL 00000221
-CSEG XT_SLITERAL 00000227
-CSEG PFA_SLITERAL 00000228
-CSEG XT_DOSLITERAL 0000f787
-CSEG XT_SCOMMA 0000f795
-CSEG XT_GMARK 0000022c
-CSEG PFA_GMARK 0000022d
-CSEG XT_GRESOLVE 00000231
-CSEG PFA_GRESOLVE 00000232
-CSEG XT_QSTACK 0000fb71
-CSEG XT_LMARK 00000237
-CSEG PFA_LMARK 00000238
-CSEG XT_LRESOLVE 0000023a
-CSEG PFA_LRESOLVE 0000023b
-CSEG VE_AHEAD 0000023e
-CSEG XT_AHEAD 00000243
-CSEG PFA_AHEAD 00000244
-CSEG XT_DOBRANCH 0000f034
-CSEG VE_IF 00000248
-CSEG XT_IF 0000024b
-CSEG PFA_IF 0000024c
-CSEG VE_ELSE 00000250
-CSEG XT_ELSE 00000254
-CSEG PFA_ELSE 00000255
-CSEG VE_THEN 0000025b
-CSEG XT_THEN 0000025f
-CSEG PFA_THEN 00000260
-CSEG VE_BEGIN 00000262
-CSEG XT_BEGIN 00000267
-CSEG PFA_BEGIN 00000268
-CSEG VE_WHILE 0000026a
-CSEG XT_WHILE 0000026f
-CSEG PFA_WHILE 00000270
-CSEG VE_REPEAT 00000273
-CSEG XT_REPEAT 00000278
-CSEG PFA_REPEAT 00000279
-CSEG XT_AGAIN 0000028c
-CSEG VE_UNTIL 0000027c
-CSEG XT_UNTIL 00000281
-CSEG PFA_UNTIL 00000282
-CSEG VE_AGAIN 00000287
-CSEG PFA_AGAIN 0000028d
-CSEG VE_DO 00000291
-CSEG XT_DO 00000294
-CSEG PFA_DO 00000295
-CSEG XT_DODO 0000f2ac
-CSEG XT_TO_L 000002ef
-CSEG VE_LOOP 0000029b
-CSEG XT_LOOP 0000029f
-CSEG PFA_LOOP 000002a0
-CSEG XT_DOLOOP 0000f2da
-CSEG XT_ENDLOOP 000002d6
-CSEG VE_PLUSLOOP 000002a4
-CSEG XT_PLUSLOOP 000002a9
-CSEG PFA_PLUSLOOP 000002aa
-CSEG XT_DOPLUSLOOP 0000f2cb
-CSEG VE_LEAVE 000002ae
-CSEG XT_LEAVE 000002b3
-CSEG PFA_LEAVE 000002b4
-CSEG XT_UNLOOP 0000f2e5
-CSEG VE_QDO 000002b9
-CSEG XT_QDO 000002bd
-CSEG PFA_QDO 000002be
-CSEG XT_QDOCHECK 000002c5
-CSEG PFA_QDOCHECK 000002c6
-CSEG PFA_QDOCHECK1 000002cd
-CSEG XT_INVERT 0000f20e
-CSEG VE_ENDLOOP 000002d0
-CSEG PFA_ENDLOOP 000002d7
-CSEG LOOP1 000002d8
-CSEG XT_L_FROM 000002e3
-CSEG XT_QDUP 0000f0ca
-CSEG LOOP2 000002df
-CSEG VE_L_FROM 000002e0
-CSEG PFA_L_FROM 000002e4
-CSEG XT_LP 00000302
-CSEG XT_FETCH 0000f08a
-CSEG XT_PLUSSTORE 0000f276
-CSEG VE_TO_L 000002ec
-CSEG PFA_TO_L 000002f0
-CSEG XT_TWO 0000fdb6
-CSEG VE_LP0 000002f7
-CSEG XT_LP0 000002fb
-CSEG PFA_LP0 000002fc
-ESEG CFG_LP0 0000007e
-CSEG VE_LP 000002ff
-CSEG PFA_LP 00000303
-DSEG ram_lp 00000251
-CSEG VE_CREATE 00000304
-CSEG XT_CREATE 00000309
-CSEG PFA_CREATE 0000030a
-CSEG XT_REVEAL 00000338
-CSEG PFA_DOCONSTANT 0000f060
-CSEG VE_HEADER 0000030f
-CSEG PFA_HEADER 00000315
-CSEG XT_GREATERZERO 0000f139
-CSEG PFA_HEADER1 00000326
-CSEG XT_OR 0000f22d
-CSEG XT_DOSCOMMA 0000f799
-CSEG XT_FETCHE 0000f370
-CSEG XT_THROW 0000f85b
-CSEG VE_WLSCOPE 00000329
-CSEG PFA_DODEFER1 0000fc2d
-CSEG PFA_WLSCOPE 00000330
-ESEG CFG_WLSCOPE 0000007a
-CSEG VE_REVEAL 00000333
-CSEG PFA_REVEAL 00000339
-CSEG REVEAL1 00000343
-CSEG XT_STOREE 0000f34c
-CSEG VE_DOES 00000344
-CSEG XT_DOES 00000349
-CSEG PFA_DOES 0000034a
-CSEG XT_DODOES 0000035c
-CSEG DO_DODOES 00000351
-CSEG PFA_DODOES 0000035d
-CSEG XT_NFA2CFA 0000fc98
-CSEG VE_COLON 00000365
-CSEG XT_COLON 00000368
-CSEG PFA_COLON 00000369
-CSEG XT_COLONNONAME 00000373
-CSEG VE_COLONNONAME 0000036d
-CSEG PFA_COLONNONAME 00000374
-CSEG XT_RBRACKET 00000388
-CSEG VE_SEMICOLON 0000037c
-CSEG XT_SEMICOLON 0000037f
-CSEG PFA_SEMICOLON 00000380
-CSEG XT_LBRACKET 00000390
-CSEG VE_RBRACKET 00000385
-CSEG PFA_RBRACKET 00000389
-CSEG XT_STATE 0000f565
-CSEG VE_LBRACKET 0000038d
-CSEG PFA_LBRACKET 00000391
-CSEG VE_VARIABLE 00000395
-CSEG XT_VARIABLE 0000039b
-CSEG PFA_VARIABLE 0000039c
-CSEG XT_HERE 0000f5d9
-CSEG XT_CONSTANT 000003a7
-CSEG XT_ALLOT 0000f5e2
-CSEG VE_CONSTANT 000003a1
-CSEG PFA_CONSTANT 000003a8
-CSEG VE_USER 000003ae
-CSEG XT_USER 000003b2
-CSEG PFA_USER 000003b3
-CSEG PFA_DOUSER 0000f066
-CSEG VE_RECURSE 000003b9
-CSEG XT_RECURSE 000003bf
-CSEG PFA_RECURSE 000003c0
-CSEG VE_IMMEDIATE 000003c4
-CSEG XT_IMMEDIATE 000003cb
-CSEG PFA_IMMEDIATE 000003cc
-CSEG XT_GET_CURRENT 0000046d
-CSEG VE_BRACKETCHAR 000003d6
-CSEG XT_BRACKETCHAR 000003db
-CSEG PFA_BRACKETCHAR 000003dc
-CSEG XT_CHAR 0000f904
-CSEG VE_ABORTQUOTE 000003e1
-CSEG XT_ABORTQUOTE 000003e6
-CSEG PFA_ABORTQUOTE 000003e7
-CSEG XT_SQUOTE 0000f4db
-CSEG XT_QABORT 000003f8
-CSEG VE_ABORT 000003eb
-CSEG XT_ABORT 000003f0
-CSEG PFA_ABORT 000003f1
-CSEG VE_QABORT 000003f3
-CSEG PFA_QABORT 000003f9
-CSEG QABO1 000003fe
-CSEG XT_ITYPE 0000f7ba
-CSEG VE_GET_STACK 00000400
-CSEG XT_GET_STACK 00000407
-CSEG PFA_N_FETCH_E2 0000041e
-CSEG PFA_N_FETCH_E1 00000414
-CSEG XT_I 0000f2bd
-CSEG XT_1MINUS 0000f246
-CSEG XT_CELLS 0000f572
-CSEG XT_OVER 0000f0e0
-CSEG VE_SET_STACK 00000421
-CSEG XT_SET_STACK 00000428
-CSEG PFA_SET_STACK 00000429
-CSEG XT_ZEROLESS 0000f132
-CSEG PFA_SET_STACK0 00000430
-CSEG PFA_SET_STACK2 0000043d
-CSEG PFA_SET_STACK1 00000438
-CSEG XT_TUCK 0000f590
-CSEG VE_MAPSTACK 0000043f
-CSEG XT_MAPSTACK 00000446
-CSEG PFA_MAPSTACK 00000447
-CSEG XT_BOUNDS 0000fd89
-CSEG PFA_MAPSTACK3 00000462
-CSEG PFA_MAPSTACK1 00000451
-CSEG XT_R_FETCH 0000f119
-CSEG XT_EXECUTE 0000f02f
-CSEG PFA_MAPSTACK2 0000045e
-CSEG VE_GET_CURRENT 00000465
-CSEG PFA_GET_CURRENT 0000046e
-ESEG CFG_CURRENT 00000084
-CSEG VE_GET_ORDER 00000472
-CSEG XT_GET_ORDER 00000479
-CSEG PFA_GET_ORDER 0000047a
-ESEG CFG_ORDERLISTLEN 00000088
-CSEG VE_CFG_ORDER 0000047e
-CSEG XT_CFG_ORDER 00000485
-CSEG PFA_CFG_ORDER 00000486
-CSEG VE_COMPARE 00000487
-CSEG XT_COMPARE 0000048d
-CSEG PFA_COMPARE 0000048e
-CSEG PFA_COMPARE_LOOP 0000049a
-CSEG PFA_COMPARE_NOTEQUAL 000004a8
-CSEG PFA_COMPARE_ENDREACHED2 000004a3
-CSEG PFA_COMPARE_ENDREACHED 000004a4
-CSEG PFA_COMPARE_CHECKLASTCHAR 000004a8
-CSEG PFA_COMPARE_DONE 000004aa
-CSEG VE_NFA2LFA 000004af
-CSEG XT_NFA2LFA 000004b5
-CSEG PFA_NFA2LFA 000004b6
-CSEG XT_NAME2STRING 0000fc8c
-CSEG XT_2SLASH 0000f215
-CSEG VE_SET_CURRENT 000004bb
-CSEG XT_SET_CURRENT 000004c3
-CSEG PFA_SET_CURRENT 000004c4
-CSEG VE_WORDLIST 000004c8
-CSEG XT_WORDLIST 000004ce
-CSEG PFA_WORDLIST 000004cf
-CSEG XT_EHERE 0000f5d1
-CSEG PFA_EHERE 0000f5d2
-CSEG VE_FORTHWORDLIST 000004d8
-CSEG XT_FORTHWORDLIST 000004e1
-CSEG PFA_FORTHWORDLIST 000004e2
-ESEG CFG_FORTHWORDLIST 00000086
-CSEG VE_SET_ORDER 000004e3
-CSEG XT_SET_ORDER 000004ea
-CSEG PFA_SET_ORDER 000004eb
-CSEG VE_SET_RECOGNIZERS 000004ef
-CSEG XT_SET_RECOGNIZERS 000004f9
-CSEG PFA_SET_RECOGNIZERS 000004fa
-ESEG CFG_RECOGNIZERLISTLEN 0000009a
-CSEG VE_GET_RECOGNIZERS 000004fe
-CSEG XT_GET_RECOGNIZERS 00000508
-CSEG PFA_GET_RECOGNIZERS 00000509
-CSEG VE_CODE 0000050d
-CSEG XT_CODE 00000511
-CSEG PFA_CODE 00000512
-CSEG VE_ENDCODE 00000518
-CSEG XT_ENDCODE 0000051e
-CSEG PFA_ENDCODE 0000051f
-CSEG VE_MARKER 00000524
-CSEG XT_MARKER 0000052a
-CSEG PFA_MARKER 0000052b
-ESEG EE_MARKER 000000a6
-CSEG VE_POSTPONE 0000052e
-CSEG XT_POSTPONE 00000534
-CSEG PFA_POSTPONE 00000535
-CSEG XT_FORTHRECOGNIZER 0000fae6
-CSEG XT_RECOGNIZE 0000faf1
-CSEG VE_APPLTURNKEY 00000543
-CSEG XT_APPLTURNKEY 0000054b
-CSEG PFA_APPLTURNKEY 0000054c
-CSEG XT_INTON 0000f493
-CSEG XT_DOT_VER 0000fb7e
-CSEG XT_SPACE 0000f7fc
-SET DPSTART 00000559
-CSEG DO_INTERRUPT 0000f019
-CSEG DO_EXECUTE 0000f00f
-CSEG XT_ISREXEC 0000f4bc
-CSEG VE_EXIT 0000f021
-CSEG PFA_EXIT 0000f026
-CSEG VE_EXECUTE 0000f029
-CSEG PFA_EXECUTE 0000f030
-CSEG PFA_DOBRANCH 0000f035
-CSEG PFA_DOCONDBRANCH 0000f03f
-CSEG PFA_DOLITERAL 0000f046
-CSEG XT_DOVARIABLE 0000f052
-CSEG XT_DOCONSTANT 0000f05f
-CSEG XT_DOUSER 0000f065
-CSEG VE_DOVALUE 0000f074
-CSEG XT_DOVALUE 0000f07a
-CSEG PFA_DOVALUE 0000f07b
-CSEG VE_FETCH 0000f087
-CSEG PFA_FETCH 0000f08b
-CSEG PFA_FETCHRAM 0000f08b
-CSEG VE_STORE 0000f08f
-CSEG PFA_STORE 0000f093
-CSEG PFA_STORERAM 0000f093
-CSEG VE_CSTORE 0000f09b
-CSEG PFA_CSTORE 0000f09f
-CSEG VE_CFETCH 0000f0a6
-CSEG PFA_CFETCH 0000f0aa
-CSEG VE_FETCHU 0000f0ae
-CSEG XT_FETCHU 0000f0b1
-CSEG PFA_FETCHU 0000f0b2
-CSEG XT_UP_FETCH 0000f313
-CSEG VE_STOREU 0000f0b6
-CSEG XT_STOREU 0000f0b9
-CSEG PFA_STOREU 0000f0ba
-CSEG VE_DUP 0000f0be
-CSEG PFA_DUP 0000f0c3
-CSEG VE_QDUP 0000f0c6
-CSEG PFA_QDUP 0000f0cb
-CSEG PFA_QDUP1 0000f0d0
-CSEG VE_SWAP 0000f0d1
-CSEG PFA_SWAP 0000f0d6
-CSEG VE_OVER 0000f0dc
-CSEG PFA_OVER 0000f0e1
-CSEG VE_DROP 0000f0e6
-CSEG PFA_DROP 0000f0eb
-CSEG VE_ROT 0000f0ee
-CSEG PFA_ROT 0000f0f3
-CSEG VE_NIP 0000f0fd
-CSEG PFA_NIP 0000f102
-CSEG VE_R_FROM 0000f104
-CSEG PFA_R_FROM 0000f108
-CSEG VE_TO_R 0000f10d
-CSEG PFA_TO_R 0000f111
-CSEG VE_R_FETCH 0000f116
-CSEG PFA_R_FETCH 0000f11a
-CSEG VE_NOTEQUAL 0000f121
-CSEG PFA_NOTEQUAL 0000f125
-CSEG VE_ZEROEQUAL 0000f128
-CSEG PFA_ZEROEQUAL 0000f12c
-CSEG PFA_ZERO1 0000f168
-CSEG PFA_TRUE1 0000f15f
-CSEG VE_ZEROLESS 0000f12f
-CSEG PFA_ZEROLESS 0000f133
-CSEG VE_GREATERZERO 0000f136
-CSEG PFA_GREATERZERO 0000f13a
-CSEG VE_DGREATERZERO 0000f13f
-CSEG XT_DGREATERZERO 0000f143
-CSEG PFA_DGREATERZERO 0000f144
-CSEG VE_DXT_ZEROLESS 0000f14d
-CSEG XT_DXT_ZEROLESS 0000f151
-CSEG PFA_DXT_ZEROLESS 0000f152
-CSEG VE_TRUE 0000f158
-CSEG PFA_TRUE 0000f15d
-CSEG VE_ZERO 0000f162
-CSEG PFA_ZERO 0000f166
-CSEG VE_ULESS 0000f16a
-CSEG PFA_ULESS 0000f16e
-CSEG VE_UGREATER 0000f175
-CSEG PFA_UGREATER 0000f179
-CSEG VE_LESS 0000f17c
-CSEG XT_LESS 0000f17f
-CSEG PFA_LESS 0000f180
-CSEG PFA_LESSDONE 0000f184
-CSEG VE_GREATER 0000f186
-CSEG XT_GREATER 0000f189
-CSEG PFA_GREATER 0000f18a
-CSEG PFA_GREATERDONE 0000f18e
-CSEG VE_LOG2 0000f191
-CSEG XT_LOG2 0000f195
-CSEG PFA_LOG2 0000f196
-CSEG PFA_LOG2_1 0000f199
-CSEG PFA_LOG2_2 0000f19f
-CSEG VE_MINUS 0000f1a1
-CSEG XT_MINUS 0000f1a4
-CSEG PFA_MINUS 0000f1a5
-CSEG VE_PLUS 0000f1ab
-CSEG PFA_PLUS 0000f1af
-CSEG VE_MSTAR 0000f1b4
-CSEG XT_MSTAR 0000f1b7
-CSEG PFA_MSTAR 0000f1b8
-CSEG VE_UMSLASHMOD 0000f1ce
-CSEG XT_UMSLASHMOD 0000f1d3
-CSEG PFA_UMSLASHMOD 0000f1d4
-CSEG PFA_UMSLASHMODmod 0000f1d9
-CSEG PFA_UMSLASHMODmod_loop 0000f1da
-CSEG PFA_UMSLASHMODmod_loop_control 0000f1e7
-CSEG PFA_UMSLASHMODmod_subtract 0000f1e4
-CSEG PFA_UMSLASHMODmod_done 0000f1e9
-CSEG VE_UMSTAR 0000f1ed
-CSEG PFA_UMSTAR 0000f1f2
-CSEG VE_INVERT 0000f209
-CSEG PFA_INVERT 0000f20f
-CSEG VE_2SLASH 0000f212
-CSEG PFA_2SLASH 0000f216
-CSEG VE_2STAR 0000f219
-CSEG XT_2STAR 0000f21c
-CSEG PFA_2STAR 0000f21d
-CSEG VE_AND 0000f220
-CSEG PFA_AND 0000f225
-CSEG VE_OR 0000f22a
-CSEG PFA_OR 0000f22e
-CSEG VE_XOR 0000f233
-CSEG XT_XOR 0000f237
-CSEG PFA_XOR 0000f238
-CSEG VE_1PLUS 0000f23d
-CSEG PFA_1PLUS 0000f241
-CSEG VE_1MINUS 0000f243
-CSEG PFA_1MINUS 0000f247
-CSEG VE_QNEGATE 0000f249
-CSEG XT_QNEGATE 0000f24f
-CSEG PFA_QNEGATE 0000f250
-CSEG QNEG1 0000f254
-CSEG XT_NEGATE 0000f659
-CSEG VE_LSHIFT 0000f255
-CSEG XT_LSHIFT 0000f25a
-CSEG PFA_LSHIFT 0000f25b
-CSEG PFA_LSHIFT1 0000f25e
-CSEG PFA_LSHIFT2 0000f263
-CSEG VE_RSHIFT 0000f264
-CSEG XT_RSHIFT 0000f269
-CSEG PFA_RSHIFT 0000f26a
-CSEG PFA_RSHIFT1 0000f26d
-CSEG PFA_RSHIFT2 0000f272
-CSEG VE_PLUSSTORE 0000f273
-CSEG PFA_PLUSSTORE 0000f277
-CSEG VE_RP_FETCH 0000f283
-CSEG XT_RP_FETCH 0000f287
-CSEG PFA_RP_FETCH 0000f288
-CSEG VE_RP_STORE 0000f28d
-CSEG XT_RP_STORE 0000f291
-CSEG PFA_RP_STORE 0000f292
-CSEG VE_SP_FETCH 0000f29a
-CSEG XT_SP_FETCH 0000f29e
-CSEG PFA_SP_FETCH 0000f29f
-CSEG VE_SP_STORE 0000f2a3
-CSEG XT_SP_STORE 0000f2a7
-CSEG PFA_SP_STORE 0000f2a8
-CSEG PFA_DODO 0000f2ad
-CSEG PFA_DODO1 0000f2af
-CSEG VE_I 0000f2ba
-CSEG PFA_I 0000f2be
-CSEG PFA_DOPLUSLOOP 0000f2cc
-CSEG PFA_DOPLUSLOOP_LEAVE 0000f2d6
-CSEG PFA_DOPLUSLOOP_NEXT 0000f2d3
-CSEG PFA_DOLOOP 0000f2db
-CSEG VE_UNLOOP 0000f2e0
-CSEG PFA_UNLOOP 0000f2e6
-CSEG VE_CMOVE_G 0000f2eb
-CSEG XT_CMOVE_G 0000f2f0
-CSEG PFA_CMOVE_G 0000f2f1
-CSEG PFA_CMOVE_G1 0000f302
-CSEG PFA_CMOVE_G2 0000f2fe
-CSEG VE_BYTESWAP 0000f307
-CSEG PFA_BYTESWAP 0000f30b
-CSEG VE_UP_FETCH 0000f30f
-CSEG PFA_UP_FETCH 0000f314
-CSEG VE_UP_STORE 0000f318
-CSEG XT_UP_STORE 0000f31c
-CSEG PFA_UP_STORE 0000f31d
-CSEG VE_1MS 0000f321
-CSEG XT_1MS 0000f325
-CSEG PFA_1MS 0000f326
-CSEG VE_2TO_R 0000f32b
-CSEG XT_2TO_R 0000f32f
-CSEG PFA_2TO_R 0000f330
-CSEG VE_2R_FROM 0000f33a
-CSEG XT_2R_FROM 0000f33e
-CSEG PFA_2R_FROM 0000f33f
-CSEG VE_STOREE 0000f349
-CSEG PFA_STOREE 0000f34d
-CSEG PFA_STOREE0 0000f34d
-CSEG PFA_FETCHE2 0000f37b
-CSEG PFA_STOREE3 0000f357
-CSEG PFA_STOREE1 0000f362
-CSEG PFA_STOREE4 0000f35e
-CSEG PFA_STOREE2 0000f364
-CSEG VE_FETCHE 0000f36d
-CSEG PFA_FETCHE 0000f371
-CSEG PFA_FETCHE1 0000f371
-CSEG VE_STOREI 0000f381
-CSEG PFA_STOREI 0000f385
-ESEG EE_STOREI 000000a4
-CSEG VE_DO_STOREI_NRWW 0000f388
-CSEG XT_DO_STOREI 0000f38f
-CSEG PFA_DO_STOREI_NRWW 0000f390
-CSEG DO_STOREI_atmega 0000f3a4
-CSEG pageload 0000f3b5
-CSEG DO_STOREI_writepage 0000f3ae
-CSEG dospm 0000f3d1
-EQU pagemask ffffff80
-CSEG pageload_loop 0000f3bb
-CSEG pageload_newdata 0000f3c9
-CSEG pageload_cont 0000f3cb
-CSEG pageload_done 0000f3d0
-CSEG dospm_wait_ee 0000f3d1
-CSEG dospm_wait_spm 0000f3d3
-CSEG VE_FETCHI 0000f3df
-CSEG PFA_FETCHI 0000f3e3
-CSEG VE_N_TO_R 0000f3ec
-CSEG XT_N_TO_R 0000f3f0
-CSEG PFA_N_TO_R 0000f3f1
-CSEG PFA_N_TO_R1 0000f3f3
-CSEG VE_N_R_FROM 0000f3fe
-CSEG XT_N_R_FROM 0000f402
-CSEG PFA_N_R_FROM 0000f403
-CSEG PFA_N_R_FROM1 0000f408
-CSEG VE_D2STAR 0000f410
-CSEG XT_D2STAR 0000f414
-CSEG PFA_D2STAR 0000f415
-CSEG VE_D2SLASH 0000f41e
-CSEG XT_D2SLASH 0000f422
-CSEG PFA_D2SLASH 0000f423
-CSEG VE_DPLUS 0000f42c
-CSEG PFA_DPLUS 0000f430
-CSEG VE_DMINUS 0000f43d
-CSEG XT_DMINUS 0000f440
-CSEG PFA_DMINUS 0000f441
-CSEG VE_DINVERT 0000f44f
-CSEG XT_DINVERT 0000f455
-CSEG PFA_DINVERT 0000f456
-CSEG VE_UDOT 0000f45f
-CSEG XT_UDOT 0000f462
-CSEG PFA_UDOT 0000f463
-CSEG XT_UDDOT 0000f744
-CSEG VE_UDOTR 0000f466
-CSEG XT_UDOTR 0000f46a
-CSEG PFA_UDOTR 0000f46b
-CSEG XT_UDDOTR 0000f74d
-CSEG VE_SHOWWORDLIST 0000f46f
-CSEG XT_SHOWWORDLIST 0000f478
-CSEG PFA_SHOWWORDLIST 0000f479
-CSEG XT_SHOWWORD 0000f47e
-CSEG XT_TRAVERSEWORDLIST 0000fc71
-CSEG PFA_SHOWWORD 0000f47f
-CSEG VE_WORDS 0000f484
-CSEG XT_WORDS 0000f489
-CSEG PFA_WORDS 0000f48a
-CSEG VE_INTON 0000f48f
-CSEG PFA_INTON 0000f494
-CSEG VE_INTOFF 0000f496
-CSEG XT_INTOFF 0000f49a
-CSEG PFA_INTOFF 0000f49b
-CSEG VE_INTSTORE 0000f49d
-CSEG PFA_INTSTORE 0000f4a2
-CSEG VE_INTFETCH 0000f4a7
-CSEG XT_INTFETCH 0000f4ab
-CSEG PFA_INTFETCH 0000f4ac
-CSEG VE_INTTRAP 0000f4b1
-CSEG XT_INTTRAP 0000f4b7
-CSEG PFA_INTTRAP 0000f4b8
-CSEG PFA_ISREXEC 0000f4bd
-CSEG XT_ISREND 0000f4c1
-CSEG PFA_ISREND 0000f4c2
-CSEG PFA_ISREND1 0000f4c4
-CSEG VE_PICK 0000f4c5
-CSEG XT_PICK 0000f4c9
-CSEG PFA_PICK 0000f4ca
-CSEG VE_DOTSTRING 0000f4d0
-CSEG XT_DOTSTRING 0000f4d3
-CSEG PFA_DOTSTRING 0000f4d4
-CSEG VE_SQUOTE 0000f4d8
-CSEG PFA_SQUOTE 0000f4dc
-CSEG PFA_SQUOTE1 0000f4e4
-CSEG VE_FILL 0000f4e5
-CSEG PFA_FILL 0000f4ea
-CSEG PFA_FILL2 0000f4f6
-CSEG PFA_FILL1 0000f4f1
-CSEG VE_ENVIRONMENT 0000f4f8
-CSEG XT_ENVIRONMENT 0000f500
-CSEG PFA_ENVIRONMENT 0000f501
-ESEG CFG_ENVIRONMENT 00000082
-CSEG VE_ENVWORDLISTS 0000f502
-CSEG XT_ENVWORDLISTS 0000f509
-CSEG PFA_ENVWORDLISTS 0000f50a
-CSEG VE_ENVSLASHPAD 0000f50d
-CSEG XT_ENVSLASHPAD 0000f511
-CSEG PFA_ENVSLASHPAD 0000f512
-CSEG XT_PAD 0000f59e
-CSEG VE_ENVSLASHHOLD 0000f516
-CSEG XT_ENVSLASHHOLD 0000f51b
-CSEG PFA_ENVSLASHHOLD 0000f51c
-CSEG VE_ENV_FORTHNAME 0000f520
-CSEG XT_ENV_FORTHNAME 0000f527
-CSEG PFA_EN_FORTHNAME 0000f528
-CSEG VE_ENV_FORTHVERSION 0000f52f
-CSEG XT_ENV_FORTHVERSION 0000f535
-CSEG PFA_EN_FORTHVERSION 0000f536
-CSEG VE_ENV_CPU 0000f539
-CSEG XT_ENV_CPU 0000f53d
-CSEG PFA_EN_CPU 0000f53e
-CSEG XT_ICOUNT 0000f7e6
-CSEG VE_ENV_MCUINFO 0000f542
-CSEG XT_ENV_MCUINFO 0000f548
-CSEG PFA_EN_MCUINFO 0000f549
-CSEG VE_ENVUSERSIZE 0000f54c
-CSEG XT_ENVUSERSIZE 0000f551
-CSEG PFA_ENVUSERSIZE 0000f552
-CSEG VE_F_CPU 0000f555
-CSEG XT_F_CPU 0000f55a
-CSEG PFA_F_CPU 0000f55b
-CSEG VE_STATE 0000f560
-CSEG PFA_STATE 0000f566
-DSEG ram_state 00000253
-CSEG VE_BASE 0000f567
-CSEG XT_BASE 0000f56b
-CSEG PFA_BASE 0000f56c
-CSEG VE_CELLS 0000f56d
-CSEG VE_CELLPLUS 0000f573
-CSEG PFA_CELLPLUS 0000f579
-CSEG VE_2DUP 0000f57b
-CSEG PFA_2DUP 0000f580
-CSEG VE_2DROP 0000f583
-CSEG PFA_2DROP 0000f589
-CSEG VE_TUCK 0000f58c
-CSEG PFA_TUCK 0000f591
-CSEG VE_TO_IN 0000f594
-CSEG PFA_TO_IN 0000f599
-CSEG VE_PAD 0000f59a
-CSEG PFA_PAD 0000f59f
-CSEG VE_EMIT 0000f5a4
-CSEG XT_EMIT 0000f5a8
-CSEG PFA_EMIT 0000f5a9
-CSEG XT_UDEFERFETCH 0000fbf6
-CSEG XT_UDEFERSTORE 0000fc02
-CSEG VE_EMITQ 0000f5ac
-CSEG XT_EMITQ 0000f5b1
-CSEG PFA_EMITQ 0000f5b2
-CSEG VE_KEY 0000f5b5
-CSEG XT_KEY 0000f5b9
-CSEG PFA_KEY 0000f5ba
-CSEG VE_KEYQ 0000f5bd
-CSEG XT_KEYQ 0000f5c1
-CSEG PFA_KEYQ 0000f5c2
-CSEG VE_DP 0000f5c5
-ESEG CFG_DP 00000074
-CSEG VE_EHERE 0000f5cc
-ESEG EE_EHERE 00000078
-CSEG VE_HERE 0000f5d5
-CSEG PFA_HERE 0000f5da
-ESEG EE_HERE 00000076
-CSEG VE_ALLOT 0000f5dd
-CSEG PFA_ALLOT 0000f5e3
-CSEG VE_BIN 0000f5e8
-CSEG XT_BIN 0000f5ec
-CSEG PFA_BIN 0000f5ed
-CSEG VE_DECIMAL 0000f5f1
-CSEG XT_DECIMAL 0000f5f7
-CSEG PFA_DECIMAL 0000f5f8
-CSEG VE_HEX 0000f5fd
-CSEG XT_HEX 0000f601
-CSEG PFA_HEX 0000f602
-CSEG VE_BL 0000f607
-CSEG XT_BL 0000f60a
-CSEG PFA_BL 0000f60b
-CSEG VE_TURNKEY 0000f60c
-CSEG XT_TURNKEY 0000f612
-CSEG PFA_TURNKEY 0000f613
-ESEG CFG_TURNKEY 00000080
-CSEG VE_SLASHMOD 0000f616
-CSEG XT_SLASHMOD 0000f61a
-CSEG PFA_SLASHMOD 0000f61b
-CSEG PFA_SLASHMOD_1 0000f626
-CSEG PFA_SLASHMOD_2 0000f62c
-CSEG PFA_SLASHMOD_3 0000f62f
-CSEG PFA_SLASHMOD_5 0000f63a
-CSEG PFA_SLASHMOD_4 0000f639
-CSEG PFA_SLASHMODmod_done 0000f645
-CSEG PFA_SLASHMOD_6 0000f643
-CSEG VE_USLASHMOD 0000f649
-CSEG XT_USLASHMOD 0000f64e
-CSEG PFA_USLASHMOD 0000f64f
-CSEG VE_NEGATE 0000f654
-CSEG PFA_NEGATE 0000f65a
-CSEG VE_SLASH 0000f65d
-CSEG XT_SLASH 0000f660
-CSEG PFA_SLASH 0000f661
-CSEG VE_MOD 0000f664
-CSEG XT_MOD 0000f668
-CSEG PFA_MOD 0000f669
-CSEG VE_ABS 0000f66c
-CSEG XT_ABS 0000f670
-CSEG PFA_ABS 0000f671
-CSEG VE_MIN 0000f674
-CSEG XT_MIN 0000f678
-CSEG PFA_MIN 0000f679
-CSEG PFA_MIN1 0000f67e
-CSEG VE_MAX 0000f680
-CSEG XT_MAX 0000f684
-CSEG PFA_MAX 0000f685
-CSEG PFA_MAX1 0000f68a
-CSEG VE_WITHIN 0000f68c
-CSEG XT_WITHIN 0000f691
-CSEG PFA_WITHIN 0000f692
-CSEG VE_TOUPPER 0000f699
-CSEG XT_TOUPPER 0000f69f
-CSEG PFA_TOUPPER 0000f6a0
-CSEG PFA_TOUPPER0 0000f6ab
-CSEG VE_TOLOWER 0000f6ac
-CSEG XT_TOLOWER 0000f6b2
-CSEG PFA_TOLOWER 0000f6b3
-CSEG PFA_TOLOWER0 0000f6be
-CSEG VE_HLD 0000f6bf
-CSEG XT_HLD 0000f6c3
-CSEG PFA_HLD 0000f6c4
-DSEG ram_hld 00000255
-CSEG VE_HOLD 0000f6c5
-CSEG XT_HOLD 0000f6c9
-CSEG PFA_HOLD 0000f6ca
-CSEG VE_L_SHARP 0000f6d5
-CSEG XT_L_SHARP 0000f6d8
-CSEG PFA_L_SHARP 0000f6d9
-CSEG VE_SHARP 0000f6dd
-CSEG XT_SHARP 0000f6e0
-CSEG PFA_SHARP 0000f6e1
-CSEG XT_UDSLASHMOD 0000f75d
-CSEG PFA_SHARP1 0000f6ee
-CSEG VE_SHARP_S 0000f6f3
-CSEG XT_SHARP_S 0000f6f6
-CSEG PFA_SHARP_S 0000f6f7
-CSEG NUMS1 0000f6f7
-CSEG VE_SHARP_G 0000f6fe
-CSEG XT_SHARP_G 0000f701
-CSEG PFA_SHARP_G 0000f702
-CSEG VE_SIGN 0000f709
-CSEG XT_SIGN 0000f70d
-CSEG PFA_SIGN 0000f70e
-CSEG PFA_SIGN1 0000f714
-CSEG VE_DDOTR 0000f715
-CSEG XT_DDOTR 0000f719
-CSEG PFA_DDOTR 0000f71a
-CSEG XT_DABS 0000fcff
-CSEG XT_SPACES 0000f805
-CSEG XT_TYPE 0000f815
-CSEG VE_DOTR 0000f728
-CSEG XT_DOTR 0000f72b
-CSEG PFA_DOTR 0000f72c
-CSEG VE_DDOT 0000f731
-CSEG XT_DDOT 0000f734
-CSEG PFA_DDOT 0000f735
-CSEG VE_DOT 0000f739
-CSEG XT_DOT 0000f73c
-CSEG PFA_DOT 0000f73d
-CSEG VE_UDDOT 0000f740
-CSEG PFA_UDDOT 0000f745
-CSEG VE_UDDOTR 0000f749
-CSEG PFA_UDDOTR 0000f74e
-CSEG VE_UDSLASHMOD 0000f758
-CSEG PFA_UDSLASHMOD 0000f75e
-CSEG VE_DIGITQ 0000f768
-CSEG XT_DIGITQ 0000f76d
-CSEG PFA_DIGITQ 0000f76e
-CSEG PFA_DOSLITERAL 0000f788
-CSEG VE_SCOMMA 0000f792
-CSEG PFA_SCOMMA 0000f796
-CSEG PFA_DOSCOMMA 0000f79a
-CSEG PFA_SCOMMA2 0000f7ac
-CSEG PFA_SCOMMA1 0000f7a6
-CSEG PFA_SCOMMA3 0000f7b3
-CSEG VE_ITYPE 0000f7b5
-CSEG PFA_ITYPE 0000f7bb
-CSEG PFA_ITYPE2 0000f7ce
-CSEG PFA_ITYPE1 0000f7c6
-CSEG XT_LOWEMIT 0000f7db
-CSEG XT_HIEMIT 0000f7d7
-CSEG PFA_ITYPE3 0000f7d5
-CSEG PFA_HIEMIT 0000f7d8
-CSEG PFA_LOWEMIT 0000f7dc
-CSEG VE_ICOUNT 0000f7e1
-CSEG PFA_ICOUNT 0000f7e7
-CSEG VE_CR 0000f7ec
-CSEG XT_CR 0000f7ef
-CSEG PFA_CR 0000f7f0
-CSEG VE_SPACE 0000f7f7
-CSEG PFA_SPACE 0000f7fd
-CSEG VE_SPACES 0000f800
-CSEG PFA_SPACES 0000f806
-CSEG SPCS1 0000f808
-CSEG SPCS2 0000f80f
-CSEG VE_TYPE 0000f811
-CSEG PFA_TYPE 0000f816
-CSEG PFA_TYPE2 0000f820
-CSEG PFA_TYPE1 0000f81b
-CSEG VE_TICK 0000f821
-CSEG PFA_TICK 0000f825
-CSEG XT_DT_NULL 0000fb64
-CSEG XT_NOOP 0000fb99
-CSEG PFA_TICK1 0000f836
-CSEG VE_HANDLER 0000f838
-CSEG XT_HANDLER 0000f83e
-CSEG PFA_HANDLER 0000f83f
-CSEG VE_CATCH 0000f840
-CSEG XT_CATCH 0000f845
-CSEG PFA_CATCH 0000f846
-CSEG VE_THROW 0000f856
-CSEG PFA_THROW 0000f85c
-CSEG PFA_THROW1 0000f862
-CSEG VE_CSKIP 0000f86f
-CSEG XT_CSKIP 0000f874
-CSEG PFA_CSKIP 0000f875
-CSEG PFA_CSKIP1 0000f876
-CSEG PFA_CSKIP2 0000f883
-CSEG XT_SLASHSTRING 0000f9bf
-CSEG VE_CSCAN 0000f886
-CSEG XT_CSCAN 0000f88b
-CSEG PFA_CSCAN 0000f88c
-CSEG PFA_CSCAN1 0000f88e
-CSEG PFA_CSCAN2 0000f8a0
-CSEG VE_ACCEPT 0000f8a6
-CSEG XT_ACCEPT 0000f8ab
-CSEG PFA_ACCEPT 0000f8ac
-CSEG ACC1 0000f8b0
-CSEG XT_CRLFQ 0000f8ec
-CSEG ACC5 0000f8de
-CSEG ACC3 0000f8ce
-CSEG ACC6 0000f8cc
-CSEG XT_BS 0000f8e4
-CSEG ACC4 0000f8dc
-CSEG PFA_ACCEPT6 0000f8d5
-CSEG VE_REFILL 0000f8f7
-CSEG XT_REFILL 0000f8fc
-CSEG PFA_REFILL 0000f8fd
-CSEG VE_CHAR 0000f900
-CSEG PFA_CHAR 0000f905
-CSEG VE_NUMBER 0000f909
-CSEG XT_NUMBER 0000f90e
-CSEG PFA_NUMBER 0000f90f
-CSEG XT_QSIGN 0000f952
-CSEG XT_SET_BASE 0000f965
-CSEG PFA_NUMBER0 0000f925
-CSEG XT_TO_NUMBER 0000f983
-CSEG PFA_NUMBER1 0000f947
-CSEG PFA_NUMBER2 0000f93e
-CSEG PFA_NUMBER6 0000f93f
-CSEG PFA_NUMBER3 0000f93b
-CSEG XT_DNEGATE 0000fd0c
-CSEG PFA_NUMBER5 0000f94d
-CSEG PFA_NUMBER4 0000f94c
-CSEG PFA_QSIGN 0000f953
-CSEG PFA_NUMBERSIGN_DONE 0000f95e
-CSEG XT_BASES 0000f960
-CSEG PFA_SET_BASE 0000f966
-CSEG SET_BASE1 0000f97b
-CSEG SET_BASE2 0000f97c
-CSEG VE_TO_NUMBER 0000f97d
-CSEG TONUM1 0000f984
-CSEG TONUM3 0000f99b
-CSEG TONUM2 0000f98f
-CSEG XT_2SWAP 0000fd30
-CSEG VE_PARSE 0000f99c
-CSEG PFA_PARSE 0000f9a2
-CSEG VE_SOURCE 0000f9b0
-CSEG PFA_SOURCE 0000f9b6
-CSEG VE_SLASHSTRING 0000f9b9
-CSEG PFA_SLASHSTRING 0000f9c0
-CSEG VE_PARSENAME 0000f9c7
-CSEG PFA_PARSENAME 0000f9cf
-CSEG XT_SKIPSCANCHAR 0000f9d2
-CSEG PFA_SKIPSCANCHAR 0000f9d3
-CSEG VE_FINDXT 0000f9e4
-CSEG XT_FINDXT 0000f9ea
-CSEG PFA_FINDXT 0000f9eb
-CSEG XT_FINDXTA 0000f9f6
-CSEG PFA_FINDXT1 0000f9f5
-CSEG PFA_FINDXTA 0000f9f7
-CSEG XT_SEARCH_WORDLIST 0000fc3f
-CSEG PFA_FINDXTA1 0000fa03
-CSEG XT_DEFAULT_PROMPTOK 0000fa04
-CSEG PFA_DEFAULT_PROMPTOK 0000fa05
-CSEG VE_PROMPTOK 0000fa0b
-CSEG XT_PROMPTOK 0000fa0f
-CSEG PFA_PROMPTOK 0000fa10
-CSEG XT_DEFAULT_PROMPTREADY 0000fa13
-CSEG PFA_DEFAULT_PROMPTREADY 0000fa14
-CSEG VE_PROMPTREADY 0000fa1a
-CSEG XT_PROMPTREADY 0000fa1f
-CSEG PFA_PROMPTREADY 0000fa20
-CSEG XT_DEFAULT_PROMPTERROR 0000fa23
-CSEG PFA_DEFAULT_PROMPTERROR 0000fa24
-CSEG VE_PROMPTERROR 0000fa35
-CSEG XT_PROMPTERROR 0000fa3a
-CSEG PFA_PROMPTERROR 0000fa3b
-CSEG VE_QUIT 0000fa3e
-CSEG XT_QUIT 0000fa42
-CSEG PFA_QUIT 0000fa43
-CSEG XT_SP0 0000faa3
-CSEG XT_RP0 0000fab0
-CSEG PFA_QUIT2 0000fa4b
-CSEG PFA_QUIT4 0000fa51
-CSEG PFA_QUIT3 0000fa63
-CSEG XT_INTERPRET 0000fac9
-CSEG PFA_QUIT5 0000fa61
-CSEG VE_PAUSE 0000fa66
-CSEG PFA_PAUSE 0000fa6c
-DSEG ram_pause 00000257
-CSEG XT_RDEFERFETCH 0000fbe2
-CSEG XT_RDEFERSTORE 0000fbec
-CSEG VE_COLD 0000fa6f
-CSEG clearloop 0000fa7b
-DSEG ram_user1 00000259
-CSEG PFA_WARM 0000fa96
-CSEG VE_WARM 0000fa91
-CSEG XT_WARM 0000fa95
-CSEG XT_INIT_RAM 0000fd7b
-CSEG XT_DEFERSTORE 0000fc0d
-CSEG VE_SP0 0000fa9f
-CSEG PFA_SP0 0000faa4
-CSEG VE_SP 0000faa7
-CSEG XT_SP 0000faaa
-CSEG PFA_SP 0000faab
-CSEG VE_RP0 0000faac
-CSEG PFA_RP0 0000fab1
-CSEG XT_DORP0 0000fab4
-CSEG PFA_DORP0 0000fab5
-CSEG VE_DEPTH 0000fab6
-CSEG XT_DEPTH 0000fabb
-CSEG PFA_DEPTH 0000fabc
-CSEG VE_INTERPRET 0000fac2
-CSEG PFA_INTERPRET 0000faca
-CSEG PFA_INTERPRET2 0000fada
-CSEG PFA_INTERPRET1 0000fad5
-CSEG VE_FORTHRECOGNIZER 0000fadc
-CSEG PFA_FORTHRECOGNIZER 0000fae7
-ESEG CFG_FORTHRECOGNIZER 0000007c
-CSEG VE_RECOGNIZE 0000faea
-CSEG PFA_RECOGNIZE 0000faf2
-CSEG XT_RECOGNIZE_A 0000fafc
-CSEG PFA_RECOGNIZE1 0000fafb
-CSEG PFA_RECOGNIZE_A 0000fafd
-CSEG PFA_RECOGNIZE_A1 0000fb0d
-CSEG VE_DT_NUM 0000fb11
-CSEG XT_DT_NUM 0000fb16
-CSEG PFA_DT_NUM 0000fb17
-CSEG VE_DT_DNUM 0000fb1a
-CSEG XT_DT_DNUM 0000fb20
-CSEG PFA_DT_DNUM 0000fb21
-CSEG XT_2LITERAL 0000fda2
-CSEG VE_REC_NUM 0000fb24
-CSEG XT_REC_NUM 0000fb2a
-CSEG PFA_REC_NUM 0000fb2b
-CSEG PFA_REC_NONUMBER 0000fb36
-CSEG PFA_REC_INTNUM2 0000fb34
-CSEG VE_REC_FIND 0000fb38
-CSEG XT_REC_FIND 0000fb3e
-CSEG PFA_REC_FIND 0000fb3f
-CSEG PFA_REC_WORD_FOUND 0000fb47
-CSEG XT_DT_XT 0000fb4e
-CSEG VE_DT_XT 0000fb49
-CSEG PFA_DT_XT 0000fb4f
-CSEG XT_R_WORD_INTERPRET 0000fb52
-CSEG XT_R_WORD_COMPILE 0000fb56
-CSEG PFA_R_WORD_INTERPRET 0000fb53
-CSEG PFA_R_WORD_COMPILE 0000fb57
-CSEG PFA_R_WORD_COMPILE1 0000fb5c
-CSEG VE_DT_NULL 0000fb5e
-CSEG PFA_DT_NULL 0000fb65
-CSEG XT_FAIL 0000fb68
-CSEG PFA_FAIL 0000fb69
-CSEG VE_QSTACK 0000fb6c
-CSEG PFA_QSTACK 0000fb72
-CSEG PFA_QSTACK1 0000fb79
-CSEG VE_DOT_VER 0000fb7a
-CSEG PFA_DOT_VER 0000fb7f
-CSEG VE_NOOP 0000fb95
-CSEG PFA_NOOP 0000fb9a
-CSEG VE_UNUSED 0000fb9b
-CSEG XT_UNUSED 0000fba0
-CSEG PFA_UNUSED 0000fba1
-CSEG VE_TO 0000fba5
-CSEG XT_TO 0000fba8
-CSEG PFA_TO 0000fba9
-CSEG XT_TO_BODY 0000fd9b
-CSEG PFA_TO1 0000fbb9
-CSEG PFA_DOTO 0000fbb4
-CSEG VE_ICELLPLUS 0000fbbf
-CSEG PFA_ICELLPLUS 0000fbc6
-CSEG VE_EDEFERFETCH 0000fbc8
-CSEG PFA_EDEFERFETCH 0000fbcf
-CSEG VE_EDEFERSTORE 0000fbd2
-CSEG PFA_EDEFERSTORE 0000fbd9
-CSEG VE_RDEFERFETCH 0000fbdc
-CSEG PFA_RDEFERFETCH 0000fbe3
-CSEG VE_RDEFERSTORE 0000fbe6
-CSEG PFA_RDEFERSTORE 0000fbed
-CSEG VE_UDEFERFETCH 0000fbf0
-CSEG PFA_UDEFERFETCH 0000fbf7
-CSEG VE_UDEFERSTORE 0000fbfc
-CSEG PFA_UDEFERSTORE 0000fc03
-CSEG VE_DEFERSTORE 0000fc08
-CSEG PFA_DEFERSTORE 0000fc0e
-CSEG VE_DEFERFETCH 0000fc15
-CSEG XT_DEFERFETCH 0000fc1a
-CSEG PFA_DEFERFETCH 0000fc1b
-CSEG VE_DODEFER 0000fc21
-CSEG XT_DODEFER 0000fc27
-CSEG PFA_DODEFER 0000fc28
-CSEG VE_SEARCH_WORDLIST 0000fc35
-CSEG PFA_SEARCH_WORDLIST 0000fc40
-CSEG XT_ISWORD 0000fc54
-CSEG PFA_SEARCH_WORDLIST1 0000fc4e
-CSEG PFA_ISWORD 0000fc55
-CSEG XT_ICOMPARE 0000fca2
-CSEG PFA_ISWORD3 0000fc62
-CSEG VE_TRAVERSEWORDLIST 0000fc66
-CSEG PFA_TRAVERSEWORDLIST 0000fc72
-CSEG PFA_TRAVERSEWORDLIST1 0000fc73
-CSEG PFA_TRAVERSEWORDLIST2 0000fc82
-CSEG VE_NAME2STRING 0000fc84
-CSEG PFA_NAME2STRING 0000fc8d
-CSEG VE_NFA2CFA 0000fc92
-CSEG PFA_NFA2CFA 0000fc99
-CSEG VE_ICOMPARE 0000fc9c
-CSEG PFA_ICOMPARE 0000fca3
-CSEG PFA_ICOMPARE_SAMELEN 0000fcad
-CSEG PFA_ICOMPARE_DONE 0000fcd2
-CSEG PFA_ICOMPARE_LOOP 0000fcb3
-CSEG XT_ICOMPARE_LC 0000fcd5
-CSEG PFA_ICOMPARE_LASTCELL 0000fcc3
-CSEG PFA_ICOMPARE_NEXTLOOP 0000fcca
-CSEG PFA_ICOMPARE_LC 0000fcd6
-CSEG VE_STAR 0000fce4
-CSEG XT_STAR 0000fce7
-CSEG PFA_STAR 0000fce8
-CSEG VE_J 0000fceb
-CSEG XT_J 0000fcee
-CSEG PFA_J 0000fcef
-CSEG VE_DABS 0000fcfb
-CSEG PFA_DABS 0000fd00
-CSEG PFA_DABS1 0000fd05
-CSEG VE_DNEGATE 0000fd06
-CSEG PFA_DNEGATE 0000fd0d
-CSEG VE_CMOVE 0000fd12
-CSEG XT_CMOVE 0000fd17
-CSEG PFA_CMOVE 0000fd18
-CSEG PFA_CMOVE1 0000fd25
-CSEG PFA_CMOVE2 0000fd21
-CSEG VE_2SWAP 0000fd2b
-CSEG PFA_2SWAP 0000fd31
-CSEG VE_REFILLTIB 0000fd36
-CSEG XT_REFILLTIB 0000fd3d
-CSEG PFA_REFILLTIB 0000fd3e
-CSEG XT_TIB 0000fd59
-CSEG XT_NUMBERTIB 0000fd5f
-CSEG VE_SOURCETIB 0000fd49
-CSEG XT_SOURCETIB 0000fd50
-CSEG PFA_SOURCETIB 0000fd51
-CSEG VE_TIB 0000fd55
-CSEG PFA_TIB 0000fd5a
-DSEG ram_tib 00000285
-CSEG VE_NUMBERTIB 0000fd5b
-CSEG PFA_NUMBERTIB 0000fd60
-DSEG ram_sharptib 000002df
-CSEG VE_EE2RAM 0000fd61
-CSEG XT_EE2RAM 0000fd66
-CSEG PFA_EE2RAM 0000fd67
-CSEG PFA_EE2RAM_1 0000fd69
-CSEG PFA_EE2RAM_2 0000fd73
-CSEG VE_INIT_RAM 0000fd75
-CSEG PFA_INI_RAM 0000fd7c
-ESEG EE_INITUSER 000000a8
-CSEG VE_BOUNDS 0000fd84
-CSEG PFA_BOUNDS 0000fd8a
-CSEG VE_S2D 0000fd8e
-CSEG PFA_S2D 0000fd93
-CSEG VE_TO_BODY 0000fd96
-CSEG VE_2LITERAL 0000fd9c
-CSEG PFA_2LITERAL 0000fda3
-CSEG VE_EQUAL 0000fda7
-CSEG PFA_EQUAL 0000fdab
-CSEG VE_ONE 0000fdae
-CSEG PFA_ONE 0000fdb2
-CSEG VE_TWO 0000fdb3
-CSEG PFA_TWO 0000fdb7
-CSEG VE_MINUSONE 0000fdb8
-CSEG XT_MINUSONE 0000fdbb
-CSEG PFA_MINUSONE 0000fdbc
-SET flashlast 0000fdbd
-DSEG HERESTART 000002e1
-ESEG EHERESTART 000000cc
-ESEG CFG_ORDERLIST 0000008a
-ESEG CFG_RECOGNIZERLIST 0000009c
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/arduino/readme.txt b/amforth-6.5/appl/arduino/readme.txt
deleted file mode 100644
index 45b79df..0000000
--- a/amforth-6.5/appl/arduino/readme.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Authore: Andy Kirby (andy@kirbyand.co.uk), Based on the Amforth Application Template.
-Licensing: as per the Amforth Project.
-
-These are demo application templates for using standard off the shelf Arduino Boards (or Clones) as an Amforth development system. Three of the templates are useable with DIL devices for cheap entry level use or embeding into your own breadboard/stripboard deisgns.
-
-Models Described are:-
-
-Model Microcontroler Host Xtal DBG-LED Flash B-Load Ram Fuses (E,H,L)
-Mega ATMega 1280 uart0 16Mhz PB7 128K 512b/1k/2k/4k 8k F7 D9 FF
-Diecimila ATMega 168 uart0 16Mhz PB5 16K 128b/256b/512b/1k 1k F9 DD FF
-Duemilanove ATMega 328 uart0 16Mhz PB5 32k 256b/512b/1k/2k 2k 05 D9 FF
-Uno ATMega 328 uart0 16Mhz PB5 32k 256b/512b/1k/2k 2k 05 D9 FF
-Sanguino ATMega 644 uart0 16Mhz PB0 64k 512/1k/2k/4k 4k FD F9 FF
-
-
-Notes
-
-0. double check the fuses settings. Esp. the duemilanove may have the wrong settings. set the HFuse to 0xd9
- to maximize the bootloader size.
-
-1. Whilst most errors and problems you encounter are likely to be those I have created rather than the original
- code on which this is based, please report forward comments, feedback, reports, bugs, fixes and patches etc
- through the Amforth Projects development mailing lists and forums etc.
-
-2. The binary Amforth images cannot be loaded/programmed using the Arduino Bootloader. An ICSP programmer
- (avrisp, etc) must be used to load the image.
-
-3. The Arduino bootloader is over writen with the Amforth code and is no longer available after programing.
- To restore your board for use with the Arduino IDE you must overwrite the Amforth image with an Arduino
- Bootloader image.
-
-4. The Sanguino is not correctly speaking an Arduino Project design, but forms the basis of the Reprap
- controller designed and made popular by Makerbot. This processor/board is also notable for being the
- largest ATMega device available in a DIL format that makes it poular for prototyping and ammateur constructors.
-
-5. The 168 and 328 devices similar to note 4 above are available in DIL packaging making them popular for
- prototyping and ammateur constructors.
-
-6. The 1280 device is only available in surface mount options and is likely only to be found in commercialy
- produced boards and used by dedicated electronics enthusiasts.
-
-7. Whilst described as using a 328 device early versions of the Duemilanove may actualy have a 168 installed.
- This can be easily exchanged for a 328 if more resources are needed.
-
-8. The Diecimila board is also compatible with the 328 device commonly found in the newer Duemilanove board.
-
-9. For the arduino mega the content of the dict_appl.inc can be moved to dict_appl_core.inc. This gives more
- usable dictionary space.
-
-10. The UNO has the same controller as the duemilanove, the hexfiles are the same. \ No newline at end of file
diff --git a/amforth-6.5/appl/arduino/sanguino.asm b/amforth-6.5/appl/arduino/sanguino.asm
deleted file mode 100644
index ab95c11..0000000
--- a/amforth-6.5/appl/arduino/sanguino.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-; for a description, what can be done in this
-; file see ../template/template.asm. You may want to
-; copy that file to this one and edit it afterwards.
-
-.include "preamble.inc"
-
-.equ F_CPU = 16000000
-.include "drivers/usart_0.asm"
-
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/arduino/uno.asm b/amforth-6.5/appl/arduino/uno.asm
deleted file mode 100644
index 74a0d2b..0000000
--- a/amforth-6.5/appl/arduino/uno.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; for a description, what can be done in this
-; file see ../template/template.asm. You may want to
-; copy that file to this one and edit it afterwards.
-
-.include "preamble.inc"
-
-.equ F_CPU = 16000000
-.include "drivers/usart_0.asm"
-
-; settings for 1wire interface, if desired
-.equ OW_PORT=PORTB
-.EQU OW_BIT=4
-.include "drivers/1wire.asm"
-
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/arduino/uno.eep.hex b/amforth-6.5/appl/arduino/uno.eep.hex
deleted file mode 100644
index 0011602..0000000
--- a/amforth-6.5/appl/arduino/uno.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10003400FFFFBA0AC2018E00CE095C00B008AC0A08
-:0A004400FF024800EC3F01004800F5
-:06005C00020070065C06C4
-:100066007D3B680000000000FF08AF08AF080000F5
-:100076000A00A300B1007800930077020000640232
-:08008600C83CE73CD73C19001F
-:00000001FF
diff --git a/amforth-6.5/appl/arduino/uno.hex b/amforth-6.5/appl/arduino/uno.hex
deleted file mode 100644
index f0489b7..0000000
--- a/amforth-6.5/appl/arduino/uno.hex
+++ /dev/null
@@ -1,620 +0,0 @@
-:020000020000FC
-:0200040026D103
-:0200080024D101
-:02000C0022D1FF
-:0200100020D1FD
-:020014001ED1FB
-:020018001CD1F9
-:02001C001AD1F7
-:0200200018D1F5
-:0200240016D1F3
-:0200280014D1F1
-:02002C0012D1EF
-:0200300010D1ED
-:020034000ED1EB
-:020038000CD1E9
-:02003C000AD1E7
-:0200400008D1E5
-:0200440006D1E3
-:0200480004D1E1
-:02004C0002D1DF
-:0200500000D1DD
-:02005400FED0DC
-:02005800FCD0DA
-:02005C00FAD0D8
-:02006000F8D0D6
-:10006400F6D00008000400701A000A0041546D65BF
-:1000740067613332385007FF3E72782D627566002F
-:1000840000004400082F10911001E0E0F1E0E10FBE
-:10009400F31D008313951F7010931001899199919A
-:1000A4000C94043806FF6973722D72783D00003891
-:1000B4003C38C6009738B0383C380300DE3F35384A
-:1000C4006400373D43001F3800383C3859003C3841
-:1000D4002400A43C3C3800013C3816005339973EB8
-:1000E4001F3806FF72782D6275665400003893003D
-:1000F400353879003C3811019738B0383C38000164
-:100104009C399738C3382E3A3C380F00123A3C38A1
-:1001140011018C381F3807FF72783F2D6275660015
-:10012400730000382F3D3C38110197383C381001DA
-:10013400973812391F3807FF74782D706F6C6C0074
-:100144008D000038B1003538A4003C38C6008C3826
-:100154001F3808FF74783F2D706F6C6C9D00003859
-:100164002F3D3C38C00097383C382000123A1F38E5
-:1001740004FF75627272AB006E388C009F3DA93D1E
-:1001840006FF2B7573617274BA0000383C3898000E
-:100194003C38C1008C383C3806003C38C2008C38EE
-:1001A400BE00B038F83A3C38C5008C383C38C4003E
-:1001B4008C3866001F3808FF31772E7265736574BA
-:1001C400C200E4009A938A93249A2C98E0E8F7E01A
-:1001D4003197F1F71FB7F8942C9A2498E0E0F1E0F6
-:1001E4003197F1F783B184FF9FEF1FBF24982C98B8
-:1001F400E0E8F6E03197F1F7892F0C94043807FF13
-:1002040031772E736C6F7400DD0008012C98249AEA
-:100214001FB7F894E8E1F0E03197F1F788948795F7
-:1002240010F42C9A2498E4E2F0E03197F1F703B14A
-:1002340004FD8068ECECF0E03197F1F72C9A2498F7
-:0E024400E8E0F0E03197F1F71FBF0C940438AA
-:040000000C94383DE7
-:100252000A920FB60A920F900F900A94B02CFF9355
-:10026200EF93E2E1F1E00694E00DF31D00800394C8
-:100272000082EF91FF9109900FBE0990089502FF4D
-:100282006D2B01010038C63F143C1F3803FF756413
-:100292002A0040010038B038FE38DF39D838C33878
-:1002A200F538DF39E0389C391F3804FF756D617805
-:1002B20047010038C83E5B3935386001C338D83849
-:1002C2001F3804FF756D696E56010038C83E6639E5
-:1002D20035386C01C338D8381F3800383C380080B4
-:1002E200123A193935387701E53F1F384A391F3834
-:1002F2000AFF6E616D653E666C616773620100386C
-:10030200CA3B3C3800FF123A1F3803FF7665720081
-:1003120079010038DA020304AD3FBC3E7838E802C6
-:10032200403FC63F210329033C382E0012033F03FE
-:100332004A033904BC3E8038AD3FF00203041F3843
-:1003420004FF6E6F6F70860100381F3806FF756EEE
-:1003520075736564A10100388C3A223F92391F38C7
-:100362000200746FA70100384804CF3FB63E7838C8
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diff --git a/amforth-6.5/appl/arduino/uno.lst b/amforth-6.5/appl/arduino/uno.lst
deleted file mode 100644
index ee0e8b2..0000000
--- a/amforth-6.5/appl/arduino/uno.lst
+++ /dev/null
@@ -1,10263 +0,0 @@
-
-AVRASM ver. 2.1.52 uno.asm Sun Apr 30 20:10:12 2017
-
-uno.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega328p\device.asm'
-../../avr8/devices/atmega328p\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m328Pdef.inc'
-uno.asm(8): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-uno.asm(13): Including file '../../avr8\drivers/1wire.asm'
-uno.asm(15): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(11): Including file '../../avr8\dict/appl_4k.inc'
-../../avr8\dict/appl_4k.inc(1): Including file '../../common\words/ver.asm'
-../../avr8\dict/appl_4k.inc(4): Including file '../../common\words/noop.asm'
-../../avr8\dict/appl_4k.inc(5): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/appl_4k.inc(6): Including file '../../common\words/to.asm'
-../../avr8\dict/appl_4k.inc(7): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/appl_4k.inc(8): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/appl_4k.inc(9): Including file '../../common\words/star.asm'
-../../avr8\dict/appl_4k.inc(10): Including file '../../avr8\words/j.asm'
-../../avr8\dict/appl_4k.inc(11): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/appl_4k.inc(12): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/appl_4k.inc(13): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/appl_4k.inc(14): Including file '../../common\words/2swap.asm'
-../../avr8\dict/appl_4k.inc(15): Including file '../../common\words/tib.asm'
-../../avr8\dict/appl_4k.inc(16): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/appl_4k.inc(20): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/appl_4k.inc(21): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/appl_4k.inc(22): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/appl_4k.inc(23): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/appl_4k.inc(24): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/appl_4k.inc(25): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/appl_4k.inc(26): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/appl_4k.inc(27): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/appl_4k.inc(28): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/appl_4k.inc(30): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/appl_4k.inc(31): Including file '../../common\words/hold.asm'
-../../avr8\dict/appl_4k.inc(32): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/appl_4k.inc(33): Including file '../../common\words/sharp.asm'
-../../avr8\dict/appl_4k.inc(34): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/appl_4k.inc(35): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/appl_4k.inc(36): Including file '../../common\words/sign.asm'
-../../avr8\dict/appl_4k.inc(37): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/appl_4k.inc(38): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/appl_4k.inc(39): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/appl_4k.inc(40): Including file '../../common\words/dot.asm'
-../../avr8\dict/appl_4k.inc(41): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/appl_4k.inc(42): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/appl_4k.inc(43): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/appl_4k.inc(44): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/appl_4k.inc(46): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/appl_4k.inc(47): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/appl_4k.inc(48): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/appl_4k.inc(49): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/appl_4k.inc(50): Including file '../../common\words/type.asm'
-../../avr8\dict/appl_4k.inc(51): Including file '../../common\words/tick.asm'
-../../avr8\dict/appl_4k.inc(53): Including file '../../common\words/cskip.asm'
-../../avr8\dict/appl_4k.inc(54): Including file '../../common\words/cscan.asm'
-../../avr8\dict/appl_4k.inc(55): Including file '../../common\words/accept.asm'
-../../avr8\dict/appl_4k.inc(56): Including file '../../common\words/refill.asm'
-../../avr8\dict/appl_4k.inc(57): Including file '../../common\words/char.asm'
-../../avr8\dict/appl_4k.inc(58): Including file '../../common\words/number.asm'
-../../avr8\dict/appl_4k.inc(59): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/appl_4k.inc(60): Including file '../../common\words/set-base.asm'
-../../avr8\dict/appl_4k.inc(61): Including file '../../common\words/to-number.asm'
-../../avr8\dict/appl_4k.inc(62): Including file '../../common\words/parse.asm'
-../../avr8\dict/appl_4k.inc(63): Including file '../../common\words/source.asm'
-../../avr8\dict/appl_4k.inc(64): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/appl_4k.inc(65): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/appl_4k.inc(66): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/appl_4k.inc(67): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/appl_4k.inc(68): Including file '../../common\words/depth.asm'
-../../avr8\dict/appl_4k.inc(69): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/appl_4k.inc(70): Including file '../../common\words/recognize.asm'
-../../avr8\dict/appl_4k.inc(71): Including file '../../common\words/interpret.asm'
-../../avr8\dict/appl_4k.inc(72): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/appl_4k.inc(73): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/appl_4k.inc(74): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/appl_4k.inc(75): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/appl_4k.inc(76): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/appl_4k.inc(77): Including file '../../common\words/name2string.asm'
-../../avr8\dict/appl_4k.inc(78): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/appl_4k.inc(79): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/appl_4k.inc(81): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(4): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(104): Including file '../../avr8\dict/core_4k.inc'
-../../avr8\dict/core_4k.inc(3): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_4k.inc(4): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_4k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_4k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_4k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_4k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_4k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_4k.inc(10): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_4k.inc(11): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_4k.inc(12): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_4k.inc(13): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_4k.inc(14): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_4k.inc(17): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_4k.inc(18): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_4k.inc(19): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_4k.inc(21): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_4k.inc(22): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_4k.inc(23): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_4k.inc(24): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_4k.inc(26): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_4k.inc(27): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_4k.inc(28): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_4k.inc(31): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_4k.inc(32): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_4k.inc(33): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_4k.inc(34): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_4k.inc(35): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_4k.inc(36): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_4k.inc(37): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_4k.inc(38): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_4k.inc(39): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_4k.inc(41): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_4k.inc(42): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_4k.inc(45): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_4k.inc(46): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_4k.inc(47): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_4k.inc(48): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_4k.inc(50): Including file '../../common\words/min.asm'
-../../avr8\dict/core_4k.inc(51): Including file '../../common\words/max.asm'
-../../avr8\dict/core_4k.inc(52): Including file '../../common\words/within.asm'
-../../avr8\dict/core_4k.inc(54): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_4k.inc(55): Including file '../../common\words/words.asm'
-../../avr8\dict/core_4k.inc(57): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_4k.inc(58): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_4k.inc(59): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_4k.inc(61): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_4k.inc(62): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_4k.inc(63): Including file '../../common\words/base.asm'
-../../avr8\dict/core_4k.inc(65): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_4k.inc(67): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_4k.inc(68): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_4k.inc(69): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_4k.inc(71): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_4k.inc(72): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_4k.inc(73): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_4k.inc(74): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_4k.inc(75): Including file '../../common\words/key.asm'
-../../avr8\dict/core_4k.inc(76): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_4k.inc(78): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_4k.inc(79): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_4k.inc(80): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_4k.inc(81): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_4k.inc(83): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_4k.inc(84): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_4k.inc(85): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_4k.inc(86): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_4k.inc(88): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_4k.inc(89): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_4k.inc(90): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_4k.inc(92): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_4k.inc(93): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_4k.inc(94): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_4k.inc(95): Including file '../../common\words/space.asm'
-../../avr8\dict/core_4k.inc(96): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_4k.inc(97): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_4k.inc(98): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_USART0 = 0
- .set WANT_TWI = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_SPI = 0
- .set WANT_WATCHDOG = 0
- .set WANT_CPU = 0
- .set WANT_EEPROM = 0
- .equ intvecsize = 2 ; please verify; flash size: 32768 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d126 rcall isr ; External Interrupt Request 0
- .org 4
-000004 d124 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d122 rcall isr ; Pin Change Interrupt Request 0
- .org 8
-000008 d120 rcall isr ; Pin Change Interrupt Request 0
- .org 10
-00000a d11e rcall isr ; Pin Change Interrupt Request 1
- .org 12
-00000c d11c rcall isr ; Watchdog Time-out Interrupt
- .org 14
-00000e d11a rcall isr ; Timer/Counter2 Compare Match A
- .org 16
-000010 d118 rcall isr ; Timer/Counter2 Compare Match A
- .org 18
-000012 d116 rcall isr ; Timer/Counter2 Overflow
- .org 20
-000014 d114 rcall isr ; Timer/Counter1 Capture Event
- .org 22
-000016 d112 rcall isr ; Timer/Counter1 Compare Match A
- .org 24
-000018 d110 rcall isr ; Timer/Counter1 Compare Match B
- .org 26
-00001a d10e rcall isr ; Timer/Counter1 Overflow
- .org 28
-00001c d10c rcall isr ; TimerCounter0 Compare Match A
- .org 30
-00001e d10a rcall isr ; TimerCounter0 Compare Match B
- .org 32
-000020 d108 rcall isr ; Timer/Couner0 Overflow
- .org 34
-000022 d106 rcall isr ; SPI Serial Transfer Complete
- .org 36
-000024 d104 rcall isr ; USART Rx Complete
- .org 38
-000026 d102 rcall isr ; USART, Data Register Empty
- .org 40
-000028 d100 rcall isr ; USART Tx Complete
- .org 42
-00002a d0fe rcall isr ; ADC Conversion Complete
- .org 44
-00002c d0fc rcall isr ; EEPROM Ready
- .org 46
-00002e d0fa rcall isr ; Analog Comparator
- .org 48
-000030 d0f8 rcall isr ; Two-wire Serial Interface
- .org 50
-000032 d0f6 rcall isr ; Store Program Memory Read
- .equ INTVECTORS = 26
- .nooverlap
-
- ; compatability layer (maybe empty)
- .equ SPMEN = SELFPRGEN
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000033 0800 .dw 2048
- mcu_eepromsize:
-000034 0400 .dw 1024
- mcu_maxdp:
-000035 7000 .dw 28672
- mcu_numints:
-000036 001a .dw 26
- mcu_name:
-000037 000a .dw 10
-000038 5441
-000039 656d
-00003a 6167
-00003b 3233
-00003c 5038 .db "ATmega328P"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .equ F_CPU = 16000000
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-00003d ff07 .dw $ff07
-00003e 723e
-00003f 2d78
-000040 7562
-000041 0066 .db ">rx-buf",0
-000042 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000043 0044 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000044 2f08 mov temp0, tosl
-000045 9110 0110 lds temp1, usart_rx_in
-000047 e0e0 ldi zl, low(usart_rx_data)
-000048 e0f1 ldi zh, high(usart_rx_data)
-000049 0fe1 add zl, temp1
-00004a 1df3 adc zh, zeroh
-00004b 8300 st Z, temp0
-00004c 9513 inc temp1
-00004d 701f andi temp1,usart_rx_mask
-00004e 9310 0110 sts usart_rx_in, temp1
-000050 9189
-000051 9199 loadtos
-000052 940c 3804 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000054 ff06 .dw $ff06
-000055 7369
-000056 2d72
-000057 7872 .db "isr-rx"
-000058 003d .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-000059 3800 .dw DO_COLON
- usart_rx_isr:
-00005a 383c .dw XT_DOLITERAL
-00005b 00c6 .dw usart_data
-00005c 3897 .dw XT_CFETCH
-00005d 38b0 .dw XT_DUP
-00005e 383c .dw XT_DOLITERAL
-00005f 0003 .dw 3
-000060 3fde .dw XT_EQUAL
-000061 3835 .dw XT_DOCONDBRANCH
-000062 0064 .dw usart_rx_isr1
-000063 3d37 .dw XT_COLD
- usart_rx_isr1:
-000064 0043 .dw XT_TO_RXBUF
-000065 381f .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-000066 3800 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-000067 383c
-000068 0059 .dw XT_DOLITERAL, XT_ISR_RX
-000069 383c
-00006a 0024 .dw XT_DOLITERAL, URXCaddr
-00006b 3ca4 .dw XT_INTSTORE
-
-00006c 383c .dw XT_DOLITERAL
-00006d 0100 .dw usart_rx_data
-00006e 383c .dw XT_DOLITERAL
-00006f 0016 .dw usart_rx_size + 6
-000070 3953 .dw XT_ZERO
-000071 3e97 .dw XT_FILL
-000072 381f .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000073 ff06 .dw $ff06
-000074 7872
-000075 622d
-000076 6675 .db "rx-buf"
-000077 0054 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-000078 3800 .dw DO_COLON
- PFA_RX_BUFFER:
-000079 0093 .dw XT_RXQ_BUFFER
-00007a 3835 .dw XT_DOCONDBRANCH
-00007b 0079 .dw PFA_RX_BUFFER
-00007c 383c .dw XT_DOLITERAL
-00007d 0111 .dw usart_rx_out
-00007e 3897 .dw XT_CFETCH
-00007f 38b0 .dw XT_DUP
-000080 383c .dw XT_DOLITERAL
-000081 0100 .dw usart_rx_data
-000082 399c .dw XT_PLUS
-000083 3897 .dw XT_CFETCH
-000084 38c3 .dw XT_SWAP
-000085 3a2e .dw XT_1PLUS
-000086 383c .dw XT_DOLITERAL
-000087 000f .dw usart_rx_mask
-000088 3a12 .dw XT_AND
-000089 383c .dw XT_DOLITERAL
-00008a 0111 .dw usart_rx_out
-00008b 388c .dw XT_CSTORE
-00008c 381f .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-00008d ff07 .dw $ff07
-00008e 7872
-00008f 2d3f
-000090 7562
-000091 0066 .db "rx?-buf",0
-000092 0073 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-000093 3800 .dw DO_COLON
- PFA_RXQ_BUFFER:
-000094 3d2f .dw XT_PAUSE
-000095 383c .dw XT_DOLITERAL
-000096 0111 .dw usart_rx_out
-000097 3897 .dw XT_CFETCH
-000098 383c .dw XT_DOLITERAL
-000099 0110 .dw usart_rx_in
-00009a 3897 .dw XT_CFETCH
-00009b 3912 .dw XT_NOTEQUAL
-00009c 381f .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-00009d ff07 .dw $ff07
-00009e 7874
-00009f 702d
-0000a0 6c6f
-0000a1 006c .db "tx-poll",0
-0000a2 008d .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000a3 3800 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000a4 00b1 .dw XT_TXQ_POLL
-0000a5 3835 .dw XT_DOCONDBRANCH
-0000a6 00a4 .dw PFA_TX_POLL
- ; send to usart
-0000a7 383c .dw XT_DOLITERAL
-0000a8 00c6 .dw USART_DATA
-0000a9 388c .dw XT_CSTORE
-0000aa 381f .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000ab ff08 .dw $ff08
-0000ac 7874
-0000ad 2d3f
-0000ae 6f70
-0000af 6c6c .db "tx?-poll"
-0000b0 009d .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000b1 3800 .dw DO_COLON
- PFA_TXQ_POLL:
-0000b2 3d2f .dw XT_PAUSE
-0000b3 383c .dw XT_DOLITERAL
-0000b4 00c0 .dw USART_A
-0000b5 3897 .dw XT_CFETCH
-0000b6 383c .dw XT_DOLITERAL
-0000b7 0020 .dw bm_USART_TXRD
-0000b8 3a12 .dw XT_AND
-0000b9 381f .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000ba ff04 .dw $ff04
-0000bb 6275
-0000bc 7272 .db "ubrr"
-0000bd 00ab .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000be 386e .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000bf 008c .dw EE_UBRRVAL
-0000c0 3d9f .dw XT_EDEFERFETCH
-0000c1 3da9 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000c2 ff06 .dw $ff06
-0000c3 752b
-0000c4 6173
-0000c5 7472 .db "+usart"
-0000c6 00ba .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000c7 3800 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000c8 383c .dw XT_DOLITERAL
-0000c9 0098 .dw USART_B_VALUE
-0000ca 383c .dw XT_DOLITERAL
-0000cb 00c1 .dw USART_B
-0000cc 388c .dw XT_CSTORE
-
-0000cd 383c .dw XT_DOLITERAL
-0000ce 0006 .dw USART_C_VALUE
-0000cf 383c .dw XT_DOLITERAL
-0000d0 00c2 .dw USART_C | bm_USARTC_en
-0000d1 388c .dw XT_CSTORE
-
-0000d2 00be .dw XT_UBRR
-0000d3 38b0 .dw XT_DUP
-0000d4 3af8 .dw XT_BYTESWAP
-0000d5 383c .dw XT_DOLITERAL
-0000d6 00c5 .dw BAUDRATE_HIGH
-0000d7 388c .dw XT_CSTORE
-0000d8 383c .dw XT_DOLITERAL
-0000d9 00c4 .dw BAUDRATE_LOW
-0000da 388c .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000db 0066 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000dc 381f .dw XT_EXIT
-
- ; settings for 1wire interface, if desired
- .equ OW_PORT=PORTB
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-0000dd ff08 .dw $ff08
-0000de 7731
-0000df 722e
-0000e0 7365
-0000e1 7465 .db "1w.reset"
-0000e2 00c2 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-0000e3 00e4 .dw PFA_OW_RESET
- PFA_OW_RESET:
-0000e4 939a
-0000e5 938a savetos
- ; setup to output
-0000e6 9a24 sbi OW_DDR, OW_BIT
- ; Pull output low
-0000e7 982c cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-0000e8 e8e0
-0000e9 e0f7
-0000ea 9731
-0000eb f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-0000ec b71f in temp1, SREG
-0000ed 94f8 cli
- ; Pull output high
-0000ee 9a2c sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-0000ef 9824 cbi OW_DDR, OW_BIT
-0000f0 e0e0
-0000f1 e0f1
-0000f2 9731
-0000f3 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-0000f4 b183 in tosl, OW_PIN
-0000f5 ff84 sbrs tosl, OW_BIT
-0000f6 ef9f ser tosh
- ; End critical timing period, enable interrupts
-0000f7 bf1f out SREG, temp1
- ; release bus
-0000f8 9824 cbi OW_DDR, OW_BIT
-0000f9 982c cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-0000fa e8e0
-0000fb e0f6
-0000fc 9731
-0000fd f7f1 DELAY 416
- ; we now have the result flag in TOS
-0000fe 2f89 mov tosl, tosh
-0000ff 940c 3804 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-000101 ff07 .dw $ff07
-000102 7731
-000103 732e
-000104 6f6c
-000105 0074 .db "1w.slot",0
-000106 00dd .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-000107 0108 .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-000108 982c cbi OW_PORT, OW_BIT
-000109 9a24 sbi OW_DDR, OW_BIT
- ; disable interrupts
-00010a b71f in temp1, SREG
-00010b 94f8 cli
-00010c e1e8
-00010d e0f0
-00010e 9731
-00010f f7f1 DELAY 6 ; DELAY A
- ; check bit
-000110 9488 clc
-000111 9587 ror tosl
-000112 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000113 9a2c sbi OW_PORT, OW_BIT
-000114 9824 cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-000115 e2e4
-000116 e0f0
-000117 9731
-000118 f7f1 DELAY 9 ; wait DELAY E to sample
-000119 b103 in temp0, OW_PIN
-00011a fd04 sbrc temp0, OW_BIT
-00011b 6880 ori tosl, $80
-
-00011c ecec
-00011d e0f0
-00011e 9731
-00011f f7f1 DELAY 51 ; DELAY B
-000120 9a2c sbi OW_PORT, OW_BIT ; release bus
-000121 9824 cbi OW_DDR, OW_BIT
-000122 e0e8
-000123 e0f0
-000124 9731
-000125 f7f1 delay 2
- ; re-enable interrupts
-000126 bf1f out SREG, temp1
-000127 940c 3804 jmp_ DO_NEXT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 3d38 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-000129 920a st -Y, r0
-00012a b60f in r0, SREG
-00012b 920a st -Y, r0
- .if (pclen==3)
- .endif
-00012c 900f pop r0
-00012d 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-00012e 940a dec r0
- .if intvecsize == 1 ;
- .endif
-00012f 2cb0 mov isrflag, r0
-000130 93ff push zh
-000131 93ef push zl
-000132 e1e2 ldi zl, low(intcnt)
-000133 e0f1 ldi zh, high(intcnt)
-000134 9406 lsr r0 ; we use byte addresses in the counter array, not words
-000135 0de0 add zl, r0
-000136 1df3 adc zh, zeroh
-000137 8000 ld r0, Z
-000138 9403 inc r0
-000139 8200 st Z, r0
-00013a 91ef pop zl
-00013b 91ff pop zh
-
-00013c 9009 ld r0, Y+
-00013d be0f out SREG, r0
-00013e 9009 ld r0, Y+
-00013f 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000140 ff02 .dw $ff02
-000141 2b6d .db "m+"
-000142 0101 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000143 3800 .dw DO_COLON
- PFA_MPLUS:
-000144 3fc6 .dw XT_S2D
-000145 3c14 .dw XT_DPLUS
-000146 381f .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-000147 ff03 .dw $ff03
-000148 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-000149 002a .db "ud*"
-00014a 0140 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-00014b 3800 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-00014c 38b0
-00014d 38fe
-00014e 39df
-00014f 38d8 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000150 38c3
-000151 38f5
-000152 39df
-000153 38e0
-000154 399c
-000155 381f .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-000156 ff04 .dw $ff04
-000157 6d75
-000158 7861 .db "umax"
-000159 0147 .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00015a 3800 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-00015b 3ec8
-00015c 395b .DW XT_2DUP,XT_ULESS
-00015d 3835 .dw XT_DOCONDBRANCH
-00015e 0160 DEST(UMAX1)
-00015f 38c3 .DW XT_SWAP
-000160 38d8 UMAX1: .DW XT_DROP
-000161 381f .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000162 ff04 .dw $ff04
-000163 6d75
-000164 6e69 .db "umin"
-000165 0156 .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-000166 3800 .dw DO_COLON
- PFA_UMIN:
- .endif
-000167 3ec8
-000168 3966 .DW XT_2DUP,XT_UGREATER
-000169 3835 .dw XT_DOCONDBRANCH
-00016a 016c DEST(UMIN1)
-00016b 38c3 .DW XT_SWAP
-00016c 38d8 UMIN1: .DW XT_DROP
-00016d 381f .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-00016e 3800 .dw DO_COLON
- PFA_IMMEDIATEQ:
-00016f 383c .dw XT_DOLITERAL
-000170 8000 .dw $8000
-000171 3a12 .dw XT_AND
-000172 3919 .dw XT_ZEROEQUAL
-000173 3835 .dw XT_DOCONDBRANCH
-000174 0177 DEST(IMMEDIATEQ1)
-000175 3fe5 .dw XT_ONE
-000176 381f .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-000177 394a .dw XT_TRUE
-000178 381f .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-000179 ff0a .dw $ff0a
-00017a 616e
-00017b 656d
-00017c 663e
-00017d 616c
-00017e 7367 .db "name>flags"
-00017f 0162 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000180 3800 .dw DO_COLON
- PFA_NAME2FLAGS:
-000181 3bca .dw XT_FETCHI ; skip to link field
-000182 383c .dw XT_DOLITERAL
-000183 ff00 .dw $ff00
-000184 3a12 .dw XT_AND
-000185 381f .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .elif AMFORTH_NRWW_SIZE > 4000
- .include "dict/appl_4k.inc"
-
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-000186 ff03 .dw $ff03
-000187 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-000188 0072 .db "ver"
-000189 0179 .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00018a 3800 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-00018b 02da .dw XT_ENV_FORTHNAME
-00018c 0403 .dw XT_ITYPE
-00018d 3fad .dw XT_SPACE
-00018e 3ebc .dw XT_BASE
-00018f 3878 .dw XT_FETCH
-
-000190 02e8 .dw XT_ENV_FORTHVERSION
-000191 3f40 .dw XT_DECIMAL
-000192 3fc6 .dw XT_S2D
-000193 0321 .dw XT_L_SHARP
-000194 0329 .dw XT_SHARP
-000195 383c .dw XT_DOLITERAL
-000196 002e .dw '.'
-000197 0312 .dw XT_HOLD
-000198 033f .dw XT_SHARP_S
-000199 034a .dw XT_SHARP_G
-00019a 0439 .dw XT_TYPE
-00019b 3ebc .dw XT_BASE
-00019c 3880 .dw XT_STORE
-00019d 3fad .dw XT_SPACE
-00019e 02f0 .dw XT_ENV_CPU
-00019f 0403 .dw XT_ITYPE
-
-0001a0 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-0001a1 ff04 .dw $ff04
-0001a2 6f6e
-0001a3 706f .db "noop"
-0001a4 0186 .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-0001a5 3800 .dw DO_COLON
- PFA_NOOP:
- .endif
-0001a6 381f .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-0001a7 ff06 .dw $ff06
-0001a8 6e75
-0001a9 7375
-0001aa 6465 .db "unused"
-0001ab 01a1 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-0001ac 3800 .dw DO_COLON
- PFA_UNUSED:
-0001ad 3a8c .dw XT_SP_FETCH
-0001ae 3f22 .dw XT_HERE
-0001af 3992 .dw XT_MINUS
-0001b0 381f .dw XT_EXIT
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-0001b1 0002 .dw $0002
-0001b2 6f74 .db "to"
-0001b3 01a7 .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-0001b4 3800 .dw DO_COLON
- PFA_TO:
- .endif
-0001b5 0448 .dw XT_TICK
-0001b6 3fcf .dw XT_TO_BODY
-0001b7 3eb6 .dw XT_STATE
-0001b8 3878 .dw XT_FETCH
-0001b9 3835 .dw XT_DOCONDBRANCH
-0001ba 01c5 DEST(PFA_TO1)
-0001bb 075c .dw XT_COMPILE
-0001bc 01bf .dw XT_DOTO
-0001bd 0767 .dw XT_COMMA
-0001be 381f .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-0001bf 3800 .dw DO_COLON
- PFA_DOTO:
- .endif
-0001c0 38f5 .dw XT_R_FROM
-0001c1 38b0 .dw XT_DUP
-0001c2 01d1 .dw XT_ICELLPLUS
-0001c3 38fe .dw XT_TO_R
-0001c4 3bca .dw XT_FETCHI
- PFA_TO1:
-0001c5 38b0 .dw XT_DUP
-0001c6 01d1 .dw XT_ICELLPLUS
-0001c7 01d1 .dw XT_ICELLPLUS
-0001c8 3bca .dw XT_FETCHI
-0001c9 3829 .dw XT_EXECUTE
-0001ca 381f .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-0001cb ff07 .dw $FF07
-0001cc 2d69
-0001cd 6563
-0001ce 6c6c
-0001cf 002b .db "i-cell+",0
-0001d0 01b1 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-0001d1 3800 .dw DO_COLON
- PFA_ICELLPLUS:
-0001d2 3a2e .dw XT_1PLUS
-0001d3 381f .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-0001d4 ff08 .dw $ff08
-0001d5 6369
-0001d6 6d6f
-0001d7 6170
-0001d8 6572 .db "icompare"
-0001d9 01cb .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-0001da 3800 .dw DO_COLON
- PFA_ICOMPARE:
-0001db 38fe .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-0001dc 38ce .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-0001dd 38f5 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-0001de 3912 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-0001df 3835 .dw XT_DOCONDBRANCH
-0001e0 01e5 .dw PFA_ICOMPARE_SAMELEN
-0001e1 3ed1 .dw XT_2DROP
-0001e2 38d8 .dw XT_DROP
-0001e3 394a .dw XT_TRUE
-0001e4 381f .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-0001e5 38c3 .dw XT_SWAP ; ( -- r-addr f-addr len )
-0001e6 3953 .dw XT_ZERO
-0001e7 0826 .dw XT_QDOCHECK
-0001e8 3835 .dw XT_DOCONDBRANCH
-0001e9 0208 .dw PFA_ICOMPARE_DONE
-0001ea 3a9a .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-0001eb 38ce .dw XT_OVER
-0001ec 3878 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-0001ed 38ce .dw XT_OVER
-0001ee 3bca .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-0001ef 38b0 .dw XT_DUP
- ;.dw XT_BYTESWAP
-0001f0 383c .dw XT_DOLITERAL
-0001f1 0100 .dw $100
-0001f2 395b .dw XT_ULESS
-0001f3 3835 .dw XT_DOCONDBRANCH
-0001f4 01f9 .dw PFA_ICOMPARE_LASTCELL
-0001f5 38c3 .dw XT_SWAP
-0001f6 383c .dw XT_DOLITERAL
-0001f7 00ff .dw $00FF
-0001f8 3a12 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-0001f9 3912 .dw XT_NOTEQUAL
-0001fa 3835 .dw XT_DOCONDBRANCH
-0001fb 0200 .dw PFA_ICOMPARE_NEXTLOOP
-0001fc 3ed1 .dw XT_2DROP
-0001fd 394a .dw XT_TRUE
-0001fe 3ad3 .dw XT_UNLOOP
-0001ff 381f .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-000200 3a2e .dw XT_1PLUS
-000201 38c3 .dw XT_SWAP
-000202 3c8f .dw XT_CELLPLUS
-000203 38c3 .dw XT_SWAP
-000204 383c .dw XT_DOLITERAL
-000205 0002 .dw 2
-000206 3ab9 .dw XT_DOPLUSLOOP
-000207 01eb .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-000208 3ed1 .dw XT_2DROP
-000209 3953 .dw XT_ZERO
-00020a 381f .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-00020b ff01 .dw $ff01
-00020c 002a .db "*",0
-00020d 01d4 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-00020e 3800 .dw DO_COLON
- PFA_STAR:
- .endif
-
-00020f 39a5 .dw XT_MSTAR
-000210 38d8 .dw XT_DROP
-000211 381f .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-000212 ff01 .dw $FF01
-000213 006a .db "j",0
-000214 020b .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-000215 3800 .dw DO_COLON
- PFA_J:
-000216 3a75 .dw XT_RP_FETCH
-000217 383c .dw XT_DOLITERAL
-000218 0007 .dw 7
-000219 399c .dw XT_PLUS
-00021a 3878 .dw XT_FETCH
-00021b 3a75 .dw XT_RP_FETCH
-00021c 383c .dw XT_DOLITERAL
-00021d 0009 .dw 9
-00021e 399c .dw XT_PLUS
-00021f 3878 .dw XT_FETCH
-000220 399c .dw XT_PLUS
-000221 381f .dw XT_EXIT
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-000222 ff04 .dw $ff04
-000223 6164
-000224 7362 .db "dabs"
-000225 0212 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-000226 3800 .dw DO_COLON
- PFA_DABS:
-000227 38b0 .dw XT_DUP
-000228 3920 .dw XT_ZEROLESS
-000229 3835 .dw XT_DOCONDBRANCH
-00022a 022c .dw PFA_DABS1
-00022b 0233 .dw XT_DNEGATE
- PFA_DABS1:
-00022c 381f .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-00022d ff07 .dw $ff07
-00022e 6e64
-00022f 6765
-000230 7461
-000231 0065 .db "dnegate",0
-000232 0222 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-000233 3800 .dw DO_COLON
- PFA_DNEGATE:
-000234 3c3a .dw XT_DINVERT
-000235 3fe5 .dw XT_ONE
-000236 3953 .dw XT_ZERO
-000237 3c14 .dw XT_DPLUS
-000238 381f .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-000239 ff05 .dw $ff05
-00023a 6d63
-00023b 766f
-00023c 0065 .db "cmove",0
-00023d 022d .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-00023e 023f .dw PFA_CMOVE
- PFA_CMOVE:
-00023f 93bf push xh
-000240 93af push xl
-000241 91e9 ld zl, Y+
-000242 91f9 ld zh, Y+ ; addr-to
-000243 91a9 ld xl, Y+
-000244 91b9 ld xh, Y+ ; addr-from
-000245 2f09 mov temp0, tosh
-000246 2b08 or temp0, tosl
-000247 f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-000248 911d ld temp1, X+
-000249 9311 st Z+, temp1
-00024a 9701 sbiw tosl, 1
-00024b f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-00024c 91af pop xl
-00024d 91bf pop xh
-00024e 9189
-00024f 9199 loadtos
-000250 940c 3804 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-000252 ff05 .dw $ff05
-000253 7332
-000254 6177
-000255 0070 .db "2swap",0
-000256 0239 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-000257 3800 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-000258 38e0 .dw XT_ROT
-000259 38fe .dw XT_TO_R
-00025a 38e0 .dw XT_ROT
-00025b 38f5 .dw XT_R_FROM
-00025c 381f .dw XT_EXIT
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-00025d ff0a .dw $ff0a
-00025e 6572
-00025f 6966
-000260 6c6c
-000261 742d
-000262 6269 .db "refill-tib"
-000263 0252 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-000264 3800 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-000265 0280 .dw XT_TIB
-000266 383c .dw XT_DOLITERAL
-000267 005a .dw TIB_SIZE
-000268 0498 .dw XT_ACCEPT
-000269 0286 .dw XT_NUMBERTIB
-00026a 3880 .dw XT_STORE
-00026b 3953 .dw XT_ZERO
-00026c 3ee1 .dw XT_TO_IN
-00026d 3880 .dw XT_STORE
-00026e 394a .dw XT_TRUE ; -1
-00026f 381f .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-000270 ff0a .dw $FF0A
-000271 6f73
-000272 7275
-000273 6563
-000274 742d
-000275 6269 .db "source-tib"
-000276 025d .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-000277 3800 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-000278 0280 .dw XT_TIB
-000279 0286 .dw XT_NUMBERTIB
-00027a 3878 .dw XT_FETCH
-00027b 381f .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-00027c ff03 .dw $ff03
-00027d 6974
-00027e 0062 .db "tib",0
-00027f 0270 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-000280 3847 .dw PFA_DOVARIABLE
- PFA_TIB:
-000281 012c .dw ram_tib
- .dseg
-00012c ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-000282 ff04 .dw $ff04
-000283 7423
-000284 6269 .db "#tib"
-000285 027c .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-000286 3847 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-000287 0186 .dw ram_sharptib
- .dseg
-000186 ram_sharptib: .byte 2
- .cseg
- .endif
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-000288 ff06 .dw $ff06
-000289 6565
-00028a 723e
-00028b 6d61 .db "ee>ram"
-00028c 0282 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-00028d 3800 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-00028e 3953 .dw XT_ZERO
-00028f 3a9a .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-000290 38ce .dw XT_OVER
-000291 3b5e .dw XT_FETCHE
-000292 38ce .dw XT_OVER
-000293 3880 .dw XT_STORE
-000294 3c8f .dw XT_CELLPLUS
-000295 38c3 .dw XT_SWAP
-000296 3c8f .dw XT_CELLPLUS
-000297 38c3 .dw XT_SWAP
-000298 3ac8 .dw XT_DOLOOP
-000299 0290 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00029a 3ed1 .dw XT_2DROP
-00029b 381f .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-00029c ff08 .dw $ff08
-00029d 6e69
-00029e 7469
-00029f 722d
-0002a0 6d61 .db "init-ram"
-0002a1 0288 .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-0002a2 3800 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-0002a3 383c .dw XT_DOLITERAL
-0002a4 006a .dw EE_INITUSER
-0002a5 3b01 .dw XT_UP_FETCH
-0002a6 383c .dw XT_DOLITERAL
-0002a7 0022 .dw SYSUSERSIZE
-0002a8 3a03 .dw XT_2SLASH
-0002a9 028d .dw XT_EE2RAM
-0002aa 381f .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-0002ab ff0b .dw $ff0b
-0002ac 6e65
-0002ad 6976
-0002ae 6f72
-0002af 6d6e
-0002b0 6e65
-0002b1 0074 .db "environment",0
-0002b2 029c .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-0002b3 3847 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-0002b4 0044 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-0002b5 ff09 .dw $ff09
-0002b6 6f77
-0002b7 6472
-0002b8 696c
-0002b9 7473
-0002ba 0073 .db "wordlists",0
-0002bb 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-0002bc 3800 .dw DO_COLON
- PFA_ENVWORDLISTS:
-0002bd 383c .dw XT_DOLITERAL
-0002be 0008 .dw NUMWORDLISTS
-0002bf 381f .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-0002c0 ff04 .dw $ff04
-0002c1 702f
-0002c2 6461 .db "/pad"
-0002c3 02b5 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-0002c4 3800 .dw DO_COLON
- PFA_ENVSLASHPAD:
-0002c5 3a8c .dw XT_SP_FETCH
-0002c6 3ee7 .dw XT_PAD
-0002c7 3992 .dw XT_MINUS
-0002c8 381f .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-0002c9 ff05 .dw $ff05
-0002ca 682f
-0002cb 6c6f
-0002cc 0064 .db "/hold",0
-0002cd 02c0 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-0002ce 3800 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-0002cf 3ee7 .dw XT_PAD
-0002d0 3f22 .dw XT_HERE
-0002d1 3992 .dw XT_MINUS
-0002d2 381f .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-0002d3 ff0a .dw $ff0a
-0002d4 6f66
-0002d5 7472
-0002d6 2d68
-0002d7 616e
-0002d8 656d .db "forth-name"
-0002d9 02c9 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-0002da 3800 .dw DO_COLON
- PFA_EN_FORTHNAME:
-0002db 03d0 .dw XT_DOSLITERAL
-0002dc 0007 .dw 7
- .endif
-0002dd 6d61
-0002de 6f66
-0002df 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-0002e0 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-0002e1 381f .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-0002e2 ff07 .dw $ff07
-0002e3 6576
-0002e4 7372
-0002e5 6f69
-0002e6 006e .db "version",0
-0002e7 02d3 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-0002e8 3800 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-0002e9 383c .dw XT_DOLITERAL
-0002ea 0041 .dw 65
-0002eb 381f .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-0002ec ff03 .dw $ff03
-0002ed 7063
-0002ee 0075 .db "cpu",0
-0002ef 02e2 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-0002f0 3800 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-0002f1 383c .dw XT_DOLITERAL
-0002f2 0037 .dw mcu_name
-0002f3 042f .dw XT_ICOUNT
-0002f4 381f .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-0002f5 ff08 .dw $ff08
-0002f6 636d
-0002f7 2d75
-0002f8 6e69
-0002f9 6f66 .db "mcu-info"
-0002fa 02ec .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-0002fb 3800 .dw DO_COLON
- PFA_EN_MCUINFO:
-0002fc 383c .dw XT_DOLITERAL
-0002fd 0033 .dw mcu_info
-0002fe 381f .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-0002ff ff05 .dw $ff05
-000300 752f
-000301 6573
-000302 0072 .db "/user",0
-000303 02f5 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-000304 3800 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-000305 383c .dw XT_DOLITERAL
-000306 002c .dw SYSUSERSIZE + APPUSERSIZE
-000307 381f .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-000308 ff03 .dw $ff03
-000309 6c68
-00030a 0064 .db "hld",0
-00030b 02ab .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-00030c 3847 .dw PFA_DOVARIABLE
- PFA_HLD:
-00030d 0188 .dw ram_hld
-
- .dseg
-000188 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-00030e ff04 .dw $ff04
-00030f 6f68
-000310 646c .db "hold"
-000311 0308 .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-000312 3800 .dw DO_COLON
- PFA_HOLD:
- .endif
-000313 030c .dw XT_HLD
-000314 38b0 .dw XT_DUP
-000315 3878 .dw XT_FETCH
-000316 3a34 .dw XT_1MINUS
-000317 38b0 .dw XT_DUP
-000318 38fe .dw XT_TO_R
-000319 38c3 .dw XT_SWAP
-00031a 3880 .dw XT_STORE
-00031b 38f5 .dw XT_R_FROM
-00031c 388c .dw XT_CSTORE
-00031d 381f .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-00031e ff02 .dw $ff02
-00031f 233c .db "<#"
-000320 030e .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-000321 3800 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-000322 3ee7 .dw XT_PAD
-000323 030c .dw XT_HLD
-000324 3880 .dw XT_STORE
-000325 381f .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-000326 ff01 .dw $ff01
-000327 0023 .db "#",0
-000328 031e .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-000329 3800 .dw DO_COLON
- PFA_SHARP:
- .endif
-00032a 3ebc .dw XT_BASE
-00032b 3878 .dw XT_FETCH
-00032c 03a6 .dw XT_UDSLASHMOD
-00032d 38e0 .dw XT_ROT
-00032e 383c .dw XT_DOLITERAL
-00032f 0009 .dw 9
-000330 38ce .dw XT_OVER
-000331 396d .dw XT_LESS
-000332 3835 .dw XT_DOCONDBRANCH
-000333 0337 DEST(PFA_SHARP1)
-000334 383c .dw XT_DOLITERAL
-000335 0007 .dw 7
-000336 399c .dw XT_PLUS
- PFA_SHARP1:
-000337 383c .dw XT_DOLITERAL
-000338 0030 .dw 48 ; ASCII 0
-000339 399c .dw XT_PLUS
-00033a 0312 .dw XT_HOLD
-00033b 381f .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-00033c ff02 .dw $ff02
-00033d 7323 .db "#s"
-00033e 0326 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-00033f 3800 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000340 0329 .dw XT_SHARP
-000341 3ec8 .dw XT_2DUP
-000342 3a1b .dw XT_OR
-000343 3919 .dw XT_ZEROEQUAL
-000344 3835 .dw XT_DOCONDBRANCH
-000345 0340 DEST(NUMS1) ; PFA_SHARP_S
-000346 381f .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-000347 ff02 .dw $ff02
-000348 3e23 .db "#>"
-000349 033c .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00034a 3800 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-00034b 3ed1 .dw XT_2DROP
-00034c 030c .dw XT_HLD
-00034d 3878 .dw XT_FETCH
-00034e 3ee7 .dw XT_PAD
-00034f 38ce .dw XT_OVER
-000350 3992 .dw XT_MINUS
-000351 381f .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000352 ff04 .dw $ff04
-000353 6973
-000354 6e67 .db "sign"
-000355 0347 .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-000356 3800 .dw DO_COLON
- PFA_SIGN:
- .endif
-000357 3920 .dw XT_ZEROLESS
-000358 3835 .dw XT_DOCONDBRANCH
-000359 035d DEST(PFA_SIGN1)
-00035a 383c .dw XT_DOLITERAL
-00035b 002d .dw 45 ; ascii -
-00035c 0312 .dw XT_HOLD
- PFA_SIGN1:
-00035d 381f .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-00035e ff03 .dw $ff03
-00035f 2e64
-000360 0072 .db "d.r",0
-000361 0352 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000362 3800 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-000363 38fe .dw XT_TO_R
-000364 3ed9 .dw XT_TUCK
-000365 0226 .dw XT_DABS
-000366 0321 .dw XT_L_SHARP
-000367 033f .dw XT_SHARP_S
-000368 38e0 .dw XT_ROT
-000369 0356 .dw XT_SIGN
-00036a 034a .dw XT_SHARP_G
-00036b 38f5 .dw XT_R_FROM
-00036c 38ce .dw XT_OVER
-00036d 3992 .dw XT_MINUS
-00036e 3fb6 .dw XT_SPACES
-00036f 0439 .dw XT_TYPE
-000370 381f .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000371 ff02 .dw $ff02
-000372 722e .db ".r"
-000373 035e .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-000374 3800 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-000375 38fe .dw XT_TO_R
-000376 3fc6 .dw XT_S2D
-000377 38f5 .dw XT_R_FROM
-000378 0362 .dw XT_DDOTR
-000379 381f .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00037a ff02 .dw $ff02
-00037b 2e64 .db "d."
-00037c 0371 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-00037d 3800 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-00037e 3953 .dw XT_ZERO
-00037f 0362 .dw XT_DDOTR
-000380 3fad .dw XT_SPACE
-000381 381f .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-000382 ff01 .dw $ff01
-000383 002e .db ".",0
-000384 037a .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-000385 3800 .dw DO_COLON
- PFA_DOT:
- .endif
-000386 3fc6 .dw XT_S2D
-000387 037d .dw XT_DDOT
-000388 381f .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-000389 ff03 .dw $ff03
-00038a 6475
-00038b 002e .db "ud.",0
-00038c 0382 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-00038d 3800 .dw DO_COLON
- PFA_UDDOT:
- .endif
-00038e 3953 .dw XT_ZERO
-00038f 0396 .dw XT_UDDOTR
-000390 3fad .dw XT_SPACE
-000391 381f .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-000392 ff04 .dw $ff04
-000393 6475
-000394 722e .db "ud.r"
-000395 0389 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-000396 3800 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-000397 38fe .dw XT_TO_R
-000398 0321 .dw XT_L_SHARP
-000399 033f .dw XT_SHARP_S
-00039a 034a .dw XT_SHARP_G
-00039b 38f5 .dw XT_R_FROM
-00039c 38ce .dw XT_OVER
-00039d 3992 .dw XT_MINUS
-00039e 3fb6 .dw XT_SPACES
-00039f 0439 .dw XT_TYPE
-0003a0 381f .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-0003a1 ff06 .dw $ff06
-0003a2 6475
-0003a3 6d2f
-0003a4 646f .db "ud/mod"
-0003a5 0392 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-0003a6 3800 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-0003a7 38fe .dw XT_TO_R
-0003a8 3953 .dw XT_ZERO
-0003a9 3907 .dw XT_R_FETCH
-0003aa 39c1 .dw XT_UMSLASHMOD
-0003ab 38f5 .dw XT_R_FROM
-0003ac 38c3 .dw XT_SWAP
-0003ad 38fe .dw XT_TO_R
-0003ae 39c1 .dw XT_UMSLASHMOD
-0003af 38f5 .dw XT_R_FROM
-0003b0 381f .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-0003b1 ff06 .dw $ff06
-0003b2 6964
-0003b3 6967
-0003b4 3f74 .db "digit?"
-0003b5 03a1 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-0003b6 3800 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-0003b7 3f65 .dw XT_TOUPPER
-0003b8 38b0
-0003b9 383c
-0003ba 0039
-0003bb 3977
-0003bc 383c
-0003bd 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-0003be 3a12
-0003bf 399c
-0003c0 38b0
-0003c1 383c
-0003c2 0140
-0003c3 3977 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-0003c4 383c
-0003c5 0107
-0003c6 3a12
-0003c7 3992
-0003c8 383c
-0003c9 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-0003ca 3992
-0003cb 38b0
-0003cc 3ebc
-0003cd 3878
-0003ce 395b .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-0003cf 381f .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-0003d0 3800 .dw DO_COLON
- PFA_DOSLITERAL:
-0003d1 3907 .dw XT_R_FETCH ; ( -- addr )
-0003d2 042f .dw XT_ICOUNT
-0003d3 38f5 .dw XT_R_FROM
-0003d4 38ce .dw XT_OVER ; ( -- addr' n addr n)
-0003d5 3a2e .dw XT_1PLUS
-0003d6 3a03 .dw XT_2SLASH ; ( -- addr' n addr k )
-0003d7 399c .dw XT_PLUS ; ( -- addr' n addr'' )
-0003d8 3a2e .dw XT_1PLUS
-0003d9 38fe .dw XT_TO_R ; ( -- )
-0003da 381f .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-0003db ff02 .dw $ff02
-0003dc 2c73 .db "s",$2c
-0003dd 03b1 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-0003de 3800 .dw DO_COLON
- PFA_SCOMMA:
-0003df 38b0 .dw XT_DUP
-0003e0 03e2 .dw XT_DOSCOMMA
-0003e1 381f .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-0003e2 3800 .dw DO_COLON
- PFA_DOSCOMMA:
-0003e3 0767 .dw XT_COMMA
-0003e4 38b0 .dw XT_DUP ; ( --addr len len)
-0003e5 3a03 .dw XT_2SLASH ; ( -- addr len len/2
-0003e6 3ed9 .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003e7 3a0a .dw XT_2STAR ; ( -- addr len/2 len len'
-0003e8 3992 .dw XT_MINUS ; ( -- addr len/2 rem
-0003e9 38fe .dw XT_TO_R
-0003ea 3953 .dw XT_ZERO
-0003eb 0826 .dw XT_QDOCHECK
-0003ec 3835 .dw XT_DOCONDBRANCH
-0003ed 03f5 .dw PFA_SCOMMA2
-0003ee 3a9a .dw XT_DODO
- PFA_SCOMMA1:
-0003ef 38b0 .dw XT_DUP ; ( -- addr addr )
-0003f0 3878 .dw XT_FETCH ; ( -- addr c1c2 )
-0003f1 0767 .dw XT_COMMA ; ( -- addr )
-0003f2 3c8f .dw XT_CELLPLUS ; ( -- addr+cell )
-0003f3 3ac8 .dw XT_DOLOOP
-0003f4 03ef .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-0003f5 38f5 .dw XT_R_FROM
-0003f6 3927 .dw XT_GREATERZERO
-0003f7 3835 .dw XT_DOCONDBRANCH
-0003f8 03fc .dw PFA_SCOMMA3
-0003f9 38b0 .dw XT_DUP ; well, tricky
-0003fa 3897 .dw XT_CFETCH
-0003fb 0767 .dw XT_COMMA
- PFA_SCOMMA3:
-0003fc 38d8 .dw XT_DROP ; ( -- )
-0003fd 381f .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-0003fe ff05 .dw $ff05
-0003ff 7469
-000400 7079
-000401 0065 .db "itype",0
-000402 03db .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-000403 3800 .dw DO_COLON
- PFA_ITYPE:
-000404 38b0 .dw XT_DUP ; ( --addr len len)
-000405 3a03 .dw XT_2SLASH ; ( -- addr len len/2
-000406 3ed9 .dw XT_TUCK ; ( -- addr len/2 len len/2
-000407 3a0a .dw XT_2STAR ; ( -- addr len/2 len len'
-000408 3992 .dw XT_MINUS ; ( -- addr len/2 rem
-000409 38fe .dw XT_TO_R
-00040a 3953 .dw XT_ZERO
-00040b 0826 .dw XT_QDOCHECK
-00040c 3835 .dw XT_DOCONDBRANCH
-00040d 0417 .dw PFA_ITYPE2
-00040e 3a9a .dw XT_DODO
- PFA_ITYPE1:
-00040f 38b0 .dw XT_DUP ; ( -- addr addr )
-000410 3bca .dw XT_FETCHI ; ( -- addr c1c2 )
-000411 38b0 .dw XT_DUP
-000412 0424 .dw XT_LOWEMIT
-000413 0420 .dw XT_HIEMIT
-000414 3a2e .dw XT_1PLUS ; ( -- addr+cell )
-000415 3ac8 .dw XT_DOLOOP
-000416 040f .dw PFA_ITYPE1
- PFA_ITYPE2:
-000417 38f5 .dw XT_R_FROM
-000418 3927 .dw XT_GREATERZERO
-000419 3835 .dw XT_DOCONDBRANCH
-00041a 041e .dw PFA_ITYPE3
-00041b 38b0 .dw XT_DUP ; make sure the drop below has always something to do
-00041c 3bca .dw XT_FETCHI
-00041d 0424 .dw XT_LOWEMIT
- PFA_ITYPE3:
-00041e 38d8 .dw XT_DROP
-00041f 381f .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-000420 3800 .dw DO_COLON
- PFA_HIEMIT:
-000421 3af8 .dw XT_BYTESWAP
-000422 0424 .dw XT_LOWEMIT
-000423 381f .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-000424 3800 .dw DO_COLON
- PFA_LOWEMIT:
-000425 383c .dw XT_DOLITERAL
-000426 00ff .dw $00ff
-000427 3a12 .dw XT_AND
-000428 3ef1 .dw XT_EMIT
-000429 381f .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00042a ff06 .dw $ff06
-00042b 6369
-00042c 756f
-00042d 746e .db "icount"
-00042e 03fe .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-00042f 3800 .dw DO_COLON
- PFA_ICOUNT:
-000430 38b0 .dw XT_DUP
-000431 3a2e .dw XT_1PLUS
-000432 38c3 .dw XT_SWAP
-000433 3bca .dw XT_FETCHI
-000434 381f .dw XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-000435 ff04 .dw $ff04
-000436 7974
-000437 6570 .db "type"
-000438 042a .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-000439 3800 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-00043a 3f98 .dw XT_BOUNDS
-00043b 0826 .dw XT_QDOCHECK
-00043c 3835 .dw XT_DOCONDBRANCH
-00043d 0444 DEST(PFA_TYPE2)
-00043e 3a9a .dw XT_DODO
- PFA_TYPE1:
-00043f 3aab .dw XT_I
-000440 3897 .dw XT_CFETCH
-000441 3ef1 .dw XT_EMIT
-000442 3ac8 .dw XT_DOLOOP
-000443 043f DEST(PFA_TYPE1)
- PFA_TYPE2:
-000444 381f .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-000445 ff01 .dw $ff01
-000446 0027 .db "'",0
-000447 0435 .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-000448 3800 .dw DO_COLON
- PFA_TICK:
- .endif
-000449 05bb .dw XT_PARSENAME
-00044a 05fe .dw XT_FORTHRECOGNIZER
-00044b 0609 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-00044c 38b0 .dw XT_DUP
-00044d 0696 .dw XT_DT_NULL
-00044e 3fde .dw XT_EQUAL
-00044f 38c3 .dw XT_SWAP
-000450 3bca .dw XT_FETCHI
-000451 383c .dw XT_DOLITERAL
-000452 01a5 .dw XT_NOOP
-000453 3fde .dw XT_EQUAL
-000454 3a1b .dw XT_OR
-000455 3835 .dw XT_DOCONDBRANCH
-000456 045a DEST(PFA_TICK1)
-000457 383c .dw XT_DOLITERAL
-000458 fff3 .dw -13
-000459 3d85 .dw XT_THROW
- PFA_TICK1:
-00045a 38d8 .dw XT_DROP
-00045b 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-00045c ff05 .dw $ff05
-00045d 7363
-00045e 696b
-00045f 0070 .db "cskip",0
-000460 0445 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-000461 3800 .dw DO_COLON
- PFA_CSKIP:
- .endif
-000462 38fe .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-000463 38b0 .dw XT_DUP ; ( -- addr' n' n' )
-000464 3835 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000465 0470 DEST(PFA_CSKIP2)
-000466 38ce .dw XT_OVER ; ( -- addr' n' addr' )
-000467 3897 .dw XT_CFETCH ; ( -- addr' n' c' )
-000468 3907 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-000469 3fde .dw XT_EQUAL ; ( -- addr' n' f )
-00046a 3835 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00046b 0470 DEST(PFA_CSKIP2)
-00046c 3fe5 .dw XT_ONE
-00046d 05ac .dw XT_SLASHSTRING
-00046e 382e .dw XT_DOBRANCH
-00046f 0463 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-000470 38f5 .dw XT_R_FROM
-000471 38d8 .dw XT_DROP ; ( -- addr2 n2)
-000472 381f .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-000473 ff05 .dw $ff05
-000474 7363
-000475 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-000476 006e .db "cscan"
-000477 045c .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-000478 3800 .dw DO_COLON
- PFA_CSCAN:
- .endif
-000479 38fe .dw XT_TO_R
-00047a 38ce .dw XT_OVER
- PFA_CSCAN1:
-00047b 38b0 .dw XT_DUP
-00047c 3897 .dw XT_CFETCH
-00047d 3907 .dw XT_R_FETCH
-00047e 3fde .dw XT_EQUAL
-00047f 3919 .dw XT_ZEROEQUAL
-000480 3835 .dw XT_DOCONDBRANCH
-000481 048d DEST(PFA_CSCAN2)
-000482 38c3 .dw XT_SWAP
-000483 3a34 .dw XT_1MINUS
-000484 38c3 .dw XT_SWAP
-000485 38ce .dw XT_OVER
-000486 3920 .dw XT_ZEROLESS ; not negative
-000487 3919 .dw XT_ZEROEQUAL
-000488 3835 .dw XT_DOCONDBRANCH
-000489 048d DEST(PFA_CSCAN2)
-00048a 3a2e .dw XT_1PLUS
-00048b 382e .dw XT_DOBRANCH
-00048c 047b DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-00048d 38ef .dw XT_NIP
-00048e 38ce .dw XT_OVER
-00048f 3992 .dw XT_MINUS
-000490 38f5 .dw XT_R_FROM
-000491 38d8 .dw XT_DROP
-000492 381f .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-000493 ff06 .dw $ff06
-000494 6361
-000495 6563
-000496 7470 .db "accept"
-000497 0473 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-000498 3800 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-000499 38ce
-00049a 399c
-00049b 3a34
-00049c 38ce .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-00049d 3f02
-00049e 38b0
-00049f 04d9
-0004a0 3919
-0004a1 3835 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-0004a2 04cb DEST(ACC5)
-0004a3 38b0
-0004a4 383c
-0004a5 0008
-0004a6 3fde
-0004a7 3835 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-0004a8 04bb DEST(ACC3)
-0004a9 38d8
-0004aa 38e0
-0004ab 3ec8
-0004ac 3977
-0004ad 38fe
-0004ae 38e0
-0004af 38e0
-0004b0 38f5
-0004b1 3835 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-0004b2 04b9 DEST(ACC6)
-0004b3 04d1
-0004b4 3a34
-0004b5 38fe
-0004b6 38ce
-0004b7 38f5
-0004b8 015a .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-0004b9 382e ACC6: .DW XT_DOBRANCH
-0004ba 04c9 DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-0004bb 38b0 .dw XT_DUP ; ( -- addr k k )
-0004bc 3f53 .dw XT_BL
-0004bd 396d .dw XT_LESS
-0004be 3835 .dw XT_DOCONDBRANCH
-0004bf 04c2 DEST(PFA_ACCEPT6)
-0004c0 38d8 .dw XT_DROP
-0004c1 3f53 .dw XT_BL
- PFA_ACCEPT6:
-0004c2 38b0
-0004c3 3ef1
-0004c4 38ce
-0004c5 388c
-0004c6 3a2e
-0004c7 38ce
-0004c8 0166 .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-0004c9 382e ACC4: .DW XT_DOBRANCH
-0004ca 049d DEST(ACC1)
-0004cb 38d8
-0004cc 38ef
-0004cd 38c3
-0004ce 3992
-0004cf 3fa0
-0004d0 381f ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-0004d1 3800 .dw DO_COLON
- .endif
-0004d2 383c .dw XT_DOLITERAL
-0004d3 0008 .dw 8
-0004d4 38b0 .dw XT_DUP
-0004d5 3ef1 .dw XT_EMIT
-0004d6 3fad .dw XT_SPACE
-0004d7 3ef1 .dw XT_EMIT
-0004d8 381f .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-0004d9 3800 .dw DO_COLON
- .endif
-0004da 38b0 .dw XT_DUP
-0004db 383c .dw XT_DOLITERAL
-0004dc 000d .dw 13
-0004dd 3fde .dw XT_EQUAL
-0004de 38c3 .dw XT_SWAP
-0004df 383c .dw XT_DOLITERAL
-0004e0 000a .dw 10
-0004e1 3fde .dw XT_EQUAL
-0004e2 3a1b .dw XT_OR
-0004e3 381f .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-0004e4 ff06 .dw $ff06
-0004e5 6572
-0004e6 6966
-0004e7 6c6c .db "refill"
-0004e8 0493 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-0004e9 3dfe .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-0004ea 001a .dw USER_REFILL
-0004eb 3dc7 .dw XT_UDEFERFETCH
-0004ec 3dd3 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-0004ed ff04 .dw $ff04
-0004ee 6863
-0004ef 7261 .db "char"
-0004f0 04e4 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-0004f1 3800 .dw DO_COLON
- PFA_CHAR:
- .endif
-0004f2 05bb .dw XT_PARSENAME
-0004f3 38d8 .dw XT_DROP
-0004f4 3897 .dw XT_CFETCH
-0004f5 381f .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-0004f6 ff06 .dw $ff06
-0004f7 756e
-0004f8 626d
-0004f9 7265 .db "number"
-0004fa 04ed .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-0004fb 3800 .dw DO_COLON
- PFA_NUMBER:
- .endif
-0004fc 3ebc .dw XT_BASE
-0004fd 3878 .dw XT_FETCH
-0004fe 38fe .dw XT_TO_R
-0004ff 053f .dw XT_QSIGN
-000500 38fe .dw XT_TO_R
-000501 0552 .dw XT_SET_BASE
-000502 053f .dw XT_QSIGN
-000503 38f5 .dw XT_R_FROM
-000504 3a1b .dw XT_OR
-000505 38fe .dw XT_TO_R
- ; check whether something is left
-000506 38b0 .dw XT_DUP
-000507 3919 .dw XT_ZEROEQUAL
-000508 3835 .dw XT_DOCONDBRANCH
-000509 0512 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-00050a 3ed1 .dw XT_2DROP
-00050b 38f5 .dw XT_R_FROM
-00050c 38d8 .dw XT_DROP
-00050d 38f5 .dw XT_R_FROM
-00050e 3ebc .dw XT_BASE
-00050f 3880 .dw XT_STORE
-000510 3953 .dw XT_ZERO
-000511 381f .dw XT_EXIT
- PFA_NUMBER0:
-000512 3b1d .dw XT_2TO_R
-000513 3953 .dw XT_ZERO ; starting value
-000514 3953 .dw XT_ZERO
-000515 3b2c .dw XT_2R_FROM
-000516 0570 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-000517 38b8 .dw XT_QDUP
-000518 3835 .dw XT_DOCONDBRANCH
-000519 0534 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00051a 3fe5 .dw XT_ONE
-00051b 3fde .dw XT_EQUAL
-00051c 3835 .dw XT_DOCONDBRANCH
-00051d 052b DEST(PFA_NUMBER2)
- ; excatly one character is left
-00051e 3897 .dw XT_CFETCH
-00051f 383c .dw XT_DOLITERAL
-000520 002e .dw 46 ; .
-000521 3fde .dw XT_EQUAL
-000522 3835 .dw XT_DOCONDBRANCH
-000523 052c DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-000524 38f5 .dw XT_R_FROM
-000525 3835 .dw XT_DOCONDBRANCH
-000526 0528 DEST(PFA_NUMBER3)
-000527 0233 .dw XT_DNEGATE
- PFA_NUMBER3:
-000528 3fea .dw XT_TWO
-000529 382e .dw XT_DOBRANCH
-00052a 053a DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-00052b 38d8 .dw XT_DROP
- PFA_NUMBER6:
-00052c 3ed1 .dw XT_2DROP
-00052d 38f5 .dw XT_R_FROM
-00052e 38d8 .dw XT_DROP
-00052f 38f5 .dw XT_R_FROM
-000530 3ebc .dw XT_BASE
-000531 3880 .dw XT_STORE
-000532 3953 .dw XT_ZERO
-000533 381f .dw XT_EXIT
- PFA_NUMBER1:
-000534 3ed1 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-000535 38f5 .dw XT_R_FROM
-000536 3835 .dw XT_DOCONDBRANCH
-000537 0539 DEST(PFA_NUMBER4)
-000538 3e26 .dw XT_NEGATE
- PFA_NUMBER4:
-000539 3fe5 .dw XT_ONE
- PFA_NUMBER5:
-00053a 38f5 .dw XT_R_FROM
-00053b 3ebc .dw XT_BASE
-00053c 3880 .dw XT_STORE
-00053d 394a .dw XT_TRUE
-00053e 381f .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-00053f 3800 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-000540 38ce .dw XT_OVER ; ( -- addr len addr )
-000541 3897 .dw XT_CFETCH
-000542 383c .dw XT_DOLITERAL
-000543 002d .dw '-'
-000544 3fde .dw XT_EQUAL ; ( -- addr len flag )
-000545 38b0 .dw XT_DUP
-000546 38fe .dw XT_TO_R
-000547 3835 .dw XT_DOCONDBRANCH
-000548 054b DEST(PFA_NUMBERSIGN_DONE)
-000549 3fe5 .dw XT_ONE ; skip sign character
-00054a 05ac .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-00054b 38f5 .dw XT_R_FROM
-00054c 381f .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-00054d 3851 .dw PFA_DOCONSTANT
- .endif
-00054e 000a
-00054f 0010
-000550 0002
-000551 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-000552 3800 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-000553 38ce .dw XT_OVER
-000554 3897 .dw XT_CFETCH
-000555 383c .dw XT_DOLITERAL
-000556 0023 .dw 35
-000557 3992 .dw XT_MINUS
-000558 38b0 .dw XT_DUP
-000559 3953 .dw XT_ZERO
-00055a 383c .dw XT_DOLITERAL
-00055b 0004 .dw 4
-00055c 3e56 .dw XT_WITHIN
-00055d 3835 .dw XT_DOCONDBRANCH
-00055e 0568 DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-00055f 054d .dw XT_BASES
-000560 399c .dw XT_PLUS
-000561 3bca .dw XT_FETCHI
-000562 3ebc .dw XT_BASE
-000563 3880 .dw XT_STORE
-000564 3fe5 .dw XT_ONE
-000565 05ac .dw XT_SLASHSTRING
-000566 382e .dw XT_DOBRANCH
-000567 0569 DEST(SET_BASE2)
- SET_BASE1:
-000568 38d8 .dw XT_DROP
- SET_BASE2:
-000569 381f .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00056a ff07 .dw $ff07
-00056b 6e3e
-00056c 6d75
-00056d 6562
-00056e 0072 .db ">number",0
-00056f 04f6 .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-000570 3800 .dw DO_COLON
-
- .endif
-
-000571 38b0
-000572 3835 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-000573 0588 DEST(TONUM3)
-000574 38ce
-000575 3897
-000576 03b6 .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-000577 3919
-000578 3835 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-000579 057c DEST(TONUM2)
-00057a 38d8
-00057b 381f .DW XT_DROP,XT_EXIT
-00057c 38fe
-00057d 0257
-00057e 3ebc
-00057f 3878
-000580 014b TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000581 38f5
-000582 0143
-000583 0257 .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-000584 3fe5
-000585 05ac
-000586 382e .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-000587 0571 DEST(TONUM1)
-000588 381f TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-000589 ff05 .dw $ff05
-00058a 6170
-00058b 7372
-00058c 0065 .db "parse",0
-00058d 056a .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-00058e 3800 .dw DO_COLON
- PFA_PARSE:
- .endif
-00058f 38fe .dw XT_TO_R ; ( -- )
-000590 05a2 .dw XT_SOURCE ; ( -- addr len)
-000591 3ee1 .dw XT_TO_IN ; ( -- addr len >in)
-000592 3878 .dw XT_FETCH
-000593 05ac .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-000594 38f5 .dw XT_R_FROM ; ( -- addr' len' c)
-000595 0478 .dw XT_CSCAN ; ( -- addr' len'')
-000596 38b0 .dw XT_DUP ; ( -- addr' len'' len'')
-000597 3a2e .dw XT_1PLUS
-000598 3ee1 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-000599 3a64 .dw XT_PLUSSTORE ; ( -- addr' len')
-00059a 3fe5 .dw XT_ONE
-00059b 05ac .dw XT_SLASHSTRING
-00059c 381f .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-00059d ff06 .dw $FF06
-00059e 6f73
-00059f 7275
-0005a0 6563 .db "source"
-0005a1 0589 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-0005a2 3dfe .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-0005a3 0016 .dw USER_SOURCE
-0005a4 3dc7 .dw XT_UDEFERFETCH
-0005a5 3dd3 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-0005a6 ff07 .dw $ff07
-0005a7 732f
-0005a8 7274
-0005a9 6e69
-0005aa 0067 .db "/string",0
-0005ab 059d .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-0005ac 3800 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-0005ad 38e0 .dw XT_ROT
-0005ae 38ce .dw XT_OVER
-0005af 399c .dw XT_PLUS
-0005b0 38e0 .dw XT_ROT
-0005b1 38e0 .dw XT_ROT
-0005b2 3992 .dw XT_MINUS
-0005b3 381f .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-0005b4 ff0a .dw $FF0A
-0005b5 6170
-0005b6 7372
-0005b7 2d65
-0005b8 616e
-0005b9 656d .db "parse-name"
-0005ba 05a6 .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-0005bb 3800 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-0005bc 3f53 .dw XT_BL
-0005bd 05bf .dw XT_SKIPSCANCHAR
-0005be 381f .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-0005bf 3800 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-0005c0 38fe .dw XT_TO_R
-0005c1 05a2 .dw XT_SOURCE
-0005c2 3ee1 .dw XT_TO_IN
-0005c3 3878 .dw XT_FETCH
-0005c4 05ac .dw XT_SLASHSTRING
-
-0005c5 3907 .dw XT_R_FETCH
-0005c6 0461 .dw XT_CSKIP
-0005c7 38f5 .dw XT_R_FROM
-0005c8 0478 .dw XT_CSCAN
-
- ; adjust >IN
-0005c9 3ec8 .dw XT_2DUP
-0005ca 399c .dw XT_PLUS
-0005cb 05a2 .dw XT_SOURCE
-0005cc 38d8 .dw XT_DROP
-0005cd 3992 .dw XT_MINUS
-0005ce 3ee1 .dw XT_TO_IN
-0005cf 3880 .dw XT_STORE
-0005d0 381f .dw XT_EXIT
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-0005d1 ff03 .dw $ff03
-0005d2 7073
-0005d3 0030 .db "sp0",0
-0005d4 05b4 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-0005d5 386e .dw PFA_DOVALUE1
- PFA_SP0:
-0005d6 0006 .dw USER_SP0
-0005d7 3dc7 .dw XT_UDEFERFETCH
-0005d8 3dd3 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-0005d9 ff02 .dw $ff02
-0005da 7073 .db "sp"
-0005db 05d1 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-0005dc 3857 .dw PFA_DOUSER
- PFA_SP:
-0005dd 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-0005de ff03 .dw $ff03
-0005df 7072
-0005e0 0030 .db "rp0",0
-0005e1 05d9 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-0005e2 3800 .dw DO_COLON
- PFA_RP0:
-0005e3 05e6 .dw XT_DORP0
-0005e4 3878 .dw XT_FETCH
-0005e5 381f .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-0005e6 3857 .dw PFA_DOUSER
- PFA_DORP0:
-0005e7 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-0005e8 ff05 .dw $ff05
-0005e9 6564
-0005ea 7470
-0005eb 0068 .db "depth",0
-0005ec 05de .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-0005ed 3800 .dw DO_COLON
- PFA_DEPTH:
- .endif
-0005ee 05d5 .dw XT_SP0
-0005ef 3a8c .dw XT_SP_FETCH
-0005f0 3992 .dw XT_MINUS
-0005f1 3a03 .dw XT_2SLASH
-0005f2 3a34 .dw XT_1MINUS
-0005f3 381f .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-0005f4 ff10 .dw $ff10
-0005f5 6f66
-0005f6 7472
-0005f7 2d68
-0005f8 6572
-0005f9 6f63
-0005fa 6e67
-0005fb 7a69
-0005fc 7265 .db "forth-recognizer"
-0005fd 05e8 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-0005fe 386e .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-0005ff 003e .dw CFG_FORTHRECOGNIZER
-000600 3d9f .dw XT_EDEFERFETCH
-000601 3da9 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-000602 ff09 .dw $ff09
-000603 6572
-000604 6f63
-000605 6e67
-000606 7a69
-000607 0065 .db "recognize",0
-000608 05f4 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-000609 3800 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-00060a 383c .dw XT_DOLITERAL
-00060b 0614 .dw XT_RECOGNIZE_A
-00060c 38c3 .dw XT_SWAP
-00060d 09a7 .dw XT_MAPSTACK
-00060e 3919 .dw XT_ZEROEQUAL
-00060f 3835 .dw XT_DOCONDBRANCH
-000610 0613 DEST(PFA_RECOGNIZE1)
-000611 3ed1 .dw XT_2DROP
-000612 0696 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-000613 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-000614 3800 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-000615 38e0 .dw XT_ROT ; -- len xt addr
-000616 38e0 .dw XT_ROT ; -- xt addr len
-000617 3ec8 .dw XT_2DUP
-000618 3b1d .dw XT_2TO_R
-000619 38e0 .dw XT_ROT ; -- addr len xt
-00061a 3829 .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-00061b 3b2c .dw XT_2R_FROM
-00061c 38e0 .dw XT_ROT
-00061d 38b0 .dw XT_DUP
-00061e 0696 .dw XT_DT_NULL
-00061f 3fde .dw XT_EQUAL
-000620 3835 .dw XT_DOCONDBRANCH
-000621 0625 DEST(PFA_RECOGNIZE_A1)
-000622 38d8 .dw XT_DROP
-000623 3953 .dw XT_ZERO
-000624 381f .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-000625 38ef .dw XT_NIP
-000626 38ef .dw XT_NIP
-000627 394a .dw XT_TRUE
-000628 381f .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-000629 ff09 .dw $ff09
-00062a 6e69
-00062b 6574
-00062c 7072
-00062d 6572
-00062e 0074 .db "interpret",0
-00062f 0602 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-000630 3800 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-000631 05bb .dw XT_PARSENAME ; ( -- addr len )
-000632 38b0 .dw XT_DUP ; ( -- addr len flag)
-000633 3835 .dw XT_DOCONDBRANCH
-000634 0641 DEST(PFA_INTERPRET2)
-000635 05fe .dw XT_FORTHRECOGNIZER
-000636 0609 .dw XT_RECOGNIZE
-000637 3eb6 .dw XT_STATE
-000638 3878 .dw XT_FETCH
-000639 3835 .dw XT_DOCONDBRANCH
-00063a 063c DEST(PFA_INTERPRET1)
-00063b 01d1 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-00063c 3bca .dw XT_FETCHI
-00063d 3829 .dw XT_EXECUTE
-00063e 3f8a .dw XT_QSTACK
-00063f 382e .dw XT_DOBRANCH
-000640 0631 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000641 3ed1 .dw XT_2DROP
-000642 381f .dw XT_EXIT
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-000643 ff06 .dw $ff06
-000644 7464
-000645 6e3a
-000646 6d75 .db "dt:num"
-000647 0629 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-000648 3851 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-000649 01a5 .dw XT_NOOP ; interpret
-00064a 077d .dw XT_LITERAL ; compile
-00064b 077d .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-00064c ff07 .dw $ff07
-00064d 7464
-00064e 643a
-00064f 756e
-000650 006d .db "dt:dnum",0
-000651 0643 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000652 3851 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-000653 01a5 .dw XT_NOOP ; interpret
-000654 3fd6 .dw XT_2LITERAL ; compile
-000655 3fd6 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-000656 ff07 .dw $ff07
-000657 6572
-000658 3a63
-000659 756e
-00065a 006d .db "rec:num",0
-00065b 064c .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-00065c 3800 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-00065d 04fb .dw XT_NUMBER
-00065e 3835 .dw XT_DOCONDBRANCH
-00065f 0668 DEST(PFA_REC_NONUMBER)
-000660 3fe5 .dw XT_ONE
-000661 3fde .dw XT_EQUAL
-000662 3835 .dw XT_DOCONDBRANCH
-000663 0666 DEST(PFA_REC_INTNUM2)
-000664 0648 .dw XT_DT_NUM
-000665 381f .dw XT_EXIT
- PFA_REC_INTNUM2:
-000666 0652 .dw XT_DT_DNUM
-000667 381f .dw XT_EXIT
- PFA_REC_NONUMBER:
-000668 0696 .dw XT_DT_NULL
-000669 381f .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00066a ff08 .dw $ff08
-00066b 6572
-00066c 3a63
-00066d 6966
-00066e 646e .db "rec:find"
-00066f 0656 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000670 3800 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000671 070b .DW XT_FINDXT
-000672 38b0 .dw XT_DUP
-000673 3919 .dw XT_ZEROEQUAL
-000674 3835 .dw XT_DOCONDBRANCH
-000675 0679 DEST(PFA_REC_WORD_FOUND)
-000676 38d8 .dw XT_DROP
-000677 0696 .dw XT_DT_NULL
-000678 381f .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-000679 0680 .dw XT_DT_XT
-
-00067a 381f .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-00067b ff05 .dw $ff05
-00067c 7464
-00067d 783a
-00067e 0074 .db "dt:xt",0
-00067f 066a .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000680 3851 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000681 0684 .dw XT_R_WORD_INTERPRET
-000682 0688 .dw XT_R_WORD_COMPILE
-000683 3fd6 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-000684 3800 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-000685 38d8 .dw XT_DROP ; the flags are in the way
-000686 3829 .dw XT_EXECUTE
-000687 381f .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-000688 3800 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-000689 3920 .dw XT_ZEROLESS
-00068a 3835 .dw XT_DOCONDBRANCH
-00068b 068e DEST(PFA_R_WORD_COMPILE1)
-00068c 0767 .dw XT_COMMA
-00068d 381f .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-00068e 3829 .dw XT_EXECUTE
-00068f 381f .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000690 ff07 .dw $ff07
-000691 7464
-000692 6e3a
-000693 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-000694 006c .db "dt:null"
-000695 067b .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-000696 3851 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-000697 069a .dw XT_FAIL ; interpret
-000698 069a .dw XT_FAIL ; compile
-000699 069a .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00069a 3800 .dw DO_COLON
- PFA_FAIL:
- .endif
-00069b 383c .dw XT_DOLITERAL
-00069c fff3 .dw -13
-00069d 3d85 .dw XT_THROW
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-00069e ff0f .dw $ff0f
-00069f 6573
-0006a0 7261
-0006a1 6863
-0006a2 772d
-0006a3 726f
-0006a4 6c64
-0006a5 7369
-0006a6 0074 .db "search-wordlist",0
-0006a7 0690 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-0006a8 3800 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-0006a9 38fe .dw XT_TO_R
-0006aa 3953 .dw XT_ZERO
-0006ab 383c .dw XT_DOLITERAL
-0006ac 06bd .dw XT_ISWORD
-0006ad 38f5 .dw XT_R_FROM
-0006ae 06da .dw XT_TRAVERSEWORDLIST
-0006af 38b0 .dw XT_DUP
-0006b0 3919 .dw XT_ZEROEQUAL
-0006b1 3835 .dw XT_DOCONDBRANCH
-0006b2 06b7 DEST(PFA_SEARCH_WORDLIST1)
-0006b3 3ed1 .dw XT_2DROP
-0006b4 38d8 .dw XT_DROP
-0006b5 3953 .dw XT_ZERO
-0006b6 381f .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-0006b7 38b0 .dw XT_DUP
-0006b8 0701 .dw XT_NFA2CFA
- ; .. and get the header flag
-0006b9 38c3 .dw XT_SWAP
-0006ba 0180 .dw XT_NAME2FLAGS
-0006bb 016e .dw XT_IMMEDIATEQ
-0006bc 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-0006bd 3800 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-0006be 38fe .dw XT_TO_R
-0006bf 38d8 .dw XT_DROP
-0006c0 3ec8 .dw XT_2DUP
-0006c1 3907 .dw XT_R_FETCH ; -- addr len addr len nt
-0006c2 06f5 .dw XT_NAME2STRING
-0006c3 01da .dw XT_ICOMPARE ; (-- addr len f )
-0006c4 3835 .dw XT_DOCONDBRANCH
-0006c5 06cb DEST(PFA_ISWORD3)
- ; not now
-0006c6 38f5 .dw XT_R_FROM
-0006c7 38d8 .dw XT_DROP
-0006c8 3953 .dw XT_ZERO
-0006c9 394a .dw XT_TRUE ; maybe next word
-0006ca 381f .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-0006cb 3ed1 .dw XT_2DROP
-0006cc 38f5 .dw XT_R_FROM
-0006cd 3953 .dw XT_ZERO ; finish traverse-wordlist
-0006ce 381f .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-0006cf ff11 .dw $ff11
-0006d0 7274
-0006d1 7661
-0006d2 7265
-0006d3 6573
-0006d4 772d
-0006d5 726f
-0006d6 6c64
-0006d7 7369
-0006d8 0074 .db "traverse-wordlist",0
-0006d9 069e .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-0006da 3800 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-0006db 3b5e .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-0006dc 38b0 .dw XT_DUP ; ( -- xt nt nt )
-0006dd 3835 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-0006de 06eb DEST(PFA_TRAVERSEWORDLIST2)
-0006df 3ec8 .dw XT_2DUP
-0006e0 3b1d .dw XT_2TO_R
-0006e1 38c3 .dw XT_SWAP
-0006e2 3829 .dw XT_EXECUTE
-0006e3 3b2c .dw XT_2R_FROM
-0006e4 38e0 .dw XT_ROT
-0006e5 3835 .dw XT_DOCONDBRANCH
-0006e6 06eb DEST(PFA_TRAVERSEWORDLIST2)
-0006e7 0a16 .dw XT_NFA2LFA
-0006e8 3bca .dw XT_FETCHI
-0006e9 382e .dw XT_DOBRANCH ; ( -- addr )
-0006ea 06dc DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-0006eb 3ed1 .dw XT_2DROP
-0006ec 381f .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-0006ed ff0b .dw $ff0b
-0006ee 616e
-0006ef 656d
-0006f0 733e
-0006f1 7274
-0006f2 6e69
-0006f3 0067 .db "name>string",0
-0006f4 06cf .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-0006f5 3800 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-0006f6 042f .dw XT_ICOUNT ; ( -- addr n )
-0006f7 383c .dw XT_DOLITERAL
-0006f8 00ff .dw 255
-0006f9 3a12 .dw XT_AND ; mask immediate bit
-0006fa 381f .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-0006fb ff07 .dw $ff07
-0006fc 666e
-0006fd 3e61
-0006fe 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-0006ff 0061 .db "nfa>cfa"
-000700 06ed .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-000701 3800 .dw DO_COLON
- PFA_NFA2CFA:
-000702 0a16 .dw XT_NFA2LFA ; skip to link field
-000703 3a2e .dw XT_1PLUS ; next is the execution token
-000704 381f .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-000705 ff07 .dw $ff07
-000706 6966
-000707 646e
-000708 782d
-000709 0074 .db "find-xt",0
-00070a 06fb .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-00070b 3800 .dw DO_COLON
- PFA_FINDXT:
- .endif
-00070c 383c .dw XT_DOLITERAL
-00070d 0717 .dw XT_FINDXTA
-00070e 383c .dw XT_DOLITERAL
-00070f 004a .dw CFG_ORDERLISTLEN
-000710 09a7 .dw XT_MAPSTACK
-000711 3919 .dw XT_ZEROEQUAL
-000712 3835 .dw XT_DOCONDBRANCH
-000713 0716 DEST(PFA_FINDXT1)
-000714 3ed1 .dw XT_2DROP
-000715 3953 .dw XT_ZERO
- PFA_FINDXT1:
-000716 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-000717 3800 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-000718 38fe .dw XT_TO_R
-000719 3ec8 .dw XT_2DUP
-00071a 38f5 .dw XT_R_FROM
-00071b 06a8 .dw XT_SEARCH_WORDLIST
-00071c 38b0 .dw XT_DUP
-00071d 3835 .dw XT_DOCONDBRANCH
-00071e 0724 DEST(PFA_FINDXTA1)
-00071f 38fe .dw XT_TO_R
-000720 38ef .dw XT_NIP
-000721 38ef .dw XT_NIP
-000722 38f5 .dw XT_R_FROM
-000723 394a .dw XT_TRUE
- PFA_FINDXTA1:
-000724 381f .dw XT_EXIT
-
- .include "dict/compiler1.inc"
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-000725 ff06 .dw $ff06
-000726 656e
-000727 6577
-000728 7473 .db "newest"
-000729 0705 .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-00072a 3847 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-00072b 018a .dw ram_newest
-
- .dseg
-00018a ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-00072c ff06 .dw $ff06
-00072d 616c
-00072e 6574
-00072f 7473 .db "latest"
-000730 0725 .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000731 3847 .dw PFA_DOVARIABLE
- PFA_LATEST:
-000732 018e .dw ram_latest
-
- .dseg
-00018e ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-000733 ff08 .dw $ff08
-000734 6328
-000735 6572
-000736 7461
-000737 2965 .db "(create)"
-000738 072c .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-000739 3800 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-00073a 05bb
-00073b 0890 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-00073c 38b0
-00073d 072a
-00073e 3c8f
-00073f 3880 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000740 0875
-000741 072a
-000742 3880 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-000743 381f .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-000744 0001 .dw $0001
-000745 005c .db $5c,0
-000746 0733 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-000747 3800 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-000748 05a2 .dw XT_SOURCE
-000749 38ef .dw XT_NIP
-00074a 3ee1 .dw XT_TO_IN
-00074b 3880 .dw XT_STORE
-00074c 381f .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-00074d 0001 .dw $0001
-00074e 0028 .db "(" ,0
-00074f 0744 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000750 3800 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000751 383c .dw XT_DOLITERAL
-000752 0029 .dw ')'
-000753 058e .dw XT_PARSE
-000754 3ed1 .dw XT_2DROP
-000755 381f .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-000756 ff07 .dw $ff07
-000757 6f63
-000758 706d
-000759 6c69
-00075a 0065 .db "compile",0
-00075b 074d .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-00075c 3800 .dw DO_COLON
- PFA_COMPILE:
- .endif
-00075d 38f5 .dw XT_R_FROM
-00075e 38b0 .dw XT_DUP
-00075f 01d1 .dw XT_ICELLPLUS
-000760 38fe .dw XT_TO_R
-000761 3bca .dw XT_FETCHI
-000762 0767 .dw XT_COMMA
-000763 381f .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-000764 ff01 .dw $ff01
-000765 002c .db ',',0 ; ,
-000766 0756 .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-000767 3800 .dw DO_COLON
- PFA_COMMA:
-000768 3f11 .dw XT_DP
-000769 3b72 .dw XT_STOREI
-00076a 3f11 .dw XT_DP
-00076b 3a2e .dw XT_1PLUS
-00076c 01bf .dw XT_DOTO
-00076d 3f12 .dw PFA_DP
-00076e 381f .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-00076f 0003 .dw $0003
-000770 275b
-000771 005d .db "[']",0
-000772 0764 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-000773 3800 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-000774 0448 .dw XT_TICK
-000775 077d .dw XT_LITERAL
-000776 381f .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-000777 0007 .dw $0007
-000778 696c
-000779 6574
-00077a 6172
-00077b 006c .db "literal",0
-00077c 076f .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-00077d 3800 .dw DO_COLON
- PFA_LITERAL:
- .endif
-00077e 075c .DW XT_COMPILE
-00077f 383c .DW XT_DOLITERAL
-000780 0767 .DW XT_COMMA
-000781 381f .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-000782 0008 .dw $0008
-000783 6c73
-000784 7469
-000785 7265
-000786 6c61 .db "sliteral"
-000787 0777 .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-000788 3800 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-000789 075c .dw XT_COMPILE
-00078a 03d0 .dw XT_DOSLITERAL ; ( -- addr n)
-00078b 03de .dw XT_SCOMMA
-00078c 381f .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-00078d 3800 .dw DO_COLON
- PFA_GMARK:
-00078e 3f11 .dw XT_DP
-00078f 075c .dw XT_COMPILE
-000790 ffff .dw -1 ; ffff does not erase flash
-000791 381f .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000792 3800 .dw DO_COLON
- PFA_GRESOLVE:
-000793 3f8a .dw XT_QSTACK
-000794 3f11 .dw XT_DP
-000795 38c3 .dw XT_SWAP
-000796 3b72 .dw XT_STOREI
-000797 381f .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-000798 3800 .dw DO_COLON
- PFA_LMARK:
-000799 3f11 .dw XT_DP
-00079a 381f .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-00079b 3800 .dw DO_COLON
- PFA_LRESOLVE:
-00079c 3f8a .dw XT_QSTACK
-00079d 0767 .dw XT_COMMA
-00079e 381f .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-00079f 0005 .dw $0005
-0007a0 6861
-0007a1 6165
-0007a2 0064 .db "ahead",0
-0007a3 0782 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-0007a4 3800 .dw DO_COLON
- PFA_AHEAD:
- .endif
-0007a5 075c .dw XT_COMPILE
-0007a6 382e .dw XT_DOBRANCH
-0007a7 078d .dw XT_GMARK
-0007a8 381f .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-0007a9 0002 .dw $0002
-0007aa 6669 .db "if"
-0007ab 079f .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-0007ac 3800 .dw DO_COLON
- PFA_IF:
- .endif
-0007ad 075c .dw XT_COMPILE
-0007ae 3835 .dw XT_DOCONDBRANCH
-0007af 078d .dw XT_GMARK
-0007b0 381f .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-0007b1 0004 .dw $0004
-0007b2 6c65
-0007b3 6573 .db "else"
-0007b4 07a9 .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-0007b5 3800 .dw DO_COLON
- PFA_ELSE:
- .endif
-0007b6 075c .dw XT_COMPILE
-0007b7 382e .dw XT_DOBRANCH
-0007b8 078d .dw XT_GMARK
-0007b9 38c3 .dw XT_SWAP
-0007ba 0792 .dw XT_GRESOLVE
-0007bb 381f .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-0007bc 0004 .dw $0004
-0007bd 6874
-0007be 6e65 .db "then"
-0007bf 07b1 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-0007c0 3800 .dw DO_COLON
- PFA_THEN:
- .endif
-0007c1 0792 .dw XT_GRESOLVE
-0007c2 381f .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-0007c3 0005 .dw $0005
-0007c4 6562
-0007c5 6967
-0007c6 006e .db "begin",0
-0007c7 07bc .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-0007c8 3800 .dw DO_COLON
- PFA_BEGIN:
- .endif
-0007c9 0798 .dw XT_LMARK
-0007ca 381f .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-0007cb 0005 .dw $0005
-0007cc 6877
-0007cd 6c69
-0007ce 0065 .db "while",0
-0007cf 07c3 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-0007d0 3800 .dw DO_COLON
- PFA_WHILE:
- .endif
-0007d1 07ac .dw XT_IF
-0007d2 38c3 .dw XT_SWAP
-0007d3 381f .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-0007d4 0006 .dw $0006
-0007d5 6572
-0007d6 6570
-0007d7 7461 .db "repeat"
-0007d8 07cb .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-0007d9 3800 .dw DO_COLON
- PFA_REPEAT:
- .endif
-0007da 07ed .dw XT_AGAIN
-0007db 07c0 .dw XT_THEN
-0007dc 381f .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-0007dd 0005 .dw $0005
-0007de 6e75
-0007df 6974
-0007e0 006c .db "until",0
-0007e1 07d4 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-0007e2 3800 .dw DO_COLON
- PFA_UNTIL:
- .endif
-0007e3 383c .dw XT_DOLITERAL
-0007e4 3835 .dw XT_DOCONDBRANCH
-0007e5 0767 .dw XT_COMMA
-
-0007e6 079b .dw XT_LRESOLVE
-0007e7 381f .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-0007e8 0005 .dw $0005
-0007e9 6761
-0007ea 6961
-0007eb 006e .db "again",0
-0007ec 07dd .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-0007ed 3800 .dw DO_COLON
- PFA_AGAIN:
- .endif
-0007ee 075c .dw XT_COMPILE
-0007ef 382e .dw XT_DOBRANCH
-0007f0 079b .dw XT_LRESOLVE
-0007f1 381f .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-0007f2 0002 .dw $0002
-0007f3 6f64 .db "do"
-0007f4 07e8 .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-0007f5 3800 .dw DO_COLON
- PFA_DO:
-
- .endif
-0007f6 075c .dw XT_COMPILE
-0007f7 3a9a .dw XT_DODO
-0007f8 0798 .dw XT_LMARK
-0007f9 3953 .dw XT_ZERO
-0007fa 0850 .dw XT_TO_L
-0007fb 381f .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-0007fc 0004 .dw $0004
-0007fd 6f6c
-0007fe 706f .db "loop"
-0007ff 07f2 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000800 3800 .dw DO_COLON
- PFA_LOOP:
- .endif
-000801 075c .dw XT_COMPILE
-000802 3ac8 .dw XT_DOLOOP
-000803 0837 .dw XT_ENDLOOP
-000804 381f .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-000805 0005 .dw $0005
-000806 6c2b
-000807 6f6f
-000808 0070 .db "+loop",0
-000809 07fc .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-00080a 3800 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-00080b 075c .dw XT_COMPILE
-00080c 3ab9 .dw XT_DOPLUSLOOP
-00080d 0837 .dw XT_ENDLOOP
-00080e 381f .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-00080f 0005 .dw $0005
-000810 656c
-000811 7661
-000812 0065 .db "leave",0
-000813 0805 .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-000814 3800 .dw DO_COLON
- PFA_LEAVE:
- .endif
-000815 075c
-000816 3ad3 .DW XT_COMPILE,XT_UNLOOP
-000817 07a4
-000818 0850
-000819 381f .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-00081a 0003 .dw $0003
-00081b 643f
-00081c 006f .db "?do",0
-00081d 080f .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-00081e 3800 .dw DO_COLON
- PFA_QDO:
- .endif
-00081f 075c .dw XT_COMPILE
-000820 0826 .dw XT_QDOCHECK
-000821 07ac .dw XT_IF
-000822 07f5 .dw XT_DO
-000823 38c3 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-000824 0850 .dw XT_TO_L ; then follows at the end.
-000825 381f .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-000826 3800 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-000827 3ec8 .dw XT_2DUP
-000828 3fde .dw XT_EQUAL
-000829 38b0 .dw XT_DUP
-00082a 38fe .dw XT_TO_R
-00082b 3835 .dw XT_DOCONDBRANCH
-00082c 082e DEST(PFA_QDOCHECK1)
-00082d 3ed1 .dw XT_2DROP
- PFA_QDOCHECK1:
-00082e 38f5 .dw XT_R_FROM
-00082f 39fc .dw XT_INVERT
-000830 381f .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000831 ff07 .dw $ff07
-000832 6e65
-000833 6c64
-000834 6f6f
-000835 0070 .db "endloop",0
-000836 081a .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-000837 3800 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-000838 079b .DW XT_LRESOLVE
-000839 0844
-00083a 38b8
-00083b 3835 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-00083c 0840 DEST(LOOP2)
-00083d 07c0 .DW XT_THEN
-00083e 382e .dw XT_DOBRANCH
-00083f 0839 DEST(LOOP1)
-000840 381f LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000841 ff02 .dw $ff02
-000842 3e6c .db "l>"
-000843 0831 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-000844 3800 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-000845 0863 .dw XT_LP
-000846 3878 .dw XT_FETCH
-000847 3878 .dw XT_FETCH
-000848 383c .dw XT_DOLITERAL
-000849 fffe .dw -2
-00084a 0863 .dw XT_LP
-00084b 3a64 .dw XT_PLUSSTORE
-00084c 381f .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-00084d ff02 .dw $ff02
-00084e 6c3e .db ">l"
-00084f 0841 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000850 3800 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000851 3fea .dw XT_TWO
-000852 0863 .dw XT_LP
-000853 3a64 .dw XT_PLUSSTORE
-000854 0863 .dw XT_LP
-000855 3878 .dw XT_FETCH
-000856 3880 .dw XT_STORE
-000857 381f .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-000858 ff03 .dw $ff03
-000859 706c
-00085a 0030 .db "lp0",0
-00085b 084d .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-00085c 386e .dw PFA_DOVALUE1
- PFA_LP0:
-00085d 0040 .dw CFG_LP0
-00085e 3d9f .dw XT_EDEFERFETCH
-00085f 3da9 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-000860 ff02 .dw $ff02
-000861 706c .db "lp"
-000862 0858 .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-000863 3847 .dw PFA_DOVARIABLE
- PFA_LP:
-000864 0190 .dw ram_lp
-
- .dseg
-000190 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-000865 ff06 .dw $ff06
-000866 7263
-000867 6165
-000868 6574 .db "create"
-000869 0860 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-00086a 3800 .dw DO_COLON
- PFA_CREATE:
- .endif
-00086b 0739 .dw XT_DOCREATE
-00086c 0899 .dw XT_REVEAL
-00086d 075c .dw XT_COMPILE
-00086e 3851 .dw PFA_DOCONSTANT
-00086f 381f .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-000870 ff06 .dw $ff06
-000871 6568
-000872 6461
-000873 7265 .db "header"
-000874 0865 .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-000875 3800 .dw DO_COLON
- PFA_HEADER:
-000876 3f11 .dw XT_DP ; the new Name Field
-000877 38fe .dw XT_TO_R
-000878 38fe .dw XT_TO_R ; ( R: NFA WID )
-000879 38b0 .dw XT_DUP
-00087a 3927 .dw XT_GREATERZERO
-00087b 3835 .dw XT_DOCONDBRANCH
-00087c 0887 .dw PFA_HEADER1
-00087d 38b0 .dw XT_DUP
-00087e 383c .dw XT_DOLITERAL
-00087f ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-000880 3a1b .dw XT_OR
-000881 03e2 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-000882 38f5 .dw XT_R_FROM
-000883 3b5e .dw XT_FETCHE
-000884 0767 .dw XT_COMMA
-000885 38f5 .dw XT_R_FROM
-000886 381f .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-000887 383c .dw XT_DOLITERAL
-000888 fff0 .dw -16
-000889 3d85 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-00088a ff07 .dw $ff07
-00088b 6c77
-00088c 6373
-00088d 706f
-00088e 0065 .db "wlscope",0
-00088f 0870 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000890 3dfe .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000891 003c .dw CFG_WLSCOPE
-000892 3d9f .dw XT_EDEFERFETCH
-000893 3da9 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000894 ff06 .dw $ff06
-000895 6572
-000896 6576
-000897 6c61 .db "reveal"
-000898 088a .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-000899 3800 .dw DO_COLON
- PFA_REVEAL:
- .endif
-00089a 072a
-00089b 3c8f
-00089c 3878 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-00089d 38b8
-00089e 3835 .DW XT_QDUP,XT_DOCONDBRANCH
-00089f 08a4 DEST(REVEAL1)
-0008a0 072a
-0008a1 3878
-0008a2 38c3
-0008a3 3b3a .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-0008a4 381f .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-0008a5 0005 .dw $0005
-0008a6 6f64
-0008a7 7365
-0008a8 003e .db "does>",0
-0008a9 0894 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-0008aa 3800 .dw DO_COLON
- PFA_DOES:
-0008ab 075c .dw XT_COMPILE
-0008ac 08bd .dw XT_DODOES
-0008ad 075c .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-0008ae 940e .dw $940e ; the address of this compiled
-0008af 075c .dw XT_COMPILE ; code will replace the XT of the
-0008b0 08b2 .dw DO_DODOES ; word that CREATE created
-0008b1 381f .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-0008b2 939a
-0008b3 938a savetos
-0008b4 01cb movw tosl, wl
-0008b5 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-0008b6 917f pop wh
-0008b7 916f pop wl
-
-0008b8 93bf push XH
-0008b9 93af push XL
-0008ba 01db movw XL, wl
-0008bb 940c 3804 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-0008bd 3800 .dw DO_COLON
- PFA_DODOES:
-0008be 38f5 .dw XT_R_FROM
-0008bf 072a .dw XT_NEWEST
-0008c0 3c8f .dw XT_CELLPLUS
-0008c1 3878 .dw XT_FETCH
-0008c2 3b5e .dw XT_FETCHE
-0008c3 0701 .dw XT_NFA2CFA
-0008c4 3b72 .dw XT_STOREI
-0008c5 381f .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-0008c6 ff01 .dw $ff01
-0008c7 003a .db ":",0
-0008c8 08a5 .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-0008c9 3800 .dw DO_COLON
- PFA_COLON:
- .endif
-0008ca 0739 .dw XT_DOCREATE
-0008cb 08d4 .dw XT_COLONNONAME
-0008cc 38d8 .dw XT_DROP
-0008cd 381f .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-0008ce ff07 .dw $ff07
-0008cf 6e3a
-0008d0 6e6f
-0008d1 6d61
-0008d2 0065 .db ":noname",0
-0008d3 08c6 .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-0008d4 3800 .dw DO_COLON
- PFA_COLONNONAME:
-0008d5 3f11 .dw XT_DP
-0008d6 38b0 .dw XT_DUP
-0008d7 0731 .dw XT_LATEST
-0008d8 3880 .dw XT_STORE
-
-0008d9 075c .dw XT_COMPILE
-0008da 3800 .dw DO_COLON
-
-0008db 08e9 .dw XT_RBRACKET
-0008dc 381f .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-0008dd 0001 .dw $0001
-0008de 003b .db $3b,0
-0008df 08ce .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-0008e0 3800 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-0008e1 075c .dw XT_COMPILE
-0008e2 381f .dw XT_EXIT
-0008e3 08f1 .dw XT_LBRACKET
-0008e4 0899 .dw XT_REVEAL
-0008e5 381f .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-0008e6 ff01 .dw $ff01
-0008e7 005d .db "]",0
-0008e8 08dd .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-0008e9 3800 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-0008ea 3fe5 .dw XT_ONE
-0008eb 3eb6 .dw XT_STATE
-0008ec 3880 .dw XT_STORE
-0008ed 381f .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-0008ee 0001 .dw $0001
-0008ef 005b .db "[",0
-0008f0 08e6 .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-0008f1 3800 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-0008f2 3953 .dw XT_ZERO
-0008f3 3eb6 .dw XT_STATE
-0008f4 3880 .dw XT_STORE
-0008f5 381f .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-0008f6 ff08 .dw $ff08
-0008f7 6176
-0008f8 6972
-0008f9 6261
-0008fa 656c .db "variable"
-0008fb 08ee .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-0008fc 3800 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-0008fd 3f22 .dw XT_HERE
-0008fe 0908 .dw XT_CONSTANT
-0008ff 3fea .dw XT_TWO
-000900 3f2b .dw XT_ALLOT
-000901 381f .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-000902 ff08 .dw $ff08
-000903 6f63
-000904 736e
-000905 6174
-000906 746e .db "constant"
-000907 08f6 .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-000908 3800 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-000909 0739 .dw XT_DOCREATE
-00090a 0899 .dw XT_REVEAL
-00090b 075c .dw XT_COMPILE
-00090c 3847 .dw PFA_DOVARIABLE
-00090d 0767 .dw XT_COMMA
-00090e 381f .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-00090f ff04 .dw $ff04
-000910 7375
-000911 7265 .db "user"
-000912 0902 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-000913 3800 .dw DO_COLON
- PFA_USER:
-000914 0739 .dw XT_DOCREATE
-000915 0899 .dw XT_REVEAL
-
-000916 075c .dw XT_COMPILE
-000917 3857 .dw PFA_DOUSER
-000918 0767 .dw XT_COMMA
-000919 381f .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-00091a 0007 .dw $0007
-00091b 6572
-00091c 7563
-00091d 7372
-00091e 0065 .db "recurse",0
-00091f 090f .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000920 3800 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000921 0731 .dw XT_LATEST
-000922 3878 .dw XT_FETCH
-000923 0767 .dw XT_COMMA
-000924 381f .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-000925 ff09 .dw $ff09
-000926 6d69
-000927 656d
-000928 6964
-000929 7461
-00092a 0065 .db "immediate",0
-00092b 091a .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-00092c 3800 .dw DO_COLON
- PFA_IMMEDIATE:
-00092d 09ce .dw XT_GET_CURRENT
-00092e 3b5e .dw XT_FETCHE
-00092f 38b0 .dw XT_DUP
-000930 3bca .dw XT_FETCHI
-000931 383c .dw XT_DOLITERAL
-000932 7fff .dw $7fff
-000933 3a12 .dw XT_AND
-000934 38c3 .dw XT_SWAP
-000935 3b72 .dw XT_STOREI
-000936 381f .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-000937 0006 .dw $0006
-000938 635b
-000939 6168
-00093a 5d72 .db "[char]"
-00093b 0925 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-00093c 3800 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-00093d 075c .dw XT_COMPILE
-00093e 383c .dw XT_DOLITERAL
-00093f 04f1 .dw XT_CHAR
-000940 0767 .dw XT_COMMA
-000941 381f .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-000942 0006 .dw $0006
-000943 6261
-000944 726f
-000945 2274 .db "abort",'"'
-000946 0937 .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-000947 3800 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-000948 3e89 .dw XT_SQUOTE
-000949 075c .dw XT_COMPILE
-00094a 0959 .dw XT_QABORT
-00094b 381f .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-00094c ff05 .dw $ff05
-00094d 6261
-00094e 726f
-00094f 0074 .db "abort",0
-000950 0942 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000951 3800 .dw DO_COLON
- PFA_ABORT:
- .endif
-000952 394a .dw XT_TRUE
-000953 3d85 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-000954 ff06 .dw $ff06
-000955 613f
-000956 6f62
-000957 7472 .db "?abort"
-000958 094c .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-000959 3800 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-00095a 38e0
-00095b 3835 .DW XT_ROT,XT_DOCONDBRANCH
-00095c 095f DEST(QABO1)
-00095d 0403
-00095e 0951 .DW XT_ITYPE,XT_ABORT
-00095f 3ed1
-000960 381f QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000961 ff09 .dw $ff09
-000962 6567
-000963 2d74
-000964 7473
-000965 6361
-000966 006b .db "get-stack",0
-000967 0954 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-000968 3800 .dw DO_COLON
- .endif
-000969 38b0 .dw XT_DUP
-00096a 3c8f .dw XT_CELLPLUS
-00096b 38c3 .dw XT_SWAP
-00096c 3b5e .dw XT_FETCHE
-00096d 38b0 .dw XT_DUP
-00096e 38fe .dw XT_TO_R
-00096f 3953 .dw XT_ZERO
-000970 38c3 .dw XT_SWAP ; go from bigger to smaller addresses
-000971 0826 .dw XT_QDOCHECK
-000972 3835 .dw XT_DOCONDBRANCH
-000973 097f DEST(PFA_N_FETCH_E2)
-000974 3a9a .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-000975 3aab .dw XT_I
-000976 3a34 .dw XT_1MINUS
-000977 3ec3 .dw XT_CELLS ; ( -- ee-addr i*2 )
-000978 38ce .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-000979 399c .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-00097a 3b5e .dw XT_FETCHE ;( -- ee-addr item_i )
-00097b 38c3 .dw XT_SWAP ;( -- item_i ee-addr )
-00097c 394a .dw XT_TRUE ; shortcut for -1
-00097d 3ab9 .dw XT_DOPLUSLOOP
-00097e 0975 DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-00097f 3ed1 .dw XT_2DROP
-000980 38f5 .dw XT_R_FROM
-000981 381f .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-000982 ff09 .dw $ff09
-000983 6573
-000984 2d74
-000985 7473
-000986 6361
-000987 006b .db "set-stack",0
-000988 0961 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-000989 3800 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-00098a 38ce .dw XT_OVER
-00098b 3920 .dw XT_ZEROLESS
-00098c 3835 .dw XT_DOCONDBRANCH
-00098d 0991 DEST(PFA_SET_STACK0)
-00098e 383c .dw XT_DOLITERAL
-00098f fffc .dw -4
-000990 3d85 .dw XT_THROW
- PFA_SET_STACK0:
-000991 3ec8 .dw XT_2DUP
-000992 3b3a .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000993 38c3 .dw XT_SWAP
-000994 3953 .dw XT_ZERO
-000995 0826 .dw XT_QDOCHECK
-000996 3835 .dw XT_DOCONDBRANCH
-000997 099e DEST(PFA_SET_STACK2)
-000998 3a9a .dw XT_DODO
- PFA_SET_STACK1:
-000999 3c8f .dw XT_CELLPLUS ; ( -- i_x e-addr )
-00099a 3ed9 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-00099b 3b3a .dw XT_STOREE
-00099c 3ac8 .dw XT_DOLOOP
-00099d 0999 DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-00099e 38d8 .dw XT_DROP
-00099f 381f .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-0009a0 ff09 .dw $ff09
-0009a1 616d
-0009a2 2d70
-0009a3 7473
-0009a4 6361
-0009a5 006b .db "map-stack",0
-0009a6 0982 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-0009a7 3800 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-0009a8 38b0 .dw XT_DUP
-0009a9 3c8f .dw XT_CELLPLUS
-0009aa 38c3 .dw XT_SWAP
-0009ab 3b5e .dw XT_FETCHE
-0009ac 3ec3 .dw XT_CELLS
-0009ad 3f98 .dw XT_BOUNDS
-0009ae 0826 .dw XT_QDOCHECK
-0009af 3835 .dw XT_DOCONDBRANCH
-0009b0 09c3 DEST(PFA_MAPSTACK3)
-0009b1 3a9a .dw XT_DODO
- PFA_MAPSTACK1:
-0009b2 3aab .dw XT_I
-0009b3 3b5e .dw XT_FETCHE ; -- i*x XT id
-0009b4 38c3 .dw XT_SWAP
-0009b5 38fe .dw XT_TO_R
-0009b6 3907 .dw XT_R_FETCH
-0009b7 3829 .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-0009b8 38b8 .dw XT_QDUP
-0009b9 3835 .dw XT_DOCONDBRANCH
-0009ba 09bf DEST(PFA_MAPSTACK2)
-0009bb 38f5 .dw XT_R_FROM
-0009bc 38d8 .dw XT_DROP
-0009bd 3ad3 .dw XT_UNLOOP
-0009be 381f .dw XT_EXIT
- PFA_MAPSTACK2:
-0009bf 38f5 .dw XT_R_FROM
-0009c0 3fea .dw XT_TWO
-0009c1 3ab9 .dw XT_DOPLUSLOOP
-0009c2 09b2 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-0009c3 38d8 .dw XT_DROP
-0009c4 3953 .dw XT_ZERO
-0009c5 381f .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-0009c6 ff0b .dw $ff0b
-0009c7 6567
-0009c8 2d74
-0009c9 7563
-0009ca 7272
-0009cb 6e65
-0009cc 0074 .db "get-current",0
-0009cd 09a0 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-0009ce 3800 .dw DO_COLON
- PFA_GET_CURRENT:
-0009cf 383c .dw XT_DOLITERAL
-0009d0 0046 .dw CFG_CURRENT
-0009d1 3b5e .dw XT_FETCHE
-0009d2 381f .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-0009d3 ff09 .dw $ff09
-0009d4 6567
-0009d5 2d74
-0009d6 726f
-0009d7 6564
-0009d8 0072 .db "get-order",0
-0009d9 09c6 .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-0009da 3800 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-0009db 383c .dw XT_DOLITERAL
-0009dc 004a .dw CFG_ORDERLISTLEN
-0009dd 0968 .dw XT_GET_STACK
-0009de 381f .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-0009df ff09 .dw $ff09
-0009e0 6663
-0009e1 2d67
-0009e2 726f
-0009e3 6564
-0009e4 0072 .db "cfg-order",0
-0009e5 09d3 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-0009e6 3847 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-0009e7 004a .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-0009e8 ff07 .dw $ff07
-0009e9 6f63
-0009ea 706d
-0009eb 7261
-0009ec 0065 .db "compare",0
-0009ed 09df .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-0009ee 09ef .dw PFA_COMPARE
- PFA_COMPARE:
-0009ef 93bf push xh
-0009f0 93af push xl
-0009f1 018c movw temp0, tosl
-0009f2 9189
-0009f3 9199 loadtos
-0009f4 01dc movw xl, tosl
-0009f5 9189
-0009f6 9199 loadtos
-0009f7 019c movw temp2, tosl
-0009f8 9189
-0009f9 9199 loadtos
-0009fa 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-0009fb 90ed ld temp4, X+
-0009fc 90f1 ld temp5, Z+
-0009fd 14ef cp temp4, temp5
-0009fe f451 brne PFA_COMPARE_NOTEQUAL
-0009ff 950a dec temp0
-000a00 f019 breq PFA_COMPARE_ENDREACHED2
-000a01 952a dec temp2
-000a02 f7c1 brne PFA_COMPARE_LOOP
-000a03 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-000a04 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-000a05 2b02 or temp0, temp2
-000a06 f411 brne PFA_COMPARE_CHECKLASTCHAR
-000a07 2788 clr tosl
-000a08 c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-000a09 ef8f ser tosl
-000a0a c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000a0b 2f98 mov tosh, tosl
-000a0c 91af pop xl
-000a0d 91bf pop xh
-000a0e 940c 3804 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000a10 ff07 .dw $ff07
-000a11 666e
-000a12 3e61
-000a13 666c
-000a14 0061 .db "nfa>lfa",0
-000a15 09e8 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-000a16 3800 .dw DO_COLON
- PFA_NFA2LFA:
-000a17 06f5 .dw XT_NAME2STRING
-000a18 3a2e .dw XT_1PLUS
-000a19 3a03 .dw XT_2SLASH
-000a1a 399c .dw XT_PLUS
-000a1b 381f .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
-
- .include "dict/compiler2.inc" ; additional words for the compiler
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-000a1c ff0b .dw $ff0b
-000a1d 6573
-000a1e 2d74
-000a1f 7563
-000a20 7272
-000a21 6e65
-000a22 0074 .db "set-current",0
-000a23 0a10 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-000a24 3800 .dw DO_COLON
- PFA_SET_CURRENT:
-000a25 383c .dw XT_DOLITERAL
-000a26 0046 .dw CFG_CURRENT
-000a27 3b3a .dw XT_STOREE
-000a28 381f .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-000a29 ff08 .dw $ff08
-000a2a 6f77
-000a2b 6472
-000a2c 696c
-000a2d 7473 .db "wordlist"
-000a2e 0a1c .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000a2f 3800 .dw DO_COLON
- PFA_WORDLIST:
-000a30 3f1a .dw XT_EHERE
-000a31 3953 .dw XT_ZERO
-000a32 38ce .dw XT_OVER
-000a33 3b3a .dw XT_STOREE
-000a34 38b0 .dw XT_DUP
-000a35 3c8f .dw XT_CELLPLUS
-000a36 01bf .dw XT_DOTO
-000a37 3f1b .dw PFA_EHERE
-000a38 381f .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-000a39 ff0e .dw $ff0e
-000a3a 6f66
-000a3b 7472
-000a3c 2d68
-000a3d 6f77
-000a3e 6472
-000a3f 696c
-000a40 7473 .db "forth-wordlist"
-000a41 0a29 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000a42 3847 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000a43 0048 .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000a44 ff09 .dw $ff09
-000a45 6573
-000a46 2d74
-000a47 726f
-000a48 6564
-000a49 0072 .db "set-order",0
-000a4a 0a39 .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000a4b 3800 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000a4c 383c .dw XT_DOLITERAL
-000a4d 004a .dw CFG_ORDERLISTLEN
-000a4e 0989 .dw XT_SET_STACK
-000a4f 381f .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000a50 ff0f .dw $ff0f
-000a51 6573
-000a52 2d74
-000a53 6572
-000a54 6f63
-000a55 6e67
-000a56 7a69
-000a57 7265
-000a58 0073 .db "set-recognizers",0
-000a59 0a44 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000a5a 3800 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000a5b 383c .dw XT_DOLITERAL
-000a5c 005c .dw CFG_RECOGNIZERLISTLEN
-000a5d 0989 .dw XT_SET_STACK
-000a5e 381f .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000a5f ff0f .dw $ff0f
-000a60 6567
-000a61 2d74
-000a62 6572
-000a63 6f63
-000a64 6e67
-000a65 7a69
-000a66 7265
-000a67 0073 .db "get-recognizers",0
-000a68 0a50 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000a69 3800 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000a6a 383c .dw XT_DOLITERAL
-000a6b 005c .dw CFG_RECOGNIZERLISTLEN
-000a6c 0968 .dw XT_GET_STACK
-000a6d 381f .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000a6e ff04 .dw $ff04
-000a6f 6f63
-000a70 6564 .db "code"
-000a71 0a5f .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000a72 3800 .dw DO_COLON
- PFA_CODE:
-000a73 0739 .dw XT_DOCREATE
-000a74 0899 .dw XT_REVEAL
-000a75 3f11 .dw XT_DP
-000a76 01d1 .dw XT_ICELLPLUS
-000a77 0767 .dw XT_COMMA
-000a78 381f .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000a79 ff08 .dw $ff08
-000a7a 6e65
-000a7b 2d64
-000a7c 6f63
-000a7d 6564 .db "end-code"
-000a7e 0a6e .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000a7f 3800 .dw DO_COLON
- PFA_ENDCODE:
-000a80 075c .dw XT_COMPILE
-000a81 940c .dw $940c
-000a82 075c .dw XT_COMPILE
-000a83 3804 .dw DO_NEXT
-000a84 381f .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000a85 ff08 .dw $ff08
-000a86 6d28
-000a87 7261
-000a88 656b
-000a89 2972 .db "(marker)"
-000a8a 0a79 .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-000a8b 386e .dw PFA_DOVALUE1
- PFA_MARKER:
-000a8c 0068 .dw EE_MARKER
-000a8d 3d9f .dw XT_EDEFERFETCH
-000a8e 3da9 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000a8f 0008 .dw $0008
-000a90 6f70
-000a91 7473
-000a92 6f70
-000a93 656e .db "postpone"
-000a94 0a85 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000a95 3800 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000a96 05bb .dw XT_PARSENAME
-000a97 05fe .dw XT_FORTHRECOGNIZER
-000a98 0609 .dw XT_RECOGNIZE
-000a99 38b0 .dw XT_DUP
-000a9a 38fe .dw XT_TO_R
-000a9b 01d1 .dw XT_ICELLPLUS
-000a9c 01d1 .dw XT_ICELLPLUS
-000a9d 3bca .dw XT_FETCHI
-000a9e 3829 .dw XT_EXECUTE
-000a9f 38f5 .dw XT_R_FROM
-000aa0 01d1 .dw XT_ICELLPLUS
-000aa1 3bca .dw XT_FETCHI
-000aa2 0767 .dw XT_COMMA
-000aa3 381f .dw XT_EXIT
- .endif
-
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000aa4 ff0b .dw $ff0b
-000aa5 7061
-000aa6 6c70
-000aa7 7574
-000aa8 6e72
-000aa9 656b
-000aaa 0079 .db "applturnkey",0
-000aab 0a8f .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000aac 3800 .dw DO_COLON
- PFA_APPLTURNKEY:
-000aad 00c7 .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-000aae 3c96 .dw XT_INTON
- .endif
-
-000aaf 018a .dw XT_DOT_VER
-000ab0 3fad .dw XT_SPACE
-000ab1 03d0 .dw XT_DOSLITERAL
-000ab2 000a .dw 10
-000ab3 6f46
-000ab4 7472
-000ab5 6468
-000ab6 6975
-000ab7 6f6e .db "Forthduino"
-000ab8 0403 .dw XT_ITYPE
-
-000ab9 381f .dw XT_EXIT
-
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-003800 93bf push XH
-003801 93af push XL ; PUSH IP
-003802 01db movw XL, wl
-003803 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-003804 14b2 cp isrflag, zerol
-003805 f469 brne DO_INTERRUPT
- .endif
-003806 01fd movw zl, XL ; READ IP
-003807 0fee
-003808 1fff
-003809 9165
-00380a 9175 readflashcell wl, wh
-00380b 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00380c 01fb movw zl, wl
-00380d 0fee
-00380e 1fff
-00380f 9105
-003810 9115 readflashcell temp0,temp1
-003811 01f8 movw zl, temp0
-003812 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-003813 939a
-003814 938a savetos
-003815 2d8b mov tosl, isrflag
-003816 2799 clr tosh
-003817 24bb clr isrflag
-003818 eb6f ldi wl, LOW(XT_ISREXEC)
-003819 e37c ldi wh, HIGH(XT_ISREXEC)
-00381a cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00381b ff04 .dw $ff04
-00381c 7865
-00381d 7469 .db "exit"
-00381e 0aa4 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-00381f 3820 .dw PFA_EXIT
- PFA_EXIT:
-003820 91af pop XL
-003821 91bf pop XH
-003822 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-003823 ff07 .dw $ff07
-003824 7865
-003825 6365
-003826 7475
-003827 0065 .db "execute",0
-003828 381b .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-003829 382a .dw PFA_EXECUTE
- PFA_EXECUTE:
-00382a 01bc movw wl, tosl
-00382b 9189
-00382c 9199 loadtos
-00382d cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00382e 382f .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-00382f 01fd movw zl, XL
-003830 0fee
-003831 1fff
-003832 91a5
-003833 91b5 readflashcell XL,XH
-003834 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-003835 3836 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-003836 2b98 or tosh, tosl
-003837 9189
-003838 9199 loadtos
-003839 f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00383a 9611 adiw XL, 1
-00383b cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00383c 383d .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00383d 939a
-00383e 938a savetos
-00383f 01fd movw zl, xl
-003840 0fee
-003841 1fff
-003842 9185
-003843 9195 readflashcell tosl,tosh
-003844 9611 adiw xl, 1
-003845 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-003846 3847 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-003847 939a
-003848 938a savetos
-003849 01fb movw zl, wl
-00384a 9631 adiw zl,1
-00384b 0fee
-00384c 1fff
-00384d 9185
-00384e 9195 readflashcell tosl,tosh
-00384f cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-003850 3851 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-003851 939a
-003852 938a savetos
-003853 01cb movw tosl, wl
-003854 9601 adiw tosl, 1
-003855 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-003856 3857 .dw PFA_DOUSER
- PFA_DOUSER:
-003857 939a
-003858 938a savetos
-003859 01fb movw zl, wl
-00385a 9631 adiw zl, 1
-00385b 0fee
-00385c 1fff
-00385d 9185
-00385e 9195 readflashcell tosl,tosh
-00385f 0d84 add tosl, upl
-003860 1d95 adc tosh, uph
-003861 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-003862 ff07 .dw $ff07
-003863 7628
-003864 6c61
-003865 6575
-003866 0029 .db "(value)", 0
-003867 3823 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-003868 3800 .dw DO_COLON
- PFA_DOVALUE:
-003869 0739 .dw XT_DOCREATE
-00386a 0899 .dw XT_REVEAL
-00386b 075c .dw XT_COMPILE
-00386c 386e .dw PFA_DOVALUE1
-00386d 381f .dw XT_EXIT
- PFA_DOVALUE1:
-00386e 940e 08b2 call_ DO_DODOES
-003870 38b0 .dw XT_DUP
-003871 01d1 .dw XT_ICELLPLUS
-003872 3bca .dw XT_FETCHI
-003873 3829 .dw XT_EXECUTE
-003874 381f .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-003875 ff01 .dw $ff01
-003876 0040 .db "@",0
-003877 3862 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-003878 3879 .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-003879 01fc movw zl, tosl
- ; low byte is read before the high byte
-00387a 9181 ld tosl, z+
-00387b 9191 ld tosh, z+
-00387c cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00387d ff01 .dw $ff01
-00387e 0021 .db "!",0
-00387f 3875 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-003880 3881 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-003881 01fc movw zl, tosl
-003882 9189
-003883 9199 loadtos
- ; the high byte is written before the low byte
-003884 8391 std Z+1, tosh
-003885 8380 std Z+0, tosl
-003886 9189
-003887 9199 loadtos
-003888 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-003889 ff02 .dw $ff02
-00388a 2163 .db "c!"
-00388b 387d .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00388c 388d .dw PFA_CSTORE
- PFA_CSTORE:
-00388d 01fc movw zl, tosl
-00388e 9189
-00388f 9199 loadtos
-003890 8380 st Z, tosl
-003891 9189
-003892 9199 loadtos
-003893 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-003894 ff02 .dw $ff02
-003895 4063 .db "c@"
-003896 3889 .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-003897 3898 .dw PFA_CFETCH
- PFA_CFETCH:
-003898 01fc movw zl, tosl
-003899 2799 clr tosh
-00389a 8180 ld tosl, Z
-00389b cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00389c ff02 .dw $ff02
-00389d 7540 .db "@u"
-00389e 3894 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-00389f 3800 .dw DO_COLON
- PFA_FETCHU:
-0038a0 3b01 .dw XT_UP_FETCH
-0038a1 399c .dw XT_PLUS
-0038a2 3878 .dw XT_FETCH
-0038a3 381f .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-0038a4 ff02 .dw $ff02
-0038a5 7521 .db "!u"
-0038a6 389c .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-0038a7 3800 .dw DO_COLON
- PFA_STOREU:
-0038a8 3b01 .dw XT_UP_FETCH
-0038a9 399c .dw XT_PLUS
-0038aa 3880 .dw XT_STORE
-0038ab 381f .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-0038ac ff03 .dw $ff03
-0038ad 7564
-0038ae 0070 .db "dup",0
-0038af 38a4 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-0038b0 38b1 .dw PFA_DUP
- PFA_DUP:
-0038b1 939a
-0038b2 938a savetos
-0038b3 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-0038b4 ff04 .dw $ff04
-0038b5 643f
-0038b6 7075 .db "?dup"
-0038b7 38ac .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-0038b8 38b9 .dw PFA_QDUP
- PFA_QDUP:
-0038b9 2f08 mov temp0, tosl
-0038ba 2b09 or temp0, tosh
-0038bb f011 breq PFA_QDUP1
-0038bc 939a
-0038bd 938a savetos
- PFA_QDUP1:
-0038be cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-0038bf ff04 .dw $ff04
-0038c0 7773
-0038c1 7061 .db "swap"
-0038c2 38b4 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-0038c3 38c4 .dw PFA_SWAP
- PFA_SWAP:
-0038c4 018c movw temp0, tosl
-0038c5 9189
-0038c6 9199 loadtos
-0038c7 931a st -Y, temp1
-0038c8 930a st -Y, temp0
-0038c9 cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-0038ca ff04 .dw $ff04
-0038cb 766f
-0038cc 7265 .db "over"
-0038cd 38bf .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-0038ce 38cf .dw PFA_OVER
- PFA_OVER:
-0038cf 939a
-0038d0 938a savetos
-0038d1 818a ldd tosl, Y+2
-0038d2 819b ldd tosh, Y+3
-
-0038d3 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-0038d4 ff04 .dw $ff04
-0038d5 7264
-0038d6 706f .db "drop"
-0038d7 38ca .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-0038d8 38d9 .dw PFA_DROP
- PFA_DROP:
-0038d9 9189
-0038da 9199 loadtos
-0038db cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-0038dc ff03 .dw $ff03
-0038dd 6f72
-0038de 0074 .db "rot",0
-0038df 38d4 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-0038e0 38e1 .dw PFA_ROT
- PFA_ROT:
-0038e1 018c movw temp0, tosl
-0038e2 9129 ld temp2, Y+
-0038e3 9139 ld temp3, Y+
-0038e4 9189
-0038e5 9199 loadtos
-
-0038e6 933a st -Y, temp3
-0038e7 932a st -Y, temp2
-0038e8 931a st -Y, temp1
-0038e9 930a st -Y, temp0
-
-0038ea cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-0038eb ff03 .dw $ff03
-0038ec 696e
-0038ed 0070 .db "nip",0
-0038ee 38dc .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-0038ef 38f0 .dw PFA_NIP
- PFA_NIP:
-0038f0 9622 adiw yl, 2
-0038f1 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-0038f2 ff02 .dw $ff02
-0038f3 3e72 .db "r>"
-0038f4 38eb .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-0038f5 38f6 .dw PFA_R_FROM
- PFA_R_FROM:
-0038f6 939a
-0038f7 938a savetos
-0038f8 918f pop tosl
-0038f9 919f pop tosh
-0038fa cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-0038fb ff02 .dw $ff02
-0038fc 723e .db ">r"
-0038fd 38f2 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-0038fe 38ff .dw PFA_TO_R
- PFA_TO_R:
-0038ff 939f push tosh
-003900 938f push tosl
-003901 9189
-003902 9199 loadtos
-003903 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-003904 ff02 .dw $ff02
-003905 4072 .db "r@"
-003906 38fb .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-003907 3908 .dw PFA_R_FETCH
- PFA_R_FETCH:
-003908 939a
-003909 938a savetos
-00390a 918f pop tosl
-00390b 919f pop tosh
-00390c 939f push tosh
-00390d 938f push tosl
-00390e cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-00390f ff02 .dw $ff02
-003910 3e3c .db "<>"
-003911 3904 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-003912 3800 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-003913 3fde
-003914 3919
-003915 381f .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-003916 ff02 .dw $ff02
-003917 3d30 .db "0="
-003918 390f .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-003919 391a .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00391a 2b98 or tosh, tosl
-00391b f5d1 brne PFA_ZERO1
-00391c c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00391d ff02 .dw $ff02
-00391e 3c30 .db "0<"
-00391f 3916 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-003920 3921 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-003921 fd97 sbrc tosh,7
-003922 c02a rjmp PFA_TRUE1
-003923 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-003924 ff02 .dw $ff02
-003925 3e30 .db "0>"
-003926 391d .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-003927 3928 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-003928 1582 cp tosl, zerol
-003929 0593 cpc tosh, zeroh
-00392a f15c brlt PFA_ZERO1
-00392b f151 brbs 1, PFA_ZERO1
-00392c c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00392d ff03 .dw $ff03
-00392e 3064
-00392f 003e .db "d0>",0
-003930 3924 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-003931 3932 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-003932 1582 cp tosl, zerol
-003933 0593 cpc tosh, zeroh
-003934 9189
-003935 9199 loadtos
-003936 0582 cpc tosl, zerol
-003937 0593 cpc tosh, zeroh
-003938 f0ec brlt PFA_ZERO1
-003939 f0e1 brbs 1, PFA_ZERO1
-00393a c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00393b ff03 .dw $ff03
-00393c 3064
-00393d 003c .db "d0<",0
-00393e 392d .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-00393f 3940 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-003940 9622 adiw Y,2
-003941 fd97 sbrc tosh,7
-003942 940c 394d jmp PFA_TRUE1
-003944 940c 3956 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-003946 ff04 .dw $ff04
-003947 7274
-003948 6575 .db "true"
-003949 393b .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00394a 394b .dw PFA_TRUE
- PFA_TRUE:
-00394b 939a
-00394c 938a savetos
- PFA_TRUE1:
-00394d ef8f ser tosl
-00394e ef9f ser tosh
-00394f ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-003950 ff01 .dw $ff01
-003951 0030 .db "0",0
-003952 3946 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-003953 3954 .dw PFA_ZERO
- PFA_ZERO:
-003954 939a
-003955 938a savetos
- PFA_ZERO1:
-003956 01c1 movw tosl, zerol
-003957 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-003958 ff02 .dw $ff02
-003959 3c75 .db "u<"
-00395a 3950 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00395b 395c .dw PFA_ULESS
- PFA_ULESS:
-00395c 9129 ld temp2, Y+
-00395d 9139 ld temp3, Y+
-00395e 1782 cp tosl, temp2
-00395f 0793 cpc tosh, temp3
-003960 f3a8 brlo PFA_ZERO1
-003961 f3a1 brbs 1, PFA_ZERO1
-003962 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-003963 ff02 .dw $ff02
-003964 3e75 .db "u>"
-003965 3958 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-003966 3800 .dw DO_COLON
- PFA_UGREATER:
- .endif
-003967 38c3 .DW XT_SWAP
-003968 395b .dw XT_ULESS
-003969 381f .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00396a ff01 .dw $ff01
-00396b 003c .db "<",0
-00396c 3963 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00396d 396e .dw PFA_LESS
- PFA_LESS:
-00396e 9129 ld temp2, Y+
-00396f 9139 ld temp3, Y+
-003970 1728 cp temp2, tosl
-003971 0739 cpc temp3, tosh
- PFA_LESSDONE:
-003972 f71c brge PFA_ZERO1
-003973 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-003974 ff01 .dw $ff01
-003975 003e .db ">",0
-003976 396a .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-003977 3978 .dw PFA_GREATER
- PFA_GREATER:
-003978 9129 ld temp2, Y+
-003979 9139 ld temp3, Y+
-00397a 1728 cp temp2, tosl
-00397b 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00397c f2cc brlt PFA_ZERO1
-00397d f2c1 brbs 1, PFA_ZERO1
-00397e cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-00397f ff04 .dw $ff04
-003980 6f6c
-003981 3267 .db "log2"
-003982 3974 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-003983 3984 .dw PFA_LOG2
- PFA_LOG2:
-003984 01fc movw zl, tosl
-003985 2799 clr tosh
-003986 e180 ldi tosl, 16
- PFA_LOG2_1:
-003987 958a dec tosl
-003988 f022 brmi PFA_LOG2_2 ; wrong data
-003989 0fee lsl zl
-00398a 1fff rol zh
-00398b f7d8 brcc PFA_LOG2_1
-00398c ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00398d 959a dec tosh
-00398e ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-00398f ff01 .dw $ff01
-003990 002d .db "-",0
-003991 397f .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-003992 3993 .dw PFA_MINUS
- PFA_MINUS:
-003993 9109 ld temp0, Y+
-003994 9119 ld temp1, Y+
-003995 1b08 sub temp0, tosl
-003996 0b19 sbc temp1, tosh
-003997 01c8 movw tosl, temp0
-003998 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-003999 ff01 .dw $ff01
-00399a 002b .db "+",0
-00399b 398f .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00399c 399d .dw PFA_PLUS
- PFA_PLUS:
-00399d 9109 ld temp0, Y+
-00399e 9119 ld temp1, Y+
-00399f 0f80 add tosl, temp0
-0039a0 1f91 adc tosh, temp1
-0039a1 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-0039a2 ff02 .dw $ff02
-0039a3 2a6d .db "m*"
-0039a4 3999 .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-0039a5 39a6 .dw PFA_MSTAR
- PFA_MSTAR:
-0039a6 018c movw temp0, tosl
-0039a7 9189
-0039a8 9199 loadtos
-0039a9 019c movw temp2, tosl
- ; high cell ah*bh
-0039aa 0231 muls temp3, temp1
-0039ab 0170 movw temp4, r0
- ; low cell al*bl
-0039ac 9f20 mul temp2, temp0
-0039ad 01c0 movw tosl, r0
- ; signed ah*bl
-0039ae 0330 mulsu temp3, temp0
-0039af 08f3 sbc temp5, zeroh
-0039b0 0d90 add tosh, r0
-0039b1 1ce1 adc temp4, r1
-0039b2 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-0039b3 0312 mulsu temp1, temp2
-0039b4 08f3 sbc temp5, zeroh
-0039b5 0d90 add tosh, r0
-0039b6 1ce1 adc temp4, r1
-0039b7 1cf3 adc temp5, zeroh
-
-0039b8 939a
-0039b9 938a savetos
-0039ba 01c7 movw tosl, temp4
-0039bb ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-0039bc ff06 .dw $ff06
-0039bd 6d75
-0039be 6d2f
-0039bf 646f .db "um/mod"
-0039c0 39a2 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-0039c1 39c2 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-0039c2 017c movw temp4, tosl
-
-0039c3 9129 ld temp2, Y+
-0039c4 9139 ld temp3, Y+
-
-0039c5 9109 ld temp0, Y+
-0039c6 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-0039c7 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-0039c8 2755 clr temp7
-0039c9 0f00 lsl temp0
-0039ca 1f11 rol temp1
-0039cb 1f22 rol temp2
-0039cc 1f33 rol temp3
-0039cd 1f55 rol temp7
-
- ; try subtracting divisor
-0039ce 152e cp temp2, temp4
-0039cf 053f cpc temp3, temp5
-0039d0 0552 cpc temp7,zerol
-
-0039d1 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-0039d2 9503 inc temp0
-0039d3 192e sub temp2, temp4
-0039d4 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-0039d5 954a dec temp6
-0039d6 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-0039d7 933a st -Y,temp3
-0039d8 932a st -Y,temp2
-
- ; put quotient on stack
-0039d9 01c8 movw tosl, temp0
-0039da ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-0039db ff03 .dw $ff03
-0039dc 6d75
-0039dd 002a .db "um*",0
-0039de 39bc .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-0039df 39e0 .dw PFA_UMSTAR
- PFA_UMSTAR:
-0039e0 018c movw temp0, tosl
-0039e1 9189
-0039e2 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-0039e3 9f80 mul tosl,temp0
-0039e4 01f0 movw zl, r0
-0039e5 2722 clr temp2
-0039e6 2733 clr temp3
- ; middle bytes
-0039e7 9f90 mul tosh, temp0
-0039e8 0df0 add zh, r0
-0039e9 1d21 adc temp2, r1
-0039ea 1d33 adc temp3, zeroh
-
-0039eb 9f81 mul tosl, temp1
-0039ec 0df0 add zh, r0
-0039ed 1d21 adc temp2, r1
-0039ee 1d33 adc temp3, zeroh
-
-0039ef 9f91 mul tosh, temp1
-0039f0 0d20 add temp2, r0
-0039f1 1d31 adc temp3, r1
-0039f2 01cf movw tosl, zl
-0039f3 939a
-0039f4 938a savetos
-0039f5 01c9 movw tosl, temp2
-0039f6 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-0039f7 ff06 .dw $ff06
-0039f8 6e69
-0039f9 6576
-0039fa 7472 .db "invert"
-0039fb 39db .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-0039fc 39fd .dw PFA_INVERT
- PFA_INVERT:
-0039fd 9580 com tosl
-0039fe 9590 com tosh
-0039ff ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-003a00 ff02 .dw $ff02
-003a01 2f32 .db "2/"
-003a02 39f7 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-003a03 3a04 .dw PFA_2SLASH
- PFA_2SLASH:
-003a04 9595 asr tosh
-003a05 9587 ror tosl
-003a06 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-003a07 ff02 .dw $ff02
-003a08 2a32 .db "2*"
-003a09 3a00 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-003a0a 3a0b .dw PFA_2STAR
- PFA_2STAR:
-003a0b 0f88 lsl tosl
-003a0c 1f99 rol tosh
-003a0d cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-003a0e ff03 .dw $ff03
-003a0f 6e61
-003a10 0064 .db "and",0
-003a11 3a07 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-003a12 3a13 .dw PFA_AND
- PFA_AND:
-003a13 9109 ld temp0, Y+
-003a14 9119 ld temp1, Y+
-003a15 2380 and tosl, temp0
-003a16 2391 and tosh, temp1
-003a17 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-003a18 ff02 .dw $ff02
-003a19 726f .db "or"
-003a1a 3a0e .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-003a1b 3a1c .dw PFA_OR
- PFA_OR:
-003a1c 9109 ld temp0, Y+
-003a1d 9119 ld temp1, Y+
-003a1e 2b80 or tosl, temp0
-003a1f 2b91 or tosh, temp1
-003a20 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-003a21 ff03 .dw $ff03
-003a22 6f78
-003a23 0072 .db "xor",0
-003a24 3a18 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-003a25 3a26 .dw PFA_XOR
- PFA_XOR:
-003a26 9109 ld temp0, Y+
-003a27 9119 ld temp1, Y+
-003a28 2780 eor tosl, temp0
-003a29 2791 eor tosh, temp1
-003a2a cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-003a2b ff02 .dw $ff02
-003a2c 2b31 .db "1+"
-003a2d 3a21 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-003a2e 3a2f .dw PFA_1PLUS
- PFA_1PLUS:
-003a2f 9601 adiw tosl,1
-003a30 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-003a31 ff02 .dw $ff02
-003a32 2d31 .db "1-"
-003a33 3a2b .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-003a34 3a35 .dw PFA_1MINUS
- PFA_1MINUS:
-003a35 9701 sbiw tosl, 1
-003a36 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-003a37 ff07 .dw $ff07
-003a38 6e3f
-003a39 6765
-003a3a 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-003a3b 0065 .db "?negate"
-003a3c 3a31 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-003a3d 3800 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-003a3e 3920
-003a3f 3835 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-003a40 3a42 DEST(QNEG1)
-003a41 3e26 .DW XT_NEGATE
-003a42 381f QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-003a43 ff06 .dw $ff06
-003a44 736c
-003a45 6968
-003a46 7466 .db "lshift"
-003a47 3a37 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-003a48 3a49 .dw PFA_LSHIFT
- PFA_LSHIFT:
-003a49 01fc movw zl, tosl
-003a4a 9189
-003a4b 9199 loadtos
- PFA_LSHIFT1:
-003a4c 9731 sbiw zl, 1
-003a4d f01a brmi PFA_LSHIFT2
-003a4e 0f88 lsl tosl
-003a4f 1f99 rol tosh
-003a50 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-003a51 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-003a52 ff06 .dw $ff06
-003a53 7372
-003a54 6968
-003a55 7466 .db "rshift"
-003a56 3a43 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-003a57 3a58 .dw PFA_RSHIFT
- PFA_RSHIFT:
-003a58 01fc movw zl, tosl
-003a59 9189
-003a5a 9199 loadtos
- PFA_RSHIFT1:
-003a5b 9731 sbiw zl, 1
-003a5c f01a brmi PFA_RSHIFT2
-003a5d 9596 lsr tosh
-003a5e 9587 ror tosl
-003a5f cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-003a60 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-003a61 ff02 .dw $ff02
-003a62 212b .db "+!"
-003a63 3a52 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-003a64 3a65 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-003a65 01fc movw zl, tosl
-003a66 9189
-003a67 9199 loadtos
-003a68 8120 ldd temp2, Z+0
-003a69 8131 ldd temp3, Z+1
-003a6a 0f82 add tosl, temp2
-003a6b 1f93 adc tosh, temp3
-003a6c 8380 std Z+0, tosl
-003a6d 8391 std Z+1, tosh
-003a6e 9189
-003a6f 9199 loadtos
-003a70 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-003a71 ff03 .dw $ff03
-003a72 7072
-003a73 0040 .db "rp@",0
-003a74 3a61 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-003a75 3a76 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-003a76 939a
-003a77 938a savetos
-003a78 b78d in tosl, SPL
-003a79 b79e in tosh, SPH
-003a7a cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-003a7b ff03 .dw $ff03
-003a7c 7072
-003a7d 0021 .db "rp!",0
-003a7e 3a71 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-003a7f 3a80 .dw PFA_RP_STORE
- PFA_RP_STORE:
-003a80 b72f in temp2, SREG
-003a81 94f8 cli
-003a82 bf8d out SPL, tosl
-003a83 bf9e out SPH, tosh
-003a84 bf2f out SREG, temp2
-003a85 9189
-003a86 9199 loadtos
-003a87 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-003a88 ff03 .dw $ff03
-003a89 7073
-003a8a 0040 .db "sp@",0
-003a8b 3a7b .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-003a8c 3a8d .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-003a8d 939a
-003a8e 938a savetos
-003a8f 01ce movw tosl, yl
-003a90 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-003a91 ff03 .dw $ff03
-003a92 7073
-003a93 0021 .db "sp!",0
-003a94 3a88 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-003a95 3a96 .dw PFA_SP_STORE
- PFA_SP_STORE:
-003a96 01ec movw yl, tosl
-003a97 9189
-003a98 9199 loadtos
-003a99 cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-003a9a 3a9b .dw PFA_DODO
- PFA_DODO:
-003a9b 9129 ld temp2, Y+
-003a9c 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-003a9d e8e0 ldi zl, $80
-003a9e 0f3e add temp3, zl
-003a9f 1b82 sub tosl, temp2
-003aa0 0b93 sbc tosh, temp3
-
-003aa1 933f push temp3
-003aa2 932f push temp2 ; limit ( --> limit + $8000)
-003aa3 939f push tosh
-003aa4 938f push tosl ; start -> index ( --> index - (limit - $8000)
-003aa5 9189
-003aa6 9199 loadtos
-003aa7 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-003aa8 ff01 .dw $FF01
-003aa9 0069 .db "i",0
-003aaa 3a91 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-003aab 3aac .dw PFA_I
- PFA_I:
-003aac 939a
-003aad 938a savetos
-003aae 918f pop tosl
-003aaf 919f pop tosh ; index
-003ab0 91ef pop zl
-003ab1 91ff pop zh ; limit
-003ab2 93ff push zh
-003ab3 93ef push zl
-003ab4 939f push tosh
-003ab5 938f push tosl
-003ab6 0f8e add tosl, zl
-003ab7 1f9f adc tosh, zh
-003ab8 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-003ab9 3aba .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-003aba 91ef pop zl
-003abb 91ff pop zh
-003abc 0fe8 add zl, tosl
-003abd 1ff9 adc zh, tosh
-003abe 9189
-003abf 9199 loadtos
-003ac0 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-003ac1 93ff push zh
-003ac2 93ef push zl
-003ac3 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-003ac4 910f pop temp0
-003ac5 911f pop temp1 ; remove limit
-003ac6 9611 adiw xl, 1 ; skip branch-back address
-003ac7 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-003ac8 3ac9 .dw PFA_DOLOOP
- PFA_DOLOOP:
-003ac9 91ef pop zl
-003aca 91ff pop zh
-003acb 9631 adiw zl,1
-003acc f3bb brvs PFA_DOPLUSLOOP_LEAVE
-003acd cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-003ace ff06 .dw $ff06
-003acf 6e75
-003ad0 6f6c
-003ad1 706f .db "unloop"
-003ad2 3aa8 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-003ad3 3ad4 .dw PFA_UNLOOP
- PFA_UNLOOP:
-003ad4 911f pop temp1
-003ad5 910f pop temp0
-003ad6 911f pop temp1
-003ad7 910f pop temp0
-003ad8 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-003ad9 ff06 .dw $ff06
-003ada 6d63
-003adb 766f
-003adc 3e65 .db "cmove>"
-003add 3ace .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-003ade 3adf .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-003adf 93bf push xh
-003ae0 93af push xl
-003ae1 91e9 ld zl, Y+
-003ae2 91f9 ld zh, Y+ ; addr-to
-003ae3 91a9 ld xl, Y+
-003ae4 91b9 ld xh, Y+ ; addr-from
-003ae5 2f09 mov temp0, tosh
-003ae6 2b08 or temp0, tosl
-003ae7 f041 brbs 1, PFA_CMOVE_G1
-003ae8 0fe8 add zl, tosl
-003ae9 1ff9 adc zh, tosh
-003aea 0fa8 add xl, tosl
-003aeb 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-003aec 911e ld temp1, -X
-003aed 9312 st -Z, temp1
-003aee 9701 sbiw tosl, 1
-003aef f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-003af0 91af pop xl
-003af1 91bf pop xh
-003af2 9189
-003af3 9199 loadtos
-003af4 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-003af5 ff02 .dw $ff02
-003af6 3c3e .db "><"
-003af7 3ad9 .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-003af8 3af9 .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-003af9 2f09 mov temp0, tosh
-003afa 2f98 mov tosh, tosl
-003afb 2f80 mov tosl, temp0
-003afc cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-003afd ff03 .dw $ff03
-003afe 7075
-003aff 0040 .db "up@",0
-003b00 3af5 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-003b01 3b02 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-003b02 939a
-003b03 938a savetos
-003b04 01c2 movw tosl, upl
-003b05 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-003b06 ff03 .dw $ff03
-003b07 7075
-003b08 0021 .db "up!",0
-003b09 3afd .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-003b0a 3b0b .dw PFA_UP_STORE
- PFA_UP_STORE:
-003b0b 012c movw upl, tosl
-003b0c 9189
-003b0d 9199 loadtos
-003b0e ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-003b0f ff03 .dw $ff03
-003b10 6d31
-003b11 0073 .db "1ms",0
-003b12 3b06 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-003b13 3b14 .dw PFA_1MS
- PFA_1MS:
-003b14 eae0
-003b15 e0ff
-003b16 9731
-003b17 f7f1 delay 1000
-003b18 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-003b19 ff03 .dw $ff03
-003b1a 3e32
-003b1b 0072 .db "2>r",0
-003b1c 3b0f .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-003b1d 3b1e .dw PFA_2TO_R
- PFA_2TO_R:
-003b1e 01fc movw zl, tosl
-003b1f 9189
-003b20 9199 loadtos
-003b21 939f push tosh
-003b22 938f push tosl
-003b23 93ff push zh
-003b24 93ef push zl
-003b25 9189
-003b26 9199 loadtos
-003b27 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-003b28 ff03 .dw $ff03
-003b29 7232
-003b2a 003e .db "2r>",0
-003b2b 3b19 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-003b2c 3b2d .dw PFA_2R_FROM
- PFA_2R_FROM:
-003b2d 939a
-003b2e 938a savetos
-003b2f 91ef pop zl
-003b30 91ff pop zh
-003b31 918f pop tosl
-003b32 919f pop tosh
-003b33 939a
-003b34 938a savetos
-003b35 01cf movw tosl, zl
-003b36 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-003b37 ff02 .dw $ff02
-003b38 6521 .db "!e"
-003b39 3b28 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-003b3a 3b3b .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-003b3b 01fc movw zl, tosl
-003b3c 9189
-003b3d 9199 loadtos
-003b3e b72f in_ temp2, SREG
-003b3f 94f8 cli
-003b40 d028 rcall PFA_FETCHE2
-003b41 b500 in_ temp0, EEDR
-003b42 1708 cp temp0,tosl
-003b43 f009 breq PFA_STOREE3
-003b44 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-003b45 9631 adiw zl,1
-003b46 d022 rcall PFA_FETCHE2
-003b47 b500 in_ temp0, EEDR
-003b48 1709 cp temp0,tosh
-003b49 f011 breq PFA_STOREE4
-003b4a 2f89 mov tosl, tosh
-003b4b d004 rcall PFA_STOREE1
- PFA_STOREE4:
-003b4c bf2f out_ SREG, temp2
-003b4d 9189
-003b4e 9199 loadtos
-003b4f ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-003b50 99f9 sbic EECR, EEPE
-003b51 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-003b52 b707 in_ temp0, SPMCSR
-003b53 fd00 sbrc temp0,SPMEN
-003b54 cffd rjmp PFA_STOREE2
-
-003b55 bdf2 out_ EEARH,zh
-003b56 bde1 out_ EEARL,zl
-003b57 bd80 out_ EEDR, tosl
-003b58 9afa sbi EECR,EEMPE
-003b59 9af9 sbi EECR,EEPE
-
-003b5a 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-003b5b ff02 .dw $ff02
-003b5c 6540 .db "@e"
-003b5d 3b37 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-003b5e 3b5f .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-003b5f b72f in_ temp2, SREG
-003b60 94f8 cli
-003b61 01fc movw zl, tosl
-003b62 d006 rcall PFA_FETCHE2
-003b63 b580 in_ tosl, EEDR
-
-003b64 9631 adiw zl,1
-
-003b65 d003 rcall PFA_FETCHE2
-003b66 b590 in_ tosh, EEDR
-003b67 bf2f out_ SREG, temp2
-003b68 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-003b69 99f9 sbic EECR, EEPE
-003b6a cffe rjmp PFA_FETCHE2
-
-003b6b bdf2 out_ EEARH,zh
-003b6c bde1 out_ EEARL,zl
-
-003b6d 9af8 sbi EECR,EERE
-003b6e 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-003b6f ff02 .dw $ff02
-003b70 6921 .db "!i"
-003b71 3b5b .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-003b72 3dfe .dw PFA_DODEFER1
- PFA_STOREI:
-003b73 0066 .dw EE_STOREI
-003b74 3d9f .dw XT_EDEFERFETCH
-003b75 3da9 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-003b76 ff09 .dw $ff09
-003b77 2128
-003b78 2d69
-003b79 726e
-003b7a 7777
-003b7b 0029 .db "(!i-nrww)",0
-003b7c 3b6f .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-003b7d 3b7e .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-003b7e b71f in temp1,SREG
-003b7f 931f push temp1
-003b80 94f8 cli
-
-003b81 019c movw temp2, tosl ; save the (word) address
-003b82 9189
-003b83 9199 loadtos ; get the new value for the flash cell
-003b84 93af push xl
-003b85 93bf push xh
-003b86 93cf push yl
-003b87 93df push yh
-003b88 d009 rcall DO_STOREI_atmega
-003b89 91df pop yh
-003b8a 91cf pop yl
-003b8b 91bf pop xh
-003b8c 91af pop xl
- ; finally clear the stack
-003b8d 9189
-003b8e 9199 loadtos
-003b8f 911f pop temp1
- ; restore status register (and interrupt enable flag)
-003b90 bf1f out SREG,temp1
-
-003b91 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-003b92 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-003b93 94e0 com temp4
-003b94 94f0 com temp5
-003b95 218e and tosl, temp4
-003b96 219f and tosh, temp5
-003b97 2b98 or tosh, tosl
-003b98 f019 breq DO_STOREI_writepage
-003b99 01f9 movw zl, temp2
-003b9a e002 ldi temp0,(1<<PGERS)
-003b9b d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-003b9c 01f9 movw zl, temp2
-003b9d e004 ldi temp0,(1<<PGWRT)
-003b9e d01d rcall dospm
-
- ; reenable RWW section
-003b9f 01f9 movw zl, temp2
-003ba0 e100 ldi temp0,(1<<RWWSRE)
-003ba1 d01a rcall dospm
-003ba2 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-003ba3 01f9 movw zl, temp2
- ; get the beginning of page
-003ba4 7ce0 andi zl,low(pagemask)
-003ba5 7fff andi zh,high(pagemask)
-003ba6 01ef movw y, z
- ; loop counter (in words)
-003ba7 e4a0 ldi xl,low(pagesize)
-003ba8 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-003ba9 01fe movw z, y
-003baa 0fee
-003bab 1fff
-003bac 9145
-003bad 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-003bae 01fe movw z, y
-003baf 17e2 cp zl, temp2
-003bb0 07f3 cpc zh, temp3
-003bb1 f011 breq pageload_newdata
-003bb2 010a movw r0, temp6
-003bb3 c002 rjmp pageload_cont
- pageload_newdata:
-003bb4 017a movw temp4, temp6
-003bb5 010c movw r0, tosl
- pageload_cont:
-003bb6 2700 clr temp0
-003bb7 d004 rcall dospm
-003bb8 9621 adiw y, 1
-003bb9 9711 sbiw x, 1
-003bba f771 brne pageload_loop
-
- pageload_done:
-003bbb 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-003bbc 99f9 sbic EECR, EEPE
-003bbd cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-003bbe b717 in_ temp1, SPMCSR
-003bbf fd10 sbrc temp1, SPMEN
-003bc0 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-003bc1 0fee
-003bc2 1fff writeflashcell
- ; execute spm
-003bc3 6001 ori temp0, (1<<SPMEN)
-003bc4 bf07 out_ SPMCSR,temp0
-003bc5 95e8 spm
-003bc6 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-003bc7 ff02 .dw $ff02
-003bc8 6940 .db "@i"
-003bc9 3b76 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-003bca 3bcb .dw PFA_FETCHI
- PFA_FETCHI:
-003bcb 01fc movw zl, tosl
-003bcc 0fee
-003bcd 1fff
-003bce 9185
-003bcf 9195 readflashcell tosl,tosh
-003bd0 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .elif AMFORTH_NRWW_SIZE>4000
- .include "dict/core_4k.inc"
-
- ; in a short distance to DO_NEXT
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-003bd1 ff03 .dw $ff03
-003bd2 3e6e
-003bd3 0072 .db "n>r",0
-003bd4 3bc7 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-003bd5 3bd6 .dw PFA_N_TO_R
- PFA_N_TO_R:
-003bd6 01fc movw zl, tosl
-003bd7 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-003bd8 9189
-003bd9 9199 loadtos
-003bda 939f push tosh
-003bdb 938f push tosl
-003bdc 950a dec temp0
-003bdd f7d1 brne PFA_N_TO_R1
-003bde 93ef push zl
-003bdf 93ff push zh
-003be0 9189
-003be1 9199 loadtos
-003be2 cc21 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-003be3 ff03 .dw $ff03
-003be4 726e
-003be5 003e .db "nr>",0
-003be6 3bd1 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-003be7 3be8 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-003be8 939a
-003be9 938a savetos
-003bea 91ff pop zh
-003beb 91ef pop zl
-003bec 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-003bed 918f pop tosl
-003bee 919f pop tosh
-003bef 939a
-003bf0 938a savetos
-003bf1 950a dec temp0
-003bf2 f7d1 brne PFA_N_R_FROM1
-003bf3 01cf movw tosl, zl
-003bf4 cc0f jmp_ DO_NEXT
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-003bf5 ff03 .dw $ff03
-003bf6 3264
-003bf7 002a .db "d2*",0
-003bf8 3be3 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-003bf9 3bfa .dw PFA_D2STAR
- PFA_D2STAR:
-003bfa 9109 ld temp0, Y+
-003bfb 9119 ld temp1, Y+
-003bfc 0f00 lsl temp0
-003bfd 1f11 rol temp1
-003bfe 1f88 rol tosl
-003bff 1f99 rol tosh
-003c00 931a st -Y, temp1
-003c01 930a st -Y, temp0
-003c02 cc01 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-003c03 ff03 .dw $ff03
-003c04 3264
-003c05 002f .db "d2/",0
-003c06 3bf5 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-003c07 3c08 .dw PFA_D2SLASH
- PFA_D2SLASH:
-003c08 9109 ld temp0, Y+
-003c09 9119 ld temp1, Y+
-003c0a 9595 asr tosh
-003c0b 9587 ror tosl
-003c0c 9517 ror temp1
-003c0d 9507 ror temp0
-003c0e 931a st -Y, temp1
-003c0f 930a st -Y, temp0
-003c10 cbf3 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-003c11 ff02 .dw $ff02
-003c12 2b64 .db "d+"
-003c13 3c03 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-003c14 3c15 .dw PFA_DPLUS
- PFA_DPLUS:
-003c15 9129 ld temp2, Y+
-003c16 9139 ld temp3, Y+
-
-003c17 90e9 ld temp4, Y+
-003c18 90f9 ld temp5, Y+
-003c19 9149 ld temp6, Y+
-003c1a 9159 ld temp7, Y+
-
-003c1b 0f24 add temp2, temp6
-003c1c 1f35 adc temp3, temp7
-003c1d 1d8e adc tosl, temp4
-003c1e 1d9f adc tosh, temp5
-
-003c1f 933a st -Y, temp3
-003c20 932a st -Y, temp2
-003c21 cbe2 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-003c22 ff02 .dw $ff02
-003c23 2d64 .db "d-"
-003c24 3c11 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-003c25 3c26 .dw PFA_DMINUS
- PFA_DMINUS:
-003c26 9129 ld temp2, Y+
-003c27 9139 ld temp3, Y+
-
-003c28 90e9 ld temp4, Y+
-003c29 90f9 ld temp5, Y+
-003c2a 9149 ld temp6, Y+
-003c2b 9159 ld temp7, Y+
-
-003c2c 1b42 sub temp6, temp2
-003c2d 0b53 sbc temp7, temp3
-003c2e 0ae8 sbc temp4, tosl
-003c2f 0af9 sbc temp5, tosh
-
-003c30 935a st -Y, temp7
-003c31 934a st -Y, temp6
-003c32 01c7 movw tosl, temp4
-003c33 cbd0 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-003c34 ff07 .dw $ff07
-003c35 6964
-003c36 766e
-003c37 7265
-003c38 0074 .db "dinvert",0
-003c39 3c22 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-003c3a 3c3b .dw PFA_DINVERT
- PFA_DINVERT:
-003c3b 9109 ld temp0, Y+
-003c3c 9119 ld temp1, Y+
-003c3d 9580 com tosl
-003c3e 9590 com tosh
-003c3f 9500 com temp0
-003c40 9510 com temp1
-003c41 931a st -Y, temp1
-003c42 930a st -Y, temp0
-003c43 cbc0 jmp_ DO_NEXT
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-003c44 ff04 .dw $ff04
-003c45 6d2f
-003c46 646f .db "/mod"
-003c47 3c34 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-003c48 3c49 .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-003c49 019c movw temp2, tosl
-
-003c4a 9109 ld temp0, Y+
-003c4b 9119 ld temp1, Y+
-
-003c4c 2f41 mov temp6,temp1 ;move dividend High to sign register
-003c4d 2743 eor temp6,temp3 ;xor divisor High with sign register
-003c4e ff17 sbrs temp1,7 ;if MSB in dividend set
-003c4f c004 rjmp PFA_SLASHMOD_1
-003c50 9510 com temp1 ; change sign of dividend
-003c51 9500 com temp0
-003c52 5f0f subi temp0,low(-1)
-003c53 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-003c54 ff37 sbrs temp3,7 ;if MSB in divisor set
-003c55 c004 rjmp PFA_SLASHMOD_2
-003c56 9530 com temp3 ; change sign of divisor
-003c57 9520 com temp2
-003c58 5f2f subi temp2,low(-1)
-003c59 4f3f sbci temp3,high(-1)
-003c5a 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-003c5b 18ff sub temp5,temp5;clear remainder High byte and carry
-003c5c e151 ldi temp7,17 ;init loop counter
-
-003c5d 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-003c5e 1f11 rol temp1
-003c5f 955a dec temp7 ;decrement counter
-003c60 f439 brne PFA_SLASHMOD_5 ;if done
-003c61 ff47 sbrs temp6,7 ; if MSB in sign register set
-003c62 c004 rjmp PFA_SLASHMOD_4
-003c63 9510 com temp1 ; change sign of result
-003c64 9500 com temp0
-003c65 5f0f subi temp0,low(-1)
-003c66 4f1f sbci temp1,high(-1)
-003c67 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-003c68 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-003c69 1cff rol temp5
-003c6a 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-003c6b 0af3 sbc temp5,temp3 ;
-003c6c f420 brcc PFA_SLASHMOD_6 ;if result negative
-003c6d 0ee2 add temp4,temp2 ; restore remainder
-003c6e 1ef3 adc temp5,temp3
-003c6f 9488 clc ; clear carry to be shifted into result
-003c70 cfec rjmp PFA_SLASHMOD_3 ;else
-003c71 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-003c72 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-003c73 92fa st -Y,temp5
-003c74 92ea st -Y,temp4
-
- ; put quotient on stack
-003c75 01c8 movw tosl, temp0
-003c76 cb8d jmp_ DO_NEXT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-003c77 ff03 .dw $ff03
-003c78 6261
-003c79 0073 .db "abs",0
-003c7a 3c44 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-003c7b 3800 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-003c7c 38b0
-003c7d 3a3d
-003c7e 381f .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-003c7f ff04 .dw $ff04
-003c80 6970
-003c81 6b63 .db "pick"
-003c82 3c77 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-003c83 3800 .dw DO_COLON
- PFA_PICK:
- .endif
-003c84 3a2e .dw XT_1PLUS
-003c85 3ec3 .dw XT_CELLS
-003c86 3a8c .dw XT_SP_FETCH
-003c87 399c .dw XT_PLUS
-003c88 3878 .dw XT_FETCH
-003c89 381f .dw XT_EXIT
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-003c8a ff05 .dw $ff05
-003c8b 6563
-003c8c 6c6c
-003c8d 002b .db "cell+",0
-003c8e 3c7f .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-003c8f 3c90 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-003c90 9602 adiw tosl, CELLSIZE
-003c91 cb72 jmp_ DO_NEXT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-003c92 ff04 .dw $ff04
-003c93 692b
-003c94 746e .db "+int"
-003c95 3c8a .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-003c96 3c97 .dw PFA_INTON
- PFA_INTON:
-003c97 9478 sei
-003c98 cb6b jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-003c99 ff04 .dw $ff04
-003c9a 692d
-003c9b 746e .db "-int"
-003c9c 3c92 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-003c9d 3c9e .dw PFA_INTOFF
- PFA_INTOFF:
-003c9e 94f8 cli
-003c9f cb64 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-003ca0 ff04 .dw $ff04
-003ca1 6e69
-003ca2 2174 .db "int!"
-003ca3 3c99 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-003ca4 3800 .dw DO_COLON
- PFA_INTSTORE:
-003ca5 383c .dw XT_DOLITERAL
-003ca6 0000 .dw intvec
-003ca7 399c .dw XT_PLUS
-003ca8 3b3a .dw XT_STOREE
-003ca9 381f .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-003caa ff04 .dw $ff04
-003cab 6e69
-003cac 4074 .db "int@"
-003cad 3ca0 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-003cae 3800 .dw DO_COLON
- PFA_INTFETCH:
-003caf 383c .dw XT_DOLITERAL
-003cb0 0000 .dw intvec
-003cb1 399c .dw XT_PLUS
-003cb2 3b5e .dw XT_FETCHE
-003cb3 381f .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-003cb4 ff08 .dw $ff08
-003cb5 6e69
-003cb6 2d74
-003cb7 7274
-003cb8 7061 .db "int-trap"
-003cb9 3caa .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-003cba 3cbb .dw PFA_INTTRAP
- PFA_INTTRAP:
-003cbb 2eb8 mov isrflag, tosl
-003cbc 9189
-003cbd 9199 loadtos
-003cbe cb45 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-003cbf 3800 .dw DO_COLON
- PFA_ISREXEC:
-003cc0 3cae .dw XT_INTFETCH
-003cc1 3829 .dw XT_EXECUTE
-003cc2 3cc4 .dw XT_ISREND
-003cc3 381f .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-003cc4 3cc5 .dw PFA_ISREND
- PFA_ISREND:
-003cc5 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-003cc6 cb3d jmp_ DO_NEXT
- PFA_ISREND1:
-003cc7 9518 reti
- .endif
-
- ; now the relocatable colon words
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-003cc8 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-003cc9 03d0 .dw XT_DOSLITERAL
-003cca 0003 .dw 3
-003ccb 6f20
-003ccc 006b .db " ok",0
- .endif
-003ccd 0403 .dw XT_ITYPE
-003cce 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-003ccf ff03 .dw $FF03
-003cd0 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-003cd1 006b .db ".ok"
-003cd2 3cb4 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-003cd3 3dfe .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-003cd4 001c .dw USER_P_OK
-003cd5 3dc7 .dw XT_UDEFERFETCH
-003cd6 3dd3 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-003cd7 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-003cd8 03d0 .dw XT_DOSLITERAL
-003cd9 0002 .dw 2
-003cda 203e .db "> "
- .endif
-003cdb 3fa0 .dw XT_CR
-003cdc 0403 .dw XT_ITYPE
-003cdd 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-003cde ff06 .dw $FF06
-003cdf 722e
-003ce0 6165
-003ce1 7964 .db ".ready"
-003ce2 3ccf .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-003ce3 3dfe .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-003ce4 0020 .dw USER_P_RDY
-003ce5 3dc7 .dw XT_UDEFERFETCH
-003ce6 3dd3 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-003ce7 3800 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-003ce8 03d0 .dw XT_DOSLITERAL
-003ce9 0004 .dw 4
-003cea 3f20
-003ceb 203f .db " ?? "
- .endif
-003cec 0403 .dw XT_ITYPE
-003ced 3ebc .dw XT_BASE
-003cee 3878 .dw XT_FETCH
-003cef 38fe .dw XT_TO_R
-003cf0 3f40 .dw XT_DECIMAL
-003cf1 0385 .dw XT_DOT
-003cf2 3ee1 .dw XT_TO_IN
-003cf3 3878 .dw XT_FETCH
-003cf4 0385 .dw XT_DOT
-003cf5 38f5 .dw XT_R_FROM
-003cf6 3ebc .dw XT_BASE
-003cf7 3880 .dw XT_STORE
-003cf8 381f .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-003cf9 ff06 .dw $FF06
-003cfa 652e
-003cfb 7272
-003cfc 726f .db ".error"
-003cfd 3cde .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-003cfe 3dfe .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-003cff 001e .dw USER_P_ERR
-003d00 3dc7 .dw XT_UDEFERFETCH
-003d01 3dd3 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-003d02 ff04 .dw $ff04
-003d03 7571
-003d04 7469 .db "quit"
-003d05 3cf9 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-003d06 3800 .dw DO_COLON
- .endif
- PFA_QUIT:
-003d07 085c
-003d08 0863
-003d09 3880 .dw XT_LP0,XT_LP,XT_STORE
-003d0a 05d5 .dw XT_SP0
-003d0b 3a95 .dw XT_SP_STORE
-003d0c 05e2 .dw XT_RP0
-003d0d 3a7f .dw XT_RP_STORE
-003d0e 08f1 .dw XT_LBRACKET
-
- PFA_QUIT2:
-003d0f 3eb6 .dw XT_STATE
-003d10 3878 .dw XT_FETCH
-003d11 3919 .dw XT_ZEROEQUAL
-003d12 3835 .dw XT_DOCONDBRANCH
-003d13 3d15 DEST(PFA_QUIT4)
-003d14 3ce3 .dw XT_PROMPTREADY
- PFA_QUIT4:
-003d15 04e9 .dw XT_REFILL
-003d16 3835 .dw XT_DOCONDBRANCH
-003d17 3d27 DEST(PFA_QUIT3)
-003d18 383c .dw XT_DOLITERAL
-003d19 0630 .dw XT_INTERPRET
-003d1a 3d6f .dw XT_CATCH
-003d1b 38b8 .dw XT_QDUP
-003d1c 3835 .dw XT_DOCONDBRANCH
-003d1d 3d27 DEST(PFA_QUIT3)
-003d1e 38b0 .dw XT_DUP
-003d1f 383c .dw XT_DOLITERAL
-003d20 fffe .dw -2
-003d21 396d .dw XT_LESS
-003d22 3835 .dw XT_DOCONDBRANCH
-003d23 3d25 DEST(PFA_QUIT5)
-003d24 3cfe .dw XT_PROMPTERROR
- PFA_QUIT5:
-003d25 382e .dw XT_DOBRANCH
-003d26 3d07 DEST(PFA_QUIT)
- PFA_QUIT3:
-003d27 3cd3 .dw XT_PROMPTOK
-003d28 382e .dw XT_DOBRANCH
-003d29 3d0f DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-003d2a ff05 .dw $ff05
-003d2b 6170
-003d2c 7375
-003d2d 0065 .db "pause",0
-003d2e 3d02 .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-003d2f 3dfe .dw PFA_DODEFER1
- PFA_PAUSE:
-003d30 0192 .dw ram_pause
-003d31 3db3 .dw XT_RDEFERFETCH
-003d32 3dbd .dw XT_RDEFERSTORE
-
- .dseg
-000192 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-003d33 ff04 .dw $ff04
-003d34 6f63
-003d35 646c .db "cold"
-003d36 3d2a .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-003d37 3d38 .dw PFA_COLD
- PFA_COLD:
-003d38 b6a4 in_ mcu_boot, MCUSR
-003d39 2422 clr zerol
-003d3a 2433 clr zeroh
-003d3b 24bb clr isrflag
-003d3c be24 out_ MCUSR, zerol
- ; clear RAM
-003d3d e0e0 ldi zl, low(ramstart)
-003d3e e0f1 ldi zh, high(ramstart)
- clearloop:
-003d3f 9221 st Z+, zerol
-003d40 30e0 cpi zl, low(sram_size+ramstart)
-003d41 f7e9 brne clearloop
-003d42 30f9 cpi zh, high(sram_size+ramstart)
-003d43 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000194 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-003d44 e9e4 ldi zl, low(ram_user1)
-003d45 e0f1 ldi zh, high(ram_user1)
-003d46 012f movw upl, zl
- ; init return stack pointer
-003d47 ef0f ldi temp0,low(rstackstart)
-003d48 bf0d out_ SPL,temp0
-003d49 8304 std Z+4, temp0
-003d4a e018 ldi temp1,high(rstackstart)
-003d4b bf1e out_ SPH,temp1
-003d4c 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-003d4d eacf ldi yl,low(stackstart)
-003d4e 83c6 std Z+6, yl
-003d4f e0d8 ldi yh,high(stackstart)
-003d50 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-003d51 e5a9 ldi XL, low(PFA_WARM)
-003d52 e3bd ldi XH, high(PFA_WARM)
- ; its a far jump...
-003d53 cab0 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-003d54 ff04 .dw $ff04
-003d55 6177
-003d56 6d72 .db "warm"
-003d57 3d33 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-003d58 3800 .dw DO_COLON
- PFA_WARM:
- .endif
-003d59 02a2 .dw XT_INIT_RAM
-003d5a 383c .dw XT_DOLITERAL
-003d5b 01a5 .dw XT_NOOP
-003d5c 383c .dw XT_DOLITERAL
-003d5d 3d2f .dw XT_PAUSE
-003d5e 3dde .dw XT_DEFERSTORE
-003d5f 08f1 .dw XT_LBRACKET
-003d60 3f5b .dw XT_TURNKEY
-003d61 3d06 .dw XT_QUIT ; never returns
-
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-003d62 ff07 .dw $ff07
-003d63 6168
-003d64 646e
-003d65 656c
-003d66 0072 .db "handler",0
-003d67 3d54 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-003d68 3857 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-003d69 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-003d6a ff05 .dw $ff05
-003d6b 6163
-003d6c 6374
-003d6d 0068 .db "catch",0
-003d6e 3d62 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-003d6f 3800 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-003d70 3a8c .dw XT_SP_FETCH
-003d71 38fe .dw XT_TO_R
- ; handler @ >r
-003d72 3d68 .dw XT_HANDLER
-003d73 3878 .dw XT_FETCH
-003d74 38fe .dw XT_TO_R
- ; rp@ handler !
-003d75 3a75 .dw XT_RP_FETCH
-003d76 3d68 .dw XT_HANDLER
-003d77 3880 .dw XT_STORE
-003d78 3829 .dw XT_EXECUTE
- ; r> handler !
-003d79 38f5 .dw XT_R_FROM
-003d7a 3d68 .dw XT_HANDLER
-003d7b 3880 .dw XT_STORE
-003d7c 38f5 .dw XT_R_FROM
-003d7d 38d8 .dw XT_DROP
-003d7e 3953 .dw XT_ZERO
-003d7f 381f .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-003d80 ff05 .dw $ff05
-003d81 6874
-003d82 6f72
-003d83 0077 .db "throw",0
-003d84 3d6a .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-003d85 3800 .dw DO_COLON
- PFA_THROW:
- .endif
-003d86 38b0 .dw XT_DUP
-003d87 3919 .dw XT_ZEROEQUAL
-003d88 3835 .dw XT_DOCONDBRANCH
-003d89 3d8c DEST(PFA_THROW1)
-003d8a 38d8 .dw XT_DROP
-003d8b 381f .dw XT_EXIT
- PFA_THROW1:
-003d8c 3d68 .dw XT_HANDLER
-003d8d 3878 .dw XT_FETCH
-003d8e 3a7f .dw XT_RP_STORE
-003d8f 38f5 .dw XT_R_FROM
-003d90 3d68 .dw XT_HANDLER
-003d91 3880 .dw XT_STORE
-003d92 38f5 .dw XT_R_FROM
-003d93 38c3 .dw XT_SWAP
-003d94 38fe .dw XT_TO_R
-003d95 3a95 .dw XT_SP_STORE
-003d96 38d8 .dw XT_DROP
-003d97 38f5 .dw XT_R_FROM
-003d98 381f .dw XT_EXIT
-
-
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-003d99 ff07 .dw $ff07
-003d9a 6445
-003d9b 6665
-003d9c 7265
-003d9d 0040 .db "Edefer@",0
-003d9e 3d80 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-003d9f 3800 .dw DO_COLON
- PFA_EDEFERFETCH:
-003da0 3bca .dw XT_FETCHI
-003da1 3b5e .dw XT_FETCHE
-003da2 381f .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-003da3 ff07 .dw $ff07
-003da4 6445
-003da5 6665
-003da6 7265
-003da7 0021 .db "Edefer!",0
-003da8 3d99 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-003da9 3800 .dw DO_COLON
- PFA_EDEFERSTORE:
-003daa 3bca .dw XT_FETCHI
-003dab 3b3a .dw XT_STOREE
-003dac 381f .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-003dad ff07 .dw $ff07
-003dae 6452
-003daf 6665
-003db0 7265
-003db1 0040 .db "Rdefer@",0
-003db2 3da3 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-003db3 3800 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-003db4 3bca .dw XT_FETCHI
-003db5 3878 .dw XT_FETCH
-003db6 381f .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-003db7 ff07 .dw $ff07
-003db8 6452
-003db9 6665
-003dba 7265
-003dbb 0021 .db "Rdefer!",0
-003dbc 3dad .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-003dbd 3800 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-003dbe 3bca .dw XT_FETCHI
-003dbf 3880 .dw XT_STORE
-003dc0 381f .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-003dc1 ff07 .dw $ff07
-003dc2 6455
-003dc3 6665
-003dc4 7265
-003dc5 0040 .db "Udefer@",0
-003dc6 3db7 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-003dc7 3800 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-003dc8 3bca .dw XT_FETCHI
-003dc9 3b01 .dw XT_UP_FETCH
-003dca 399c .dw XT_PLUS
-003dcb 3878 .dw XT_FETCH
-003dcc 381f .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-003dcd ff07 .dw $ff07
-003dce 6455
-003dcf 6665
-003dd0 7265
-003dd1 0021 .db "Udefer!",0
-003dd2 3dc1 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-003dd3 3800 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-003dd4 3bca .dw XT_FETCHI
-003dd5 3b01 .dw XT_UP_FETCH
-003dd6 399c .dw XT_PLUS
-003dd7 3880 .dw XT_STORE
-003dd8 381f .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-003dd9 ff06 .dw $ff06
-003dda 6564
-003ddb 6566
-003ddc 2172 .db "defer!"
-003ddd 3dcd .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-003dde 3800 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-003ddf 3fcf .dw XT_TO_BODY
-003de0 38b0 .dw XT_DUP
-003de1 01d1 .dw XT_ICELLPLUS
-003de2 01d1 .dw XT_ICELLPLUS
-003de3 3bca .dw XT_FETCHI
-003de4 3829 .dw XT_EXECUTE
-003de5 381f .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-003de6 ff06 .dw $ff06
-003de7 6564
-003de8 6566
-003de9 4072 .db "defer@"
-003dea 3dd9 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-003deb 3800 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-003dec 3fcf .dw XT_TO_BODY
-003ded 38b0 .dw XT_DUP
-003dee 01d1 .dw XT_ICELLPLUS
-003def 3bca .dw XT_FETCHI
-003df0 3829 .dw XT_EXECUTE
-003df1 381f .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-003df2 ff07 .dw $ff07
-003df3 6428
-003df4 6665
-003df5 7265
-003df6 0029 .db "(defer)", 0
-003df7 3de6 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-003df8 3800 .dw DO_COLON
- PFA_DODEFER:
-003df9 0739 .dw XT_DOCREATE
-003dfa 0899 .dw XT_REVEAL
-003dfb 075c .dw XT_COMPILE
-003dfc 3dfe .dw PFA_DODEFER1
-003dfd 381f .dw XT_EXIT
- PFA_DODEFER1:
-003dfe 940e 08b2 call_ DO_DODOES
-003e00 38b0 .dw XT_DUP
-003e01 01d1 .dw XT_ICELLPLUS
-003e02 3bca .dw XT_FETCHI
-003e03 3829 .dw XT_EXECUTE
-003e04 3829 .dw XT_EXECUTE
-003e05 381f .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-003e06 ff02 .dw $ff02
-003e07 2e75 .db "u."
-003e08 3df2 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-003e09 3800 .dw DO_COLON
- PFA_UDOT:
- .endif
-003e0a 3953 .dw XT_ZERO
-003e0b 038d .dw XT_UDDOT
-003e0c 381f .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-003e0d ff03 .dw $ff03
-003e0e 2e75
-003e0f 0072 .db "u.r",0
-003e10 3e06 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-003e11 3800 .dw DO_COLON
- PFA_UDOTR:
- .endif
-003e12 3953 .dw XT_ZERO
-003e13 38c3 .dw XT_SWAP
-003e14 0396 .dw XT_UDDOTR
-003e15 381f .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-003e16 ff05 .dw $ff05
-003e17 2f75
-003e18 6f6d
-003e19 0064 .db "u/mod",0
-003e1a 3e0d .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-003e1b 3800 .dw DO_COLON
- PFA_USLASHMOD:
-003e1c 38fe .dw XT_TO_R
-003e1d 3953 .dw XT_ZERO
-003e1e 38f5 .dw XT_R_FROM
-003e1f 39c1 .dw XT_UMSLASHMOD
-003e20 381f .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-003e21 ff06 .dw $ff06
-003e22 656e
-003e23 6167
-003e24 6574 .db "negate"
-003e25 3e16 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-003e26 3800 .dw DO_COLON
- PFA_NEGATE:
-003e27 39fc .dw XT_INVERT
-003e28 3a2e .dw XT_1PLUS
-003e29 381f .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-003e2a ff01 .dw $ff01
-003e2b 002f .db "/",0
-003e2c 3e21 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-003e2d 3800 .dw DO_COLON
- PFA_SLASH:
- .endif
-003e2e 3c48 .dw XT_SLASHMOD
-003e2f 38ef .dw XT_NIP
-003e30 381f .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-003e31 ff03 .dw $ff03
-003e32 6f6d
-003e33 0064 .db "mod",0
-003e34 3e2a .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-003e35 3800 .dw DO_COLON
- PFA_MOD:
- .endif
-003e36 3c48 .dw XT_SLASHMOD
-003e37 38d8 .dw XT_DROP
-003e38 381f .dw XT_EXIT
-
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-003e39 ff03 .dw $ff03
-003e3a 696d
-003e3b 006e .db "min",0
-003e3c 3e31 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-003e3d 3800 .dw DO_COLON
- PFA_MIN:
- .endif
-003e3e 3ec8 .dw XT_2DUP
-003e3f 3977 .dw XT_GREATER
-003e40 3835 .dw XT_DOCONDBRANCH
-003e41 3e43 DEST(PFA_MIN1)
-003e42 38c3 .dw XT_SWAP
- PFA_MIN1:
-003e43 38d8 .dw XT_DROP
-003e44 381f .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-003e45 ff03 .dw $ff03
-003e46 616d
-003e47 0078 .db "max",0
-003e48 3e39 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-003e49 3800 .dw DO_COLON
- PFA_MAX:
-
- .endif
-003e4a 3ec8 .dw XT_2DUP
-003e4b 396d .dw XT_LESS
-003e4c 3835 .dw XT_DOCONDBRANCH
-003e4d 3e4f DEST(PFA_MAX1)
-003e4e 38c3 .dw XT_SWAP
- PFA_MAX1:
-003e4f 38d8 .dw XT_DROP
-003e50 381f .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-003e51 ff06 .dw $ff06
-003e52 6977
-003e53 6874
-003e54 6e69 .db "within"
-003e55 3e45 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-003e56 3800 .dw DO_COLON
- PFA_WITHIN:
- .endif
-003e57 38ce .dw XT_OVER
-003e58 3992 .dw XT_MINUS
-003e59 38fe .dw XT_TO_R
-003e5a 3992 .dw XT_MINUS
-003e5b 38f5 .dw XT_R_FROM
-003e5c 395b .dw XT_ULESS
-003e5d 381f .dw XT_EXIT
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-003e5e ff0d .dw $ff0d
-003e5f 6873
-003e60 776f
-003e61 772d
-003e62 726f
-003e63 6c64
-003e64 7369
-003e65 0074 .db "show-wordlist",0
-003e66 3e51 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-003e67 3800 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-003e68 383c .dw XT_DOLITERAL
-003e69 3e6d .dw XT_SHOWWORD
-003e6a 38c3 .dw XT_SWAP
-003e6b 06da .dw XT_TRAVERSEWORDLIST
-003e6c 381f .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-003e6d 3800 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-003e6e 06f5 .dw XT_NAME2STRING
-003e6f 0403 .dw XT_ITYPE
-003e70 3fad .dw XT_SPACE ; ( -- addr n)
-003e71 394a .dw XT_TRUE
-003e72 381f .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-003e73 ff05 .dw $ff05
-003e74 6f77
-003e75 6472
-003e76 0073 .db "words",0
-003e77 3e5e .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-003e78 3800 .dw DO_COLON
- PFA_WORDS:
- .endif
-003e79 383c .dw XT_DOLITERAL
-003e7a 004c .dw CFG_ORDERLISTLEN+2
-003e7b 3b5e .dw XT_FETCHE
-003e7c 3e67 .dw XT_SHOWWORDLIST
-003e7d 381f .dw XT_EXIT
-
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-003e7e 0002 .dw $0002
-003e7f 222e .db ".",$22
-003e80 3e73 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-003e81 3800 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-003e82 3e89 .dw XT_SQUOTE
-003e83 075c .dw XT_COMPILE
-003e84 0403 .dw XT_ITYPE
-003e85 381f .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-003e86 0002 .dw $0002
-003e87 2273 .db "s",$22
-003e88 3e7e .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-003e89 3800 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-003e8a 383c .dw XT_DOLITERAL
-003e8b 0022 .dw 34 ; 0x22
-003e8c 058e .dw XT_PARSE ; ( -- addr n)
-003e8d 3eb6 .dw XT_STATE
-003e8e 3878 .dw XT_FETCH
-003e8f 3835 .dw XT_DOCONDBRANCH
-003e90 3e92 DEST(PFA_SQUOTE1)
-003e91 0788 .dw XT_SLITERAL
- PFA_SQUOTE1:
-003e92 381f .dw XT_EXIT
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-003e93 ff04 .dw $ff04
-003e94 6966
-003e95 6c6c .db "fill"
-003e96 3e86 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-003e97 3800 .dw DO_COLON
- PFA_FILL:
-003e98 38e0 .dw XT_ROT
-003e99 38e0 .dw XT_ROT
-003e9a 38b8
-003e9b 3835 .dw XT_QDUP,XT_DOCONDBRANCH
-003e9c 3ea4 DEST(PFA_FILL2)
-003e9d 3f98 .dw XT_BOUNDS
-003e9e 3a9a .dw XT_DODO
- PFA_FILL1:
-003e9f 38b0 .dw XT_DUP
-003ea0 3aab .dw XT_I
-003ea1 388c .dw XT_CSTORE ; ( -- c c-addr)
-003ea2 3ac8 .dw XT_DOLOOP
-003ea3 3e9f .dw PFA_FILL1
- PFA_FILL2:
-003ea4 38d8 .dw XT_DROP
-003ea5 381f .dw XT_EXIT
-
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-003ea6 ff05 .dw $ff05
-003ea7 5f66
-003ea8 7063
-003ea9 0075 .db "f_cpu",0
-003eaa 3e93 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-003eab 3800 .dw DO_COLON
- PFA_F_CPU:
- .endif
-003eac 383c .dw XT_DOLITERAL
-003ead 2400 .dw (F_CPU % 65536)
-003eae 383c .dw XT_DOLITERAL
-003eaf 00f4 .dw (F_CPU / 65536)
-003eb0 381f .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-003eb1 ff05 .dw $ff05
-003eb2 7473
-003eb3 7461
-003eb4 0065 .db "state",0
-003eb5 3ea6 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-003eb6 3847 .dw PFA_DOVARIABLE
- PFA_STATE:
-003eb7 01c0 .dw ram_state
-
- .dseg
-0001c0 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-003eb8 ff04 .dw $ff04
-003eb9 6162
-003eba 6573 .db "base"
-003ebb 3eb1 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-003ebc 3857 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-003ebd 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-003ebe ff05 .dw $ff05
-003ebf 6563
-003ec0 6c6c
-003ec1 0073 .db "cells",0
-003ec2 3eb8 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-003ec3 3a0b .dw PFA_2STAR
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-003ec4 ff04 .dw $ff04
-003ec5 6432
-003ec6 7075 .db "2dup"
-003ec7 3ebe .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-003ec8 3800 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-003ec9 38ce .dw XT_OVER
-003eca 38ce .dw XT_OVER
-003ecb 381f .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-003ecc ff05 .dw $ff05
-003ecd 6432
-003ece 6f72
-003ecf 0070 .db "2drop",0
-003ed0 3ec4 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-003ed1 3800 .dw DO_COLON
- PFA_2DROP:
- .endif
-003ed2 38d8 .dw XT_DROP
-003ed3 38d8 .dw XT_DROP
-003ed4 381f .dw XT_EXIT
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-003ed5 ff04 .dw $ff04
-003ed6 7574
-003ed7 6b63 .db "tuck"
-003ed8 3ecc .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-003ed9 3800 .dw DO_COLON
- PFA_TUCK:
- .endif
-003eda 38c3 .dw XT_SWAP
-003edb 38ce .dw XT_OVER
-003edc 381f .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-003edd ff03 .dw $ff03
-003ede 693e
-003edf 006e .db ">in",0
-003ee0 3ed5 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-003ee1 3857 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-003ee2 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-003ee3 ff03 .dw $ff03
-003ee4 6170
-003ee5 0064 .db "pad",0
-003ee6 3edd .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-003ee7 3800 .dw DO_COLON
- PFA_PAD:
- .endif
-003ee8 3f22 .dw XT_HERE
-003ee9 383c .dw XT_DOLITERAL
-003eea 0028 .dw 40
-003eeb 399c .dw XT_PLUS
-003eec 381f .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-003eed ff04 .dw $ff04
-003eee 6d65
-003eef 7469 .db "emit"
-003ef0 3ee3 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-003ef1 3dfe .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-003ef2 000e .dw USER_EMIT
-003ef3 3dc7 .dw XT_UDEFERFETCH
-003ef4 3dd3 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-003ef5 ff05 .dw $ff05
-003ef6 6d65
-003ef7 7469
-003ef8 003f .db "emit?",0
-003ef9 3eed .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-003efa 3dfe .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-003efb 0010 .dw USER_EMITQ
-003efc 3dc7 .dw XT_UDEFERFETCH
-003efd 3dd3 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-003efe ff03 .dw $ff03
-003eff 656b
-003f00 0079 .db "key",0
-003f01 3ef5 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-003f02 3dfe .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-003f03 0012 .dw USER_KEY
-003f04 3dc7 .dw XT_UDEFERFETCH
-003f05 3dd3 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-003f06 ff04 .dw $ff04
-003f07 656b
-003f08 3f79 .db "key?"
-003f09 3efe .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-003f0a 3dfe .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-003f0b 0014 .dw USER_KEYQ
-003f0c 3dc7 .dw XT_UDEFERFETCH
-003f0d 3dd3 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-003f0e ff02 .dw $ff02
-003f0f 7064 .db "dp"
-003f10 3f06 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-003f11 386e .dw PFA_DOVALUE1
- PFA_DP:
-003f12 0036 .dw CFG_DP
-003f13 3d9f .dw XT_EDEFERFETCH
-003f14 3da9 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-003f15 ff05 .dw $ff05
-003f16 6865
-003f17 7265
-003f18 0065 .db "ehere",0
-003f19 3f0e .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-003f1a 386e .dw PFA_DOVALUE1
- PFA_EHERE:
-003f1b 003a .dw EE_EHERE
-003f1c 3d9f .dw XT_EDEFERFETCH
-003f1d 3da9 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-003f1e ff04 .dw $ff04
-003f1f 6568
-003f20 6572 .db "here"
-003f21 3f15 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-003f22 386e .dw PFA_DOVALUE1
- PFA_HERE:
-003f23 0038 .dw EE_HERE
-003f24 3d9f .dw XT_EDEFERFETCH
-003f25 3da9 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-003f26 ff05 .dw $ff05
-003f27 6c61
-003f28 6f6c
-003f29 0074 .db "allot",0
-003f2a 3f1e .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-003f2b 3800 .dw DO_COLON
- PFA_ALLOT:
-003f2c 3f22 .dw XT_HERE
-003f2d 399c .dw XT_PLUS
-003f2e 01bf .dw XT_DOTO
-003f2f 3f23 .dw PFA_HERE
-003f30 381f .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-003f31 ff03 .dw $ff03
-003f32 6962
-003f33 006e .db "bin",0
-003f34 3f26 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-003f35 3800 .dw DO_COLON
- PFA_BIN:
- .endif
-003f36 3fea .dw XT_TWO
-003f37 3ebc .dw XT_BASE
-003f38 3880 .dw XT_STORE
-003f39 381f .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-003f3a ff07 .dw $ff07
-003f3b 6564
-003f3c 6963
-003f3d 616d
-003f3e 006c .db "decimal",0
-003f3f 3f31 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-003f40 3800 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-003f41 383c .dw XT_DOLITERAL
-003f42 000a .dw 10
-003f43 3ebc .dw XT_BASE
-003f44 3880 .dw XT_STORE
-003f45 381f .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-003f46 ff03 .dw $ff03
-003f47 6568
-003f48 0078 .db "hex",0
-003f49 3f3a .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-003f4a 3800 .dw DO_COLON
- PFA_HEX:
- .endif
-003f4b 383c .dw XT_DOLITERAL
-003f4c 0010 .dw 16
-003f4d 3ebc .dw XT_BASE
-003f4e 3880 .dw XT_STORE
-003f4f 381f .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-003f50 ff02 .dw $ff02
-003f51 6c62 .db "bl"
-003f52 3f46 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-003f53 3847 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-003f54 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-003f55 ff07 .dw $ff07
-003f56 7574
-003f57 6e72
-003f58 656b
-003f59 0079 .db "turnkey",0
-003f5a 3f50 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-003f5b 3dfe .dw PFA_DODEFER1
- PFA_TURNKEY:
-003f5c 0042 .dw CFG_TURNKEY
-003f5d 3d9f .dw XT_EDEFERFETCH
-003f5e 3da9 .dw XT_EDEFERSTORE
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-003f5f ff07 .dw $ff07
-003f60 6f74
-003f61 7075
-003f62 6570
-003f63 0072 .db "toupper",0
-003f64 3f55 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-003f65 3800 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-003f66 38b0 .dw XT_DUP
-003f67 383c .dw XT_DOLITERAL
-003f68 0061 .dw 'a'
-003f69 383c .dw XT_DOLITERAL
-003f6a 007b .dw 'z'+1
-003f6b 3e56 .dw XT_WITHIN
-003f6c 3835 .dw XT_DOCONDBRANCH
-003f6d 3f71 DEST(PFA_TOUPPER0)
-003f6e 383c .dw XT_DOLITERAL
-003f6f 00df .dw 223 ; inverse of 0x20: 0xdf
-003f70 3a12 .dw XT_AND
- PFA_TOUPPER0:
-003f71 381f .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-003f72 ff07 .dw $ff07
-003f73 6f74
-003f74 6f6c
-003f75 6577
-003f76 0072 .db "tolower",0
-003f77 3f5f .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-003f78 3800 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-003f79 38b0 .dw XT_DUP
-003f7a 383c .dw XT_DOLITERAL
-003f7b 0041 .dw 'A'
-003f7c 383c .dw XT_DOLITERAL
-003f7d 005b .dw 'Z'+1
-003f7e 3e56 .dw XT_WITHIN
-003f7f 3835 .dw XT_DOCONDBRANCH
-003f80 3f84 DEST(PFA_TOLOWER0)
-003f81 383c .dw XT_DOLITERAL
-003f82 0020 .dw 32
-003f83 3a1b .dw XT_OR
- PFA_TOLOWER0:
-003f84 381f .dw XT_EXIT
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-003f85 ff06 .dw $ff06
-003f86 733f
-003f87 6174
-003f88 6b63 .db "?stack"
-003f89 3f72 .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-003f8a 3800 .dw DO_COLON
- PFA_QSTACK:
- .endif
-003f8b 05ed .dw XT_DEPTH
-003f8c 3920 .dw XT_ZEROLESS
-003f8d 3835 .dw XT_DOCONDBRANCH
-003f8e 3f92 DEST(PFA_QSTACK1)
-003f8f 383c .dw XT_DOLITERAL
-003f90 fffc .dw -4
-003f91 3d85 .dw XT_THROW
- PFA_QSTACK1:
-003f92 381f .dw XT_EXIT
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-003f93 ff06 .dw $ff06
-003f94 6f62
-003f95 6e75
-003f96 7364 .db "bounds"
-003f97 3f85 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-003f98 3800 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-003f99 38ce .dw XT_OVER
-003f9a 399c .dw XT_PLUS
-003f9b 38c3 .dw XT_SWAP
-003f9c 381f .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-003f9d ff02 .dw 0xff02
-003f9e 7263 .db "cr"
-003f9f 3f93 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-003fa0 3800 .dw DO_COLON
- PFA_CR:
- .endif
-
-003fa1 383c .dw XT_DOLITERAL
-003fa2 000d .dw 13
-003fa3 3ef1 .dw XT_EMIT
-003fa4 383c .dw XT_DOLITERAL
-003fa5 000a .dw 10
-003fa6 3ef1 .dw XT_EMIT
-003fa7 381f .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-003fa8 ff05 .dw $ff05
-003fa9 7073
-003faa 6361
-003fab 0065 .db "space",0
-003fac 3f9d .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-003fad 3800 .dw DO_COLON
- PFA_SPACE:
- .endif
-003fae 3f53 .dw XT_BL
-003faf 3ef1 .dw XT_EMIT
-003fb0 381f .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-003fb1 ff06 .dw $ff06
-003fb2 7073
-003fb3 6361
-003fb4 7365 .db "spaces"
-003fb5 3fa8 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-003fb6 3800 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-003fb7 3953
-003fb8 3e49 .DW XT_ZERO, XT_MAX
-003fb9 38b0
-003fba 3835 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-003fbb 3fc0 DEST(SPCS2)
-003fbc 3fad
-003fbd 3a34
-003fbe 382e .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-003fbf 3fb9 DEST(SPCS1)
-003fc0 38d8
-003fc1 381f SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-003fc2 ff03 .dw $ff03
-003fc3 3e73
-003fc4 0064 .db "s>d",0
-003fc5 3fb1 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-003fc6 3800 .dw DO_COLON
- PFA_S2D:
- .endif
-003fc7 38b0 .dw XT_DUP
-003fc8 3920 .dw XT_ZEROLESS
-003fc9 381f .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-003fca ff05 .dw $ff05
-003fcb 623e
-003fcc 646f
-003fcd 0079 .db ">body",0
-003fce 3fc2 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-003fcf 3a2f .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-003fd0 0008 .dw $0008
-003fd1 6c32
-003fd2 7469
-003fd3 7265
-003fd4 6c61 .db "2literal"
-003fd5 3fca .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-003fd6 3800 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-003fd7 38c3 .dw XT_SWAP
-003fd8 077d .dw XT_LITERAL
-003fd9 077d .dw XT_LITERAL
-003fda 381f .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-003fdb ff01 .dw $ff01
-003fdc 003d .db "=",0
-003fdd 3fd0 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-003fde 3800 .dw DO_COLON
- PFA_EQUAL:
-003fdf 3992 .dw XT_MINUS
-003fe0 3919 .dw XT_ZEROEQUAL
-003fe1 381f .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-003fe2 ff01 .dw $ff01
-003fe3 0031 .db "1",0
-003fe4 3fdb .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-003fe5 3847 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-003fe6 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-003fe7 ff01 .dw $ff01
-003fe8 0032 .db "2",0
-003fe9 3fe2 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-003fea 3847 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-003feb 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-003fec ff02 .dw $ff02
-003fed 312d .db "-1"
-003fee 3fe7 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-003fef 3847 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-003ff0 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000034 ff ff
- ; some configs
-000036 ba 0a CFG_DP: .dw DPSTART ; Dictionary Pointer
-000038 c2 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00003a 8e 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00003c ce 09 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-00003e 5c 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000040 b0 08 CFG_LP0: .dw stackstart+1
-000042 ac 0a CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000044 ff 02 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000046 48 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-000048 ec 3f CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00004a 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00004c 48 00 .dw CFG_FORTHWORDLIST ; get/set-order
-00004e .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00005c 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-00005e 70 06 .dw XT_REC_FIND
-000060 5c 06 .dw XT_REC_NUM
-000062 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-000066 7d 3b .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-000068 68 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00006a 00 00 .dw 0 ; USER_STATE
-00006c 00 00 .dw 0 ; USER_FOLLOWER
-00006e ff 08 .dw rstackstart ; USER_RP
-000070 af 08 .dw stackstart ; USER_SP0
-000072 af 08 .dw stackstart ; USER_SP
-
-000074 00 00 .dw 0 ; USER_HANDLER
-000076 0a 00 .dw 10 ; USER_BASE
-
-000078 a3 00 .dw XT_TX ; USER_EMIT
-00007a b1 00 .dw XT_TXQ ; USER_EMITQ
-00007c 78 00 .dw XT_RX ; USER_KEY
-00007e 93 00 .dw XT_RXQ ; USER_KEYQ
-000080 77 02 .dw XT_SOURCETIB ; USER_SOURCE
-000082 00 00 .dw 0 ; USER_G_IN
-000084 64 02 .dw XT_REFILLTIB ; USER_REFILL
-000086 c8 3c .dw XT_DEFAULT_PROMPTOK
-000088 e7 3c .dw XT_DEFAULT_PROMPTERROR
-00008a d7 3c .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-00008c 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega328P" register use summary:
-r0 : 25 r1 : 5 r2 : 9 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 80 r17: 61 r18: 52 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 193 r25: 136 r26: 28 r27: 17 r28: 7 r29: 4 r30: 85 r31: 47
-x : 4 y : 205 z : 48
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega328P" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 20 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 0
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 13 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 18 inc : 3 jmp : 9
-ld : 136 ldd : 4 ldi : 41 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 16 movw : 65 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 2 out : 18 pop : 45
-push : 39 rcall : 38 ret : 6 reti : 1 rjmp : 103 rol : 23
-ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3 sbis : 0
-sbiw : 14 sbr : 0 sbrc : 5 sbrs : 4 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 4 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 76 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 71 out of 113 (62.8%)
-
-"ATmega328P" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x007fe2 1958 11618 13576 32768 41.4%
-[.dseg] 0x000100 0x0001c2 0 194 194 2048 9.5%
-[.eseg] 0x000000 0x00008e 0 142 142 1024 13.9%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/arduino/uno.map b/amforth-6.5/appl/arduino/uno.map
deleted file mode 100644
index b3bd846..0000000
--- a/amforth-6.5/appl/arduino/uno.map
+++ /dev/null
@@ -1,2030 +0,0 @@
-
-AVRASM ver. 2.1.52 uno.asm Sun Apr 30 20:10:12 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000095
-EQU SIGNATURE_002 0000000f
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK1 0000006c
-EQU PCMSK2 0000006d
-EQU PCMSK0 0000006b
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU WGM11 00000001
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU PSRSYNC 00000000
-EQU TSM 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ACME 00000006
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSR10 00000000
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SELFPRGEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU BODSE 00000005
-EQU BODS 00000006
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU EXTREF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU DWEN 00000006
-EQU RSTDISBL 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00003fff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00000800
-EQU RAMEND 000008ff
-EQU XRAMEND 00000000
-EQU E2END 000003ff
-EQU EEPROMEND 000003ff
-EQU EEADRBITS 0000000a
-EQU NRWW_START_ADDR 00003800
-EQU NRWW_STOP_ADDR 00003fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 000037ff
-EQU PAGESIZE 00000040
-EQU FIRSTBOOTSTART 00003f00
-EQU SECONDBOOTSTART 00003e00
-EQU THIRDBOOTSTART 00003c00
-EQU FOURTHBOOTSTART 00003800
-EQU SMALLBOOTSTART 00003f00
-EQU LARGEBOOTSTART 00003800
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU PCI0addr 00000006
-EQU PCI1addr 00000008
-EQU PCI2addr 0000000a
-EQU WDTaddr 0000000c
-EQU OC2Aaddr 0000000e
-EQU OC2Baddr 00000010
-EQU OVF2addr 00000012
-EQU ICP1addr 00000014
-EQU OC1Aaddr 00000016
-EQU OC1Baddr 00000018
-EQU OVF1addr 0000001a
-EQU OC0Aaddr 0000001c
-EQU OC0Baddr 0000001e
-EQU OVF0addr 00000020
-EQU SPIaddr 00000022
-EQU URXCaddr 00000024
-EQU UDREaddr 00000026
-EQU UTXCaddr 00000028
-EQU ADCCaddr 0000002a
-EQU ERDYaddr 0000002c
-EQU ACIaddr 0000002e
-EQU TWIaddr 00000030
-EQU SPMRaddr 00000032
-EQU INT_VECTORS_SIZE 00000034
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_USART0 00000000
-SET WANT_TWI 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_SPI 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_CPU 00000000
-SET WANT_EEPROM 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 00000129
-EQU INTVECTORS 0000001a
-EQU SPMEN 00000000
-CSEG mcu_info 00000033
-CSEG mcu_ramsize 00000033
-CSEG mcu_eepromsize 00000034
-CSEG mcu_maxdp 00000035
-CSEG mcu_numints 00000036
-CSEG mcu_name 00000037
-SET codestart 0000003d
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000008ff
-SET stackstart 000008af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000000a
-SET VE_HEAD 00003fec
-SET VE_ENVHEAD 000002ff
-SET AMFORTH_RO_SEG 00003800
-EQU F_CPU 00f42400
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 0000003d
-CSEG XT_TO_RXBUF 00000043
-CSEG PFA_rx_tobuf 00000044
-CSEG DO_NEXT 00003804
-CSEG VE_ISR_RX 00000054
-CSEG XT_ISR_RX 00000059
-CSEG DO_COLON 00003800
-CSEG usart_rx_isr 0000005a
-CSEG XT_DOLITERAL 0000383c
-CSEG XT_CFETCH 00003897
-CSEG XT_DUP 000038b0
-CSEG XT_EQUAL 00003fde
-CSEG XT_DOCONDBRANCH 00003835
-CSEG usart_rx_isr1 00000064
-CSEG XT_COLD 00003d37
-CSEG XT_EXIT 0000381f
-CSEG XT_USART_INIT_RX_BUFFER 00000066
-CSEG PFA_USART_INIT_RX_BUFFER 00000067
-CSEG XT_INTSTORE 00003ca4
-CSEG XT_ZERO 00003953
-CSEG XT_FILL 00003e97
-CSEG VE_RX_BUFFER 00000073
-CSEG XT_RX_BUFFER 00000078
-CSEG PFA_RX_BUFFER 00000079
-CSEG XT_RXQ_BUFFER 00000093
-CSEG XT_PLUS 0000399c
-CSEG XT_SWAP 000038c3
-CSEG XT_1PLUS 00003a2e
-CSEG XT_AND 00003a12
-CSEG XT_CSTORE 0000388c
-CSEG VE_RXQ_BUFFER 0000008d
-CSEG PFA_RXQ_BUFFER 00000094
-CSEG XT_PAUSE 00003d2f
-CSEG XT_NOTEQUAL 00003912
-SET XT_RX 00000078
-SET XT_RXQ 00000093
-SET XT_USART_INIT_RX 00000066
-CSEG VE_TX_POLL 0000009d
-CSEG XT_TX_POLL 000000a3
-CSEG PFA_TX_POLL 000000a4
-CSEG XT_TXQ_POLL 000000b1
-CSEG VE_TXQ_POLL 000000ab
-CSEG PFA_TXQ_POLL 000000b2
-SET XT_TX 000000a3
-SET XT_TXQ 000000b1
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000ba
-CSEG XT_UBRR 000000be
-CSEG PFA_DOVALUE1 0000386e
-CSEG PFA_UBRR 000000bf
-ESEG EE_UBRRVAL 0000008c
-CSEG XT_EDEFERFETCH 00003d9f
-CSEG XT_EDEFERSTORE 00003da9
-CSEG VE_USART 000000c2
-CSEG XT_USART 000000c7
-CSEG PFA_USART 000000c8
-CSEG XT_BYTESWAP 00003af8
-EQU OW_PORT 00000005
-EQU OW_BIT 00000004
-SET OW_DDR 00000004
-SET OW_PIN 00000003
-CSEG VE_OW_RESET 000000dd
-CSEG XT_OW_RESET 000000e3
-CSEG PFA_OW_RESET 000000e4
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_OW_SLOT 00000101
-CSEG XT_OW_SLOT 00000107
-CSEG PFA_OW_SLOT 00000108
-CSEG PFA_OW_SLOT0 00000115
-SET AMFORTH_NRWW_SIZE 00000ffe
-SET corepc 00000129
-CSEG PFA_COLD 00003d38
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 00000140
-CSEG XT_MPLUS 00000143
-CSEG PFA_MPLUS 00000144
-CSEG XT_S2D 00003fc6
-CSEG XT_DPLUS 00003c14
-CSEG VE_UDSTAR 00000147
-CSEG XT_UDSTAR 0000014b
-CSEG PFA_UDSTAR 0000014c
-CSEG XT_TO_R 000038fe
-CSEG XT_UMSTAR 000039df
-CSEG XT_DROP 000038d8
-CSEG XT_R_FROM 000038f5
-CSEG XT_ROT 000038e0
-CSEG VE_UMAX 00000156
-CSEG XT_UMAX 0000015a
-CSEG PFA_UMAX 0000015b
-CSEG XT_2DUP 00003ec8
-CSEG XT_ULESS 0000395b
-CSEG UMAX1 00000160
-CSEG VE_UMIN 00000162
-CSEG XT_UMIN 00000166
-CSEG PFA_UMIN 00000167
-CSEG XT_UGREATER 00003966
-CSEG UMIN1 0000016c
-CSEG XT_IMMEDIATEQ 0000016e
-CSEG PFA_IMMEDIATEQ 0000016f
-CSEG XT_ZEROEQUAL 00003919
-CSEG IMMEDIATEQ1 00000177
-CSEG XT_ONE 00003fe5
-CSEG XT_TRUE 0000394a
-CSEG VE_NAME2FLAGS 00000179
-CSEG XT_NAME2FLAGS 00000180
-CSEG PFA_NAME2FLAGS 00000181
-CSEG XT_FETCHI 00003bca
-CSEG VE_DOT_VER 00000186
-CSEG XT_DOT_VER 0000018a
-CSEG PFA_DOT_VER 0000018b
-CSEG XT_ENV_FORTHNAME 000002da
-CSEG XT_ITYPE 00000403
-CSEG XT_SPACE 00003fad
-CSEG XT_BASE 00003ebc
-CSEG XT_FETCH 00003878
-CSEG XT_ENV_FORTHVERSION 000002e8
-CSEG XT_DECIMAL 00003f40
-CSEG XT_L_SHARP 00000321
-CSEG XT_SHARP 00000329
-CSEG XT_HOLD 00000312
-CSEG XT_SHARP_S 0000033f
-CSEG XT_SHARP_G 0000034a
-CSEG XT_TYPE 00000439
-CSEG XT_STORE 00003880
-CSEG XT_ENV_CPU 000002f0
-CSEG VE_NOOP 000001a1
-CSEG XT_NOOP 000001a5
-CSEG PFA_NOOP 000001a6
-CSEG VE_UNUSED 000001a7
-CSEG XT_UNUSED 000001ac
-CSEG PFA_UNUSED 000001ad
-CSEG XT_SP_FETCH 00003a8c
-CSEG XT_HERE 00003f22
-CSEG XT_MINUS 00003992
-CSEG VE_TO 000001b1
-CSEG XT_TO 000001b4
-CSEG PFA_TO 000001b5
-CSEG XT_TICK 00000448
-CSEG XT_TO_BODY 00003fcf
-CSEG XT_STATE 00003eb6
-CSEG PFA_TO1 000001c5
-CSEG XT_COMPILE 0000075c
-CSEG XT_DOTO 000001bf
-CSEG XT_COMMA 00000767
-CSEG PFA_DOTO 000001c0
-CSEG XT_ICELLPLUS 000001d1
-CSEG XT_EXECUTE 00003829
-CSEG VE_ICELLPLUS 000001cb
-CSEG PFA_ICELLPLUS 000001d2
-CSEG VE_ICOMPARE 000001d4
-CSEG XT_ICOMPARE 000001da
-CSEG PFA_ICOMPARE 000001db
-CSEG XT_OVER 000038ce
-CSEG PFA_ICOMPARE_SAMELEN 000001e5
-CSEG XT_2DROP 00003ed1
-CSEG XT_QDOCHECK 00000826
-CSEG PFA_ICOMPARE_DONE 00000208
-CSEG XT_DODO 00003a9a
-CSEG PFA_ICOMPARE_LOOP 000001eb
-CSEG PFA_ICOMPARE_LASTCELL 000001f9
-CSEG PFA_ICOMPARE_NEXTLOOP 00000200
-CSEG XT_UNLOOP 00003ad3
-CSEG XT_CELLPLUS 00003c8f
-CSEG XT_DOPLUSLOOP 00003ab9
-CSEG VE_STAR 0000020b
-CSEG XT_STAR 0000020e
-CSEG PFA_STAR 0000020f
-CSEG XT_MSTAR 000039a5
-CSEG VE_J 00000212
-CSEG XT_J 00000215
-CSEG PFA_J 00000216
-CSEG XT_RP_FETCH 00003a75
-CSEG VE_DABS 00000222
-CSEG XT_DABS 00000226
-CSEG PFA_DABS 00000227
-CSEG XT_ZEROLESS 00003920
-CSEG PFA_DABS1 0000022c
-CSEG XT_DNEGATE 00000233
-CSEG VE_DNEGATE 0000022d
-CSEG PFA_DNEGATE 00000234
-CSEG XT_DINVERT 00003c3a
-CSEG VE_CMOVE 00000239
-CSEG XT_CMOVE 0000023e
-CSEG PFA_CMOVE 0000023f
-CSEG PFA_CMOVE1 0000024c
-CSEG PFA_CMOVE2 00000248
-CSEG VE_2SWAP 00000252
-CSEG XT_2SWAP 00000257
-CSEG PFA_2SWAP 00000258
-CSEG VE_REFILLTIB 0000025d
-CSEG XT_REFILLTIB 00000264
-CSEG PFA_REFILLTIB 00000265
-CSEG XT_TIB 00000280
-CSEG XT_ACCEPT 00000498
-CSEG XT_NUMBERTIB 00000286
-CSEG XT_TO_IN 00003ee1
-CSEG VE_SOURCETIB 00000270
-CSEG XT_SOURCETIB 00000277
-CSEG PFA_SOURCETIB 00000278
-CSEG VE_TIB 0000027c
-CSEG PFA_DOVARIABLE 00003847
-CSEG PFA_TIB 00000281
-DSEG ram_tib 0000012c
-CSEG VE_NUMBERTIB 00000282
-CSEG PFA_NUMBERTIB 00000287
-DSEG ram_sharptib 00000186
-CSEG VE_EE2RAM 00000288
-CSEG XT_EE2RAM 0000028d
-CSEG PFA_EE2RAM 0000028e
-CSEG PFA_EE2RAM_1 00000290
-CSEG XT_FETCHE 00003b5e
-CSEG XT_DOLOOP 00003ac8
-CSEG PFA_EE2RAM_2 0000029a
-CSEG VE_INIT_RAM 0000029c
-CSEG XT_INIT_RAM 000002a2
-CSEG PFA_INI_RAM 000002a3
-ESEG EE_INITUSER 0000006a
-CSEG XT_UP_FETCH 00003b01
-CSEG XT_2SLASH 00003a03
-CSEG VE_ENVIRONMENT 000002ab
-CSEG XT_ENVIRONMENT 000002b3
-CSEG PFA_ENVIRONMENT 000002b4
-ESEG CFG_ENVIRONMENT 00000044
-CSEG VE_ENVWORDLISTS 000002b5
-CSEG XT_ENVWORDLISTS 000002bc
-CSEG PFA_ENVWORDLISTS 000002bd
-CSEG VE_ENVSLASHPAD 000002c0
-CSEG XT_ENVSLASHPAD 000002c4
-CSEG PFA_ENVSLASHPAD 000002c5
-CSEG XT_PAD 00003ee7
-CSEG VE_ENVSLASHHOLD 000002c9
-CSEG XT_ENVSLASHHOLD 000002ce
-CSEG PFA_ENVSLASHHOLD 000002cf
-CSEG VE_ENV_FORTHNAME 000002d3
-CSEG PFA_EN_FORTHNAME 000002db
-CSEG XT_DOSLITERAL 000003d0
-CSEG VE_ENV_FORTHVERSION 000002e2
-CSEG PFA_EN_FORTHVERSION 000002e9
-CSEG VE_ENV_CPU 000002ec
-CSEG PFA_EN_CPU 000002f1
-CSEG XT_ICOUNT 0000042f
-CSEG VE_ENV_MCUINFO 000002f5
-CSEG XT_ENV_MCUINFO 000002fb
-CSEG PFA_EN_MCUINFO 000002fc
-CSEG VE_ENVUSERSIZE 000002ff
-CSEG XT_ENVUSERSIZE 00000304
-CSEG PFA_ENVUSERSIZE 00000305
-CSEG VE_HLD 00000308
-CSEG XT_HLD 0000030c
-CSEG PFA_HLD 0000030d
-DSEG ram_hld 00000188
-CSEG VE_HOLD 0000030e
-CSEG PFA_HOLD 00000313
-CSEG XT_1MINUS 00003a34
-CSEG VE_L_SHARP 0000031e
-CSEG PFA_L_SHARP 00000322
-CSEG VE_SHARP 00000326
-CSEG PFA_SHARP 0000032a
-CSEG XT_UDSLASHMOD 000003a6
-CSEG XT_LESS 0000396d
-CSEG PFA_SHARP1 00000337
-CSEG VE_SHARP_S 0000033c
-CSEG PFA_SHARP_S 00000340
-CSEG NUMS1 00000340
-CSEG XT_OR 00003a1b
-CSEG VE_SHARP_G 00000347
-CSEG PFA_SHARP_G 0000034b
-CSEG VE_SIGN 00000352
-CSEG XT_SIGN 00000356
-CSEG PFA_SIGN 00000357
-CSEG PFA_SIGN1 0000035d
-CSEG VE_DDOTR 0000035e
-CSEG XT_DDOTR 00000362
-CSEG PFA_DDOTR 00000363
-CSEG XT_TUCK 00003ed9
-CSEG XT_SPACES 00003fb6
-CSEG VE_DOTR 00000371
-CSEG XT_DOTR 00000374
-CSEG PFA_DOTR 00000375
-CSEG VE_DDOT 0000037a
-CSEG XT_DDOT 0000037d
-CSEG PFA_DDOT 0000037e
-CSEG VE_DOT 00000382
-CSEG XT_DOT 00000385
-CSEG PFA_DOT 00000386
-CSEG VE_UDDOT 00000389
-CSEG XT_UDDOT 0000038d
-CSEG PFA_UDDOT 0000038e
-CSEG XT_UDDOTR 00000396
-CSEG VE_UDDOTR 00000392
-CSEG PFA_UDDOTR 00000397
-CSEG VE_UDSLASHMOD 000003a1
-CSEG PFA_UDSLASHMOD 000003a7
-CSEG XT_R_FETCH 00003907
-CSEG XT_UMSLASHMOD 000039c1
-CSEG VE_DIGITQ 000003b1
-CSEG XT_DIGITQ 000003b6
-CSEG PFA_DIGITQ 000003b7
-CSEG XT_TOUPPER 00003f65
-CSEG XT_GREATER 00003977
-CSEG PFA_DOSLITERAL 000003d1
-CSEG VE_SCOMMA 000003db
-CSEG XT_SCOMMA 000003de
-CSEG PFA_SCOMMA 000003df
-CSEG XT_DOSCOMMA 000003e2
-CSEG PFA_DOSCOMMA 000003e3
-CSEG XT_2STAR 00003a0a
-CSEG PFA_SCOMMA2 000003f5
-CSEG PFA_SCOMMA1 000003ef
-CSEG XT_GREATERZERO 00003927
-CSEG PFA_SCOMMA3 000003fc
-CSEG VE_ITYPE 000003fe
-CSEG PFA_ITYPE 00000404
-CSEG PFA_ITYPE2 00000417
-CSEG PFA_ITYPE1 0000040f
-CSEG XT_LOWEMIT 00000424
-CSEG XT_HIEMIT 00000420
-CSEG PFA_ITYPE3 0000041e
-CSEG PFA_HIEMIT 00000421
-CSEG PFA_LOWEMIT 00000425
-CSEG XT_EMIT 00003ef1
-CSEG VE_ICOUNT 0000042a
-CSEG PFA_ICOUNT 00000430
-CSEG VE_TYPE 00000435
-CSEG PFA_TYPE 0000043a
-CSEG XT_BOUNDS 00003f98
-CSEG PFA_TYPE2 00000444
-CSEG PFA_TYPE1 0000043f
-CSEG XT_I 00003aab
-CSEG VE_TICK 00000445
-CSEG PFA_TICK 00000449
-CSEG XT_PARSENAME 000005bb
-CSEG XT_FORTHRECOGNIZER 000005fe
-CSEG XT_RECOGNIZE 00000609
-CSEG XT_DT_NULL 00000696
-CSEG PFA_TICK1 0000045a
-CSEG XT_THROW 00003d85
-CSEG VE_CSKIP 0000045c
-CSEG XT_CSKIP 00000461
-CSEG PFA_CSKIP 00000462
-CSEG PFA_CSKIP1 00000463
-CSEG PFA_CSKIP2 00000470
-CSEG XT_SLASHSTRING 000005ac
-CSEG XT_DOBRANCH 0000382e
-CSEG VE_CSCAN 00000473
-CSEG XT_CSCAN 00000478
-CSEG PFA_CSCAN 00000479
-CSEG PFA_CSCAN1 0000047b
-CSEG PFA_CSCAN2 0000048d
-CSEG XT_NIP 000038ef
-CSEG VE_ACCEPT 00000493
-CSEG PFA_ACCEPT 00000499
-CSEG ACC1 0000049d
-CSEG XT_KEY 00003f02
-CSEG XT_CRLFQ 000004d9
-CSEG ACC5 000004cb
-CSEG ACC3 000004bb
-CSEG ACC6 000004b9
-CSEG XT_BS 000004d1
-CSEG ACC4 000004c9
-CSEG XT_BL 00003f53
-CSEG PFA_ACCEPT6 000004c2
-CSEG XT_CR 00003fa0
-CSEG VE_REFILL 000004e4
-CSEG XT_REFILL 000004e9
-CSEG PFA_DODEFER1 00003dfe
-CSEG PFA_REFILL 000004ea
-CSEG XT_UDEFERFETCH 00003dc7
-CSEG XT_UDEFERSTORE 00003dd3
-CSEG VE_CHAR 000004ed
-CSEG XT_CHAR 000004f1
-CSEG PFA_CHAR 000004f2
-CSEG VE_NUMBER 000004f6
-CSEG XT_NUMBER 000004fb
-CSEG PFA_NUMBER 000004fc
-CSEG XT_QSIGN 0000053f
-CSEG XT_SET_BASE 00000552
-CSEG PFA_NUMBER0 00000512
-CSEG XT_2TO_R 00003b1d
-CSEG XT_2R_FROM 00003b2c
-CSEG XT_TO_NUMBER 00000570
-CSEG XT_QDUP 000038b8
-CSEG PFA_NUMBER1 00000534
-CSEG PFA_NUMBER2 0000052b
-CSEG PFA_NUMBER6 0000052c
-CSEG PFA_NUMBER3 00000528
-CSEG XT_TWO 00003fea
-CSEG PFA_NUMBER5 0000053a
-CSEG PFA_NUMBER4 00000539
-CSEG XT_NEGATE 00003e26
-CSEG PFA_QSIGN 00000540
-CSEG PFA_NUMBERSIGN_DONE 0000054b
-CSEG XT_BASES 0000054d
-CSEG PFA_DOCONSTANT 00003851
-CSEG PFA_SET_BASE 00000553
-CSEG XT_WITHIN 00003e56
-CSEG SET_BASE1 00000568
-CSEG SET_BASE2 00000569
-CSEG VE_TO_NUMBER 0000056a
-CSEG TONUM1 00000571
-CSEG TONUM3 00000588
-CSEG TONUM2 0000057c
-CSEG VE_PARSE 00000589
-CSEG XT_PARSE 0000058e
-CSEG PFA_PARSE 0000058f
-CSEG XT_SOURCE 000005a2
-CSEG XT_PLUSSTORE 00003a64
-CSEG VE_SOURCE 0000059d
-CSEG PFA_SOURCE 000005a3
-CSEG VE_SLASHSTRING 000005a6
-CSEG PFA_SLASHSTRING 000005ad
-CSEG VE_PARSENAME 000005b4
-CSEG PFA_PARSENAME 000005bc
-CSEG XT_SKIPSCANCHAR 000005bf
-CSEG PFA_SKIPSCANCHAR 000005c0
-CSEG VE_SP0 000005d1
-CSEG XT_SP0 000005d5
-CSEG PFA_SP0 000005d6
-CSEG VE_SP 000005d9
-CSEG XT_SP 000005dc
-CSEG PFA_DOUSER 00003857
-CSEG PFA_SP 000005dd
-CSEG VE_RP0 000005de
-CSEG XT_RP0 000005e2
-CSEG PFA_RP0 000005e3
-CSEG XT_DORP0 000005e6
-CSEG PFA_DORP0 000005e7
-CSEG VE_DEPTH 000005e8
-CSEG XT_DEPTH 000005ed
-CSEG PFA_DEPTH 000005ee
-CSEG VE_FORTHRECOGNIZER 000005f4
-CSEG PFA_FORTHRECOGNIZER 000005ff
-ESEG CFG_FORTHRECOGNIZER 0000003e
-CSEG VE_RECOGNIZE 00000602
-CSEG PFA_RECOGNIZE 0000060a
-CSEG XT_RECOGNIZE_A 00000614
-CSEG XT_MAPSTACK 000009a7
-CSEG PFA_RECOGNIZE1 00000613
-CSEG PFA_RECOGNIZE_A 00000615
-CSEG PFA_RECOGNIZE_A1 00000625
-CSEG VE_INTERPRET 00000629
-CSEG XT_INTERPRET 00000630
-CSEG PFA_INTERPRET 00000631
-CSEG PFA_INTERPRET2 00000641
-CSEG PFA_INTERPRET1 0000063c
-CSEG XT_QSTACK 00003f8a
-CSEG VE_DT_NUM 00000643
-CSEG XT_DT_NUM 00000648
-CSEG PFA_DT_NUM 00000649
-CSEG XT_LITERAL 0000077d
-CSEG VE_DT_DNUM 0000064c
-CSEG XT_DT_DNUM 00000652
-CSEG PFA_DT_DNUM 00000653
-CSEG XT_2LITERAL 00003fd6
-CSEG VE_REC_NUM 00000656
-CSEG XT_REC_NUM 0000065c
-CSEG PFA_REC_NUM 0000065d
-CSEG PFA_REC_NONUMBER 00000668
-CSEG PFA_REC_INTNUM2 00000666
-CSEG VE_REC_FIND 0000066a
-CSEG XT_REC_FIND 00000670
-CSEG PFA_REC_FIND 00000671
-CSEG XT_FINDXT 0000070b
-CSEG PFA_REC_WORD_FOUND 00000679
-CSEG XT_DT_XT 00000680
-CSEG VE_DT_XT 0000067b
-CSEG PFA_DT_XT 00000681
-CSEG XT_R_WORD_INTERPRET 00000684
-CSEG XT_R_WORD_COMPILE 00000688
-CSEG PFA_R_WORD_INTERPRET 00000685
-CSEG PFA_R_WORD_COMPILE 00000689
-CSEG PFA_R_WORD_COMPILE1 0000068e
-CSEG VE_DT_NULL 00000690
-CSEG PFA_DT_NULL 00000697
-CSEG XT_FAIL 0000069a
-CSEG PFA_FAIL 0000069b
-CSEG VE_SEARCH_WORDLIST 0000069e
-CSEG XT_SEARCH_WORDLIST 000006a8
-CSEG PFA_SEARCH_WORDLIST 000006a9
-CSEG XT_ISWORD 000006bd
-CSEG XT_TRAVERSEWORDLIST 000006da
-CSEG PFA_SEARCH_WORDLIST1 000006b7
-CSEG XT_NFA2CFA 00000701
-CSEG PFA_ISWORD 000006be
-CSEG XT_NAME2STRING 000006f5
-CSEG PFA_ISWORD3 000006cb
-CSEG VE_TRAVERSEWORDLIST 000006cf
-CSEG PFA_TRAVERSEWORDLIST 000006db
-CSEG PFA_TRAVERSEWORDLIST1 000006dc
-CSEG PFA_TRAVERSEWORDLIST2 000006eb
-CSEG XT_NFA2LFA 00000a16
-CSEG VE_NAME2STRING 000006ed
-CSEG PFA_NAME2STRING 000006f6
-CSEG VE_NFA2CFA 000006fb
-CSEG PFA_NFA2CFA 00000702
-CSEG VE_FINDXT 00000705
-CSEG PFA_FINDXT 0000070c
-CSEG XT_FINDXTA 00000717
-ESEG CFG_ORDERLISTLEN 0000004a
-CSEG PFA_FINDXT1 00000716
-CSEG PFA_FINDXTA 00000718
-CSEG PFA_FINDXTA1 00000724
-CSEG VE_NEWEST 00000725
-CSEG XT_NEWEST 0000072a
-CSEG PFA_NEWEST 0000072b
-DSEG ram_newest 0000018a
-CSEG VE_LATEST 0000072c
-CSEG XT_LATEST 00000731
-CSEG PFA_LATEST 00000732
-DSEG ram_latest 0000018e
-CSEG VE_DOCREATE 00000733
-CSEG XT_DOCREATE 00000739
-CSEG PFA_DOCREATE 0000073a
-CSEG XT_WLSCOPE 00000890
-CSEG XT_HEADER 00000875
-CSEG VE_BACKSLASH 00000744
-CSEG XT_BACKSLASH 00000747
-CSEG PFA_BACKSLASH 00000748
-CSEG VE_LPAREN 0000074d
-CSEG XT_LPAREN 00000750
-CSEG PFA_LPAREN 00000751
-CSEG VE_COMPILE 00000756
-CSEG PFA_COMPILE 0000075d
-CSEG VE_COMMA 00000764
-CSEG PFA_COMMA 00000768
-CSEG XT_DP 00003f11
-CSEG XT_STOREI 00003b72
-CSEG PFA_DP 00003f12
-CSEG VE_BRACKETTICK 0000076f
-CSEG XT_BRACKETTICK 00000773
-CSEG PFA_BRACKETTICK 00000774
-CSEG VE_LITERAL 00000777
-CSEG PFA_LITERAL 0000077e
-CSEG VE_SLITERAL 00000782
-CSEG XT_SLITERAL 00000788
-CSEG PFA_SLITERAL 00000789
-CSEG XT_GMARK 0000078d
-CSEG PFA_GMARK 0000078e
-CSEG XT_GRESOLVE 00000792
-CSEG PFA_GRESOLVE 00000793
-CSEG XT_LMARK 00000798
-CSEG PFA_LMARK 00000799
-CSEG XT_LRESOLVE 0000079b
-CSEG PFA_LRESOLVE 0000079c
-CSEG VE_AHEAD 0000079f
-CSEG XT_AHEAD 000007a4
-CSEG PFA_AHEAD 000007a5
-CSEG VE_IF 000007a9
-CSEG XT_IF 000007ac
-CSEG PFA_IF 000007ad
-CSEG VE_ELSE 000007b1
-CSEG XT_ELSE 000007b5
-CSEG PFA_ELSE 000007b6
-CSEG VE_THEN 000007bc
-CSEG XT_THEN 000007c0
-CSEG PFA_THEN 000007c1
-CSEG VE_BEGIN 000007c3
-CSEG XT_BEGIN 000007c8
-CSEG PFA_BEGIN 000007c9
-CSEG VE_WHILE 000007cb
-CSEG XT_WHILE 000007d0
-CSEG PFA_WHILE 000007d1
-CSEG VE_REPEAT 000007d4
-CSEG XT_REPEAT 000007d9
-CSEG PFA_REPEAT 000007da
-CSEG XT_AGAIN 000007ed
-CSEG VE_UNTIL 000007dd
-CSEG XT_UNTIL 000007e2
-CSEG PFA_UNTIL 000007e3
-CSEG VE_AGAIN 000007e8
-CSEG PFA_AGAIN 000007ee
-CSEG VE_DO 000007f2
-CSEG XT_DO 000007f5
-CSEG PFA_DO 000007f6
-CSEG XT_TO_L 00000850
-CSEG VE_LOOP 000007fc
-CSEG XT_LOOP 00000800
-CSEG PFA_LOOP 00000801
-CSEG XT_ENDLOOP 00000837
-CSEG VE_PLUSLOOP 00000805
-CSEG XT_PLUSLOOP 0000080a
-CSEG PFA_PLUSLOOP 0000080b
-CSEG VE_LEAVE 0000080f
-CSEG XT_LEAVE 00000814
-CSEG PFA_LEAVE 00000815
-CSEG VE_QDO 0000081a
-CSEG XT_QDO 0000081e
-CSEG PFA_QDO 0000081f
-CSEG PFA_QDOCHECK 00000827
-CSEG PFA_QDOCHECK1 0000082e
-CSEG XT_INVERT 000039fc
-CSEG VE_ENDLOOP 00000831
-CSEG PFA_ENDLOOP 00000838
-CSEG LOOP1 00000839
-CSEG XT_L_FROM 00000844
-CSEG LOOP2 00000840
-CSEG VE_L_FROM 00000841
-CSEG PFA_L_FROM 00000845
-CSEG XT_LP 00000863
-CSEG VE_TO_L 0000084d
-CSEG PFA_TO_L 00000851
-CSEG VE_LP0 00000858
-CSEG XT_LP0 0000085c
-CSEG PFA_LP0 0000085d
-ESEG CFG_LP0 00000040
-CSEG VE_LP 00000860
-CSEG PFA_LP 00000864
-DSEG ram_lp 00000190
-CSEG VE_CREATE 00000865
-CSEG XT_CREATE 0000086a
-CSEG PFA_CREATE 0000086b
-CSEG XT_REVEAL 00000899
-CSEG VE_HEADER 00000870
-CSEG PFA_HEADER 00000876
-CSEG PFA_HEADER1 00000887
-CSEG VE_WLSCOPE 0000088a
-CSEG PFA_WLSCOPE 00000891
-ESEG CFG_WLSCOPE 0000003c
-CSEG VE_REVEAL 00000894
-CSEG PFA_REVEAL 0000089a
-CSEG REVEAL1 000008a4
-CSEG XT_STOREE 00003b3a
-CSEG VE_DOES 000008a5
-CSEG XT_DOES 000008aa
-CSEG PFA_DOES 000008ab
-CSEG XT_DODOES 000008bd
-CSEG DO_DODOES 000008b2
-CSEG PFA_DODOES 000008be
-CSEG VE_COLON 000008c6
-CSEG XT_COLON 000008c9
-CSEG PFA_COLON 000008ca
-CSEG XT_COLONNONAME 000008d4
-CSEG VE_COLONNONAME 000008ce
-CSEG PFA_COLONNONAME 000008d5
-CSEG XT_RBRACKET 000008e9
-CSEG VE_SEMICOLON 000008dd
-CSEG XT_SEMICOLON 000008e0
-CSEG PFA_SEMICOLON 000008e1
-CSEG XT_LBRACKET 000008f1
-CSEG VE_RBRACKET 000008e6
-CSEG PFA_RBRACKET 000008ea
-CSEG VE_LBRACKET 000008ee
-CSEG PFA_LBRACKET 000008f2
-CSEG VE_VARIABLE 000008f6
-CSEG XT_VARIABLE 000008fc
-CSEG PFA_VARIABLE 000008fd
-CSEG XT_CONSTANT 00000908
-CSEG XT_ALLOT 00003f2b
-CSEG VE_CONSTANT 00000902
-CSEG PFA_CONSTANT 00000909
-CSEG VE_USER 0000090f
-CSEG XT_USER 00000913
-CSEG PFA_USER 00000914
-CSEG VE_RECURSE 0000091a
-CSEG XT_RECURSE 00000920
-CSEG PFA_RECURSE 00000921
-CSEG VE_IMMEDIATE 00000925
-CSEG XT_IMMEDIATE 0000092c
-CSEG PFA_IMMEDIATE 0000092d
-CSEG XT_GET_CURRENT 000009ce
-CSEG VE_BRACKETCHAR 00000937
-CSEG XT_BRACKETCHAR 0000093c
-CSEG PFA_BRACKETCHAR 0000093d
-CSEG VE_ABORTQUOTE 00000942
-CSEG XT_ABORTQUOTE 00000947
-CSEG PFA_ABORTQUOTE 00000948
-CSEG XT_SQUOTE 00003e89
-CSEG XT_QABORT 00000959
-CSEG VE_ABORT 0000094c
-CSEG XT_ABORT 00000951
-CSEG PFA_ABORT 00000952
-CSEG VE_QABORT 00000954
-CSEG PFA_QABORT 0000095a
-CSEG QABO1 0000095f
-CSEG VE_GET_STACK 00000961
-CSEG XT_GET_STACK 00000968
-CSEG PFA_N_FETCH_E2 0000097f
-CSEG PFA_N_FETCH_E1 00000975
-CSEG XT_CELLS 00003ec3
-CSEG VE_SET_STACK 00000982
-CSEG XT_SET_STACK 00000989
-CSEG PFA_SET_STACK 0000098a
-CSEG PFA_SET_STACK0 00000991
-CSEG PFA_SET_STACK2 0000099e
-CSEG PFA_SET_STACK1 00000999
-CSEG VE_MAPSTACK 000009a0
-CSEG PFA_MAPSTACK 000009a8
-CSEG PFA_MAPSTACK3 000009c3
-CSEG PFA_MAPSTACK1 000009b2
-CSEG PFA_MAPSTACK2 000009bf
-CSEG VE_GET_CURRENT 000009c6
-CSEG PFA_GET_CURRENT 000009cf
-ESEG CFG_CURRENT 00000046
-CSEG VE_GET_ORDER 000009d3
-CSEG XT_GET_ORDER 000009da
-CSEG PFA_GET_ORDER 000009db
-CSEG VE_CFG_ORDER 000009df
-CSEG XT_CFG_ORDER 000009e6
-CSEG PFA_CFG_ORDER 000009e7
-CSEG VE_COMPARE 000009e8
-CSEG XT_COMPARE 000009ee
-CSEG PFA_COMPARE 000009ef
-CSEG PFA_COMPARE_LOOP 000009fb
-CSEG PFA_COMPARE_NOTEQUAL 00000a09
-CSEG PFA_COMPARE_ENDREACHED2 00000a04
-CSEG PFA_COMPARE_ENDREACHED 00000a05
-CSEG PFA_COMPARE_CHECKLASTCHAR 00000a09
-CSEG PFA_COMPARE_DONE 00000a0b
-CSEG VE_NFA2LFA 00000a10
-CSEG PFA_NFA2LFA 00000a17
-CSEG VE_SET_CURRENT 00000a1c
-CSEG XT_SET_CURRENT 00000a24
-CSEG PFA_SET_CURRENT 00000a25
-CSEG VE_WORDLIST 00000a29
-CSEG XT_WORDLIST 00000a2f
-CSEG PFA_WORDLIST 00000a30
-CSEG XT_EHERE 00003f1a
-CSEG PFA_EHERE 00003f1b
-CSEG VE_FORTHWORDLIST 00000a39
-CSEG XT_FORTHWORDLIST 00000a42
-CSEG PFA_FORTHWORDLIST 00000a43
-ESEG CFG_FORTHWORDLIST 00000048
-CSEG VE_SET_ORDER 00000a44
-CSEG XT_SET_ORDER 00000a4b
-CSEG PFA_SET_ORDER 00000a4c
-CSEG VE_SET_RECOGNIZERS 00000a50
-CSEG XT_SET_RECOGNIZERS 00000a5a
-CSEG PFA_SET_RECOGNIZERS 00000a5b
-ESEG CFG_RECOGNIZERLISTLEN 0000005c
-CSEG VE_GET_RECOGNIZERS 00000a5f
-CSEG XT_GET_RECOGNIZERS 00000a69
-CSEG PFA_GET_RECOGNIZERS 00000a6a
-CSEG VE_CODE 00000a6e
-CSEG XT_CODE 00000a72
-CSEG PFA_CODE 00000a73
-CSEG VE_ENDCODE 00000a79
-CSEG XT_ENDCODE 00000a7f
-CSEG PFA_ENDCODE 00000a80
-CSEG VE_MARKER 00000a85
-CSEG XT_MARKER 00000a8b
-CSEG PFA_MARKER 00000a8c
-ESEG EE_MARKER 00000068
-CSEG VE_POSTPONE 00000a8f
-CSEG XT_POSTPONE 00000a95
-CSEG PFA_POSTPONE 00000a96
-CSEG VE_APPLTURNKEY 00000aa4
-CSEG XT_APPLTURNKEY 00000aac
-CSEG PFA_APPLTURNKEY 00000aad
-CSEG XT_INTON 00003c96
-SET DPSTART 00000aba
-CSEG DO_INTERRUPT 00003813
-CSEG DO_EXECUTE 0000380c
-CSEG XT_ISREXEC 00003cbf
-CSEG VE_EXIT 0000381b
-CSEG PFA_EXIT 00003820
-CSEG VE_EXECUTE 00003823
-CSEG PFA_EXECUTE 0000382a
-CSEG PFA_DOBRANCH 0000382f
-CSEG PFA_DOCONDBRANCH 00003836
-CSEG PFA_DOLITERAL 0000383d
-CSEG XT_DOVARIABLE 00003846
-CSEG XT_DOCONSTANT 00003850
-CSEG XT_DOUSER 00003856
-CSEG VE_DOVALUE 00003862
-CSEG XT_DOVALUE 00003868
-CSEG PFA_DOVALUE 00003869
-CSEG VE_FETCH 00003875
-CSEG PFA_FETCH 00003879
-CSEG PFA_FETCHRAM 00003879
-CSEG VE_STORE 0000387d
-CSEG PFA_STORE 00003881
-CSEG PFA_STORERAM 00003881
-CSEG VE_CSTORE 00003889
-CSEG PFA_CSTORE 0000388d
-CSEG VE_CFETCH 00003894
-CSEG PFA_CFETCH 00003898
-CSEG VE_FETCHU 0000389c
-CSEG XT_FETCHU 0000389f
-CSEG PFA_FETCHU 000038a0
-CSEG VE_STOREU 000038a4
-CSEG XT_STOREU 000038a7
-CSEG PFA_STOREU 000038a8
-CSEG VE_DUP 000038ac
-CSEG PFA_DUP 000038b1
-CSEG VE_QDUP 000038b4
-CSEG PFA_QDUP 000038b9
-CSEG PFA_QDUP1 000038be
-CSEG VE_SWAP 000038bf
-CSEG PFA_SWAP 000038c4
-CSEG VE_OVER 000038ca
-CSEG PFA_OVER 000038cf
-CSEG VE_DROP 000038d4
-CSEG PFA_DROP 000038d9
-CSEG VE_ROT 000038dc
-CSEG PFA_ROT 000038e1
-CSEG VE_NIP 000038eb
-CSEG PFA_NIP 000038f0
-CSEG VE_R_FROM 000038f2
-CSEG PFA_R_FROM 000038f6
-CSEG VE_TO_R 000038fb
-CSEG PFA_TO_R 000038ff
-CSEG VE_R_FETCH 00003904
-CSEG PFA_R_FETCH 00003908
-CSEG VE_NOTEQUAL 0000390f
-CSEG PFA_NOTEQUAL 00003913
-CSEG VE_ZEROEQUAL 00003916
-CSEG PFA_ZEROEQUAL 0000391a
-CSEG PFA_ZERO1 00003956
-CSEG PFA_TRUE1 0000394d
-CSEG VE_ZEROLESS 0000391d
-CSEG PFA_ZEROLESS 00003921
-CSEG VE_GREATERZERO 00003924
-CSEG PFA_GREATERZERO 00003928
-CSEG VE_DGREATERZERO 0000392d
-CSEG XT_DGREATERZERO 00003931
-CSEG PFA_DGREATERZERO 00003932
-CSEG VE_DXT_ZEROLESS 0000393b
-CSEG XT_DXT_ZEROLESS 0000393f
-CSEG PFA_DXT_ZEROLESS 00003940
-CSEG VE_TRUE 00003946
-CSEG PFA_TRUE 0000394b
-CSEG VE_ZERO 00003950
-CSEG PFA_ZERO 00003954
-CSEG VE_ULESS 00003958
-CSEG PFA_ULESS 0000395c
-CSEG VE_UGREATER 00003963
-CSEG PFA_UGREATER 00003967
-CSEG VE_LESS 0000396a
-CSEG PFA_LESS 0000396e
-CSEG PFA_LESSDONE 00003972
-CSEG VE_GREATER 00003974
-CSEG PFA_GREATER 00003978
-CSEG PFA_GREATERDONE 0000397c
-CSEG VE_LOG2 0000397f
-CSEG XT_LOG2 00003983
-CSEG PFA_LOG2 00003984
-CSEG PFA_LOG2_1 00003987
-CSEG PFA_LOG2_2 0000398d
-CSEG VE_MINUS 0000398f
-CSEG PFA_MINUS 00003993
-CSEG VE_PLUS 00003999
-CSEG PFA_PLUS 0000399d
-CSEG VE_MSTAR 000039a2
-CSEG PFA_MSTAR 000039a6
-CSEG VE_UMSLASHMOD 000039bc
-CSEG PFA_UMSLASHMOD 000039c2
-CSEG PFA_UMSLASHMODmod 000039c7
-CSEG PFA_UMSLASHMODmod_loop 000039c8
-CSEG PFA_UMSLASHMODmod_loop_control 000039d5
-CSEG PFA_UMSLASHMODmod_subtract 000039d2
-CSEG PFA_UMSLASHMODmod_done 000039d7
-CSEG VE_UMSTAR 000039db
-CSEG PFA_UMSTAR 000039e0
-CSEG VE_INVERT 000039f7
-CSEG PFA_INVERT 000039fd
-CSEG VE_2SLASH 00003a00
-CSEG PFA_2SLASH 00003a04
-CSEG VE_2STAR 00003a07
-CSEG PFA_2STAR 00003a0b
-CSEG VE_AND 00003a0e
-CSEG PFA_AND 00003a13
-CSEG VE_OR 00003a18
-CSEG PFA_OR 00003a1c
-CSEG VE_XOR 00003a21
-CSEG XT_XOR 00003a25
-CSEG PFA_XOR 00003a26
-CSEG VE_1PLUS 00003a2b
-CSEG PFA_1PLUS 00003a2f
-CSEG VE_1MINUS 00003a31
-CSEG PFA_1MINUS 00003a35
-CSEG VE_QNEGATE 00003a37
-CSEG XT_QNEGATE 00003a3d
-CSEG PFA_QNEGATE 00003a3e
-CSEG QNEG1 00003a42
-CSEG VE_LSHIFT 00003a43
-CSEG XT_LSHIFT 00003a48
-CSEG PFA_LSHIFT 00003a49
-CSEG PFA_LSHIFT1 00003a4c
-CSEG PFA_LSHIFT2 00003a51
-CSEG VE_RSHIFT 00003a52
-CSEG XT_RSHIFT 00003a57
-CSEG PFA_RSHIFT 00003a58
-CSEG PFA_RSHIFT1 00003a5b
-CSEG PFA_RSHIFT2 00003a60
-CSEG VE_PLUSSTORE 00003a61
-CSEG PFA_PLUSSTORE 00003a65
-CSEG VE_RP_FETCH 00003a71
-CSEG PFA_RP_FETCH 00003a76
-CSEG VE_RP_STORE 00003a7b
-CSEG XT_RP_STORE 00003a7f
-CSEG PFA_RP_STORE 00003a80
-CSEG VE_SP_FETCH 00003a88
-CSEG PFA_SP_FETCH 00003a8d
-CSEG VE_SP_STORE 00003a91
-CSEG XT_SP_STORE 00003a95
-CSEG PFA_SP_STORE 00003a96
-CSEG PFA_DODO 00003a9b
-CSEG PFA_DODO1 00003a9d
-CSEG VE_I 00003aa8
-CSEG PFA_I 00003aac
-CSEG PFA_DOPLUSLOOP 00003aba
-CSEG PFA_DOPLUSLOOP_LEAVE 00003ac4
-CSEG PFA_DOPLUSLOOP_NEXT 00003ac1
-CSEG PFA_DOLOOP 00003ac9
-CSEG VE_UNLOOP 00003ace
-CSEG PFA_UNLOOP 00003ad4
-CSEG VE_CMOVE_G 00003ad9
-CSEG XT_CMOVE_G 00003ade
-CSEG PFA_CMOVE_G 00003adf
-CSEG PFA_CMOVE_G1 00003af0
-CSEG PFA_CMOVE_G2 00003aec
-CSEG VE_BYTESWAP 00003af5
-CSEG PFA_BYTESWAP 00003af9
-CSEG VE_UP_FETCH 00003afd
-CSEG PFA_UP_FETCH 00003b02
-CSEG VE_UP_STORE 00003b06
-CSEG XT_UP_STORE 00003b0a
-CSEG PFA_UP_STORE 00003b0b
-CSEG VE_1MS 00003b0f
-CSEG XT_1MS 00003b13
-CSEG PFA_1MS 00003b14
-CSEG VE_2TO_R 00003b19
-CSEG PFA_2TO_R 00003b1e
-CSEG VE_2R_FROM 00003b28
-CSEG PFA_2R_FROM 00003b2d
-CSEG VE_STOREE 00003b37
-CSEG PFA_STOREE 00003b3b
-CSEG PFA_STOREE0 00003b3b
-CSEG PFA_FETCHE2 00003b69
-CSEG PFA_STOREE3 00003b45
-CSEG PFA_STOREE1 00003b50
-CSEG PFA_STOREE4 00003b4c
-CSEG PFA_STOREE2 00003b52
-CSEG VE_FETCHE 00003b5b
-CSEG PFA_FETCHE 00003b5f
-CSEG PFA_FETCHE1 00003b5f
-CSEG VE_STOREI 00003b6f
-CSEG PFA_STOREI 00003b73
-ESEG EE_STOREI 00000066
-CSEG VE_DO_STOREI_NRWW 00003b76
-CSEG XT_DO_STOREI 00003b7d
-CSEG PFA_DO_STOREI_NRWW 00003b7e
-CSEG DO_STOREI_atmega 00003b92
-CSEG pageload 00003ba3
-CSEG DO_STOREI_writepage 00003b9c
-CSEG dospm 00003bbc
-EQU pagemask ffffffc0
-CSEG pageload_loop 00003ba9
-CSEG pageload_newdata 00003bb4
-CSEG pageload_cont 00003bb6
-CSEG pageload_done 00003bbb
-CSEG dospm_wait_ee 00003bbc
-CSEG dospm_wait_spm 00003bbe
-CSEG VE_FETCHI 00003bc7
-CSEG PFA_FETCHI 00003bcb
-CSEG VE_N_TO_R 00003bd1
-CSEG XT_N_TO_R 00003bd5
-CSEG PFA_N_TO_R 00003bd6
-CSEG PFA_N_TO_R1 00003bd8
-CSEG VE_N_R_FROM 00003be3
-CSEG XT_N_R_FROM 00003be7
-CSEG PFA_N_R_FROM 00003be8
-CSEG PFA_N_R_FROM1 00003bed
-CSEG VE_D2STAR 00003bf5
-CSEG XT_D2STAR 00003bf9
-CSEG PFA_D2STAR 00003bfa
-CSEG VE_D2SLASH 00003c03
-CSEG XT_D2SLASH 00003c07
-CSEG PFA_D2SLASH 00003c08
-CSEG VE_DPLUS 00003c11
-CSEG PFA_DPLUS 00003c15
-CSEG VE_DMINUS 00003c22
-CSEG XT_DMINUS 00003c25
-CSEG PFA_DMINUS 00003c26
-CSEG VE_DINVERT 00003c34
-CSEG PFA_DINVERT 00003c3b
-CSEG VE_SLASHMOD 00003c44
-CSEG XT_SLASHMOD 00003c48
-CSEG PFA_SLASHMOD 00003c49
-CSEG PFA_SLASHMOD_1 00003c54
-CSEG PFA_SLASHMOD_2 00003c5a
-CSEG PFA_SLASHMOD_3 00003c5d
-CSEG PFA_SLASHMOD_5 00003c68
-CSEG PFA_SLASHMOD_4 00003c67
-CSEG PFA_SLASHMODmod_done 00003c73
-CSEG PFA_SLASHMOD_6 00003c71
-CSEG VE_ABS 00003c77
-CSEG XT_ABS 00003c7b
-CSEG PFA_ABS 00003c7c
-CSEG VE_PICK 00003c7f
-CSEG XT_PICK 00003c83
-CSEG PFA_PICK 00003c84
-CSEG VE_CELLPLUS 00003c8a
-CSEG PFA_CELLPLUS 00003c90
-CSEG VE_INTON 00003c92
-CSEG PFA_INTON 00003c97
-CSEG VE_INTOFF 00003c99
-CSEG XT_INTOFF 00003c9d
-CSEG PFA_INTOFF 00003c9e
-CSEG VE_INTSTORE 00003ca0
-CSEG PFA_INTSTORE 00003ca5
-CSEG VE_INTFETCH 00003caa
-CSEG XT_INTFETCH 00003cae
-CSEG PFA_INTFETCH 00003caf
-CSEG VE_INTTRAP 00003cb4
-CSEG XT_INTTRAP 00003cba
-CSEG PFA_INTTRAP 00003cbb
-CSEG PFA_ISREXEC 00003cc0
-CSEG XT_ISREND 00003cc4
-CSEG PFA_ISREND 00003cc5
-CSEG PFA_ISREND1 00003cc7
-CSEG XT_DEFAULT_PROMPTOK 00003cc8
-CSEG PFA_DEFAULT_PROMPTOK 00003cc9
-CSEG VE_PROMPTOK 00003ccf
-CSEG XT_PROMPTOK 00003cd3
-CSEG PFA_PROMPTOK 00003cd4
-CSEG XT_DEFAULT_PROMPTREADY 00003cd7
-CSEG PFA_DEFAULT_PROMPTREADY 00003cd8
-CSEG VE_PROMPTREADY 00003cde
-CSEG XT_PROMPTREADY 00003ce3
-CSEG PFA_PROMPTREADY 00003ce4
-CSEG XT_DEFAULT_PROMPTERROR 00003ce7
-CSEG PFA_DEFAULT_PROMPTERROR 00003ce8
-CSEG VE_PROMPTERROR 00003cf9
-CSEG XT_PROMPTERROR 00003cfe
-CSEG PFA_PROMPTERROR 00003cff
-CSEG VE_QUIT 00003d02
-CSEG XT_QUIT 00003d06
-CSEG PFA_QUIT 00003d07
-CSEG PFA_QUIT2 00003d0f
-CSEG PFA_QUIT4 00003d15
-CSEG PFA_QUIT3 00003d27
-CSEG XT_CATCH 00003d6f
-CSEG PFA_QUIT5 00003d25
-CSEG VE_PAUSE 00003d2a
-CSEG PFA_PAUSE 00003d30
-DSEG ram_pause 00000192
-CSEG XT_RDEFERFETCH 00003db3
-CSEG XT_RDEFERSTORE 00003dbd
-CSEG VE_COLD 00003d33
-CSEG clearloop 00003d3f
-DSEG ram_user1 00000194
-CSEG PFA_WARM 00003d59
-CSEG VE_WARM 00003d54
-CSEG XT_WARM 00003d58
-CSEG XT_DEFERSTORE 00003dde
-CSEG XT_TURNKEY 00003f5b
-CSEG VE_HANDLER 00003d62
-CSEG XT_HANDLER 00003d68
-CSEG PFA_HANDLER 00003d69
-CSEG VE_CATCH 00003d6a
-CSEG PFA_CATCH 00003d70
-CSEG VE_THROW 00003d80
-CSEG PFA_THROW 00003d86
-CSEG PFA_THROW1 00003d8c
-CSEG VE_EDEFERFETCH 00003d99
-CSEG PFA_EDEFERFETCH 00003da0
-CSEG VE_EDEFERSTORE 00003da3
-CSEG PFA_EDEFERSTORE 00003daa
-CSEG VE_RDEFERFETCH 00003dad
-CSEG PFA_RDEFERFETCH 00003db4
-CSEG VE_RDEFERSTORE 00003db7
-CSEG PFA_RDEFERSTORE 00003dbe
-CSEG VE_UDEFERFETCH 00003dc1
-CSEG PFA_UDEFERFETCH 00003dc8
-CSEG VE_UDEFERSTORE 00003dcd
-CSEG PFA_UDEFERSTORE 00003dd4
-CSEG VE_DEFERSTORE 00003dd9
-CSEG PFA_DEFERSTORE 00003ddf
-CSEG VE_DEFERFETCH 00003de6
-CSEG XT_DEFERFETCH 00003deb
-CSEG PFA_DEFERFETCH 00003dec
-CSEG VE_DODEFER 00003df2
-CSEG XT_DODEFER 00003df8
-CSEG PFA_DODEFER 00003df9
-CSEG VE_UDOT 00003e06
-CSEG XT_UDOT 00003e09
-CSEG PFA_UDOT 00003e0a
-CSEG VE_UDOTR 00003e0d
-CSEG XT_UDOTR 00003e11
-CSEG PFA_UDOTR 00003e12
-CSEG VE_USLASHMOD 00003e16
-CSEG XT_USLASHMOD 00003e1b
-CSEG PFA_USLASHMOD 00003e1c
-CSEG VE_NEGATE 00003e21
-CSEG PFA_NEGATE 00003e27
-CSEG VE_SLASH 00003e2a
-CSEG XT_SLASH 00003e2d
-CSEG PFA_SLASH 00003e2e
-CSEG VE_MOD 00003e31
-CSEG XT_MOD 00003e35
-CSEG PFA_MOD 00003e36
-CSEG VE_MIN 00003e39
-CSEG XT_MIN 00003e3d
-CSEG PFA_MIN 00003e3e
-CSEG PFA_MIN1 00003e43
-CSEG VE_MAX 00003e45
-CSEG XT_MAX 00003e49
-CSEG PFA_MAX 00003e4a
-CSEG PFA_MAX1 00003e4f
-CSEG VE_WITHIN 00003e51
-CSEG PFA_WITHIN 00003e57
-CSEG VE_SHOWWORDLIST 00003e5e
-CSEG XT_SHOWWORDLIST 00003e67
-CSEG PFA_SHOWWORDLIST 00003e68
-CSEG XT_SHOWWORD 00003e6d
-CSEG PFA_SHOWWORD 00003e6e
-CSEG VE_WORDS 00003e73
-CSEG XT_WORDS 00003e78
-CSEG PFA_WORDS 00003e79
-CSEG VE_DOTSTRING 00003e7e
-CSEG XT_DOTSTRING 00003e81
-CSEG PFA_DOTSTRING 00003e82
-CSEG VE_SQUOTE 00003e86
-CSEG PFA_SQUOTE 00003e8a
-CSEG PFA_SQUOTE1 00003e92
-CSEG VE_FILL 00003e93
-CSEG PFA_FILL 00003e98
-CSEG PFA_FILL2 00003ea4
-CSEG PFA_FILL1 00003e9f
-CSEG VE_F_CPU 00003ea6
-CSEG XT_F_CPU 00003eab
-CSEG PFA_F_CPU 00003eac
-CSEG VE_STATE 00003eb1
-CSEG PFA_STATE 00003eb7
-DSEG ram_state 000001c0
-CSEG VE_BASE 00003eb8
-CSEG PFA_BASE 00003ebd
-CSEG VE_CELLS 00003ebe
-CSEG VE_2DUP 00003ec4
-CSEG PFA_2DUP 00003ec9
-CSEG VE_2DROP 00003ecc
-CSEG PFA_2DROP 00003ed2
-CSEG VE_TUCK 00003ed5
-CSEG PFA_TUCK 00003eda
-CSEG VE_TO_IN 00003edd
-CSEG PFA_TO_IN 00003ee2
-CSEG VE_PAD 00003ee3
-CSEG PFA_PAD 00003ee8
-CSEG VE_EMIT 00003eed
-CSEG PFA_EMIT 00003ef2
-CSEG VE_EMITQ 00003ef5
-CSEG XT_EMITQ 00003efa
-CSEG PFA_EMITQ 00003efb
-CSEG VE_KEY 00003efe
-CSEG PFA_KEY 00003f03
-CSEG VE_KEYQ 00003f06
-CSEG XT_KEYQ 00003f0a
-CSEG PFA_KEYQ 00003f0b
-CSEG VE_DP 00003f0e
-ESEG CFG_DP 00000036
-CSEG VE_EHERE 00003f15
-ESEG EE_EHERE 0000003a
-CSEG VE_HERE 00003f1e
-CSEG PFA_HERE 00003f23
-ESEG EE_HERE 00000038
-CSEG VE_ALLOT 00003f26
-CSEG PFA_ALLOT 00003f2c
-CSEG VE_BIN 00003f31
-CSEG XT_BIN 00003f35
-CSEG PFA_BIN 00003f36
-CSEG VE_DECIMAL 00003f3a
-CSEG PFA_DECIMAL 00003f41
-CSEG VE_HEX 00003f46
-CSEG XT_HEX 00003f4a
-CSEG PFA_HEX 00003f4b
-CSEG VE_BL 00003f50
-CSEG PFA_BL 00003f54
-CSEG VE_TURNKEY 00003f55
-CSEG PFA_TURNKEY 00003f5c
-ESEG CFG_TURNKEY 00000042
-CSEG VE_TOUPPER 00003f5f
-CSEG PFA_TOUPPER 00003f66
-CSEG PFA_TOUPPER0 00003f71
-CSEG VE_TOLOWER 00003f72
-CSEG XT_TOLOWER 00003f78
-CSEG PFA_TOLOWER 00003f79
-CSEG PFA_TOLOWER0 00003f84
-CSEG VE_QSTACK 00003f85
-CSEG PFA_QSTACK 00003f8b
-CSEG PFA_QSTACK1 00003f92
-CSEG VE_BOUNDS 00003f93
-CSEG PFA_BOUNDS 00003f99
-CSEG VE_CR 00003f9d
-CSEG PFA_CR 00003fa1
-CSEG VE_SPACE 00003fa8
-CSEG PFA_SPACE 00003fae
-CSEG VE_SPACES 00003fb1
-CSEG PFA_SPACES 00003fb7
-CSEG SPCS1 00003fb9
-CSEG SPCS2 00003fc0
-CSEG VE_S2D 00003fc2
-CSEG PFA_S2D 00003fc7
-CSEG VE_TO_BODY 00003fca
-CSEG VE_2LITERAL 00003fd0
-CSEG PFA_2LITERAL 00003fd7
-CSEG VE_EQUAL 00003fdb
-CSEG PFA_EQUAL 00003fdf
-CSEG VE_ONE 00003fe2
-CSEG PFA_ONE 00003fe6
-CSEG VE_TWO 00003fe7
-CSEG PFA_TWO 00003feb
-CSEG VE_MINUSONE 00003fec
-CSEG XT_MINUSONE 00003fef
-CSEG PFA_MINUSONE 00003ff0
-SET flashlast 00003ff1
-DSEG HERESTART 000001c2
-ESEG EHERESTART 0000008e
-ESEG CFG_ORDERLIST 0000004c
-ESEG CFG_RECOGNIZERLIST 0000005e
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/arduino/words/applturnkey.asm b/amforth-6.5/appl/arduino/words/applturnkey.asm
deleted file mode 100644
index 89ab5fb..0000000
--- a/amforth-6.5/appl/arduino/words/applturnkey.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- ) System
-; R( -- )
-; application specific turnkey action
-VE_APPLTURNKEY:
- .dw $ff0b
- .db "applturnkey",0
- .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
-XT_APPLTURNKEY:
- .dw DO_COLON
-PFA_APPLTURNKEY:
- .dw XT_USART
-
-.if WANT_INTERRUPTS == 1
- .dw XT_INTON
-.endif
-
- .dw XT_DOT_VER
- .dw XT_SPACE
- .dw XT_DOSLITERAL
- .dw 10
- .db "Forthduino"
- .dw XT_ITYPE
-
- .dw XT_EXIT
diff --git a/amforth-6.5/appl/atmega2561/atmega256.asm b/amforth-6.5/appl/atmega2561/atmega256.asm
deleted file mode 100644
index 30e1300..0000000
--- a/amforth-6.5/appl/atmega2561/atmega256.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; the 256x devices are special since they *require*
-; both a 24bit address space and they need a special
-; flash store placement in the NRWW section, way outside
-; of the standard 16bit jump distance.
-
-; note that dict_appl_core includes a store-i_big.asm
-; instead if the normal store-i.asm file. This file
-; has all the magic needed for the large address space.
-; *everything else* is identical to other controllers.
-
-.include "preamble.inc"
-
-; cpu clock in hertz
-.equ F_CPU = 14745600
-.include "drivers/usart_1.asm"
-
-; all of amforth is in one segment
-.include "amforth-low.asm"
diff --git a/amforth-6.5/appl/atmega2561/atmega256.eep.hex b/amforth-6.5/appl/atmega2561/atmega256.eep.hex
deleted file mode 100644
index 9bebfd9..0000000
--- a/amforth-6.5/appl/atmega2561/atmega256.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10007200FFFF8012E102CC0043049A00B0219804F1
-:0A008200960986007B12010086003B
-:06009A0002008A0F760F40
-:1000A4001508A60000000000FF21AF21AF210000C9
-:1000B4000A00E100EF00B600D1008B1100007811B6
-:0800C400500E6F0E5F0E1700D5
-:00000001FF
diff --git a/amforth-6.5/appl/atmega2561/atmega256.hex b/amforth-6.5/appl/atmega2561/atmega256.hex
deleted file mode 100644
index 1ad9cb0..0000000
--- a/amforth-6.5/appl/atmega2561/atmega256.hex
+++ /dev/null
@@ -1,647 +0,0 @@
-:020000020000FC
-:0200040039D1F0
-:0200080037D1EE
-:02000C0035D1EC
-:0200100033D1EA
-:0200140031D1E8
-:020018002FD1E6
-:02001C002DD1E4
-:020020002BD1E2
-:0200240029D1E0
-:0200280027D1DE
-:02002C0025D1DC
-:0200300023D1DA
-:0200340021D1D8
-:020038001FD1D6
-:02003C001DD1D4
-:020040001BD1D2
-:0200440019D1D0
-:0200480017D1CE
-:02004C0015D1CC
-:0200500013D1CA
-:0200540011D1C8
-:020058000FD1C6
-:02005C000DD1C4
-:020060000BD1C2
-:0200640009D1C0
-:0200680007D1BE
-:02006C0005D1BC
-:0200700003D1BA
-:0200740001D1B8
-:02007800FFD0B7
-:02007C00FDD0B5
-:02008000FBD0B3
-:02008400F9D0B1
-:02008800F7D0AF
-:02008C00F5D0AD
-:02009000F3D0AB
-:02009400F1D0A9
-:02009800EFD0A7
-:02009C00EDD0A5
-:0200A000EBD0A3
-:0200A400E9D0A1
-:0200A800E7D09F
-:0200AC00E5D09D
-:0200B000E3D09B
-:0200B400E1D099
-:0200B800DFD097
-:0200BC00DDD095
-:0200C000DBD093
-:0200C400D9D091
-:0200C800D7D08F
-:0200CC00D5D08D
-:0200D000D3D08B
-:0200D400D1D089
-:0200D800CFD087
-:0200DC00CDD085
-:1000E000CBD000200010FFFF39000A0041546D659D
-:1000F00067613235363107FF3E72782D62756600D2
-:1001000000008200082F10911002E0E0F2E0E10F01
-:10011000F31D008313951F7010931002899199911C
-:100120000C941F0106FF6973722D72787B001B010E
-:10013000CE04CE0031054A05CE0403006D12C7047B
-:10014000A200BF0E8100AE041B01CE049700CE04B6
-:100150004800EB08CE040002CE041600ED0533097A
-:10016000AE0406FF72782D62756692001B01D10005
-:10017000C704B700CE04110231054A05CE040002BF
-:10018000360631055D05C806CE040F00AC06CE0468
-:1001900011022605AE0407FF72783F2D62756600D6
-:1001A000B1001B01B70ECE0411023105CE041002BE
-:1001B0003105AC05AE0407FF74782D706F6C6C00D0
-:1001C000CB001B01EF00C704E200CE04CE002605E1
-:1001D000AE0408FF74783F2D706F6C6CDB001B0160
-:1001E000B70ECE04C8003105CE042000AC06AE0424
-:1001F00004FF75627272E9000905CA001A10241022
-:1002000006FF2B7573617274F8001B01CE04980011
-:10021000CE04C9002605CE040600CE04CA00260579
-:10022000FC004A059207CE04CD002605CE04CC0082
-:060230002605A400AE0447
-:040000000C94C00E8E
-:10023600BF93AF93DB011196B21499F4FD015527D4
-:10024600EE0FFF1F551F5BBF679177911196FB015C
-:100256005527EE0FFF1F551F5BBF07911791F8013A
-:1002660009949A938A938B2D9927BB2466E079E0AB
-:10027600EECF0A920FB60A920F900F900F900A9443
-:10028600B02CFF93EF93E2E1F2E00694E00DF31D4C
-:10029600008003940082EF91FF9109900FBE0990B0
-:1002A600089502FF6D2B00011B0155127908AE045B
-:1002B60003FF75642A0054011B014A059805790657
-:1002C60072055D058F0579067A053606AE0404FFCC
-:1002D600756D61785B011B01CA09F505C7047401D8
-:1002E6005D057205AE0404FF756D696E6A011B013A
-:1002F600CA090006C70480015D057205AE041B012C
-:10030600CE040080AC06B305C7048B017412AE049C
-:10031600E405AE040AFF6E616D653E666C61677347
-:1003260076011B012C08CE0400FFAC06AE0406FFC6
-:100336006E65776573748D01DC044B0206FF6C6194
-:10034600746573749A01DC044F0208FF28637265B2
-:1003560061746529A1011B011A0E05034A059F0157
-:10036600C2091A05EA029F011A05AE0401005C00E3
-:10037600A8011B01010E8905E3091A05AE04010057
-:100386002800B9011B01CE042900ED0DD309AE04E6
-:1003960007FF636F6D70696C6500C2011B018F05F5
-:1003A6004A05111098052C08DC01AE0401FF2C004B
-:1003B600CB011B01130A0D08130AC806FF0F140A06
-:1003C600AE0403005B275D00D9011B01700CF2012E
-:1003D600AE0407006C69746572616C00E4011B0170
-:1003E600D101CE04DC01AE040800736C6974657239
-:1003F600616CEC011B01D101D30BE10BAE041B01B7
-:10040600130AD101FFFFAE041B01BD0F130A5D05E0
-:100416000D08AE041B01130AAE041B01BD0FDC015F
-:10042600AE040500616865616400F7011B01D10136
-:10043600BD040202AE040200696614021B01D1016A
-:10044600C7040202AE040400656C73651E021B013C
-:10045600D101BD0402025D050702AE040400746802
-:10046600656E26021B010702AE0405006265676918
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diff --git a/amforth-6.5/appl/atmega2561/atmega256.lst b/amforth-6.5/appl/atmega2561/atmega256.lst
deleted file mode 100644
index 6c42c66..0000000
--- a/amforth-6.5/appl/atmega2561/atmega256.lst
+++ /dev/null
@@ -1,10182 +0,0 @@
-
-AVRASM ver. 2.1.52 atmega256.asm Sun Apr 30 20:10:15 2017
-
-atmega256.asm(11): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega2561\device.asm'
-../../avr8/devices/atmega2561\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m2561def.inc'
-atmega256.asm(15): Including file '../../avr8\drivers/usart_1.asm'
-../../avr8\drivers/usart_1.asm(31): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-atmega256.asm(18): Including file '../../avr8\amforth-low.asm'
-../../avr8\amforth-low.asm(11): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth-low.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth-low.asm(15): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(9): Including file '../../avr8\dict/appl_8k.inc'
-../../avr8\dict/appl_8k.inc(1): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth-low.asm(16): Including file 'dict_appl.inc'
-dict_appl.inc(4): Including file 'words/applturnkey.asm'
-../../avr8\amforth-low.asm(17): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(95): Including file '../../avr8\words/store-i_big.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(102): Including file '../../avr8\dict/core_8k.inc'
-../../avr8\dict/core_8k.inc(2): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_8k.inc(3): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_8k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_8k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_8k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_8k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_8k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_8k.inc(10): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_8k.inc(11): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_8k.inc(13): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_8k.inc(14): Including file '../../common\words/words.asm'
-../../avr8\dict/core_8k.inc(15): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_8k.inc(17): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_8k.inc(18): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_8k.inc(19): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_8k.inc(21): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_8k.inc(23): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/core_8k.inc(24): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/core_8k.inc(25): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/core_8k.inc(26): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/core_8k.inc(27): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/core_8k.inc(28): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/core_8k.inc(29): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/core_8k.inc(30): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/core_8k.inc(31): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/core_8k.inc(33): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_8k.inc(34): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_8k.inc(35): Including file '../../common\words/base.asm'
-../../avr8\dict/core_8k.inc(37): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_8k.inc(38): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_8k.inc(40): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_8k.inc(41): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_8k.inc(43): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_8k.inc(45): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_8k.inc(46): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_8k.inc(47): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_8k.inc(48): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_8k.inc(49): Including file '../../common\words/key.asm'
-../../avr8\dict/core_8k.inc(50): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_8k.inc(52): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_8k.inc(53): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_8k.inc(54): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_8k.inc(55): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_8k.inc(57): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_8k.inc(58): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_8k.inc(59): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_8k.inc(60): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_8k.inc(62): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_8k.inc(64): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_8k.inc(65): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_8k.inc(66): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_8k.inc(67): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_8k.inc(68): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_8k.inc(69): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_8k.inc(70): Including file '../../common\words/min.asm'
-../../avr8\dict/core_8k.inc(71): Including file '../../common\words/max.asm'
-../../avr8\dict/core_8k.inc(72): Including file '../../common\words/within.asm'
-../../avr8\dict/core_8k.inc(74): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_8k.inc(75): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_8k.inc(77): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/core_8k.inc(78): Including file '../../common\words/hold.asm'
-../../avr8\dict/core_8k.inc(79): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/core_8k.inc(80): Including file '../../common\words/sharp.asm'
-../../avr8\dict/core_8k.inc(81): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/core_8k.inc(82): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/core_8k.inc(83): Including file '../../common\words/sign.asm'
-../../avr8\dict/core_8k.inc(84): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/core_8k.inc(85): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/core_8k.inc(86): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/core_8k.inc(87): Including file '../../common\words/dot.asm'
-../../avr8\dict/core_8k.inc(88): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/core_8k.inc(89): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/core_8k.inc(90): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/core_8k.inc(91): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/core_8k.inc(93): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/core_8k.inc(94): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/core_8k.inc(95): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/core_8k.inc(96): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/core_8k.inc(97): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_8k.inc(98): Including file '../../common\words/space.asm'
-../../avr8\dict/core_8k.inc(99): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_8k.inc(100): Including file '../../common\words/type.asm'
-../../avr8\dict/core_8k.inc(101): Including file '../../common\words/tick.asm'
-../../avr8\dict/core_8k.inc(103): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_8k.inc(104): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_8k.inc(105): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_8k.inc(107): Including file '../../common\words/cskip.asm'
-../../avr8\dict/core_8k.inc(108): Including file '../../common\words/cscan.asm'
-../../avr8\dict/core_8k.inc(109): Including file '../../common\words/accept.asm'
-../../avr8\dict/core_8k.inc(110): Including file '../../common\words/refill.asm'
-../../avr8\dict/core_8k.inc(111): Including file '../../common\words/char.asm'
-../../avr8\dict/core_8k.inc(112): Including file '../../common\words/number.asm'
-../../avr8\dict/core_8k.inc(113): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/core_8k.inc(114): Including file '../../common\words/set-base.asm'
-../../avr8\dict/core_8k.inc(115): Including file '../../common\words/to-number.asm'
-../../avr8\dict/core_8k.inc(116): Including file '../../common\words/parse.asm'
-../../avr8\dict/core_8k.inc(117): Including file '../../common\words/source.asm'
-../../avr8\dict/core_8k.inc(118): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/core_8k.inc(119): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/core_8k.inc(120): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/core_8k.inc(122): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_8k.inc(123): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_8k.inc(124): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_8k.inc(126): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_8k.inc(127): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_8k.inc(128): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_8k.inc(129): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_8k.inc(131): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/core_8k.inc(132): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/core_8k.inc(133): Including file '../../common\words/depth.asm'
-../../avr8\dict/core_8k.inc(134): Including file '../../common\words/interpret.asm'
-../../avr8\dict/core_8k.inc(135): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/core_8k.inc(136): Including file '../../common\words/recognize.asm'
-../../avr8\dict/core_8k.inc(137): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/core_8k.inc(138): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/core_8k.inc(139): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/core_8k.inc(141): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_8k.inc(142): Including file '../../common\words/ver.asm'
-../../avr8\dict/core_8k.inc(144): Including file '../../common\words/noop.asm'
-../../avr8\dict/core_8k.inc(145): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/core_8k.inc(147): Including file '../../common\words/to.asm'
-../../avr8\dict/core_8k.inc(148): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/core_8k.inc(150): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_8k.inc(151): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_8k.inc(152): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_8k.inc(153): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_8k.inc(154): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_8k.inc(155): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_8k.inc(156): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_8k.inc(157): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_8k.inc(158): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_8k.inc(160): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/core_8k.inc(161): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/core_8k.inc(162): Including file '../../common\words/name2string.asm'
-../../avr8\dict/core_8k.inc(163): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/core_8k.inc(164): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/core_8k.inc(166): Including file '../../common\words/star.asm'
-../../avr8\dict/core_8k.inc(167): Including file '../../avr8\words/j.asm'
-../../avr8\dict/core_8k.inc(169): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/core_8k.inc(170): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/core_8k.inc(171): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/core_8k.inc(172): Including file '../../common\words/2swap.asm'
-../../avr8\dict/core_8k.inc(174): Including file '../../common\words/tib.asm'
-../../avr8\dict/core_8k.inc(176): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/core_8k.inc(177): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-../../avr8\dict/core_8k.inc(178): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_8k.inc(179): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_8k.inc(180): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth-low.asm(18): Including file 'dict_appl_core.inc'
-../../avr8\amforth-low.asm(27): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; both a 24bit address space and they need a special
- ; flash store placement in the NRWW section, way outside
- ; of the standard 16bit jump distance.
-
- ; note that dict_appl_core includes a store-i_big.asm
- ; instead if the normal store-i.asm file. This file
- ; has all the magic needed for the large address space.
- ; *everything else* is identical to other controllers.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 512
- .equ CELLSIZE = 2
- .macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
- .endmacro
- .macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- .endmacro
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_USART0 = 0
- .set WANT_TWI = 0
- .set WANT_SPI = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_PORTE = 0
- .set WANT_PORTF = 0
- .set WANT_PORTG = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_WATCHDOG = 0
- .set WANT_USART1 = 0
- .set WANT_EEPROM = 0
- .set WANT_TIMER_COUNTER_5 = 0
- .set WANT_TIMER_COUNTER_4 = 0
- .set WANT_TIMER_COUNTER_3 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_JTAG = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_CPU = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_BOOT_LOAD = 0
- .equ intvecsize = 2 ; please verify; flash size: 262144 bytes
- .equ pclen = 3 ; please verify
- .overlap
- .org 2
-000002 d139 rcall isr ; External Interrupt Request 0
- .org 4
-000004 d137 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d135 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d133 rcall isr ; External Interrupt Request 3
- .org 10
-00000a d131 rcall isr ; External Interrupt Request 4
- .org 12
-00000c d12f rcall isr ; External Interrupt Request 5
- .org 14
-00000e d12d rcall isr ; External Interrupt Request 6
- .org 16
-000010 d12b rcall isr ; External Interrupt Request 7
- .org 18
-000012 d129 rcall isr ; Pin Change Interrupt Request 0
- .org 20
-000014 d127 rcall isr ; Pin Change Interrupt Request 1
- .org 22
-000016 d125 rcall isr ; Pin Change Interrupt Request 2
- .org 24
-000018 d123 rcall isr ; Watchdog Time-out Interrupt
- .org 26
-00001a d121 rcall isr ; Timer/Counter2 Compare Match A
- .org 28
-00001c d11f rcall isr ; Timer/Counter2 Compare Match B
- .org 30
-00001e d11d rcall isr ; Timer/Counter2 Overflow
- .org 32
-000020 d11b rcall isr ; Timer/Counter1 Capture Event
- .org 34
-000022 d119 rcall isr ; Timer/Counter1 Compare Match A
- .org 36
-000024 d117 rcall isr ; Timer/Counter1 Compare Match B
- .org 38
-000026 d115 rcall isr ; Timer/Counter1 Compare Match C
- .org 40
-000028 d113 rcall isr ; Timer/Counter1 Overflow
- .org 42
-00002a d111 rcall isr ; Timer/Counter0 Compare Match A
- .org 44
-00002c d10f rcall isr ; Timer/Counter0 Compare Match B
- .org 46
-00002e d10d rcall isr ; Timer/Counter0 Overflow
- .org 48
-000030 d10b rcall isr ; SPI Serial Transfer Complete
- .org 50
-000032 d109 rcall isr ; USART0, Rx Complete
- .org 52
-000034 d107 rcall isr ; USART0 Data register Empty
- .org 54
-000036 d105 rcall isr ; USART0, Tx Complete
- .org 56
-000038 d103 rcall isr ; Analog Comparator
- .org 58
-00003a d101 rcall isr ; ADC Conversion Complete
- .org 60
-00003c d0ff rcall isr ; EEPROM Ready
- .org 62
-00003e d0fd rcall isr ; Timer/Counter3 Capture Event
- .org 64
-000040 d0fb rcall isr ; Timer/Counter3 Compare Match A
- .org 66
-000042 d0f9 rcall isr ; Timer/Counter3 Compare Match B
- .org 68
-000044 d0f7 rcall isr ; Timer/Counter3 Compare Match C
- .org 70
-000046 d0f5 rcall isr ; Timer/Counter3 Overflow
- .org 72
-000048 d0f3 rcall isr ; USART1, Rx Complete
- .org 74
-00004a d0f1 rcall isr ; USART1 Data register Empty
- .org 76
-00004c d0ef rcall isr ; USART1, Tx Complete
- .org 78
-00004e d0ed rcall isr ; 2-wire Serial Interface
- .org 80
-000050 d0eb rcall isr ; Store Program Memory Read
- .org 82
-000052 d0e9 rcall isr ; Timer/Counter4 Capture Event
- .org 84
-000054 d0e7 rcall isr ; Timer/Counter4 Compare Match A
- .org 86
-000056 d0e5 rcall isr ; Timer/Counter4 Compare Match B
- .org 88
-000058 d0e3 rcall isr ; Timer/Counter4 Compare Match C
- .org 90
-00005a d0e1 rcall isr ; Timer/Counter4 Overflow
- .org 92
-00005c d0df rcall isr ; Timer/Counter5 Capture Event
- .org 94
-00005e d0dd rcall isr ; Timer/Counter5 Compare Match A
- .org 96
-000060 d0db rcall isr ; Timer/Counter5 Compare Match B
- .org 98
-000062 d0d9 rcall isr ; Timer/Counter5 Compare Match C
- .org 100
-000064 d0d7 rcall isr ; Timer/Counter5 Overflow
- .org 102
-000066 d0d5 rcall isr ; USART2, Rx Complete
- .org 104
-000068 d0d3 rcall isr ; USART2 Data register Empty
- .org 106
-00006a d0d1 rcall isr ; USART2, Tx Complete
- .org 108
-00006c d0cf rcall isr ; USART3, Rx Complete
- .org 110
-00006e d0cd rcall isr ; USART3 Data register Empty
- .org 112
-000070 d0cb rcall isr ; USART3, Tx Complete
- .equ INTVECTORS = 57
- .nooverlap
-
- ; compatability layer (maybe empty)
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000071 2000 .dw 8192
- mcu_eepromsize:
-000072 1000 .dw 4096
- mcu_maxdp:
-000073 ffff .dw 65535
- mcu_numints:
-000074 0039 .dw 57
- mcu_name:
-000075 000a .dw 10
-000076 5441
-000077 656d
-000078 6167
-000079 3532
-00007a 3136 .db "ATmega2561"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- ; cpu clock in hertz
- .equ F_CPU = 14745600
- .include "drivers/usart_1.asm"
-
- .equ BAUDRATE_HIGH = UBRR1H
- .equ USART_C = UCSR1C
- .equ USART_B = UCSR1B
- .equ USART_A = UCSR1A
- .equ USART_DATA = UDR1
-
- .equ URXCaddr = URXC1addr
- .equ UDREaddr = UDRE1addr
-
- .equ bm_USART_RXRD = 1 << RXC1
- .equ bm_USART_TXRD = 1 << UDRE1
- .equ bm_ENABLE_TX = 1 << TXEN1
- .equ bm_ENABLE_RX = 1 << RXEN1
- .equ bm_ENABLE_INT_RX = 1<<RXCIE1
- .equ bm_ENABLE_INT_TX = 1<<UDRIE1
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000200 usart_rx_data: .byte usart_rx_size
-000210 usart_rx_in: .byte 1
-000211 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-00007b ff07 .dw $ff07
-00007c 723e
-00007d 2d78
-00007e 7562
-00007f 0066 .db ">rx-buf",0
-000080 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000081 0082 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000082 2f08 mov temp0, tosl
-000083 9110 0210 lds temp1, usart_rx_in
-000085 e0e0 ldi zl, low(usart_rx_data)
-000086 e0f2 ldi zh, high(usart_rx_data)
-000087 0fe1 add zl, temp1
-000088 1df3 adc zh, zeroh
-000089 8300 st Z, temp0
-00008a 9513 inc temp1
-00008b 701f andi temp1,usart_rx_mask
-00008c 9310 0210 sts usart_rx_in, temp1
-00008e 9189
-00008f 9199 loadtos
-000090 940c 011f jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000092 ff06 .dw $ff06
-000093 7369
-000094 2d72
-000095 7872 .db "isr-rx"
-000096 007b .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-000097 011b .dw DO_COLON
- usart_rx_isr:
-000098 04ce .dw XT_DOLITERAL
-000099 00ce .dw usart_data
-00009a 0531 .dw XT_CFETCH
-00009b 054a .dw XT_DUP
-00009c 04ce .dw XT_DOLITERAL
-00009d 0003 .dw 3
-00009e 126d .dw XT_EQUAL
-00009f 04c7 .dw XT_DOCONDBRANCH
-0000a0 00a2 .dw usart_rx_isr1
-0000a1 0ebf .dw XT_COLD
- usart_rx_isr1:
-0000a2 0081 .dw XT_TO_RXBUF
-0000a3 04ae .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-0000a4 011b .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-0000a5 04ce
-0000a6 0097 .dw XT_DOLITERAL, XT_ISR_RX
-0000a7 04ce
-0000a8 0048 .dw XT_DOLITERAL, URXCaddr
-0000a9 08eb .dw XT_INTSTORE
-
-0000aa 04ce .dw XT_DOLITERAL
-0000ab 0200 .dw usart_rx_data
-0000ac 04ce .dw XT_DOLITERAL
-0000ad 0016 .dw usart_rx_size + 6
-0000ae 05ed .dw XT_ZERO
-0000af 0933 .dw XT_FILL
-0000b0 04ae .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-0000b1 ff06 .dw $ff06
-0000b2 7872
-0000b3 622d
-0000b4 6675 .db "rx-buf"
-0000b5 0092 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-0000b6 011b .dw DO_COLON
- PFA_RX_BUFFER:
-0000b7 00d1 .dw XT_RXQ_BUFFER
-0000b8 04c7 .dw XT_DOCONDBRANCH
-0000b9 00b7 .dw PFA_RX_BUFFER
-0000ba 04ce .dw XT_DOLITERAL
-0000bb 0211 .dw usart_rx_out
-0000bc 0531 .dw XT_CFETCH
-0000bd 054a .dw XT_DUP
-0000be 04ce .dw XT_DOLITERAL
-0000bf 0200 .dw usart_rx_data
-0000c0 0636 .dw XT_PLUS
-0000c1 0531 .dw XT_CFETCH
-0000c2 055d .dw XT_SWAP
-0000c3 06c8 .dw XT_1PLUS
-0000c4 04ce .dw XT_DOLITERAL
-0000c5 000f .dw usart_rx_mask
-0000c6 06ac .dw XT_AND
-0000c7 04ce .dw XT_DOLITERAL
-0000c8 0211 .dw usart_rx_out
-0000c9 0526 .dw XT_CSTORE
-0000ca 04ae .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-0000cb ff07 .dw $ff07
-0000cc 7872
-0000cd 2d3f
-0000ce 7562
-0000cf 0066 .db "rx?-buf",0
-0000d0 00b1 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-0000d1 011b .dw DO_COLON
- PFA_RXQ_BUFFER:
-0000d2 0eb7 .dw XT_PAUSE
-0000d3 04ce .dw XT_DOLITERAL
-0000d4 0211 .dw usart_rx_out
-0000d5 0531 .dw XT_CFETCH
-0000d6 04ce .dw XT_DOLITERAL
-0000d7 0210 .dw usart_rx_in
-0000d8 0531 .dw XT_CFETCH
-0000d9 05ac .dw XT_NOTEQUAL
-0000da 04ae .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-0000db ff07 .dw $ff07
-0000dc 7874
-0000dd 702d
-0000de 6c6f
-0000df 006c .db "tx-poll",0
-0000e0 00cb .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000e1 011b .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000e2 00ef .dw XT_TXQ_POLL
-0000e3 04c7 .dw XT_DOCONDBRANCH
-0000e4 00e2 .dw PFA_TX_POLL
- ; send to usart
-0000e5 04ce .dw XT_DOLITERAL
-0000e6 00ce .dw USART_DATA
-0000e7 0526 .dw XT_CSTORE
-0000e8 04ae .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000e9 ff08 .dw $ff08
-0000ea 7874
-0000eb 2d3f
-0000ec 6f70
-0000ed 6c6c .db "tx?-poll"
-0000ee 00db .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000ef 011b .dw DO_COLON
- PFA_TXQ_POLL:
-0000f0 0eb7 .dw XT_PAUSE
-0000f1 04ce .dw XT_DOLITERAL
-0000f2 00c8 .dw USART_A
-0000f3 0531 .dw XT_CFETCH
-0000f4 04ce .dw XT_DOLITERAL
-0000f5 0020 .dw bm_USART_TXRD
-0000f6 06ac .dw XT_AND
-0000f7 04ae .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000f8 ff04 .dw $ff04
-0000f9 6275
-0000fa 7272 .db "ubrr"
-0000fb 00e9 .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000fc 0509 .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000fd 00ca .dw EE_UBRRVAL
-0000fe 101a .dw XT_EDEFERFETCH
-0000ff 1024 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-000100 ff06 .dw $ff06
-000101 752b
-000102 6173
-000103 7472 .db "+usart"
-000104 00f8 .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-000105 011b .dw DO_COLON
- PFA_USART: ; ( -- )
-
-000106 04ce .dw XT_DOLITERAL
-000107 0098 .dw USART_B_VALUE
-000108 04ce .dw XT_DOLITERAL
-000109 00c9 .dw USART_B
-00010a 0526 .dw XT_CSTORE
-
-00010b 04ce .dw XT_DOLITERAL
-00010c 0006 .dw USART_C_VALUE
-00010d 04ce .dw XT_DOLITERAL
-00010e 00ca .dw USART_C | bm_USARTC_en
-00010f 0526 .dw XT_CSTORE
-
-000110 00fc .dw XT_UBRR
-000111 054a .dw XT_DUP
-000112 0792 .dw XT_BYTESWAP
-000113 04ce .dw XT_DOLITERAL
-000114 00cd .dw BAUDRATE_HIGH
-000115 0526 .dw XT_CSTORE
-000116 04ce .dw XT_DOLITERAL
-000117 00cc .dw BAUDRATE_LOW
-000118 0526 .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-000119 00a4 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-00011a 04ae .dw XT_EXIT
-
- ; all of amforth is in one segment
- .include "amforth-low.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set pc_ = pc
-
- .org $0000
-000000 940c 0ec0 jmp_ PFA_COLD
- .org pc_
-
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-00011b 93bf push XH
-00011c 93af push XL ; PUSH IP
-00011d 01db movw XL, wl
-00011e 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-00011f 14b2 cp isrflag, zerol
-000120 f499 brne DO_INTERRUPT
- .endif
-000121 01fd movw zl, XL ; READ IP
-000122 2755
-000123 0fee
-000124 1fff
-000125 1f55
-000126 bf5b
-000127 9167
-000128 9177 readflashcell wl, wh
-000129 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00012a 01fb movw zl, wl
-00012b 2755
-00012c 0fee
-00012d 1fff
-00012e 1f55
-00012f bf5b
-000130 9107
-000131 9117 readflashcell temp0,temp1
-000132 01f8 movw zl, temp0
-000133 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-000134 939a
-000135 938a savetos
-000136 2d8b mov tosl, isrflag
-000137 2799 clr tosh
-000138 24bb clr isrflag
-000139 e066 ldi wl, LOW(XT_ISREXEC)
-00013a e079 ldi wh, HIGH(XT_ISREXEC)
-00013b cfee rjmp DO_EXECUTE
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000212 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-00013c 920a st -Y, r0
-00013d b60f in r0, SREG
-00013e 920a st -Y, r0
- .if (pclen==3)
-00013f 900f pop r0 ; some 128+K Flash devices use 3 cells for call/ret
- .endif
-000140 900f pop r0
-000141 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-000142 940a dec r0
- .if intvecsize == 1 ;
- .endif
-000143 2cb0 mov isrflag, r0
-000144 93ff push zh
-000145 93ef push zl
-000146 e1e2 ldi zl, low(intcnt)
-000147 e0f2 ldi zh, high(intcnt)
-000148 9406 lsr r0 ; we use byte addresses in the counter array, not words
-000149 0de0 add zl, r0
-00014a 1df3 adc zh, zeroh
-00014b 8000 ld r0, Z
-00014c 9403 inc r0
-00014d 8200 st Z, r0
-00014e 91ef pop zl
-00014f 91ff pop zh
-
-000150 9009 ld r0, Y+
-000151 be0f out SREG, r0
-000152 9009 ld r0, Y+
-000153 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000154 ff02 .dw $ff02
-000155 2b6d .db "m+"
-000156 0100 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000157 011b .dw DO_COLON
- PFA_MPLUS:
-000158 1255 .dw XT_S2D
-000159 0879 .dw XT_DPLUS
-00015a 04ae .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00015b ff03 .dw $ff03
-00015c 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-00015d 002a .db "ud*"
-00015e 0154 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-00015f 011b .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000160 054a
-000161 0598
-000162 0679
-000163 0572 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000164 055d
-000165 058f
-000166 0679
-000167 057a
-000168 0636
-000169 04ae .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00016a ff04 .dw $ff04
-00016b 6d75
-00016c 7861 .db "umax"
-00016d 015b .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00016e 011b .dw DO_COLON
- PFA_UMAX:
- .endif
-
-00016f 09ca
-000170 05f5 .DW XT_2DUP,XT_ULESS
-000171 04c7 .dw XT_DOCONDBRANCH
-000172 0174 DEST(UMAX1)
-000173 055d .DW XT_SWAP
-000174 0572 UMAX1: .DW XT_DROP
-000175 04ae .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000176 ff04 .dw $ff04
-000177 6d75
-000178 6e69 .db "umin"
-000179 016a .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00017a 011b .dw DO_COLON
- PFA_UMIN:
- .endif
-00017b 09ca
-00017c 0600 .DW XT_2DUP,XT_UGREATER
-00017d 04c7 .dw XT_DOCONDBRANCH
-00017e 0180 DEST(UMIN1)
-00017f 055d .DW XT_SWAP
-000180 0572 UMIN1: .DW XT_DROP
-000181 04ae .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000182 011b .dw DO_COLON
- PFA_IMMEDIATEQ:
-000183 04ce .dw XT_DOLITERAL
-000184 8000 .dw $8000
-000185 06ac .dw XT_AND
-000186 05b3 .dw XT_ZEROEQUAL
-000187 04c7 .dw XT_DOCONDBRANCH
-000188 018b DEST(IMMEDIATEQ1)
-000189 1274 .dw XT_ONE
-00018a 04ae .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00018b 05e4 .dw XT_TRUE
-00018c 04ae .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00018d ff0a .dw $ff0a
-00018e 616e
-00018f 656d
-000190 663e
-000191 616c
-000192 7367 .db "name>flags"
-000193 0176 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000194 011b .dw DO_COLON
- PFA_NAME2FLAGS:
-000195 082c .dw XT_FETCHI ; skip to link field
-000196 04ce .dw XT_DOLITERAL
-000197 ff00 .dw $ff00
-000198 06ac .dw XT_AND
-000199 04ae .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .include "dict/appl_8k.inc"
-
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-00019a ff06 .dw $ff06
-00019b 656e
-00019c 6577
-00019d 7473 .db "newest"
-00019e 018d .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-00019f 04dc .dw PFA_DOVARIABLE
- PFA_NEWEST:
-0001a0 024b .dw ram_newest
-
- .dseg
-00024b ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-0001a1 ff06 .dw $ff06
-0001a2 616c
-0001a3 6574
-0001a4 7473 .db "latest"
-0001a5 019a .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-0001a6 04dc .dw PFA_DOVARIABLE
- PFA_LATEST:
-0001a7 024f .dw ram_latest
-
- .dseg
-00024f ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-0001a8 ff08 .dw $ff08
-0001a9 6328
-0001aa 6572
-0001ab 7461
-0001ac 2965 .db "(create)"
-0001ad 01a1 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-0001ae 011b .dw DO_COLON
- PFA_DOCREATE:
- .endif
-0001af 0e1a
-0001b0 0305 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-0001b1 054a
-0001b2 019f
-0001b3 09c2
-0001b4 051a .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-0001b5 02ea
-0001b6 019f
-0001b7 051a .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-0001b8 04ae .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-0001b9 0001 .dw $0001
-0001ba 005c .db $5c,0
-0001bb 01a8 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-0001bc 011b .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-0001bd 0e01 .dw XT_SOURCE
-0001be 0589 .dw XT_NIP
-0001bf 09e3 .dw XT_TO_IN
-0001c0 051a .dw XT_STORE
-0001c1 04ae .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-0001c2 0001 .dw $0001
-0001c3 0028 .db "(" ,0
-0001c4 01b9 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-0001c5 011b .dw DO_COLON
- PFA_LPAREN:
- .endif
-0001c6 04ce .dw XT_DOLITERAL
-0001c7 0029 .dw ')'
-0001c8 0ded .dw XT_PARSE
-0001c9 09d3 .dw XT_2DROP
-0001ca 04ae .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-0001cb ff07 .dw $ff07
-0001cc 6f63
-0001cd 706d
-0001ce 6c69
-0001cf 0065 .db "compile",0
-0001d0 01c2 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-0001d1 011b .dw DO_COLON
- PFA_COMPILE:
- .endif
-0001d2 058f .dw XT_R_FROM
-0001d3 054a .dw XT_DUP
-0001d4 1011 .dw XT_ICELLPLUS
-0001d5 0598 .dw XT_TO_R
-0001d6 082c .dw XT_FETCHI
-0001d7 01dc .dw XT_COMMA
-0001d8 04ae .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-0001d9 ff01 .dw $ff01
-0001da 002c .db ',',0 ; ,
-0001db 01cb .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-0001dc 011b .dw DO_COLON
- PFA_COMMA:
-0001dd 0a13 .dw XT_DP
-0001de 080d .dw XT_STOREI
-0001df 0a13 .dw XT_DP
-0001e0 06c8 .dw XT_1PLUS
-0001e1 0fff .dw XT_DOTO
-0001e2 0a14 .dw PFA_DP
-0001e3 04ae .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-0001e4 0003 .dw $0003
-0001e5 275b
-0001e6 005d .db "[']",0
-0001e7 01d9 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-0001e8 011b .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-0001e9 0c70 .dw XT_TICK
-0001ea 01f2 .dw XT_LITERAL
-0001eb 04ae .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-0001ec 0007 .dw $0007
-0001ed 696c
-0001ee 6574
-0001ef 6172
-0001f0 006c .db "literal",0
-0001f1 01e4 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-0001f2 011b .dw DO_COLON
- PFA_LITERAL:
- .endif
-0001f3 01d1 .DW XT_COMPILE
-0001f4 04ce .DW XT_DOLITERAL
-0001f5 01dc .DW XT_COMMA
-0001f6 04ae .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-0001f7 0008 .dw $0008
-0001f8 6c73
-0001f9 7469
-0001fa 7265
-0001fb 6c61 .db "sliteral"
-0001fc 01ec .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-0001fd 011b .dw DO_COLON
- PFA_SLITERAL:
- .endif
-0001fe 01d1 .dw XT_COMPILE
-0001ff 0bd3 .dw XT_DOSLITERAL ; ( -- addr n)
-000200 0be1 .dw XT_SCOMMA
-000201 04ae .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-000202 011b .dw DO_COLON
- PFA_GMARK:
-000203 0a13 .dw XT_DP
-000204 01d1 .dw XT_COMPILE
-000205 ffff .dw -1 ; ffff does not erase flash
-000206 04ae .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000207 011b .dw DO_COLON
- PFA_GRESOLVE:
-000208 0fbd .dw XT_QSTACK
-000209 0a13 .dw XT_DP
-00020a 055d .dw XT_SWAP
-00020b 080d .dw XT_STOREI
-00020c 04ae .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-00020d 011b .dw DO_COLON
- PFA_LMARK:
-00020e 0a13 .dw XT_DP
-00020f 04ae .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-000210 011b .dw DO_COLON
- PFA_LRESOLVE:
-000211 0fbd .dw XT_QSTACK
-000212 01dc .dw XT_COMMA
-000213 04ae .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-000214 0005 .dw $0005
-000215 6861
-000216 6165
-000217 0064 .db "ahead",0
-000218 01f7 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-000219 011b .dw DO_COLON
- PFA_AHEAD:
- .endif
-00021a 01d1 .dw XT_COMPILE
-00021b 04bd .dw XT_DOBRANCH
-00021c 0202 .dw XT_GMARK
-00021d 04ae .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-00021e 0002 .dw $0002
-00021f 6669 .db "if"
-000220 0214 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-000221 011b .dw DO_COLON
- PFA_IF:
- .endif
-000222 01d1 .dw XT_COMPILE
-000223 04c7 .dw XT_DOCONDBRANCH
-000224 0202 .dw XT_GMARK
-000225 04ae .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-000226 0004 .dw $0004
-000227 6c65
-000228 6573 .db "else"
-000229 021e .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-00022a 011b .dw DO_COLON
- PFA_ELSE:
- .endif
-00022b 01d1 .dw XT_COMPILE
-00022c 04bd .dw XT_DOBRANCH
-00022d 0202 .dw XT_GMARK
-00022e 055d .dw XT_SWAP
-00022f 0207 .dw XT_GRESOLVE
-000230 04ae .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-000231 0004 .dw $0004
-000232 6874
-000233 6e65 .db "then"
-000234 0226 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-000235 011b .dw DO_COLON
- PFA_THEN:
- .endif
-000236 0207 .dw XT_GRESOLVE
-000237 04ae .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-000238 0005 .dw $0005
-000239 6562
-00023a 6967
-00023b 006e .db "begin",0
-00023c 0231 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-00023d 011b .dw DO_COLON
- PFA_BEGIN:
- .endif
-00023e 020d .dw XT_LMARK
-00023f 04ae .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-000240 0005 .dw $0005
-000241 6877
-000242 6c69
-000243 0065 .db "while",0
-000244 0238 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-000245 011b .dw DO_COLON
- PFA_WHILE:
- .endif
-000246 0221 .dw XT_IF
-000247 055d .dw XT_SWAP
-000248 04ae .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-000249 0006 .dw $0006
-00024a 6572
-00024b 6570
-00024c 7461 .db "repeat"
-00024d 0240 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-00024e 011b .dw DO_COLON
- PFA_REPEAT:
- .endif
-00024f 0262 .dw XT_AGAIN
-000250 0235 .dw XT_THEN
-000251 04ae .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-000252 0005 .dw $0005
-000253 6e75
-000254 6974
-000255 006c .db "until",0
-000256 0249 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-000257 011b .dw DO_COLON
- PFA_UNTIL:
- .endif
-000258 04ce .dw XT_DOLITERAL
-000259 04c7 .dw XT_DOCONDBRANCH
-00025a 01dc .dw XT_COMMA
-
-00025b 0210 .dw XT_LRESOLVE
-00025c 04ae .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-00025d 0005 .dw $0005
-00025e 6761
-00025f 6961
-000260 006e .db "again",0
-000261 0252 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-000262 011b .dw DO_COLON
- PFA_AGAIN:
- .endif
-000263 01d1 .dw XT_COMPILE
-000264 04bd .dw XT_DOBRANCH
-000265 0210 .dw XT_LRESOLVE
-000266 04ae .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-000267 0002 .dw $0002
-000268 6f64 .db "do"
-000269 025d .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-00026a 011b .dw DO_COLON
- PFA_DO:
-
- .endif
-00026b 01d1 .dw XT_COMPILE
-00026c 0734 .dw XT_DODO
-00026d 020d .dw XT_LMARK
-00026e 05ed .dw XT_ZERO
-00026f 02c5 .dw XT_TO_L
-000270 04ae .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-000271 0004 .dw $0004
-000272 6f6c
-000273 706f .db "loop"
-000274 0267 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000275 011b .dw DO_COLON
- PFA_LOOP:
- .endif
-000276 01d1 .dw XT_COMPILE
-000277 0762 .dw XT_DOLOOP
-000278 02ac .dw XT_ENDLOOP
-000279 04ae .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-00027a 0005 .dw $0005
-00027b 6c2b
-00027c 6f6f
-00027d 0070 .db "+loop",0
-00027e 0271 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-00027f 011b .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-000280 01d1 .dw XT_COMPILE
-000281 0753 .dw XT_DOPLUSLOOP
-000282 02ac .dw XT_ENDLOOP
-000283 04ae .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-000284 0005 .dw $0005
-000285 656c
-000286 7661
-000287 0065 .db "leave",0
-000288 027a .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-000289 011b .dw DO_COLON
- PFA_LEAVE:
- .endif
-00028a 01d1
-00028b 076d .DW XT_COMPILE,XT_UNLOOP
-00028c 0219
-00028d 02c5
-00028e 04ae .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-00028f 0003 .dw $0003
-000290 643f
-000291 006f .db "?do",0
-000292 0284 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000293 011b .dw DO_COLON
- PFA_QDO:
- .endif
-000294 01d1 .dw XT_COMPILE
-000295 029b .dw XT_QDOCHECK
-000296 0221 .dw XT_IF
-000297 026a .dw XT_DO
-000298 055d .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-000299 02c5 .dw XT_TO_L ; then follows at the end.
-00029a 04ae .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00029b 011b .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00029c 09ca .dw XT_2DUP
-00029d 126d .dw XT_EQUAL
-00029e 054a .dw XT_DUP
-00029f 0598 .dw XT_TO_R
-0002a0 04c7 .dw XT_DOCONDBRANCH
-0002a1 02a3 DEST(PFA_QDOCHECK1)
-0002a2 09d3 .dw XT_2DROP
- PFA_QDOCHECK1:
-0002a3 058f .dw XT_R_FROM
-0002a4 0696 .dw XT_INVERT
-0002a5 04ae .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-0002a6 ff07 .dw $ff07
-0002a7 6e65
-0002a8 6c64
-0002a9 6f6f
-0002aa 0070 .db "endloop",0
-0002ab 028f .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-0002ac 011b .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-0002ad 0210 .DW XT_LRESOLVE
-0002ae 02b9
-0002af 0552
-0002b0 04c7 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-0002b1 02b5 DEST(LOOP2)
-0002b2 0235 .DW XT_THEN
-0002b3 04bd .dw XT_DOBRANCH
-0002b4 02ae DEST(LOOP1)
-0002b5 04ae LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-0002b6 ff02 .dw $ff02
-0002b7 3e6c .db "l>"
-0002b8 02a6 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-0002b9 011b .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-0002ba 02d8 .dw XT_LP
-0002bb 0512 .dw XT_FETCH
-0002bc 0512 .dw XT_FETCH
-0002bd 04ce .dw XT_DOLITERAL
-0002be fffe .dw -2
-0002bf 02d8 .dw XT_LP
-0002c0 06fe .dw XT_PLUSSTORE
-0002c1 04ae .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-0002c2 ff02 .dw $ff02
-0002c3 6c3e .db ">l"
-0002c4 02b6 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-0002c5 011b .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-0002c6 1279 .dw XT_TWO
-0002c7 02d8 .dw XT_LP
-0002c8 06fe .dw XT_PLUSSTORE
-0002c9 02d8 .dw XT_LP
-0002ca 0512 .dw XT_FETCH
-0002cb 051a .dw XT_STORE
-0002cc 04ae .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-0002cd ff03 .dw $ff03
-0002ce 706c
-0002cf 0030 .db "lp0",0
-0002d0 02c2 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-0002d1 0509 .dw PFA_DOVALUE1
- PFA_LP0:
-0002d2 007e .dw CFG_LP0
-0002d3 101a .dw XT_EDEFERFETCH
-0002d4 1024 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-0002d5 ff02 .dw $ff02
-0002d6 706c .db "lp"
-0002d7 02cd .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-0002d8 04dc .dw PFA_DOVARIABLE
- PFA_LP:
-0002d9 0251 .dw ram_lp
-
- .dseg
-000251 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-0002da ff06 .dw $ff06
-0002db 7263
-0002dc 6165
-0002dd 6574 .db "create"
-0002de 02d5 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-0002df 011b .dw DO_COLON
- PFA_CREATE:
- .endif
-0002e0 01ae .dw XT_DOCREATE
-0002e1 030e .dw XT_REVEAL
-0002e2 01d1 .dw XT_COMPILE
-0002e3 04e9 .dw PFA_DOCONSTANT
-0002e4 04ae .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-0002e5 ff06 .dw $ff06
-0002e6 6568
-0002e7 6461
-0002e8 7265 .db "header"
-0002e9 02da .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-0002ea 011b .dw DO_COLON
- PFA_HEADER:
-0002eb 0a13 .dw XT_DP ; the new Name Field
-0002ec 0598 .dw XT_TO_R
-0002ed 0598 .dw XT_TO_R ; ( R: NFA WID )
-0002ee 054a .dw XT_DUP
-0002ef 05c1 .dw XT_GREATERZERO
-0002f0 04c7 .dw XT_DOCONDBRANCH
-0002f1 02fc .dw PFA_HEADER1
-0002f2 054a .dw XT_DUP
-0002f3 04ce .dw XT_DOLITERAL
-0002f4 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-0002f5 06b5 .dw XT_OR
-0002f6 0be5 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-0002f7 058f .dw XT_R_FROM
-0002f8 07f9 .dw XT_FETCHE
-0002f9 01dc .dw XT_COMMA
-0002fa 058f .dw XT_R_FROM
-0002fb 04ae .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-0002fc 04ce .dw XT_DOLITERAL
-0002fd fff0 .dw -16
-0002fe 0ca7 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-0002ff ff07 .dw $ff07
-000300 6c77
-000301 6373
-000302 706f
-000303 0065 .db "wlscope",0
-000304 02e5 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000305 1079 .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000306 007a .dw CFG_WLSCOPE
-000307 101a .dw XT_EDEFERFETCH
-000308 1024 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000309 ff06 .dw $ff06
-00030a 6572
-00030b 6576
-00030c 6c61 .db "reveal"
-00030d 02ff .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-00030e 011b .dw DO_COLON
- PFA_REVEAL:
- .endif
-00030f 019f
-000310 09c2
-000311 0512 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-000312 0552
-000313 04c7 .DW XT_QDUP,XT_DOCONDBRANCH
-000314 0319 DEST(REVEAL1)
-000315 019f
-000316 0512
-000317 055d
-000318 07d5 .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-000319 04ae .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-00031a 0005 .dw $0005
-00031b 6f64
-00031c 7365
-00031d 003e .db "does>",0
-00031e 0309 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-00031f 011b .dw DO_COLON
- PFA_DOES:
-000320 01d1 .dw XT_COMPILE
-000321 0332 .dw XT_DODOES
-000322 01d1 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-000323 940e .dw $940e ; the address of this compiled
-000324 01d1 .dw XT_COMPILE ; code will replace the XT of the
-000325 0327 .dw DO_DODOES ; word that CREATE created
-000326 04ae .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-000327 939a
-000328 938a savetos
-000329 01cb movw tosl, wl
-00032a 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
-00032b 917f pop wh ; some 128K Flash devices use 3 cells for call/ret
- .endif
-00032c 917f pop wh
-00032d 916f pop wl
-
-00032e 93bf push XH
-00032f 93af push XL
-000330 01db movw XL, wl
-000331 cded jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-000332 011b .dw DO_COLON
- PFA_DODOES:
-000333 058f .dw XT_R_FROM
-000334 019f .dw XT_NEWEST
-000335 09c2 .dw XT_CELLPLUS
-000336 0512 .dw XT_FETCH
-000337 07f9 .dw XT_FETCHE
-000338 10e4 .dw XT_NFA2CFA
-000339 080d .dw XT_STOREI
-00033a 04ae .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-00033b ff01 .dw $ff01
-00033c 003a .db ":",0
-00033d 031a .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-00033e 011b .dw DO_COLON
- PFA_COLON:
- .endif
-00033f 01ae .dw XT_DOCREATE
-000340 0349 .dw XT_COLONNONAME
-000341 0572 .dw XT_DROP
-000342 04ae .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-000343 ff07 .dw $ff07
-000344 6e3a
-000345 6e6f
-000346 6d61
-000347 0065 .db ":noname",0
-000348 033b .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-000349 011b .dw DO_COLON
- PFA_COLONNONAME:
-00034a 0a13 .dw XT_DP
-00034b 054a .dw XT_DUP
-00034c 01a6 .dw XT_LATEST
-00034d 051a .dw XT_STORE
-
-00034e 01d1 .dw XT_COMPILE
-00034f 011b .dw DO_COLON
-
-000350 035e .dw XT_RBRACKET
-000351 04ae .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-000352 0001 .dw $0001
-000353 003b .db $3b,0
-000354 0343 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-000355 011b .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-000356 01d1 .dw XT_COMPILE
-000357 04ae .dw XT_EXIT
-000358 0366 .dw XT_LBRACKET
-000359 030e .dw XT_REVEAL
-00035a 04ae .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-00035b ff01 .dw $ff01
-00035c 005d .db "]",0
-00035d 0352 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-00035e 011b .dw DO_COLON
- PFA_RBRACKET:
- .endif
-00035f 1274 .dw XT_ONE
-000360 09af .dw XT_STATE
-000361 051a .dw XT_STORE
-000362 04ae .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-000363 0001 .dw $0001
-000364 005b .db "[",0
-000365 035b .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-000366 011b .dw DO_COLON
- PFA_LBRACKET:
- .endif
-000367 05ed .dw XT_ZERO
-000368 09af .dw XT_STATE
-000369 051a .dw XT_STORE
-00036a 04ae .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-00036b ff08 .dw $ff08
-00036c 6176
-00036d 6972
-00036e 6261
-00036f 656c .db "variable"
-000370 0363 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-000371 011b .dw DO_COLON
- PFA_VARIABLE:
- .endif
-000372 0a24 .dw XT_HERE
-000373 037d .dw XT_CONSTANT
-000374 1279 .dw XT_TWO
-000375 0a2d .dw XT_ALLOT
-000376 04ae .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-000377 ff08 .dw $ff08
-000378 6f63
-000379 736e
-00037a 6174
-00037b 746e .db "constant"
-00037c 036b .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-00037d 011b .dw DO_COLON
- PFA_CONSTANT:
- .endif
-00037e 01ae .dw XT_DOCREATE
-00037f 030e .dw XT_REVEAL
-000380 01d1 .dw XT_COMPILE
-000381 04dc .dw PFA_DOVARIABLE
-000382 01dc .dw XT_COMMA
-000383 04ae .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-000384 ff04 .dw $ff04
-000385 7375
-000386 7265 .db "user"
-000387 0377 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-000388 011b .dw DO_COLON
- PFA_USER:
-000389 01ae .dw XT_DOCREATE
-00038a 030e .dw XT_REVEAL
-
-00038b 01d1 .dw XT_COMPILE
-00038c 04ef .dw PFA_DOUSER
-00038d 01dc .dw XT_COMMA
-00038e 04ae .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-00038f 0007 .dw $0007
-000390 6572
-000391 7563
-000392 7372
-000393 0065 .db "recurse",0
-000394 0384 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000395 011b .dw DO_COLON
- PFA_RECURSE:
- .endif
-000396 01a6 .dw XT_LATEST
-000397 0512 .dw XT_FETCH
-000398 01dc .dw XT_COMMA
-000399 04ae .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-00039a ff09 .dw $ff09
-00039b 6d69
-00039c 656d
-00039d 6964
-00039e 7461
-00039f 0065 .db "immediate",0
-0003a0 038f .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-0003a1 011b .dw DO_COLON
- PFA_IMMEDIATE:
-0003a2 0443 .dw XT_GET_CURRENT
-0003a3 07f9 .dw XT_FETCHE
-0003a4 054a .dw XT_DUP
-0003a5 082c .dw XT_FETCHI
-0003a6 04ce .dw XT_DOLITERAL
-0003a7 7fff .dw $7fff
-0003a8 06ac .dw XT_AND
-0003a9 055d .dw XT_SWAP
-0003aa 080d .dw XT_STOREI
-0003ab 04ae .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-0003ac 0006 .dw $0006
-0003ad 635b
-0003ae 6168
-0003af 5d72 .db "[char]"
-0003b0 039a .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-0003b1 011b .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-0003b2 01d1 .dw XT_COMPILE
-0003b3 04ce .dw XT_DOLITERAL
-0003b4 0d50 .dw XT_CHAR
-0003b5 01dc .dw XT_COMMA
-0003b6 04ae .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-0003b7 0006 .dw $0006
-0003b8 6261
-0003b9 726f
-0003ba 2274 .db "abort",'"'
-0003bb 03ac .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-0003bc 011b .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-0003bd 0925 .dw XT_SQUOTE
-0003be 01d1 .dw XT_COMPILE
-0003bf 03ce .dw XT_QABORT
-0003c0 04ae .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-0003c1 ff05 .dw $ff05
-0003c2 6261
-0003c3 726f
-0003c4 0074 .db "abort",0
-0003c5 03b7 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-0003c6 011b .dw DO_COLON
- PFA_ABORT:
- .endif
-0003c7 05e4 .dw XT_TRUE
-0003c8 0ca7 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-0003c9 ff06 .dw $ff06
-0003ca 613f
-0003cb 6f62
-0003cc 7472 .db "?abort"
-0003cd 03c1 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-0003ce 011b .dw DO_COLON
- PFA_QABORT:
-
- .endif
-0003cf 057a
-0003d0 04c7 .DW XT_ROT,XT_DOCONDBRANCH
-0003d1 03d4 DEST(QABO1)
-0003d2 0c06
-0003d3 03c6 .DW XT_ITYPE,XT_ABORT
-0003d4 09d3
-0003d5 04ae QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-0003d6 ff09 .dw $ff09
-0003d7 6567
-0003d8 2d74
-0003d9 7473
-0003da 6361
-0003db 006b .db "get-stack",0
-0003dc 03c9 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-0003dd 011b .dw DO_COLON
- .endif
-0003de 054a .dw XT_DUP
-0003df 09c2 .dw XT_CELLPLUS
-0003e0 055d .dw XT_SWAP
-0003e1 07f9 .dw XT_FETCHE
-0003e2 054a .dw XT_DUP
-0003e3 0598 .dw XT_TO_R
-0003e4 05ed .dw XT_ZERO
-0003e5 055d .dw XT_SWAP ; go from bigger to smaller addresses
-0003e6 029b .dw XT_QDOCHECK
-0003e7 04c7 .dw XT_DOCONDBRANCH
-0003e8 03f4 DEST(PFA_N_FETCH_E2)
-0003e9 0734 .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-0003ea 0745 .dw XT_I
-0003eb 06ce .dw XT_1MINUS
-0003ec 09bc .dw XT_CELLS ; ( -- ee-addr i*2 )
-0003ed 0568 .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-0003ee 0636 .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-0003ef 07f9 .dw XT_FETCHE ;( -- ee-addr item_i )
-0003f0 055d .dw XT_SWAP ;( -- item_i ee-addr )
-0003f1 05e4 .dw XT_TRUE ; shortcut for -1
-0003f2 0753 .dw XT_DOPLUSLOOP
-0003f3 03ea DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-0003f4 09d3 .dw XT_2DROP
-0003f5 058f .dw XT_R_FROM
-0003f6 04ae .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-0003f7 ff09 .dw $ff09
-0003f8 6573
-0003f9 2d74
-0003fa 7473
-0003fb 6361
-0003fc 006b .db "set-stack",0
-0003fd 03d6 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-0003fe 011b .dw DO_COLON
- PFA_SET_STACK:
- .endif
-0003ff 0568 .dw XT_OVER
-000400 05ba .dw XT_ZEROLESS
-000401 04c7 .dw XT_DOCONDBRANCH
-000402 0406 DEST(PFA_SET_STACK0)
-000403 04ce .dw XT_DOLITERAL
-000404 fffc .dw -4
-000405 0ca7 .dw XT_THROW
- PFA_SET_STACK0:
-000406 09ca .dw XT_2DUP
-000407 07d5 .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000408 055d .dw XT_SWAP
-000409 05ed .dw XT_ZERO
-00040a 029b .dw XT_QDOCHECK
-00040b 04c7 .dw XT_DOCONDBRANCH
-00040c 0413 DEST(PFA_SET_STACK2)
-00040d 0734 .dw XT_DODO
- PFA_SET_STACK1:
-00040e 09c2 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-00040f 09db .dw XT_TUCK ; ( -- e-addr i_x e-addr
-000410 07d5 .dw XT_STOREE
-000411 0762 .dw XT_DOLOOP
-000412 040e DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-000413 0572 .dw XT_DROP
-000414 04ae .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-000415 ff09 .dw $ff09
-000416 616d
-000417 2d70
-000418 7473
-000419 6361
-00041a 006b .db "map-stack",0
-00041b 03f7 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-00041c 011b .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-00041d 054a .dw XT_DUP
-00041e 09c2 .dw XT_CELLPLUS
-00041f 055d .dw XT_SWAP
-000420 07f9 .dw XT_FETCHE
-000421 09bc .dw XT_CELLS
-000422 124c .dw XT_BOUNDS
-000423 029b .dw XT_QDOCHECK
-000424 04c7 .dw XT_DOCONDBRANCH
-000425 0438 DEST(PFA_MAPSTACK3)
-000426 0734 .dw XT_DODO
- PFA_MAPSTACK1:
-000427 0745 .dw XT_I
-000428 07f9 .dw XT_FETCHE ; -- i*x XT id
-000429 055d .dw XT_SWAP
-00042a 0598 .dw XT_TO_R
-00042b 05a1 .dw XT_R_FETCH
-00042c 04b8 .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-00042d 0552 .dw XT_QDUP
-00042e 04c7 .dw XT_DOCONDBRANCH
-00042f 0434 DEST(PFA_MAPSTACK2)
-000430 058f .dw XT_R_FROM
-000431 0572 .dw XT_DROP
-000432 076d .dw XT_UNLOOP
-000433 04ae .dw XT_EXIT
- PFA_MAPSTACK2:
-000434 058f .dw XT_R_FROM
-000435 1279 .dw XT_TWO
-000436 0753 .dw XT_DOPLUSLOOP
-000437 0427 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-000438 0572 .dw XT_DROP
-000439 05ed .dw XT_ZERO
-00043a 04ae .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-00043b ff0b .dw $ff0b
-00043c 6567
-00043d 2d74
-00043e 7563
-00043f 7272
-000440 6e65
-000441 0074 .db "get-current",0
-000442 0415 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-000443 011b .dw DO_COLON
- PFA_GET_CURRENT:
-000444 04ce .dw XT_DOLITERAL
-000445 0084 .dw CFG_CURRENT
-000446 07f9 .dw XT_FETCHE
-000447 04ae .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-000448 ff09 .dw $ff09
-000449 6567
-00044a 2d74
-00044b 726f
-00044c 6564
-00044d 0072 .db "get-order",0
-00044e 043b .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-00044f 011b .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-000450 04ce .dw XT_DOLITERAL
-000451 0088 .dw CFG_ORDERLISTLEN
-000452 03dd .dw XT_GET_STACK
-000453 04ae .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-000454 ff09 .dw $ff09
-000455 6663
-000456 2d67
-000457 726f
-000458 6564
-000459 0072 .db "cfg-order",0
-00045a 0448 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-00045b 04dc .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-00045c 0088 .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-00045d ff07 .dw $ff07
-00045e 6f63
-00045f 706d
-000460 7261
-000461 0065 .db "compare",0
-000462 0454 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-000463 0464 .dw PFA_COMPARE
- PFA_COMPARE:
-000464 93bf push xh
-000465 93af push xl
-000466 018c movw temp0, tosl
-000467 9189
-000468 9199 loadtos
-000469 01dc movw xl, tosl
-00046a 9189
-00046b 9199 loadtos
-00046c 019c movw temp2, tosl
-00046d 9189
-00046e 9199 loadtos
-00046f 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-000470 90ed ld temp4, X+
-000471 90f1 ld temp5, Z+
-000472 14ef cp temp4, temp5
-000473 f451 brne PFA_COMPARE_NOTEQUAL
-000474 950a dec temp0
-000475 f019 breq PFA_COMPARE_ENDREACHED2
-000476 952a dec temp2
-000477 f7c1 brne PFA_COMPARE_LOOP
-000478 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-000479 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-00047a 2b02 or temp0, temp2
-00047b f411 brne PFA_COMPARE_CHECKLASTCHAR
-00047c 2788 clr tosl
-00047d c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-00047e ef8f ser tosl
-00047f c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000480 2f98 mov tosh, tosl
-000481 91af pop xl
-000482 91bf pop xh
-000483 cc9b jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000484 ff07 .dw $ff07
-000485 666e
-000486 3e61
-000487 666c
-000488 0061 .db "nfa>lfa",0
-000489 045d .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-00048a 011b .dw DO_COLON
- PFA_NFA2LFA:
-00048b 10d8 .dw XT_NAME2STRING
-00048c 06c8 .dw XT_1PLUS
-00048d 069d .dw XT_2SLASH
-00048e 0636 .dw XT_PLUS
-00048f 04ae .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 4000
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
-
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000490 ff0b .dw $ff0b
-000491 7061
-000492 6c70
-000493 7574
-000494 6e72
-000495 656b
-000496 0079 .db "applturnkey",0
-000497 0484 .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000498 011b .dw DO_COLON
- PFA_APPLTURNKEY:
-000499 0105 .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-00049a 08dd .dw XT_INTON
- .endif
-
-00049b 0fca .dw XT_DOT_VER
-00049c 0c48 .dw XT_SPACE
-00049d 09a4 .dw XT_F_CPU
-00049e 04ce .dw XT_DOLITERAL
-00049f 03e8 .dw 1000
-0004a0 065b .dw XT_UMSLASHMOD
-0004a1 0589 .dw XT_NIP
-0004a2 0a42 .dw XT_DECIMAL
-0004a3 0b88 .dw XT_DOT
-0004a4 0bd3 .dw XT_DOSLITERAL
-0004a5 0004 .dw 4
-0004a6 486b
-0004a7 207a .db "kHz "
-0004a8 0c06 .dw XT_ITYPE
-
-0004a9 04ae .dw XT_EXIT
-
- .include "dict/nrww.inc" ; well, not really nrww, but simplifies things alot
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-0004aa ff04 .dw $ff04
-0004ab 7865
-0004ac 7469 .db "exit"
-0004ad 0490 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-0004ae 04af .dw PFA_EXIT
- PFA_EXIT:
-0004af 91af pop XL
-0004b0 91bf pop XH
-0004b1 cc6d jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-0004b2 ff07 .dw $ff07
-0004b3 7865
-0004b4 6365
-0004b5 7475
-0004b6 0065 .db "execute",0
-0004b7 04aa .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-0004b8 04b9 .dw PFA_EXECUTE
- PFA_EXECUTE:
-0004b9 01bc movw wl, tosl
-0004ba 9189
-0004bb 9199 loadtos
-0004bc cc6d jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-0004bd 04be .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-0004be 01fd movw zl, XL
-0004bf 2755
-0004c0 0fee
-0004c1 1fff
-0004c2 1f55
-0004c3 bf5b
-0004c4 91a7
-0004c5 91b7 readflashcell XL,XH
-0004c6 cc58 jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-0004c7 04c8 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-0004c8 2b98 or tosh, tosl
-0004c9 9189
-0004ca 9199 loadtos
-0004cb f391 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-0004cc 9611 adiw XL, 1
-0004cd cc51 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-0004ce 04cf .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-0004cf 939a
-0004d0 938a savetos
-0004d1 01fd movw zl, xl
-0004d2 2755
-0004d3 0fee
-0004d4 1fff
-0004d5 1f55
-0004d6 bf5b
-0004d7 9187
-0004d8 9197 readflashcell tosl,tosh
-0004d9 9611 adiw xl, 1
-0004da cc44 jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-0004db 04dc .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-0004dc 939a
-0004dd 938a savetos
-0004de 01fb movw zl, wl
-0004df 9631 adiw zl,1
-0004e0 2755
-0004e1 0fee
-0004e2 1fff
-0004e3 1f55
-0004e4 bf5b
-0004e5 9187
-0004e6 9197 readflashcell tosl,tosh
-0004e7 cc37 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-0004e8 04e9 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-0004e9 939a
-0004ea 938a savetos
-0004eb 01cb movw tosl, wl
-0004ec 9601 adiw tosl, 1
-0004ed cc31 jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-0004ee 04ef .dw PFA_DOUSER
- PFA_DOUSER:
-0004ef 939a
-0004f0 938a savetos
-0004f1 01fb movw zl, wl
-0004f2 9631 adiw zl, 1
-0004f3 2755
-0004f4 0fee
-0004f5 1fff
-0004f6 1f55
-0004f7 bf5b
-0004f8 9187
-0004f9 9197 readflashcell tosl,tosh
-0004fa 0d84 add tosl, upl
-0004fb 1d95 adc tosh, uph
-0004fc cc22 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-0004fd ff07 .dw $ff07
-0004fe 7628
-0004ff 6c61
-000500 6575
-000501 0029 .db "(value)", 0
-000502 04b2 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-000503 011b .dw DO_COLON
- PFA_DOVALUE:
-000504 01ae .dw XT_DOCREATE
-000505 030e .dw XT_REVEAL
-000506 01d1 .dw XT_COMPILE
-000507 0509 .dw PFA_DOVALUE1
-000508 04ae .dw XT_EXIT
- PFA_DOVALUE1:
-000509 de1d call_ DO_DODOES
-00050a 054a .dw XT_DUP
-00050b 1011 .dw XT_ICELLPLUS
-00050c 082c .dw XT_FETCHI
-00050d 04b8 .dw XT_EXECUTE
-00050e 04ae .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-00050f ff01 .dw $ff01
-000510 0040 .db "@",0
-000511 04fd .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-000512 0513 .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-000513 01fc movw zl, tosl
- ; low byte is read before the high byte
-000514 9181 ld tosl, z+
-000515 9191 ld tosh, z+
-000516 cc08 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-000517 ff01 .dw $ff01
-000518 0021 .db "!",0
-000519 050f .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-00051a 051b .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-00051b 01fc movw zl, tosl
-00051c 9189
-00051d 9199 loadtos
- ; the high byte is written before the low byte
-00051e 8391 std Z+1, tosh
-00051f 8380 std Z+0, tosl
-000520 9189
-000521 9199 loadtos
-000522 cbfc jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-000523 ff02 .dw $ff02
-000524 2163 .db "c!"
-000525 0517 .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-000526 0527 .dw PFA_CSTORE
- PFA_CSTORE:
-000527 01fc movw zl, tosl
-000528 9189
-000529 9199 loadtos
-00052a 8380 st Z, tosl
-00052b 9189
-00052c 9199 loadtos
-00052d cbf1 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-00052e ff02 .dw $ff02
-00052f 4063 .db "c@"
-000530 0523 .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-000531 0532 .dw PFA_CFETCH
- PFA_CFETCH:
-000532 01fc movw zl, tosl
-000533 2799 clr tosh
-000534 8180 ld tosl, Z
-000535 cbe9 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-000536 ff02 .dw $ff02
-000537 7540 .db "@u"
-000538 052e .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-000539 011b .dw DO_COLON
- PFA_FETCHU:
-00053a 079b .dw XT_UP_FETCH
-00053b 0636 .dw XT_PLUS
-00053c 0512 .dw XT_FETCH
-00053d 04ae .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-00053e ff02 .dw $ff02
-00053f 7521 .db "!u"
-000540 0536 .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-000541 011b .dw DO_COLON
- PFA_STOREU:
-000542 079b .dw XT_UP_FETCH
-000543 0636 .dw XT_PLUS
-000544 051a .dw XT_STORE
-000545 04ae .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-000546 ff03 .dw $ff03
-000547 7564
-000548 0070 .db "dup",0
-000549 053e .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-00054a 054b .dw PFA_DUP
- PFA_DUP:
-00054b 939a
-00054c 938a savetos
-00054d cbd1 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-00054e ff04 .dw $ff04
-00054f 643f
-000550 7075 .db "?dup"
-000551 0546 .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-000552 0553 .dw PFA_QDUP
- PFA_QDUP:
-000553 2f08 mov temp0, tosl
-000554 2b09 or temp0, tosh
-000555 f011 breq PFA_QDUP1
-000556 939a
-000557 938a savetos
- PFA_QDUP1:
-000558 cbc6 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-000559 ff04 .dw $ff04
-00055a 7773
-00055b 7061 .db "swap"
-00055c 054e .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-00055d 055e .dw PFA_SWAP
- PFA_SWAP:
-00055e 018c movw temp0, tosl
-00055f 9189
-000560 9199 loadtos
-000561 931a st -Y, temp1
-000562 930a st -Y, temp0
-000563 cbbb jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-000564 ff04 .dw $ff04
-000565 766f
-000566 7265 .db "over"
-000567 0559 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-000568 0569 .dw PFA_OVER
- PFA_OVER:
-000569 939a
-00056a 938a savetos
-00056b 818a ldd tosl, Y+2
-00056c 819b ldd tosh, Y+3
-
-00056d cbb1 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-00056e ff04 .dw $ff04
-00056f 7264
-000570 706f .db "drop"
-000571 0564 .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-000572 0573 .dw PFA_DROP
- PFA_DROP:
-000573 9189
-000574 9199 loadtos
-000575 cba9 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-000576 ff03 .dw $ff03
-000577 6f72
-000578 0074 .db "rot",0
-000579 056e .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-00057a 057b .dw PFA_ROT
- PFA_ROT:
-00057b 018c movw temp0, tosl
-00057c 9129 ld temp2, Y+
-00057d 9139 ld temp3, Y+
-00057e 9189
-00057f 9199 loadtos
-
-000580 933a st -Y, temp3
-000581 932a st -Y, temp2
-000582 931a st -Y, temp1
-000583 930a st -Y, temp0
-
-000584 cb9a jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-000585 ff03 .dw $ff03
-000586 696e
-000587 0070 .db "nip",0
-000588 0576 .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-000589 058a .dw PFA_NIP
- PFA_NIP:
-00058a 9622 adiw yl, 2
-00058b cb93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-00058c ff02 .dw $ff02
-00058d 3e72 .db "r>"
-00058e 0585 .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-00058f 0590 .dw PFA_R_FROM
- PFA_R_FROM:
-000590 939a
-000591 938a savetos
-000592 918f pop tosl
-000593 919f pop tosh
-000594 cb8a jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-000595 ff02 .dw $ff02
-000596 723e .db ">r"
-000597 058c .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-000598 0599 .dw PFA_TO_R
- PFA_TO_R:
-000599 939f push tosh
-00059a 938f push tosl
-00059b 9189
-00059c 9199 loadtos
-00059d cb81 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-00059e ff02 .dw $ff02
-00059f 4072 .db "r@"
-0005a0 0595 .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-0005a1 05a2 .dw PFA_R_FETCH
- PFA_R_FETCH:
-0005a2 939a
-0005a3 938a savetos
-0005a4 918f pop tosl
-0005a5 919f pop tosh
-0005a6 939f push tosh
-0005a7 938f push tosl
-0005a8 cb76 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-0005a9 ff02 .dw $ff02
-0005aa 3e3c .db "<>"
-0005ab 059e .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-0005ac 011b .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-0005ad 126d
-0005ae 05b3
-0005af 04ae .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-0005b0 ff02 .dw $ff02
-0005b1 3d30 .db "0="
-0005b2 05a9 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-0005b3 05b4 .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-0005b4 2b98 or tosh, tosl
-0005b5 f5d1 brne PFA_ZERO1
-0005b6 c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-0005b7 ff02 .dw $ff02
-0005b8 3c30 .db "0<"
-0005b9 05b0 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-0005ba 05bb .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-0005bb fd97 sbrc tosh,7
-0005bc c02a rjmp PFA_TRUE1
-0005bd c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-0005be ff02 .dw $ff02
-0005bf 3e30 .db "0>"
-0005c0 05b7 .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-0005c1 05c2 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-0005c2 1582 cp tosl, zerol
-0005c3 0593 cpc tosh, zeroh
-0005c4 f15c brlt PFA_ZERO1
-0005c5 f151 brbs 1, PFA_ZERO1
-0005c6 c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-0005c7 ff03 .dw $ff03
-0005c8 3064
-0005c9 003e .db "d0>",0
-0005ca 05be .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-0005cb 05cc .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-0005cc 1582 cp tosl, zerol
-0005cd 0593 cpc tosh, zeroh
-0005ce 9189
-0005cf 9199 loadtos
-0005d0 0582 cpc tosl, zerol
-0005d1 0593 cpc tosh, zeroh
-0005d2 f0ec brlt PFA_ZERO1
-0005d3 f0e1 brbs 1, PFA_ZERO1
-0005d4 c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-0005d5 ff03 .dw $ff03
-0005d6 3064
-0005d7 003c .db "d0<",0
-0005d8 05c7 .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-0005d9 05da .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-0005da 9622 adiw Y,2
-0005db fd97 sbrc tosh,7
-0005dc 940c 05e7 jmp PFA_TRUE1
-0005de 940c 05f0 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-0005e0 ff04 .dw $ff04
-0005e1 7274
-0005e2 6575 .db "true"
-0005e3 05d5 .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-0005e4 05e5 .dw PFA_TRUE
- PFA_TRUE:
-0005e5 939a
-0005e6 938a savetos
- PFA_TRUE1:
-0005e7 ef8f ser tosl
-0005e8 ef9f ser tosh
-0005e9 cb35 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-0005ea ff01 .dw $ff01
-0005eb 0030 .db "0",0
-0005ec 05e0 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-0005ed 05ee .dw PFA_ZERO
- PFA_ZERO:
-0005ee 939a
-0005ef 938a savetos
- PFA_ZERO1:
-0005f0 01c1 movw tosl, zerol
-0005f1 cb2d jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-0005f2 ff02 .dw $ff02
-0005f3 3c75 .db "u<"
-0005f4 05ea .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-0005f5 05f6 .dw PFA_ULESS
- PFA_ULESS:
-0005f6 9129 ld temp2, Y+
-0005f7 9139 ld temp3, Y+
-0005f8 1782 cp tosl, temp2
-0005f9 0793 cpc tosh, temp3
-0005fa f3a8 brlo PFA_ZERO1
-0005fb f3a1 brbs 1, PFA_ZERO1
-0005fc cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-0005fd ff02 .dw $ff02
-0005fe 3e75 .db "u>"
-0005ff 05f2 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-000600 011b .dw DO_COLON
- PFA_UGREATER:
- .endif
-000601 055d .DW XT_SWAP
-000602 05f5 .dw XT_ULESS
-000603 04ae .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-000604 ff01 .dw $ff01
-000605 003c .db "<",0
-000606 05fd .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-000607 0608 .dw PFA_LESS
- PFA_LESS:
-000608 9129 ld temp2, Y+
-000609 9139 ld temp3, Y+
-00060a 1728 cp temp2, tosl
-00060b 0739 cpc temp3, tosh
- PFA_LESSDONE:
-00060c f71c brge PFA_ZERO1
-00060d cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-00060e ff01 .dw $ff01
-00060f 003e .db ">",0
-000610 0604 .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-000611 0612 .dw PFA_GREATER
- PFA_GREATER:
-000612 9129 ld temp2, Y+
-000613 9139 ld temp3, Y+
-000614 1728 cp temp2, tosl
-000615 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-000616 f2cc brlt PFA_ZERO1
-000617 f2c1 brbs 1, PFA_ZERO1
-000618 cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-000619 ff04 .dw $ff04
-00061a 6f6c
-00061b 3267 .db "log2"
-00061c 060e .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-00061d 061e .dw PFA_LOG2
- PFA_LOG2:
-00061e 01fc movw zl, tosl
-00061f 2799 clr tosh
-000620 e180 ldi tosl, 16
- PFA_LOG2_1:
-000621 958a dec tosl
-000622 f022 brmi PFA_LOG2_2 ; wrong data
-000623 0fee lsl zl
-000624 1fff rol zh
-000625 f7d8 brcc PFA_LOG2_1
-000626 caf8 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-000627 959a dec tosh
-000628 caf6 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-000629 ff01 .dw $ff01
-00062a 002d .db "-",0
-00062b 0619 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-00062c 062d .dw PFA_MINUS
- PFA_MINUS:
-00062d 9109 ld temp0, Y+
-00062e 9119 ld temp1, Y+
-00062f 1b08 sub temp0, tosl
-000630 0b19 sbc temp1, tosh
-000631 01c8 movw tosl, temp0
-000632 caec jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-000633 ff01 .dw $ff01
-000634 002b .db "+",0
-000635 0629 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-000636 0637 .dw PFA_PLUS
- PFA_PLUS:
-000637 9109 ld temp0, Y+
-000638 9119 ld temp1, Y+
-000639 0f80 add tosl, temp0
-00063a 1f91 adc tosh, temp1
-00063b cae3 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-00063c ff02 .dw $ff02
-00063d 2a6d .db "m*"
-00063e 0633 .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-00063f 0640 .dw PFA_MSTAR
- PFA_MSTAR:
-000640 018c movw temp0, tosl
-000641 9189
-000642 9199 loadtos
-000643 019c movw temp2, tosl
- ; high cell ah*bh
-000644 0231 muls temp3, temp1
-000645 0170 movw temp4, r0
- ; low cell al*bl
-000646 9f20 mul temp2, temp0
-000647 01c0 movw tosl, r0
- ; signed ah*bl
-000648 0330 mulsu temp3, temp0
-000649 08f3 sbc temp5, zeroh
-00064a 0d90 add tosh, r0
-00064b 1ce1 adc temp4, r1
-00064c 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-00064d 0312 mulsu temp1, temp2
-00064e 08f3 sbc temp5, zeroh
-00064f 0d90 add tosh, r0
-000650 1ce1 adc temp4, r1
-000651 1cf3 adc temp5, zeroh
-
-000652 939a
-000653 938a savetos
-000654 01c7 movw tosl, temp4
-000655 cac9 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-000656 ff06 .dw $ff06
-000657 6d75
-000658 6d2f
-000659 646f .db "um/mod"
-00065a 063c .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-00065b 065c .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-00065c 017c movw temp4, tosl
-
-00065d 9129 ld temp2, Y+
-00065e 9139 ld temp3, Y+
-
-00065f 9109 ld temp0, Y+
-000660 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-000661 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-000662 2755 clr temp7
-000663 0f00 lsl temp0
-000664 1f11 rol temp1
-000665 1f22 rol temp2
-000666 1f33 rol temp3
-000667 1f55 rol temp7
-
- ; try subtracting divisor
-000668 152e cp temp2, temp4
-000669 053f cpc temp3, temp5
-00066a 0552 cpc temp7,zerol
-
-00066b f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-00066c 9503 inc temp0
-00066d 192e sub temp2, temp4
-00066e 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-00066f 954a dec temp6
-000670 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-000671 933a st -Y,temp3
-000672 932a st -Y,temp2
-
- ; put quotient on stack
-000673 01c8 movw tosl, temp0
-000674 caaa jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-000675 ff03 .dw $ff03
-000676 6d75
-000677 002a .db "um*",0
-000678 0656 .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-000679 067a .dw PFA_UMSTAR
- PFA_UMSTAR:
-00067a 018c movw temp0, tosl
-00067b 9189
-00067c 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-00067d 9f80 mul tosl,temp0
-00067e 01f0 movw zl, r0
-00067f 2722 clr temp2
-000680 2733 clr temp3
- ; middle bytes
-000681 9f90 mul tosh, temp0
-000682 0df0 add zh, r0
-000683 1d21 adc temp2, r1
-000684 1d33 adc temp3, zeroh
-
-000685 9f81 mul tosl, temp1
-000686 0df0 add zh, r0
-000687 1d21 adc temp2, r1
-000688 1d33 adc temp3, zeroh
-
-000689 9f91 mul tosh, temp1
-00068a 0d20 add temp2, r0
-00068b 1d31 adc temp3, r1
-00068c 01cf movw tosl, zl
-00068d 939a
-00068e 938a savetos
-00068f 01c9 movw tosl, temp2
-000690 ca8e jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-000691 ff06 .dw $ff06
-000692 6e69
-000693 6576
-000694 7472 .db "invert"
-000695 0675 .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-000696 0697 .dw PFA_INVERT
- PFA_INVERT:
-000697 9580 com tosl
-000698 9590 com tosh
-000699 ca85 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-00069a ff02 .dw $ff02
-00069b 2f32 .db "2/"
-00069c 0691 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-00069d 069e .dw PFA_2SLASH
- PFA_2SLASH:
-00069e 9595 asr tosh
-00069f 9587 ror tosl
-0006a0 ca7e jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-0006a1 ff02 .dw $ff02
-0006a2 2a32 .db "2*"
-0006a3 069a .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-0006a4 06a5 .dw PFA_2STAR
- PFA_2STAR:
-0006a5 0f88 lsl tosl
-0006a6 1f99 rol tosh
-0006a7 ca77 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-0006a8 ff03 .dw $ff03
-0006a9 6e61
-0006aa 0064 .db "and",0
-0006ab 06a1 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-0006ac 06ad .dw PFA_AND
- PFA_AND:
-0006ad 9109 ld temp0, Y+
-0006ae 9119 ld temp1, Y+
-0006af 2380 and tosl, temp0
-0006b0 2391 and tosh, temp1
-0006b1 ca6d jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-0006b2 ff02 .dw $ff02
-0006b3 726f .db "or"
-0006b4 06a8 .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-0006b5 06b6 .dw PFA_OR
- PFA_OR:
-0006b6 9109 ld temp0, Y+
-0006b7 9119 ld temp1, Y+
-0006b8 2b80 or tosl, temp0
-0006b9 2b91 or tosh, temp1
-0006ba ca64 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-0006bb ff03 .dw $ff03
-0006bc 6f78
-0006bd 0072 .db "xor",0
-0006be 06b2 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-0006bf 06c0 .dw PFA_XOR
- PFA_XOR:
-0006c0 9109 ld temp0, Y+
-0006c1 9119 ld temp1, Y+
-0006c2 2780 eor tosl, temp0
-0006c3 2791 eor tosh, temp1
-0006c4 ca5a jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-0006c5 ff02 .dw $ff02
-0006c6 2b31 .db "1+"
-0006c7 06bb .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-0006c8 06c9 .dw PFA_1PLUS
- PFA_1PLUS:
-0006c9 9601 adiw tosl,1
-0006ca ca54 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-0006cb ff02 .dw $ff02
-0006cc 2d31 .db "1-"
-0006cd 06c5 .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-0006ce 06cf .dw PFA_1MINUS
- PFA_1MINUS:
-0006cf 9701 sbiw tosl, 1
-0006d0 ca4e jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-0006d1 ff07 .dw $ff07
-0006d2 6e3f
-0006d3 6765
-0006d4 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-0006d5 0065 .db "?negate"
-0006d6 06cb .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-0006d7 011b .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-0006d8 05ba
-0006d9 04c7 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-0006da 06dc DEST(QNEG1)
-0006db 0aa5 .DW XT_NEGATE
-0006dc 04ae QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-0006dd ff06 .dw $ff06
-0006de 736c
-0006df 6968
-0006e0 7466 .db "lshift"
-0006e1 06d1 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-0006e2 06e3 .dw PFA_LSHIFT
- PFA_LSHIFT:
-0006e3 01fc movw zl, tosl
-0006e4 9189
-0006e5 9199 loadtos
- PFA_LSHIFT1:
-0006e6 9731 sbiw zl, 1
-0006e7 f01a brmi PFA_LSHIFT2
-0006e8 0f88 lsl tosl
-0006e9 1f99 rol tosh
-0006ea cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-0006eb ca33 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-0006ec ff06 .dw $ff06
-0006ed 7372
-0006ee 6968
-0006ef 7466 .db "rshift"
-0006f0 06dd .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-0006f1 06f2 .dw PFA_RSHIFT
- PFA_RSHIFT:
-0006f2 01fc movw zl, tosl
-0006f3 9189
-0006f4 9199 loadtos
- PFA_RSHIFT1:
-0006f5 9731 sbiw zl, 1
-0006f6 f01a brmi PFA_RSHIFT2
-0006f7 9596 lsr tosh
-0006f8 9587 ror tosl
-0006f9 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-0006fa ca24 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-0006fb ff02 .dw $ff02
-0006fc 212b .db "+!"
-0006fd 06ec .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-0006fe 06ff .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-0006ff 01fc movw zl, tosl
-000700 9189
-000701 9199 loadtos
-000702 8120 ldd temp2, Z+0
-000703 8131 ldd temp3, Z+1
-000704 0f82 add tosl, temp2
-000705 1f93 adc tosh, temp3
-000706 8380 std Z+0, tosl
-000707 8391 std Z+1, tosh
-000708 9189
-000709 9199 loadtos
-00070a ca14 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-00070b ff03 .dw $ff03
-00070c 7072
-00070d 0040 .db "rp@",0
-00070e 06fb .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-00070f 0710 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-000710 939a
-000711 938a savetos
-000712 b78d in tosl, SPL
-000713 b79e in tosh, SPH
-000714 ca0a jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-000715 ff03 .dw $ff03
-000716 7072
-000717 0021 .db "rp!",0
-000718 070b .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-000719 071a .dw PFA_RP_STORE
- PFA_RP_STORE:
-00071a b72f in temp2, SREG
-00071b 94f8 cli
-00071c bf8d out SPL, tosl
-00071d bf9e out SPH, tosh
-00071e bf2f out SREG, temp2
-00071f 9189
-000720 9199 loadtos
-000721 c9fd jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-000722 ff03 .dw $ff03
-000723 7073
-000724 0040 .db "sp@",0
-000725 0715 .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-000726 0727 .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-000727 939a
-000728 938a savetos
-000729 01ce movw tosl, yl
-00072a c9f4 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-00072b ff03 .dw $ff03
-00072c 7073
-00072d 0021 .db "sp!",0
-00072e 0722 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-00072f 0730 .dw PFA_SP_STORE
- PFA_SP_STORE:
-000730 01ec movw yl, tosl
-000731 9189
-000732 9199 loadtos
-000733 c9eb jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-000734 0735 .dw PFA_DODO
- PFA_DODO:
-000735 9129 ld temp2, Y+
-000736 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-000737 e8e0 ldi zl, $80
-000738 0f3e add temp3, zl
-000739 1b82 sub tosl, temp2
-00073a 0b93 sbc tosh, temp3
-
-00073b 933f push temp3
-00073c 932f push temp2 ; limit ( --> limit + $8000)
-00073d 939f push tosh
-00073e 938f push tosl ; start -> index ( --> index - (limit - $8000)
-00073f 9189
-000740 9199 loadtos
-000741 c9dd jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-000742 ff01 .dw $FF01
-000743 0069 .db "i",0
-000744 072b .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-000745 0746 .dw PFA_I
- PFA_I:
-000746 939a
-000747 938a savetos
-000748 918f pop tosl
-000749 919f pop tosh ; index
-00074a 91ef pop zl
-00074b 91ff pop zh ; limit
-00074c 93ff push zh
-00074d 93ef push zl
-00074e 939f push tosh
-00074f 938f push tosl
-000750 0f8e add tosl, zl
-000751 1f9f adc tosh, zh
-000752 c9cc jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-000753 0754 .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-000754 91ef pop zl
-000755 91ff pop zh
-000756 0fe8 add zl, tosl
-000757 1ff9 adc zh, tosh
-000758 9189
-000759 9199 loadtos
-00075a f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-00075b 93ff push zh
-00075c 93ef push zl
-00075d cd60 rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-00075e 910f pop temp0
-00075f 911f pop temp1 ; remove limit
-000760 9611 adiw xl, 1 ; skip branch-back address
-000761 c9bd jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-000762 0763 .dw PFA_DOLOOP
- PFA_DOLOOP:
-000763 91ef pop zl
-000764 91ff pop zh
-000765 9631 adiw zl,1
-000766 f3bb brvs PFA_DOPLUSLOOP_LEAVE
-000767 cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-000768 ff06 .dw $ff06
-000769 6e75
-00076a 6f6c
-00076b 706f .db "unloop"
-00076c 0742 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-00076d 076e .dw PFA_UNLOOP
- PFA_UNLOOP:
-00076e 911f pop temp1
-00076f 910f pop temp0
-000770 911f pop temp1
-000771 910f pop temp0
-000772 c9ac jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-000773 ff06 .dw $ff06
-000774 6d63
-000775 766f
-000776 3e65 .db "cmove>"
-000777 0768 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-000778 0779 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-000779 93bf push xh
-00077a 93af push xl
-00077b 91e9 ld zl, Y+
-00077c 91f9 ld zh, Y+ ; addr-to
-00077d 91a9 ld xl, Y+
-00077e 91b9 ld xh, Y+ ; addr-from
-00077f 2f09 mov temp0, tosh
-000780 2b08 or temp0, tosl
-000781 f041 brbs 1, PFA_CMOVE_G1
-000782 0fe8 add zl, tosl
-000783 1ff9 adc zh, tosh
-000784 0fa8 add xl, tosl
-000785 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-000786 911e ld temp1, -X
-000787 9312 st -Z, temp1
-000788 9701 sbiw tosl, 1
-000789 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-00078a 91af pop xl
-00078b 91bf pop xh
-00078c 9189
-00078d 9199 loadtos
-00078e c990 jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-00078f ff02 .dw $ff02
-000790 3c3e .db "><"
-000791 0773 .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-000792 0793 .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-000793 2f09 mov temp0, tosh
-000794 2f98 mov tosh, tosl
-000795 2f80 mov tosl, temp0
-000796 c988 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-000797 ff03 .dw $ff03
-000798 7075
-000799 0040 .db "up@",0
-00079a 078f .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-00079b 079c .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-00079c 939a
-00079d 938a savetos
-00079e 01c2 movw tosl, upl
-00079f c97f jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-0007a0 ff03 .dw $ff03
-0007a1 7075
-0007a2 0021 .db "up!",0
-0007a3 0797 .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-0007a4 07a5 .dw PFA_UP_STORE
- PFA_UP_STORE:
-0007a5 012c movw upl, tosl
-0007a6 9189
-0007a7 9199 loadtos
-0007a8 c976 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-0007a9 ff03 .dw $ff03
-0007aa 6d31
-0007ab 0073 .db "1ms",0
-0007ac 07a0 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-0007ad 07ae .dw PFA_1MS
- PFA_1MS:
-0007ae e6e6
-0007af e0fe
-0007b0 9731
-0007b1 f7f1
-0007b2 0000 delay 1000
-0007b3 c96b jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-0007b4 ff03 .dw $ff03
-0007b5 3e32
-0007b6 0072 .db "2>r",0
-0007b7 07a9 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-0007b8 07b9 .dw PFA_2TO_R
- PFA_2TO_R:
-0007b9 01fc movw zl, tosl
-0007ba 9189
-0007bb 9199 loadtos
-0007bc 939f push tosh
-0007bd 938f push tosl
-0007be 93ff push zh
-0007bf 93ef push zl
-0007c0 9189
-0007c1 9199 loadtos
-0007c2 c95c jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-0007c3 ff03 .dw $ff03
-0007c4 7232
-0007c5 003e .db "2r>",0
-0007c6 07b4 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-0007c7 07c8 .dw PFA_2R_FROM
- PFA_2R_FROM:
-0007c8 939a
-0007c9 938a savetos
-0007ca 91ef pop zl
-0007cb 91ff pop zh
-0007cc 918f pop tosl
-0007cd 919f pop tosh
-0007ce 939a
-0007cf 938a savetos
-0007d0 01cf movw tosl, zl
-0007d1 c94d jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-0007d2 ff02 .dw $ff02
-0007d3 6521 .db "!e"
-0007d4 07c3 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-0007d5 07d6 .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-0007d6 01fc movw zl, tosl
-0007d7 9189
-0007d8 9199 loadtos
-0007d9 b72f in_ temp2, SREG
-0007da 94f8 cli
-0007db d028 rcall PFA_FETCHE2
-0007dc b500 in_ temp0, EEDR
-0007dd 1708 cp temp0,tosl
-0007de f009 breq PFA_STOREE3
-0007df d00b rcall PFA_STOREE1
- PFA_STOREE3:
-0007e0 9631 adiw zl,1
-0007e1 d022 rcall PFA_FETCHE2
-0007e2 b500 in_ temp0, EEDR
-0007e3 1709 cp temp0,tosh
-0007e4 f011 breq PFA_STOREE4
-0007e5 2f89 mov tosl, tosh
-0007e6 d004 rcall PFA_STOREE1
- PFA_STOREE4:
-0007e7 bf2f out_ SREG, temp2
-0007e8 9189
-0007e9 9199 loadtos
-0007ea c934 jmp_ DO_NEXT
-
- PFA_STOREE1:
-0007eb 99f9 sbic EECR, EEPE
-0007ec cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-0007ed b707 in_ temp0, SPMCSR
-0007ee fd00 sbrc temp0,SPMEN
-0007ef cffd rjmp PFA_STOREE2
-
-0007f0 bdf2 out_ EEARH,zh
-0007f1 bde1 out_ EEARL,zl
-0007f2 bd80 out_ EEDR, tosl
-0007f3 9afa sbi EECR,EEMPE
-0007f4 9af9 sbi EECR,EEPE
-
-0007f5 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-0007f6 ff02 .dw $ff02
-0007f7 6540 .db "@e"
-0007f8 07d2 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-0007f9 07fa .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-0007fa b72f in_ temp2, SREG
-0007fb 94f8 cli
-0007fc 01fc movw zl, tosl
-0007fd d006 rcall PFA_FETCHE2
-0007fe b580 in_ tosl, EEDR
-
-0007ff 9631 adiw zl,1
-
-000800 d003 rcall PFA_FETCHE2
-000801 b590 in_ tosh, EEDR
-000802 bf2f out_ SREG, temp2
-000803 c91b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-000804 99f9 sbic EECR, EEPE
-000805 cffe rjmp PFA_FETCHE2
-
-000806 bdf2 out_ EEARH,zh
-000807 bde1 out_ EEARL,zl
-
-000808 9af8 sbi EECR,EERE
-000809 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-00080a ff02 .dw $ff02
-00080b 6921 .db "!i"
-00080c 07f6 .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-00080d 1079 .dw PFA_DODEFER1
- PFA_STOREI:
-00080e 00a4 .dw EE_STOREI
-00080f 101a .dw XT_EDEFERFETCH
-000810 1024 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .include "words/store-i_big.asm"
-
- ; R( -- )
- ; writes a cell in flash
- VE_DO_STOREI_BIG:
-000811 ff04 .dw $ff04
-000812 6928
-000813 2921 .db "(i!)"
-000814 080a .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_BIG
- XT_DO_STOREI:
-000815 0816 .dw PFA_DO_STOREI_BIG
- PFA_DO_STOREI_BIG:
-000816 019c movw temp2, tosl ; save the (word) address
-000817 9189
-000818 9199 loadtos ; get the new value for the flash cell
-000819 93af push xl
-00081a 93bf push xh
-00081b 93cf push yl
-00081c 93df push yh
-00081d e0e1 ldi zl, byte3(DO_STOREI_atmega)
-00081e bfeb out_ rampz, zl
-00081f eff0 ldi zh, byte2(DO_STOREI_atmega)
-000820 e0e0 ldi zl, byte1(DO_STOREI_atmega)
-000821 9519 eicall
-000822 91df pop yh
-000823 91cf pop yl
-000824 91bf pop xh
-000825 91af pop xl
- ; finally clear the stack
-000826 9189
-000827 9199 loadtos
-000828 c8f6 jmp_ DO_NEXT
-
- ;
- .set _pc = pc
- .org NRWW_START_ADDR
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-01f000 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-01f001 94e0 com temp4
-01f002 94f0 com temp5
-01f003 218e and tosl, temp4
-01f004 219f and tosh, temp5
-01f005 2b98 or tosh, tosl
-01f006 f019 breq DO_STOREI_writepage
-
-01f007 01f9 movw zl, temp2
-01f008 e003 ldi temp0,(1<<PGERS|1<<SPMEN)
-01f009 d023 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-01f00a 01f9 movw zl, temp2
-01f00b e005 ldi temp0,(1<<PGWRT|1<<SPMEN)
-01f00c d020 rcall dospm
-
- ; reenable RWW section
-01f00d 01f9 movw zl, temp2
-01f00e e101 ldi temp0,(1<<RWWSRE|1<<SPMEN)
-01f00f d01d rcall dospm
-01f010 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-01f011 01f9 movw zl, temp2
- ; get the beginning of page
-01f012 78e0 andi zl,low(pagemask)
-01f013 7fff andi zh,high(pagemask)
-01f014 01ef movw y, z
- ; loop counter (in words)
-01f015 e8a0 ldi xl,low(pagesize)
-01f016 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-01f017 01fe movw z, y
-01f018 2755
-01f019 0fee
-01f01a 1fff
-01f01b 1f55
-01f01c bf5b
-01f01d 9147
-01f01e 9157 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-01f01f 01fe movw z, y
-01f020 17e2 cp zl, temp2
-01f021 07f3 cpc zh, temp3
-01f022 f011 breq pageload_newdata
-01f023 010a movw r0, temp6
-01f024 c002 rjmp pageload_cont
- pageload_newdata:
-01f025 017a movw temp4, temp6
-01f026 010c movw r0, tosl
- pageload_cont:
-01f027 e001 ldi temp0,(1<<SPMEN)
-01f028 d004 rcall dospm
-01f029 9621 adiw y, 1
-01f02a 9711 sbiw x, 1
-01f02b f759 brne pageload_loop
-
- pageload_done:
-01f02c 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- ; store status register
-01f02d b71f in temp1,SREG
-01f02e 931f push temp1
-01f02f 94f8 cli
- Wait_ee:
-01f030 99f9 sbic EECR, EEPE
-01f031 cffe rjmp Wait_ee
- wait_spm:
-01f032 b717 in temp1, SPMCSR
-01f033 fd10 sbrc temp1, SPMEN
-01f034 cffd rjmp Wait_spm
-
- ; turn the word addres into a byte address
-01f035 2755
-01f036 0fee
-01f037 1fff
-01f038 1f55
-01f039 bf5b writeflashcell
- ; execute spm
-01f03a bf07 out SPMCSR,temp0
-01f03b 95e8 spm
-01f03c 911f pop temp1
- ; restore status register
-01f03d bf1f out SREG,temp1
-01f03e 9508 ret
-
- .org _pc
- .else
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-000829 ff02 .dw $ff02
-00082a 6940 .db "@i"
-00082b 0811 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-00082c 082d .dw PFA_FETCHI
- PFA_FETCHI:
-00082d 01fc movw zl, tosl
-00082e 2755
-00082f 0fee
-000830 1fff
-000831 1f55
-000832 bf5b
-000833 9187
-000834 9197 readflashcell tosl,tosh
-000835 c8e9 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .include "dict/core_8k.inc"
-
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-000836 ff03 .dw $ff03
-000837 3e6e
-000838 0072 .db "n>r",0
-000839 0829 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-00083a 083b .dw PFA_N_TO_R
- PFA_N_TO_R:
-00083b 01fc movw zl, tosl
-00083c 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-00083d 9189
-00083e 9199 loadtos
-00083f 939f push tosh
-000840 938f push tosl
-000841 950a dec temp0
-000842 f7d1 brne PFA_N_TO_R1
-000843 93ef push zl
-000844 93ff push zh
-000845 9189
-000846 9199 loadtos
-000847 c8d7 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-000848 ff03 .dw $ff03
-000849 726e
-00084a 003e .db "nr>",0
-00084b 0836 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-00084c 084d .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-00084d 939a
-00084e 938a savetos
-00084f 91ff pop zh
-000850 91ef pop zl
-000851 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-000852 918f pop tosl
-000853 919f pop tosh
-000854 939a
-000855 938a savetos
-000856 950a dec temp0
-000857 f7d1 brne PFA_N_R_FROM1
-000858 01cf movw tosl, zl
-000859 c8c5 jmp_ DO_NEXT
-
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-00085a ff03 .dw $ff03
-00085b 3264
-00085c 002a .db "d2*",0
-00085d 0848 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-00085e 085f .dw PFA_D2STAR
- PFA_D2STAR:
-00085f 9109 ld temp0, Y+
-000860 9119 ld temp1, Y+
-000861 0f00 lsl temp0
-000862 1f11 rol temp1
-000863 1f88 rol tosl
-000864 1f99 rol tosh
-000865 931a st -Y, temp1
-000866 930a st -Y, temp0
-000867 c8b7 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-000868 ff03 .dw $ff03
-000869 3264
-00086a 002f .db "d2/",0
-00086b 085a .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-00086c 086d .dw PFA_D2SLASH
- PFA_D2SLASH:
-00086d 9109 ld temp0, Y+
-00086e 9119 ld temp1, Y+
-00086f 9595 asr tosh
-000870 9587 ror tosl
-000871 9517 ror temp1
-000872 9507 ror temp0
-000873 931a st -Y, temp1
-000874 930a st -Y, temp0
-000875 c8a9 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-000876 ff02 .dw $ff02
-000877 2b64 .db "d+"
-000878 0868 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-000879 087a .dw PFA_DPLUS
- PFA_DPLUS:
-00087a 9129 ld temp2, Y+
-00087b 9139 ld temp3, Y+
-
-00087c 90e9 ld temp4, Y+
-00087d 90f9 ld temp5, Y+
-00087e 9149 ld temp6, Y+
-00087f 9159 ld temp7, Y+
-
-000880 0f24 add temp2, temp6
-000881 1f35 adc temp3, temp7
-000882 1d8e adc tosl, temp4
-000883 1d9f adc tosh, temp5
-
-000884 933a st -Y, temp3
-000885 932a st -Y, temp2
-000886 c898 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-000887 ff02 .dw $ff02
-000888 2d64 .db "d-"
-000889 0876 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-00088a 088b .dw PFA_DMINUS
- PFA_DMINUS:
-00088b 9129 ld temp2, Y+
-00088c 9139 ld temp3, Y+
-
-00088d 90e9 ld temp4, Y+
-00088e 90f9 ld temp5, Y+
-00088f 9149 ld temp6, Y+
-000890 9159 ld temp7, Y+
-
-000891 1b42 sub temp6, temp2
-000892 0b53 sbc temp7, temp3
-000893 0ae8 sbc temp4, tosl
-000894 0af9 sbc temp5, tosh
-
-000895 935a st -Y, temp7
-000896 934a st -Y, temp6
-000897 01c7 movw tosl, temp4
-000898 c886 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-000899 ff07 .dw $ff07
-00089a 6964
-00089b 766e
-00089c 7265
-00089d 0074 .db "dinvert",0
-00089e 0887 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-00089f 08a0 .dw PFA_DINVERT
- PFA_DINVERT:
-0008a0 9109 ld temp0, Y+
-0008a1 9119 ld temp1, Y+
-0008a2 9580 com tosl
-0008a3 9590 com tosh
-0008a4 9500 com temp0
-0008a5 9510 com temp1
-0008a6 931a st -Y, temp1
-0008a7 930a st -Y, temp0
-0008a8 c876 jmp_ DO_NEXT
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-0008a9 ff02 .dw $ff02
-0008aa 2e75 .db "u."
-0008ab 0899 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-0008ac 011b .dw DO_COLON
- PFA_UDOT:
- .endif
-0008ad 05ed .dw XT_ZERO
-0008ae 0b90 .dw XT_UDDOT
-0008af 04ae .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-0008b0 ff03 .dw $ff03
-0008b1 2e75
-0008b2 0072 .db "u.r",0
-0008b3 08a9 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-0008b4 011b .dw DO_COLON
- PFA_UDOTR:
- .endif
-0008b5 05ed .dw XT_ZERO
-0008b6 055d .dw XT_SWAP
-0008b7 0b99 .dw XT_UDDOTR
-0008b8 04ae .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-0008b9 ff0d .dw $ff0d
-0008ba 6873
-0008bb 776f
-0008bc 772d
-0008bd 726f
-0008be 6c64
-0008bf 7369
-0008c0 0074 .db "show-wordlist",0
-0008c1 08b0 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-0008c2 011b .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-0008c3 04ce .dw XT_DOLITERAL
-0008c4 08c8 .dw XT_SHOWWORD
-0008c5 055d .dw XT_SWAP
-0008c6 10bd .dw XT_TRAVERSEWORDLIST
-0008c7 04ae .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-0008c8 011b .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-0008c9 10d8 .dw XT_NAME2STRING
-0008ca 0c06 .dw XT_ITYPE
-0008cb 0c48 .dw XT_SPACE ; ( -- addr n)
-0008cc 05e4 .dw XT_TRUE
-0008cd 04ae .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-0008ce ff05 .dw $ff05
-0008cf 6f77
-0008d0 6472
-0008d1 0073 .db "words",0
-0008d2 08b9 .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-0008d3 011b .dw DO_COLON
- PFA_WORDS:
- .endif
-0008d4 04ce .dw XT_DOLITERAL
-0008d5 008a .dw CFG_ORDERLISTLEN+2
-0008d6 07f9 .dw XT_FETCHE
-0008d7 08c2 .dw XT_SHOWWORDLIST
-0008d8 04ae .dw XT_EXIT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-0008d9 ff04 .dw $ff04
-0008da 692b
-0008db 746e .db "+int"
-0008dc 08ce .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-0008dd 08de .dw PFA_INTON
- PFA_INTON:
-0008de 9478 sei
-0008df c83f jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-0008e0 ff04 .dw $ff04
-0008e1 692d
-0008e2 746e .db "-int"
-0008e3 08d9 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-0008e4 08e5 .dw PFA_INTOFF
- PFA_INTOFF:
-0008e5 94f8 cli
-0008e6 c838 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-0008e7 ff04 .dw $ff04
-0008e8 6e69
-0008e9 2174 .db "int!"
-0008ea 08e0 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-0008eb 011b .dw DO_COLON
- PFA_INTSTORE:
-0008ec 04ce .dw XT_DOLITERAL
-0008ed 0000 .dw intvec
-0008ee 0636 .dw XT_PLUS
-0008ef 07d5 .dw XT_STOREE
-0008f0 04ae .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-0008f1 ff04 .dw $ff04
-0008f2 6e69
-0008f3 4074 .db "int@"
-0008f4 08e7 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-0008f5 011b .dw DO_COLON
- PFA_INTFETCH:
-0008f6 04ce .dw XT_DOLITERAL
-0008f7 0000 .dw intvec
-0008f8 0636 .dw XT_PLUS
-0008f9 07f9 .dw XT_FETCHE
-0008fa 04ae .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-0008fb ff08 .dw $ff08
-0008fc 6e69
-0008fd 2d74
-0008fe 7274
-0008ff 7061 .db "int-trap"
-000900 08f1 .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-000901 0902 .dw PFA_INTTRAP
- PFA_INTTRAP:
-000902 2eb8 mov isrflag, tosl
-000903 9189
-000904 9199 loadtos
-000905 c819 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-000906 011b .dw DO_COLON
- PFA_ISREXEC:
-000907 08f5 .dw XT_INTFETCH
-000908 04b8 .dw XT_EXECUTE
-000909 090b .dw XT_ISREND
-00090a 04ae .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-00090b 090c .dw PFA_ISREND
- PFA_ISREND:
-00090c d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-00090d c811 jmp_ DO_NEXT
- PFA_ISREND1:
-00090e 9518 reti
- .endif
-
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-00090f ff04 .dw $ff04
-000910 6970
-000911 6b63 .db "pick"
-000912 08fb .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-000913 011b .dw DO_COLON
- PFA_PICK:
- .endif
-000914 06c8 .dw XT_1PLUS
-000915 09bc .dw XT_CELLS
-000916 0726 .dw XT_SP_FETCH
-000917 0636 .dw XT_PLUS
-000918 0512 .dw XT_FETCH
-000919 04ae .dw XT_EXIT
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-00091a 0002 .dw $0002
-00091b 222e .db ".",$22
-00091c 090f .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-00091d 011b .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-00091e 0925 .dw XT_SQUOTE
-00091f 01d1 .dw XT_COMPILE
-000920 0c06 .dw XT_ITYPE
-000921 04ae .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-000922 0002 .dw $0002
-000923 2273 .db "s",$22
-000924 091a .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-000925 011b .dw DO_COLON
- PFA_SQUOTE:
- .endif
-000926 04ce .dw XT_DOLITERAL
-000927 0022 .dw 34 ; 0x22
-000928 0ded .dw XT_PARSE ; ( -- addr n)
-000929 09af .dw XT_STATE
-00092a 0512 .dw XT_FETCH
-00092b 04c7 .dw XT_DOCONDBRANCH
-00092c 092e DEST(PFA_SQUOTE1)
-00092d 01fd .dw XT_SLITERAL
- PFA_SQUOTE1:
-00092e 04ae .dw XT_EXIT
-
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-00092f ff04 .dw $ff04
-000930 6966
-000931 6c6c .db "fill"
-000932 0922 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-000933 011b .dw DO_COLON
- PFA_FILL:
-000934 057a .dw XT_ROT
-000935 057a .dw XT_ROT
-000936 0552
-000937 04c7 .dw XT_QDUP,XT_DOCONDBRANCH
-000938 0940 DEST(PFA_FILL2)
-000939 124c .dw XT_BOUNDS
-00093a 0734 .dw XT_DODO
- PFA_FILL1:
-00093b 054a .dw XT_DUP
-00093c 0745 .dw XT_I
-00093d 0526 .dw XT_CSTORE ; ( -- c c-addr)
-00093e 0762 .dw XT_DOLOOP
-00093f 093b .dw PFA_FILL1
- PFA_FILL2:
-000940 0572 .dw XT_DROP
-000941 04ae .dw XT_EXIT
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-000942 ff0b .dw $ff0b
-000943 6e65
-000944 6976
-000945 6f72
-000946 6d6e
-000947 6e65
-000948 0074 .db "environment",0
-000949 092f .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-00094a 04dc .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-00094b 0082 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00094c ff09 .dw $ff09
-00094d 6f77
-00094e 6472
-00094f 696c
-000950 7473
-000951 0073 .db "wordlists",0
-000952 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-000953 011b .dw DO_COLON
- PFA_ENVWORDLISTS:
-000954 04ce .dw XT_DOLITERAL
-000955 0008 .dw NUMWORDLISTS
-000956 04ae .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-000957 ff04 .dw $ff04
-000958 702f
-000959 6461 .db "/pad"
-00095a 094c .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-00095b 011b .dw DO_COLON
- PFA_ENVSLASHPAD:
-00095c 0726 .dw XT_SP_FETCH
-00095d 09e9 .dw XT_PAD
-00095e 062c .dw XT_MINUS
-00095f 04ae .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-000960 ff05 .dw $ff05
-000961 682f
-000962 6c6f
-000963 0064 .db "/hold",0
-000964 0957 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-000965 011b .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-000966 09e9 .dw XT_PAD
-000967 0a24 .dw XT_HERE
-000968 062c .dw XT_MINUS
-000969 04ae .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-00096a ff0a .dw $ff0a
-00096b 6f66
-00096c 7472
-00096d 2d68
-00096e 616e
-00096f 656d .db "forth-name"
-000970 0960 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-000971 011b .dw DO_COLON
- PFA_EN_FORTHNAME:
-000972 0bd3 .dw XT_DOSLITERAL
-000973 0007 .dw 7
- .endif
-000974 6d61
-000975 6f66
-000976 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-000977 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-000978 04ae .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-000979 ff07 .dw $ff07
-00097a 6576
-00097b 7372
-00097c 6f69
-00097d 006e .db "version",0
-00097e 096a .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-00097f 011b .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-000980 04ce .dw XT_DOLITERAL
-000981 0041 .dw 65
-000982 04ae .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-000983 ff03 .dw $ff03
-000984 7063
-000985 0075 .db "cpu",0
-000986 0979 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-000987 011b .dw DO_COLON
- PFA_EN_CPU:
- .endif
-000988 04ce .dw XT_DOLITERAL
-000989 0075 .dw mcu_name
-00098a 0c32 .dw XT_ICOUNT
-00098b 04ae .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-00098c ff08 .dw $ff08
-00098d 636d
-00098e 2d75
-00098f 6e69
-000990 6f66 .db "mcu-info"
-000991 0983 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-000992 011b .dw DO_COLON
- PFA_EN_MCUINFO:
-000993 04ce .dw XT_DOLITERAL
-000994 0071 .dw mcu_info
-000995 04ae .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-000996 ff05 .dw $ff05
-000997 752f
-000998 6573
-000999 0072 .db "/user",0
-00099a 098c .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-00099b 011b .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-00099c 04ce .dw XT_DOLITERAL
-00099d 002c .dw SYSUSERSIZE + APPUSERSIZE
-00099e 04ae .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-00099f ff05 .dw $ff05
-0009a0 5f66
-0009a1 7063
-0009a2 0075 .db "f_cpu",0
-0009a3 0942 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-0009a4 011b .dw DO_COLON
- PFA_F_CPU:
- .endif
-0009a5 04ce .dw XT_DOLITERAL
-0009a6 0000 .dw (F_CPU % 65536)
-0009a7 04ce .dw XT_DOLITERAL
-0009a8 00e1 .dw (F_CPU / 65536)
-0009a9 04ae .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-0009aa ff05 .dw $ff05
-0009ab 7473
-0009ac 7461
-0009ad 0065 .db "state",0
-0009ae 099f .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-0009af 04dc .dw PFA_DOVARIABLE
- PFA_STATE:
-0009b0 0253 .dw ram_state
-
- .dseg
-000253 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-0009b1 ff04 .dw $ff04
-0009b2 6162
-0009b3 6573 .db "base"
-0009b4 09aa .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-0009b5 04ef .dw PFA_DOUSER
- PFA_BASE:
- .endif
-0009b6 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-0009b7 ff05 .dw $ff05
-0009b8 6563
-0009b9 6c6c
-0009ba 0073 .db "cells",0
-0009bb 09b1 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-0009bc 06a5 .dw PFA_2STAR
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-0009bd ff05 .dw $ff05
-0009be 6563
-0009bf 6c6c
-0009c0 002b .db "cell+",0
-0009c1 09b7 .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-0009c2 09c3 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-0009c3 9602 adiw tosl, CELLSIZE
-0009c4 940c 011f jmp_ DO_NEXT
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-0009c6 ff04 .dw $ff04
-0009c7 6432
-0009c8 7075 .db "2dup"
-0009c9 09bd .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-0009ca 011b .dw DO_COLON
- PFA_2DUP:
- .endif
-
-0009cb 0568 .dw XT_OVER
-0009cc 0568 .dw XT_OVER
-0009cd 04ae .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-0009ce ff05 .dw $ff05
-0009cf 6432
-0009d0 6f72
-0009d1 0070 .db "2drop",0
-0009d2 09c6 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-0009d3 011b .dw DO_COLON
- PFA_2DROP:
- .endif
-0009d4 0572 .dw XT_DROP
-0009d5 0572 .dw XT_DROP
-0009d6 04ae .dw XT_EXIT
-
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-0009d7 ff04 .dw $ff04
-0009d8 7574
-0009d9 6b63 .db "tuck"
-0009da 09ce .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-0009db 011b .dw DO_COLON
- PFA_TUCK:
- .endif
-0009dc 055d .dw XT_SWAP
-0009dd 0568 .dw XT_OVER
-0009de 04ae .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-0009df ff03 .dw $ff03
-0009e0 693e
-0009e1 006e .db ">in",0
-0009e2 09d7 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-0009e3 04ef .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-0009e4 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-0009e5 ff03 .dw $ff03
-0009e6 6170
-0009e7 0064 .db "pad",0
-0009e8 09df .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-0009e9 011b .dw DO_COLON
- PFA_PAD:
- .endif
-0009ea 0a24 .dw XT_HERE
-0009eb 04ce .dw XT_DOLITERAL
-0009ec 0028 .dw 40
-0009ed 0636 .dw XT_PLUS
-0009ee 04ae .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-0009ef ff04 .dw $ff04
-0009f0 6d65
-0009f1 7469 .db "emit"
-0009f2 09e5 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-0009f3 1079 .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-0009f4 000e .dw USER_EMIT
-0009f5 1042 .dw XT_UDEFERFETCH
-0009f6 104e .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-0009f7 ff05 .dw $ff05
-0009f8 6d65
-0009f9 7469
-0009fa 003f .db "emit?",0
-0009fb 09ef .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-0009fc 1079 .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-0009fd 0010 .dw USER_EMITQ
-0009fe 1042 .dw XT_UDEFERFETCH
-0009ff 104e .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-000a00 ff03 .dw $ff03
-000a01 656b
-000a02 0079 .db "key",0
-000a03 09f7 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-000a04 1079 .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-000a05 0012 .dw USER_KEY
-000a06 1042 .dw XT_UDEFERFETCH
-000a07 104e .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-000a08 ff04 .dw $ff04
-000a09 656b
-000a0a 3f79 .db "key?"
-000a0b 0a00 .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-000a0c 1079 .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-000a0d 0014 .dw USER_KEYQ
-000a0e 1042 .dw XT_UDEFERFETCH
-000a0f 104e .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-000a10 ff02 .dw $ff02
-000a11 7064 .db "dp"
-000a12 0a08 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-000a13 0509 .dw PFA_DOVALUE1
- PFA_DP:
-000a14 0074 .dw CFG_DP
-000a15 101a .dw XT_EDEFERFETCH
-000a16 1024 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-000a17 ff05 .dw $ff05
-000a18 6865
-000a19 7265
-000a1a 0065 .db "ehere",0
-000a1b 0a10 .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-000a1c 0509 .dw PFA_DOVALUE1
- PFA_EHERE:
-000a1d 0078 .dw EE_EHERE
-000a1e 101a .dw XT_EDEFERFETCH
-000a1f 1024 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-000a20 ff04 .dw $ff04
-000a21 6568
-000a22 6572 .db "here"
-000a23 0a17 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-000a24 0509 .dw PFA_DOVALUE1
- PFA_HERE:
-000a25 0076 .dw EE_HERE
-000a26 101a .dw XT_EDEFERFETCH
-000a27 1024 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-000a28 ff05 .dw $ff05
-000a29 6c61
-000a2a 6f6c
-000a2b 0074 .db "allot",0
-000a2c 0a20 .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-000a2d 011b .dw DO_COLON
- PFA_ALLOT:
-000a2e 0a24 .dw XT_HERE
-000a2f 0636 .dw XT_PLUS
-000a30 0fff .dw XT_DOTO
-000a31 0a25 .dw PFA_HERE
-000a32 04ae .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-000a33 ff03 .dw $ff03
-000a34 6962
-000a35 006e .db "bin",0
-000a36 0a28 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-000a37 011b .dw DO_COLON
- PFA_BIN:
- .endif
-000a38 1279 .dw XT_TWO
-000a39 09b5 .dw XT_BASE
-000a3a 051a .dw XT_STORE
-000a3b 04ae .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-000a3c ff07 .dw $ff07
-000a3d 6564
-000a3e 6963
-000a3f 616d
-000a40 006c .db "decimal",0
-000a41 0a33 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-000a42 011b .dw DO_COLON
- PFA_DECIMAL:
- .endif
-000a43 04ce .dw XT_DOLITERAL
-000a44 000a .dw 10
-000a45 09b5 .dw XT_BASE
-000a46 051a .dw XT_STORE
-000a47 04ae .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-000a48 ff03 .dw $ff03
-000a49 6568
-000a4a 0078 .db "hex",0
-000a4b 0a3c .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-000a4c 011b .dw DO_COLON
- PFA_HEX:
- .endif
-000a4d 04ce .dw XT_DOLITERAL
-000a4e 0010 .dw 16
-000a4f 09b5 .dw XT_BASE
-000a50 051a .dw XT_STORE
-000a51 04ae .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-000a52 ff02 .dw $ff02
-000a53 6c62 .db "bl"
-000a54 0a48 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-000a55 04dc .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-000a56 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-000a57 ff07 .dw $ff07
-000a58 7574
-000a59 6e72
-000a5a 656b
-000a5b 0079 .db "turnkey",0
-000a5c 0a52 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-000a5d 1079 .dw PFA_DODEFER1
- PFA_TURNKEY:
-000a5e 0080 .dw CFG_TURNKEY
-000a5f 101a .dw XT_EDEFERFETCH
-000a60 1024 .dw XT_EDEFERSTORE
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-000a61 ff04 .dw $ff04
-000a62 6d2f
-000a63 646f .db "/mod"
-000a64 0a57 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-000a65 0a66 .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-000a66 019c movw temp2, tosl
-
-000a67 9109 ld temp0, Y+
-000a68 9119 ld temp1, Y+
-
-000a69 2f41 mov temp6,temp1 ;move dividend High to sign register
-000a6a 2743 eor temp6,temp3 ;xor divisor High with sign register
-000a6b ff17 sbrs temp1,7 ;if MSB in dividend set
-000a6c c004 rjmp PFA_SLASHMOD_1
-000a6d 9510 com temp1 ; change sign of dividend
-000a6e 9500 com temp0
-000a6f 5f0f subi temp0,low(-1)
-000a70 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-000a71 ff37 sbrs temp3,7 ;if MSB in divisor set
-000a72 c004 rjmp PFA_SLASHMOD_2
-000a73 9530 com temp3 ; change sign of divisor
-000a74 9520 com temp2
-000a75 5f2f subi temp2,low(-1)
-000a76 4f3f sbci temp3,high(-1)
-000a77 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-000a78 18ff sub temp5,temp5;clear remainder High byte and carry
-000a79 e151 ldi temp7,17 ;init loop counter
-
-000a7a 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-000a7b 1f11 rol temp1
-000a7c 955a dec temp7 ;decrement counter
-000a7d f439 brne PFA_SLASHMOD_5 ;if done
-000a7e ff47 sbrs temp6,7 ; if MSB in sign register set
-000a7f c004 rjmp PFA_SLASHMOD_4
-000a80 9510 com temp1 ; change sign of result
-000a81 9500 com temp0
-000a82 5f0f subi temp0,low(-1)
-000a83 4f1f sbci temp1,high(-1)
-000a84 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-000a85 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-000a86 1cff rol temp5
-000a87 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-000a88 0af3 sbc temp5,temp3 ;
-000a89 f420 brcc PFA_SLASHMOD_6 ;if result negative
-000a8a 0ee2 add temp4,temp2 ; restore remainder
-000a8b 1ef3 adc temp5,temp3
-000a8c 9488 clc ; clear carry to be shifted into result
-000a8d cfec rjmp PFA_SLASHMOD_3 ;else
-000a8e 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-000a8f cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-000a90 92fa st -Y,temp5
-000a91 92ea st -Y,temp4
-
- ; put quotient on stack
-000a92 01c8 movw tosl, temp0
-000a93 940c 011f jmp_ DO_NEXT
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-000a95 ff05 .dw $ff05
-000a96 2f75
-000a97 6f6d
-000a98 0064 .db "u/mod",0
-000a99 0a61 .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-000a9a 011b .dw DO_COLON
- PFA_USLASHMOD:
-000a9b 0598 .dw XT_TO_R
-000a9c 05ed .dw XT_ZERO
-000a9d 058f .dw XT_R_FROM
-000a9e 065b .dw XT_UMSLASHMOD
-000a9f 04ae .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-000aa0 ff06 .dw $ff06
-000aa1 656e
-000aa2 6167
-000aa3 6574 .db "negate"
-000aa4 0a95 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-000aa5 011b .dw DO_COLON
- PFA_NEGATE:
-000aa6 0696 .dw XT_INVERT
-000aa7 06c8 .dw XT_1PLUS
-000aa8 04ae .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-000aa9 ff01 .dw $ff01
-000aaa 002f .db "/",0
-000aab 0aa0 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-000aac 011b .dw DO_COLON
- PFA_SLASH:
- .endif
-000aad 0a65 .dw XT_SLASHMOD
-000aae 0589 .dw XT_NIP
-000aaf 04ae .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-000ab0 ff03 .dw $ff03
-000ab1 6f6d
-000ab2 0064 .db "mod",0
-000ab3 0aa9 .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-000ab4 011b .dw DO_COLON
- PFA_MOD:
- .endif
-000ab5 0a65 .dw XT_SLASHMOD
-000ab6 0572 .dw XT_DROP
-000ab7 04ae .dw XT_EXIT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-000ab8 ff03 .dw $ff03
-000ab9 6261
-000aba 0073 .db "abs",0
-000abb 0ab0 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-000abc 011b .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-000abd 054a
-000abe 06d7
-000abf 04ae .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-000ac0 ff03 .dw $ff03
-000ac1 696d
-000ac2 006e .db "min",0
-000ac3 0ab8 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-000ac4 011b .dw DO_COLON
- PFA_MIN:
- .endif
-000ac5 09ca .dw XT_2DUP
-000ac6 0611 .dw XT_GREATER
-000ac7 04c7 .dw XT_DOCONDBRANCH
-000ac8 0aca DEST(PFA_MIN1)
-000ac9 055d .dw XT_SWAP
- PFA_MIN1:
-000aca 0572 .dw XT_DROP
-000acb 04ae .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-000acc ff03 .dw $ff03
-000acd 616d
-000ace 0078 .db "max",0
-000acf 0ac0 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-000ad0 011b .dw DO_COLON
- PFA_MAX:
-
- .endif
-000ad1 09ca .dw XT_2DUP
-000ad2 0607 .dw XT_LESS
-000ad3 04c7 .dw XT_DOCONDBRANCH
-000ad4 0ad6 DEST(PFA_MAX1)
-000ad5 055d .dw XT_SWAP
- PFA_MAX1:
-000ad6 0572 .dw XT_DROP
-000ad7 04ae .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-000ad8 ff06 .dw $ff06
-000ad9 6977
-000ada 6874
-000adb 6e69 .db "within"
-000adc 0acc .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-000add 011b .dw DO_COLON
- PFA_WITHIN:
- .endif
-000ade 0568 .dw XT_OVER
-000adf 062c .dw XT_MINUS
-000ae0 0598 .dw XT_TO_R
-000ae1 062c .dw XT_MINUS
-000ae2 058f .dw XT_R_FROM
-000ae3 05f5 .dw XT_ULESS
-000ae4 04ae .dw XT_EXIT
-
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-000ae5 ff07 .dw $ff07
-000ae6 6f74
-000ae7 7075
-000ae8 6570
-000ae9 0072 .db "toupper",0
-000aea 0ad8 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-000aeb 011b .dw DO_COLON
- PFA_TOUPPER:
- .endif
-000aec 054a .dw XT_DUP
-000aed 04ce .dw XT_DOLITERAL
-000aee 0061 .dw 'a'
-000aef 04ce .dw XT_DOLITERAL
-000af0 007b .dw 'z'+1
-000af1 0add .dw XT_WITHIN
-000af2 04c7 .dw XT_DOCONDBRANCH
-000af3 0af7 DEST(PFA_TOUPPER0)
-000af4 04ce .dw XT_DOLITERAL
-000af5 00df .dw 223 ; inverse of 0x20: 0xdf
-000af6 06ac .dw XT_AND
- PFA_TOUPPER0:
-000af7 04ae .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-000af8 ff07 .dw $ff07
-000af9 6f74
-000afa 6f6c
-000afb 6577
-000afc 0072 .db "tolower",0
-000afd 0ae5 .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-000afe 011b .dw DO_COLON
- PFA_TOLOWER:
- .endif
-000aff 054a .dw XT_DUP
-000b00 04ce .dw XT_DOLITERAL
-000b01 0041 .dw 'A'
-000b02 04ce .dw XT_DOLITERAL
-000b03 005b .dw 'Z'+1
-000b04 0add .dw XT_WITHIN
-000b05 04c7 .dw XT_DOCONDBRANCH
-000b06 0b0a DEST(PFA_TOLOWER0)
-000b07 04ce .dw XT_DOLITERAL
-000b08 0020 .dw 32
-000b09 06b5 .dw XT_OR
- PFA_TOLOWER0:
-000b0a 04ae .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-000b0b ff03 .dw $ff03
-000b0c 6c68
-000b0d 0064 .db "hld",0
-000b0e 0af8 .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-000b0f 04dc .dw PFA_DOVARIABLE
- PFA_HLD:
-000b10 0255 .dw ram_hld
-
- .dseg
-000255 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-000b11 ff04 .dw $ff04
-000b12 6f68
-000b13 646c .db "hold"
-000b14 0b0b .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-000b15 011b .dw DO_COLON
- PFA_HOLD:
- .endif
-000b16 0b0f .dw XT_HLD
-000b17 054a .dw XT_DUP
-000b18 0512 .dw XT_FETCH
-000b19 06ce .dw XT_1MINUS
-000b1a 054a .dw XT_DUP
-000b1b 0598 .dw XT_TO_R
-000b1c 055d .dw XT_SWAP
-000b1d 051a .dw XT_STORE
-000b1e 058f .dw XT_R_FROM
-000b1f 0526 .dw XT_CSTORE
-000b20 04ae .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-000b21 ff02 .dw $ff02
-000b22 233c .db "<#"
-000b23 0b11 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-000b24 011b .dw DO_COLON
- PFA_L_SHARP:
- .endif
-000b25 09e9 .dw XT_PAD
-000b26 0b0f .dw XT_HLD
-000b27 051a .dw XT_STORE
-000b28 04ae .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-000b29 ff01 .dw $ff01
-000b2a 0023 .db "#",0
-000b2b 0b21 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-000b2c 011b .dw DO_COLON
- PFA_SHARP:
- .endif
-000b2d 09b5 .dw XT_BASE
-000b2e 0512 .dw XT_FETCH
-000b2f 0ba9 .dw XT_UDSLASHMOD
-000b30 057a .dw XT_ROT
-000b31 04ce .dw XT_DOLITERAL
-000b32 0009 .dw 9
-000b33 0568 .dw XT_OVER
-000b34 0607 .dw XT_LESS
-000b35 04c7 .dw XT_DOCONDBRANCH
-000b36 0b3a DEST(PFA_SHARP1)
-000b37 04ce .dw XT_DOLITERAL
-000b38 0007 .dw 7
-000b39 0636 .dw XT_PLUS
- PFA_SHARP1:
-000b3a 04ce .dw XT_DOLITERAL
-000b3b 0030 .dw 48 ; ASCII 0
-000b3c 0636 .dw XT_PLUS
-000b3d 0b15 .dw XT_HOLD
-000b3e 04ae .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-000b3f ff02 .dw $ff02
-000b40 7323 .db "#s"
-000b41 0b29 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-000b42 011b .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000b43 0b2c .dw XT_SHARP
-000b44 09ca .dw XT_2DUP
-000b45 06b5 .dw XT_OR
-000b46 05b3 .dw XT_ZEROEQUAL
-000b47 04c7 .dw XT_DOCONDBRANCH
-000b48 0b43 DEST(NUMS1) ; PFA_SHARP_S
-000b49 04ae .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-000b4a ff02 .dw $ff02
-000b4b 3e23 .db "#>"
-000b4c 0b3f .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-000b4d 011b .dw DO_COLON
- PFA_SHARP_G:
- .endif
-000b4e 09d3 .dw XT_2DROP
-000b4f 0b0f .dw XT_HLD
-000b50 0512 .dw XT_FETCH
-000b51 09e9 .dw XT_PAD
-000b52 0568 .dw XT_OVER
-000b53 062c .dw XT_MINUS
-000b54 04ae .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000b55 ff04 .dw $ff04
-000b56 6973
-000b57 6e67 .db "sign"
-000b58 0b4a .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-000b59 011b .dw DO_COLON
- PFA_SIGN:
- .endif
-000b5a 05ba .dw XT_ZEROLESS
-000b5b 04c7 .dw XT_DOCONDBRANCH
-000b5c 0b60 DEST(PFA_SIGN1)
-000b5d 04ce .dw XT_DOLITERAL
-000b5e 002d .dw 45 ; ascii -
-000b5f 0b15 .dw XT_HOLD
- PFA_SIGN1:
-000b60 04ae .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-000b61 ff03 .dw $ff03
-000b62 2e64
-000b63 0072 .db "d.r",0
-000b64 0b55 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000b65 011b .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-000b66 0598 .dw XT_TO_R
-000b67 09db .dw XT_TUCK
-000b68 113a .dw XT_DABS
-000b69 0b24 .dw XT_L_SHARP
-000b6a 0b42 .dw XT_SHARP_S
-000b6b 057a .dw XT_ROT
-000b6c 0b59 .dw XT_SIGN
-000b6d 0b4d .dw XT_SHARP_G
-000b6e 058f .dw XT_R_FROM
-000b6f 0568 .dw XT_OVER
-000b70 062c .dw XT_MINUS
-000b71 0c51 .dw XT_SPACES
-000b72 0c61 .dw XT_TYPE
-000b73 04ae .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000b74 ff02 .dw $ff02
-000b75 722e .db ".r"
-000b76 0b61 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-000b77 011b .dw DO_COLON
- PFA_DOTR:
-
- .endif
-000b78 0598 .dw XT_TO_R
-000b79 1255 .dw XT_S2D
-000b7a 058f .dw XT_R_FROM
-000b7b 0b65 .dw XT_DDOTR
-000b7c 04ae .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-000b7d ff02 .dw $ff02
-000b7e 2e64 .db "d."
-000b7f 0b74 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-000b80 011b .dw DO_COLON
- PFA_DDOT:
-
- .endif
-000b81 05ed .dw XT_ZERO
-000b82 0b65 .dw XT_DDOTR
-000b83 0c48 .dw XT_SPACE
-000b84 04ae .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-000b85 ff01 .dw $ff01
-000b86 002e .db ".",0
-000b87 0b7d .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-000b88 011b .dw DO_COLON
- PFA_DOT:
- .endif
-000b89 1255 .dw XT_S2D
-000b8a 0b80 .dw XT_DDOT
-000b8b 04ae .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-000b8c ff03 .dw $ff03
-000b8d 6475
-000b8e 002e .db "ud.",0
-000b8f 0b85 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-000b90 011b .dw DO_COLON
- PFA_UDDOT:
- .endif
-000b91 05ed .dw XT_ZERO
-000b92 0b99 .dw XT_UDDOTR
-000b93 0c48 .dw XT_SPACE
-000b94 04ae .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-000b95 ff04 .dw $ff04
-000b96 6475
-000b97 722e .db "ud.r"
-000b98 0b8c .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-000b99 011b .dw DO_COLON
- PFA_UDDOTR:
- .endif
-000b9a 0598 .dw XT_TO_R
-000b9b 0b24 .dw XT_L_SHARP
-000b9c 0b42 .dw XT_SHARP_S
-000b9d 0b4d .dw XT_SHARP_G
-000b9e 058f .dw XT_R_FROM
-000b9f 0568 .dw XT_OVER
-000ba0 062c .dw XT_MINUS
-000ba1 0c51 .dw XT_SPACES
-000ba2 0c61 .dw XT_TYPE
-000ba3 04ae .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-000ba4 ff06 .dw $ff06
-000ba5 6475
-000ba6 6d2f
-000ba7 646f .db "ud/mod"
-000ba8 0b95 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-000ba9 011b .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-000baa 0598 .dw XT_TO_R
-000bab 05ed .dw XT_ZERO
-000bac 05a1 .dw XT_R_FETCH
-000bad 065b .dw XT_UMSLASHMOD
-000bae 058f .dw XT_R_FROM
-000baf 055d .dw XT_SWAP
-000bb0 0598 .dw XT_TO_R
-000bb1 065b .dw XT_UMSLASHMOD
-000bb2 058f .dw XT_R_FROM
-000bb3 04ae .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-000bb4 ff06 .dw $ff06
-000bb5 6964
-000bb6 6967
-000bb7 3f74 .db "digit?"
-000bb8 0ba4 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-000bb9 011b .dw DO_COLON
- PFA_DIGITQ:
- .endif
-000bba 0aeb .dw XT_TOUPPER
-000bbb 054a
-000bbc 04ce
-000bbd 0039
-000bbe 0611
-000bbf 04ce
-000bc0 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-000bc1 06ac
-000bc2 0636
-000bc3 054a
-000bc4 04ce
-000bc5 0140
-000bc6 0611 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-000bc7 04ce
-000bc8 0107
-000bc9 06ac
-000bca 062c
-000bcb 04ce
-000bcc 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-000bcd 062c
-000bce 054a
-000bcf 09b5
-000bd0 0512
-000bd1 05f5 .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-000bd2 04ae .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-000bd3 011b .dw DO_COLON
- PFA_DOSLITERAL:
-000bd4 05a1 .dw XT_R_FETCH ; ( -- addr )
-000bd5 0c32 .dw XT_ICOUNT
-000bd6 058f .dw XT_R_FROM
-000bd7 0568 .dw XT_OVER ; ( -- addr' n addr n)
-000bd8 06c8 .dw XT_1PLUS
-000bd9 069d .dw XT_2SLASH ; ( -- addr' n addr k )
-000bda 0636 .dw XT_PLUS ; ( -- addr' n addr'' )
-000bdb 06c8 .dw XT_1PLUS
-000bdc 0598 .dw XT_TO_R ; ( -- )
-000bdd 04ae .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-000bde ff02 .dw $ff02
-000bdf 2c73 .db "s",$2c
-000be0 0bb4 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-000be1 011b .dw DO_COLON
- PFA_SCOMMA:
-000be2 054a .dw XT_DUP
-000be3 0be5 .dw XT_DOSCOMMA
-000be4 04ae .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-000be5 011b .dw DO_COLON
- PFA_DOSCOMMA:
-000be6 01dc .dw XT_COMMA
-000be7 054a .dw XT_DUP ; ( --addr len len)
-000be8 069d .dw XT_2SLASH ; ( -- addr len len/2
-000be9 09db .dw XT_TUCK ; ( -- addr len/2 len len/2
-000bea 06a4 .dw XT_2STAR ; ( -- addr len/2 len len'
-000beb 062c .dw XT_MINUS ; ( -- addr len/2 rem
-000bec 0598 .dw XT_TO_R
-000bed 05ed .dw XT_ZERO
-000bee 029b .dw XT_QDOCHECK
-000bef 04c7 .dw XT_DOCONDBRANCH
-000bf0 0bf8 .dw PFA_SCOMMA2
-000bf1 0734 .dw XT_DODO
- PFA_SCOMMA1:
-000bf2 054a .dw XT_DUP ; ( -- addr addr )
-000bf3 0512 .dw XT_FETCH ; ( -- addr c1c2 )
-000bf4 01dc .dw XT_COMMA ; ( -- addr )
-000bf5 09c2 .dw XT_CELLPLUS ; ( -- addr+cell )
-000bf6 0762 .dw XT_DOLOOP
-000bf7 0bf2 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-000bf8 058f .dw XT_R_FROM
-000bf9 05c1 .dw XT_GREATERZERO
-000bfa 04c7 .dw XT_DOCONDBRANCH
-000bfb 0bff .dw PFA_SCOMMA3
-000bfc 054a .dw XT_DUP ; well, tricky
-000bfd 0531 .dw XT_CFETCH
-000bfe 01dc .dw XT_COMMA
- PFA_SCOMMA3:
-000bff 0572 .dw XT_DROP ; ( -- )
-000c00 04ae .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-000c01 ff05 .dw $ff05
-000c02 7469
-000c03 7079
-000c04 0065 .db "itype",0
-000c05 0bde .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-000c06 011b .dw DO_COLON
- PFA_ITYPE:
-000c07 054a .dw XT_DUP ; ( --addr len len)
-000c08 069d .dw XT_2SLASH ; ( -- addr len len/2
-000c09 09db .dw XT_TUCK ; ( -- addr len/2 len len/2
-000c0a 06a4 .dw XT_2STAR ; ( -- addr len/2 len len'
-000c0b 062c .dw XT_MINUS ; ( -- addr len/2 rem
-000c0c 0598 .dw XT_TO_R
-000c0d 05ed .dw XT_ZERO
-000c0e 029b .dw XT_QDOCHECK
-000c0f 04c7 .dw XT_DOCONDBRANCH
-000c10 0c1a .dw PFA_ITYPE2
-000c11 0734 .dw XT_DODO
- PFA_ITYPE1:
-000c12 054a .dw XT_DUP ; ( -- addr addr )
-000c13 082c .dw XT_FETCHI ; ( -- addr c1c2 )
-000c14 054a .dw XT_DUP
-000c15 0c27 .dw XT_LOWEMIT
-000c16 0c23 .dw XT_HIEMIT
-000c17 06c8 .dw XT_1PLUS ; ( -- addr+cell )
-000c18 0762 .dw XT_DOLOOP
-000c19 0c12 .dw PFA_ITYPE1
- PFA_ITYPE2:
-000c1a 058f .dw XT_R_FROM
-000c1b 05c1 .dw XT_GREATERZERO
-000c1c 04c7 .dw XT_DOCONDBRANCH
-000c1d 0c21 .dw PFA_ITYPE3
-000c1e 054a .dw XT_DUP ; make sure the drop below has always something to do
-000c1f 082c .dw XT_FETCHI
-000c20 0c27 .dw XT_LOWEMIT
- PFA_ITYPE3:
-000c21 0572 .dw XT_DROP
-000c22 04ae .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-000c23 011b .dw DO_COLON
- PFA_HIEMIT:
-000c24 0792 .dw XT_BYTESWAP
-000c25 0c27 .dw XT_LOWEMIT
-000c26 04ae .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-000c27 011b .dw DO_COLON
- PFA_LOWEMIT:
-000c28 04ce .dw XT_DOLITERAL
-000c29 00ff .dw $00ff
-000c2a 06ac .dw XT_AND
-000c2b 09f3 .dw XT_EMIT
-000c2c 04ae .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-000c2d ff06 .dw $ff06
-000c2e 6369
-000c2f 756f
-000c30 746e .db "icount"
-000c31 0c01 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-000c32 011b .dw DO_COLON
- PFA_ICOUNT:
-000c33 054a .dw XT_DUP
-000c34 06c8 .dw XT_1PLUS
-000c35 055d .dw XT_SWAP
-000c36 082c .dw XT_FETCHI
-000c37 04ae .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-000c38 ff02 .dw 0xff02
-000c39 7263 .db "cr"
-000c3a 0c2d .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-000c3b 011b .dw DO_COLON
- PFA_CR:
- .endif
-
-000c3c 04ce .dw XT_DOLITERAL
-000c3d 000d .dw 13
-000c3e 09f3 .dw XT_EMIT
-000c3f 04ce .dw XT_DOLITERAL
-000c40 000a .dw 10
-000c41 09f3 .dw XT_EMIT
-000c42 04ae .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-000c43 ff05 .dw $ff05
-000c44 7073
-000c45 6361
-000c46 0065 .db "space",0
-000c47 0c38 .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-000c48 011b .dw DO_COLON
- PFA_SPACE:
- .endif
-000c49 0a55 .dw XT_BL
-000c4a 09f3 .dw XT_EMIT
-000c4b 04ae .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-000c4c ff06 .dw $ff06
-000c4d 7073
-000c4e 6361
-000c4f 7365 .db "spaces"
-000c50 0c43 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-000c51 011b .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-000c52 05ed
-000c53 0ad0 .DW XT_ZERO, XT_MAX
-000c54 054a
-000c55 04c7 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-000c56 0c5b DEST(SPCS2)
-000c57 0c48
-000c58 06ce
-000c59 04bd .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-000c5a 0c54 DEST(SPCS1)
-000c5b 0572
-000c5c 04ae SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-000c5d ff04 .dw $ff04
-000c5e 7974
-000c5f 6570 .db "type"
-000c60 0c4c .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-000c61 011b .dw DO_COLON
- PFA_TYPE:
-
- .endif
-000c62 124c .dw XT_BOUNDS
-000c63 029b .dw XT_QDOCHECK
-000c64 04c7 .dw XT_DOCONDBRANCH
-000c65 0c6c DEST(PFA_TYPE2)
-000c66 0734 .dw XT_DODO
- PFA_TYPE1:
-000c67 0745 .dw XT_I
-000c68 0531 .dw XT_CFETCH
-000c69 09f3 .dw XT_EMIT
-000c6a 0762 .dw XT_DOLOOP
-000c6b 0c67 DEST(PFA_TYPE1)
- PFA_TYPE2:
-000c6c 04ae .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-000c6d ff01 .dw $ff01
-000c6e 0027 .db "'",0
-000c6f 0c5d .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-000c70 011b .dw DO_COLON
- PFA_TICK:
- .endif
-000c71 0e1a .dw XT_PARSENAME
-000c72 0f32 .dw XT_FORTHRECOGNIZER
-000c73 0f3d .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-000c74 054a .dw XT_DUP
-000c75 0fb0 .dw XT_DT_NULL
-000c76 126d .dw XT_EQUAL
-000c77 055d .dw XT_SWAP
-000c78 082c .dw XT_FETCHI
-000c79 04ce .dw XT_DOLITERAL
-000c7a 0fe5 .dw XT_NOOP
-000c7b 126d .dw XT_EQUAL
-000c7c 06b5 .dw XT_OR
-000c7d 04c7 .dw XT_DOCONDBRANCH
-000c7e 0c82 DEST(PFA_TICK1)
-000c7f 04ce .dw XT_DOLITERAL
-000c80 fff3 .dw -13
-000c81 0ca7 .dw XT_THROW
- PFA_TICK1:
-000c82 0572 .dw XT_DROP
-000c83 04ae .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-000c84 ff07 .dw $ff07
-000c85 6168
-000c86 646e
-000c87 656c
-000c88 0072 .db "handler",0
-000c89 0c6d .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-000c8a 04ef .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-000c8b 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-000c8c ff05 .dw $ff05
-000c8d 6163
-000c8e 6374
-000c8f 0068 .db "catch",0
-000c90 0c84 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-000c91 011b .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-000c92 0726 .dw XT_SP_FETCH
-000c93 0598 .dw XT_TO_R
- ; handler @ >r
-000c94 0c8a .dw XT_HANDLER
-000c95 0512 .dw XT_FETCH
-000c96 0598 .dw XT_TO_R
- ; rp@ handler !
-000c97 070f .dw XT_RP_FETCH
-000c98 0c8a .dw XT_HANDLER
-000c99 051a .dw XT_STORE
-000c9a 04b8 .dw XT_EXECUTE
- ; r> handler !
-000c9b 058f .dw XT_R_FROM
-000c9c 0c8a .dw XT_HANDLER
-000c9d 051a .dw XT_STORE
-000c9e 058f .dw XT_R_FROM
-000c9f 0572 .dw XT_DROP
-000ca0 05ed .dw XT_ZERO
-000ca1 04ae .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-000ca2 ff05 .dw $ff05
-000ca3 6874
-000ca4 6f72
-000ca5 0077 .db "throw",0
-000ca6 0c8c .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-000ca7 011b .dw DO_COLON
- PFA_THROW:
- .endif
-000ca8 054a .dw XT_DUP
-000ca9 05b3 .dw XT_ZEROEQUAL
-000caa 04c7 .dw XT_DOCONDBRANCH
-000cab 0cae DEST(PFA_THROW1)
-000cac 0572 .dw XT_DROP
-000cad 04ae .dw XT_EXIT
- PFA_THROW1:
-000cae 0c8a .dw XT_HANDLER
-000caf 0512 .dw XT_FETCH
-000cb0 0719 .dw XT_RP_STORE
-000cb1 058f .dw XT_R_FROM
-000cb2 0c8a .dw XT_HANDLER
-000cb3 051a .dw XT_STORE
-000cb4 058f .dw XT_R_FROM
-000cb5 055d .dw XT_SWAP
-000cb6 0598 .dw XT_TO_R
-000cb7 072f .dw XT_SP_STORE
-000cb8 0572 .dw XT_DROP
-000cb9 058f .dw XT_R_FROM
-000cba 04ae .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-000cbb ff05 .dw $ff05
-000cbc 7363
-000cbd 696b
-000cbe 0070 .db "cskip",0
-000cbf 0ca2 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-000cc0 011b .dw DO_COLON
- PFA_CSKIP:
- .endif
-000cc1 0598 .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-000cc2 054a .dw XT_DUP ; ( -- addr' n' n' )
-000cc3 04c7 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000cc4 0ccf DEST(PFA_CSKIP2)
-000cc5 0568 .dw XT_OVER ; ( -- addr' n' addr' )
-000cc6 0531 .dw XT_CFETCH ; ( -- addr' n' c' )
-000cc7 05a1 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-000cc8 126d .dw XT_EQUAL ; ( -- addr' n' f )
-000cc9 04c7 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000cca 0ccf DEST(PFA_CSKIP2)
-000ccb 1274 .dw XT_ONE
-000ccc 0e0b .dw XT_SLASHSTRING
-000ccd 04bd .dw XT_DOBRANCH
-000cce 0cc2 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-000ccf 058f .dw XT_R_FROM
-000cd0 0572 .dw XT_DROP ; ( -- addr2 n2)
-000cd1 04ae .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-000cd2 ff05 .dw $ff05
-000cd3 7363
-000cd4 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-000cd5 006e .db "cscan"
-000cd6 0cbb .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-000cd7 011b .dw DO_COLON
- PFA_CSCAN:
- .endif
-000cd8 0598 .dw XT_TO_R
-000cd9 0568 .dw XT_OVER
- PFA_CSCAN1:
-000cda 054a .dw XT_DUP
-000cdb 0531 .dw XT_CFETCH
-000cdc 05a1 .dw XT_R_FETCH
-000cdd 126d .dw XT_EQUAL
-000cde 05b3 .dw XT_ZEROEQUAL
-000cdf 04c7 .dw XT_DOCONDBRANCH
-000ce0 0cec DEST(PFA_CSCAN2)
-000ce1 055d .dw XT_SWAP
-000ce2 06ce .dw XT_1MINUS
-000ce3 055d .dw XT_SWAP
-000ce4 0568 .dw XT_OVER
-000ce5 05ba .dw XT_ZEROLESS ; not negative
-000ce6 05b3 .dw XT_ZEROEQUAL
-000ce7 04c7 .dw XT_DOCONDBRANCH
-000ce8 0cec DEST(PFA_CSCAN2)
-000ce9 06c8 .dw XT_1PLUS
-000cea 04bd .dw XT_DOBRANCH
-000ceb 0cda DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-000cec 0589 .dw XT_NIP
-000ced 0568 .dw XT_OVER
-000cee 062c .dw XT_MINUS
-000cef 058f .dw XT_R_FROM
-000cf0 0572 .dw XT_DROP
-000cf1 04ae .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-000cf2 ff06 .dw $ff06
-000cf3 6361
-000cf4 6563
-000cf5 7470 .db "accept"
-000cf6 0cd2 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-000cf7 011b .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-000cf8 0568
-000cf9 0636
-000cfa 06ce
-000cfb 0568 .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-000cfc 0a04
-000cfd 054a
-000cfe 0d38
-000cff 05b3
-000d00 04c7 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-000d01 0d2a DEST(ACC5)
-000d02 054a
-000d03 04ce
-000d04 0008
-000d05 126d
-000d06 04c7 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-000d07 0d1a DEST(ACC3)
-000d08 0572
-000d09 057a
-000d0a 09ca
-000d0b 0611
-000d0c 0598
-000d0d 057a
-000d0e 057a
-000d0f 058f
-000d10 04c7 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-000d11 0d18 DEST(ACC6)
-000d12 0d30
-000d13 06ce
-000d14 0598
-000d15 0568
-000d16 058f
-000d17 016e .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-000d18 04bd ACC6: .DW XT_DOBRANCH
-000d19 0d28 DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-000d1a 054a .dw XT_DUP ; ( -- addr k k )
-000d1b 0a55 .dw XT_BL
-000d1c 0607 .dw XT_LESS
-000d1d 04c7 .dw XT_DOCONDBRANCH
-000d1e 0d21 DEST(PFA_ACCEPT6)
-000d1f 0572 .dw XT_DROP
-000d20 0a55 .dw XT_BL
- PFA_ACCEPT6:
-000d21 054a
-000d22 09f3
-000d23 0568
-000d24 0526
-000d25 06c8
-000d26 0568
-000d27 017a .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-000d28 04bd ACC4: .DW XT_DOBRANCH
-000d29 0cfc DEST(ACC1)
-000d2a 0572
-000d2b 0589
-000d2c 055d
-000d2d 062c
-000d2e 0c3b
-000d2f 04ae ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-000d30 011b .dw DO_COLON
- .endif
-000d31 04ce .dw XT_DOLITERAL
-000d32 0008 .dw 8
-000d33 054a .dw XT_DUP
-000d34 09f3 .dw XT_EMIT
-000d35 0c48 .dw XT_SPACE
-000d36 09f3 .dw XT_EMIT
-000d37 04ae .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-000d38 011b .dw DO_COLON
- .endif
-000d39 054a .dw XT_DUP
-000d3a 04ce .dw XT_DOLITERAL
-000d3b 000d .dw 13
-000d3c 126d .dw XT_EQUAL
-000d3d 055d .dw XT_SWAP
-000d3e 04ce .dw XT_DOLITERAL
-000d3f 000a .dw 10
-000d40 126d .dw XT_EQUAL
-000d41 06b5 .dw XT_OR
-000d42 04ae .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-000d43 ff06 .dw $ff06
-000d44 6572
-000d45 6966
-000d46 6c6c .db "refill"
-000d47 0cf2 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-000d48 1079 .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-000d49 001a .dw USER_REFILL
-000d4a 1042 .dw XT_UDEFERFETCH
-000d4b 104e .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-000d4c ff04 .dw $ff04
-000d4d 6863
-000d4e 7261 .db "char"
-000d4f 0d43 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-000d50 011b .dw DO_COLON
- PFA_CHAR:
- .endif
-000d51 0e1a .dw XT_PARSENAME
-000d52 0572 .dw XT_DROP
-000d53 0531 .dw XT_CFETCH
-000d54 04ae .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-000d55 ff06 .dw $ff06
-000d56 756e
-000d57 626d
-000d58 7265 .db "number"
-000d59 0d4c .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-000d5a 011b .dw DO_COLON
- PFA_NUMBER:
- .endif
-000d5b 09b5 .dw XT_BASE
-000d5c 0512 .dw XT_FETCH
-000d5d 0598 .dw XT_TO_R
-000d5e 0d9e .dw XT_QSIGN
-000d5f 0598 .dw XT_TO_R
-000d60 0db1 .dw XT_SET_BASE
-000d61 0d9e .dw XT_QSIGN
-000d62 058f .dw XT_R_FROM
-000d63 06b5 .dw XT_OR
-000d64 0598 .dw XT_TO_R
- ; check whether something is left
-000d65 054a .dw XT_DUP
-000d66 05b3 .dw XT_ZEROEQUAL
-000d67 04c7 .dw XT_DOCONDBRANCH
-000d68 0d71 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-000d69 09d3 .dw XT_2DROP
-000d6a 058f .dw XT_R_FROM
-000d6b 0572 .dw XT_DROP
-000d6c 058f .dw XT_R_FROM
-000d6d 09b5 .dw XT_BASE
-000d6e 051a .dw XT_STORE
-000d6f 05ed .dw XT_ZERO
-000d70 04ae .dw XT_EXIT
- PFA_NUMBER0:
-000d71 07b8 .dw XT_2TO_R
-000d72 05ed .dw XT_ZERO ; starting value
-000d73 05ed .dw XT_ZERO
-000d74 07c7 .dw XT_2R_FROM
-000d75 0dcf .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-000d76 0552 .dw XT_QDUP
-000d77 04c7 .dw XT_DOCONDBRANCH
-000d78 0d93 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-000d79 1274 .dw XT_ONE
-000d7a 126d .dw XT_EQUAL
-000d7b 04c7 .dw XT_DOCONDBRANCH
-000d7c 0d8a DEST(PFA_NUMBER2)
- ; excatly one character is left
-000d7d 0531 .dw XT_CFETCH
-000d7e 04ce .dw XT_DOLITERAL
-000d7f 002e .dw 46 ; .
-000d80 126d .dw XT_EQUAL
-000d81 04c7 .dw XT_DOCONDBRANCH
-000d82 0d8b DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-000d83 058f .dw XT_R_FROM
-000d84 04c7 .dw XT_DOCONDBRANCH
-000d85 0d87 DEST(PFA_NUMBER3)
-000d86 1147 .dw XT_DNEGATE
- PFA_NUMBER3:
-000d87 1279 .dw XT_TWO
-000d88 04bd .dw XT_DOBRANCH
-000d89 0d99 DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-000d8a 0572 .dw XT_DROP
- PFA_NUMBER6:
-000d8b 09d3 .dw XT_2DROP
-000d8c 058f .dw XT_R_FROM
-000d8d 0572 .dw XT_DROP
-000d8e 058f .dw XT_R_FROM
-000d8f 09b5 .dw XT_BASE
-000d90 051a .dw XT_STORE
-000d91 05ed .dw XT_ZERO
-000d92 04ae .dw XT_EXIT
- PFA_NUMBER1:
-000d93 09d3 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-000d94 058f .dw XT_R_FROM
-000d95 04c7 .dw XT_DOCONDBRANCH
-000d96 0d98 DEST(PFA_NUMBER4)
-000d97 0aa5 .dw XT_NEGATE
- PFA_NUMBER4:
-000d98 1274 .dw XT_ONE
- PFA_NUMBER5:
-000d99 058f .dw XT_R_FROM
-000d9a 09b5 .dw XT_BASE
-000d9b 051a .dw XT_STORE
-000d9c 05e4 .dw XT_TRUE
-000d9d 04ae .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-000d9e 011b .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-000d9f 0568 .dw XT_OVER ; ( -- addr len addr )
-000da0 0531 .dw XT_CFETCH
-000da1 04ce .dw XT_DOLITERAL
-000da2 002d .dw '-'
-000da3 126d .dw XT_EQUAL ; ( -- addr len flag )
-000da4 054a .dw XT_DUP
-000da5 0598 .dw XT_TO_R
-000da6 04c7 .dw XT_DOCONDBRANCH
-000da7 0daa DEST(PFA_NUMBERSIGN_DONE)
-000da8 1274 .dw XT_ONE ; skip sign character
-000da9 0e0b .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-000daa 058f .dw XT_R_FROM
-000dab 04ae .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-000dac 04e9 .dw PFA_DOCONSTANT
- .endif
-000dad 000a
-000dae 0010
-000daf 0002
-000db0 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-000db1 011b .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-000db2 0568 .dw XT_OVER
-000db3 0531 .dw XT_CFETCH
-000db4 04ce .dw XT_DOLITERAL
-000db5 0023 .dw 35
-000db6 062c .dw XT_MINUS
-000db7 054a .dw XT_DUP
-000db8 05ed .dw XT_ZERO
-000db9 04ce .dw XT_DOLITERAL
-000dba 0004 .dw 4
-000dbb 0add .dw XT_WITHIN
-000dbc 04c7 .dw XT_DOCONDBRANCH
-000dbd 0dc7 DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-000dbe 0dac .dw XT_BASES
-000dbf 0636 .dw XT_PLUS
-000dc0 082c .dw XT_FETCHI
-000dc1 09b5 .dw XT_BASE
-000dc2 051a .dw XT_STORE
-000dc3 1274 .dw XT_ONE
-000dc4 0e0b .dw XT_SLASHSTRING
-000dc5 04bd .dw XT_DOBRANCH
-000dc6 0dc8 DEST(SET_BASE2)
- SET_BASE1:
-000dc7 0572 .dw XT_DROP
- SET_BASE2:
-000dc8 04ae .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-000dc9 ff07 .dw $ff07
-000dca 6e3e
-000dcb 6d75
-000dcc 6562
-000dcd 0072 .db ">number",0
-000dce 0d55 .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-000dcf 011b .dw DO_COLON
-
- .endif
-
-000dd0 054a
-000dd1 04c7 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-000dd2 0de7 DEST(TONUM3)
-000dd3 0568
-000dd4 0531
-000dd5 0bb9 .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-000dd6 05b3
-000dd7 04c7 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-000dd8 0ddb DEST(TONUM2)
-000dd9 0572
-000dda 04ae .DW XT_DROP,XT_EXIT
-000ddb 0598
-000ddc 116b
-000ddd 09b5
-000dde 0512
-000ddf 015f TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000de0 058f
-000de1 0157
-000de2 116b .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-000de3 1274
-000de4 0e0b
-000de5 04bd .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-000de6 0dd0 DEST(TONUM1)
-000de7 04ae TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-000de8 ff05 .dw $ff05
-000de9 6170
-000dea 7372
-000deb 0065 .db "parse",0
-000dec 0dc9 .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-000ded 011b .dw DO_COLON
- PFA_PARSE:
- .endif
-000dee 0598 .dw XT_TO_R ; ( -- )
-000def 0e01 .dw XT_SOURCE ; ( -- addr len)
-000df0 09e3 .dw XT_TO_IN ; ( -- addr len >in)
-000df1 0512 .dw XT_FETCH
-000df2 0e0b .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-000df3 058f .dw XT_R_FROM ; ( -- addr' len' c)
-000df4 0cd7 .dw XT_CSCAN ; ( -- addr' len'')
-000df5 054a .dw XT_DUP ; ( -- addr' len'' len'')
-000df6 06c8 .dw XT_1PLUS
-000df7 09e3 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-000df8 06fe .dw XT_PLUSSTORE ; ( -- addr' len')
-000df9 1274 .dw XT_ONE
-000dfa 0e0b .dw XT_SLASHSTRING
-000dfb 04ae .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-000dfc ff06 .dw $FF06
-000dfd 6f73
-000dfe 7275
-000dff 6563 .db "source"
-000e00 0de8 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-000e01 1079 .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-000e02 0016 .dw USER_SOURCE
-000e03 1042 .dw XT_UDEFERFETCH
-000e04 104e .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-000e05 ff07 .dw $ff07
-000e06 732f
-000e07 7274
-000e08 6e69
-000e09 0067 .db "/string",0
-000e0a 0dfc .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-000e0b 011b .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-000e0c 057a .dw XT_ROT
-000e0d 0568 .dw XT_OVER
-000e0e 0636 .dw XT_PLUS
-000e0f 057a .dw XT_ROT
-000e10 057a .dw XT_ROT
-000e11 062c .dw XT_MINUS
-000e12 04ae .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-000e13 ff0a .dw $FF0A
-000e14 6170
-000e15 7372
-000e16 2d65
-000e17 616e
-000e18 656d .db "parse-name"
-000e19 0e05 .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-000e1a 011b .dw DO_COLON
- PFA_PARSENAME:
- .endif
-000e1b 0a55 .dw XT_BL
-000e1c 0e1e .dw XT_SKIPSCANCHAR
-000e1d 04ae .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-000e1e 011b .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-000e1f 0598 .dw XT_TO_R
-000e20 0e01 .dw XT_SOURCE
-000e21 09e3 .dw XT_TO_IN
-000e22 0512 .dw XT_FETCH
-000e23 0e0b .dw XT_SLASHSTRING
-
-000e24 05a1 .dw XT_R_FETCH
-000e25 0cc0 .dw XT_CSKIP
-000e26 058f .dw XT_R_FROM
-000e27 0cd7 .dw XT_CSCAN
-
- ; adjust >IN
-000e28 09ca .dw XT_2DUP
-000e29 0636 .dw XT_PLUS
-000e2a 0e01 .dw XT_SOURCE
-000e2b 0572 .dw XT_DROP
-000e2c 062c .dw XT_MINUS
-000e2d 09e3 .dw XT_TO_IN
-000e2e 051a .dw XT_STORE
-000e2f 04ae .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-000e30 ff07 .dw $ff07
-000e31 6966
-000e32 646e
-000e33 782d
-000e34 0074 .db "find-xt",0
-000e35 0e13 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-000e36 011b .dw DO_COLON
- PFA_FINDXT:
- .endif
-000e37 04ce .dw XT_DOLITERAL
-000e38 0e42 .dw XT_FINDXTA
-000e39 04ce .dw XT_DOLITERAL
-000e3a 0088 .dw CFG_ORDERLISTLEN
-000e3b 041c .dw XT_MAPSTACK
-000e3c 05b3 .dw XT_ZEROEQUAL
-000e3d 04c7 .dw XT_DOCONDBRANCH
-000e3e 0e41 DEST(PFA_FINDXT1)
-000e3f 09d3 .dw XT_2DROP
-000e40 05ed .dw XT_ZERO
- PFA_FINDXT1:
-000e41 04ae .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-000e42 011b .dw DO_COLON
- PFA_FINDXTA:
- .endif
-000e43 0598 .dw XT_TO_R
-000e44 09ca .dw XT_2DUP
-000e45 058f .dw XT_R_FROM
-000e46 108b .dw XT_SEARCH_WORDLIST
-000e47 054a .dw XT_DUP
-000e48 04c7 .dw XT_DOCONDBRANCH
-000e49 0e4f DEST(PFA_FINDXTA1)
-000e4a 0598 .dw XT_TO_R
-000e4b 0589 .dw XT_NIP
-000e4c 0589 .dw XT_NIP
-000e4d 058f .dw XT_R_FROM
-000e4e 05e4 .dw XT_TRUE
- PFA_FINDXTA1:
-000e4f 04ae .dw XT_EXIT
-
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-000e50 011b .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-000e51 0bd3 .dw XT_DOSLITERAL
-000e52 0003 .dw 3
-000e53 6f20
-000e54 006b .db " ok",0
- .endif
-000e55 0c06 .dw XT_ITYPE
-000e56 04ae .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-000e57 ff03 .dw $FF03
-000e58 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-000e59 006b .db ".ok"
-000e5a 0e30 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-000e5b 1079 .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-000e5c 001c .dw USER_P_OK
-000e5d 1042 .dw XT_UDEFERFETCH
-000e5e 104e .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-000e5f 011b .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-000e60 0bd3 .dw XT_DOSLITERAL
-000e61 0002 .dw 2
-000e62 203e .db "> "
- .endif
-000e63 0c3b .dw XT_CR
-000e64 0c06 .dw XT_ITYPE
-000e65 04ae .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-000e66 ff06 .dw $FF06
-000e67 722e
-000e68 6165
-000e69 7964 .db ".ready"
-000e6a 0e57 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-000e6b 1079 .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-000e6c 0020 .dw USER_P_RDY
-000e6d 1042 .dw XT_UDEFERFETCH
-000e6e 104e .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-000e6f 011b .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-000e70 0bd3 .dw XT_DOSLITERAL
-000e71 0004 .dw 4
-000e72 3f20
-000e73 203f .db " ?? "
- .endif
-000e74 0c06 .dw XT_ITYPE
-000e75 09b5 .dw XT_BASE
-000e76 0512 .dw XT_FETCH
-000e77 0598 .dw XT_TO_R
-000e78 0a42 .dw XT_DECIMAL
-000e79 0b88 .dw XT_DOT
-000e7a 09e3 .dw XT_TO_IN
-000e7b 0512 .dw XT_FETCH
-000e7c 0b88 .dw XT_DOT
-000e7d 058f .dw XT_R_FROM
-000e7e 09b5 .dw XT_BASE
-000e7f 051a .dw XT_STORE
-000e80 04ae .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-000e81 ff06 .dw $FF06
-000e82 652e
-000e83 7272
-000e84 726f .db ".error"
-000e85 0e66 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-000e86 1079 .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-000e87 001e .dw USER_P_ERR
-000e88 1042 .dw XT_UDEFERFETCH
-000e89 104e .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-000e8a ff04 .dw $ff04
-000e8b 7571
-000e8c 7469 .db "quit"
-000e8d 0e81 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-000e8e 011b .dw DO_COLON
- .endif
- PFA_QUIT:
-000e8f 02d1
-000e90 02d8
-000e91 051a .dw XT_LP0,XT_LP,XT_STORE
-000e92 0eef .dw XT_SP0
-000e93 072f .dw XT_SP_STORE
-000e94 0efc .dw XT_RP0
-000e95 0719 .dw XT_RP_STORE
-000e96 0366 .dw XT_LBRACKET
-
- PFA_QUIT2:
-000e97 09af .dw XT_STATE
-000e98 0512 .dw XT_FETCH
-000e99 05b3 .dw XT_ZEROEQUAL
-000e9a 04c7 .dw XT_DOCONDBRANCH
-000e9b 0e9d DEST(PFA_QUIT4)
-000e9c 0e6b .dw XT_PROMPTREADY
- PFA_QUIT4:
-000e9d 0d48 .dw XT_REFILL
-000e9e 04c7 .dw XT_DOCONDBRANCH
-000e9f 0eaf DEST(PFA_QUIT3)
-000ea0 04ce .dw XT_DOLITERAL
-000ea1 0f15 .dw XT_INTERPRET
-000ea2 0c91 .dw XT_CATCH
-000ea3 0552 .dw XT_QDUP
-000ea4 04c7 .dw XT_DOCONDBRANCH
-000ea5 0eaf DEST(PFA_QUIT3)
-000ea6 054a .dw XT_DUP
-000ea7 04ce .dw XT_DOLITERAL
-000ea8 fffe .dw -2
-000ea9 0607 .dw XT_LESS
-000eaa 04c7 .dw XT_DOCONDBRANCH
-000eab 0ead DEST(PFA_QUIT5)
-000eac 0e86 .dw XT_PROMPTERROR
- PFA_QUIT5:
-000ead 04bd .dw XT_DOBRANCH
-000eae 0e8f DEST(PFA_QUIT)
- PFA_QUIT3:
-000eaf 0e5b .dw XT_PROMPTOK
-000eb0 04bd .dw XT_DOBRANCH
-000eb1 0e97 DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-000eb2 ff05 .dw $ff05
-000eb3 6170
-000eb4 7375
-000eb5 0065 .db "pause",0
-000eb6 0e8a .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-000eb7 1079 .dw PFA_DODEFER1
- PFA_PAUSE:
-000eb8 0257 .dw ram_pause
-000eb9 102e .dw XT_RDEFERFETCH
-000eba 1038 .dw XT_RDEFERSTORE
-
- .dseg
-000257 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-000ebb ff04 .dw $ff04
-000ebc 6f63
-000ebd 646c .db "cold"
-000ebe 0eb2 .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-000ebf 0ec0 .dw PFA_COLD
- PFA_COLD:
-000ec0 b6a4 in_ mcu_boot, MCUSR
-000ec1 2422 clr zerol
-000ec2 2433 clr zeroh
-000ec3 24bb clr isrflag
-000ec4 be24 out_ MCUSR, zerol
- ; clear RAM
-000ec5 e0e0 ldi zl, low(ramstart)
-000ec6 e0f2 ldi zh, high(ramstart)
- clearloop:
-000ec7 9221 st Z+, zerol
-000ec8 30e0 cpi zl, low(sram_size+ramstart)
-000ec9 f7e9 brne clearloop
-000eca 32f2 cpi zh, high(sram_size+ramstart)
-000ecb f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000259 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-000ecc e5e9 ldi zl, low(ram_user1)
-000ecd e0f2 ldi zh, high(ram_user1)
-000ece 012f movw upl, zl
- ; init return stack pointer
-000ecf ef0f ldi temp0,low(rstackstart)
-000ed0 bf0d out_ SPL,temp0
-000ed1 8304 std Z+4, temp0
-000ed2 e211 ldi temp1,high(rstackstart)
-000ed3 bf1e out_ SPH,temp1
-000ed4 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-000ed5 eacf ldi yl,low(stackstart)
-000ed6 83c6 std Z+6, yl
-000ed7 e2d1 ldi yh,high(stackstart)
-000ed8 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-000ed9 eea2 ldi XL, low(PFA_WARM)
-000eda e0be ldi XH, high(PFA_WARM)
- ; its a far jump...
-000edb 940c 011f jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-000edd ff04 .dw $ff04
-000ede 6177
-000edf 6d72 .db "warm"
-000ee0 0ebb .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-000ee1 011b .dw DO_COLON
- PFA_WARM:
- .endif
-000ee2 11b6 .dw XT_INIT_RAM
-000ee3 04ce .dw XT_DOLITERAL
-000ee4 0fe5 .dw XT_NOOP
-000ee5 04ce .dw XT_DOLITERAL
-000ee6 0eb7 .dw XT_PAUSE
-000ee7 1059 .dw XT_DEFERSTORE
-000ee8 0366 .dw XT_LBRACKET
-000ee9 0a5d .dw XT_TURNKEY
-000eea 0e8e .dw XT_QUIT ; never returns
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-000eeb ff03 .dw $ff03
-000eec 7073
-000eed 0030 .db "sp0",0
-000eee 0edd .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-000eef 0509 .dw PFA_DOVALUE1
- PFA_SP0:
-000ef0 0006 .dw USER_SP0
-000ef1 1042 .dw XT_UDEFERFETCH
-000ef2 104e .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-000ef3 ff02 .dw $ff02
-000ef4 7073 .db "sp"
-000ef5 0eeb .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-000ef6 04ef .dw PFA_DOUSER
- PFA_SP:
-000ef7 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-000ef8 ff03 .dw $ff03
-000ef9 7072
-000efa 0030 .db "rp0",0
-000efb 0ef3 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-000efc 011b .dw DO_COLON
- PFA_RP0:
-000efd 0f00 .dw XT_DORP0
-000efe 0512 .dw XT_FETCH
-000eff 04ae .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-000f00 04ef .dw PFA_DOUSER
- PFA_DORP0:
-000f01 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-000f02 ff05 .dw $ff05
-000f03 6564
-000f04 7470
-000f05 0068 .db "depth",0
-000f06 0ef8 .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-000f07 011b .dw DO_COLON
- PFA_DEPTH:
- .endif
-000f08 0eef .dw XT_SP0
-000f09 0726 .dw XT_SP_FETCH
-000f0a 062c .dw XT_MINUS
-000f0b 069d .dw XT_2SLASH
-000f0c 06ce .dw XT_1MINUS
-000f0d 04ae .dw XT_EXIT
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-000f0e ff09 .dw $ff09
-000f0f 6e69
-000f10 6574
-000f11 7072
-000f12 6572
-000f13 0074 .db "interpret",0
-000f14 0f02 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-000f15 011b .dw DO_COLON
- .endif
- PFA_INTERPRET:
-000f16 0e1a .dw XT_PARSENAME ; ( -- addr len )
-000f17 054a .dw XT_DUP ; ( -- addr len flag)
-000f18 04c7 .dw XT_DOCONDBRANCH
-000f19 0f26 DEST(PFA_INTERPRET2)
-000f1a 0f32 .dw XT_FORTHRECOGNIZER
-000f1b 0f3d .dw XT_RECOGNIZE
-000f1c 09af .dw XT_STATE
-000f1d 0512 .dw XT_FETCH
-000f1e 04c7 .dw XT_DOCONDBRANCH
-000f1f 0f21 DEST(PFA_INTERPRET1)
-000f20 1011 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-000f21 082c .dw XT_FETCHI
-000f22 04b8 .dw XT_EXECUTE
-000f23 0fbd .dw XT_QSTACK
-000f24 04bd .dw XT_DOBRANCH
-000f25 0f16 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000f26 09d3 .dw XT_2DROP
-000f27 04ae .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-000f28 ff10 .dw $ff10
-000f29 6f66
-000f2a 7472
-000f2b 2d68
-000f2c 6572
-000f2d 6f63
-000f2e 6e67
-000f2f 7a69
-000f30 7265 .db "forth-recognizer"
-000f31 0f0e .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-000f32 0509 .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-000f33 007c .dw CFG_FORTHRECOGNIZER
-000f34 101a .dw XT_EDEFERFETCH
-000f35 1024 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-000f36 ff09 .dw $ff09
-000f37 6572
-000f38 6f63
-000f39 6e67
-000f3a 7a69
-000f3b 0065 .db "recognize",0
-000f3c 0f28 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-000f3d 011b .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-000f3e 04ce .dw XT_DOLITERAL
-000f3f 0f48 .dw XT_RECOGNIZE_A
-000f40 055d .dw XT_SWAP
-000f41 041c .dw XT_MAPSTACK
-000f42 05b3 .dw XT_ZEROEQUAL
-000f43 04c7 .dw XT_DOCONDBRANCH
-000f44 0f47 DEST(PFA_RECOGNIZE1)
-000f45 09d3 .dw XT_2DROP
-000f46 0fb0 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-000f47 04ae .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-000f48 011b .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-000f49 057a .dw XT_ROT ; -- len xt addr
-000f4a 057a .dw XT_ROT ; -- xt addr len
-000f4b 09ca .dw XT_2DUP
-000f4c 07b8 .dw XT_2TO_R
-000f4d 057a .dw XT_ROT ; -- addr len xt
-000f4e 04b8 .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-000f4f 07c7 .dw XT_2R_FROM
-000f50 057a .dw XT_ROT
-000f51 054a .dw XT_DUP
-000f52 0fb0 .dw XT_DT_NULL
-000f53 126d .dw XT_EQUAL
-000f54 04c7 .dw XT_DOCONDBRANCH
-000f55 0f59 DEST(PFA_RECOGNIZE_A1)
-000f56 0572 .dw XT_DROP
-000f57 05ed .dw XT_ZERO
-000f58 04ae .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-000f59 0589 .dw XT_NIP
-000f5a 0589 .dw XT_NIP
-000f5b 05e4 .dw XT_TRUE
-000f5c 04ae .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-000f5d ff06 .dw $ff06
-000f5e 7464
-000f5f 6e3a
-000f60 6d75 .db "dt:num"
-000f61 0f36 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-000f62 04e9 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-000f63 0fe5 .dw XT_NOOP ; interpret
-000f64 01f2 .dw XT_LITERAL ; compile
-000f65 01f2 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-000f66 ff07 .dw $ff07
-000f67 7464
-000f68 643a
-000f69 756e
-000f6a 006d .db "dt:dnum",0
-000f6b 0f5d .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000f6c 04e9 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-000f6d 0fe5 .dw XT_NOOP ; interpret
-000f6e 1265 .dw XT_2LITERAL ; compile
-000f6f 1265 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-000f70 ff07 .dw $ff07
-000f71 6572
-000f72 3a63
-000f73 756e
-000f74 006d .db "rec:num",0
-000f75 0f66 .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-000f76 011b .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-000f77 0d5a .dw XT_NUMBER
-000f78 04c7 .dw XT_DOCONDBRANCH
-000f79 0f82 DEST(PFA_REC_NONUMBER)
-000f7a 1274 .dw XT_ONE
-000f7b 126d .dw XT_EQUAL
-000f7c 04c7 .dw XT_DOCONDBRANCH
-000f7d 0f80 DEST(PFA_REC_INTNUM2)
-000f7e 0f62 .dw XT_DT_NUM
-000f7f 04ae .dw XT_EXIT
- PFA_REC_INTNUM2:
-000f80 0f6c .dw XT_DT_DNUM
-000f81 04ae .dw XT_EXIT
- PFA_REC_NONUMBER:
-000f82 0fb0 .dw XT_DT_NULL
-000f83 04ae .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-000f84 ff08 .dw $ff08
-000f85 6572
-000f86 3a63
-000f87 6966
-000f88 646e .db "rec:find"
-000f89 0f70 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000f8a 011b .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000f8b 0e36 .DW XT_FINDXT
-000f8c 054a .dw XT_DUP
-000f8d 05b3 .dw XT_ZEROEQUAL
-000f8e 04c7 .dw XT_DOCONDBRANCH
-000f8f 0f93 DEST(PFA_REC_WORD_FOUND)
-000f90 0572 .dw XT_DROP
-000f91 0fb0 .dw XT_DT_NULL
-000f92 04ae .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-000f93 0f9a .dw XT_DT_XT
-
-000f94 04ae .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-000f95 ff05 .dw $ff05
-000f96 7464
-000f97 783a
-000f98 0074 .db "dt:xt",0
-000f99 0f84 .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000f9a 04e9 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000f9b 0f9e .dw XT_R_WORD_INTERPRET
-000f9c 0fa2 .dw XT_R_WORD_COMPILE
-000f9d 1265 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-000f9e 011b .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-000f9f 0572 .dw XT_DROP ; the flags are in the way
-000fa0 04b8 .dw XT_EXECUTE
-000fa1 04ae .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-000fa2 011b .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-000fa3 05ba .dw XT_ZEROLESS
-000fa4 04c7 .dw XT_DOCONDBRANCH
-000fa5 0fa8 DEST(PFA_R_WORD_COMPILE1)
-000fa6 01dc .dw XT_COMMA
-000fa7 04ae .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-000fa8 04b8 .dw XT_EXECUTE
-000fa9 04ae .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000faa ff07 .dw $ff07
-000fab 7464
-000fac 6e3a
-000fad 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-000fae 006c .db "dt:null"
-000faf 0f95 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-000fb0 04e9 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-000fb1 0fb4 .dw XT_FAIL ; interpret
-000fb2 0fb4 .dw XT_FAIL ; compile
-000fb3 0fb4 .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-000fb4 011b .dw DO_COLON
- PFA_FAIL:
- .endif
-000fb5 04ce .dw XT_DOLITERAL
-000fb6 fff3 .dw -13
-000fb7 0ca7 .dw XT_THROW
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-000fb8 ff06 .dw $ff06
-000fb9 733f
-000fba 6174
-000fbb 6b63 .db "?stack"
-000fbc 0faa .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-000fbd 011b .dw DO_COLON
- PFA_QSTACK:
- .endif
-000fbe 0f07 .dw XT_DEPTH
-000fbf 05ba .dw XT_ZEROLESS
-000fc0 04c7 .dw XT_DOCONDBRANCH
-000fc1 0fc5 DEST(PFA_QSTACK1)
-000fc2 04ce .dw XT_DOLITERAL
-000fc3 fffc .dw -4
-000fc4 0ca7 .dw XT_THROW
- PFA_QSTACK1:
-000fc5 04ae .dw XT_EXIT
- .include "words/ver.asm"
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-000fc6 ff03 .dw $ff03
-000fc7 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-000fc8 0072 .db "ver"
-000fc9 0fb8 .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-000fca 011b .dw DO_COLON
- PFA_DOT_VER:
- .endif
-000fcb 0971 .dw XT_ENV_FORTHNAME
-000fcc 0c06 .dw XT_ITYPE
-000fcd 0c48 .dw XT_SPACE
-000fce 09b5 .dw XT_BASE
-000fcf 0512 .dw XT_FETCH
-
-000fd0 097f .dw XT_ENV_FORTHVERSION
-000fd1 0a42 .dw XT_DECIMAL
-000fd2 1255 .dw XT_S2D
-000fd3 0b24 .dw XT_L_SHARP
-000fd4 0b2c .dw XT_SHARP
-000fd5 04ce .dw XT_DOLITERAL
-000fd6 002e .dw '.'
-000fd7 0b15 .dw XT_HOLD
-000fd8 0b42 .dw XT_SHARP_S
-000fd9 0b4d .dw XT_SHARP_G
-000fda 0c61 .dw XT_TYPE
-000fdb 09b5 .dw XT_BASE
-000fdc 051a .dw XT_STORE
-000fdd 0c48 .dw XT_SPACE
-000fde 0987 .dw XT_ENV_CPU
-000fdf 0c06 .dw XT_ITYPE
-
-000fe0 04ae .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-000fe1 ff04 .dw $ff04
-000fe2 6f6e
-000fe3 706f .db "noop"
-000fe4 0fc6 .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-000fe5 011b .dw DO_COLON
- PFA_NOOP:
- .endif
-000fe6 04ae .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-000fe7 ff06 .dw $ff06
-000fe8 6e75
-000fe9 7375
-000fea 6465 .db "unused"
-000feb 0fe1 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-000fec 011b .dw DO_COLON
- PFA_UNUSED:
-000fed 0726 .dw XT_SP_FETCH
-000fee 0a24 .dw XT_HERE
-000fef 062c .dw XT_MINUS
-000ff0 04ae .dw XT_EXIT
-
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-000ff1 0002 .dw $0002
-000ff2 6f74 .db "to"
-000ff3 0fe7 .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-000ff4 011b .dw DO_COLON
- PFA_TO:
- .endif
-000ff5 0c70 .dw XT_TICK
-000ff6 125e .dw XT_TO_BODY
-000ff7 09af .dw XT_STATE
-000ff8 0512 .dw XT_FETCH
-000ff9 04c7 .dw XT_DOCONDBRANCH
-000ffa 1005 DEST(PFA_TO1)
-000ffb 01d1 .dw XT_COMPILE
-000ffc 0fff .dw XT_DOTO
-000ffd 01dc .dw XT_COMMA
-000ffe 04ae .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-000fff 011b .dw DO_COLON
- PFA_DOTO:
- .endif
-001000 058f .dw XT_R_FROM
-001001 054a .dw XT_DUP
-001002 1011 .dw XT_ICELLPLUS
-001003 0598 .dw XT_TO_R
-001004 082c .dw XT_FETCHI
- PFA_TO1:
-001005 054a .dw XT_DUP
-001006 1011 .dw XT_ICELLPLUS
-001007 1011 .dw XT_ICELLPLUS
-001008 082c .dw XT_FETCHI
-001009 04b8 .dw XT_EXECUTE
-00100a 04ae .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-00100b ff07 .dw $FF07
-00100c 2d69
-00100d 6563
-00100e 6c6c
-00100f 002b .db "i-cell+",0
-001010 0ff1 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-001011 011b .dw DO_COLON
- PFA_ICELLPLUS:
-001012 06c8 .dw XT_1PLUS
-001013 04ae .dw XT_EXIT
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-001014 ff07 .dw $ff07
-001015 6445
-001016 6665
-001017 7265
-001018 0040 .db "Edefer@",0
-001019 100b .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-00101a 011b .dw DO_COLON
- PFA_EDEFERFETCH:
-00101b 082c .dw XT_FETCHI
-00101c 07f9 .dw XT_FETCHE
-00101d 04ae .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-00101e ff07 .dw $ff07
-00101f 6445
-001020 6665
-001021 7265
-001022 0021 .db "Edefer!",0
-001023 1014 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-001024 011b .dw DO_COLON
- PFA_EDEFERSTORE:
-001025 082c .dw XT_FETCHI
-001026 07d5 .dw XT_STOREE
-001027 04ae .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-001028 ff07 .dw $ff07
-001029 6452
-00102a 6665
-00102b 7265
-00102c 0040 .db "Rdefer@",0
-00102d 101e .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-00102e 011b .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-00102f 082c .dw XT_FETCHI
-001030 0512 .dw XT_FETCH
-001031 04ae .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-001032 ff07 .dw $ff07
-001033 6452
-001034 6665
-001035 7265
-001036 0021 .db "Rdefer!",0
-001037 1028 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-001038 011b .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-001039 082c .dw XT_FETCHI
-00103a 051a .dw XT_STORE
-00103b 04ae .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-00103c ff07 .dw $ff07
-00103d 6455
-00103e 6665
-00103f 7265
-001040 0040 .db "Udefer@",0
-001041 1032 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-001042 011b .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-001043 082c .dw XT_FETCHI
-001044 079b .dw XT_UP_FETCH
-001045 0636 .dw XT_PLUS
-001046 0512 .dw XT_FETCH
-001047 04ae .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-001048 ff07 .dw $ff07
-001049 6455
-00104a 6665
-00104b 7265
-00104c 0021 .db "Udefer!",0
-00104d 103c .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-00104e 011b .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-00104f 082c .dw XT_FETCHI
-001050 079b .dw XT_UP_FETCH
-001051 0636 .dw XT_PLUS
-001052 051a .dw XT_STORE
-001053 04ae .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-001054 ff06 .dw $ff06
-001055 6564
-001056 6566
-001057 2172 .db "defer!"
-001058 1048 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-001059 011b .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-00105a 125e .dw XT_TO_BODY
-00105b 054a .dw XT_DUP
-00105c 1011 .dw XT_ICELLPLUS
-00105d 1011 .dw XT_ICELLPLUS
-00105e 082c .dw XT_FETCHI
-00105f 04b8 .dw XT_EXECUTE
-001060 04ae .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-001061 ff06 .dw $ff06
-001062 6564
-001063 6566
-001064 4072 .db "defer@"
-001065 1054 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-001066 011b .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-001067 125e .dw XT_TO_BODY
-001068 054a .dw XT_DUP
-001069 1011 .dw XT_ICELLPLUS
-00106a 082c .dw XT_FETCHI
-00106b 04b8 .dw XT_EXECUTE
-00106c 04ae .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-00106d ff07 .dw $ff07
-00106e 6428
-00106f 6665
-001070 7265
-001071 0029 .db "(defer)", 0
-001072 1061 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-001073 011b .dw DO_COLON
- PFA_DODEFER:
-001074 01ae .dw XT_DOCREATE
-001075 030e .dw XT_REVEAL
-001076 01d1 .dw XT_COMPILE
-001077 1079 .dw PFA_DODEFER1
-001078 04ae .dw XT_EXIT
- PFA_DODEFER1:
-001079 940e 0327 call_ DO_DODOES
-00107b 054a .dw XT_DUP
-00107c 1011 .dw XT_ICELLPLUS
-00107d 082c .dw XT_FETCHI
-00107e 04b8 .dw XT_EXECUTE
-00107f 04b8 .dw XT_EXECUTE
-001080 04ae .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-001081 ff0f .dw $ff0f
-001082 6573
-001083 7261
-001084 6863
-001085 772d
-001086 726f
-001087 6c64
-001088 7369
-001089 0074 .db "search-wordlist",0
-00108a 106d .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00108b 011b .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-00108c 0598 .dw XT_TO_R
-00108d 05ed .dw XT_ZERO
-00108e 04ce .dw XT_DOLITERAL
-00108f 10a0 .dw XT_ISWORD
-001090 058f .dw XT_R_FROM
-001091 10bd .dw XT_TRAVERSEWORDLIST
-001092 054a .dw XT_DUP
-001093 05b3 .dw XT_ZEROEQUAL
-001094 04c7 .dw XT_DOCONDBRANCH
-001095 109a DEST(PFA_SEARCH_WORDLIST1)
-001096 09d3 .dw XT_2DROP
-001097 0572 .dw XT_DROP
-001098 05ed .dw XT_ZERO
-001099 04ae .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-00109a 054a .dw XT_DUP
-00109b 10e4 .dw XT_NFA2CFA
- ; .. and get the header flag
-00109c 055d .dw XT_SWAP
-00109d 0194 .dw XT_NAME2FLAGS
-00109e 0182 .dw XT_IMMEDIATEQ
-00109f 04ae .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-0010a0 011b .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-0010a1 0598 .dw XT_TO_R
-0010a2 0572 .dw XT_DROP
-0010a3 09ca .dw XT_2DUP
-0010a4 05a1 .dw XT_R_FETCH ; -- addr len addr len nt
-0010a5 10d8 .dw XT_NAME2STRING
-0010a6 10ee .dw XT_ICOMPARE ; (-- addr len f )
-0010a7 04c7 .dw XT_DOCONDBRANCH
-0010a8 10ae DEST(PFA_ISWORD3)
- ; not now
-0010a9 058f .dw XT_R_FROM
-0010aa 0572 .dw XT_DROP
-0010ab 05ed .dw XT_ZERO
-0010ac 05e4 .dw XT_TRUE ; maybe next word
-0010ad 04ae .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-0010ae 09d3 .dw XT_2DROP
-0010af 058f .dw XT_R_FROM
-0010b0 05ed .dw XT_ZERO ; finish traverse-wordlist
-0010b1 04ae .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-0010b2 ff11 .dw $ff11
-0010b3 7274
-0010b4 7661
-0010b5 7265
-0010b6 6573
-0010b7 772d
-0010b8 726f
-0010b9 6c64
-0010ba 7369
-0010bb 0074 .db "traverse-wordlist",0
-0010bc 1081 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-0010bd 011b .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-0010be 07f9 .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-0010bf 054a .dw XT_DUP ; ( -- xt nt nt )
-0010c0 04c7 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-0010c1 10ce DEST(PFA_TRAVERSEWORDLIST2)
-0010c2 09ca .dw XT_2DUP
-0010c3 07b8 .dw XT_2TO_R
-0010c4 055d .dw XT_SWAP
-0010c5 04b8 .dw XT_EXECUTE
-0010c6 07c7 .dw XT_2R_FROM
-0010c7 057a .dw XT_ROT
-0010c8 04c7 .dw XT_DOCONDBRANCH
-0010c9 10ce DEST(PFA_TRAVERSEWORDLIST2)
-0010ca 048a .dw XT_NFA2LFA
-0010cb 082c .dw XT_FETCHI
-0010cc 04bd .dw XT_DOBRANCH ; ( -- addr )
-0010cd 10bf DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-0010ce 09d3 .dw XT_2DROP
-0010cf 04ae .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-0010d0 ff0b .dw $ff0b
-0010d1 616e
-0010d2 656d
-0010d3 733e
-0010d4 7274
-0010d5 6e69
-0010d6 0067 .db "name>string",0
-0010d7 10b2 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-0010d8 011b .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-0010d9 0c32 .dw XT_ICOUNT ; ( -- addr n )
-0010da 04ce .dw XT_DOLITERAL
-0010db 00ff .dw 255
-0010dc 06ac .dw XT_AND ; mask immediate bit
-0010dd 04ae .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-0010de ff07 .dw $ff07
-0010df 666e
-0010e0 3e61
-0010e1 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-0010e2 0061 .db "nfa>cfa"
-0010e3 10d0 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-0010e4 011b .dw DO_COLON
- PFA_NFA2CFA:
-0010e5 048a .dw XT_NFA2LFA ; skip to link field
-0010e6 06c8 .dw XT_1PLUS ; next is the execution token
-0010e7 04ae .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-0010e8 ff08 .dw $ff08
-0010e9 6369
-0010ea 6d6f
-0010eb 6170
-0010ec 6572 .db "icompare"
-0010ed 10de .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-0010ee 011b .dw DO_COLON
- PFA_ICOMPARE:
-0010ef 0598 .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-0010f0 0568 .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-0010f1 058f .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-0010f2 05ac .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-0010f3 04c7 .dw XT_DOCONDBRANCH
-0010f4 10f9 .dw PFA_ICOMPARE_SAMELEN
-0010f5 09d3 .dw XT_2DROP
-0010f6 0572 .dw XT_DROP
-0010f7 05e4 .dw XT_TRUE
-0010f8 04ae .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-0010f9 055d .dw XT_SWAP ; ( -- r-addr f-addr len )
-0010fa 05ed .dw XT_ZERO
-0010fb 029b .dw XT_QDOCHECK
-0010fc 04c7 .dw XT_DOCONDBRANCH
-0010fd 111c .dw PFA_ICOMPARE_DONE
-0010fe 0734 .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-0010ff 0568 .dw XT_OVER
-001100 0512 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-001101 0568 .dw XT_OVER
-001102 082c .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-001103 054a .dw XT_DUP
- ;.dw XT_BYTESWAP
-001104 04ce .dw XT_DOLITERAL
-001105 0100 .dw $100
-001106 05f5 .dw XT_ULESS
-001107 04c7 .dw XT_DOCONDBRANCH
-001108 110d .dw PFA_ICOMPARE_LASTCELL
-001109 055d .dw XT_SWAP
-00110a 04ce .dw XT_DOLITERAL
-00110b 00ff .dw $00FF
-00110c 06ac .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-00110d 05ac .dw XT_NOTEQUAL
-00110e 04c7 .dw XT_DOCONDBRANCH
-00110f 1114 .dw PFA_ICOMPARE_NEXTLOOP
-001110 09d3 .dw XT_2DROP
-001111 05e4 .dw XT_TRUE
-001112 076d .dw XT_UNLOOP
-001113 04ae .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-001114 06c8 .dw XT_1PLUS
-001115 055d .dw XT_SWAP
-001116 09c2 .dw XT_CELLPLUS
-001117 055d .dw XT_SWAP
-001118 04ce .dw XT_DOLITERAL
-001119 0002 .dw 2
-00111a 0753 .dw XT_DOPLUSLOOP
-00111b 10ff .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-00111c 09d3 .dw XT_2DROP
-00111d 05ed .dw XT_ZERO
-00111e 04ae .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
-
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-00111f ff01 .dw $ff01
-001120 002a .db "*",0
-001121 10e8 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-001122 011b .dw DO_COLON
- PFA_STAR:
- .endif
-
-001123 063f .dw XT_MSTAR
-001124 0572 .dw XT_DROP
-001125 04ae .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-001126 ff01 .dw $FF01
-001127 006a .db "j",0
-001128 111f .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-001129 011b .dw DO_COLON
- PFA_J:
-00112a 070f .dw XT_RP_FETCH
-00112b 04ce .dw XT_DOLITERAL
-00112c 0007 .dw 7
-00112d 0636 .dw XT_PLUS
-00112e 0512 .dw XT_FETCH
-00112f 070f .dw XT_RP_FETCH
-001130 04ce .dw XT_DOLITERAL
-001131 0009 .dw 9
-001132 0636 .dw XT_PLUS
-001133 0512 .dw XT_FETCH
-001134 0636 .dw XT_PLUS
-001135 04ae .dw XT_EXIT
-
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-001136 ff04 .dw $ff04
-001137 6164
-001138 7362 .db "dabs"
-001139 1126 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-00113a 011b .dw DO_COLON
- PFA_DABS:
-00113b 054a .dw XT_DUP
-00113c 05ba .dw XT_ZEROLESS
-00113d 04c7 .dw XT_DOCONDBRANCH
-00113e 1140 .dw PFA_DABS1
-00113f 1147 .dw XT_DNEGATE
- PFA_DABS1:
-001140 04ae .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-001141 ff07 .dw $ff07
-001142 6e64
-001143 6765
-001144 7461
-001145 0065 .db "dnegate",0
-001146 1136 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-001147 011b .dw DO_COLON
- PFA_DNEGATE:
-001148 089f .dw XT_DINVERT
-001149 1274 .dw XT_ONE
-00114a 05ed .dw XT_ZERO
-00114b 0879 .dw XT_DPLUS
-00114c 04ae .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-00114d ff05 .dw $ff05
-00114e 6d63
-00114f 766f
-001150 0065 .db "cmove",0
-001151 1141 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-001152 1153 .dw PFA_CMOVE
- PFA_CMOVE:
-001153 93bf push xh
-001154 93af push xl
-001155 91e9 ld zl, Y+
-001156 91f9 ld zh, Y+ ; addr-to
-001157 91a9 ld xl, Y+
-001158 91b9 ld xh, Y+ ; addr-from
-001159 2f09 mov temp0, tosh
-00115a 2b08 or temp0, tosl
-00115b f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00115c 911d ld temp1, X+
-00115d 9311 st Z+, temp1
-00115e 9701 sbiw tosl, 1
-00115f f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-001160 91af pop xl
-001161 91bf pop xh
-001162 9189
-001163 9199 loadtos
-001164 940c 011f jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-001166 ff05 .dw $ff05
-001167 7332
-001168 6177
-001169 0070 .db "2swap",0
-00116a 114d .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00116b 011b .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00116c 057a .dw XT_ROT
-00116d 0598 .dw XT_TO_R
-00116e 057a .dw XT_ROT
-00116f 058f .dw XT_R_FROM
-001170 04ae .dw XT_EXIT
-
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-001171 ff0a .dw $ff0a
-001172 6572
-001173 6966
-001174 6c6c
-001175 742d
-001176 6269 .db "refill-tib"
-001177 1166 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-001178 011b .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-001179 1194 .dw XT_TIB
-00117a 04ce .dw XT_DOLITERAL
-00117b 005a .dw TIB_SIZE
-00117c 0cf7 .dw XT_ACCEPT
-00117d 119a .dw XT_NUMBERTIB
-00117e 051a .dw XT_STORE
-00117f 05ed .dw XT_ZERO
-001180 09e3 .dw XT_TO_IN
-001181 051a .dw XT_STORE
-001182 05e4 .dw XT_TRUE ; -1
-001183 04ae .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-001184 ff0a .dw $FF0A
-001185 6f73
-001186 7275
-001187 6563
-001188 742d
-001189 6269 .db "source-tib"
-00118a 1171 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00118b 011b .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00118c 1194 .dw XT_TIB
-00118d 119a .dw XT_NUMBERTIB
-00118e 0512 .dw XT_FETCH
-00118f 04ae .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-001190 ff03 .dw $ff03
-001191 6974
-001192 0062 .db "tib",0
-001193 1184 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-001194 04dc .dw PFA_DOVARIABLE
- PFA_TIB:
-001195 0285 .dw ram_tib
- .dseg
-000285 ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-001196 ff04 .dw $ff04
-001197 7423
-001198 6269 .db "#tib"
-001199 1190 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00119a 04dc .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00119b 02df .dw ram_sharptib
- .dseg
-0002df ram_sharptib: .byte 2
- .cseg
- .endif
-
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00119c ff06 .dw $ff06
-00119d 6565
-00119e 723e
-00119f 6d61 .db "ee>ram"
-0011a0 1196 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-0011a1 011b .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-0011a2 05ed .dw XT_ZERO
-0011a3 0734 .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-0011a4 0568 .dw XT_OVER
-0011a5 07f9 .dw XT_FETCHE
-0011a6 0568 .dw XT_OVER
-0011a7 051a .dw XT_STORE
-0011a8 09c2 .dw XT_CELLPLUS
-0011a9 055d .dw XT_SWAP
-0011aa 09c2 .dw XT_CELLPLUS
-0011ab 055d .dw XT_SWAP
-0011ac 0762 .dw XT_DOLOOP
-0011ad 11a4 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-0011ae 09d3 .dw XT_2DROP
-0011af 04ae .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-0011b0 ff08 .dw $ff08
-0011b1 6e69
-0011b2 7469
-0011b3 722d
-0011b4 6d61 .db "init-ram"
-0011b5 119c .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-0011b6 011b .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-0011b7 04ce .dw XT_DOLITERAL
-0011b8 00a8 .dw EE_INITUSER
-0011b9 079b .dw XT_UP_FETCH
-0011ba 04ce .dw XT_DOLITERAL
-0011bb 0022 .dw SYSUSERSIZE
-0011bc 069d .dw XT_2SLASH
-0011bd 11a1 .dw XT_EE2RAM
-0011be 04ae .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-0011bf ff0b .dw $ff0b
-0011c0 6573
-0011c1 2d74
-0011c2 7563
-0011c3 7272
-0011c4 6e65
-0011c5 0074 .db "set-current",0
-0011c6 11b0 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-0011c7 011b .dw DO_COLON
- PFA_SET_CURRENT:
-0011c8 04ce .dw XT_DOLITERAL
-0011c9 0084 .dw CFG_CURRENT
-0011ca 07d5 .dw XT_STOREE
-0011cb 04ae .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-0011cc ff08 .dw $ff08
-0011cd 6f77
-0011ce 6472
-0011cf 696c
-0011d0 7473 .db "wordlist"
-0011d1 11bf .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-0011d2 011b .dw DO_COLON
- PFA_WORDLIST:
-0011d3 0a1c .dw XT_EHERE
-0011d4 05ed .dw XT_ZERO
-0011d5 0568 .dw XT_OVER
-0011d6 07d5 .dw XT_STOREE
-0011d7 054a .dw XT_DUP
-0011d8 09c2 .dw XT_CELLPLUS
-0011d9 0fff .dw XT_DOTO
-0011da 0a1d .dw PFA_EHERE
-0011db 04ae .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-0011dc ff0e .dw $ff0e
-0011dd 6f66
-0011de 7472
-0011df 2d68
-0011e0 6f77
-0011e1 6472
-0011e2 696c
-0011e3 7473 .db "forth-wordlist"
-0011e4 11cc .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-0011e5 04dc .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-0011e6 0086 .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-0011e7 ff09 .dw $ff09
-0011e8 6573
-0011e9 2d74
-0011ea 726f
-0011eb 6564
-0011ec 0072 .db "set-order",0
-0011ed 11dc .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-0011ee 011b .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-0011ef 04ce .dw XT_DOLITERAL
-0011f0 0088 .dw CFG_ORDERLISTLEN
-0011f1 03fe .dw XT_SET_STACK
-0011f2 04ae .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-0011f3 ff0f .dw $ff0f
-0011f4 6573
-0011f5 2d74
-0011f6 6572
-0011f7 6f63
-0011f8 6e67
-0011f9 7a69
-0011fa 7265
-0011fb 0073 .db "set-recognizers",0
-0011fc 11e7 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-0011fd 011b .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-0011fe 04ce .dw XT_DOLITERAL
-0011ff 009a .dw CFG_RECOGNIZERLISTLEN
-001200 03fe .dw XT_SET_STACK
-001201 04ae .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-001202 ff0f .dw $ff0f
-001203 6567
-001204 2d74
-001205 6572
-001206 6f63
-001207 6e67
-001208 7a69
-001209 7265
-00120a 0073 .db "get-recognizers",0
-00120b 11f3 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-00120c 011b .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-00120d 04ce .dw XT_DOLITERAL
-00120e 009a .dw CFG_RECOGNIZERLISTLEN
-00120f 03dd .dw XT_GET_STACK
-001210 04ae .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-001211 ff04 .dw $ff04
-001212 6f63
-001213 6564 .db "code"
-001214 1202 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-001215 011b .dw DO_COLON
- PFA_CODE:
-001216 01ae .dw XT_DOCREATE
-001217 030e .dw XT_REVEAL
-001218 0a13 .dw XT_DP
-001219 1011 .dw XT_ICELLPLUS
-00121a 01dc .dw XT_COMMA
-00121b 04ae .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-00121c ff08 .dw $ff08
-00121d 6e65
-00121e 2d64
-00121f 6f63
-001220 6564 .db "end-code"
-001221 1211 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-001222 011b .dw DO_COLON
- PFA_ENDCODE:
-001223 01d1 .dw XT_COMPILE
-001224 940c .dw $940c
-001225 01d1 .dw XT_COMPILE
-001226 011f .dw DO_NEXT
-001227 04ae .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-001228 ff08 .dw $ff08
-001229 6d28
-00122a 7261
-00122b 656b
-00122c 2972 .db "(marker)"
-00122d 121c .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-00122e 0509 .dw PFA_DOVALUE1
- PFA_MARKER:
-00122f 00a6 .dw EE_MARKER
-001230 101a .dw XT_EDEFERFETCH
-001231 1024 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-001232 0008 .dw $0008
-001233 6f70
-001234 7473
-001235 6f70
-001236 656e .db "postpone"
-001237 1228 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-001238 011b .dw DO_COLON
- PFA_POSTPONE:
- .endif
-001239 0e1a .dw XT_PARSENAME
-00123a 0f32 .dw XT_FORTHRECOGNIZER
-00123b 0f3d .dw XT_RECOGNIZE
-00123c 054a .dw XT_DUP
-00123d 0598 .dw XT_TO_R
-00123e 1011 .dw XT_ICELLPLUS
-00123f 1011 .dw XT_ICELLPLUS
-001240 082c .dw XT_FETCHI
-001241 04b8 .dw XT_EXECUTE
-001242 058f .dw XT_R_FROM
-001243 1011 .dw XT_ICELLPLUS
-001244 082c .dw XT_FETCHI
-001245 01dc .dw XT_COMMA
-001246 04ae .dw XT_EXIT
- .endif
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-001247 ff06 .dw $ff06
-001248 6f62
-001249 6e75
-00124a 7364 .db "bounds"
-00124b 1232 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-00124c 011b .dw DO_COLON
- PFA_BOUNDS:
- .endif
-00124d 0568 .dw XT_OVER
-00124e 0636 .dw XT_PLUS
-00124f 055d .dw XT_SWAP
-001250 04ae .dw XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-001251 ff03 .dw $ff03
-001252 3e73
-001253 0064 .db "s>d",0
-001254 1247 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-001255 011b .dw DO_COLON
- PFA_S2D:
- .endif
-001256 054a .dw XT_DUP
-001257 05ba .dw XT_ZEROLESS
-001258 04ae .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-001259 ff05 .dw $ff05
-00125a 623e
-00125b 646f
-00125c 0079 .db ">body",0
-00125d 1251 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-00125e 06c9 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>4000
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-00125f 0008 .dw $0008
-001260 6c32
-001261 7469
-001262 7265
-001263 6c61 .db "2literal"
-001264 1259 .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-001265 011b .dw DO_COLON
- PFA_2LITERAL:
- .endif
-001266 055d .dw XT_SWAP
-001267 01f2 .dw XT_LITERAL
-001268 01f2 .dw XT_LITERAL
-001269 04ae .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-00126a ff01 .dw $ff01
-00126b 003d .db "=",0
-00126c 125f .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-00126d 011b .dw DO_COLON
- PFA_EQUAL:
-00126e 062c .dw XT_MINUS
-00126f 05b3 .dw XT_ZEROEQUAL
-001270 04ae .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-001271 ff01 .dw $ff01
-001272 0031 .db "1",0
-001273 126a .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-001274 04dc .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-001275 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-001276 ff01 .dw $ff01
-001277 0032 .db "2",0
-001278 1271 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-001279 04dc .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-00127a 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-00127b ff02 .dw $ff02
-00127c 312d .db "-1"
-00127d 1276 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-00127e 04dc .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-00127f ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
-
- .set DPSTART = pc
- .set flashlast = pc
-
- .dseg
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000072 ff ff
- ; some configs
-000074 80 12 CFG_DP: .dw DPSTART ; Dictionary Pointer
-000076 e1 02 EE_HERE: .dw HERESTART ; Memory Allocation
-000078 cc 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00007a 43 04 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-00007c 9a 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-00007e b0 21 CFG_LP0: .dw stackstart+1
-000080 98 04 CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000082 96 09 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000084 86 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-000086 7b 12 CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-000088 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00008a 86 00 .dw CFG_FORTHWORDLIST ; get/set-order
-00008c .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00009a 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-00009c 8a 0f .dw XT_REC_FIND
-00009e 76 0f .dw XT_REC_NUM
-0000a0 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-0000a4 15 08 .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-0000a6 a6 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-0000a8 00 00 .dw 0 ; USER_STATE
-0000aa 00 00 .dw 0 ; USER_FOLLOWER
-0000ac ff 21 .dw rstackstart ; USER_RP
-0000ae af 21 .dw stackstart ; USER_SP0
-0000b0 af 21 .dw stackstart ; USER_SP
-
-0000b2 00 00 .dw 0 ; USER_HANDLER
-0000b4 0a 00 .dw 10 ; USER_BASE
-
-0000b6 e1 00 .dw XT_TX ; USER_EMIT
-0000b8 ef 00 .dw XT_TXQ ; USER_EMITQ
-0000ba b6 00 .dw XT_RX ; USER_KEY
-0000bc d1 00 .dw XT_RXQ ; USER_KEYQ
-0000be 8b 11 .dw XT_SOURCETIB ; USER_SOURCE
-0000c0 00 00 .dw 0 ; USER_G_IN
-0000c2 78 11 .dw XT_REFILLTIB ; USER_REFILL
-0000c4 50 0e .dw XT_DEFAULT_PROMPTOK
-0000c6 6f 0e .dw XT_DEFAULT_PROMPTERROR
-0000c8 5f 0e .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-0000ca 17 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
-
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega2561" register use summary:
-r0 : 26 r1 : 5 r2 : 9 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 77 r17: 57 r18: 52 r19: 37 r20: 13 r21: 38 r22: 11 r23: 4
-r24: 187 r25: 133 r26: 28 r27: 17 r28: 7 r29: 4 r30: 81 r31: 41
-x : 4 y : 203 z : 41
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega2561" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 2 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 13 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 1 cbi : 0 cbr : 0
-clc : 1 clh : 0 cli : 5 cln : 0 clr : 21 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eicall: 1 eijmp : 0 elpm : 16
-eor : 3 fmul : 0 fmuls : 0 fmulsu: 0 icall : 0 ijmp : 1
-in : 14 inc : 3 jmp : 8 ld : 136 ldd : 4 ldi : 31
-lds : 1 lpm : 0 lsl : 14 lsr : 2 mov : 15 movw : 65
-mul : 5 muls : 1 mulsu : 2 neg : 0 nop : 1 or : 9
-ori : 0 out : 26 pop : 47 push : 39 rcall : 69 ret : 6
-reti : 1 rjmp : 102 rol : 32 ror : 5 sbc : 9 sbci : 3
-sbi : 3 sbic : 3 sbis : 0 sbiw : 7 sbr : 0 sbrc : 4
-sbrs : 3 sec : 1 seh : 0 sei : 1 sen : 0 ser : 3
-ses : 0 set : 0 sev : 0 sez : 0 sleep : 0 spm : 2
-st : 74 std : 8 sts : 1 sub : 6 subi : 3 swap : 0
-tst : 0 wdr : 0
-Instructions used: 71 out of 116 (61.2%)
-
-"ATmega2561" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x03e07e 1962 12820 14782 262144 5.6%
-[.dseg] 0x000200 0x0002e1 0 225 225 8192 2.7%
-[.eseg] 0x000000 0x0000cc 0 204 204 4096 5.0%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/atmega2561/atmega256.map b/amforth-6.5/appl/atmega2561/atmega256.map
deleted file mode 100644
index b8ce7fe..0000000
--- a/amforth-6.5/appl/atmega2561/atmega256.map
+++ /dev/null
@@ -1,2503 +0,0 @@
-
-AVRASM ver. 2.1.52 atmega256.asm Sun Apr 30 20:10:15 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000098
-EQU SIGNATURE_002 00000002
-EQU UDR3 00000136
-EQU UBRR3H 00000135
-EQU UBRR3L 00000134
-EQU UCSR3C 00000132
-EQU UCSR3B 00000131
-EQU UCSR3A 00000130
-EQU OCR5CL 0000012c
-EQU OCR5CH 0000012d
-EQU OCR5BL 0000012a
-EQU OCR5BH 0000012b
-EQU OCR5AL 00000128
-EQU OCR5AH 00000129
-EQU ICR5H 00000127
-EQU ICR5L 00000126
-EQU TCNT5L 00000124
-EQU TCNT5H 00000125
-EQU TCCR5C 00000122
-EQU TCCR5B 00000121
-EQU TCCR5A 00000120
-EQU PORTL 0000010b
-EQU DDRL 0000010a
-EQU PINL 00000109
-EQU PORTK 00000108
-EQU DDRK 00000107
-EQU PINK 00000106
-EQU PORTJ 00000105
-EQU DDRJ 00000104
-EQU PINJ 00000103
-EQU PORTH 00000102
-EQU DDRH 00000101
-EQU PINH 00000100
-EQU UDR2 000000d6
-EQU UBRR2H 000000d5
-EQU UBRR2L 000000d4
-EQU UCSR2C 000000d2
-EQU UCSR2B 000000d1
-EQU UCSR2A 000000d0
-EQU UDR1 000000ce
-EQU UBRR1L 000000cc
-EQU UBRR1H 000000cd
-EQU UCSR1C 000000ca
-EQU UCSR1B 000000c9
-EQU UCSR1A 000000c8
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR4CL 000000ac
-EQU OCR4CH 000000ad
-EQU OCR4BL 000000aa
-EQU OCR4BH 000000ab
-EQU OCR4AL 000000a8
-EQU OCR4AH 000000a9
-EQU ICR4L 000000a6
-EQU ICR4H 000000a7
-EQU TCNT4L 000000a4
-EQU TCNT4H 000000a5
-EQU TCCR4C 000000a2
-EQU TCCR4B 000000a1
-EQU TCCR4A 000000a0
-EQU OCR3CL 0000009c
-EQU OCR3CH 0000009d
-EQU OCR3BL 0000009a
-EQU OCR3BH 0000009b
-EQU OCR3AL 00000098
-EQU OCR3AH 00000099
-EQU ICR3L 00000096
-EQU ICR3H 00000097
-EQU TCNT3L 00000094
-EQU TCNT3H 00000095
-EQU TCCR3C 00000092
-EQU TCCR3B 00000091
-EQU TCCR3A 00000090
-EQU OCR1CL 0000008c
-EQU OCR1CH 0000008d
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU DIDR2 0000007d
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU XMCRB 00000075
-EQU XMCRA 00000074
-EQU TIMSK5 00000073
-EQU TIMSK4 00000072
-EQU TIMSK3 00000071
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK2 0000006d
-EQU PCMSK1 0000006c
-EQU PCMSK0 0000006b
-EQU EICRB 0000006a
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR1 00000065
-EQU PRR0 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU EIND 0000003c
-EQU RAMPZ 0000003b
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU OCDR 00000031
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR5 0000001a
-EQU TIFR4 00000019
-EQU TIFR3 00000018
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTG 00000014
-EQU DDRG 00000013
-EQU PING 00000012
-EQU PORTF 00000011
-EQU DDRF 00000010
-EQU PINF 0000000f
-EQU PORTE 0000000e
-EQU DDRE 0000000d
-EQU PINE 0000000c
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU PORTA 00000002
-EQU DDRA 00000001
-EQU PINA 00000000
-EQU ACME 00000006
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU PORTE0 00000000
-EQU PE0 00000000
-EQU PORTE1 00000001
-EQU PE1 00000001
-EQU PORTE2 00000002
-EQU PE2 00000002
-EQU PORTE3 00000003
-EQU PE3 00000003
-EQU PORTE4 00000004
-EQU PE4 00000004
-EQU PORTE5 00000005
-EQU PE5 00000005
-EQU PORTE6 00000006
-EQU PE6 00000006
-EQU PORTE7 00000007
-EQU PE7 00000007
-EQU DDE0 00000000
-EQU DDE1 00000001
-EQU DDE2 00000002
-EQU DDE3 00000003
-EQU DDE4 00000004
-EQU DDE5 00000005
-EQU DDE6 00000006
-EQU DDE7 00000007
-EQU PINE0 00000000
-EQU PINE1 00000001
-EQU PINE2 00000002
-EQU PINE3 00000003
-EQU PINE4 00000004
-EQU PINE5 00000005
-EQU PINE6 00000006
-EQU PINE7 00000007
-EQU PORTF0 00000000
-EQU PF0 00000000
-EQU PORTF1 00000001
-EQU PF1 00000001
-EQU PORTF2 00000002
-EQU PF2 00000002
-EQU PORTF3 00000003
-EQU PF3 00000003
-EQU PORTF4 00000004
-EQU PF4 00000004
-EQU PORTF5 00000005
-EQU PF5 00000005
-EQU PORTF6 00000006
-EQU PF6 00000006
-EQU PORTF7 00000007
-EQU PF7 00000007
-EQU DDF0 00000000
-EQU DDF1 00000001
-EQU DDF2 00000002
-EQU DDF3 00000003
-EQU DDF4 00000004
-EQU DDF5 00000005
-EQU DDF6 00000006
-EQU DDF7 00000007
-EQU PINF0 00000000
-EQU PINF1 00000001
-EQU PINF2 00000002
-EQU PINF3 00000003
-EQU PINF4 00000004
-EQU PINF5 00000005
-EQU PINF6 00000006
-EQU PINF7 00000007
-EQU PORTG0 00000000
-EQU PG0 00000000
-EQU PORTG1 00000001
-EQU PG1 00000001
-EQU PORTG2 00000002
-EQU PG2 00000002
-EQU PORTG3 00000003
-EQU PG3 00000003
-EQU PORTG4 00000004
-EQU PG4 00000004
-EQU PORTG5 00000005
-EQU PG5 00000005
-EQU DDG0 00000000
-EQU DDG1 00000001
-EQU DDG2 00000002
-EQU DDG3 00000003
-EQU DDG4 00000004
-EQU DDG5 00000005
-EQU PING0 00000000
-EQU PING1 00000001
-EQU PING2 00000002
-EQU PING3 00000003
-EQU PING4 00000004
-EQU PING5 00000005
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSRSYNC 00000000
-EQU PSR10 00000000
-EQU TSM 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU UDR1_0 00000000
-EQU UDR1_1 00000001
-EQU UDR1_2 00000002
-EQU UDR1_3 00000003
-EQU UDR1_4 00000004
-EQU UDR1_5 00000005
-EQU UDR1_6 00000006
-EQU UDR1_7 00000007
-EQU MPCM1 00000000
-EQU U2X1 00000001
-EQU UPE1 00000002
-EQU DOR1 00000003
-EQU FE1 00000004
-EQU UDRE1 00000005
-EQU TXC1 00000006
-EQU RXC1 00000007
-EQU TXB81 00000000
-EQU RXB81 00000001
-EQU UCSZ12 00000002
-EQU TXEN1 00000003
-EQU RXEN1 00000004
-EQU UDRIE1 00000005
-EQU TXCIE1 00000006
-EQU RXCIE1 00000007
-EQU UCPOL1 00000000
-EQU UCSZ10 00000001
-EQU UCPHA1 00000001
-EQU UCSZ11 00000002
-EQU UDORD1 00000002
-EQU USBS1 00000003
-EQU UPM10 00000004
-EQU UPM11 00000005
-EQU UMSEL10 00000006
-EQU UMSEL11 00000007
-EQU UBRR_8 00000000
-EQU UBRR_9 00000001
-EQU UBRR_10 00000002
-EQU UBRR_11 00000003
-EQU UBRR_0 00000000
-EQU UBRR_1 00000001
-EQU UBRR_2 00000002
-EQU UBRR_3 00000003
-EQU UBRR_4 00000004
-EQU UBRR_5 00000005
-EQU UBRR_6 00000006
-EQU UBRR_7 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEAR10 00000002
-EQU EEAR11 00000003
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU TOIE5 00000000
-EQU OCIE5A 00000001
-EQU OCIE5B 00000002
-EQU OCIE5C 00000003
-EQU ICIE5 00000005
-EQU TOV5 00000000
-EQU OCF5A 00000001
-EQU OCF5B 00000002
-EQU OCF5C 00000003
-EQU ICF5 00000005
-EQU WGM50 00000000
-EQU WGM51 00000001
-EQU COM5C0 00000002
-EQU COM5C1 00000003
-EQU COM5B0 00000004
-EQU COM5B1 00000005
-EQU COM5A0 00000006
-EQU COM5A1 00000007
-EQU CS50 00000000
-EQU CS51 00000001
-EQU CS52 00000002
-EQU WGM52 00000003
-EQU WGM53 00000004
-EQU ICES5 00000006
-EQU ICNC5 00000007
-EQU FOC5C 00000005
-EQU FOC5B 00000006
-EQU FOC5A 00000007
-EQU ICR5H0 00000000
-EQU ICR5H1 00000001
-EQU ICR5H2 00000002
-EQU ICR5H3 00000003
-EQU ICR5H4 00000004
-EQU ICR5H5 00000005
-EQU ICR5H6 00000006
-EQU ICR5H7 00000007
-EQU ICR5L0 00000000
-EQU ICR5L1 00000001
-EQU ICR5L2 00000002
-EQU ICR5L3 00000003
-EQU ICR5L4 00000004
-EQU ICR5L5 00000005
-EQU ICR5L6 00000006
-EQU ICR5L7 00000007
-EQU TOIE4 00000000
-EQU OCIE4A 00000001
-EQU OCIE4B 00000002
-EQU OCIE4C 00000003
-EQU ICIE4 00000005
-EQU TOV4 00000000
-EQU OCF4A 00000001
-EQU OCF4B 00000002
-EQU OCF4C 00000003
-EQU ICF4 00000005
-EQU WGM40 00000000
-EQU WGM41 00000001
-EQU COM4C0 00000002
-EQU COM4C1 00000003
-EQU COM4B0 00000004
-EQU COM4B1 00000005
-EQU COM4A0 00000006
-EQU COM4A1 00000007
-EQU CS40 00000000
-EQU CS41 00000001
-EQU CS42 00000002
-EQU WGM42 00000003
-EQU WGM43 00000004
-EQU ICES4 00000006
-EQU ICNC4 00000007
-EQU FOC4C 00000005
-EQU FOC4B 00000006
-EQU FOC4A 00000007
-EQU TOIE3 00000000
-EQU OCIE3A 00000001
-EQU OCIE3B 00000002
-EQU OCIE3C 00000003
-EQU ICIE3 00000005
-EQU TOV3 00000000
-EQU OCF3A 00000001
-EQU OCF3B 00000002
-EQU OCF3C 00000003
-EQU ICF3 00000005
-EQU WGM30 00000000
-EQU WGM31 00000001
-EQU COM3C0 00000002
-EQU COM3C1 00000003
-EQU COM3B0 00000004
-EQU COM3B1 00000005
-EQU COM3A0 00000006
-EQU COM3A1 00000007
-EQU CS30 00000000
-EQU CS31 00000001
-EQU CS32 00000002
-EQU WGM32 00000003
-EQU WGM33 00000004
-EQU ICES3 00000006
-EQU ICNC3 00000007
-EQU FOC3C 00000005
-EQU FOC3B 00000006
-EQU FOC3A 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU OCIE1C 00000003
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU OCF1C 00000003
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU WGM11 00000001
-EQU COM1C0 00000002
-EQU COM1C1 00000003
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1C 00000005
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU JTD 00000007
-EQU JTRF 00000004
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC20 00000004
-EQU ISC21 00000005
-EQU ISC30 00000006
-EQU ISC31 00000007
-EQU ISC40 00000000
-EQU ISC41 00000001
-EQU ISC50 00000002
-EQU ISC51 00000003
-EQU ISC60 00000004
-EQU ISC61 00000005
-EQU ISC70 00000006
-EQU ISC71 00000007
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INT2 00000002
-EQU INT3 00000003
-EQU INT4 00000004
-EQU INT5 00000005
-EQU INT6 00000006
-EQU INT7 00000007
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU INTF2 00000002
-EQU INTF3 00000003
-EQU INTF4 00000004
-EQU INTF5 00000005
-EQU INTF6 00000006
-EQU INTF7 00000007
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT15 00000007
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU SRW00 00000000
-EQU SRW01 00000001
-EQU SRW10 00000002
-EQU SRW11 00000003
-EQU SRL0 00000004
-EQU SRL1 00000005
-EQU SRL2 00000006
-EQU SRE 00000007
-EQU XMM0 00000000
-EQU XMM1 00000001
-EQU XMM2 00000002
-EQU XMBK 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU RAMPZ0 00000000
-EQU RAMPZ1 00000001
-EQU EIND0 00000000
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRUSART1 00000000
-EQU PRUSART2 00000001
-EQU PRUSART3 00000002
-EQU PRTIM3 00000003
-EQU PRTIM4 00000004
-EQU PRTIM5 00000005
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU MUX5 00000003
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ADC6D 00000006
-EQU ADC7D 00000007
-EQU ADC8D 00000000
-EQU ADC9D 00000001
-EQU ADC10D 00000002
-EQU ADC11D 00000003
-EQU ADC12D 00000004
-EQU ADC13D 00000005
-EQU ADC14D 00000006
-EQU ADC15D 00000007
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU SIGRD 00000005
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 0001ffff
-EQU IOEND 000001ff
-EQU SRAM_START 00000200
-EQU SRAM_SIZE 00002000
-EQU RAMEND 000021ff
-EQU XRAMEND 0000ffff
-EQU E2END 00000fff
-EQU EEPROMEND 00000fff
-EQU EEADRBITS 0000000c
-EQU NRWW_START_ADDR 0001f000
-EQU NRWW_STOP_ADDR 0001ffff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 0001efff
-EQU PAGESIZE 00000080
-EQU FIRSTBOOTSTART 0001fe00
-EQU SECONDBOOTSTART 0001fc00
-EQU THIRDBOOTSTART 0001f800
-EQU FOURTHBOOTSTART 0001f000
-EQU SMALLBOOTSTART 0001fe00
-EQU LARGEBOOTSTART 0001f000
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU INT3addr 00000008
-EQU INT4addr 0000000a
-EQU INT5addr 0000000c
-EQU INT6addr 0000000e
-EQU INT7addr 00000010
-EQU PCI0addr 00000012
-EQU PCI1addr 00000014
-EQU PCI2addr 00000016
-EQU WDTaddr 00000018
-EQU OC2Aaddr 0000001a
-EQU OC2Baddr 0000001c
-EQU OVF2addr 0000001e
-EQU ICP1addr 00000020
-EQU OC1Aaddr 00000022
-EQU OC1Baddr 00000024
-EQU OC1Caddr 00000026
-EQU OVF1addr 00000028
-EQU OC0Aaddr 0000002a
-EQU OC0Baddr 0000002c
-EQU OVF0addr 0000002e
-EQU SPIaddr 00000030
-EQU URXC0addr 00000032
-EQU UDRE0addr 00000034
-EQU UTXC0addr 00000036
-EQU ACIaddr 00000038
-EQU ADCCaddr 0000003a
-EQU ERDYaddr 0000003c
-EQU ICP3addr 0000003e
-EQU OC3Aaddr 00000040
-EQU OC3Baddr 00000042
-EQU OC3Caddr 00000044
-EQU OVF3addr 00000046
-EQU URXC1addr 00000048
-EQU UDRE1addr 0000004a
-EQU UTXC1addr 0000004c
-EQU TWIaddr 0000004e
-EQU SPMRaddr 00000050
-EQU ICP4addr 00000052
-EQU OC4Aaddr 00000054
-EQU OC4Baddr 00000056
-EQU OC4Caddr 00000058
-EQU OVF4addr 0000005a
-EQU ICP5addr 0000005c
-EQU OC5Aaddr 0000005e
-EQU OC5Baddr 00000060
-EQU OC5Caddr 00000062
-EQU OVF5addr 00000064
-EQU URXC2addr 00000066
-EQU UDRE2addr 00000068
-EQU UTXC2addr 0000006a
-EQU URXC3addr 0000006c
-EQU UDRE3addr 0000006e
-EQU UTXC3addr 00000070
-EQU INT_VECTORS_SIZE 00000072
-EQU ramstart 00000200
-EQU CELLSIZE 00000002
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_USART0 00000000
-SET WANT_TWI 00000000
-SET WANT_SPI 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_PORTE 00000000
-SET WANT_PORTF 00000000
-SET WANT_PORTG 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_USART1 00000000
-SET WANT_EEPROM 00000000
-SET WANT_TIMER_COUNTER_5 00000000
-SET WANT_TIMER_COUNTER_4 00000000
-SET WANT_TIMER_COUNTER_3 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_JTAG 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_CPU 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_BOOT_LOAD 00000000
-EQU intvecsize 00000002
-EQU pclen 00000003
-CSEG isr 0000013c
-EQU INTVECTORS 00000039
-CSEG mcu_info 00000071
-CSEG mcu_ramsize 00000071
-CSEG mcu_eepromsize 00000072
-CSEG mcu_maxdp 00000073
-CSEG mcu_numints 00000074
-CSEG mcu_name 00000075
-SET codestart 0000007b
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000021ff
-SET stackstart 000021af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000000a
-SET VE_HEAD 0000127b
-SET VE_ENVHEAD 00000996
-SET AMFORTH_RO_SEG 0001f000
-EQU F_CPU 00e10000
-EQU BAUDRATE_LOW 000000cc
-EQU BAUDRATE_HIGH 000000cd
-EQU USART_C 000000ca
-EQU USART_B 000000c9
-EQU USART_A 000000c8
-EQU USART_DATA 000000ce
-EQU URXCaddr 00000048
-EQU UDREaddr 0000004a
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000200
-DSEG usart_rx_in 00000210
-DSEG usart_rx_out 00000211
-CSEG VE_TO_RXBUF 0000007b
-CSEG XT_TO_RXBUF 00000081
-CSEG PFA_rx_tobuf 00000082
-CSEG DO_NEXT 0000011f
-CSEG VE_ISR_RX 00000092
-CSEG XT_ISR_RX 00000097
-CSEG DO_COLON 0000011b
-CSEG usart_rx_isr 00000098
-CSEG XT_DOLITERAL 000004ce
-CSEG XT_CFETCH 00000531
-CSEG XT_DUP 0000054a
-CSEG XT_EQUAL 0000126d
-CSEG XT_DOCONDBRANCH 000004c7
-CSEG usart_rx_isr1 000000a2
-CSEG XT_COLD 00000ebf
-CSEG XT_EXIT 000004ae
-CSEG XT_USART_INIT_RX_BUFFER 000000a4
-CSEG PFA_USART_INIT_RX_BUFFER 000000a5
-CSEG XT_INTSTORE 000008eb
-CSEG XT_ZERO 000005ed
-CSEG XT_FILL 00000933
-CSEG VE_RX_BUFFER 000000b1
-CSEG XT_RX_BUFFER 000000b6
-CSEG PFA_RX_BUFFER 000000b7
-CSEG XT_RXQ_BUFFER 000000d1
-CSEG XT_PLUS 00000636
-CSEG XT_SWAP 0000055d
-CSEG XT_1PLUS 000006c8
-CSEG XT_AND 000006ac
-CSEG XT_CSTORE 00000526
-CSEG VE_RXQ_BUFFER 000000cb
-CSEG PFA_RXQ_BUFFER 000000d2
-CSEG XT_PAUSE 00000eb7
-CSEG XT_NOTEQUAL 000005ac
-SET XT_RX 000000b6
-SET XT_RXQ 000000d1
-SET XT_USART_INIT_RX 000000a4
-CSEG VE_TX_POLL 000000db
-CSEG XT_TX_POLL 000000e1
-CSEG PFA_TX_POLL 000000e2
-CSEG XT_TXQ_POLL 000000ef
-CSEG VE_TXQ_POLL 000000e9
-CSEG PFA_TXQ_POLL 000000f0
-SET XT_TX 000000e1
-SET XT_TXQ 000000ef
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000f8
-CSEG XT_UBRR 000000fc
-CSEG PFA_DOVALUE1 00000509
-CSEG PFA_UBRR 000000fd
-ESEG EE_UBRRVAL 000000ca
-CSEG XT_EDEFERFETCH 0000101a
-CSEG XT_EDEFERSTORE 00001024
-CSEG VE_USART 00000100
-CSEG XT_USART 00000105
-CSEG PFA_USART 00000106
-CSEG XT_BYTESWAP 00000792
-SET pc_ 0000011b
-CSEG PFA_COLD 00000ec0
-CSEG DO_INTERRUPT 00000134
-CSEG DO_EXECUTE 0000012a
-CSEG XT_ISREXEC 00000906
-ESEG intvec 00000000
-DSEG intcnt 00000212
-SET AMFORTH_NRWW_SIZE 00001ffe
-CSEG VE_MPLUS 00000154
-CSEG XT_MPLUS 00000157
-CSEG PFA_MPLUS 00000158
-CSEG XT_S2D 00001255
-CSEG XT_DPLUS 00000879
-CSEG VE_UDSTAR 0000015b
-CSEG XT_UDSTAR 0000015f
-CSEG PFA_UDSTAR 00000160
-CSEG XT_TO_R 00000598
-CSEG XT_UMSTAR 00000679
-CSEG XT_DROP 00000572
-CSEG XT_R_FROM 0000058f
-CSEG XT_ROT 0000057a
-CSEG VE_UMAX 0000016a
-CSEG XT_UMAX 0000016e
-CSEG PFA_UMAX 0000016f
-CSEG XT_2DUP 000009ca
-CSEG XT_ULESS 000005f5
-CSEG UMAX1 00000174
-CSEG VE_UMIN 00000176
-CSEG XT_UMIN 0000017a
-CSEG PFA_UMIN 0000017b
-CSEG XT_UGREATER 00000600
-CSEG UMIN1 00000180
-CSEG XT_IMMEDIATEQ 00000182
-CSEG PFA_IMMEDIATEQ 00000183
-CSEG XT_ZEROEQUAL 000005b3
-CSEG IMMEDIATEQ1 0000018b
-CSEG XT_ONE 00001274
-CSEG XT_TRUE 000005e4
-CSEG VE_NAME2FLAGS 0000018d
-CSEG XT_NAME2FLAGS 00000194
-CSEG PFA_NAME2FLAGS 00000195
-CSEG XT_FETCHI 0000082c
-CSEG VE_NEWEST 0000019a
-CSEG XT_NEWEST 0000019f
-CSEG PFA_DOVARIABLE 000004dc
-CSEG PFA_NEWEST 000001a0
-DSEG ram_newest 0000024b
-CSEG VE_LATEST 000001a1
-CSEG XT_LATEST 000001a6
-CSEG PFA_LATEST 000001a7
-DSEG ram_latest 0000024f
-CSEG VE_DOCREATE 000001a8
-CSEG XT_DOCREATE 000001ae
-CSEG PFA_DOCREATE 000001af
-CSEG XT_PARSENAME 00000e1a
-CSEG XT_WLSCOPE 00000305
-CSEG XT_CELLPLUS 000009c2
-CSEG XT_STORE 0000051a
-CSEG XT_HEADER 000002ea
-CSEG VE_BACKSLASH 000001b9
-CSEG XT_BACKSLASH 000001bc
-CSEG PFA_BACKSLASH 000001bd
-CSEG XT_SOURCE 00000e01
-CSEG XT_NIP 00000589
-CSEG XT_TO_IN 000009e3
-CSEG VE_LPAREN 000001c2
-CSEG XT_LPAREN 000001c5
-CSEG PFA_LPAREN 000001c6
-CSEG XT_PARSE 00000ded
-CSEG XT_2DROP 000009d3
-CSEG VE_COMPILE 000001cb
-CSEG XT_COMPILE 000001d1
-CSEG PFA_COMPILE 000001d2
-CSEG XT_ICELLPLUS 00001011
-CSEG XT_COMMA 000001dc
-CSEG VE_COMMA 000001d9
-CSEG PFA_COMMA 000001dd
-CSEG XT_DP 00000a13
-CSEG XT_STOREI 0000080d
-CSEG XT_DOTO 00000fff
-CSEG PFA_DP 00000a14
-CSEG VE_BRACKETTICK 000001e4
-CSEG XT_BRACKETTICK 000001e8
-CSEG PFA_BRACKETTICK 000001e9
-CSEG XT_TICK 00000c70
-CSEG XT_LITERAL 000001f2
-CSEG VE_LITERAL 000001ec
-CSEG PFA_LITERAL 000001f3
-CSEG VE_SLITERAL 000001f7
-CSEG XT_SLITERAL 000001fd
-CSEG PFA_SLITERAL 000001fe
-CSEG XT_DOSLITERAL 00000bd3
-CSEG XT_SCOMMA 00000be1
-CSEG XT_GMARK 00000202
-CSEG PFA_GMARK 00000203
-CSEG XT_GRESOLVE 00000207
-CSEG PFA_GRESOLVE 00000208
-CSEG XT_QSTACK 00000fbd
-CSEG XT_LMARK 0000020d
-CSEG PFA_LMARK 0000020e
-CSEG XT_LRESOLVE 00000210
-CSEG PFA_LRESOLVE 00000211
-CSEG VE_AHEAD 00000214
-CSEG XT_AHEAD 00000219
-CSEG PFA_AHEAD 0000021a
-CSEG XT_DOBRANCH 000004bd
-CSEG VE_IF 0000021e
-CSEG XT_IF 00000221
-CSEG PFA_IF 00000222
-CSEG VE_ELSE 00000226
-CSEG XT_ELSE 0000022a
-CSEG PFA_ELSE 0000022b
-CSEG VE_THEN 00000231
-CSEG XT_THEN 00000235
-CSEG PFA_THEN 00000236
-CSEG VE_BEGIN 00000238
-CSEG XT_BEGIN 0000023d
-CSEG PFA_BEGIN 0000023e
-CSEG VE_WHILE 00000240
-CSEG XT_WHILE 00000245
-CSEG PFA_WHILE 00000246
-CSEG VE_REPEAT 00000249
-CSEG XT_REPEAT 0000024e
-CSEG PFA_REPEAT 0000024f
-CSEG XT_AGAIN 00000262
-CSEG VE_UNTIL 00000252
-CSEG XT_UNTIL 00000257
-CSEG PFA_UNTIL 00000258
-CSEG VE_AGAIN 0000025d
-CSEG PFA_AGAIN 00000263
-CSEG VE_DO 00000267
-CSEG XT_DO 0000026a
-CSEG PFA_DO 0000026b
-CSEG XT_DODO 00000734
-CSEG XT_TO_L 000002c5
-CSEG VE_LOOP 00000271
-CSEG XT_LOOP 00000275
-CSEG PFA_LOOP 00000276
-CSEG XT_DOLOOP 00000762
-CSEG XT_ENDLOOP 000002ac
-CSEG VE_PLUSLOOP 0000027a
-CSEG XT_PLUSLOOP 0000027f
-CSEG PFA_PLUSLOOP 00000280
-CSEG XT_DOPLUSLOOP 00000753
-CSEG VE_LEAVE 00000284
-CSEG XT_LEAVE 00000289
-CSEG PFA_LEAVE 0000028a
-CSEG XT_UNLOOP 0000076d
-CSEG VE_QDO 0000028f
-CSEG XT_QDO 00000293
-CSEG PFA_QDO 00000294
-CSEG XT_QDOCHECK 0000029b
-CSEG PFA_QDOCHECK 0000029c
-CSEG PFA_QDOCHECK1 000002a3
-CSEG XT_INVERT 00000696
-CSEG VE_ENDLOOP 000002a6
-CSEG PFA_ENDLOOP 000002ad
-CSEG LOOP1 000002ae
-CSEG XT_L_FROM 000002b9
-CSEG XT_QDUP 00000552
-CSEG LOOP2 000002b5
-CSEG VE_L_FROM 000002b6
-CSEG PFA_L_FROM 000002ba
-CSEG XT_LP 000002d8
-CSEG XT_FETCH 00000512
-CSEG XT_PLUSSTORE 000006fe
-CSEG VE_TO_L 000002c2
-CSEG PFA_TO_L 000002c6
-CSEG XT_TWO 00001279
-CSEG VE_LP0 000002cd
-CSEG XT_LP0 000002d1
-CSEG PFA_LP0 000002d2
-ESEG CFG_LP0 0000007e
-CSEG VE_LP 000002d5
-CSEG PFA_LP 000002d9
-DSEG ram_lp 00000251
-CSEG VE_CREATE 000002da
-CSEG XT_CREATE 000002df
-CSEG PFA_CREATE 000002e0
-CSEG XT_REVEAL 0000030e
-CSEG PFA_DOCONSTANT 000004e9
-CSEG VE_HEADER 000002e5
-CSEG PFA_HEADER 000002eb
-CSEG XT_GREATERZERO 000005c1
-CSEG PFA_HEADER1 000002fc
-CSEG XT_OR 000006b5
-CSEG XT_DOSCOMMA 00000be5
-CSEG XT_FETCHE 000007f9
-CSEG XT_THROW 00000ca7
-CSEG VE_WLSCOPE 000002ff
-CSEG PFA_DODEFER1 00001079
-CSEG PFA_WLSCOPE 00000306
-ESEG CFG_WLSCOPE 0000007a
-CSEG VE_REVEAL 00000309
-CSEG PFA_REVEAL 0000030f
-CSEG REVEAL1 00000319
-CSEG XT_STOREE 000007d5
-CSEG VE_DOES 0000031a
-CSEG XT_DOES 0000031f
-CSEG PFA_DOES 00000320
-CSEG XT_DODOES 00000332
-CSEG DO_DODOES 00000327
-CSEG PFA_DODOES 00000333
-CSEG XT_NFA2CFA 000010e4
-CSEG VE_COLON 0000033b
-CSEG XT_COLON 0000033e
-CSEG PFA_COLON 0000033f
-CSEG XT_COLONNONAME 00000349
-CSEG VE_COLONNONAME 00000343
-CSEG PFA_COLONNONAME 0000034a
-CSEG XT_RBRACKET 0000035e
-CSEG VE_SEMICOLON 00000352
-CSEG XT_SEMICOLON 00000355
-CSEG PFA_SEMICOLON 00000356
-CSEG XT_LBRACKET 00000366
-CSEG VE_RBRACKET 0000035b
-CSEG PFA_RBRACKET 0000035f
-CSEG XT_STATE 000009af
-CSEG VE_LBRACKET 00000363
-CSEG PFA_LBRACKET 00000367
-CSEG VE_VARIABLE 0000036b
-CSEG XT_VARIABLE 00000371
-CSEG PFA_VARIABLE 00000372
-CSEG XT_HERE 00000a24
-CSEG XT_CONSTANT 0000037d
-CSEG XT_ALLOT 00000a2d
-CSEG VE_CONSTANT 00000377
-CSEG PFA_CONSTANT 0000037e
-CSEG VE_USER 00000384
-CSEG XT_USER 00000388
-CSEG PFA_USER 00000389
-CSEG PFA_DOUSER 000004ef
-CSEG VE_RECURSE 0000038f
-CSEG XT_RECURSE 00000395
-CSEG PFA_RECURSE 00000396
-CSEG VE_IMMEDIATE 0000039a
-CSEG XT_IMMEDIATE 000003a1
-CSEG PFA_IMMEDIATE 000003a2
-CSEG XT_GET_CURRENT 00000443
-CSEG VE_BRACKETCHAR 000003ac
-CSEG XT_BRACKETCHAR 000003b1
-CSEG PFA_BRACKETCHAR 000003b2
-CSEG XT_CHAR 00000d50
-CSEG VE_ABORTQUOTE 000003b7
-CSEG XT_ABORTQUOTE 000003bc
-CSEG PFA_ABORTQUOTE 000003bd
-CSEG XT_SQUOTE 00000925
-CSEG XT_QABORT 000003ce
-CSEG VE_ABORT 000003c1
-CSEG XT_ABORT 000003c6
-CSEG PFA_ABORT 000003c7
-CSEG VE_QABORT 000003c9
-CSEG PFA_QABORT 000003cf
-CSEG QABO1 000003d4
-CSEG XT_ITYPE 00000c06
-CSEG VE_GET_STACK 000003d6
-CSEG XT_GET_STACK 000003dd
-CSEG PFA_N_FETCH_E2 000003f4
-CSEG PFA_N_FETCH_E1 000003ea
-CSEG XT_I 00000745
-CSEG XT_1MINUS 000006ce
-CSEG XT_CELLS 000009bc
-CSEG XT_OVER 00000568
-CSEG VE_SET_STACK 000003f7
-CSEG XT_SET_STACK 000003fe
-CSEG PFA_SET_STACK 000003ff
-CSEG XT_ZEROLESS 000005ba
-CSEG PFA_SET_STACK0 00000406
-CSEG PFA_SET_STACK2 00000413
-CSEG PFA_SET_STACK1 0000040e
-CSEG XT_TUCK 000009db
-CSEG VE_MAPSTACK 00000415
-CSEG XT_MAPSTACK 0000041c
-CSEG PFA_MAPSTACK 0000041d
-CSEG XT_BOUNDS 0000124c
-CSEG PFA_MAPSTACK3 00000438
-CSEG PFA_MAPSTACK1 00000427
-CSEG XT_R_FETCH 000005a1
-CSEG XT_EXECUTE 000004b8
-CSEG PFA_MAPSTACK2 00000434
-CSEG VE_GET_CURRENT 0000043b
-CSEG PFA_GET_CURRENT 00000444
-ESEG CFG_CURRENT 00000084
-CSEG VE_GET_ORDER 00000448
-CSEG XT_GET_ORDER 0000044f
-CSEG PFA_GET_ORDER 00000450
-ESEG CFG_ORDERLISTLEN 00000088
-CSEG VE_CFG_ORDER 00000454
-CSEG XT_CFG_ORDER 0000045b
-CSEG PFA_CFG_ORDER 0000045c
-CSEG VE_COMPARE 0000045d
-CSEG XT_COMPARE 00000463
-CSEG PFA_COMPARE 00000464
-CSEG PFA_COMPARE_LOOP 00000470
-CSEG PFA_COMPARE_NOTEQUAL 0000047e
-CSEG PFA_COMPARE_ENDREACHED2 00000479
-CSEG PFA_COMPARE_ENDREACHED 0000047a
-CSEG PFA_COMPARE_CHECKLASTCHAR 0000047e
-CSEG PFA_COMPARE_DONE 00000480
-CSEG VE_NFA2LFA 00000484
-CSEG XT_NFA2LFA 0000048a
-CSEG PFA_NFA2LFA 0000048b
-CSEG XT_NAME2STRING 000010d8
-CSEG XT_2SLASH 0000069d
-CSEG VE_APPLTURNKEY 00000490
-CSEG XT_APPLTURNKEY 00000498
-CSEG PFA_APPLTURNKEY 00000499
-CSEG XT_INTON 000008dd
-CSEG XT_DOT_VER 00000fca
-CSEG XT_SPACE 00000c48
-CSEG XT_F_CPU 000009a4
-CSEG XT_UMSLASHMOD 0000065b
-CSEG XT_DECIMAL 00000a42
-CSEG XT_DOT 00000b88
-CSEG VE_EXIT 000004aa
-CSEG PFA_EXIT 000004af
-CSEG VE_EXECUTE 000004b2
-CSEG PFA_EXECUTE 000004b9
-CSEG PFA_DOBRANCH 000004be
-CSEG PFA_DOCONDBRANCH 000004c8
-CSEG PFA_DOLITERAL 000004cf
-CSEG XT_DOVARIABLE 000004db
-CSEG XT_DOCONSTANT 000004e8
-CSEG XT_DOUSER 000004ee
-CSEG VE_DOVALUE 000004fd
-CSEG XT_DOVALUE 00000503
-CSEG PFA_DOVALUE 00000504
-CSEG VE_FETCH 0000050f
-CSEG PFA_FETCH 00000513
-CSEG PFA_FETCHRAM 00000513
-CSEG VE_STORE 00000517
-CSEG PFA_STORE 0000051b
-CSEG PFA_STORERAM 0000051b
-CSEG VE_CSTORE 00000523
-CSEG PFA_CSTORE 00000527
-CSEG VE_CFETCH 0000052e
-CSEG PFA_CFETCH 00000532
-CSEG VE_FETCHU 00000536
-CSEG XT_FETCHU 00000539
-CSEG PFA_FETCHU 0000053a
-CSEG XT_UP_FETCH 0000079b
-CSEG VE_STOREU 0000053e
-CSEG XT_STOREU 00000541
-CSEG PFA_STOREU 00000542
-CSEG VE_DUP 00000546
-CSEG PFA_DUP 0000054b
-CSEG VE_QDUP 0000054e
-CSEG PFA_QDUP 00000553
-CSEG PFA_QDUP1 00000558
-CSEG VE_SWAP 00000559
-CSEG PFA_SWAP 0000055e
-CSEG VE_OVER 00000564
-CSEG PFA_OVER 00000569
-CSEG VE_DROP 0000056e
-CSEG PFA_DROP 00000573
-CSEG VE_ROT 00000576
-CSEG PFA_ROT 0000057b
-CSEG VE_NIP 00000585
-CSEG PFA_NIP 0000058a
-CSEG VE_R_FROM 0000058c
-CSEG PFA_R_FROM 00000590
-CSEG VE_TO_R 00000595
-CSEG PFA_TO_R 00000599
-CSEG VE_R_FETCH 0000059e
-CSEG PFA_R_FETCH 000005a2
-CSEG VE_NOTEQUAL 000005a9
-CSEG PFA_NOTEQUAL 000005ad
-CSEG VE_ZEROEQUAL 000005b0
-CSEG PFA_ZEROEQUAL 000005b4
-CSEG PFA_ZERO1 000005f0
-CSEG PFA_TRUE1 000005e7
-CSEG VE_ZEROLESS 000005b7
-CSEG PFA_ZEROLESS 000005bb
-CSEG VE_GREATERZERO 000005be
-CSEG PFA_GREATERZERO 000005c2
-CSEG VE_DGREATERZERO 000005c7
-CSEG XT_DGREATERZERO 000005cb
-CSEG PFA_DGREATERZERO 000005cc
-CSEG VE_DXT_ZEROLESS 000005d5
-CSEG XT_DXT_ZEROLESS 000005d9
-CSEG PFA_DXT_ZEROLESS 000005da
-CSEG VE_TRUE 000005e0
-CSEG PFA_TRUE 000005e5
-CSEG VE_ZERO 000005ea
-CSEG PFA_ZERO 000005ee
-CSEG VE_ULESS 000005f2
-CSEG PFA_ULESS 000005f6
-CSEG VE_UGREATER 000005fd
-CSEG PFA_UGREATER 00000601
-CSEG VE_LESS 00000604
-CSEG XT_LESS 00000607
-CSEG PFA_LESS 00000608
-CSEG PFA_LESSDONE 0000060c
-CSEG VE_GREATER 0000060e
-CSEG XT_GREATER 00000611
-CSEG PFA_GREATER 00000612
-CSEG PFA_GREATERDONE 00000616
-CSEG VE_LOG2 00000619
-CSEG XT_LOG2 0000061d
-CSEG PFA_LOG2 0000061e
-CSEG PFA_LOG2_1 00000621
-CSEG PFA_LOG2_2 00000627
-CSEG VE_MINUS 00000629
-CSEG XT_MINUS 0000062c
-CSEG PFA_MINUS 0000062d
-CSEG VE_PLUS 00000633
-CSEG PFA_PLUS 00000637
-CSEG VE_MSTAR 0000063c
-CSEG XT_MSTAR 0000063f
-CSEG PFA_MSTAR 00000640
-CSEG VE_UMSLASHMOD 00000656
-CSEG PFA_UMSLASHMOD 0000065c
-CSEG PFA_UMSLASHMODmod 00000661
-CSEG PFA_UMSLASHMODmod_loop 00000662
-CSEG PFA_UMSLASHMODmod_loop_control 0000066f
-CSEG PFA_UMSLASHMODmod_subtract 0000066c
-CSEG PFA_UMSLASHMODmod_done 00000671
-CSEG VE_UMSTAR 00000675
-CSEG PFA_UMSTAR 0000067a
-CSEG VE_INVERT 00000691
-CSEG PFA_INVERT 00000697
-CSEG VE_2SLASH 0000069a
-CSEG PFA_2SLASH 0000069e
-CSEG VE_2STAR 000006a1
-CSEG XT_2STAR 000006a4
-CSEG PFA_2STAR 000006a5
-CSEG VE_AND 000006a8
-CSEG PFA_AND 000006ad
-CSEG VE_OR 000006b2
-CSEG PFA_OR 000006b6
-CSEG VE_XOR 000006bb
-CSEG XT_XOR 000006bf
-CSEG PFA_XOR 000006c0
-CSEG VE_1PLUS 000006c5
-CSEG PFA_1PLUS 000006c9
-CSEG VE_1MINUS 000006cb
-CSEG PFA_1MINUS 000006cf
-CSEG VE_QNEGATE 000006d1
-CSEG XT_QNEGATE 000006d7
-CSEG PFA_QNEGATE 000006d8
-CSEG QNEG1 000006dc
-CSEG XT_NEGATE 00000aa5
-CSEG VE_LSHIFT 000006dd
-CSEG XT_LSHIFT 000006e2
-CSEG PFA_LSHIFT 000006e3
-CSEG PFA_LSHIFT1 000006e6
-CSEG PFA_LSHIFT2 000006eb
-CSEG VE_RSHIFT 000006ec
-CSEG XT_RSHIFT 000006f1
-CSEG PFA_RSHIFT 000006f2
-CSEG PFA_RSHIFT1 000006f5
-CSEG PFA_RSHIFT2 000006fa
-CSEG VE_PLUSSTORE 000006fb
-CSEG PFA_PLUSSTORE 000006ff
-CSEG VE_RP_FETCH 0000070b
-CSEG XT_RP_FETCH 0000070f
-CSEG PFA_RP_FETCH 00000710
-CSEG VE_RP_STORE 00000715
-CSEG XT_RP_STORE 00000719
-CSEG PFA_RP_STORE 0000071a
-CSEG VE_SP_FETCH 00000722
-CSEG XT_SP_FETCH 00000726
-CSEG PFA_SP_FETCH 00000727
-CSEG VE_SP_STORE 0000072b
-CSEG XT_SP_STORE 0000072f
-CSEG PFA_SP_STORE 00000730
-CSEG PFA_DODO 00000735
-CSEG PFA_DODO1 00000737
-CSEG VE_I 00000742
-CSEG PFA_I 00000746
-CSEG PFA_DOPLUSLOOP 00000754
-CSEG PFA_DOPLUSLOOP_LEAVE 0000075e
-CSEG PFA_DOPLUSLOOP_NEXT 0000075b
-CSEG PFA_DOLOOP 00000763
-CSEG VE_UNLOOP 00000768
-CSEG PFA_UNLOOP 0000076e
-CSEG VE_CMOVE_G 00000773
-CSEG XT_CMOVE_G 00000778
-CSEG PFA_CMOVE_G 00000779
-CSEG PFA_CMOVE_G1 0000078a
-CSEG PFA_CMOVE_G2 00000786
-CSEG VE_BYTESWAP 0000078f
-CSEG PFA_BYTESWAP 00000793
-CSEG VE_UP_FETCH 00000797
-CSEG PFA_UP_FETCH 0000079c
-CSEG VE_UP_STORE 000007a0
-CSEG XT_UP_STORE 000007a4
-CSEG PFA_UP_STORE 000007a5
-CSEG VE_1MS 000007a9
-CSEG XT_1MS 000007ad
-CSEG PFA_1MS 000007ae
-SET cycles 00000001
-SET loop_cycles 00000e66
-CSEG VE_2TO_R 000007b4
-CSEG XT_2TO_R 000007b8
-CSEG PFA_2TO_R 000007b9
-CSEG VE_2R_FROM 000007c3
-CSEG XT_2R_FROM 000007c7
-CSEG PFA_2R_FROM 000007c8
-CSEG VE_STOREE 000007d2
-CSEG PFA_STOREE 000007d6
-CSEG PFA_STOREE0 000007d6
-CSEG PFA_FETCHE2 00000804
-CSEG PFA_STOREE3 000007e0
-CSEG PFA_STOREE1 000007eb
-CSEG PFA_STOREE4 000007e7
-CSEG PFA_STOREE2 000007ed
-CSEG VE_FETCHE 000007f6
-CSEG PFA_FETCHE 000007fa
-CSEG PFA_FETCHE1 000007fa
-CSEG VE_STOREI 0000080a
-CSEG PFA_STOREI 0000080e
-ESEG EE_STOREI 000000a4
-CSEG VE_DO_STOREI_BIG 00000811
-CSEG XT_DO_STOREI 00000815
-CSEG PFA_DO_STOREI_BIG 00000816
-CSEG DO_STOREI_atmega 0001f000
-SET _pc 00000829
-CSEG pageload 0001f011
-CSEG DO_STOREI_writepage 0001f00a
-CSEG dospm 0001f02d
-EQU pagemask ffffff80
-CSEG pageload_loop 0001f017
-CSEG pageload_newdata 0001f025
-CSEG pageload_cont 0001f027
-CSEG pageload_done 0001f02c
-CSEG Wait_ee 0001f030
-CSEG wait_spm 0001f032
-CSEG VE_FETCHI 00000829
-CSEG PFA_FETCHI 0000082d
-CSEG VE_N_TO_R 00000836
-CSEG XT_N_TO_R 0000083a
-CSEG PFA_N_TO_R 0000083b
-CSEG PFA_N_TO_R1 0000083d
-CSEG VE_N_R_FROM 00000848
-CSEG XT_N_R_FROM 0000084c
-CSEG PFA_N_R_FROM 0000084d
-CSEG PFA_N_R_FROM1 00000852
-CSEG VE_D2STAR 0000085a
-CSEG XT_D2STAR 0000085e
-CSEG PFA_D2STAR 0000085f
-CSEG VE_D2SLASH 00000868
-CSEG XT_D2SLASH 0000086c
-CSEG PFA_D2SLASH 0000086d
-CSEG VE_DPLUS 00000876
-CSEG PFA_DPLUS 0000087a
-CSEG VE_DMINUS 00000887
-CSEG XT_DMINUS 0000088a
-CSEG PFA_DMINUS 0000088b
-CSEG VE_DINVERT 00000899
-CSEG XT_DINVERT 0000089f
-CSEG PFA_DINVERT 000008a0
-CSEG VE_UDOT 000008a9
-CSEG XT_UDOT 000008ac
-CSEG PFA_UDOT 000008ad
-CSEG XT_UDDOT 00000b90
-CSEG VE_UDOTR 000008b0
-CSEG XT_UDOTR 000008b4
-CSEG PFA_UDOTR 000008b5
-CSEG XT_UDDOTR 00000b99
-CSEG VE_SHOWWORDLIST 000008b9
-CSEG XT_SHOWWORDLIST 000008c2
-CSEG PFA_SHOWWORDLIST 000008c3
-CSEG XT_SHOWWORD 000008c8
-CSEG XT_TRAVERSEWORDLIST 000010bd
-CSEG PFA_SHOWWORD 000008c9
-CSEG VE_WORDS 000008ce
-CSEG XT_WORDS 000008d3
-CSEG PFA_WORDS 000008d4
-CSEG VE_INTON 000008d9
-CSEG PFA_INTON 000008de
-CSEG VE_INTOFF 000008e0
-CSEG XT_INTOFF 000008e4
-CSEG PFA_INTOFF 000008e5
-CSEG VE_INTSTORE 000008e7
-CSEG PFA_INTSTORE 000008ec
-CSEG VE_INTFETCH 000008f1
-CSEG XT_INTFETCH 000008f5
-CSEG PFA_INTFETCH 000008f6
-CSEG VE_INTTRAP 000008fb
-CSEG XT_INTTRAP 00000901
-CSEG PFA_INTTRAP 00000902
-CSEG PFA_ISREXEC 00000907
-CSEG XT_ISREND 0000090b
-CSEG PFA_ISREND 0000090c
-CSEG PFA_ISREND1 0000090e
-CSEG VE_PICK 0000090f
-CSEG XT_PICK 00000913
-CSEG PFA_PICK 00000914
-CSEG VE_DOTSTRING 0000091a
-CSEG XT_DOTSTRING 0000091d
-CSEG PFA_DOTSTRING 0000091e
-CSEG VE_SQUOTE 00000922
-CSEG PFA_SQUOTE 00000926
-CSEG PFA_SQUOTE1 0000092e
-CSEG VE_FILL 0000092f
-CSEG PFA_FILL 00000934
-CSEG PFA_FILL2 00000940
-CSEG PFA_FILL1 0000093b
-CSEG VE_ENVIRONMENT 00000942
-CSEG XT_ENVIRONMENT 0000094a
-CSEG PFA_ENVIRONMENT 0000094b
-ESEG CFG_ENVIRONMENT 00000082
-CSEG VE_ENVWORDLISTS 0000094c
-CSEG XT_ENVWORDLISTS 00000953
-CSEG PFA_ENVWORDLISTS 00000954
-CSEG VE_ENVSLASHPAD 00000957
-CSEG XT_ENVSLASHPAD 0000095b
-CSEG PFA_ENVSLASHPAD 0000095c
-CSEG XT_PAD 000009e9
-CSEG VE_ENVSLASHHOLD 00000960
-CSEG XT_ENVSLASHHOLD 00000965
-CSEG PFA_ENVSLASHHOLD 00000966
-CSEG VE_ENV_FORTHNAME 0000096a
-CSEG XT_ENV_FORTHNAME 00000971
-CSEG PFA_EN_FORTHNAME 00000972
-CSEG VE_ENV_FORTHVERSION 00000979
-CSEG XT_ENV_FORTHVERSION 0000097f
-CSEG PFA_EN_FORTHVERSION 00000980
-CSEG VE_ENV_CPU 00000983
-CSEG XT_ENV_CPU 00000987
-CSEG PFA_EN_CPU 00000988
-CSEG XT_ICOUNT 00000c32
-CSEG VE_ENV_MCUINFO 0000098c
-CSEG XT_ENV_MCUINFO 00000992
-CSEG PFA_EN_MCUINFO 00000993
-CSEG VE_ENVUSERSIZE 00000996
-CSEG XT_ENVUSERSIZE 0000099b
-CSEG PFA_ENVUSERSIZE 0000099c
-CSEG VE_F_CPU 0000099f
-CSEG PFA_F_CPU 000009a5
-CSEG VE_STATE 000009aa
-CSEG PFA_STATE 000009b0
-DSEG ram_state 00000253
-CSEG VE_BASE 000009b1
-CSEG XT_BASE 000009b5
-CSEG PFA_BASE 000009b6
-CSEG VE_CELLS 000009b7
-CSEG VE_CELLPLUS 000009bd
-CSEG PFA_CELLPLUS 000009c3
-CSEG VE_2DUP 000009c6
-CSEG PFA_2DUP 000009cb
-CSEG VE_2DROP 000009ce
-CSEG PFA_2DROP 000009d4
-CSEG VE_TUCK 000009d7
-CSEG PFA_TUCK 000009dc
-CSEG VE_TO_IN 000009df
-CSEG PFA_TO_IN 000009e4
-CSEG VE_PAD 000009e5
-CSEG PFA_PAD 000009ea
-CSEG VE_EMIT 000009ef
-CSEG XT_EMIT 000009f3
-CSEG PFA_EMIT 000009f4
-CSEG XT_UDEFERFETCH 00001042
-CSEG XT_UDEFERSTORE 0000104e
-CSEG VE_EMITQ 000009f7
-CSEG XT_EMITQ 000009fc
-CSEG PFA_EMITQ 000009fd
-CSEG VE_KEY 00000a00
-CSEG XT_KEY 00000a04
-CSEG PFA_KEY 00000a05
-CSEG VE_KEYQ 00000a08
-CSEG XT_KEYQ 00000a0c
-CSEG PFA_KEYQ 00000a0d
-CSEG VE_DP 00000a10
-ESEG CFG_DP 00000074
-CSEG VE_EHERE 00000a17
-CSEG XT_EHERE 00000a1c
-CSEG PFA_EHERE 00000a1d
-ESEG EE_EHERE 00000078
-CSEG VE_HERE 00000a20
-CSEG PFA_HERE 00000a25
-ESEG EE_HERE 00000076
-CSEG VE_ALLOT 00000a28
-CSEG PFA_ALLOT 00000a2e
-CSEG VE_BIN 00000a33
-CSEG XT_BIN 00000a37
-CSEG PFA_BIN 00000a38
-CSEG VE_DECIMAL 00000a3c
-CSEG PFA_DECIMAL 00000a43
-CSEG VE_HEX 00000a48
-CSEG XT_HEX 00000a4c
-CSEG PFA_HEX 00000a4d
-CSEG VE_BL 00000a52
-CSEG XT_BL 00000a55
-CSEG PFA_BL 00000a56
-CSEG VE_TURNKEY 00000a57
-CSEG XT_TURNKEY 00000a5d
-CSEG PFA_TURNKEY 00000a5e
-ESEG CFG_TURNKEY 00000080
-CSEG VE_SLASHMOD 00000a61
-CSEG XT_SLASHMOD 00000a65
-CSEG PFA_SLASHMOD 00000a66
-CSEG PFA_SLASHMOD_1 00000a71
-CSEG PFA_SLASHMOD_2 00000a77
-CSEG PFA_SLASHMOD_3 00000a7a
-CSEG PFA_SLASHMOD_5 00000a85
-CSEG PFA_SLASHMOD_4 00000a84
-CSEG PFA_SLASHMODmod_done 00000a90
-CSEG PFA_SLASHMOD_6 00000a8e
-CSEG VE_USLASHMOD 00000a95
-CSEG XT_USLASHMOD 00000a9a
-CSEG PFA_USLASHMOD 00000a9b
-CSEG VE_NEGATE 00000aa0
-CSEG PFA_NEGATE 00000aa6
-CSEG VE_SLASH 00000aa9
-CSEG XT_SLASH 00000aac
-CSEG PFA_SLASH 00000aad
-CSEG VE_MOD 00000ab0
-CSEG XT_MOD 00000ab4
-CSEG PFA_MOD 00000ab5
-CSEG VE_ABS 00000ab8
-CSEG XT_ABS 00000abc
-CSEG PFA_ABS 00000abd
-CSEG VE_MIN 00000ac0
-CSEG XT_MIN 00000ac4
-CSEG PFA_MIN 00000ac5
-CSEG PFA_MIN1 00000aca
-CSEG VE_MAX 00000acc
-CSEG XT_MAX 00000ad0
-CSEG PFA_MAX 00000ad1
-CSEG PFA_MAX1 00000ad6
-CSEG VE_WITHIN 00000ad8
-CSEG XT_WITHIN 00000add
-CSEG PFA_WITHIN 00000ade
-CSEG VE_TOUPPER 00000ae5
-CSEG XT_TOUPPER 00000aeb
-CSEG PFA_TOUPPER 00000aec
-CSEG PFA_TOUPPER0 00000af7
-CSEG VE_TOLOWER 00000af8
-CSEG XT_TOLOWER 00000afe
-CSEG PFA_TOLOWER 00000aff
-CSEG PFA_TOLOWER0 00000b0a
-CSEG VE_HLD 00000b0b
-CSEG XT_HLD 00000b0f
-CSEG PFA_HLD 00000b10
-DSEG ram_hld 00000255
-CSEG VE_HOLD 00000b11
-CSEG XT_HOLD 00000b15
-CSEG PFA_HOLD 00000b16
-CSEG VE_L_SHARP 00000b21
-CSEG XT_L_SHARP 00000b24
-CSEG PFA_L_SHARP 00000b25
-CSEG VE_SHARP 00000b29
-CSEG XT_SHARP 00000b2c
-CSEG PFA_SHARP 00000b2d
-CSEG XT_UDSLASHMOD 00000ba9
-CSEG PFA_SHARP1 00000b3a
-CSEG VE_SHARP_S 00000b3f
-CSEG XT_SHARP_S 00000b42
-CSEG PFA_SHARP_S 00000b43
-CSEG NUMS1 00000b43
-CSEG VE_SHARP_G 00000b4a
-CSEG XT_SHARP_G 00000b4d
-CSEG PFA_SHARP_G 00000b4e
-CSEG VE_SIGN 00000b55
-CSEG XT_SIGN 00000b59
-CSEG PFA_SIGN 00000b5a
-CSEG PFA_SIGN1 00000b60
-CSEG VE_DDOTR 00000b61
-CSEG XT_DDOTR 00000b65
-CSEG PFA_DDOTR 00000b66
-CSEG XT_DABS 0000113a
-CSEG XT_SPACES 00000c51
-CSEG XT_TYPE 00000c61
-CSEG VE_DOTR 00000b74
-CSEG XT_DOTR 00000b77
-CSEG PFA_DOTR 00000b78
-CSEG VE_DDOT 00000b7d
-CSEG XT_DDOT 00000b80
-CSEG PFA_DDOT 00000b81
-CSEG VE_DOT 00000b85
-CSEG PFA_DOT 00000b89
-CSEG VE_UDDOT 00000b8c
-CSEG PFA_UDDOT 00000b91
-CSEG VE_UDDOTR 00000b95
-CSEG PFA_UDDOTR 00000b9a
-CSEG VE_UDSLASHMOD 00000ba4
-CSEG PFA_UDSLASHMOD 00000baa
-CSEG VE_DIGITQ 00000bb4
-CSEG XT_DIGITQ 00000bb9
-CSEG PFA_DIGITQ 00000bba
-CSEG PFA_DOSLITERAL 00000bd4
-CSEG VE_SCOMMA 00000bde
-CSEG PFA_SCOMMA 00000be2
-CSEG PFA_DOSCOMMA 00000be6
-CSEG PFA_SCOMMA2 00000bf8
-CSEG PFA_SCOMMA1 00000bf2
-CSEG PFA_SCOMMA3 00000bff
-CSEG VE_ITYPE 00000c01
-CSEG PFA_ITYPE 00000c07
-CSEG PFA_ITYPE2 00000c1a
-CSEG PFA_ITYPE1 00000c12
-CSEG XT_LOWEMIT 00000c27
-CSEG XT_HIEMIT 00000c23
-CSEG PFA_ITYPE3 00000c21
-CSEG PFA_HIEMIT 00000c24
-CSEG PFA_LOWEMIT 00000c28
-CSEG VE_ICOUNT 00000c2d
-CSEG PFA_ICOUNT 00000c33
-CSEG VE_CR 00000c38
-CSEG XT_CR 00000c3b
-CSEG PFA_CR 00000c3c
-CSEG VE_SPACE 00000c43
-CSEG PFA_SPACE 00000c49
-CSEG VE_SPACES 00000c4c
-CSEG PFA_SPACES 00000c52
-CSEG SPCS1 00000c54
-CSEG SPCS2 00000c5b
-CSEG VE_TYPE 00000c5d
-CSEG PFA_TYPE 00000c62
-CSEG PFA_TYPE2 00000c6c
-CSEG PFA_TYPE1 00000c67
-CSEG VE_TICK 00000c6d
-CSEG PFA_TICK 00000c71
-CSEG XT_FORTHRECOGNIZER 00000f32
-CSEG XT_RECOGNIZE 00000f3d
-CSEG XT_DT_NULL 00000fb0
-CSEG XT_NOOP 00000fe5
-CSEG PFA_TICK1 00000c82
-CSEG VE_HANDLER 00000c84
-CSEG XT_HANDLER 00000c8a
-CSEG PFA_HANDLER 00000c8b
-CSEG VE_CATCH 00000c8c
-CSEG XT_CATCH 00000c91
-CSEG PFA_CATCH 00000c92
-CSEG VE_THROW 00000ca2
-CSEG PFA_THROW 00000ca8
-CSEG PFA_THROW1 00000cae
-CSEG VE_CSKIP 00000cbb
-CSEG XT_CSKIP 00000cc0
-CSEG PFA_CSKIP 00000cc1
-CSEG PFA_CSKIP1 00000cc2
-CSEG PFA_CSKIP2 00000ccf
-CSEG XT_SLASHSTRING 00000e0b
-CSEG VE_CSCAN 00000cd2
-CSEG XT_CSCAN 00000cd7
-CSEG PFA_CSCAN 00000cd8
-CSEG PFA_CSCAN1 00000cda
-CSEG PFA_CSCAN2 00000cec
-CSEG VE_ACCEPT 00000cf2
-CSEG XT_ACCEPT 00000cf7
-CSEG PFA_ACCEPT 00000cf8
-CSEG ACC1 00000cfc
-CSEG XT_CRLFQ 00000d38
-CSEG ACC5 00000d2a
-CSEG ACC3 00000d1a
-CSEG ACC6 00000d18
-CSEG XT_BS 00000d30
-CSEG ACC4 00000d28
-CSEG PFA_ACCEPT6 00000d21
-CSEG VE_REFILL 00000d43
-CSEG XT_REFILL 00000d48
-CSEG PFA_REFILL 00000d49
-CSEG VE_CHAR 00000d4c
-CSEG PFA_CHAR 00000d51
-CSEG VE_NUMBER 00000d55
-CSEG XT_NUMBER 00000d5a
-CSEG PFA_NUMBER 00000d5b
-CSEG XT_QSIGN 00000d9e
-CSEG XT_SET_BASE 00000db1
-CSEG PFA_NUMBER0 00000d71
-CSEG XT_TO_NUMBER 00000dcf
-CSEG PFA_NUMBER1 00000d93
-CSEG PFA_NUMBER2 00000d8a
-CSEG PFA_NUMBER6 00000d8b
-CSEG PFA_NUMBER3 00000d87
-CSEG XT_DNEGATE 00001147
-CSEG PFA_NUMBER5 00000d99
-CSEG PFA_NUMBER4 00000d98
-CSEG PFA_QSIGN 00000d9f
-CSEG PFA_NUMBERSIGN_DONE 00000daa
-CSEG XT_BASES 00000dac
-CSEG PFA_SET_BASE 00000db2
-CSEG SET_BASE1 00000dc7
-CSEG SET_BASE2 00000dc8
-CSEG VE_TO_NUMBER 00000dc9
-CSEG TONUM1 00000dd0
-CSEG TONUM3 00000de7
-CSEG TONUM2 00000ddb
-CSEG XT_2SWAP 0000116b
-CSEG VE_PARSE 00000de8
-CSEG PFA_PARSE 00000dee
-CSEG VE_SOURCE 00000dfc
-CSEG PFA_SOURCE 00000e02
-CSEG VE_SLASHSTRING 00000e05
-CSEG PFA_SLASHSTRING 00000e0c
-CSEG VE_PARSENAME 00000e13
-CSEG PFA_PARSENAME 00000e1b
-CSEG XT_SKIPSCANCHAR 00000e1e
-CSEG PFA_SKIPSCANCHAR 00000e1f
-CSEG VE_FINDXT 00000e30
-CSEG XT_FINDXT 00000e36
-CSEG PFA_FINDXT 00000e37
-CSEG XT_FINDXTA 00000e42
-CSEG PFA_FINDXT1 00000e41
-CSEG PFA_FINDXTA 00000e43
-CSEG XT_SEARCH_WORDLIST 0000108b
-CSEG PFA_FINDXTA1 00000e4f
-CSEG XT_DEFAULT_PROMPTOK 00000e50
-CSEG PFA_DEFAULT_PROMPTOK 00000e51
-CSEG VE_PROMPTOK 00000e57
-CSEG XT_PROMPTOK 00000e5b
-CSEG PFA_PROMPTOK 00000e5c
-CSEG XT_DEFAULT_PROMPTREADY 00000e5f
-CSEG PFA_DEFAULT_PROMPTREADY 00000e60
-CSEG VE_PROMPTREADY 00000e66
-CSEG XT_PROMPTREADY 00000e6b
-CSEG PFA_PROMPTREADY 00000e6c
-CSEG XT_DEFAULT_PROMPTERROR 00000e6f
-CSEG PFA_DEFAULT_PROMPTERROR 00000e70
-CSEG VE_PROMPTERROR 00000e81
-CSEG XT_PROMPTERROR 00000e86
-CSEG PFA_PROMPTERROR 00000e87
-CSEG VE_QUIT 00000e8a
-CSEG XT_QUIT 00000e8e
-CSEG PFA_QUIT 00000e8f
-CSEG XT_SP0 00000eef
-CSEG XT_RP0 00000efc
-CSEG PFA_QUIT2 00000e97
-CSEG PFA_QUIT4 00000e9d
-CSEG PFA_QUIT3 00000eaf
-CSEG XT_INTERPRET 00000f15
-CSEG PFA_QUIT5 00000ead
-CSEG VE_PAUSE 00000eb2
-CSEG PFA_PAUSE 00000eb8
-DSEG ram_pause 00000257
-CSEG XT_RDEFERFETCH 0000102e
-CSEG XT_RDEFERSTORE 00001038
-CSEG VE_COLD 00000ebb
-CSEG clearloop 00000ec7
-DSEG ram_user1 00000259
-CSEG PFA_WARM 00000ee2
-CSEG VE_WARM 00000edd
-CSEG XT_WARM 00000ee1
-CSEG XT_INIT_RAM 000011b6
-CSEG XT_DEFERSTORE 00001059
-CSEG VE_SP0 00000eeb
-CSEG PFA_SP0 00000ef0
-CSEG VE_SP 00000ef3
-CSEG XT_SP 00000ef6
-CSEG PFA_SP 00000ef7
-CSEG VE_RP0 00000ef8
-CSEG PFA_RP0 00000efd
-CSEG XT_DORP0 00000f00
-CSEG PFA_DORP0 00000f01
-CSEG VE_DEPTH 00000f02
-CSEG XT_DEPTH 00000f07
-CSEG PFA_DEPTH 00000f08
-CSEG VE_INTERPRET 00000f0e
-CSEG PFA_INTERPRET 00000f16
-CSEG PFA_INTERPRET2 00000f26
-CSEG PFA_INTERPRET1 00000f21
-CSEG VE_FORTHRECOGNIZER 00000f28
-CSEG PFA_FORTHRECOGNIZER 00000f33
-ESEG CFG_FORTHRECOGNIZER 0000007c
-CSEG VE_RECOGNIZE 00000f36
-CSEG PFA_RECOGNIZE 00000f3e
-CSEG XT_RECOGNIZE_A 00000f48
-CSEG PFA_RECOGNIZE1 00000f47
-CSEG PFA_RECOGNIZE_A 00000f49
-CSEG PFA_RECOGNIZE_A1 00000f59
-CSEG VE_DT_NUM 00000f5d
-CSEG XT_DT_NUM 00000f62
-CSEG PFA_DT_NUM 00000f63
-CSEG VE_DT_DNUM 00000f66
-CSEG XT_DT_DNUM 00000f6c
-CSEG PFA_DT_DNUM 00000f6d
-CSEG XT_2LITERAL 00001265
-CSEG VE_REC_NUM 00000f70
-CSEG XT_REC_NUM 00000f76
-CSEG PFA_REC_NUM 00000f77
-CSEG PFA_REC_NONUMBER 00000f82
-CSEG PFA_REC_INTNUM2 00000f80
-CSEG VE_REC_FIND 00000f84
-CSEG XT_REC_FIND 00000f8a
-CSEG PFA_REC_FIND 00000f8b
-CSEG PFA_REC_WORD_FOUND 00000f93
-CSEG XT_DT_XT 00000f9a
-CSEG VE_DT_XT 00000f95
-CSEG PFA_DT_XT 00000f9b
-CSEG XT_R_WORD_INTERPRET 00000f9e
-CSEG XT_R_WORD_COMPILE 00000fa2
-CSEG PFA_R_WORD_INTERPRET 00000f9f
-CSEG PFA_R_WORD_COMPILE 00000fa3
-CSEG PFA_R_WORD_COMPILE1 00000fa8
-CSEG VE_DT_NULL 00000faa
-CSEG PFA_DT_NULL 00000fb1
-CSEG XT_FAIL 00000fb4
-CSEG PFA_FAIL 00000fb5
-CSEG VE_QSTACK 00000fb8
-CSEG PFA_QSTACK 00000fbe
-CSEG PFA_QSTACK1 00000fc5
-CSEG VE_DOT_VER 00000fc6
-CSEG PFA_DOT_VER 00000fcb
-CSEG VE_NOOP 00000fe1
-CSEG PFA_NOOP 00000fe6
-CSEG VE_UNUSED 00000fe7
-CSEG XT_UNUSED 00000fec
-CSEG PFA_UNUSED 00000fed
-CSEG VE_TO 00000ff1
-CSEG XT_TO 00000ff4
-CSEG PFA_TO 00000ff5
-CSEG XT_TO_BODY 0000125e
-CSEG PFA_TO1 00001005
-CSEG PFA_DOTO 00001000
-CSEG VE_ICELLPLUS 0000100b
-CSEG PFA_ICELLPLUS 00001012
-CSEG VE_EDEFERFETCH 00001014
-CSEG PFA_EDEFERFETCH 0000101b
-CSEG VE_EDEFERSTORE 0000101e
-CSEG PFA_EDEFERSTORE 00001025
-CSEG VE_RDEFERFETCH 00001028
-CSEG PFA_RDEFERFETCH 0000102f
-CSEG VE_RDEFERSTORE 00001032
-CSEG PFA_RDEFERSTORE 00001039
-CSEG VE_UDEFERFETCH 0000103c
-CSEG PFA_UDEFERFETCH 00001043
-CSEG VE_UDEFERSTORE 00001048
-CSEG PFA_UDEFERSTORE 0000104f
-CSEG VE_DEFERSTORE 00001054
-CSEG PFA_DEFERSTORE 0000105a
-CSEG VE_DEFERFETCH 00001061
-CSEG XT_DEFERFETCH 00001066
-CSEG PFA_DEFERFETCH 00001067
-CSEG VE_DODEFER 0000106d
-CSEG XT_DODEFER 00001073
-CSEG PFA_DODEFER 00001074
-CSEG VE_SEARCH_WORDLIST 00001081
-CSEG PFA_SEARCH_WORDLIST 0000108c
-CSEG XT_ISWORD 000010a0
-CSEG PFA_SEARCH_WORDLIST1 0000109a
-CSEG PFA_ISWORD 000010a1
-CSEG XT_ICOMPARE 000010ee
-CSEG PFA_ISWORD3 000010ae
-CSEG VE_TRAVERSEWORDLIST 000010b2
-CSEG PFA_TRAVERSEWORDLIST 000010be
-CSEG PFA_TRAVERSEWORDLIST1 000010bf
-CSEG PFA_TRAVERSEWORDLIST2 000010ce
-CSEG VE_NAME2STRING 000010d0
-CSEG PFA_NAME2STRING 000010d9
-CSEG VE_NFA2CFA 000010de
-CSEG PFA_NFA2CFA 000010e5
-CSEG VE_ICOMPARE 000010e8
-CSEG PFA_ICOMPARE 000010ef
-CSEG PFA_ICOMPARE_SAMELEN 000010f9
-CSEG PFA_ICOMPARE_DONE 0000111c
-CSEG PFA_ICOMPARE_LOOP 000010ff
-CSEG PFA_ICOMPARE_LASTCELL 0000110d
-CSEG PFA_ICOMPARE_NEXTLOOP 00001114
-CSEG VE_STAR 0000111f
-CSEG XT_STAR 00001122
-CSEG PFA_STAR 00001123
-CSEG VE_J 00001126
-CSEG XT_J 00001129
-CSEG PFA_J 0000112a
-CSEG VE_DABS 00001136
-CSEG PFA_DABS 0000113b
-CSEG PFA_DABS1 00001140
-CSEG VE_DNEGATE 00001141
-CSEG PFA_DNEGATE 00001148
-CSEG VE_CMOVE 0000114d
-CSEG XT_CMOVE 00001152
-CSEG PFA_CMOVE 00001153
-CSEG PFA_CMOVE1 00001160
-CSEG PFA_CMOVE2 0000115c
-CSEG VE_2SWAP 00001166
-CSEG PFA_2SWAP 0000116c
-CSEG VE_REFILLTIB 00001171
-CSEG XT_REFILLTIB 00001178
-CSEG PFA_REFILLTIB 00001179
-CSEG XT_TIB 00001194
-CSEG XT_NUMBERTIB 0000119a
-CSEG VE_SOURCETIB 00001184
-CSEG XT_SOURCETIB 0000118b
-CSEG PFA_SOURCETIB 0000118c
-CSEG VE_TIB 00001190
-CSEG PFA_TIB 00001195
-DSEG ram_tib 00000285
-CSEG VE_NUMBERTIB 00001196
-CSEG PFA_NUMBERTIB 0000119b
-DSEG ram_sharptib 000002df
-CSEG VE_EE2RAM 0000119c
-CSEG XT_EE2RAM 000011a1
-CSEG PFA_EE2RAM 000011a2
-CSEG PFA_EE2RAM_1 000011a4
-CSEG PFA_EE2RAM_2 000011ae
-CSEG VE_INIT_RAM 000011b0
-CSEG PFA_INI_RAM 000011b7
-ESEG EE_INITUSER 000000a8
-CSEG VE_SET_CURRENT 000011bf
-CSEG XT_SET_CURRENT 000011c7
-CSEG PFA_SET_CURRENT 000011c8
-CSEG VE_WORDLIST 000011cc
-CSEG XT_WORDLIST 000011d2
-CSEG PFA_WORDLIST 000011d3
-CSEG VE_FORTHWORDLIST 000011dc
-CSEG XT_FORTHWORDLIST 000011e5
-CSEG PFA_FORTHWORDLIST 000011e6
-ESEG CFG_FORTHWORDLIST 00000086
-CSEG VE_SET_ORDER 000011e7
-CSEG XT_SET_ORDER 000011ee
-CSEG PFA_SET_ORDER 000011ef
-CSEG VE_SET_RECOGNIZERS 000011f3
-CSEG XT_SET_RECOGNIZERS 000011fd
-CSEG PFA_SET_RECOGNIZERS 000011fe
-ESEG CFG_RECOGNIZERLISTLEN 0000009a
-CSEG VE_GET_RECOGNIZERS 00001202
-CSEG XT_GET_RECOGNIZERS 0000120c
-CSEG PFA_GET_RECOGNIZERS 0000120d
-CSEG VE_CODE 00001211
-CSEG XT_CODE 00001215
-CSEG PFA_CODE 00001216
-CSEG VE_ENDCODE 0000121c
-CSEG XT_ENDCODE 00001222
-CSEG PFA_ENDCODE 00001223
-CSEG VE_MARKER 00001228
-CSEG XT_MARKER 0000122e
-CSEG PFA_MARKER 0000122f
-ESEG EE_MARKER 000000a6
-CSEG VE_POSTPONE 00001232
-CSEG XT_POSTPONE 00001238
-CSEG PFA_POSTPONE 00001239
-CSEG VE_BOUNDS 00001247
-CSEG PFA_BOUNDS 0000124d
-CSEG VE_S2D 00001251
-CSEG PFA_S2D 00001256
-CSEG VE_TO_BODY 00001259
-CSEG VE_2LITERAL 0000125f
-CSEG PFA_2LITERAL 00001266
-CSEG VE_EQUAL 0000126a
-CSEG PFA_EQUAL 0000126e
-CSEG VE_ONE 00001271
-CSEG PFA_ONE 00001275
-CSEG VE_TWO 00001276
-CSEG PFA_TWO 0000127a
-CSEG VE_MINUSONE 0000127b
-CSEG XT_MINUSONE 0000127e
-CSEG PFA_MINUSONE 0000127f
-SET DPSTART 00001280
-SET flashlast 00001280
-DSEG HERESTART 000002e1
-ESEG EHERESTART 000000cc
-ESEG CFG_ORDERLIST 0000008a
-ESEG CFG_RECOGNIZERLIST 0000009c
-EQU UBRR_VAL 00000017
-EQU BAUD_REAL 00009600
-EQU BAUD_ERROR 00000000
diff --git a/amforth-6.5/appl/atmega2561/build.xml b/amforth-6.5/appl/atmega2561/build.xml
deleted file mode 100644
index b7804aa..0000000
--- a/amforth-6.5/appl/atmega2561/build.xml
+++ /dev/null
@@ -1,21 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="Atmega256" basedir="." default="Help">
-
- <import file="../avr-build.xml"/>
- <target name="atmega256.hex" description="Hexfiles for AVR atmega256">
- <avrasm2 projectname="atmega256" mcu="atmega2561"/>
- </target>
-
- <target name="atmega256" depends="atmega256.hex" description="AVR atmega256: Atmega2561 @ 14.7456 MHz">
- <echo>Uploading Hexfiles for AVR atmega256</echo>
- <avrdude
- type="dragon"
- mcu="m2561"
- flashfile="atmega256.hex"
- eepromfile="atmega256.eep.hex"
- />
- </target>
- <target name="compile" depends="atmega256.hex">
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/atmega2561/dict_appl.inc b/amforth-6.5/appl/atmega2561/dict_appl.inc
deleted file mode 100644
index a52b464..0000000
--- a/amforth-6.5/appl/atmega2561/dict_appl.inc
+++ /dev/null
@@ -1,5 +0,0 @@
-; this dictionary contains optional words
-; they may be moved to the core dictionary if needed
-
-.include "words/applturnkey.asm"
-
diff --git a/amforth-6.5/appl/atmega2561/dict_appl_core.inc b/amforth-6.5/appl/atmega2561/dict_appl_core.inc
deleted file mode 100644
index 93c0d8a..0000000
--- a/amforth-6.5/appl/atmega2561/dict_appl_core.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-; This file is intentionally left empty
-; do not delete it!
diff --git a/amforth-6.5/appl/atmega2561/words/applturnkey.asm b/amforth-6.5/appl/atmega2561/words/applturnkey.asm
deleted file mode 100644
index f2726ff..0000000
--- a/amforth-6.5/appl/atmega2561/words/applturnkey.asm
+++ /dev/null
@@ -1,32 +0,0 @@
-; ( -- ) System
-; R( -- )
-; application specific turnkey action
-VE_APPLTURNKEY:
- .dw $ff0b
- .db "applturnkey",0
- .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
-XT_APPLTURNKEY:
- .dw DO_COLON
-PFA_APPLTURNKEY:
- .dw XT_USART
-
-.if WANT_INTERRUPTS == 1
- .dw XT_INTON
-.endif
-
- .dw XT_DOT_VER
- .dw XT_SPACE
- .dw XT_F_CPU
- .dw XT_DOLITERAL
- .dw 1000
- .dw XT_UMSLASHMOD
- .dw XT_NIP
- .dw XT_DECIMAL
- .dw XT_DOT
- .dw XT_DOSLITERAL
- .dw 4
- .db "kHz "
- .dw XT_ITYPE
-
- .dw XT_EXIT
diff --git a/amforth-6.5/appl/avr-build.xml b/amforth-6.5/appl/avr-build.xml
deleted file mode 100644
index daacf9d..0000000
--- a/amforth-6.5/appl/avr-build.xml
+++ /dev/null
@@ -1,113 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="Amforth for AVR8 Tools" basedir="." default="Help">
- <import file="common-build.xml"/>
- <macrodef name="avrasm2">
- <attribute name="binary" default="wine" />
- <attribute name="avrasm" default="../../avr8/Atmel/avrasm2.exe"/>
- <attribute name="includes" default="../../avr8/Atmel/Appnotes2" />
- <attribute name="projectname" default="undefined"/>
- <attribute name="mcu" default="undefined"/>
- <attribute name="amforth.core" default="../.."/>
- <sequential>
- <echo>Producing Hexfiles for @{mcu}</echo>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="@{avrasm}"/>
- <arg line="-I @{includes}"/>
- <arg line="-I @{amforth.core}/avr8/devices/@{mcu}"/>
- <arg line="-I @{amforth.core}/avr8"/>
- <arg line="-I @{amforth.core}/common"/>
- <arg line="-I @{amforth.core}"/>
- <arg line="-fI -v0"/>
- <arg line="-e @{projectname}.eep.hex"/>
- <arg line="-l @{projectname}.lst"/>
- <arg line="-m @{projectname}.map"/>
- <arg line="-o @{projectname}.hex"/>
- <arg line="@{projectname}.asm"/>
- </exec>
- </sequential>
- </macrodef>
-
- <macrodef name="avrdude">
- <attribute name="binary" default="avrdude" />
- <attribute name="type" default="avr910"/>
- <attribute name="port" default="${avr.programmer.@{type}port}" />
- <attribute name="programmer" default="${avr.programmer.@{type}}" />
- <attribute name="mcu" default="m8"/>
-
- <attribute name="flashfile" default=""/>
- <attribute name="eepromfile" default=""/>
- <sequential>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="-c @{programmer}"/>
- <arg line="-p @{mcu}"/>
- <arg line="-P @{port}"/>
- <arg line="-e"/>
- <arg line="-U flash:w:@{flashfile}"/>
- <arg line="-U eeprom:w:@{eepromfile}"/>
- </exec>
- </sequential>
- </macrodef>
-
- <macrodef name="avrdude-back">
- <attribute name="binary" default="avrdude" />
- <attribute name="type" default="avr910"/>
- <attribute name="port" default="${avr.programmer.@{type}port}" />
- <attribute name="programmer" default="${avr.programmer.@{type}}" />
- <attribute name="mcu" default="m8"/>
-
- <attribute name="flashfile" default=""/>
- <attribute name="eepromfile" default=""/>
- <sequential>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="-c @{programmer}"/>
- <arg line="-p @{mcu}"/>
- <arg line="-P @{port}"/>
- <arg line="-U flash:r:@{flashfile}:i"/>
- <arg line="-U eeprom:r:@{eepromfile}:i"/>
- </exec>
- </sequential>
- </macrodef>
-
- <macrodef name="avrdude-2fuses">
- <attribute name="binary" default="avrdude" />
- <attribute name="type" default="avr910"/>
- <attribute name="port" default="${avr.programmer.@{type}port}" />
- <attribute name="programmer" default="${avr.programmer.@{type}}" />
-
- <attribute name="mcu" default="m8"/>
- <attribute name="hfuse" default="0xnn"/>
- <attribute name="lfuse" default="0xnn"/>
- <sequential>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="-c @{programmer}"/>
- <arg line="-p @{mcu}"/>
- <arg line="-P @{port}"/>
- <!-- $(AVRDUDE) $(USB) -p $(MCU) -U hfuse:w:$(HFUSE):m -U lfuse:w:$(LFUSE):m -->
- <arg line="-U hfuse:w:@{hfuse}:m"/>
- <arg line="-U lfuse:w:@{lfuse}:m"/>
- </exec>
- </sequential>
- </macrodef>
-
- <macrodef name="avrdude-3fuses">
- <attribute name="binary" default="avrdude" />
- <attribute name="type" default="avr910"/>
- <attribute name="port" default="${avr.programmer.@{type}port}" />
- <attribute name="programmer" default="${avr.programmer.@{type}}" />
-
- <attribute name="mcu" default="m88"/>
- <attribute name="efuse" default="0xnn"/>
- <attribute name="hfuse" default="0xnn"/>
- <attribute name="lfuse" default="0xnn"/>
- <sequential>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="-c @{programmer}"/>
- <arg line="-p @{mcu}"/>
- <arg line="-P @{port}"/>
- <arg line="-U hfuse:w:@{hfuse}:m"/>
- <arg line="-U lfuse:w:@{lfuse}:m"/>
- <arg line="-U efuse:w:@{efuse}:m"/>
- </exec>
- </sequential>
- </macrodef>
-</project>
diff --git a/amforth-6.5/appl/build.xml b/amforth-6.5/appl/build.xml
deleted file mode 100644
index 6737ee5..0000000
--- a/amforth-6.5/appl/build.xml
+++ /dev/null
@@ -1,20 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="amForth" basedir="." default="release">
-<target name="release">
- <ant antfile="build.xml" dir="arduino" target="compile" inheritAll="false"/>
-</target>
-<target name="clean">
- <ant antfile="build.xml" dir="arduino" target="clean" inheritAll="false"/>
- <ant antfile="build.xml" dir="template" target="clean" inheritAll="false"/>
- <ant antfile="build.xml" dir="eval-pollin" target="clean" inheritAll="false"/>
- <ant antfile="build.xml" dir="atmega2561" target="clean" inheritAll="false"/>
- <ant antfile="build.xml" dir="launchpad430" target="clean" inheritAll="false"/>
-</target>
-<target name="compile">
- <ant antfile="build.xml" dir="arduino" target="compile" inheritAll="false"/>
- <ant antfile="build.xml" dir="template" target="compile" inheritAll="false"/>
- <ant antfile="build.xml" dir="eval-pollin" target="compile" inheritAll="false"/>
- <ant antfile="build.xml" dir="atmega2561" target="compile" inheritAll="false"/>
- <ant antfile="build.xml" dir="launchpad430" target="compile" inheritAll="false"/>
-</target>
-</project>
diff --git a/amforth-6.5/appl/common-build.xml b/amforth-6.5/appl/common-build.xml
deleted file mode 100644
index b039a5d..0000000
--- a/amforth-6.5/appl/common-build.xml
+++ /dev/null
@@ -1,47 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="Macros and Commands for ANT" basedir="." default="Help">
- <target name="Help" description="use ant -p for more">
- <echo message="use ant -p for a list of available targets"/>
- <echo message="and look at programmer.properties for available programmers"/>
- </target>
-
- <!-- generic target to clean up directory -->
- <target name="clean" description="Delete all generated files" >
- <delete verbose="true">
- <fileset dir="." includes="*.hex"/>
- <fileset dir="." includes="*.lst"/>
- <fileset dir="." includes="*.obj"/>
- <fileset dir="." includes="*.cof"/>
- <fileset dir="." includes="*.map"/>
- </delete>
- </target>
-
- <target name="build-info">
- <tstamp>
- <format property="touch.time" pattern="MMM dd, yyyy HH:mm:ss" locale="C"/>
- </tstamp>
- <length property="touch.length" string="${touch.time}"/>
- <copy tofile="words/build-info.asm" file="../../common/words/build-info.tmpl" overwrite="true">
- <filterset>
- <filter token="TSTAMPLEN" value="${touch.length}"/>
- <filter token="TSTAMP" value="${touch.time}"/>
- </filterset>
- </copy>
-
- </target>
-
- <macrodef name="git-branch">
- <attribute name="output" />
- <sequential>
- <exec executable="git" outputproperty="branch" >
- <arg value="rev-parse"/>
- <arg value="--abbrev-ref"/>
- <arg value="HEAD"/>
- <env key="LANG" value="C"/>
- </exec>
- <property name="@{output}" value="${branch}"/>
- </sequential>
- </macrodef>
-
- <loadproperties srcfile="../programmer.properties"/>
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/blocks/hd44780.frt b/amforth-6.5/appl/eval-pollin/blocks/hd44780.frt
deleted file mode 100644
index 0524f5f..0000000
--- a/amforth-6.5/appl/eval-pollin/blocks/hd44780.frt
+++ /dev/null
@@ -1,115 +0,0 @@
-\
-\ Module: hd44780 routines
-\ use the hd44780 module in 8bit mode
-\ v 0.9
-
-\ needs marker.frt and bitnames.frt from lib
-
-marker _hd44780_
-
-
-hex
-
-\ for the pollin addon board 1.0
-1b 20 + constant hd44780-data \ PORTA
-18 20 + constant hd44780-ctrl \ PORTB
-
-hd44780-ctrl 1 portpin: hd44780-rw
-hd44780-ctrl 0 portpin: hd44780-en
-hd44780-ctrl 2 portpin: hd44780-rs
-
-2 constant hd44780-pulse-delay
-a constant hd44780-short-delay
-
-: hd44780-pulse-en
- hd44780-en high
- hd44780-pulse-delay ms
- hd44780-en low
- hd44780-pulse-delay ms
-;
-
-: hd44780-data-mode
- hd44780-rs high
-;
-
-: hd44780-command-mode
- hd44780-rs low
-;
-
-
-: hd44780-read-mode
- 0 hd44780-data 1- c! \ input
- hd44780-rw high
-;
-
-: hd44780-write-mode
- ff hd44780-data 1- c! \ output
- hd44780-rw low
-;
-
-: hd44780-read-data ( -- c )
- hd44780-read-mode
- hd44780-pulse-en
- hd44780-short-delay ms
- hd44780-data 1- 1- c@
-;
-
-: hd44780-wait
- hd44780-read-mode
- hd44780-rw high
- hd44780-rs low
- hd44780-pulse-en
- begin
- hd44780-data 1- 1- c@
- 80 and
- until
-;
-
-: hd44780-command ( n -- )
- hd44780-wait
- hd44780-write-mode
- hd44780-command-mode
- hd44780-data c!
- hd44780-pulse-en
-;
-
-: hd44780-emit ( c -- )
- hd44780-write-mode
- hd44780-data-mode
- hd44780-data c!
- hd44780-pulse-en
-;
-
-: hd44780-init
- hd44780-rw pin_output
- hd44780-en pin_output
- hd44780-rs pin_output
-;
-\ from tracker: hd44780.frt - added LCD initialization - ID: 2785157
-: hd44780-cmd-no-wait ( n -- )
- hd44780-write-mode
- hd44780-command-mode
- hd44780-data c!
- hd44780-pulse-en
-;
-
-: hd44780-start
- hd44780-init
- 15 ms
- 30 hd44780-cmd-no-wait
- 4 ms
- 30 hd44780-cmd-no-wait
- 1 ms
- 30 hd44780-cmd-no-wait
- 38 hd44780-command
- 6 hd44780-command
- c hd44780-command
- 1 hd44780-command
-;
-
-
-: hd44780-page ( clear page )
- 1 hd44780-command ( clear hd44780 )
- 3 hd44780-command ( cursor home )
-;
-
diff --git a/amforth-6.5/appl/eval-pollin/blocks/hello-world.frt b/amforth-6.5/appl/eval-pollin/blocks/hello-world.frt
deleted file mode 100644
index 94073b8..0000000
--- a/amforth-6.5/appl/eval-pollin/blocks/hello-world.frt
+++ /dev/null
@@ -1,81 +0,0 @@
-\ test routines for the atmel evaluation
-\ boards from www.pollin.de
-\ needs the device register definitions loaded
-
-#require ms.frt
-
-marker _pollin_
-
-decimal
-
-\ wait some milliseconds
-: blinkdelay 250 ms ;
-
-PORTD 5 portpin: led1
-PORTD 6 portpin: led2
-
-PORTD 2 portpin: key1
-PORTD 3 portpin: key2
-PORTD 4 portpin: key3
-
-GICR 7 portpin: en_int1
-GICR 6 portpin: en_int0
-GICR 5 portpin: en_int2
-
-: +demoports
- led1 pin_output
- led2 pin_output
- key1 pin_input
- key2 pin_input
- key3 pin_input
-
- 05 MCUCR c! \ int0/1
- en_int1 high
- en_int0 high
- en_int2 low
-;
-
-\ test runs until a terminal-key is pressed
-
-\ as long as a key on the board is pressed the
-\ corresponding led/buzzer is turned on
-: keys
- begin
- PIND c@
- [ hex ] fc and
- 3 lshift
- PORTD c!
- key? until
- key drop \ we do not want to keep this key stroke
-;
-
-
-: blink ( -- )
- led1 high blinkdelay
- led2 high blinkdelay
- led2 low blinkdelay
- led1 low blinkdelay
-;
-
-: led1blink
- led1 high
- blinkdelay
- led1 low
-;
-
-\ simple lights on/off
-: led
- begin
- blink
- key?
- until
- key drop \ we do not want to keep this key stroke
-;
-
-\ interrupt processing takes a long time, do not
-\ press the key while it runs...
-\ ' led1blink 1 int!
-\ ' noop 2 int!
-
-\ autoconfig the i/o ports
-\ ' portinit 'turnkey e!
diff --git a/amforth-6.5/appl/eval-pollin/blocks/netio.frt b/amforth-6.5/appl/eval-pollin/blocks/netio.frt
deleted file mode 100644
index 6c1f62c..0000000
--- a/amforth-6.5/appl/eval-pollin/blocks/netio.frt
+++ /dev/null
@@ -1,32 +0,0 @@
-
-\ Definitions for the netio-addon board
-
-\ SPI communication pins
- PORTB 4 portpin: /ss
- PORTB 5 portpin: _mosi
- PORTB 6 portpin: _miso
- PORTB 7 portpin: _clk
-
-\ setup the SPI pins
- : +spi ( -- )
- /ss high \ activate pullup!
- _mosi high _mosi pin_output
- _clk low _clk pin_output
- ;
-
- : -spi 0 SPCR c! ;
-
- \ transfer 1 cell
- : ><spi ( x -- x' )
- dup >< c!@spi
- swap c!@spi
- swap >< +
- ;
-
-: +mmc
- /ss low
-;
-: -mmc
- /ss high
-;
-
diff --git a/amforth-6.5/appl/eval-pollin/build.xml b/amforth-6.5/appl/eval-pollin/build.xml
deleted file mode 100644
index 081eea6..0000000
--- a/amforth-6.5/appl/eval-pollin/build.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="pollins" basedir="." default="Help">
- <import file="../avr-build.xml"/>
- <import file="p328-16.xml"/>
- <import file="p16-8.xml"/>
- <import file="p32-16.xml"/>
- <import file="p32-8.xml"/>
- <import file="p644-16.xml"/>
- <import file="p1284-16.xml"/>
- <import file="p8-12.xml"/>
-
- <target name="compile" depends="p16-8.hex, p32-8.hex, p328-16.hex, p1284-16.hex, p644-16.hex">
-
- </target>
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/dict_appl.inc b/amforth-6.5/appl/eval-pollin/dict_appl.inc
deleted file mode 100644
index a7e4b42..0000000
--- a/amforth-6.5/appl/eval-pollin/dict_appl.inc
+++ /dev/null
@@ -1,8 +0,0 @@
-; this dictionary contains optional words
-; they may be moved to the core dictionary if needed
-.include "words/dot-s.asm"
-.include "words/spirw.asm"
-.include "words/n-spi.asm"
-.include "words/applturnkey.asm"
-.include "dict/compiler2.inc"
-.include "words/2r_fetch.asm"
diff --git a/amforth-6.5/appl/eval-pollin/dict_appl_core.inc b/amforth-6.5/appl/eval-pollin/dict_appl_core.inc
deleted file mode 100644
index 93c0d8a..0000000
--- a/amforth-6.5/appl/eval-pollin/dict_appl_core.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-; This file is intentionally left empty
-; do not delete it!
diff --git a/amforth-6.5/appl/eval-pollin/p1284-16.eep.hex b/amforth-6.5/appl/eval-pollin/p1284-16.eep.hex
deleted file mode 100644
index dfec159..0000000
--- a/amforth-6.5/appl/eval-pollin/p1284-16.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10004600FFFF9A05CB01A00042046E00B040EC040D
-:0A0056004DF55A00A8FD01005A0004
-:06006E0002003FFB2BFB2A
-:1000780090F37A0000000000FF40AF40AF4000005E
-:100088000A00B600C4008B00A60040FD00002DFD4C
-:0800980005FA24FA14FA19001C
-:00000001FF
diff --git a/amforth-6.5/appl/eval-pollin/p1284-16.hex b/amforth-6.5/appl/eval-pollin/p1284-16.hex
deleted file mode 100644
index 1f80cb8..0000000
--- a/amforth-6.5/appl/eval-pollin/p1284-16.hex
+++ /dev/null
@@ -1,646 +0,0 @@
-:020000020000FC
-:0200040039D1F0
-:0200080037D1EE
-:02000C0035D1EC
-:0200100033D1EA
-:0200140031D1E8
-:020018002FD1E6
-:02001C002DD1E4
-:020020002BD1E2
-:0200240029D1E0
-:0200280027D1DE
-:02002C0025D1DC
-:0200300023D1DA
-:0200340021D1D8
-:020038001FD1D6
-:02003C001DD1D4
-:020040001BD1D2
-:0200440019D1D0
-:0200480017D1CE
-:02004C0015D1CC
-:0200500013D1CA
-:0200540011D1C8
-:020058000FD1C6
-:02005C000DD1C4
-:020060000BD1C2
-:0200640009D1C0
-:0200680007D1BE
-:02006C0005D1BC
-:0200700003D1BA
-:0200740001D1B8
-:02007800FFD0B7
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-:10FAF20001F0E1F0AFF1D6F026F003FF733E6400AF
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-:10FB120079007EFD42F20800326C69746572616C94
-:10FB220086FD01F0D6F0F101F10126F001FF3D0062
-:10FB32008CFD01F0A5F12CF126F001FF310097FDBB
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-:00000001FF
diff --git a/amforth-6.5/appl/eval-pollin/p1284-16.lst b/amforth-6.5/appl/eval-pollin/p1284-16.lst
deleted file mode 100644
index 00d54e8..0000000
--- a/amforth-6.5/appl/eval-pollin/p1284-16.lst
+++ /dev/null
@@ -1,10495 +0,0 @@
-
-AVRASM ver. 2.1.52 p1284-16.asm Sun Apr 30 20:10:15 2017
-
-p1284-16.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega1284p\device.asm'
-../../avr8/devices/atmega1284p\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m1284Pdef.inc'
-p1284-16.asm(14): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-p1284-16.asm(19): Including file '../../avr8\drivers/1wire.asm'
-p1284-16.asm(21): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(9): Including file '../../avr8\dict/appl_8k.inc'
-../../avr8\dict/appl_8k.inc(1): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(3): Including file '../../common\words/dot-s.asm'
-dict_appl.inc(4): Including file '../../avr8\words/spirw.asm'
-dict_appl.inc(5): Including file '../../avr8\words/n-spi.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-dict_appl.inc(7): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(8): Including file '../../avr8\words/2r_fetch.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(102): Including file '../../avr8\dict/core_8k.inc'
-../../avr8\dict/core_8k.inc(2): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_8k.inc(3): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_8k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_8k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_8k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_8k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_8k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_8k.inc(10): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_8k.inc(11): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_8k.inc(13): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_8k.inc(14): Including file '../../common\words/words.asm'
-../../avr8\dict/core_8k.inc(15): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_8k.inc(17): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_8k.inc(18): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_8k.inc(19): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_8k.inc(21): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_8k.inc(23): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/core_8k.inc(24): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/core_8k.inc(25): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/core_8k.inc(26): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/core_8k.inc(27): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/core_8k.inc(28): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/core_8k.inc(29): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/core_8k.inc(30): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/core_8k.inc(31): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/core_8k.inc(33): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_8k.inc(34): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_8k.inc(35): Including file '../../common\words/base.asm'
-../../avr8\dict/core_8k.inc(37): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_8k.inc(38): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_8k.inc(40): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_8k.inc(41): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_8k.inc(43): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_8k.inc(45): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_8k.inc(46): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_8k.inc(47): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_8k.inc(48): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_8k.inc(49): Including file '../../common\words/key.asm'
-../../avr8\dict/core_8k.inc(50): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_8k.inc(52): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_8k.inc(53): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_8k.inc(54): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_8k.inc(55): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_8k.inc(57): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_8k.inc(58): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_8k.inc(59): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_8k.inc(60): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_8k.inc(62): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_8k.inc(64): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_8k.inc(65): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_8k.inc(66): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_8k.inc(67): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_8k.inc(68): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_8k.inc(69): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_8k.inc(70): Including file '../../common\words/min.asm'
-../../avr8\dict/core_8k.inc(71): Including file '../../common\words/max.asm'
-../../avr8\dict/core_8k.inc(72): Including file '../../common\words/within.asm'
-../../avr8\dict/core_8k.inc(74): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_8k.inc(75): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_8k.inc(77): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/core_8k.inc(78): Including file '../../common\words/hold.asm'
-../../avr8\dict/core_8k.inc(79): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/core_8k.inc(80): Including file '../../common\words/sharp.asm'
-../../avr8\dict/core_8k.inc(81): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/core_8k.inc(82): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/core_8k.inc(83): Including file '../../common\words/sign.asm'
-../../avr8\dict/core_8k.inc(84): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/core_8k.inc(85): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/core_8k.inc(86): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/core_8k.inc(87): Including file '../../common\words/dot.asm'
-../../avr8\dict/core_8k.inc(88): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/core_8k.inc(89): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/core_8k.inc(90): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/core_8k.inc(91): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/core_8k.inc(93): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/core_8k.inc(94): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/core_8k.inc(95): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/core_8k.inc(96): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/core_8k.inc(97): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_8k.inc(98): Including file '../../common\words/space.asm'
-../../avr8\dict/core_8k.inc(99): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_8k.inc(100): Including file '../../common\words/type.asm'
-../../avr8\dict/core_8k.inc(101): Including file '../../common\words/tick.asm'
-../../avr8\dict/core_8k.inc(103): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_8k.inc(104): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_8k.inc(105): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_8k.inc(107): Including file '../../common\words/cskip.asm'
-../../avr8\dict/core_8k.inc(108): Including file '../../common\words/cscan.asm'
-../../avr8\dict/core_8k.inc(109): Including file '../../common\words/accept.asm'
-../../avr8\dict/core_8k.inc(110): Including file '../../common\words/refill.asm'
-../../avr8\dict/core_8k.inc(111): Including file '../../common\words/char.asm'
-../../avr8\dict/core_8k.inc(112): Including file '../../common\words/number.asm'
-../../avr8\dict/core_8k.inc(113): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/core_8k.inc(114): Including file '../../common\words/set-base.asm'
-../../avr8\dict/core_8k.inc(115): Including file '../../common\words/to-number.asm'
-../../avr8\dict/core_8k.inc(116): Including file '../../common\words/parse.asm'
-../../avr8\dict/core_8k.inc(117): Including file '../../common\words/source.asm'
-../../avr8\dict/core_8k.inc(118): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/core_8k.inc(119): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/core_8k.inc(120): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/core_8k.inc(122): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_8k.inc(123): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_8k.inc(124): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_8k.inc(126): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_8k.inc(127): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_8k.inc(128): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_8k.inc(129): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_8k.inc(131): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/core_8k.inc(132): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/core_8k.inc(133): Including file '../../common\words/depth.asm'
-../../avr8\dict/core_8k.inc(134): Including file '../../common\words/interpret.asm'
-../../avr8\dict/core_8k.inc(135): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/core_8k.inc(136): Including file '../../common\words/recognize.asm'
-../../avr8\dict/core_8k.inc(137): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/core_8k.inc(138): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/core_8k.inc(139): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/core_8k.inc(141): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_8k.inc(142): Including file '../../common\words/ver.asm'
-../../avr8\dict/core_8k.inc(144): Including file '../../common\words/noop.asm'
-../../avr8\dict/core_8k.inc(145): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/core_8k.inc(147): Including file '../../common\words/to.asm'
-../../avr8\dict/core_8k.inc(148): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/core_8k.inc(150): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_8k.inc(151): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_8k.inc(152): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_8k.inc(153): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_8k.inc(154): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_8k.inc(155): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_8k.inc(156): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_8k.inc(157): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_8k.inc(158): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_8k.inc(160): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/core_8k.inc(161): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/core_8k.inc(162): Including file '../../common\words/name2string.asm'
-../../avr8\dict/core_8k.inc(163): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/core_8k.inc(164): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/core_8k.inc(166): Including file '../../common\words/star.asm'
-../../avr8\dict/core_8k.inc(167): Including file '../../avr8\words/j.asm'
-../../avr8\dict/core_8k.inc(169): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/core_8k.inc(170): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/core_8k.inc(171): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/core_8k.inc(172): Including file '../../common\words/2swap.asm'
-../../avr8\dict/core_8k.inc(174): Including file '../../common\words/tib.asm'
-../../avr8\dict/core_8k.inc(176): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/core_8k.inc(177): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/core_8k.inc(178): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_8k.inc(179): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_8k.inc(180): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
- .endmacro
- .macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- .endmacro
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_USART0 = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_TIMER_COUNTER_3 = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_JTAG = 0
- .set WANT_EEPROM = 0
- .set WANT_TWI = 0
- .set WANT_USART1 = 0
- .set WANT_SPI = 0
- .set WANT_WATCHDOG = 0
- .set WANT_CPU = 0
- .equ intvecsize = 2 ; please verify; flash size: 131072 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d139 rcall isr ; External Interrupt Request 0
- .org 4
-000004 d137 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d135 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d133 rcall isr ; Pin Change Interrupt Request 0
- .org 10
-00000a d131 rcall isr ; Pin Change Interrupt Request 1
- .org 12
-00000c d12f rcall isr ; Pin Change Interrupt Request 2
- .org 14
-00000e d12d rcall isr ; Pin Change Interrupt Request 3
- .org 16
-000010 d12b rcall isr ; Watchdog Time-out Interrupt
- .org 18
-000012 d129 rcall isr ; Timer/Counter2 Compare Match A
- .org 20
-000014 d127 rcall isr ; Timer/Counter2 Compare Match B
- .org 22
-000016 d125 rcall isr ; Timer/Counter2 Overflow
- .org 24
-000018 d123 rcall isr ; Timer/Counter1 Capture Event
- .org 26
-00001a d121 rcall isr ; Timer/Counter1 Compare Match A
- .org 28
-00001c d11f rcall isr ; Timer/Counter1 Compare Match B
- .org 30
-00001e d11d rcall isr ; Timer/Counter1 Overflow
- .org 32
-000020 d11b rcall isr ; Timer/Counter0 Compare Match A
- .org 34
-000022 d119 rcall isr ; Timer/Counter0 Compare Match B
- .org 36
-000024 d117 rcall isr ; Timer/Counter0 Overflow
- .org 38
-000026 d115 rcall isr ; SPI Serial Transfer Complete
- .org 40
-000028 d113 rcall isr ; USART0, Rx Complete
- .org 42
-00002a d111 rcall isr ; USART0 Data register Empty
- .org 44
-00002c d10f rcall isr ; USART0, Tx Complete
- .org 46
-00002e d10d rcall isr ; Analog Comparator
- .org 48
-000030 d10b rcall isr ; ADC Conversion Complete
- .org 50
-000032 d109 rcall isr ; EEPROM Ready
- .org 52
-000034 d107 rcall isr ; 2-wire Serial Interface
- .org 54
-000036 d105 rcall isr ; Store Program Memory Read
- .org 56
-000038 d103 rcall isr ; USART1 RX complete
- .org 58
-00003a d101 rcall isr ; USART1 Data Register Empty
- .org 60
-00003c d0ff rcall isr ; USART1 TX complete
- .org 62
-00003e d0fd rcall isr ; Timer/Counter3 Capture Event
- .org 64
-000040 d0fb rcall isr ; Timer/Counter3 Compare Match A
- .org 66
-000042 d0f9 rcall isr ; Timer/Counter3 Compare Match B
- .org 68
-000044 d0f7 rcall isr ; Timer/Counter3 Overflow
- .equ INTVECTORS = 35
- .nooverlap
-
- ; compatability layer (maybe empty)
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000045 4000 .dw 16384
- mcu_eepromsize:
-000046 1000 .dw 4096
- mcu_maxdp:
-000047 ffff .dw 65535
- mcu_numints:
-000048 0023 .dw 35
- mcu_name:
-000049 000b .dw 11
-00004a 5441
-00004b 656d
-00004c 6167
-00004d 3231
-00004e 3438
-00004f 0050 .db "ATmega1284P",0
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set AMFORTH_RO_SEG = NRWW_START_ADDR+1
-
- ; cpu clock in hertz
- .equ F_CPU = 16000000
- .set BAUD_MAXERROR = 30
- .equ TIMER_INT = OVF2addr
-
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .equ URXCaddr = URXC0addr
- .equ UDREaddr = UDRE0addr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-000050 ff07 .dw $ff07
-000051 723e
-000052 2d78
-000053 7562
-000054 0066 .db ">rx-buf",0
-000055 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000056 0057 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000057 2f08 mov temp0, tosl
-000058 9110 0110 lds temp1, usart_rx_in
-00005a e0e0 ldi zl, low(usart_rx_data)
-00005b e0f1 ldi zh, high(usart_rx_data)
-00005c 0fe1 add zl, temp1
-00005d 1df3 adc zh, zeroh
-00005e 8300 st Z, temp0
-00005f 9513 inc temp1
-000060 701f andi temp1,usart_rx_mask
-000061 9310 0110 sts usart_rx_in, temp1
-000063 9189
-000064 9199 loadtos
-000065 940c f005 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000067 ff06 .dw $ff06
-000068 7369
-000069 2d72
-00006a 7872 .db "isr-rx"
-00006b 0050 .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-00006c f001 .dw DO_COLON
- usart_rx_isr:
-00006d f046 .dw XT_DOLITERAL
-00006e 00c6 .dw usart_data
-00006f f0aa .dw XT_CFETCH
-000070 f0c3 .dw XT_DUP
-000071 f046 .dw XT_DOLITERAL
-000072 0003 .dw 3
-000073 fd9a .dw XT_EQUAL
-000074 f03f .dw XT_DOCONDBRANCH
-000075 0077 .dw usart_rx_isr1
-000076 fa74 .dw XT_COLD
- usart_rx_isr1:
-000077 0056 .dw XT_TO_RXBUF
-000078 f026 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-000079 f001 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-00007a f046
-00007b 006c .dw XT_DOLITERAL, XT_ISR_RX
-00007c f046
-00007d 0028 .dw XT_DOLITERAL, URXCaddr
-00007e f4a2 .dw XT_INTSTORE
-
-00007f f046 .dw XT_DOLITERAL
-000080 0100 .dw usart_rx_data
-000081 f046 .dw XT_DOLITERAL
-000082 0016 .dw usart_rx_size + 6
-000083 f166 .dw XT_ZERO
-000084 f4ea .dw XT_FILL
-000085 f026 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000086 ff06 .dw $ff06
-000087 7872
-000088 622d
-000089 6675 .db "rx-buf"
-00008a 0067 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-00008b f001 .dw DO_COLON
- PFA_RX_BUFFER:
-00008c 00a6 .dw XT_RXQ_BUFFER
-00008d f03f .dw XT_DOCONDBRANCH
-00008e 008c .dw PFA_RX_BUFFER
-00008f f046 .dw XT_DOLITERAL
-000090 0111 .dw usart_rx_out
-000091 f0aa .dw XT_CFETCH
-000092 f0c3 .dw XT_DUP
-000093 f046 .dw XT_DOLITERAL
-000094 0100 .dw usart_rx_data
-000095 f1af .dw XT_PLUS
-000096 f0aa .dw XT_CFETCH
-000097 f0d6 .dw XT_SWAP
-000098 f241 .dw XT_1PLUS
-000099 f046 .dw XT_DOLITERAL
-00009a 000f .dw usart_rx_mask
-00009b f225 .dw XT_AND
-00009c f046 .dw XT_DOLITERAL
-00009d 0111 .dw usart_rx_out
-00009e f09f .dw XT_CSTORE
-00009f f026 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-0000a0 ff07 .dw $ff07
-0000a1 7872
-0000a2 2d3f
-0000a3 7562
-0000a4 0066 .db "rx?-buf",0
-0000a5 0086 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-0000a6 f001 .dw DO_COLON
- PFA_RXQ_BUFFER:
-0000a7 fa6c .dw XT_PAUSE
-0000a8 f046 .dw XT_DOLITERAL
-0000a9 0111 .dw usart_rx_out
-0000aa f0aa .dw XT_CFETCH
-0000ab f046 .dw XT_DOLITERAL
-0000ac 0110 .dw usart_rx_in
-0000ad f0aa .dw XT_CFETCH
-0000ae f125 .dw XT_NOTEQUAL
-0000af f026 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-0000b0 ff07 .dw $ff07
-0000b1 7874
-0000b2 702d
-0000b3 6c6f
-0000b4 006c .db "tx-poll",0
-0000b5 00a0 .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000b6 f001 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000b7 00c4 .dw XT_TXQ_POLL
-0000b8 f03f .dw XT_DOCONDBRANCH
-0000b9 00b7 .dw PFA_TX_POLL
- ; send to usart
-0000ba f046 .dw XT_DOLITERAL
-0000bb 00c6 .dw USART_DATA
-0000bc f09f .dw XT_CSTORE
-0000bd f026 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000be ff08 .dw $ff08
-0000bf 7874
-0000c0 2d3f
-0000c1 6f70
-0000c2 6c6c .db "tx?-poll"
-0000c3 00b0 .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000c4 f001 .dw DO_COLON
- PFA_TXQ_POLL:
-0000c5 fa6c .dw XT_PAUSE
-0000c6 f046 .dw XT_DOLITERAL
-0000c7 00c0 .dw USART_A
-0000c8 f0aa .dw XT_CFETCH
-0000c9 f046 .dw XT_DOLITERAL
-0000ca 0020 .dw bm_USART_TXRD
-0000cb f225 .dw XT_AND
-0000cc f026 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000cd ff04 .dw $ff04
-0000ce 6275
-0000cf 7272 .db "ubrr"
-0000d0 00be .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000d1 f081 .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000d2 009e .dw EE_UBRRVAL
-0000d3 fbcf .dw XT_EDEFERFETCH
-0000d4 fbd9 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000d5 ff06 .dw $ff06
-0000d6 752b
-0000d7 6173
-0000d8 7472 .db "+usart"
-0000d9 00cd .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000da f001 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000db f046 .dw XT_DOLITERAL
-0000dc 0098 .dw USART_B_VALUE
-0000dd f046 .dw XT_DOLITERAL
-0000de 00c1 .dw USART_B
-0000df f09f .dw XT_CSTORE
-
-0000e0 f046 .dw XT_DOLITERAL
-0000e1 0006 .dw USART_C_VALUE
-0000e2 f046 .dw XT_DOLITERAL
-0000e3 00c2 .dw USART_C | bm_USARTC_en
-0000e4 f09f .dw XT_CSTORE
-
-0000e5 00d1 .dw XT_UBRR
-0000e6 f0c3 .dw XT_DUP
-0000e7 f30b .dw XT_BYTESWAP
-0000e8 f046 .dw XT_DOLITERAL
-0000e9 00c5 .dw BAUDRATE_HIGH
-0000ea f09f .dw XT_CSTORE
-0000eb f046 .dw XT_DOLITERAL
-0000ec 00c4 .dw BAUDRATE_LOW
-0000ed f09f .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000ee 0079 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000ef f026 .dw XT_EXIT
-
- ; settings for 1wire interface
- .equ OW_PORT=PORTB
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-0000f0 ff08 .dw $ff08
-0000f1 7731
-0000f2 722e
-0000f3 7365
-0000f4 7465 .db "1w.reset"
-0000f5 00d5 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-0000f6 00f7 .dw PFA_OW_RESET
- PFA_OW_RESET:
-0000f7 939a
-0000f8 938a savetos
- ; setup to output
-0000f9 9a24 sbi OW_DDR, OW_BIT
- ; Pull output low
-0000fa 982c cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-0000fb e8e0
-0000fc e0f7
-0000fd 9731
-0000fe f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-0000ff b71f in temp1, SREG
-000100 94f8 cli
- ; Pull output high
-000101 9a2c sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-000102 9824 cbi OW_DDR, OW_BIT
-000103 e0e0
-000104 e0f1
-000105 9731
-000106 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-000107 b183 in tosl, OW_PIN
-000108 ff84 sbrs tosl, OW_BIT
-000109 ef9f ser tosh
- ; End critical timing period, enable interrupts
-00010a bf1f out SREG, temp1
- ; release bus
-00010b 9824 cbi OW_DDR, OW_BIT
-00010c 982c cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-00010d e8e0
-00010e e0f6
-00010f 9731
-000110 f7f1 DELAY 416
- ; we now have the result flag in TOS
-000111 2f89 mov tosl, tosh
-000112 940c f005 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-000114 ff07 .dw $ff07
-000115 7731
-000116 732e
-000117 6f6c
-000118 0074 .db "1w.slot",0
-000119 00f0 .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-00011a 011b .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-00011b 982c cbi OW_PORT, OW_BIT
-00011c 9a24 sbi OW_DDR, OW_BIT
- ; disable interrupts
-00011d b71f in temp1, SREG
-00011e 94f8 cli
-00011f e1e8
-000120 e0f0
-000121 9731
-000122 f7f1 DELAY 6 ; DELAY A
- ; check bit
-000123 9488 clc
-000124 9587 ror tosl
-000125 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000126 9a2c sbi OW_PORT, OW_BIT
-000127 9824 cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-000128 e2e4
-000129 e0f0
-00012a 9731
-00012b f7f1 DELAY 9 ; wait DELAY E to sample
-00012c b103 in temp0, OW_PIN
-00012d fd04 sbrc temp0, OW_BIT
-00012e 6880 ori tosl, $80
-
-00012f ecec
-000130 e0f0
-000131 9731
-000132 f7f1 DELAY 51 ; DELAY B
-000133 9a2c sbi OW_PORT, OW_BIT ; release bus
-000134 9824 cbi OW_DDR, OW_BIT
-000135 e0e8
-000136 e0f0
-000137 9731
-000138 f7f1 delay 2
- ; re-enable interrupts
-000139 bf1f out SREG, temp1
-00013a 940c f005 jmp_ DO_NEXT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c fa75 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-00013c 920a st -Y, r0
-00013d b60f in r0, SREG
-00013e 920a st -Y, r0
- .if (pclen==3)
- .endif
-00013f 900f pop r0
-000140 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-000141 940a dec r0
- .if intvecsize == 1 ;
- .endif
-000142 2cb0 mov isrflag, r0
-000143 93ff push zh
-000144 93ef push zl
-000145 e1e2 ldi zl, low(intcnt)
-000146 e0f1 ldi zh, high(intcnt)
-000147 9406 lsr r0 ; we use byte addresses in the counter array, not words
-000148 0de0 add zl, r0
-000149 1df3 adc zh, zeroh
-00014a 8000 ld r0, Z
-00014b 9403 inc r0
-00014c 8200 st Z, r0
-00014d 91ef pop zl
-00014e 91ff pop zh
-
-00014f 9009 ld r0, Y+
-000150 be0f out SREG, r0
-000151 9009 ld r0, Y+
-000152 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000153 ff02 .dw $ff02
-000154 2b6d .db "m+"
-000155 0114 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000156 f001 .dw DO_COLON
- PFA_MPLUS:
-000157 fd82 .dw XT_S2D
-000158 f430 .dw XT_DPLUS
-000159 f026 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00015a ff03 .dw $ff03
-00015b 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-00015c 002a .db "ud*"
-00015d 0153 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-00015e f001 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-00015f f0c3
-000160 f111
-000161 f1f2
-000162 f0eb .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000163 f0d6
-000164 f108
-000165 f1f2
-000166 f0f3
-000167 f1af
-000168 f026 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-000169 ff04 .dw $ff04
-00016a 6d75
-00016b 7861 .db "umax"
-00016c 015a .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00016d f001 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-00016e f580
-00016f f16e .DW XT_2DUP,XT_ULESS
-000170 f03f .dw XT_DOCONDBRANCH
-000171 0173 DEST(UMAX1)
-000172 f0d6 .DW XT_SWAP
-000173 f0eb UMAX1: .DW XT_DROP
-000174 f026 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000175 ff04 .dw $ff04
-000176 6d75
-000177 6e69 .db "umin"
-000178 0169 .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-000179 f001 .dw DO_COLON
- PFA_UMIN:
- .endif
-00017a f580
-00017b f179 .DW XT_2DUP,XT_UGREATER
-00017c f03f .dw XT_DOCONDBRANCH
-00017d 017f DEST(UMIN1)
-00017e f0d6 .DW XT_SWAP
-00017f f0eb UMIN1: .DW XT_DROP
-000180 f026 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000181 f001 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000182 f046 .dw XT_DOLITERAL
-000183 8000 .dw $8000
-000184 f225 .dw XT_AND
-000185 f12c .dw XT_ZEROEQUAL
-000186 f03f .dw XT_DOCONDBRANCH
-000187 018a DEST(IMMEDIATEQ1)
-000188 fda1 .dw XT_ONE
-000189 f026 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00018a f15d .dw XT_TRUE
-00018b f026 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00018c ff0a .dw $ff0a
-00018d 616e
-00018e 656d
-00018f 663e
-000190 616c
-000191 7367 .db "name>flags"
-000192 0175 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000193 f001 .dw DO_COLON
- PFA_NAME2FLAGS:
-000194 f3e3 .dw XT_FETCHI ; skip to link field
-000195 f046 .dw XT_DOLITERAL
-000196 ff00 .dw $ff00
-000197 f225 .dw XT_AND
-000198 f026 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .include "dict/appl_8k.inc"
-
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-000199 ff06 .dw $ff06
-00019a 656e
-00019b 6577
-00019c 7473 .db "newest"
-00019d 018c .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-00019e f054 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-00019f 0135 .dw ram_newest
-
- .dseg
-000135 ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-0001a0 ff06 .dw $ff06
-0001a1 616c
-0001a2 6574
-0001a3 7473 .db "latest"
-0001a4 0199 .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-0001a5 f054 .dw PFA_DOVARIABLE
- PFA_LATEST:
-0001a6 0139 .dw ram_latest
-
- .dseg
-000139 ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-0001a7 ff08 .dw $ff08
-0001a8 6328
-0001a9 6572
-0001aa 7461
-0001ab 2965 .db "(create)"
-0001ac 01a0 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-0001ad f001 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-0001ae f9cf
-0001af 0304 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-0001b0 f0c3
-0001b1 019e
-0001b2 f579
-0001b3 f093 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-0001b4 02e9
-0001b5 019e
-0001b6 f093 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-0001b7 f026 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-0001b8 0001 .dw $0001
-0001b9 005c .db $5c,0
-0001ba 01a7 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-0001bb f001 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-0001bc f9b6 .dw XT_SOURCE
-0001bd f102 .dw XT_NIP
-0001be f599 .dw XT_TO_IN
-0001bf f093 .dw XT_STORE
-0001c0 f026 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-0001c1 0001 .dw $0001
-0001c2 0028 .db "(" ,0
-0001c3 01b8 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-0001c4 f001 .dw DO_COLON
- PFA_LPAREN:
- .endif
-0001c5 f046 .dw XT_DOLITERAL
-0001c6 0029 .dw ')'
-0001c7 f9a2 .dw XT_PARSE
-0001c8 f589 .dw XT_2DROP
-0001c9 f026 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-0001ca ff07 .dw $ff07
-0001cb 6f63
-0001cc 706d
-0001cd 6c69
-0001ce 0065 .db "compile",0
-0001cf 01c1 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-0001d0 f001 .dw DO_COLON
- PFA_COMPILE:
- .endif
-0001d1 f108 .dw XT_R_FROM
-0001d2 f0c3 .dw XT_DUP
-0001d3 fbc6 .dw XT_ICELLPLUS
-0001d4 f111 .dw XT_TO_R
-0001d5 f3e3 .dw XT_FETCHI
-0001d6 01db .dw XT_COMMA
-0001d7 f026 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-0001d8 ff01 .dw $ff01
-0001d9 002c .db ',',0 ; ,
-0001da 01ca .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-0001db f001 .dw DO_COLON
- PFA_COMMA:
-0001dc f5c9 .dw XT_DP
-0001dd f385 .dw XT_STOREI
-0001de f5c9 .dw XT_DP
-0001df f241 .dw XT_1PLUS
-0001e0 fbb4 .dw XT_DOTO
-0001e1 f5ca .dw PFA_DP
-0001e2 f026 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-0001e3 0003 .dw $0003
-0001e4 275b
-0001e5 005d .db "[']",0
-0001e6 01d8 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-0001e7 f001 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-0001e8 f825 .dw XT_TICK
-0001e9 01f1 .dw XT_LITERAL
-0001ea f026 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-0001eb 0007 .dw $0007
-0001ec 696c
-0001ed 6574
-0001ee 6172
-0001ef 006c .db "literal",0
-0001f0 01e3 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-0001f1 f001 .dw DO_COLON
- PFA_LITERAL:
- .endif
-0001f2 01d0 .DW XT_COMPILE
-0001f3 f046 .DW XT_DOLITERAL
-0001f4 01db .DW XT_COMMA
-0001f5 f026 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-0001f6 0008 .dw $0008
-0001f7 6c73
-0001f8 7469
-0001f9 7265
-0001fa 6c61 .db "sliteral"
-0001fb 01eb .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-0001fc f001 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-0001fd 01d0 .dw XT_COMPILE
-0001fe f788 .dw XT_DOSLITERAL ; ( -- addr n)
-0001ff f796 .dw XT_SCOMMA
-000200 f026 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-000201 f001 .dw DO_COLON
- PFA_GMARK:
-000202 f5c9 .dw XT_DP
-000203 01d0 .dw XT_COMPILE
-000204 ffff .dw -1 ; ffff does not erase flash
-000205 f026 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000206 f001 .dw DO_COLON
- PFA_GRESOLVE:
-000207 fb72 .dw XT_QSTACK
-000208 f5c9 .dw XT_DP
-000209 f0d6 .dw XT_SWAP
-00020a f385 .dw XT_STOREI
-00020b f026 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-00020c f001 .dw DO_COLON
- PFA_LMARK:
-00020d f5c9 .dw XT_DP
-00020e f026 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-00020f f001 .dw DO_COLON
- PFA_LRESOLVE:
-000210 fb72 .dw XT_QSTACK
-000211 01db .dw XT_COMMA
-000212 f026 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-000213 0005 .dw $0005
-000214 6861
-000215 6165
-000216 0064 .db "ahead",0
-000217 01f6 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-000218 f001 .dw DO_COLON
- PFA_AHEAD:
- .endif
-000219 01d0 .dw XT_COMPILE
-00021a f035 .dw XT_DOBRANCH
-00021b 0201 .dw XT_GMARK
-00021c f026 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-00021d 0002 .dw $0002
-00021e 6669 .db "if"
-00021f 0213 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-000220 f001 .dw DO_COLON
- PFA_IF:
- .endif
-000221 01d0 .dw XT_COMPILE
-000222 f03f .dw XT_DOCONDBRANCH
-000223 0201 .dw XT_GMARK
-000224 f026 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-000225 0004 .dw $0004
-000226 6c65
-000227 6573 .db "else"
-000228 021d .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-000229 f001 .dw DO_COLON
- PFA_ELSE:
- .endif
-00022a 01d0 .dw XT_COMPILE
-00022b f035 .dw XT_DOBRANCH
-00022c 0201 .dw XT_GMARK
-00022d f0d6 .dw XT_SWAP
-00022e 0206 .dw XT_GRESOLVE
-00022f f026 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-000230 0004 .dw $0004
-000231 6874
-000232 6e65 .db "then"
-000233 0225 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-000234 f001 .dw DO_COLON
- PFA_THEN:
- .endif
-000235 0206 .dw XT_GRESOLVE
-000236 f026 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-000237 0005 .dw $0005
-000238 6562
-000239 6967
-00023a 006e .db "begin",0
-00023b 0230 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-00023c f001 .dw DO_COLON
- PFA_BEGIN:
- .endif
-00023d 020c .dw XT_LMARK
-00023e f026 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-00023f 0005 .dw $0005
-000240 6877
-000241 6c69
-000242 0065 .db "while",0
-000243 0237 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-000244 f001 .dw DO_COLON
- PFA_WHILE:
- .endif
-000245 0220 .dw XT_IF
-000246 f0d6 .dw XT_SWAP
-000247 f026 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-000248 0006 .dw $0006
-000249 6572
-00024a 6570
-00024b 7461 .db "repeat"
-00024c 023f .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-00024d f001 .dw DO_COLON
- PFA_REPEAT:
- .endif
-00024e 0261 .dw XT_AGAIN
-00024f 0234 .dw XT_THEN
-000250 f026 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-000251 0005 .dw $0005
-000252 6e75
-000253 6974
-000254 006c .db "until",0
-000255 0248 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-000256 f001 .dw DO_COLON
- PFA_UNTIL:
- .endif
-000257 f046 .dw XT_DOLITERAL
-000258 f03f .dw XT_DOCONDBRANCH
-000259 01db .dw XT_COMMA
-
-00025a 020f .dw XT_LRESOLVE
-00025b f026 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-00025c 0005 .dw $0005
-00025d 6761
-00025e 6961
-00025f 006e .db "again",0
-000260 0251 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-000261 f001 .dw DO_COLON
- PFA_AGAIN:
- .endif
-000262 01d0 .dw XT_COMPILE
-000263 f035 .dw XT_DOBRANCH
-000264 020f .dw XT_LRESOLVE
-000265 f026 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-000266 0002 .dw $0002
-000267 6f64 .db "do"
-000268 025c .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-000269 f001 .dw DO_COLON
- PFA_DO:
-
- .endif
-00026a 01d0 .dw XT_COMPILE
-00026b f2ad .dw XT_DODO
-00026c 020c .dw XT_LMARK
-00026d f166 .dw XT_ZERO
-00026e 02c4 .dw XT_TO_L
-00026f f026 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-000270 0004 .dw $0004
-000271 6f6c
-000272 706f .db "loop"
-000273 0266 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000274 f001 .dw DO_COLON
- PFA_LOOP:
- .endif
-000275 01d0 .dw XT_COMPILE
-000276 f2db .dw XT_DOLOOP
-000277 02ab .dw XT_ENDLOOP
-000278 f026 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-000279 0005 .dw $0005
-00027a 6c2b
-00027b 6f6f
-00027c 0070 .db "+loop",0
-00027d 0270 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-00027e f001 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-00027f 01d0 .dw XT_COMPILE
-000280 f2cc .dw XT_DOPLUSLOOP
-000281 02ab .dw XT_ENDLOOP
-000282 f026 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-000283 0005 .dw $0005
-000284 656c
-000285 7661
-000286 0065 .db "leave",0
-000287 0279 .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-000288 f001 .dw DO_COLON
- PFA_LEAVE:
- .endif
-000289 01d0
-00028a f2e6 .DW XT_COMPILE,XT_UNLOOP
-00028b 0218
-00028c 02c4
-00028d f026 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-00028e 0003 .dw $0003
-00028f 643f
-000290 006f .db "?do",0
-000291 0283 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000292 f001 .dw DO_COLON
- PFA_QDO:
- .endif
-000293 01d0 .dw XT_COMPILE
-000294 029a .dw XT_QDOCHECK
-000295 0220 .dw XT_IF
-000296 0269 .dw XT_DO
-000297 f0d6 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-000298 02c4 .dw XT_TO_L ; then follows at the end.
-000299 f026 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00029a f001 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00029b f580 .dw XT_2DUP
-00029c fd9a .dw XT_EQUAL
-00029d f0c3 .dw XT_DUP
-00029e f111 .dw XT_TO_R
-00029f f03f .dw XT_DOCONDBRANCH
-0002a0 02a2 DEST(PFA_QDOCHECK1)
-0002a1 f589 .dw XT_2DROP
- PFA_QDOCHECK1:
-0002a2 f108 .dw XT_R_FROM
-0002a3 f20f .dw XT_INVERT
-0002a4 f026 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-0002a5 ff07 .dw $ff07
-0002a6 6e65
-0002a7 6c64
-0002a8 6f6f
-0002a9 0070 .db "endloop",0
-0002aa 028e .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-0002ab f001 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-0002ac 020f .DW XT_LRESOLVE
-0002ad 02b8
-0002ae f0cb
-0002af f03f LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-0002b0 02b4 DEST(LOOP2)
-0002b1 0234 .DW XT_THEN
-0002b2 f035 .dw XT_DOBRANCH
-0002b3 02ad DEST(LOOP1)
-0002b4 f026 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-0002b5 ff02 .dw $ff02
-0002b6 3e6c .db "l>"
-0002b7 02a5 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-0002b8 f001 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-0002b9 02d7 .dw XT_LP
-0002ba f08b .dw XT_FETCH
-0002bb f08b .dw XT_FETCH
-0002bc f046 .dw XT_DOLITERAL
-0002bd fffe .dw -2
-0002be 02d7 .dw XT_LP
-0002bf f277 .dw XT_PLUSSTORE
-0002c0 f026 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-0002c1 ff02 .dw $ff02
-0002c2 6c3e .db ">l"
-0002c3 02b5 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-0002c4 f001 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-0002c5 fda6 .dw XT_TWO
-0002c6 02d7 .dw XT_LP
-0002c7 f277 .dw XT_PLUSSTORE
-0002c8 02d7 .dw XT_LP
-0002c9 f08b .dw XT_FETCH
-0002ca f093 .dw XT_STORE
-0002cb f026 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-0002cc ff03 .dw $ff03
-0002cd 706c
-0002ce 0030 .db "lp0",0
-0002cf 02c1 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-0002d0 f081 .dw PFA_DOVALUE1
- PFA_LP0:
-0002d1 0052 .dw CFG_LP0
-0002d2 fbcf .dw XT_EDEFERFETCH
-0002d3 fbd9 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-0002d4 ff02 .dw $ff02
-0002d5 706c .db "lp"
-0002d6 02cc .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-0002d7 f054 .dw PFA_DOVARIABLE
- PFA_LP:
-0002d8 013b .dw ram_lp
-
- .dseg
-00013b ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-0002d9 ff06 .dw $ff06
-0002da 7263
-0002db 6165
-0002dc 6574 .db "create"
-0002dd 02d4 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-0002de f001 .dw DO_COLON
- PFA_CREATE:
- .endif
-0002df 01ad .dw XT_DOCREATE
-0002e0 030d .dw XT_REVEAL
-0002e1 01d0 .dw XT_COMPILE
-0002e2 f061 .dw PFA_DOCONSTANT
-0002e3 f026 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-0002e4 ff06 .dw $ff06
-0002e5 6568
-0002e6 6461
-0002e7 7265 .db "header"
-0002e8 02d9 .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-0002e9 f001 .dw DO_COLON
- PFA_HEADER:
-0002ea f5c9 .dw XT_DP ; the new Name Field
-0002eb f111 .dw XT_TO_R
-0002ec f111 .dw XT_TO_R ; ( R: NFA WID )
-0002ed f0c3 .dw XT_DUP
-0002ee f13a .dw XT_GREATERZERO
-0002ef f03f .dw XT_DOCONDBRANCH
-0002f0 02fb .dw PFA_HEADER1
-0002f1 f0c3 .dw XT_DUP
-0002f2 f046 .dw XT_DOLITERAL
-0002f3 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-0002f4 f22e .dw XT_OR
-0002f5 f79a .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-0002f6 f108 .dw XT_R_FROM
-0002f7 f371 .dw XT_FETCHE
-0002f8 01db .dw XT_COMMA
-0002f9 f108 .dw XT_R_FROM
-0002fa f026 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-0002fb f046 .dw XT_DOLITERAL
-0002fc fff0 .dw -16
-0002fd f85c .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-0002fe ff07 .dw $ff07
-0002ff 6c77
-000300 6373
-000301 706f
-000302 0065 .db "wlscope",0
-000303 02e4 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000304 fc2e .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000305 004e .dw CFG_WLSCOPE
-000306 fbcf .dw XT_EDEFERFETCH
-000307 fbd9 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000308 ff06 .dw $ff06
-000309 6572
-00030a 6576
-00030b 6c61 .db "reveal"
-00030c 02fe .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-00030d f001 .dw DO_COLON
- PFA_REVEAL:
- .endif
-00030e 019e
-00030f f579
-000310 f08b .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-000311 f0cb
-000312 f03f .DW XT_QDUP,XT_DOCONDBRANCH
-000313 0318 DEST(REVEAL1)
-000314 019e
-000315 f08b
-000316 f0d6
-000317 f34d .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-000318 f026 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-000319 0005 .dw $0005
-00031a 6f64
-00031b 7365
-00031c 003e .db "does>",0
-00031d 0308 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-00031e f001 .dw DO_COLON
- PFA_DOES:
-00031f 01d0 .dw XT_COMPILE
-000320 0331 .dw XT_DODOES
-000321 01d0 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-000322 940e .dw $940e ; the address of this compiled
-000323 01d0 .dw XT_COMPILE ; code will replace the XT of the
-000324 0326 .dw DO_DODOES ; word that CREATE created
-000325 f026 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-000326 939a
-000327 938a savetos
-000328 01cb movw tosl, wl
-000329 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-00032a 917f pop wh
-00032b 916f pop wl
-
-00032c 93bf push XH
-00032d 93af push XL
-00032e 01db movw XL, wl
-00032f 940c f005 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-000331 f001 .dw DO_COLON
- PFA_DODOES:
-000332 f108 .dw XT_R_FROM
-000333 019e .dw XT_NEWEST
-000334 f579 .dw XT_CELLPLUS
-000335 f08b .dw XT_FETCH
-000336 f371 .dw XT_FETCHE
-000337 fc99 .dw XT_NFA2CFA
-000338 f385 .dw XT_STOREI
-000339 f026 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-00033a ff01 .dw $ff01
-00033b 003a .db ":",0
-00033c 0319 .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-00033d f001 .dw DO_COLON
- PFA_COLON:
- .endif
-00033e 01ad .dw XT_DOCREATE
-00033f 0348 .dw XT_COLONNONAME
-000340 f0eb .dw XT_DROP
-000341 f026 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-000342 ff07 .dw $ff07
-000343 6e3a
-000344 6e6f
-000345 6d61
-000346 0065 .db ":noname",0
-000347 033a .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-000348 f001 .dw DO_COLON
- PFA_COLONNONAME:
-000349 f5c9 .dw XT_DP
-00034a f0c3 .dw XT_DUP
-00034b 01a5 .dw XT_LATEST
-00034c f093 .dw XT_STORE
-
-00034d 01d0 .dw XT_COMPILE
-00034e f001 .dw DO_COLON
-
-00034f 035d .dw XT_RBRACKET
-000350 f026 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-000351 0001 .dw $0001
-000352 003b .db $3b,0
-000353 0342 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-000354 f001 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-000355 01d0 .dw XT_COMPILE
-000356 f026 .dw XT_EXIT
-000357 0365 .dw XT_LBRACKET
-000358 030d .dw XT_REVEAL
-000359 f026 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-00035a ff01 .dw $ff01
-00035b 005d .db "]",0
-00035c 0351 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-00035d f001 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-00035e fda1 .dw XT_ONE
-00035f f566 .dw XT_STATE
-000360 f093 .dw XT_STORE
-000361 f026 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-000362 0001 .dw $0001
-000363 005b .db "[",0
-000364 035a .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-000365 f001 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-000366 f166 .dw XT_ZERO
-000367 f566 .dw XT_STATE
-000368 f093 .dw XT_STORE
-000369 f026 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-00036a ff08 .dw $ff08
-00036b 6176
-00036c 6972
-00036d 6261
-00036e 656c .db "variable"
-00036f 0362 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-000370 f001 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-000371 f5da .dw XT_HERE
-000372 037c .dw XT_CONSTANT
-000373 fda6 .dw XT_TWO
-000374 f5e3 .dw XT_ALLOT
-000375 f026 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-000376 ff08 .dw $ff08
-000377 6f63
-000378 736e
-000379 6174
-00037a 746e .db "constant"
-00037b 036a .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-00037c f001 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-00037d 01ad .dw XT_DOCREATE
-00037e 030d .dw XT_REVEAL
-00037f 01d0 .dw XT_COMPILE
-000380 f054 .dw PFA_DOVARIABLE
-000381 01db .dw XT_COMMA
-000382 f026 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-000383 ff04 .dw $ff04
-000384 7375
-000385 7265 .db "user"
-000386 0376 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-000387 f001 .dw DO_COLON
- PFA_USER:
-000388 01ad .dw XT_DOCREATE
-000389 030d .dw XT_REVEAL
-
-00038a 01d0 .dw XT_COMPILE
-00038b f067 .dw PFA_DOUSER
-00038c 01db .dw XT_COMMA
-00038d f026 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-00038e 0007 .dw $0007
-00038f 6572
-000390 7563
-000391 7372
-000392 0065 .db "recurse",0
-000393 0383 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000394 f001 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000395 01a5 .dw XT_LATEST
-000396 f08b .dw XT_FETCH
-000397 01db .dw XT_COMMA
-000398 f026 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-000399 ff09 .dw $ff09
-00039a 6d69
-00039b 656d
-00039c 6964
-00039d 7461
-00039e 0065 .db "immediate",0
-00039f 038e .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-0003a0 f001 .dw DO_COLON
- PFA_IMMEDIATE:
-0003a1 0442 .dw XT_GET_CURRENT
-0003a2 f371 .dw XT_FETCHE
-0003a3 f0c3 .dw XT_DUP
-0003a4 f3e3 .dw XT_FETCHI
-0003a5 f046 .dw XT_DOLITERAL
-0003a6 7fff .dw $7fff
-0003a7 f225 .dw XT_AND
-0003a8 f0d6 .dw XT_SWAP
-0003a9 f385 .dw XT_STOREI
-0003aa f026 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-0003ab 0006 .dw $0006
-0003ac 635b
-0003ad 6168
-0003ae 5d72 .db "[char]"
-0003af 0399 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-0003b0 f001 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-0003b1 01d0 .dw XT_COMPILE
-0003b2 f046 .dw XT_DOLITERAL
-0003b3 f905 .dw XT_CHAR
-0003b4 01db .dw XT_COMMA
-0003b5 f026 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-0003b6 0006 .dw $0006
-0003b7 6261
-0003b8 726f
-0003b9 2274 .db "abort",'"'
-0003ba 03ab .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-0003bb f001 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-0003bc f4dc .dw XT_SQUOTE
-0003bd 01d0 .dw XT_COMPILE
-0003be 03cd .dw XT_QABORT
-0003bf f026 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-0003c0 ff05 .dw $ff05
-0003c1 6261
-0003c2 726f
-0003c3 0074 .db "abort",0
-0003c4 03b6 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-0003c5 f001 .dw DO_COLON
- PFA_ABORT:
- .endif
-0003c6 f15d .dw XT_TRUE
-0003c7 f85c .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-0003c8 ff06 .dw $ff06
-0003c9 613f
-0003ca 6f62
-0003cb 7472 .db "?abort"
-0003cc 03c0 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-0003cd f001 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-0003ce f0f3
-0003cf f03f .DW XT_ROT,XT_DOCONDBRANCH
-0003d0 03d3 DEST(QABO1)
-0003d1 f7bb
-0003d2 03c5 .DW XT_ITYPE,XT_ABORT
-0003d3 f589
-0003d4 f026 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-0003d5 ff09 .dw $ff09
-0003d6 6567
-0003d7 2d74
-0003d8 7473
-0003d9 6361
-0003da 006b .db "get-stack",0
-0003db 03c8 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-0003dc f001 .dw DO_COLON
- .endif
-0003dd f0c3 .dw XT_DUP
-0003de f579 .dw XT_CELLPLUS
-0003df f0d6 .dw XT_SWAP
-0003e0 f371 .dw XT_FETCHE
-0003e1 f0c3 .dw XT_DUP
-0003e2 f111 .dw XT_TO_R
-0003e3 f166 .dw XT_ZERO
-0003e4 f0d6 .dw XT_SWAP ; go from bigger to smaller addresses
-0003e5 029a .dw XT_QDOCHECK
-0003e6 f03f .dw XT_DOCONDBRANCH
-0003e7 03f3 DEST(PFA_N_FETCH_E2)
-0003e8 f2ad .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-0003e9 f2be .dw XT_I
-0003ea f247 .dw XT_1MINUS
-0003eb f573 .dw XT_CELLS ; ( -- ee-addr i*2 )
-0003ec f0e1 .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-0003ed f1af .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-0003ee f371 .dw XT_FETCHE ;( -- ee-addr item_i )
-0003ef f0d6 .dw XT_SWAP ;( -- item_i ee-addr )
-0003f0 f15d .dw XT_TRUE ; shortcut for -1
-0003f1 f2cc .dw XT_DOPLUSLOOP
-0003f2 03e9 DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-0003f3 f589 .dw XT_2DROP
-0003f4 f108 .dw XT_R_FROM
-0003f5 f026 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-0003f6 ff09 .dw $ff09
-0003f7 6573
-0003f8 2d74
-0003f9 7473
-0003fa 6361
-0003fb 006b .db "set-stack",0
-0003fc 03d5 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-0003fd f001 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-0003fe f0e1 .dw XT_OVER
-0003ff f133 .dw XT_ZEROLESS
-000400 f03f .dw XT_DOCONDBRANCH
-000401 0405 DEST(PFA_SET_STACK0)
-000402 f046 .dw XT_DOLITERAL
-000403 fffc .dw -4
-000404 f85c .dw XT_THROW
- PFA_SET_STACK0:
-000405 f580 .dw XT_2DUP
-000406 f34d .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000407 f0d6 .dw XT_SWAP
-000408 f166 .dw XT_ZERO
-000409 029a .dw XT_QDOCHECK
-00040a f03f .dw XT_DOCONDBRANCH
-00040b 0412 DEST(PFA_SET_STACK2)
-00040c f2ad .dw XT_DODO
- PFA_SET_STACK1:
-00040d f579 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-00040e f591 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-00040f f34d .dw XT_STOREE
-000410 f2db .dw XT_DOLOOP
-000411 040d DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-000412 f0eb .dw XT_DROP
-000413 f026 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-000414 ff09 .dw $ff09
-000415 616d
-000416 2d70
-000417 7473
-000418 6361
-000419 006b .db "map-stack",0
-00041a 03f6 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-00041b f001 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-00041c f0c3 .dw XT_DUP
-00041d f579 .dw XT_CELLPLUS
-00041e f0d6 .dw XT_SWAP
-00041f f371 .dw XT_FETCHE
-000420 f573 .dw XT_CELLS
-000421 fd79 .dw XT_BOUNDS
-000422 029a .dw XT_QDOCHECK
-000423 f03f .dw XT_DOCONDBRANCH
-000424 0437 DEST(PFA_MAPSTACK3)
-000425 f2ad .dw XT_DODO
- PFA_MAPSTACK1:
-000426 f2be .dw XT_I
-000427 f371 .dw XT_FETCHE ; -- i*x XT id
-000428 f0d6 .dw XT_SWAP
-000429 f111 .dw XT_TO_R
-00042a f11a .dw XT_R_FETCH
-00042b f030 .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-00042c f0cb .dw XT_QDUP
-00042d f03f .dw XT_DOCONDBRANCH
-00042e 0433 DEST(PFA_MAPSTACK2)
-00042f f108 .dw XT_R_FROM
-000430 f0eb .dw XT_DROP
-000431 f2e6 .dw XT_UNLOOP
-000432 f026 .dw XT_EXIT
- PFA_MAPSTACK2:
-000433 f108 .dw XT_R_FROM
-000434 fda6 .dw XT_TWO
-000435 f2cc .dw XT_DOPLUSLOOP
-000436 0426 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-000437 f0eb .dw XT_DROP
-000438 f166 .dw XT_ZERO
-000439 f026 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-00043a ff0b .dw $ff0b
-00043b 6567
-00043c 2d74
-00043d 7563
-00043e 7272
-00043f 6e65
-000440 0074 .db "get-current",0
-000441 0414 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-000442 f001 .dw DO_COLON
- PFA_GET_CURRENT:
-000443 f046 .dw XT_DOLITERAL
-000444 0058 .dw CFG_CURRENT
-000445 f371 .dw XT_FETCHE
-000446 f026 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-000447 ff09 .dw $ff09
-000448 6567
-000449 2d74
-00044a 726f
-00044b 6564
-00044c 0072 .db "get-order",0
-00044d 043a .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-00044e f001 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-00044f f046 .dw XT_DOLITERAL
-000450 005c .dw CFG_ORDERLISTLEN
-000451 03dc .dw XT_GET_STACK
-000452 f026 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-000453 ff09 .dw $ff09
-000454 6663
-000455 2d67
-000456 726f
-000457 6564
-000458 0072 .db "cfg-order",0
-000459 0447 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-00045a f054 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-00045b 005c .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-00045c ff07 .dw $ff07
-00045d 6f63
-00045e 706d
-00045f 7261
-000460 0065 .db "compare",0
-000461 0453 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-000462 0463 .dw PFA_COMPARE
- PFA_COMPARE:
-000463 93bf push xh
-000464 93af push xl
-000465 018c movw temp0, tosl
-000466 9189
-000467 9199 loadtos
-000468 01dc movw xl, tosl
-000469 9189
-00046a 9199 loadtos
-00046b 019c movw temp2, tosl
-00046c 9189
-00046d 9199 loadtos
-00046e 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-00046f 90ed ld temp4, X+
-000470 90f1 ld temp5, Z+
-000471 14ef cp temp4, temp5
-000472 f451 brne PFA_COMPARE_NOTEQUAL
-000473 950a dec temp0
-000474 f019 breq PFA_COMPARE_ENDREACHED2
-000475 952a dec temp2
-000476 f7c1 brne PFA_COMPARE_LOOP
-000477 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-000478 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-000479 2b02 or temp0, temp2
-00047a f411 brne PFA_COMPARE_CHECKLASTCHAR
-00047b 2788 clr tosl
-00047c c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-00047d ef8f ser tosl
-00047e c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-00047f 2f98 mov tosh, tosl
-000480 91af pop xl
-000481 91bf pop xh
-000482 940c f005 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000484 ff07 .dw $ff07
-000485 666e
-000486 3e61
-000487 666c
-000488 0061 .db "nfa>lfa",0
-000489 045c .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-00048a f001 .dw DO_COLON
- PFA_NFA2LFA:
-00048b fc8d .dw XT_NAME2STRING
-00048c f241 .dw XT_1PLUS
-00048d f216 .dw XT_2SLASH
-00048e f1af .dw XT_PLUS
-00048f f026 .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 4000
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
- .include "words/dot-s.asm"
-
- ; Tools
- ; stack dump
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTS:
-000490 ff02 .dw $ff02
-000491 732e .db ".s"
-000492 0484 .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
- XT_DOTS:
-000493 f001 .dw DO_COLON
- PFA_DOTS:
- .endif
-000494 fabc .dw XT_DEPTH
-000495 f463 .dw XT_UDOT
-000496 f7fd .dw XT_SPACE
-000497 fabc .dw XT_DEPTH
-000498 f166 .dw XT_ZERO
-000499 029a .dw XT_QDOCHECK
-00049a f03f .dw XT_DOCONDBRANCH
-00049b 04a2 DEST(PFA_DOTS2)
-00049c f2ad .dw XT_DODO
- PFA_DOTS1:
-00049d f2be .dw XT_I
-00049e f4ca .dw XT_PICK
-00049f f463 .dw XT_UDOT
-0004a0 f2db .dw XT_DOLOOP
-0004a1 049d DEST(PFA_DOTS1)
- PFA_DOTS2:
-0004a2 f026 .dw XT_EXIT
- .include "words/spirw.asm"
-
- ; MCU
- ; SPI exchange of 1 byte
- VE_SPIRW:
-0004a3 ff06 .dw $ff06
-0004a4 2163
-0004a5 7340
-0004a6 6970 .db "c!@spi"
-0004a7 0490 .dw VE_HEAD
- .set VE_HEAD = VE_SPIRW
- XT_SPIRW:
-0004a8 04a9 .dw PFA_SPIRW
- PFA_SPIRW:
-0004a9 d003 rcall do_spirw
-0004aa 2799 clr tosh
-0004ab 940c f005 jmp_ DO_NEXT
-
- do_spirw:
-0004ad bd8e out_ SPDR, tosl
- do_spirw1:
-0004ae b50d in_ temp0, SPSR
-0004af 7f08 cbr temp0,7
-0004b0 bd0d out_ SPSR, temp0
-0004b1 b50d in_ temp0, SPSR
-0004b2 ff07 sbrs temp0, 7
-0004b3 cffa rjmp do_spirw1 ; wait until complete
-0004b4 b58e in_ tosl, SPDR
-0004b5 9508 ret
- .include "words/n-spi.asm"
-
- ; MCU
- ; read len bytes from SPI to addr
- VE_N_SPIR:
-0004b6 ff05 .dw $ff05
-0004b7 406e
-0004b8 7073
-0004b9 0069 .db "n@spi",0
-0004ba 04a3 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIR
- XT_N_SPIR:
-0004bb 04bc .dw PFA_N_SPIR
- PFA_N_SPIR:
-0004bc 018c movw temp0, tosl
-0004bd 9189
-0004be 9199 loadtos
-0004bf 01fc movw zl, tosl
-0004c0 01c8 movw tosl, temp0
- PFA_N_SPIR_LOOP:
-0004c1 bc2e out_ SPDR, zerol
- PFA_N_SPIR_LOOP1:
-0004c2 b52d in_ temp2, SPSR
-0004c3 ff27 sbrs temp2, SPIF
-0004c4 cffd rjmp PFA_N_SPIR_LOOP1
-0004c5 b52e in_ temp2, SPDR
-0004c6 9321 st Z+, temp2
-0004c7 9701 sbiw tosl, 1
-0004c8 f7c1 brne PFA_N_SPIR_LOOP
-0004c9 9189
-0004ca 9199 loadtos
-0004cb 940c f005 jmp_ DO_NEXT
-
- ; ( addr len -- )
- ; MCU
- ; write len bytes to SPI from addr
- VE_N_SPIW:
-0004cd ff05 .dw $ff05
-0004ce 216e
-0004cf 7073
-0004d0 0069 .db "n!spi",0
-0004d1 04b6 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIW
- XT_N_SPIW:
-0004d2 04d3 .dw PFA_N_SPIW
- PFA_N_SPIW:
-0004d3 018c movw temp0, tosl
-0004d4 9189
-0004d5 9199 loadtos
-0004d6 01fc movw zl, tosl
-0004d7 01c8 movw tosl, temp0
- PFA_N_SPIW_LOOP:
-0004d8 9121 ld temp2, Z+
-0004d9 bd2e out_ SPDR, temp2
- PFA_N_SPIW_LOOP1:
-0004da b52d in_ temp2, SPSR
-0004db ff27 sbrs temp2, SPIF
-0004dc cffd rjmp PFA_N_SPIW_LOOP1
-0004dd b52e in_ temp2, SPDR ; ignore the data
-0004de 9701 sbiw tosl, 1
-0004df f7c1 brne PFA_N_SPIW_LOOP
-0004e0 9189
-0004e1 9199 loadtos
-0004e2 940c f005 jmp_ DO_NEXT
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-0004e4 ff0b .dw $ff0b
-0004e5 7061
-0004e6 6c70
-0004e7 7574
-0004e8 6e72
-0004e9 656b
-0004ea 0079 .db "applturnkey",0
-0004eb 04cd .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-0004ec f001 .dw DO_COLON
- PFA_APPLTURNKEY:
-0004ed 00da .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-0004ee f494 .dw XT_INTON
- .endif
-0004ef fb7f .dw XT_DOT_VER
-0004f0 f7fd .dw XT_SPACE
-0004f1 f55b .dw XT_F_CPU
-0004f2 f046 .dw XT_DOLITERAL
-0004f3 03e8 .dw 1000
-0004f4 f1d4 .dw XT_UMSLASHMOD
-0004f5 f102 .dw XT_NIP
-0004f6 f5f8 .dw XT_DECIMAL
-0004f7 f73d .dw XT_DOT
-0004f8 f788 .dw XT_DOSLITERAL
-0004f9 0004 .dw 4
-0004fa 486b
-0004fb 207a .db "kHz "
-0004fc f7bb .dw XT_ITYPE
-0004fd f026 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-0004fe ff0b .dw $ff0b
-0004ff 6573
-000500 2d74
-000501 7563
-000502 7272
-000503 6e65
-000504 0074 .db "set-current",0
-000505 04e4 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-000506 f001 .dw DO_COLON
- PFA_SET_CURRENT:
-000507 f046 .dw XT_DOLITERAL
-000508 0058 .dw CFG_CURRENT
-000509 f34d .dw XT_STOREE
-00050a f026 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-00050b ff08 .dw $ff08
-00050c 6f77
-00050d 6472
-00050e 696c
-00050f 7473 .db "wordlist"
-000510 04fe .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000511 f001 .dw DO_COLON
- PFA_WORDLIST:
-000512 f5d2 .dw XT_EHERE
-000513 f166 .dw XT_ZERO
-000514 f0e1 .dw XT_OVER
-000515 f34d .dw XT_STOREE
-000516 f0c3 .dw XT_DUP
-000517 f579 .dw XT_CELLPLUS
-000518 fbb4 .dw XT_DOTO
-000519 f5d3 .dw PFA_EHERE
-00051a f026 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-00051b ff0e .dw $ff0e
-00051c 6f66
-00051d 7472
-00051e 2d68
-00051f 6f77
-000520 6472
-000521 696c
-000522 7473 .db "forth-wordlist"
-000523 050b .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000524 f054 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000525 005a .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000526 ff09 .dw $ff09
-000527 6573
-000528 2d74
-000529 726f
-00052a 6564
-00052b 0072 .db "set-order",0
-00052c 051b .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-00052d f001 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-00052e f046 .dw XT_DOLITERAL
-00052f 005c .dw CFG_ORDERLISTLEN
-000530 03fd .dw XT_SET_STACK
-000531 f026 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000532 ff0f .dw $ff0f
-000533 6573
-000534 2d74
-000535 6572
-000536 6f63
-000537 6e67
-000538 7a69
-000539 7265
-00053a 0073 .db "set-recognizers",0
-00053b 0526 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-00053c f001 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-00053d f046 .dw XT_DOLITERAL
-00053e 006e .dw CFG_RECOGNIZERLISTLEN
-00053f 03fd .dw XT_SET_STACK
-000540 f026 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000541 ff0f .dw $ff0f
-000542 6567
-000543 2d74
-000544 6572
-000545 6f63
-000546 6e67
-000547 7a69
-000548 7265
-000549 0073 .db "get-recognizers",0
-00054a 0532 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-00054b f001 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-00054c f046 .dw XT_DOLITERAL
-00054d 006e .dw CFG_RECOGNIZERLISTLEN
-00054e 03dc .dw XT_GET_STACK
-00054f f026 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000550 ff04 .dw $ff04
-000551 6f63
-000552 6564 .db "code"
-000553 0541 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000554 f001 .dw DO_COLON
- PFA_CODE:
-000555 01ad .dw XT_DOCREATE
-000556 030d .dw XT_REVEAL
-000557 f5c9 .dw XT_DP
-000558 fbc6 .dw XT_ICELLPLUS
-000559 01db .dw XT_COMMA
-00055a f026 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-00055b ff08 .dw $ff08
-00055c 6e65
-00055d 2d64
-00055e 6f63
-00055f 6564 .db "end-code"
-000560 0550 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000561 f001 .dw DO_COLON
- PFA_ENDCODE:
-000562 01d0 .dw XT_COMPILE
-000563 940c .dw $940c
-000564 01d0 .dw XT_COMPILE
-000565 f005 .dw DO_NEXT
-000566 f026 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000567 ff08 .dw $ff08
-000568 6d28
-000569 7261
-00056a 656b
-00056b 2972 .db "(marker)"
-00056c 055b .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-00056d f081 .dw PFA_DOVALUE1
- PFA_MARKER:
-00056e 007a .dw EE_MARKER
-00056f fbcf .dw XT_EDEFERFETCH
-000570 fbd9 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000571 0008 .dw $0008
-000572 6f70
-000573 7473
-000574 6f70
-000575 656e .db "postpone"
-000576 0567 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000577 f001 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000578 f9cf .dw XT_PARSENAME
-000579 fae7 .dw XT_FORTHRECOGNIZER
-00057a faf2 .dw XT_RECOGNIZE
-00057b f0c3 .dw XT_DUP
-00057c f111 .dw XT_TO_R
-00057d fbc6 .dw XT_ICELLPLUS
-00057e fbc6 .dw XT_ICELLPLUS
-00057f f3e3 .dw XT_FETCHI
-000580 f030 .dw XT_EXECUTE
-000581 f108 .dw XT_R_FROM
-000582 fbc6 .dw XT_ICELLPLUS
-000583 f3e3 .dw XT_FETCHI
-000584 01db .dw XT_COMMA
-000585 f026 .dw XT_EXIT
- .endif
- .include "words/2r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_2R_FETCH:
-000586 ff03 .dw $ff03
-000587 7232
-000588 0040 .db "2r@",0
-000589 0571 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FETCH
- XT_2R_FETCH:
-00058a 058b .dw PFA_2R_FETCH
- PFA_2R_FETCH:
-00058b 939a
-00058c 938a savetos
-00058d 91ef pop zl
-00058e 91ff pop zh
-00058f 918f pop tosl
-000590 919f pop tosh
-000591 939f push tosh
-000592 938f push tosl
-000593 93ff push zh
-000594 93ef push zl
-000595 939a
-000596 938a savetos
-000597 01cf movw tosl, zl
-000598 940c f005 jmp_ DO_NEXT
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-00f001 93bf push XH
-00f002 93af push XL ; PUSH IP
-00f003 01db movw XL, wl
-00f004 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-00f005 14b2 cp isrflag, zerol
-00f006 f499 brne DO_INTERRUPT
- .endif
-00f007 01fd movw zl, XL ; READ IP
-00f008 2755
-00f009 0fee
-00f00a 1fff
-00f00b 1f55
-00f00c bf5b
-00f00d 9167
-00f00e 9177 readflashcell wl, wh
-00f00f 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00f010 01fb movw zl, wl
-00f011 2755
-00f012 0fee
-00f013 1fff
-00f014 1f55
-00f015 bf5b
-00f016 9107
-00f017 9117 readflashcell temp0,temp1
-00f018 01f8 movw zl, temp0
-00f019 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-00f01a 939a
-00f01b 938a savetos
-00f01c 2d8b mov tosl, isrflag
-00f01d 2799 clr tosh
-00f01e 24bb clr isrflag
-00f01f eb6d ldi wl, LOW(XT_ISREXEC)
-00f020 ef74 ldi wh, HIGH(XT_ISREXEC)
-00f021 cfee rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00f022 ff04 .dw $ff04
-00f023 7865
-00f024 7469 .db "exit"
-00f025 0586 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-00f026 f027 .dw PFA_EXIT
- PFA_EXIT:
-00f027 91af pop XL
-00f028 91bf pop XH
-00f029 cfdb jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-00f02a ff07 .dw $ff07
-00f02b 7865
-00f02c 6365
-00f02d 7475
-00f02e 0065 .db "execute",0
-00f02f f022 .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-00f030 f031 .dw PFA_EXECUTE
- PFA_EXECUTE:
-00f031 01bc movw wl, tosl
-00f032 9189
-00f033 9199 loadtos
-00f034 cfdb jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00f035 f036 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-00f036 01fd movw zl, XL
-00f037 2755
-00f038 0fee
-00f039 1fff
-00f03a 1f55
-00f03b bf5b
-00f03c 91a7
-00f03d 91b7 readflashcell XL,XH
-00f03e cfc6 jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-00f03f f040 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-00f040 2b98 or tosh, tosl
-00f041 9189
-00f042 9199 loadtos
-00f043 f391 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00f044 9611 adiw XL, 1
-00f045 cfbf jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00f046 f047 .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00f047 939a
-00f048 938a savetos
-00f049 01fd movw zl, xl
-00f04a 2755
-00f04b 0fee
-00f04c 1fff
-00f04d 1f55
-00f04e bf5b
-00f04f 9187
-00f050 9197 readflashcell tosl,tosh
-00f051 9611 adiw xl, 1
-00f052 cfb2 jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-00f053 f054 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-00f054 939a
-00f055 938a savetos
-00f056 01fb movw zl, wl
-00f057 9631 adiw zl,1
-00f058 2755
-00f059 0fee
-00f05a 1fff
-00f05b 1f55
-00f05c bf5b
-00f05d 9187
-00f05e 9197 readflashcell tosl,tosh
-00f05f cfa5 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-00f060 f061 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-00f061 939a
-00f062 938a savetos
-00f063 01cb movw tosl, wl
-00f064 9601 adiw tosl, 1
-00f065 cf9f jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-00f066 f067 .dw PFA_DOUSER
- PFA_DOUSER:
-00f067 939a
-00f068 938a savetos
-00f069 01fb movw zl, wl
-00f06a 9631 adiw zl, 1
-00f06b 2755
-00f06c 0fee
-00f06d 1fff
-00f06e 1f55
-00f06f bf5b
-00f070 9187
-00f071 9197 readflashcell tosl,tosh
-00f072 0d84 add tosl, upl
-00f073 1d95 adc tosh, uph
-00f074 cf90 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-00f075 ff07 .dw $ff07
-00f076 7628
-00f077 6c61
-00f078 6575
-00f079 0029 .db "(value)", 0
-00f07a f02a .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-00f07b f001 .dw DO_COLON
- PFA_DOVALUE:
-00f07c 01ad .dw XT_DOCREATE
-00f07d 030d .dw XT_REVEAL
-00f07e 01d0 .dw XT_COMPILE
-00f07f f081 .dw PFA_DOVALUE1
-00f080 f026 .dw XT_EXIT
- PFA_DOVALUE1:
-00f081 940e 0326 call_ DO_DODOES
-00f083 f0c3 .dw XT_DUP
-00f084 fbc6 .dw XT_ICELLPLUS
-00f085 f3e3 .dw XT_FETCHI
-00f086 f030 .dw XT_EXECUTE
-00f087 f026 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-00f088 ff01 .dw $ff01
-00f089 0040 .db "@",0
-00f08a f075 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-00f08b f08c .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-00f08c 01fc movw zl, tosl
- ; low byte is read before the high byte
-00f08d 9181 ld tosl, z+
-00f08e 9191 ld tosh, z+
-00f08f cf75 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00f090 ff01 .dw $ff01
-00f091 0021 .db "!",0
-00f092 f088 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-00f093 f094 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-00f094 01fc movw zl, tosl
-00f095 9189
-00f096 9199 loadtos
- ; the high byte is written before the low byte
-00f097 8391 std Z+1, tosh
-00f098 8380 std Z+0, tosl
-00f099 9189
-00f09a 9199 loadtos
-00f09b cf69 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-00f09c ff02 .dw $ff02
-00f09d 2163 .db "c!"
-00f09e f090 .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00f09f f0a0 .dw PFA_CSTORE
- PFA_CSTORE:
-00f0a0 01fc movw zl, tosl
-00f0a1 9189
-00f0a2 9199 loadtos
-00f0a3 8380 st Z, tosl
-00f0a4 9189
-00f0a5 9199 loadtos
-00f0a6 cf5e jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-00f0a7 ff02 .dw $ff02
-00f0a8 4063 .db "c@"
-00f0a9 f09c .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-00f0aa f0ab .dw PFA_CFETCH
- PFA_CFETCH:
-00f0ab 01fc movw zl, tosl
-00f0ac 2799 clr tosh
-00f0ad 8180 ld tosl, Z
-00f0ae cf56 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00f0af ff02 .dw $ff02
-00f0b0 7540 .db "@u"
-00f0b1 f0a7 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-00f0b2 f001 .dw DO_COLON
- PFA_FETCHU:
-00f0b3 f314 .dw XT_UP_FETCH
-00f0b4 f1af .dw XT_PLUS
-00f0b5 f08b .dw XT_FETCH
-00f0b6 f026 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-00f0b7 ff02 .dw $ff02
-00f0b8 7521 .db "!u"
-00f0b9 f0af .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-00f0ba f001 .dw DO_COLON
- PFA_STOREU:
-00f0bb f314 .dw XT_UP_FETCH
-00f0bc f1af .dw XT_PLUS
-00f0bd f093 .dw XT_STORE
-00f0be f026 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-00f0bf ff03 .dw $ff03
-00f0c0 7564
-00f0c1 0070 .db "dup",0
-00f0c2 f0b7 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-00f0c3 f0c4 .dw PFA_DUP
- PFA_DUP:
-00f0c4 939a
-00f0c5 938a savetos
-00f0c6 cf3e jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-00f0c7 ff04 .dw $ff04
-00f0c8 643f
-00f0c9 7075 .db "?dup"
-00f0ca f0bf .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-00f0cb f0cc .dw PFA_QDUP
- PFA_QDUP:
-00f0cc 2f08 mov temp0, tosl
-00f0cd 2b09 or temp0, tosh
-00f0ce f011 breq PFA_QDUP1
-00f0cf 939a
-00f0d0 938a savetos
- PFA_QDUP1:
-00f0d1 cf33 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-00f0d2 ff04 .dw $ff04
-00f0d3 7773
-00f0d4 7061 .db "swap"
-00f0d5 f0c7 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-00f0d6 f0d7 .dw PFA_SWAP
- PFA_SWAP:
-00f0d7 018c movw temp0, tosl
-00f0d8 9189
-00f0d9 9199 loadtos
-00f0da 931a st -Y, temp1
-00f0db 930a st -Y, temp0
-00f0dc cf28 jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-00f0dd ff04 .dw $ff04
-00f0de 766f
-00f0df 7265 .db "over"
-00f0e0 f0d2 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-00f0e1 f0e2 .dw PFA_OVER
- PFA_OVER:
-00f0e2 939a
-00f0e3 938a savetos
-00f0e4 818a ldd tosl, Y+2
-00f0e5 819b ldd tosh, Y+3
-
-00f0e6 cf1e jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-00f0e7 ff04 .dw $ff04
-00f0e8 7264
-00f0e9 706f .db "drop"
-00f0ea f0dd .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-00f0eb f0ec .dw PFA_DROP
- PFA_DROP:
-00f0ec 9189
-00f0ed 9199 loadtos
-00f0ee cf16 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-00f0ef ff03 .dw $ff03
-00f0f0 6f72
-00f0f1 0074 .db "rot",0
-00f0f2 f0e7 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-00f0f3 f0f4 .dw PFA_ROT
- PFA_ROT:
-00f0f4 018c movw temp0, tosl
-00f0f5 9129 ld temp2, Y+
-00f0f6 9139 ld temp3, Y+
-00f0f7 9189
-00f0f8 9199 loadtos
-
-00f0f9 933a st -Y, temp3
-00f0fa 932a st -Y, temp2
-00f0fb 931a st -Y, temp1
-00f0fc 930a st -Y, temp0
-
-00f0fd cf07 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-00f0fe ff03 .dw $ff03
-00f0ff 696e
-00f100 0070 .db "nip",0
-00f101 f0ef .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-00f102 f103 .dw PFA_NIP
- PFA_NIP:
-00f103 9622 adiw yl, 2
-00f104 cf00 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-00f105 ff02 .dw $ff02
-00f106 3e72 .db "r>"
-00f107 f0fe .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-00f108 f109 .dw PFA_R_FROM
- PFA_R_FROM:
-00f109 939a
-00f10a 938a savetos
-00f10b 918f pop tosl
-00f10c 919f pop tosh
-00f10d cef7 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-00f10e ff02 .dw $ff02
-00f10f 723e .db ">r"
-00f110 f105 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-00f111 f112 .dw PFA_TO_R
- PFA_TO_R:
-00f112 939f push tosh
-00f113 938f push tosl
-00f114 9189
-00f115 9199 loadtos
-00f116 ceee jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-00f117 ff02 .dw $ff02
-00f118 4072 .db "r@"
-00f119 f10e .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-00f11a f11b .dw PFA_R_FETCH
- PFA_R_FETCH:
-00f11b 939a
-00f11c 938a savetos
-00f11d 918f pop tosl
-00f11e 919f pop tosh
-00f11f 939f push tosh
-00f120 938f push tosl
-00f121 cee3 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-00f122 ff02 .dw $ff02
-00f123 3e3c .db "<>"
-00f124 f117 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-00f125 f001 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-00f126 fd9a
-00f127 f12c
-00f128 f026 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-00f129 ff02 .dw $ff02
-00f12a 3d30 .db "0="
-00f12b f122 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-00f12c f12d .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00f12d 2b98 or tosh, tosl
-00f12e f5d1 brne PFA_ZERO1
-00f12f c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00f130 ff02 .dw $ff02
-00f131 3c30 .db "0<"
-00f132 f129 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-00f133 f134 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-00f134 fd97 sbrc tosh,7
-00f135 c02a rjmp PFA_TRUE1
-00f136 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-00f137 ff02 .dw $ff02
-00f138 3e30 .db "0>"
-00f139 f130 .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-00f13a f13b .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-00f13b 1582 cp tosl, zerol
-00f13c 0593 cpc tosh, zeroh
-00f13d f15c brlt PFA_ZERO1
-00f13e f151 brbs 1, PFA_ZERO1
-00f13f c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00f140 ff03 .dw $ff03
-00f141 3064
-00f142 003e .db "d0>",0
-00f143 f137 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-00f144 f145 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-00f145 1582 cp tosl, zerol
-00f146 0593 cpc tosh, zeroh
-00f147 9189
-00f148 9199 loadtos
-00f149 0582 cpc tosl, zerol
-00f14a 0593 cpc tosh, zeroh
-00f14b f0ec brlt PFA_ZERO1
-00f14c f0e1 brbs 1, PFA_ZERO1
-00f14d c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00f14e ff03 .dw $ff03
-00f14f 3064
-00f150 003c .db "d0<",0
-00f151 f140 .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-00f152 f153 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-00f153 9622 adiw Y,2
-00f154 fd97 sbrc tosh,7
-00f155 940c f160 jmp PFA_TRUE1
-00f157 940c f169 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-00f159 ff04 .dw $ff04
-00f15a 7274
-00f15b 6575 .db "true"
-00f15c f14e .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00f15d f15e .dw PFA_TRUE
- PFA_TRUE:
-00f15e 939a
-00f15f 938a savetos
- PFA_TRUE1:
-00f160 ef8f ser tosl
-00f161 ef9f ser tosh
-00f162 cea2 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-00f163 ff01 .dw $ff01
-00f164 0030 .db "0",0
-00f165 f159 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-00f166 f167 .dw PFA_ZERO
- PFA_ZERO:
-00f167 939a
-00f168 938a savetos
- PFA_ZERO1:
-00f169 01c1 movw tosl, zerol
-00f16a ce9a jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-00f16b ff02 .dw $ff02
-00f16c 3c75 .db "u<"
-00f16d f163 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00f16e f16f .dw PFA_ULESS
- PFA_ULESS:
-00f16f 9129 ld temp2, Y+
-00f170 9139 ld temp3, Y+
-00f171 1782 cp tosl, temp2
-00f172 0793 cpc tosh, temp3
-00f173 f3a8 brlo PFA_ZERO1
-00f174 f3a1 brbs 1, PFA_ZERO1
-00f175 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-00f176 ff02 .dw $ff02
-00f177 3e75 .db "u>"
-00f178 f16b .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-00f179 f001 .dw DO_COLON
- PFA_UGREATER:
- .endif
-00f17a f0d6 .DW XT_SWAP
-00f17b f16e .dw XT_ULESS
-00f17c f026 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00f17d ff01 .dw $ff01
-00f17e 003c .db "<",0
-00f17f f176 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00f180 f181 .dw PFA_LESS
- PFA_LESS:
-00f181 9129 ld temp2, Y+
-00f182 9139 ld temp3, Y+
-00f183 1728 cp temp2, tosl
-00f184 0739 cpc temp3, tosh
- PFA_LESSDONE:
-00f185 f71c brge PFA_ZERO1
-00f186 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-00f187 ff01 .dw $ff01
-00f188 003e .db ">",0
-00f189 f17d .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-00f18a f18b .dw PFA_GREATER
- PFA_GREATER:
-00f18b 9129 ld temp2, Y+
-00f18c 9139 ld temp3, Y+
-00f18d 1728 cp temp2, tosl
-00f18e 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00f18f f2cc brlt PFA_ZERO1
-00f190 f2c1 brbs 1, PFA_ZERO1
-00f191 cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-00f192 ff04 .dw $ff04
-00f193 6f6c
-00f194 3267 .db "log2"
-00f195 f187 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-00f196 f197 .dw PFA_LOG2
- PFA_LOG2:
-00f197 01fc movw zl, tosl
-00f198 2799 clr tosh
-00f199 e180 ldi tosl, 16
- PFA_LOG2_1:
-00f19a 958a dec tosl
-00f19b f022 brmi PFA_LOG2_2 ; wrong data
-00f19c 0fee lsl zl
-00f19d 1fff rol zh
-00f19e f7d8 brcc PFA_LOG2_1
-00f19f ce65 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00f1a0 959a dec tosh
-00f1a1 ce63 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-00f1a2 ff01 .dw $ff01
-00f1a3 002d .db "-",0
-00f1a4 f192 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-00f1a5 f1a6 .dw PFA_MINUS
- PFA_MINUS:
-00f1a6 9109 ld temp0, Y+
-00f1a7 9119 ld temp1, Y+
-00f1a8 1b08 sub temp0, tosl
-00f1a9 0b19 sbc temp1, tosh
-00f1aa 01c8 movw tosl, temp0
-00f1ab ce59 jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-00f1ac ff01 .dw $ff01
-00f1ad 002b .db "+",0
-00f1ae f1a2 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00f1af f1b0 .dw PFA_PLUS
- PFA_PLUS:
-00f1b0 9109 ld temp0, Y+
-00f1b1 9119 ld temp1, Y+
-00f1b2 0f80 add tosl, temp0
-00f1b3 1f91 adc tosh, temp1
-00f1b4 ce50 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-00f1b5 ff02 .dw $ff02
-00f1b6 2a6d .db "m*"
-00f1b7 f1ac .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-00f1b8 f1b9 .dw PFA_MSTAR
- PFA_MSTAR:
-00f1b9 018c movw temp0, tosl
-00f1ba 9189
-00f1bb 9199 loadtos
-00f1bc 019c movw temp2, tosl
- ; high cell ah*bh
-00f1bd 0231 muls temp3, temp1
-00f1be 0170 movw temp4, r0
- ; low cell al*bl
-00f1bf 9f20 mul temp2, temp0
-00f1c0 01c0 movw tosl, r0
- ; signed ah*bl
-00f1c1 0330 mulsu temp3, temp0
-00f1c2 08f3 sbc temp5, zeroh
-00f1c3 0d90 add tosh, r0
-00f1c4 1ce1 adc temp4, r1
-00f1c5 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-00f1c6 0312 mulsu temp1, temp2
-00f1c7 08f3 sbc temp5, zeroh
-00f1c8 0d90 add tosh, r0
-00f1c9 1ce1 adc temp4, r1
-00f1ca 1cf3 adc temp5, zeroh
-
-00f1cb 939a
-00f1cc 938a savetos
-00f1cd 01c7 movw tosl, temp4
-00f1ce ce36 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-00f1cf ff06 .dw $ff06
-00f1d0 6d75
-00f1d1 6d2f
-00f1d2 646f .db "um/mod"
-00f1d3 f1b5 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-00f1d4 f1d5 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-00f1d5 017c movw temp4, tosl
-
-00f1d6 9129 ld temp2, Y+
-00f1d7 9139 ld temp3, Y+
-
-00f1d8 9109 ld temp0, Y+
-00f1d9 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-00f1da e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-00f1db 2755 clr temp7
-00f1dc 0f00 lsl temp0
-00f1dd 1f11 rol temp1
-00f1de 1f22 rol temp2
-00f1df 1f33 rol temp3
-00f1e0 1f55 rol temp7
-
- ; try subtracting divisor
-00f1e1 152e cp temp2, temp4
-00f1e2 053f cpc temp3, temp5
-00f1e3 0552 cpc temp7,zerol
-
-00f1e4 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-00f1e5 9503 inc temp0
-00f1e6 192e sub temp2, temp4
-00f1e7 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-00f1e8 954a dec temp6
-00f1e9 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-00f1ea 933a st -Y,temp3
-00f1eb 932a st -Y,temp2
-
- ; put quotient on stack
-00f1ec 01c8 movw tosl, temp0
-00f1ed ce17 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-00f1ee ff03 .dw $ff03
-00f1ef 6d75
-00f1f0 002a .db "um*",0
-00f1f1 f1cf .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-00f1f2 f1f3 .dw PFA_UMSTAR
- PFA_UMSTAR:
-00f1f3 018c movw temp0, tosl
-00f1f4 9189
-00f1f5 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-00f1f6 9f80 mul tosl,temp0
-00f1f7 01f0 movw zl, r0
-00f1f8 2722 clr temp2
-00f1f9 2733 clr temp3
- ; middle bytes
-00f1fa 9f90 mul tosh, temp0
-00f1fb 0df0 add zh, r0
-00f1fc 1d21 adc temp2, r1
-00f1fd 1d33 adc temp3, zeroh
-
-00f1fe 9f81 mul tosl, temp1
-00f1ff 0df0 add zh, r0
-00f200 1d21 adc temp2, r1
-00f201 1d33 adc temp3, zeroh
-
-00f202 9f91 mul tosh, temp1
-00f203 0d20 add temp2, r0
-00f204 1d31 adc temp3, r1
-00f205 01cf movw tosl, zl
-00f206 939a
-00f207 938a savetos
-00f208 01c9 movw tosl, temp2
-00f209 cdfb jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-00f20a ff06 .dw $ff06
-00f20b 6e69
-00f20c 6576
-00f20d 7472 .db "invert"
-00f20e f1ee .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-00f20f f210 .dw PFA_INVERT
- PFA_INVERT:
-00f210 9580 com tosl
-00f211 9590 com tosh
-00f212 cdf2 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-00f213 ff02 .dw $ff02
-00f214 2f32 .db "2/"
-00f215 f20a .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-00f216 f217 .dw PFA_2SLASH
- PFA_2SLASH:
-00f217 9595 asr tosh
-00f218 9587 ror tosl
-00f219 cdeb jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-00f21a ff02 .dw $ff02
-00f21b 2a32 .db "2*"
-00f21c f213 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-00f21d f21e .dw PFA_2STAR
- PFA_2STAR:
-00f21e 0f88 lsl tosl
-00f21f 1f99 rol tosh
-00f220 cde4 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-00f221 ff03 .dw $ff03
-00f222 6e61
-00f223 0064 .db "and",0
-00f224 f21a .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-00f225 f226 .dw PFA_AND
- PFA_AND:
-00f226 9109 ld temp0, Y+
-00f227 9119 ld temp1, Y+
-00f228 2380 and tosl, temp0
-00f229 2391 and tosh, temp1
-00f22a cdda jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-00f22b ff02 .dw $ff02
-00f22c 726f .db "or"
-00f22d f221 .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-00f22e f22f .dw PFA_OR
- PFA_OR:
-00f22f 9109 ld temp0, Y+
-00f230 9119 ld temp1, Y+
-00f231 2b80 or tosl, temp0
-00f232 2b91 or tosh, temp1
-00f233 cdd1 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-00f234 ff03 .dw $ff03
-00f235 6f78
-00f236 0072 .db "xor",0
-00f237 f22b .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-00f238 f239 .dw PFA_XOR
- PFA_XOR:
-00f239 9109 ld temp0, Y+
-00f23a 9119 ld temp1, Y+
-00f23b 2780 eor tosl, temp0
-00f23c 2791 eor tosh, temp1
-00f23d cdc7 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-00f23e ff02 .dw $ff02
-00f23f 2b31 .db "1+"
-00f240 f234 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-00f241 f242 .dw PFA_1PLUS
- PFA_1PLUS:
-00f242 9601 adiw tosl,1
-00f243 cdc1 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-00f244 ff02 .dw $ff02
-00f245 2d31 .db "1-"
-00f246 f23e .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-00f247 f248 .dw PFA_1MINUS
- PFA_1MINUS:
-00f248 9701 sbiw tosl, 1
-00f249 cdbb jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-00f24a ff07 .dw $ff07
-00f24b 6e3f
-00f24c 6765
-00f24d 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-00f24e 0065 .db "?negate"
-00f24f f244 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-00f250 f001 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-00f251 f133
-00f252 f03f .DW XT_ZEROLESS,XT_DOCONDBRANCH
-00f253 f255 DEST(QNEG1)
-00f254 f65a .DW XT_NEGATE
-00f255 f026 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-00f256 ff06 .dw $ff06
-00f257 736c
-00f258 6968
-00f259 7466 .db "lshift"
-00f25a f24a .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-00f25b f25c .dw PFA_LSHIFT
- PFA_LSHIFT:
-00f25c 01fc movw zl, tosl
-00f25d 9189
-00f25e 9199 loadtos
- PFA_LSHIFT1:
-00f25f 9731 sbiw zl, 1
-00f260 f01a brmi PFA_LSHIFT2
-00f261 0f88 lsl tosl
-00f262 1f99 rol tosh
-00f263 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-00f264 cda0 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-00f265 ff06 .dw $ff06
-00f266 7372
-00f267 6968
-00f268 7466 .db "rshift"
-00f269 f256 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-00f26a f26b .dw PFA_RSHIFT
- PFA_RSHIFT:
-00f26b 01fc movw zl, tosl
-00f26c 9189
-00f26d 9199 loadtos
- PFA_RSHIFT1:
-00f26e 9731 sbiw zl, 1
-00f26f f01a brmi PFA_RSHIFT2
-00f270 9596 lsr tosh
-00f271 9587 ror tosl
-00f272 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-00f273 cd91 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-00f274 ff02 .dw $ff02
-00f275 212b .db "+!"
-00f276 f265 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-00f277 f278 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-00f278 01fc movw zl, tosl
-00f279 9189
-00f27a 9199 loadtos
-00f27b 8120 ldd temp2, Z+0
-00f27c 8131 ldd temp3, Z+1
-00f27d 0f82 add tosl, temp2
-00f27e 1f93 adc tosh, temp3
-00f27f 8380 std Z+0, tosl
-00f280 8391 std Z+1, tosh
-00f281 9189
-00f282 9199 loadtos
-00f283 cd81 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-00f284 ff03 .dw $ff03
-00f285 7072
-00f286 0040 .db "rp@",0
-00f287 f274 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-00f288 f289 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-00f289 939a
-00f28a 938a savetos
-00f28b b78d in tosl, SPL
-00f28c b79e in tosh, SPH
-00f28d cd77 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-00f28e ff03 .dw $ff03
-00f28f 7072
-00f290 0021 .db "rp!",0
-00f291 f284 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-00f292 f293 .dw PFA_RP_STORE
- PFA_RP_STORE:
-00f293 b72f in temp2, SREG
-00f294 94f8 cli
-00f295 bf8d out SPL, tosl
-00f296 bf9e out SPH, tosh
-00f297 bf2f out SREG, temp2
-00f298 9189
-00f299 9199 loadtos
-00f29a cd6a jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-00f29b ff03 .dw $ff03
-00f29c 7073
-00f29d 0040 .db "sp@",0
-00f29e f28e .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-00f29f f2a0 .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-00f2a0 939a
-00f2a1 938a savetos
-00f2a2 01ce movw tosl, yl
-00f2a3 cd61 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-00f2a4 ff03 .dw $ff03
-00f2a5 7073
-00f2a6 0021 .db "sp!",0
-00f2a7 f29b .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-00f2a8 f2a9 .dw PFA_SP_STORE
- PFA_SP_STORE:
-00f2a9 01ec movw yl, tosl
-00f2aa 9189
-00f2ab 9199 loadtos
-00f2ac cd58 jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-00f2ad f2ae .dw PFA_DODO
- PFA_DODO:
-00f2ae 9129 ld temp2, Y+
-00f2af 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-00f2b0 e8e0 ldi zl, $80
-00f2b1 0f3e add temp3, zl
-00f2b2 1b82 sub tosl, temp2
-00f2b3 0b93 sbc tosh, temp3
-
-00f2b4 933f push temp3
-00f2b5 932f push temp2 ; limit ( --> limit + $8000)
-00f2b6 939f push tosh
-00f2b7 938f push tosl ; start -> index ( --> index - (limit - $8000)
-00f2b8 9189
-00f2b9 9199 loadtos
-00f2ba cd4a jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-00f2bb ff01 .dw $FF01
-00f2bc 0069 .db "i",0
-00f2bd f2a4 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-00f2be f2bf .dw PFA_I
- PFA_I:
-00f2bf 939a
-00f2c0 938a savetos
-00f2c1 918f pop tosl
-00f2c2 919f pop tosh ; index
-00f2c3 91ef pop zl
-00f2c4 91ff pop zh ; limit
-00f2c5 93ff push zh
-00f2c6 93ef push zl
-00f2c7 939f push tosh
-00f2c8 938f push tosl
-00f2c9 0f8e add tosl, zl
-00f2ca 1f9f adc tosh, zh
-00f2cb cd39 jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-00f2cc f2cd .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-00f2cd 91ef pop zl
-00f2ce 91ff pop zh
-00f2cf 0fe8 add zl, tosl
-00f2d0 1ff9 adc zh, tosh
-00f2d1 9189
-00f2d2 9199 loadtos
-00f2d3 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-00f2d4 93ff push zh
-00f2d5 93ef push zl
-00f2d6 cd5f rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-00f2d7 910f pop temp0
-00f2d8 911f pop temp1 ; remove limit
-00f2d9 9611 adiw xl, 1 ; skip branch-back address
-00f2da cd2a jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-00f2db f2dc .dw PFA_DOLOOP
- PFA_DOLOOP:
-00f2dc 91ef pop zl
-00f2dd 91ff pop zh
-00f2de 9631 adiw zl,1
-00f2df f3bb brvs PFA_DOPLUSLOOP_LEAVE
-00f2e0 cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-00f2e1 ff06 .dw $ff06
-00f2e2 6e75
-00f2e3 6f6c
-00f2e4 706f .db "unloop"
-00f2e5 f2bb .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-00f2e6 f2e7 .dw PFA_UNLOOP
- PFA_UNLOOP:
-00f2e7 911f pop temp1
-00f2e8 910f pop temp0
-00f2e9 911f pop temp1
-00f2ea 910f pop temp0
-00f2eb cd19 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-00f2ec ff06 .dw $ff06
-00f2ed 6d63
-00f2ee 766f
-00f2ef 3e65 .db "cmove>"
-00f2f0 f2e1 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-00f2f1 f2f2 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-00f2f2 93bf push xh
-00f2f3 93af push xl
-00f2f4 91e9 ld zl, Y+
-00f2f5 91f9 ld zh, Y+ ; addr-to
-00f2f6 91a9 ld xl, Y+
-00f2f7 91b9 ld xh, Y+ ; addr-from
-00f2f8 2f09 mov temp0, tosh
-00f2f9 2b08 or temp0, tosl
-00f2fa f041 brbs 1, PFA_CMOVE_G1
-00f2fb 0fe8 add zl, tosl
-00f2fc 1ff9 adc zh, tosh
-00f2fd 0fa8 add xl, tosl
-00f2fe 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-00f2ff 911e ld temp1, -X
-00f300 9312 st -Z, temp1
-00f301 9701 sbiw tosl, 1
-00f302 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-00f303 91af pop xl
-00f304 91bf pop xh
-00f305 9189
-00f306 9199 loadtos
-00f307 ccfd jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-00f308 ff02 .dw $ff02
-00f309 3c3e .db "><"
-00f30a f2ec .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-00f30b f30c .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-00f30c 2f09 mov temp0, tosh
-00f30d 2f98 mov tosh, tosl
-00f30e 2f80 mov tosl, temp0
-00f30f ccf5 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-00f310 ff03 .dw $ff03
-00f311 7075
-00f312 0040 .db "up@",0
-00f313 f308 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-00f314 f315 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-00f315 939a
-00f316 938a savetos
-00f317 01c2 movw tosl, upl
-00f318 ccec jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-00f319 ff03 .dw $ff03
-00f31a 7075
-00f31b 0021 .db "up!",0
-00f31c f310 .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-00f31d f31e .dw PFA_UP_STORE
- PFA_UP_STORE:
-00f31e 012c movw upl, tosl
-00f31f 9189
-00f320 9199 loadtos
-00f321 cce3 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-00f322 ff03 .dw $ff03
-00f323 6d31
-00f324 0073 .db "1ms",0
-00f325 f319 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-00f326 f327 .dw PFA_1MS
- PFA_1MS:
-00f327 eae0
-00f328 e0ff
-00f329 9731
-00f32a f7f1 delay 1000
-00f32b ccd9 jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-00f32c ff03 .dw $ff03
-00f32d 3e32
-00f32e 0072 .db "2>r",0
-00f32f f322 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-00f330 f331 .dw PFA_2TO_R
- PFA_2TO_R:
-00f331 01fc movw zl, tosl
-00f332 9189
-00f333 9199 loadtos
-00f334 939f push tosh
-00f335 938f push tosl
-00f336 93ff push zh
-00f337 93ef push zl
-00f338 9189
-00f339 9199 loadtos
-00f33a ccca jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-00f33b ff03 .dw $ff03
-00f33c 7232
-00f33d 003e .db "2r>",0
-00f33e f32c .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-00f33f f340 .dw PFA_2R_FROM
- PFA_2R_FROM:
-00f340 939a
-00f341 938a savetos
-00f342 91ef pop zl
-00f343 91ff pop zh
-00f344 918f pop tosl
-00f345 919f pop tosh
-00f346 939a
-00f347 938a savetos
-00f348 01cf movw tosl, zl
-00f349 ccbb jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-00f34a ff02 .dw $ff02
-00f34b 6521 .db "!e"
-00f34c f33b .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-00f34d f34e .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-00f34e 01fc movw zl, tosl
-00f34f 9189
-00f350 9199 loadtos
-00f351 b72f in_ temp2, SREG
-00f352 94f8 cli
-00f353 d028 rcall PFA_FETCHE2
-00f354 b500 in_ temp0, EEDR
-00f355 1708 cp temp0,tosl
-00f356 f009 breq PFA_STOREE3
-00f357 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-00f358 9631 adiw zl,1
-00f359 d022 rcall PFA_FETCHE2
-00f35a b500 in_ temp0, EEDR
-00f35b 1709 cp temp0,tosh
-00f35c f011 breq PFA_STOREE4
-00f35d 2f89 mov tosl, tosh
-00f35e d004 rcall PFA_STOREE1
- PFA_STOREE4:
-00f35f bf2f out_ SREG, temp2
-00f360 9189
-00f361 9199 loadtos
-00f362 cca2 jmp_ DO_NEXT
-
- PFA_STOREE1:
-00f363 99f9 sbic EECR, EEPE
-00f364 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-00f365 b707 in_ temp0, SPMCSR
-00f366 fd00 sbrc temp0,SPMEN
-00f367 cffd rjmp PFA_STOREE2
-
-00f368 bdf2 out_ EEARH,zh
-00f369 bde1 out_ EEARL,zl
-00f36a bd80 out_ EEDR, tosl
-00f36b 9afa sbi EECR,EEMPE
-00f36c 9af9 sbi EECR,EEPE
-
-00f36d 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-00f36e ff02 .dw $ff02
-00f36f 6540 .db "@e"
-00f370 f34a .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-00f371 f372 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-00f372 b72f in_ temp2, SREG
-00f373 94f8 cli
-00f374 01fc movw zl, tosl
-00f375 d006 rcall PFA_FETCHE2
-00f376 b580 in_ tosl, EEDR
-
-00f377 9631 adiw zl,1
-
-00f378 d003 rcall PFA_FETCHE2
-00f379 b590 in_ tosh, EEDR
-00f37a bf2f out_ SREG, temp2
-00f37b cc89 jmp_ DO_NEXT
-
- PFA_FETCHE2:
-00f37c 99f9 sbic EECR, EEPE
-00f37d cffe rjmp PFA_FETCHE2
-
-00f37e bdf2 out_ EEARH,zh
-00f37f bde1 out_ EEARL,zl
-
-00f380 9af8 sbi EECR,EERE
-00f381 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-00f382 ff02 .dw $ff02
-00f383 6921 .db "!i"
-00f384 f36e .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-00f385 fc2e .dw PFA_DODEFER1
- PFA_STOREI:
-00f386 0078 .dw EE_STOREI
-00f387 fbcf .dw XT_EDEFERFETCH
-00f388 fbd9 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-00f389 ff09 .dw $ff09
-00f38a 2128
-00f38b 2d69
-00f38c 726e
-00f38d 7777
-00f38e 0029 .db "(!i-nrww)",0
-00f38f f382 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-00f390 f391 .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-00f391 b71f in temp1,SREG
-00f392 931f push temp1
-00f393 94f8 cli
-
-00f394 019c movw temp2, tosl ; save the (word) address
-00f395 9189
-00f396 9199 loadtos ; get the new value for the flash cell
-00f397 93af push xl
-00f398 93bf push xh
-00f399 93cf push yl
-00f39a 93df push yh
-00f39b d009 rcall DO_STOREI_atmega
-00f39c 91df pop yh
-00f39d 91cf pop yl
-00f39e 91bf pop xh
-00f39f 91af pop xl
- ; finally clear the stack
-00f3a0 9189
-00f3a1 9199 loadtos
-00f3a2 911f pop temp1
- ; restore status register (and interrupt enable flag)
-00f3a3 bf1f out SREG,temp1
-
-00f3a4 cc60 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-00f3a5 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-00f3a6 94e0 com temp4
-00f3a7 94f0 com temp5
-00f3a8 218e and tosl, temp4
-00f3a9 219f and tosh, temp5
-00f3aa 2b98 or tosh, tosl
-00f3ab f019 breq DO_STOREI_writepage
-00f3ac 01f9 movw zl, temp2
-00f3ad e002 ldi temp0,(1<<PGERS)
-00f3ae d023 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-00f3af 01f9 movw zl, temp2
-00f3b0 e004 ldi temp0,(1<<PGWRT)
-00f3b1 d020 rcall dospm
-
- ; reenable RWW section
-00f3b2 01f9 movw zl, temp2
-00f3b3 e100 ldi temp0,(1<<RWWSRE)
-00f3b4 d01d rcall dospm
-00f3b5 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-00f3b6 01f9 movw zl, temp2
- ; get the beginning of page
-00f3b7 78e0 andi zl,low(pagemask)
-00f3b8 7fff andi zh,high(pagemask)
-00f3b9 01ef movw y, z
- ; loop counter (in words)
-00f3ba e8a0 ldi xl,low(pagesize)
-00f3bb e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-00f3bc 01fe movw z, y
-00f3bd 2755
-00f3be 0fee
-00f3bf 1fff
-00f3c0 1f55
-00f3c1 bf5b
-00f3c2 9147
-00f3c3 9157 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-00f3c4 01fe movw z, y
-00f3c5 17e2 cp zl, temp2
-00f3c6 07f3 cpc zh, temp3
-00f3c7 f011 breq pageload_newdata
-00f3c8 010a movw r0, temp6
-00f3c9 c002 rjmp pageload_cont
- pageload_newdata:
-00f3ca 017a movw temp4, temp6
-00f3cb 010c movw r0, tosl
- pageload_cont:
-00f3cc 2700 clr temp0
-00f3cd d004 rcall dospm
-00f3ce 9621 adiw y, 1
-00f3cf 9711 sbiw x, 1
-00f3d0 f759 brne pageload_loop
-
- pageload_done:
-00f3d1 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-00f3d2 99f9 sbic EECR, EEPE
-00f3d3 cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-00f3d4 b717 in_ temp1, SPMCSR
-00f3d5 fd10 sbrc temp1, SPMEN
-00f3d6 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-00f3d7 2755
-00f3d8 0fee
-00f3d9 1fff
-00f3da 1f55
-00f3db bf5b writeflashcell
- ; execute spm
-00f3dc 6001 ori temp0, (1<<SPMEN)
-00f3dd bf07 out_ SPMCSR,temp0
-00f3de 95e8 spm
-00f3df 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-00f3e0 ff02 .dw $ff02
-00f3e1 6940 .db "@i"
-00f3e2 f389 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-00f3e3 f3e4 .dw PFA_FETCHI
- PFA_FETCHI:
-00f3e4 01fc movw zl, tosl
-00f3e5 2755
-00f3e6 0fee
-00f3e7 1fff
-00f3e8 1f55
-00f3e9 bf5b
-00f3ea 9187
-00f3eb 9197 readflashcell tosl,tosh
-00f3ec cc18 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .include "dict/core_8k.inc"
-
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-00f3ed ff03 .dw $ff03
-00f3ee 3e6e
-00f3ef 0072 .db "n>r",0
-00f3f0 f3e0 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-00f3f1 f3f2 .dw PFA_N_TO_R
- PFA_N_TO_R:
-00f3f2 01fc movw zl, tosl
-00f3f3 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-00f3f4 9189
-00f3f5 9199 loadtos
-00f3f6 939f push tosh
-00f3f7 938f push tosl
-00f3f8 950a dec temp0
-00f3f9 f7d1 brne PFA_N_TO_R1
-00f3fa 93ef push zl
-00f3fb 93ff push zh
-00f3fc 9189
-00f3fd 9199 loadtos
-00f3fe cc06 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-00f3ff ff03 .dw $ff03
-00f400 726e
-00f401 003e .db "nr>",0
-00f402 f3ed .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-00f403 f404 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-00f404 939a
-00f405 938a savetos
-00f406 91ff pop zh
-00f407 91ef pop zl
-00f408 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-00f409 918f pop tosl
-00f40a 919f pop tosh
-00f40b 939a
-00f40c 938a savetos
-00f40d 950a dec temp0
-00f40e f7d1 brne PFA_N_R_FROM1
-00f40f 01cf movw tosl, zl
-00f410 cbf4 jmp_ DO_NEXT
-
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-00f411 ff03 .dw $ff03
-00f412 3264
-00f413 002a .db "d2*",0
-00f414 f3ff .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-00f415 f416 .dw PFA_D2STAR
- PFA_D2STAR:
-00f416 9109 ld temp0, Y+
-00f417 9119 ld temp1, Y+
-00f418 0f00 lsl temp0
-00f419 1f11 rol temp1
-00f41a 1f88 rol tosl
-00f41b 1f99 rol tosh
-00f41c 931a st -Y, temp1
-00f41d 930a st -Y, temp0
-00f41e cbe6 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-00f41f ff03 .dw $ff03
-00f420 3264
-00f421 002f .db "d2/",0
-00f422 f411 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-00f423 f424 .dw PFA_D2SLASH
- PFA_D2SLASH:
-00f424 9109 ld temp0, Y+
-00f425 9119 ld temp1, Y+
-00f426 9595 asr tosh
-00f427 9587 ror tosl
-00f428 9517 ror temp1
-00f429 9507 ror temp0
-00f42a 931a st -Y, temp1
-00f42b 930a st -Y, temp0
-00f42c cbd8 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-00f42d ff02 .dw $ff02
-00f42e 2b64 .db "d+"
-00f42f f41f .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-00f430 f431 .dw PFA_DPLUS
- PFA_DPLUS:
-00f431 9129 ld temp2, Y+
-00f432 9139 ld temp3, Y+
-
-00f433 90e9 ld temp4, Y+
-00f434 90f9 ld temp5, Y+
-00f435 9149 ld temp6, Y+
-00f436 9159 ld temp7, Y+
-
-00f437 0f24 add temp2, temp6
-00f438 1f35 adc temp3, temp7
-00f439 1d8e adc tosl, temp4
-00f43a 1d9f adc tosh, temp5
-
-00f43b 933a st -Y, temp3
-00f43c 932a st -Y, temp2
-00f43d cbc7 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-00f43e ff02 .dw $ff02
-00f43f 2d64 .db "d-"
-00f440 f42d .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-00f441 f442 .dw PFA_DMINUS
- PFA_DMINUS:
-00f442 9129 ld temp2, Y+
-00f443 9139 ld temp3, Y+
-
-00f444 90e9 ld temp4, Y+
-00f445 90f9 ld temp5, Y+
-00f446 9149 ld temp6, Y+
-00f447 9159 ld temp7, Y+
-
-00f448 1b42 sub temp6, temp2
-00f449 0b53 sbc temp7, temp3
-00f44a 0ae8 sbc temp4, tosl
-00f44b 0af9 sbc temp5, tosh
-
-00f44c 935a st -Y, temp7
-00f44d 934a st -Y, temp6
-00f44e 01c7 movw tosl, temp4
-00f44f cbb5 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-00f450 ff07 .dw $ff07
-00f451 6964
-00f452 766e
-00f453 7265
-00f454 0074 .db "dinvert",0
-00f455 f43e .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-00f456 f457 .dw PFA_DINVERT
- PFA_DINVERT:
-00f457 9109 ld temp0, Y+
-00f458 9119 ld temp1, Y+
-00f459 9580 com tosl
-00f45a 9590 com tosh
-00f45b 9500 com temp0
-00f45c 9510 com temp1
-00f45d 931a st -Y, temp1
-00f45e 930a st -Y, temp0
-00f45f cba5 jmp_ DO_NEXT
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-00f460 ff02 .dw $ff02
-00f461 2e75 .db "u."
-00f462 f450 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-00f463 f001 .dw DO_COLON
- PFA_UDOT:
- .endif
-00f464 f166 .dw XT_ZERO
-00f465 f745 .dw XT_UDDOT
-00f466 f026 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-00f467 ff03 .dw $ff03
-00f468 2e75
-00f469 0072 .db "u.r",0
-00f46a f460 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-00f46b f001 .dw DO_COLON
- PFA_UDOTR:
- .endif
-00f46c f166 .dw XT_ZERO
-00f46d f0d6 .dw XT_SWAP
-00f46e f74e .dw XT_UDDOTR
-00f46f f026 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-00f470 ff0d .dw $ff0d
-00f471 6873
-00f472 776f
-00f473 772d
-00f474 726f
-00f475 6c64
-00f476 7369
-00f477 0074 .db "show-wordlist",0
-00f478 f467 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-00f479 f001 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-00f47a f046 .dw XT_DOLITERAL
-00f47b f47f .dw XT_SHOWWORD
-00f47c f0d6 .dw XT_SWAP
-00f47d fc72 .dw XT_TRAVERSEWORDLIST
-00f47e f026 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-00f47f f001 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-00f480 fc8d .dw XT_NAME2STRING
-00f481 f7bb .dw XT_ITYPE
-00f482 f7fd .dw XT_SPACE ; ( -- addr n)
-00f483 f15d .dw XT_TRUE
-00f484 f026 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-00f485 ff05 .dw $ff05
-00f486 6f77
-00f487 6472
-00f488 0073 .db "words",0
-00f489 f470 .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-00f48a f001 .dw DO_COLON
- PFA_WORDS:
- .endif
-00f48b f046 .dw XT_DOLITERAL
-00f48c 005e .dw CFG_ORDERLISTLEN+2
-00f48d f371 .dw XT_FETCHE
-00f48e f479 .dw XT_SHOWWORDLIST
-00f48f f026 .dw XT_EXIT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-00f490 ff04 .dw $ff04
-00f491 692b
-00f492 746e .db "+int"
-00f493 f485 .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-00f494 f495 .dw PFA_INTON
- PFA_INTON:
-00f495 9478 sei
-00f496 cb6e jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-00f497 ff04 .dw $ff04
-00f498 692d
-00f499 746e .db "-int"
-00f49a f490 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-00f49b f49c .dw PFA_INTOFF
- PFA_INTOFF:
-00f49c 94f8 cli
-00f49d cb67 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-00f49e ff04 .dw $ff04
-00f49f 6e69
-00f4a0 2174 .db "int!"
-00f4a1 f497 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-00f4a2 f001 .dw DO_COLON
- PFA_INTSTORE:
-00f4a3 f046 .dw XT_DOLITERAL
-00f4a4 0000 .dw intvec
-00f4a5 f1af .dw XT_PLUS
-00f4a6 f34d .dw XT_STOREE
-00f4a7 f026 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-00f4a8 ff04 .dw $ff04
-00f4a9 6e69
-00f4aa 4074 .db "int@"
-00f4ab f49e .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-00f4ac f001 .dw DO_COLON
- PFA_INTFETCH:
-00f4ad f046 .dw XT_DOLITERAL
-00f4ae 0000 .dw intvec
-00f4af f1af .dw XT_PLUS
-00f4b0 f371 .dw XT_FETCHE
-00f4b1 f026 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-00f4b2 ff08 .dw $ff08
-00f4b3 6e69
-00f4b4 2d74
-00f4b5 7274
-00f4b6 7061 .db "int-trap"
-00f4b7 f4a8 .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-00f4b8 f4b9 .dw PFA_INTTRAP
- PFA_INTTRAP:
-00f4b9 2eb8 mov isrflag, tosl
-00f4ba 9189
-00f4bb 9199 loadtos
-00f4bc cb48 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-00f4bd f001 .dw DO_COLON
- PFA_ISREXEC:
-00f4be f4ac .dw XT_INTFETCH
-00f4bf f030 .dw XT_EXECUTE
-00f4c0 f4c2 .dw XT_ISREND
-00f4c1 f026 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-00f4c2 f4c3 .dw PFA_ISREND
- PFA_ISREND:
-00f4c3 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-00f4c4 cb40 jmp_ DO_NEXT
- PFA_ISREND1:
-00f4c5 9518 reti
- .endif
-
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-00f4c6 ff04 .dw $ff04
-00f4c7 6970
-00f4c8 6b63 .db "pick"
-00f4c9 f4b2 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-00f4ca f001 .dw DO_COLON
- PFA_PICK:
- .endif
-00f4cb f241 .dw XT_1PLUS
-00f4cc f573 .dw XT_CELLS
-00f4cd f29f .dw XT_SP_FETCH
-00f4ce f1af .dw XT_PLUS
-00f4cf f08b .dw XT_FETCH
-00f4d0 f026 .dw XT_EXIT
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-00f4d1 0002 .dw $0002
-00f4d2 222e .db ".",$22
-00f4d3 f4c6 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-00f4d4 f001 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-00f4d5 f4dc .dw XT_SQUOTE
-00f4d6 01d0 .dw XT_COMPILE
-00f4d7 f7bb .dw XT_ITYPE
-00f4d8 f026 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-00f4d9 0002 .dw $0002
-00f4da 2273 .db "s",$22
-00f4db f4d1 .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-00f4dc f001 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-00f4dd f046 .dw XT_DOLITERAL
-00f4de 0022 .dw 34 ; 0x22
-00f4df f9a2 .dw XT_PARSE ; ( -- addr n)
-00f4e0 f566 .dw XT_STATE
-00f4e1 f08b .dw XT_FETCH
-00f4e2 f03f .dw XT_DOCONDBRANCH
-00f4e3 f4e5 DEST(PFA_SQUOTE1)
-00f4e4 01fc .dw XT_SLITERAL
- PFA_SQUOTE1:
-00f4e5 f026 .dw XT_EXIT
-
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-00f4e6 ff04 .dw $ff04
-00f4e7 6966
-00f4e8 6c6c .db "fill"
-00f4e9 f4d9 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-00f4ea f001 .dw DO_COLON
- PFA_FILL:
-00f4eb f0f3 .dw XT_ROT
-00f4ec f0f3 .dw XT_ROT
-00f4ed f0cb
-00f4ee f03f .dw XT_QDUP,XT_DOCONDBRANCH
-00f4ef f4f7 DEST(PFA_FILL2)
-00f4f0 fd79 .dw XT_BOUNDS
-00f4f1 f2ad .dw XT_DODO
- PFA_FILL1:
-00f4f2 f0c3 .dw XT_DUP
-00f4f3 f2be .dw XT_I
-00f4f4 f09f .dw XT_CSTORE ; ( -- c c-addr)
-00f4f5 f2db .dw XT_DOLOOP
-00f4f6 f4f2 .dw PFA_FILL1
- PFA_FILL2:
-00f4f7 f0eb .dw XT_DROP
-00f4f8 f026 .dw XT_EXIT
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-00f4f9 ff0b .dw $ff0b
-00f4fa 6e65
-00f4fb 6976
-00f4fc 6f72
-00f4fd 6d6e
-00f4fe 6e65
-00f4ff 0074 .db "environment",0
-00f500 f4e6 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-00f501 f054 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-00f502 0056 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00f503 ff09 .dw $ff09
-00f504 6f77
-00f505 6472
-00f506 696c
-00f507 7473
-00f508 0073 .db "wordlists",0
-00f509 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-00f50a f001 .dw DO_COLON
- PFA_ENVWORDLISTS:
-00f50b f046 .dw XT_DOLITERAL
-00f50c 0008 .dw NUMWORDLISTS
-00f50d f026 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-00f50e ff04 .dw $ff04
-00f50f 702f
-00f510 6461 .db "/pad"
-00f511 f503 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-00f512 f001 .dw DO_COLON
- PFA_ENVSLASHPAD:
-00f513 f29f .dw XT_SP_FETCH
-00f514 f59f .dw XT_PAD
-00f515 f1a5 .dw XT_MINUS
-00f516 f026 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-00f517 ff05 .dw $ff05
-00f518 682f
-00f519 6c6f
-00f51a 0064 .db "/hold",0
-00f51b f50e .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-00f51c f001 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-00f51d f59f .dw XT_PAD
-00f51e f5da .dw XT_HERE
-00f51f f1a5 .dw XT_MINUS
-00f520 f026 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-00f521 ff0a .dw $ff0a
-00f522 6f66
-00f523 7472
-00f524 2d68
-00f525 616e
-00f526 656d .db "forth-name"
-00f527 f517 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-00f528 f001 .dw DO_COLON
- PFA_EN_FORTHNAME:
-00f529 f788 .dw XT_DOSLITERAL
-00f52a 0007 .dw 7
- .endif
-00f52b 6d61
-00f52c 6f66
-00f52d 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-00f52e 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-00f52f f026 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-00f530 ff07 .dw $ff07
-00f531 6576
-00f532 7372
-00f533 6f69
-00f534 006e .db "version",0
-00f535 f521 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-00f536 f001 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-00f537 f046 .dw XT_DOLITERAL
-00f538 0041 .dw 65
-00f539 f026 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-00f53a ff03 .dw $ff03
-00f53b 7063
-00f53c 0075 .db "cpu",0
-00f53d f530 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-00f53e f001 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-00f53f f046 .dw XT_DOLITERAL
-00f540 0049 .dw mcu_name
-00f541 f7e7 .dw XT_ICOUNT
-00f542 f026 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-00f543 ff08 .dw $ff08
-00f544 636d
-00f545 2d75
-00f546 6e69
-00f547 6f66 .db "mcu-info"
-00f548 f53a .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-00f549 f001 .dw DO_COLON
- PFA_EN_MCUINFO:
-00f54a f046 .dw XT_DOLITERAL
-00f54b 0045 .dw mcu_info
-00f54c f026 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-00f54d ff05 .dw $ff05
-00f54e 752f
-00f54f 6573
-00f550 0072 .db "/user",0
-00f551 f543 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-00f552 f001 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-00f553 f046 .dw XT_DOLITERAL
-00f554 002c .dw SYSUSERSIZE + APPUSERSIZE
-00f555 f026 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-00f556 ff05 .dw $ff05
-00f557 5f66
-00f558 7063
-00f559 0075 .db "f_cpu",0
-00f55a f4f9 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-00f55b f001 .dw DO_COLON
- PFA_F_CPU:
- .endif
-00f55c f046 .dw XT_DOLITERAL
-00f55d 2400 .dw (F_CPU % 65536)
-00f55e f046 .dw XT_DOLITERAL
-00f55f 00f4 .dw (F_CPU / 65536)
-00f560 f026 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-00f561 ff05 .dw $ff05
-00f562 7473
-00f563 7461
-00f564 0065 .db "state",0
-00f565 f556 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-00f566 f054 .dw PFA_DOVARIABLE
- PFA_STATE:
-00f567 013d .dw ram_state
-
- .dseg
-00013d ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-00f568 ff04 .dw $ff04
-00f569 6162
-00f56a 6573 .db "base"
-00f56b f561 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-00f56c f067 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-00f56d 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-00f56e ff05 .dw $ff05
-00f56f 6563
-00f570 6c6c
-00f571 0073 .db "cells",0
-00f572 f568 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-00f573 f21e .dw PFA_2STAR
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-00f574 ff05 .dw $ff05
-00f575 6563
-00f576 6c6c
-00f577 002b .db "cell+",0
-00f578 f56e .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-00f579 f57a .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-00f57a 9602 adiw tosl, CELLSIZE
-00f57b ca89 jmp_ DO_NEXT
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-00f57c ff04 .dw $ff04
-00f57d 6432
-00f57e 7075 .db "2dup"
-00f57f f574 .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-00f580 f001 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-00f581 f0e1 .dw XT_OVER
-00f582 f0e1 .dw XT_OVER
-00f583 f026 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-00f584 ff05 .dw $ff05
-00f585 6432
-00f586 6f72
-00f587 0070 .db "2drop",0
-00f588 f57c .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-00f589 f001 .dw DO_COLON
- PFA_2DROP:
- .endif
-00f58a f0eb .dw XT_DROP
-00f58b f0eb .dw XT_DROP
-00f58c f026 .dw XT_EXIT
-
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-00f58d ff04 .dw $ff04
-00f58e 7574
-00f58f 6b63 .db "tuck"
-00f590 f584 .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-00f591 f001 .dw DO_COLON
- PFA_TUCK:
- .endif
-00f592 f0d6 .dw XT_SWAP
-00f593 f0e1 .dw XT_OVER
-00f594 f026 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-00f595 ff03 .dw $ff03
-00f596 693e
-00f597 006e .db ">in",0
-00f598 f58d .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-00f599 f067 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-00f59a 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-00f59b ff03 .dw $ff03
-00f59c 6170
-00f59d 0064 .db "pad",0
-00f59e f595 .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-00f59f f001 .dw DO_COLON
- PFA_PAD:
- .endif
-00f5a0 f5da .dw XT_HERE
-00f5a1 f046 .dw XT_DOLITERAL
-00f5a2 0028 .dw 40
-00f5a3 f1af .dw XT_PLUS
-00f5a4 f026 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-00f5a5 ff04 .dw $ff04
-00f5a6 6d65
-00f5a7 7469 .db "emit"
-00f5a8 f59b .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-00f5a9 fc2e .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-00f5aa 000e .dw USER_EMIT
-00f5ab fbf7 .dw XT_UDEFERFETCH
-00f5ac fc03 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-00f5ad ff05 .dw $ff05
-00f5ae 6d65
-00f5af 7469
-00f5b0 003f .db "emit?",0
-00f5b1 f5a5 .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-00f5b2 fc2e .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-00f5b3 0010 .dw USER_EMITQ
-00f5b4 fbf7 .dw XT_UDEFERFETCH
-00f5b5 fc03 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-00f5b6 ff03 .dw $ff03
-00f5b7 656b
-00f5b8 0079 .db "key",0
-00f5b9 f5ad .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-00f5ba fc2e .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-00f5bb 0012 .dw USER_KEY
-00f5bc fbf7 .dw XT_UDEFERFETCH
-00f5bd fc03 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-00f5be ff04 .dw $ff04
-00f5bf 656b
-00f5c0 3f79 .db "key?"
-00f5c1 f5b6 .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-00f5c2 fc2e .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-00f5c3 0014 .dw USER_KEYQ
-00f5c4 fbf7 .dw XT_UDEFERFETCH
-00f5c5 fc03 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-00f5c6 ff02 .dw $ff02
-00f5c7 7064 .db "dp"
-00f5c8 f5be .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-00f5c9 f081 .dw PFA_DOVALUE1
- PFA_DP:
-00f5ca 0048 .dw CFG_DP
-00f5cb fbcf .dw XT_EDEFERFETCH
-00f5cc fbd9 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-00f5cd ff05 .dw $ff05
-00f5ce 6865
-00f5cf 7265
-00f5d0 0065 .db "ehere",0
-00f5d1 f5c6 .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-00f5d2 f081 .dw PFA_DOVALUE1
- PFA_EHERE:
-00f5d3 004c .dw EE_EHERE
-00f5d4 fbcf .dw XT_EDEFERFETCH
-00f5d5 fbd9 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-00f5d6 ff04 .dw $ff04
-00f5d7 6568
-00f5d8 6572 .db "here"
-00f5d9 f5cd .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-00f5da f081 .dw PFA_DOVALUE1
- PFA_HERE:
-00f5db 004a .dw EE_HERE
-00f5dc fbcf .dw XT_EDEFERFETCH
-00f5dd fbd9 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-00f5de ff05 .dw $ff05
-00f5df 6c61
-00f5e0 6f6c
-00f5e1 0074 .db "allot",0
-00f5e2 f5d6 .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-00f5e3 f001 .dw DO_COLON
- PFA_ALLOT:
-00f5e4 f5da .dw XT_HERE
-00f5e5 f1af .dw XT_PLUS
-00f5e6 fbb4 .dw XT_DOTO
-00f5e7 f5db .dw PFA_HERE
-00f5e8 f026 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-00f5e9 ff03 .dw $ff03
-00f5ea 6962
-00f5eb 006e .db "bin",0
-00f5ec f5de .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-00f5ed f001 .dw DO_COLON
- PFA_BIN:
- .endif
-00f5ee fda6 .dw XT_TWO
-00f5ef f56c .dw XT_BASE
-00f5f0 f093 .dw XT_STORE
-00f5f1 f026 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-00f5f2 ff07 .dw $ff07
-00f5f3 6564
-00f5f4 6963
-00f5f5 616d
-00f5f6 006c .db "decimal",0
-00f5f7 f5e9 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-00f5f8 f001 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-00f5f9 f046 .dw XT_DOLITERAL
-00f5fa 000a .dw 10
-00f5fb f56c .dw XT_BASE
-00f5fc f093 .dw XT_STORE
-00f5fd f026 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-00f5fe ff03 .dw $ff03
-00f5ff 6568
-00f600 0078 .db "hex",0
-00f601 f5f2 .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-00f602 f001 .dw DO_COLON
- PFA_HEX:
- .endif
-00f603 f046 .dw XT_DOLITERAL
-00f604 0010 .dw 16
-00f605 f56c .dw XT_BASE
-00f606 f093 .dw XT_STORE
-00f607 f026 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-00f608 ff02 .dw $ff02
-00f609 6c62 .db "bl"
-00f60a f5fe .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-00f60b f054 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-00f60c 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-00f60d ff07 .dw $ff07
-00f60e 7574
-00f60f 6e72
-00f610 656b
-00f611 0079 .db "turnkey",0
-00f612 f608 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-00f613 fc2e .dw PFA_DODEFER1
- PFA_TURNKEY:
-00f614 0054 .dw CFG_TURNKEY
-00f615 fbcf .dw XT_EDEFERFETCH
-00f616 fbd9 .dw XT_EDEFERSTORE
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-00f617 ff04 .dw $ff04
-00f618 6d2f
-00f619 646f .db "/mod"
-00f61a f60d .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-00f61b f61c .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-00f61c 019c movw temp2, tosl
-
-00f61d 9109 ld temp0, Y+
-00f61e 9119 ld temp1, Y+
-
-00f61f 2f41 mov temp6,temp1 ;move dividend High to sign register
-00f620 2743 eor temp6,temp3 ;xor divisor High with sign register
-00f621 ff17 sbrs temp1,7 ;if MSB in dividend set
-00f622 c004 rjmp PFA_SLASHMOD_1
-00f623 9510 com temp1 ; change sign of dividend
-00f624 9500 com temp0
-00f625 5f0f subi temp0,low(-1)
-00f626 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-00f627 ff37 sbrs temp3,7 ;if MSB in divisor set
-00f628 c004 rjmp PFA_SLASHMOD_2
-00f629 9530 com temp3 ; change sign of divisor
-00f62a 9520 com temp2
-00f62b 5f2f subi temp2,low(-1)
-00f62c 4f3f sbci temp3,high(-1)
-00f62d 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-00f62e 18ff sub temp5,temp5;clear remainder High byte and carry
-00f62f e151 ldi temp7,17 ;init loop counter
-
-00f630 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-00f631 1f11 rol temp1
-00f632 955a dec temp7 ;decrement counter
-00f633 f439 brne PFA_SLASHMOD_5 ;if done
-00f634 ff47 sbrs temp6,7 ; if MSB in sign register set
-00f635 c004 rjmp PFA_SLASHMOD_4
-00f636 9510 com temp1 ; change sign of result
-00f637 9500 com temp0
-00f638 5f0f subi temp0,low(-1)
-00f639 4f1f sbci temp1,high(-1)
-00f63a c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-00f63b 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-00f63c 1cff rol temp5
-00f63d 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-00f63e 0af3 sbc temp5,temp3 ;
-00f63f f420 brcc PFA_SLASHMOD_6 ;if result negative
-00f640 0ee2 add temp4,temp2 ; restore remainder
-00f641 1ef3 adc temp5,temp3
-00f642 9488 clc ; clear carry to be shifted into result
-00f643 cfec rjmp PFA_SLASHMOD_3 ;else
-00f644 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-00f645 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-00f646 92fa st -Y,temp5
-00f647 92ea st -Y,temp4
-
- ; put quotient on stack
-00f648 01c8 movw tosl, temp0
-00f649 c9bb jmp_ DO_NEXT
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-00f64a ff05 .dw $ff05
-00f64b 2f75
-00f64c 6f6d
-00f64d 0064 .db "u/mod",0
-00f64e f617 .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-00f64f f001 .dw DO_COLON
- PFA_USLASHMOD:
-00f650 f111 .dw XT_TO_R
-00f651 f166 .dw XT_ZERO
-00f652 f108 .dw XT_R_FROM
-00f653 f1d4 .dw XT_UMSLASHMOD
-00f654 f026 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-00f655 ff06 .dw $ff06
-00f656 656e
-00f657 6167
-00f658 6574 .db "negate"
-00f659 f64a .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-00f65a f001 .dw DO_COLON
- PFA_NEGATE:
-00f65b f20f .dw XT_INVERT
-00f65c f241 .dw XT_1PLUS
-00f65d f026 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-00f65e ff01 .dw $ff01
-00f65f 002f .db "/",0
-00f660 f655 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-00f661 f001 .dw DO_COLON
- PFA_SLASH:
- .endif
-00f662 f61b .dw XT_SLASHMOD
-00f663 f102 .dw XT_NIP
-00f664 f026 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-00f665 ff03 .dw $ff03
-00f666 6f6d
-00f667 0064 .db "mod",0
-00f668 f65e .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-00f669 f001 .dw DO_COLON
- PFA_MOD:
- .endif
-00f66a f61b .dw XT_SLASHMOD
-00f66b f0eb .dw XT_DROP
-00f66c f026 .dw XT_EXIT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-00f66d ff03 .dw $ff03
-00f66e 6261
-00f66f 0073 .db "abs",0
-00f670 f665 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-00f671 f001 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-00f672 f0c3
-00f673 f250
-00f674 f026 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-00f675 ff03 .dw $ff03
-00f676 696d
-00f677 006e .db "min",0
-00f678 f66d .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-00f679 f001 .dw DO_COLON
- PFA_MIN:
- .endif
-00f67a f580 .dw XT_2DUP
-00f67b f18a .dw XT_GREATER
-00f67c f03f .dw XT_DOCONDBRANCH
-00f67d f67f DEST(PFA_MIN1)
-00f67e f0d6 .dw XT_SWAP
- PFA_MIN1:
-00f67f f0eb .dw XT_DROP
-00f680 f026 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-00f681 ff03 .dw $ff03
-00f682 616d
-00f683 0078 .db "max",0
-00f684 f675 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-00f685 f001 .dw DO_COLON
- PFA_MAX:
-
- .endif
-00f686 f580 .dw XT_2DUP
-00f687 f180 .dw XT_LESS
-00f688 f03f .dw XT_DOCONDBRANCH
-00f689 f68b DEST(PFA_MAX1)
-00f68a f0d6 .dw XT_SWAP
- PFA_MAX1:
-00f68b f0eb .dw XT_DROP
-00f68c f026 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-00f68d ff06 .dw $ff06
-00f68e 6977
-00f68f 6874
-00f690 6e69 .db "within"
-00f691 f681 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-00f692 f001 .dw DO_COLON
- PFA_WITHIN:
- .endif
-00f693 f0e1 .dw XT_OVER
-00f694 f1a5 .dw XT_MINUS
-00f695 f111 .dw XT_TO_R
-00f696 f1a5 .dw XT_MINUS
-00f697 f108 .dw XT_R_FROM
-00f698 f16e .dw XT_ULESS
-00f699 f026 .dw XT_EXIT
-
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-00f69a ff07 .dw $ff07
-00f69b 6f74
-00f69c 7075
-00f69d 6570
-00f69e 0072 .db "toupper",0
-00f69f f68d .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-00f6a0 f001 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-00f6a1 f0c3 .dw XT_DUP
-00f6a2 f046 .dw XT_DOLITERAL
-00f6a3 0061 .dw 'a'
-00f6a4 f046 .dw XT_DOLITERAL
-00f6a5 007b .dw 'z'+1
-00f6a6 f692 .dw XT_WITHIN
-00f6a7 f03f .dw XT_DOCONDBRANCH
-00f6a8 f6ac DEST(PFA_TOUPPER0)
-00f6a9 f046 .dw XT_DOLITERAL
-00f6aa 00df .dw 223 ; inverse of 0x20: 0xdf
-00f6ab f225 .dw XT_AND
- PFA_TOUPPER0:
-00f6ac f026 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-00f6ad ff07 .dw $ff07
-00f6ae 6f74
-00f6af 6f6c
-00f6b0 6577
-00f6b1 0072 .db "tolower",0
-00f6b2 f69a .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-00f6b3 f001 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-00f6b4 f0c3 .dw XT_DUP
-00f6b5 f046 .dw XT_DOLITERAL
-00f6b6 0041 .dw 'A'
-00f6b7 f046 .dw XT_DOLITERAL
-00f6b8 005b .dw 'Z'+1
-00f6b9 f692 .dw XT_WITHIN
-00f6ba f03f .dw XT_DOCONDBRANCH
-00f6bb f6bf DEST(PFA_TOLOWER0)
-00f6bc f046 .dw XT_DOLITERAL
-00f6bd 0020 .dw 32
-00f6be f22e .dw XT_OR
- PFA_TOLOWER0:
-00f6bf f026 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-00f6c0 ff03 .dw $ff03
-00f6c1 6c68
-00f6c2 0064 .db "hld",0
-00f6c3 f6ad .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-00f6c4 f054 .dw PFA_DOVARIABLE
- PFA_HLD:
-00f6c5 013f .dw ram_hld
-
- .dseg
-00013f ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-00f6c6 ff04 .dw $ff04
-00f6c7 6f68
-00f6c8 646c .db "hold"
-00f6c9 f6c0 .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-00f6ca f001 .dw DO_COLON
- PFA_HOLD:
- .endif
-00f6cb f6c4 .dw XT_HLD
-00f6cc f0c3 .dw XT_DUP
-00f6cd f08b .dw XT_FETCH
-00f6ce f247 .dw XT_1MINUS
-00f6cf f0c3 .dw XT_DUP
-00f6d0 f111 .dw XT_TO_R
-00f6d1 f0d6 .dw XT_SWAP
-00f6d2 f093 .dw XT_STORE
-00f6d3 f108 .dw XT_R_FROM
-00f6d4 f09f .dw XT_CSTORE
-00f6d5 f026 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-00f6d6 ff02 .dw $ff02
-00f6d7 233c .db "<#"
-00f6d8 f6c6 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-00f6d9 f001 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-00f6da f59f .dw XT_PAD
-00f6db f6c4 .dw XT_HLD
-00f6dc f093 .dw XT_STORE
-00f6dd f026 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-00f6de ff01 .dw $ff01
-00f6df 0023 .db "#",0
-00f6e0 f6d6 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-00f6e1 f001 .dw DO_COLON
- PFA_SHARP:
- .endif
-00f6e2 f56c .dw XT_BASE
-00f6e3 f08b .dw XT_FETCH
-00f6e4 f75e .dw XT_UDSLASHMOD
-00f6e5 f0f3 .dw XT_ROT
-00f6e6 f046 .dw XT_DOLITERAL
-00f6e7 0009 .dw 9
-00f6e8 f0e1 .dw XT_OVER
-00f6e9 f180 .dw XT_LESS
-00f6ea f03f .dw XT_DOCONDBRANCH
-00f6eb f6ef DEST(PFA_SHARP1)
-00f6ec f046 .dw XT_DOLITERAL
-00f6ed 0007 .dw 7
-00f6ee f1af .dw XT_PLUS
- PFA_SHARP1:
-00f6ef f046 .dw XT_DOLITERAL
-00f6f0 0030 .dw 48 ; ASCII 0
-00f6f1 f1af .dw XT_PLUS
-00f6f2 f6ca .dw XT_HOLD
-00f6f3 f026 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-00f6f4 ff02 .dw $ff02
-00f6f5 7323 .db "#s"
-00f6f6 f6de .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-00f6f7 f001 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-00f6f8 f6e1 .dw XT_SHARP
-00f6f9 f580 .dw XT_2DUP
-00f6fa f22e .dw XT_OR
-00f6fb f12c .dw XT_ZEROEQUAL
-00f6fc f03f .dw XT_DOCONDBRANCH
-00f6fd f6f8 DEST(NUMS1) ; PFA_SHARP_S
-00f6fe f026 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00f6ff ff02 .dw $ff02
-00f700 3e23 .db "#>"
-00f701 f6f4 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00f702 f001 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-00f703 f589 .dw XT_2DROP
-00f704 f6c4 .dw XT_HLD
-00f705 f08b .dw XT_FETCH
-00f706 f59f .dw XT_PAD
-00f707 f0e1 .dw XT_OVER
-00f708 f1a5 .dw XT_MINUS
-00f709 f026 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-00f70a ff04 .dw $ff04
-00f70b 6973
-00f70c 6e67 .db "sign"
-00f70d f6ff .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00f70e f001 .dw DO_COLON
- PFA_SIGN:
- .endif
-00f70f f133 .dw XT_ZEROLESS
-00f710 f03f .dw XT_DOCONDBRANCH
-00f711 f715 DEST(PFA_SIGN1)
-00f712 f046 .dw XT_DOLITERAL
-00f713 002d .dw 45 ; ascii -
-00f714 f6ca .dw XT_HOLD
- PFA_SIGN1:
-00f715 f026 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-00f716 ff03 .dw $ff03
-00f717 2e64
-00f718 0072 .db "d.r",0
-00f719 f70a .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-00f71a f001 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-00f71b f111 .dw XT_TO_R
-00f71c f591 .dw XT_TUCK
-00f71d fcef .dw XT_DABS
-00f71e f6d9 .dw XT_L_SHARP
-00f71f f6f7 .dw XT_SHARP_S
-00f720 f0f3 .dw XT_ROT
-00f721 f70e .dw XT_SIGN
-00f722 f702 .dw XT_SHARP_G
-00f723 f108 .dw XT_R_FROM
-00f724 f0e1 .dw XT_OVER
-00f725 f1a5 .dw XT_MINUS
-00f726 f806 .dw XT_SPACES
-00f727 f816 .dw XT_TYPE
-00f728 f026 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-00f729 ff02 .dw $ff02
-00f72a 722e .db ".r"
-00f72b f716 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-00f72c f001 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-00f72d f111 .dw XT_TO_R
-00f72e fd82 .dw XT_S2D
-00f72f f108 .dw XT_R_FROM
-00f730 f71a .dw XT_DDOTR
-00f731 f026 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00f732 ff02 .dw $ff02
-00f733 2e64 .db "d."
-00f734 f729 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-00f735 f001 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-00f736 f166 .dw XT_ZERO
-00f737 f71a .dw XT_DDOTR
-00f738 f7fd .dw XT_SPACE
-00f739 f026 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-00f73a ff01 .dw $ff01
-00f73b 002e .db ".",0
-00f73c f732 .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-00f73d f001 .dw DO_COLON
- PFA_DOT:
- .endif
-00f73e fd82 .dw XT_S2D
-00f73f f735 .dw XT_DDOT
-00f740 f026 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-00f741 ff03 .dw $ff03
-00f742 6475
-00f743 002e .db "ud.",0
-00f744 f73a .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-00f745 f001 .dw DO_COLON
- PFA_UDDOT:
- .endif
-00f746 f166 .dw XT_ZERO
-00f747 f74e .dw XT_UDDOTR
-00f748 f7fd .dw XT_SPACE
-00f749 f026 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-00f74a ff04 .dw $ff04
-00f74b 6475
-00f74c 722e .db "ud.r"
-00f74d f741 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-00f74e f001 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-00f74f f111 .dw XT_TO_R
-00f750 f6d9 .dw XT_L_SHARP
-00f751 f6f7 .dw XT_SHARP_S
-00f752 f702 .dw XT_SHARP_G
-00f753 f108 .dw XT_R_FROM
-00f754 f0e1 .dw XT_OVER
-00f755 f1a5 .dw XT_MINUS
-00f756 f806 .dw XT_SPACES
-00f757 f816 .dw XT_TYPE
-00f758 f026 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-00f759 ff06 .dw $ff06
-00f75a 6475
-00f75b 6d2f
-00f75c 646f .db "ud/mod"
-00f75d f74a .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-00f75e f001 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-00f75f f111 .dw XT_TO_R
-00f760 f166 .dw XT_ZERO
-00f761 f11a .dw XT_R_FETCH
-00f762 f1d4 .dw XT_UMSLASHMOD
-00f763 f108 .dw XT_R_FROM
-00f764 f0d6 .dw XT_SWAP
-00f765 f111 .dw XT_TO_R
-00f766 f1d4 .dw XT_UMSLASHMOD
-00f767 f108 .dw XT_R_FROM
-00f768 f026 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-00f769 ff06 .dw $ff06
-00f76a 6964
-00f76b 6967
-00f76c 3f74 .db "digit?"
-00f76d f759 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-00f76e f001 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-00f76f f6a0 .dw XT_TOUPPER
-00f770 f0c3
-00f771 f046
-00f772 0039
-00f773 f18a
-00f774 f046
-00f775 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-00f776 f225
-00f777 f1af
-00f778 f0c3
-00f779 f046
-00f77a 0140
-00f77b f18a .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-00f77c f046
-00f77d 0107
-00f77e f225
-00f77f f1a5
-00f780 f046
-00f781 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-00f782 f1a5
-00f783 f0c3
-00f784 f56c
-00f785 f08b
-00f786 f16e .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-00f787 f026 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-00f788 f001 .dw DO_COLON
- PFA_DOSLITERAL:
-00f789 f11a .dw XT_R_FETCH ; ( -- addr )
-00f78a f7e7 .dw XT_ICOUNT
-00f78b f108 .dw XT_R_FROM
-00f78c f0e1 .dw XT_OVER ; ( -- addr' n addr n)
-00f78d f241 .dw XT_1PLUS
-00f78e f216 .dw XT_2SLASH ; ( -- addr' n addr k )
-00f78f f1af .dw XT_PLUS ; ( -- addr' n addr'' )
-00f790 f241 .dw XT_1PLUS
-00f791 f111 .dw XT_TO_R ; ( -- )
-00f792 f026 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-00f793 ff02 .dw $ff02
-00f794 2c73 .db "s",$2c
-00f795 f769 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-00f796 f001 .dw DO_COLON
- PFA_SCOMMA:
-00f797 f0c3 .dw XT_DUP
-00f798 f79a .dw XT_DOSCOMMA
-00f799 f026 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-00f79a f001 .dw DO_COLON
- PFA_DOSCOMMA:
-00f79b 01db .dw XT_COMMA
-00f79c f0c3 .dw XT_DUP ; ( --addr len len)
-00f79d f216 .dw XT_2SLASH ; ( -- addr len len/2
-00f79e f591 .dw XT_TUCK ; ( -- addr len/2 len len/2
-00f79f f21d .dw XT_2STAR ; ( -- addr len/2 len len'
-00f7a0 f1a5 .dw XT_MINUS ; ( -- addr len/2 rem
-00f7a1 f111 .dw XT_TO_R
-00f7a2 f166 .dw XT_ZERO
-00f7a3 029a .dw XT_QDOCHECK
-00f7a4 f03f .dw XT_DOCONDBRANCH
-00f7a5 f7ad .dw PFA_SCOMMA2
-00f7a6 f2ad .dw XT_DODO
- PFA_SCOMMA1:
-00f7a7 f0c3 .dw XT_DUP ; ( -- addr addr )
-00f7a8 f08b .dw XT_FETCH ; ( -- addr c1c2 )
-00f7a9 01db .dw XT_COMMA ; ( -- addr )
-00f7aa f579 .dw XT_CELLPLUS ; ( -- addr+cell )
-00f7ab f2db .dw XT_DOLOOP
-00f7ac f7a7 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-00f7ad f108 .dw XT_R_FROM
-00f7ae f13a .dw XT_GREATERZERO
-00f7af f03f .dw XT_DOCONDBRANCH
-00f7b0 f7b4 .dw PFA_SCOMMA3
-00f7b1 f0c3 .dw XT_DUP ; well, tricky
-00f7b2 f0aa .dw XT_CFETCH
-00f7b3 01db .dw XT_COMMA
- PFA_SCOMMA3:
-00f7b4 f0eb .dw XT_DROP ; ( -- )
-00f7b5 f026 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-00f7b6 ff05 .dw $ff05
-00f7b7 7469
-00f7b8 7079
-00f7b9 0065 .db "itype",0
-00f7ba f793 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-00f7bb f001 .dw DO_COLON
- PFA_ITYPE:
-00f7bc f0c3 .dw XT_DUP ; ( --addr len len)
-00f7bd f216 .dw XT_2SLASH ; ( -- addr len len/2
-00f7be f591 .dw XT_TUCK ; ( -- addr len/2 len len/2
-00f7bf f21d .dw XT_2STAR ; ( -- addr len/2 len len'
-00f7c0 f1a5 .dw XT_MINUS ; ( -- addr len/2 rem
-00f7c1 f111 .dw XT_TO_R
-00f7c2 f166 .dw XT_ZERO
-00f7c3 029a .dw XT_QDOCHECK
-00f7c4 f03f .dw XT_DOCONDBRANCH
-00f7c5 f7cf .dw PFA_ITYPE2
-00f7c6 f2ad .dw XT_DODO
- PFA_ITYPE1:
-00f7c7 f0c3 .dw XT_DUP ; ( -- addr addr )
-00f7c8 f3e3 .dw XT_FETCHI ; ( -- addr c1c2 )
-00f7c9 f0c3 .dw XT_DUP
-00f7ca f7dc .dw XT_LOWEMIT
-00f7cb f7d8 .dw XT_HIEMIT
-00f7cc f241 .dw XT_1PLUS ; ( -- addr+cell )
-00f7cd f2db .dw XT_DOLOOP
-00f7ce f7c7 .dw PFA_ITYPE1
- PFA_ITYPE2:
-00f7cf f108 .dw XT_R_FROM
-00f7d0 f13a .dw XT_GREATERZERO
-00f7d1 f03f .dw XT_DOCONDBRANCH
-00f7d2 f7d6 .dw PFA_ITYPE3
-00f7d3 f0c3 .dw XT_DUP ; make sure the drop below has always something to do
-00f7d4 f3e3 .dw XT_FETCHI
-00f7d5 f7dc .dw XT_LOWEMIT
- PFA_ITYPE3:
-00f7d6 f0eb .dw XT_DROP
-00f7d7 f026 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-00f7d8 f001 .dw DO_COLON
- PFA_HIEMIT:
-00f7d9 f30b .dw XT_BYTESWAP
-00f7da f7dc .dw XT_LOWEMIT
-00f7db f026 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-00f7dc f001 .dw DO_COLON
- PFA_LOWEMIT:
-00f7dd f046 .dw XT_DOLITERAL
-00f7de 00ff .dw $00ff
-00f7df f225 .dw XT_AND
-00f7e0 f5a9 .dw XT_EMIT
-00f7e1 f026 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00f7e2 ff06 .dw $ff06
-00f7e3 6369
-00f7e4 756f
-00f7e5 746e .db "icount"
-00f7e6 f7b6 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-00f7e7 f001 .dw DO_COLON
- PFA_ICOUNT:
-00f7e8 f0c3 .dw XT_DUP
-00f7e9 f241 .dw XT_1PLUS
-00f7ea f0d6 .dw XT_SWAP
-00f7eb f3e3 .dw XT_FETCHI
-00f7ec f026 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-00f7ed ff02 .dw 0xff02
-00f7ee 7263 .db "cr"
-00f7ef f7e2 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-00f7f0 f001 .dw DO_COLON
- PFA_CR:
- .endif
-
-00f7f1 f046 .dw XT_DOLITERAL
-00f7f2 000d .dw 13
-00f7f3 f5a9 .dw XT_EMIT
-00f7f4 f046 .dw XT_DOLITERAL
-00f7f5 000a .dw 10
-00f7f6 f5a9 .dw XT_EMIT
-00f7f7 f026 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-00f7f8 ff05 .dw $ff05
-00f7f9 7073
-00f7fa 6361
-00f7fb 0065 .db "space",0
-00f7fc f7ed .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-00f7fd f001 .dw DO_COLON
- PFA_SPACE:
- .endif
-00f7fe f60b .dw XT_BL
-00f7ff f5a9 .dw XT_EMIT
-00f800 f026 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-00f801 ff06 .dw $ff06
-00f802 7073
-00f803 6361
-00f804 7365 .db "spaces"
-00f805 f7f8 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-00f806 f001 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-00f807 f166
-00f808 f685 .DW XT_ZERO, XT_MAX
-00f809 f0c3
-00f80a f03f SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-00f80b f810 DEST(SPCS2)
-00f80c f7fd
-00f80d f247
-00f80e f035 .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-00f80f f809 DEST(SPCS1)
-00f810 f0eb
-00f811 f026 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-00f812 ff04 .dw $ff04
-00f813 7974
-00f814 6570 .db "type"
-00f815 f801 .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-00f816 f001 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-00f817 fd79 .dw XT_BOUNDS
-00f818 029a .dw XT_QDOCHECK
-00f819 f03f .dw XT_DOCONDBRANCH
-00f81a f821 DEST(PFA_TYPE2)
-00f81b f2ad .dw XT_DODO
- PFA_TYPE1:
-00f81c f2be .dw XT_I
-00f81d f0aa .dw XT_CFETCH
-00f81e f5a9 .dw XT_EMIT
-00f81f f2db .dw XT_DOLOOP
-00f820 f81c DEST(PFA_TYPE1)
- PFA_TYPE2:
-00f821 f026 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00f822 ff01 .dw $ff01
-00f823 0027 .db "'",0
-00f824 f812 .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00f825 f001 .dw DO_COLON
- PFA_TICK:
- .endif
-00f826 f9cf .dw XT_PARSENAME
-00f827 fae7 .dw XT_FORTHRECOGNIZER
-00f828 faf2 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-00f829 f0c3 .dw XT_DUP
-00f82a fb65 .dw XT_DT_NULL
-00f82b fd9a .dw XT_EQUAL
-00f82c f0d6 .dw XT_SWAP
-00f82d f3e3 .dw XT_FETCHI
-00f82e f046 .dw XT_DOLITERAL
-00f82f fb9a .dw XT_NOOP
-00f830 fd9a .dw XT_EQUAL
-00f831 f22e .dw XT_OR
-00f832 f03f .dw XT_DOCONDBRANCH
-00f833 f837 DEST(PFA_TICK1)
-00f834 f046 .dw XT_DOLITERAL
-00f835 fff3 .dw -13
-00f836 f85c .dw XT_THROW
- PFA_TICK1:
-00f837 f0eb .dw XT_DROP
-00f838 f026 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-00f839 ff07 .dw $ff07
-00f83a 6168
-00f83b 646e
-00f83c 656c
-00f83d 0072 .db "handler",0
-00f83e f822 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-00f83f f067 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-00f840 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-00f841 ff05 .dw $ff05
-00f842 6163
-00f843 6374
-00f844 0068 .db "catch",0
-00f845 f839 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-00f846 f001 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-00f847 f29f .dw XT_SP_FETCH
-00f848 f111 .dw XT_TO_R
- ; handler @ >r
-00f849 f83f .dw XT_HANDLER
-00f84a f08b .dw XT_FETCH
-00f84b f111 .dw XT_TO_R
- ; rp@ handler !
-00f84c f288 .dw XT_RP_FETCH
-00f84d f83f .dw XT_HANDLER
-00f84e f093 .dw XT_STORE
-00f84f f030 .dw XT_EXECUTE
- ; r> handler !
-00f850 f108 .dw XT_R_FROM
-00f851 f83f .dw XT_HANDLER
-00f852 f093 .dw XT_STORE
-00f853 f108 .dw XT_R_FROM
-00f854 f0eb .dw XT_DROP
-00f855 f166 .dw XT_ZERO
-00f856 f026 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-00f857 ff05 .dw $ff05
-00f858 6874
-00f859 6f72
-00f85a 0077 .db "throw",0
-00f85b f841 .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-00f85c f001 .dw DO_COLON
- PFA_THROW:
- .endif
-00f85d f0c3 .dw XT_DUP
-00f85e f12c .dw XT_ZEROEQUAL
-00f85f f03f .dw XT_DOCONDBRANCH
-00f860 f863 DEST(PFA_THROW1)
-00f861 f0eb .dw XT_DROP
-00f862 f026 .dw XT_EXIT
- PFA_THROW1:
-00f863 f83f .dw XT_HANDLER
-00f864 f08b .dw XT_FETCH
-00f865 f292 .dw XT_RP_STORE
-00f866 f108 .dw XT_R_FROM
-00f867 f83f .dw XT_HANDLER
-00f868 f093 .dw XT_STORE
-00f869 f108 .dw XT_R_FROM
-00f86a f0d6 .dw XT_SWAP
-00f86b f111 .dw XT_TO_R
-00f86c f2a8 .dw XT_SP_STORE
-00f86d f0eb .dw XT_DROP
-00f86e f108 .dw XT_R_FROM
-00f86f f026 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-00f870 ff05 .dw $ff05
-00f871 7363
-00f872 696b
-00f873 0070 .db "cskip",0
-00f874 f857 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-00f875 f001 .dw DO_COLON
- PFA_CSKIP:
- .endif
-00f876 f111 .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-00f877 f0c3 .dw XT_DUP ; ( -- addr' n' n' )
-00f878 f03f .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00f879 f884 DEST(PFA_CSKIP2)
-00f87a f0e1 .dw XT_OVER ; ( -- addr' n' addr' )
-00f87b f0aa .dw XT_CFETCH ; ( -- addr' n' c' )
-00f87c f11a .dw XT_R_FETCH ; ( -- addr' n' c' c )
-00f87d fd9a .dw XT_EQUAL ; ( -- addr' n' f )
-00f87e f03f .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00f87f f884 DEST(PFA_CSKIP2)
-00f880 fda1 .dw XT_ONE
-00f881 f9c0 .dw XT_SLASHSTRING
-00f882 f035 .dw XT_DOBRANCH
-00f883 f877 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-00f884 f108 .dw XT_R_FROM
-00f885 f0eb .dw XT_DROP ; ( -- addr2 n2)
-00f886 f026 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-00f887 ff05 .dw $ff05
-00f888 7363
-00f889 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00f88a 006e .db "cscan"
-00f88b f870 .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-00f88c f001 .dw DO_COLON
- PFA_CSCAN:
- .endif
-00f88d f111 .dw XT_TO_R
-00f88e f0e1 .dw XT_OVER
- PFA_CSCAN1:
-00f88f f0c3 .dw XT_DUP
-00f890 f0aa .dw XT_CFETCH
-00f891 f11a .dw XT_R_FETCH
-00f892 fd9a .dw XT_EQUAL
-00f893 f12c .dw XT_ZEROEQUAL
-00f894 f03f .dw XT_DOCONDBRANCH
-00f895 f8a1 DEST(PFA_CSCAN2)
-00f896 f0d6 .dw XT_SWAP
-00f897 f247 .dw XT_1MINUS
-00f898 f0d6 .dw XT_SWAP
-00f899 f0e1 .dw XT_OVER
-00f89a f133 .dw XT_ZEROLESS ; not negative
-00f89b f12c .dw XT_ZEROEQUAL
-00f89c f03f .dw XT_DOCONDBRANCH
-00f89d f8a1 DEST(PFA_CSCAN2)
-00f89e f241 .dw XT_1PLUS
-00f89f f035 .dw XT_DOBRANCH
-00f8a0 f88f DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-00f8a1 f102 .dw XT_NIP
-00f8a2 f0e1 .dw XT_OVER
-00f8a3 f1a5 .dw XT_MINUS
-00f8a4 f108 .dw XT_R_FROM
-00f8a5 f0eb .dw XT_DROP
-00f8a6 f026 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-00f8a7 ff06 .dw $ff06
-00f8a8 6361
-00f8a9 6563
-00f8aa 7470 .db "accept"
-00f8ab f887 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-00f8ac f001 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-00f8ad f0e1
-00f8ae f1af
-00f8af f247
-00f8b0 f0e1 .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-00f8b1 f5ba
-00f8b2 f0c3
-00f8b3 f8ed
-00f8b4 f12c
-00f8b5 f03f ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-00f8b6 f8df DEST(ACC5)
-00f8b7 f0c3
-00f8b8 f046
-00f8b9 0008
-00f8ba fd9a
-00f8bb f03f .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-00f8bc f8cf DEST(ACC3)
-00f8bd f0eb
-00f8be f0f3
-00f8bf f580
-00f8c0 f18a
-00f8c1 f111
-00f8c2 f0f3
-00f8c3 f0f3
-00f8c4 f108
-00f8c5 f03f .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-00f8c6 f8cd DEST(ACC6)
-00f8c7 f8e5
-00f8c8 f247
-00f8c9 f111
-00f8ca f0e1
-00f8cb f108
-00f8cc 016d .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-00f8cd f035 ACC6: .DW XT_DOBRANCH
-00f8ce f8dd DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-00f8cf f0c3 .dw XT_DUP ; ( -- addr k k )
-00f8d0 f60b .dw XT_BL
-00f8d1 f180 .dw XT_LESS
-00f8d2 f03f .dw XT_DOCONDBRANCH
-00f8d3 f8d6 DEST(PFA_ACCEPT6)
-00f8d4 f0eb .dw XT_DROP
-00f8d5 f60b .dw XT_BL
- PFA_ACCEPT6:
-00f8d6 f0c3
-00f8d7 f5a9
-00f8d8 f0e1
-00f8d9 f09f
-00f8da f241
-00f8db f0e1
-00f8dc 0179 .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-00f8dd f035 ACC4: .DW XT_DOBRANCH
-00f8de f8b1 DEST(ACC1)
-00f8df f0eb
-00f8e0 f102
-00f8e1 f0d6
-00f8e2 f1a5
-00f8e3 f7f0
-00f8e4 f026 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-00f8e5 f001 .dw DO_COLON
- .endif
-00f8e6 f046 .dw XT_DOLITERAL
-00f8e7 0008 .dw 8
-00f8e8 f0c3 .dw XT_DUP
-00f8e9 f5a9 .dw XT_EMIT
-00f8ea f7fd .dw XT_SPACE
-00f8eb f5a9 .dw XT_EMIT
-00f8ec f026 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-00f8ed f001 .dw DO_COLON
- .endif
-00f8ee f0c3 .dw XT_DUP
-00f8ef f046 .dw XT_DOLITERAL
-00f8f0 000d .dw 13
-00f8f1 fd9a .dw XT_EQUAL
-00f8f2 f0d6 .dw XT_SWAP
-00f8f3 f046 .dw XT_DOLITERAL
-00f8f4 000a .dw 10
-00f8f5 fd9a .dw XT_EQUAL
-00f8f6 f22e .dw XT_OR
-00f8f7 f026 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-00f8f8 ff06 .dw $ff06
-00f8f9 6572
-00f8fa 6966
-00f8fb 6c6c .db "refill"
-00f8fc f8a7 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-00f8fd fc2e .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-00f8fe 001a .dw USER_REFILL
-00f8ff fbf7 .dw XT_UDEFERFETCH
-00f900 fc03 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-00f901 ff04 .dw $ff04
-00f902 6863
-00f903 7261 .db "char"
-00f904 f8f8 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-00f905 f001 .dw DO_COLON
- PFA_CHAR:
- .endif
-00f906 f9cf .dw XT_PARSENAME
-00f907 f0eb .dw XT_DROP
-00f908 f0aa .dw XT_CFETCH
-00f909 f026 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-00f90a ff06 .dw $ff06
-00f90b 756e
-00f90c 626d
-00f90d 7265 .db "number"
-00f90e f901 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-00f90f f001 .dw DO_COLON
- PFA_NUMBER:
- .endif
-00f910 f56c .dw XT_BASE
-00f911 f08b .dw XT_FETCH
-00f912 f111 .dw XT_TO_R
-00f913 f953 .dw XT_QSIGN
-00f914 f111 .dw XT_TO_R
-00f915 f966 .dw XT_SET_BASE
-00f916 f953 .dw XT_QSIGN
-00f917 f108 .dw XT_R_FROM
-00f918 f22e .dw XT_OR
-00f919 f111 .dw XT_TO_R
- ; check whether something is left
-00f91a f0c3 .dw XT_DUP
-00f91b f12c .dw XT_ZEROEQUAL
-00f91c f03f .dw XT_DOCONDBRANCH
-00f91d f926 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-00f91e f589 .dw XT_2DROP
-00f91f f108 .dw XT_R_FROM
-00f920 f0eb .dw XT_DROP
-00f921 f108 .dw XT_R_FROM
-00f922 f56c .dw XT_BASE
-00f923 f093 .dw XT_STORE
-00f924 f166 .dw XT_ZERO
-00f925 f026 .dw XT_EXIT
- PFA_NUMBER0:
-00f926 f330 .dw XT_2TO_R
-00f927 f166 .dw XT_ZERO ; starting value
-00f928 f166 .dw XT_ZERO
-00f929 f33f .dw XT_2R_FROM
-00f92a f984 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-00f92b f0cb .dw XT_QDUP
-00f92c f03f .dw XT_DOCONDBRANCH
-00f92d f948 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00f92e fda1 .dw XT_ONE
-00f92f fd9a .dw XT_EQUAL
-00f930 f03f .dw XT_DOCONDBRANCH
-00f931 f93f DEST(PFA_NUMBER2)
- ; excatly one character is left
-00f932 f0aa .dw XT_CFETCH
-00f933 f046 .dw XT_DOLITERAL
-00f934 002e .dw 46 ; .
-00f935 fd9a .dw XT_EQUAL
-00f936 f03f .dw XT_DOCONDBRANCH
-00f937 f940 DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-00f938 f108 .dw XT_R_FROM
-00f939 f03f .dw XT_DOCONDBRANCH
-00f93a f93c DEST(PFA_NUMBER3)
-00f93b fcfc .dw XT_DNEGATE
- PFA_NUMBER3:
-00f93c fda6 .dw XT_TWO
-00f93d f035 .dw XT_DOBRANCH
-00f93e f94e DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-00f93f f0eb .dw XT_DROP
- PFA_NUMBER6:
-00f940 f589 .dw XT_2DROP
-00f941 f108 .dw XT_R_FROM
-00f942 f0eb .dw XT_DROP
-00f943 f108 .dw XT_R_FROM
-00f944 f56c .dw XT_BASE
-00f945 f093 .dw XT_STORE
-00f946 f166 .dw XT_ZERO
-00f947 f026 .dw XT_EXIT
- PFA_NUMBER1:
-00f948 f589 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-00f949 f108 .dw XT_R_FROM
-00f94a f03f .dw XT_DOCONDBRANCH
-00f94b f94d DEST(PFA_NUMBER4)
-00f94c f65a .dw XT_NEGATE
- PFA_NUMBER4:
-00f94d fda1 .dw XT_ONE
- PFA_NUMBER5:
-00f94e f108 .dw XT_R_FROM
-00f94f f56c .dw XT_BASE
-00f950 f093 .dw XT_STORE
-00f951 f15d .dw XT_TRUE
-00f952 f026 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-00f953 f001 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-00f954 f0e1 .dw XT_OVER ; ( -- addr len addr )
-00f955 f0aa .dw XT_CFETCH
-00f956 f046 .dw XT_DOLITERAL
-00f957 002d .dw '-'
-00f958 fd9a .dw XT_EQUAL ; ( -- addr len flag )
-00f959 f0c3 .dw XT_DUP
-00f95a f111 .dw XT_TO_R
-00f95b f03f .dw XT_DOCONDBRANCH
-00f95c f95f DEST(PFA_NUMBERSIGN_DONE)
-00f95d fda1 .dw XT_ONE ; skip sign character
-00f95e f9c0 .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-00f95f f108 .dw XT_R_FROM
-00f960 f026 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-00f961 f061 .dw PFA_DOCONSTANT
- .endif
-00f962 000a
-00f963 0010
-00f964 0002
-00f965 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-00f966 f001 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-00f967 f0e1 .dw XT_OVER
-00f968 f0aa .dw XT_CFETCH
-00f969 f046 .dw XT_DOLITERAL
-00f96a 0023 .dw 35
-00f96b f1a5 .dw XT_MINUS
-00f96c f0c3 .dw XT_DUP
-00f96d f166 .dw XT_ZERO
-00f96e f046 .dw XT_DOLITERAL
-00f96f 0004 .dw 4
-00f970 f692 .dw XT_WITHIN
-00f971 f03f .dw XT_DOCONDBRANCH
-00f972 f97c DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-00f973 f961 .dw XT_BASES
-00f974 f1af .dw XT_PLUS
-00f975 f3e3 .dw XT_FETCHI
-00f976 f56c .dw XT_BASE
-00f977 f093 .dw XT_STORE
-00f978 fda1 .dw XT_ONE
-00f979 f9c0 .dw XT_SLASHSTRING
-00f97a f035 .dw XT_DOBRANCH
-00f97b f97d DEST(SET_BASE2)
- SET_BASE1:
-00f97c f0eb .dw XT_DROP
- SET_BASE2:
-00f97d f026 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00f97e ff07 .dw $ff07
-00f97f 6e3e
-00f980 6d75
-00f981 6562
-00f982 0072 .db ">number",0
-00f983 f90a .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-00f984 f001 .dw DO_COLON
-
- .endif
-
-00f985 f0c3
-00f986 f03f TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-00f987 f99c DEST(TONUM3)
-00f988 f0e1
-00f989 f0aa
-00f98a f76e .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-00f98b f12c
-00f98c f03f .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-00f98d f990 DEST(TONUM2)
-00f98e f0eb
-00f98f f026 .DW XT_DROP,XT_EXIT
-00f990 f111
-00f991 fd20
-00f992 f56c
-00f993 f08b
-00f994 015e TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-00f995 f108
-00f996 0156
-00f997 fd20 .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-00f998 fda1
-00f999 f9c0
-00f99a f035 .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-00f99b f985 DEST(TONUM1)
-00f99c f026 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-00f99d ff05 .dw $ff05
-00f99e 6170
-00f99f 7372
-00f9a0 0065 .db "parse",0
-00f9a1 f97e .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-00f9a2 f001 .dw DO_COLON
- PFA_PARSE:
- .endif
-00f9a3 f111 .dw XT_TO_R ; ( -- )
-00f9a4 f9b6 .dw XT_SOURCE ; ( -- addr len)
-00f9a5 f599 .dw XT_TO_IN ; ( -- addr len >in)
-00f9a6 f08b .dw XT_FETCH
-00f9a7 f9c0 .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-00f9a8 f108 .dw XT_R_FROM ; ( -- addr' len' c)
-00f9a9 f88c .dw XT_CSCAN ; ( -- addr' len'')
-00f9aa f0c3 .dw XT_DUP ; ( -- addr' len'' len'')
-00f9ab f241 .dw XT_1PLUS
-00f9ac f599 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-00f9ad f277 .dw XT_PLUSSTORE ; ( -- addr' len')
-00f9ae fda1 .dw XT_ONE
-00f9af f9c0 .dw XT_SLASHSTRING
-00f9b0 f026 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-00f9b1 ff06 .dw $FF06
-00f9b2 6f73
-00f9b3 7275
-00f9b4 6563 .db "source"
-00f9b5 f99d .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-00f9b6 fc2e .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-00f9b7 0016 .dw USER_SOURCE
-00f9b8 fbf7 .dw XT_UDEFERFETCH
-00f9b9 fc03 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00f9ba ff07 .dw $ff07
-00f9bb 732f
-00f9bc 7274
-00f9bd 6e69
-00f9be 0067 .db "/string",0
-00f9bf f9b1 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-00f9c0 f001 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-00f9c1 f0f3 .dw XT_ROT
-00f9c2 f0e1 .dw XT_OVER
-00f9c3 f1af .dw XT_PLUS
-00f9c4 f0f3 .dw XT_ROT
-00f9c5 f0f3 .dw XT_ROT
-00f9c6 f1a5 .dw XT_MINUS
-00f9c7 f026 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-00f9c8 ff0a .dw $FF0A
-00f9c9 6170
-00f9ca 7372
-00f9cb 2d65
-00f9cc 616e
-00f9cd 656d .db "parse-name"
-00f9ce f9ba .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-00f9cf f001 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-00f9d0 f60b .dw XT_BL
-00f9d1 f9d3 .dw XT_SKIPSCANCHAR
-00f9d2 f026 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-00f9d3 f001 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-00f9d4 f111 .dw XT_TO_R
-00f9d5 f9b6 .dw XT_SOURCE
-00f9d6 f599 .dw XT_TO_IN
-00f9d7 f08b .dw XT_FETCH
-00f9d8 f9c0 .dw XT_SLASHSTRING
-
-00f9d9 f11a .dw XT_R_FETCH
-00f9da f875 .dw XT_CSKIP
-00f9db f108 .dw XT_R_FROM
-00f9dc f88c .dw XT_CSCAN
-
- ; adjust >IN
-00f9dd f580 .dw XT_2DUP
-00f9de f1af .dw XT_PLUS
-00f9df f9b6 .dw XT_SOURCE
-00f9e0 f0eb .dw XT_DROP
-00f9e1 f1a5 .dw XT_MINUS
-00f9e2 f599 .dw XT_TO_IN
-00f9e3 f093 .dw XT_STORE
-00f9e4 f026 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-00f9e5 ff07 .dw $ff07
-00f9e6 6966
-00f9e7 646e
-00f9e8 782d
-00f9e9 0074 .db "find-xt",0
-00f9ea f9c8 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-00f9eb f001 .dw DO_COLON
- PFA_FINDXT:
- .endif
-00f9ec f046 .dw XT_DOLITERAL
-00f9ed f9f7 .dw XT_FINDXTA
-00f9ee f046 .dw XT_DOLITERAL
-00f9ef 005c .dw CFG_ORDERLISTLEN
-00f9f0 041b .dw XT_MAPSTACK
-00f9f1 f12c .dw XT_ZEROEQUAL
-00f9f2 f03f .dw XT_DOCONDBRANCH
-00f9f3 f9f6 DEST(PFA_FINDXT1)
-00f9f4 f589 .dw XT_2DROP
-00f9f5 f166 .dw XT_ZERO
- PFA_FINDXT1:
-00f9f6 f026 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-00f9f7 f001 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-00f9f8 f111 .dw XT_TO_R
-00f9f9 f580 .dw XT_2DUP
-00f9fa f108 .dw XT_R_FROM
-00f9fb fc40 .dw XT_SEARCH_WORDLIST
-00f9fc f0c3 .dw XT_DUP
-00f9fd f03f .dw XT_DOCONDBRANCH
-00f9fe fa04 DEST(PFA_FINDXTA1)
-00f9ff f111 .dw XT_TO_R
-00fa00 f102 .dw XT_NIP
-00fa01 f102 .dw XT_NIP
-00fa02 f108 .dw XT_R_FROM
-00fa03 f15d .dw XT_TRUE
- PFA_FINDXTA1:
-00fa04 f026 .dw XT_EXIT
-
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-00fa05 f001 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-00fa06 f788 .dw XT_DOSLITERAL
-00fa07 0003 .dw 3
-00fa08 6f20
-00fa09 006b .db " ok",0
- .endif
-00fa0a f7bb .dw XT_ITYPE
-00fa0b f026 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-00fa0c ff03 .dw $FF03
-00fa0d 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-00fa0e 006b .db ".ok"
-00fa0f f9e5 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-00fa10 fc2e .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-00fa11 001c .dw USER_P_OK
-00fa12 fbf7 .dw XT_UDEFERFETCH
-00fa13 fc03 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-00fa14 f001 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-00fa15 f788 .dw XT_DOSLITERAL
-00fa16 0002 .dw 2
-00fa17 203e .db "> "
- .endif
-00fa18 f7f0 .dw XT_CR
-00fa19 f7bb .dw XT_ITYPE
-00fa1a f026 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-00fa1b ff06 .dw $FF06
-00fa1c 722e
-00fa1d 6165
-00fa1e 7964 .db ".ready"
-00fa1f fa0c .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-00fa20 fc2e .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-00fa21 0020 .dw USER_P_RDY
-00fa22 fbf7 .dw XT_UDEFERFETCH
-00fa23 fc03 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-00fa24 f001 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-00fa25 f788 .dw XT_DOSLITERAL
-00fa26 0004 .dw 4
-00fa27 3f20
-00fa28 203f .db " ?? "
- .endif
-00fa29 f7bb .dw XT_ITYPE
-00fa2a f56c .dw XT_BASE
-00fa2b f08b .dw XT_FETCH
-00fa2c f111 .dw XT_TO_R
-00fa2d f5f8 .dw XT_DECIMAL
-00fa2e f73d .dw XT_DOT
-00fa2f f599 .dw XT_TO_IN
-00fa30 f08b .dw XT_FETCH
-00fa31 f73d .dw XT_DOT
-00fa32 f108 .dw XT_R_FROM
-00fa33 f56c .dw XT_BASE
-00fa34 f093 .dw XT_STORE
-00fa35 f026 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-00fa36 ff06 .dw $FF06
-00fa37 652e
-00fa38 7272
-00fa39 726f .db ".error"
-00fa3a fa1b .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-00fa3b fc2e .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-00fa3c 001e .dw USER_P_ERR
-00fa3d fbf7 .dw XT_UDEFERFETCH
-00fa3e fc03 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-00fa3f ff04 .dw $ff04
-00fa40 7571
-00fa41 7469 .db "quit"
-00fa42 fa36 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-00fa43 f001 .dw DO_COLON
- .endif
- PFA_QUIT:
-00fa44 02d0
-00fa45 02d7
-00fa46 f093 .dw XT_LP0,XT_LP,XT_STORE
-00fa47 faa4 .dw XT_SP0
-00fa48 f2a8 .dw XT_SP_STORE
-00fa49 fab1 .dw XT_RP0
-00fa4a f292 .dw XT_RP_STORE
-00fa4b 0365 .dw XT_LBRACKET
-
- PFA_QUIT2:
-00fa4c f566 .dw XT_STATE
-00fa4d f08b .dw XT_FETCH
-00fa4e f12c .dw XT_ZEROEQUAL
-00fa4f f03f .dw XT_DOCONDBRANCH
-00fa50 fa52 DEST(PFA_QUIT4)
-00fa51 fa20 .dw XT_PROMPTREADY
- PFA_QUIT4:
-00fa52 f8fd .dw XT_REFILL
-00fa53 f03f .dw XT_DOCONDBRANCH
-00fa54 fa64 DEST(PFA_QUIT3)
-00fa55 f046 .dw XT_DOLITERAL
-00fa56 faca .dw XT_INTERPRET
-00fa57 f846 .dw XT_CATCH
-00fa58 f0cb .dw XT_QDUP
-00fa59 f03f .dw XT_DOCONDBRANCH
-00fa5a fa64 DEST(PFA_QUIT3)
-00fa5b f0c3 .dw XT_DUP
-00fa5c f046 .dw XT_DOLITERAL
-00fa5d fffe .dw -2
-00fa5e f180 .dw XT_LESS
-00fa5f f03f .dw XT_DOCONDBRANCH
-00fa60 fa62 DEST(PFA_QUIT5)
-00fa61 fa3b .dw XT_PROMPTERROR
- PFA_QUIT5:
-00fa62 f035 .dw XT_DOBRANCH
-00fa63 fa44 DEST(PFA_QUIT)
- PFA_QUIT3:
-00fa64 fa10 .dw XT_PROMPTOK
-00fa65 f035 .dw XT_DOBRANCH
-00fa66 fa4c DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-00fa67 ff05 .dw $ff05
-00fa68 6170
-00fa69 7375
-00fa6a 0065 .db "pause",0
-00fa6b fa3f .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-00fa6c fc2e .dw PFA_DODEFER1
- PFA_PAUSE:
-00fa6d 0141 .dw ram_pause
-00fa6e fbe3 .dw XT_RDEFERFETCH
-00fa6f fbed .dw XT_RDEFERSTORE
-
- .dseg
-000141 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-00fa70 ff04 .dw $ff04
-00fa71 6f63
-00fa72 646c .db "cold"
-00fa73 fa67 .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-00fa74 fa75 .dw PFA_COLD
- PFA_COLD:
-00fa75 b6a4 in_ mcu_boot, MCUSR
-00fa76 2422 clr zerol
-00fa77 2433 clr zeroh
-00fa78 24bb clr isrflag
-00fa79 be24 out_ MCUSR, zerol
- ; clear RAM
-00fa7a e0e0 ldi zl, low(ramstart)
-00fa7b e0f1 ldi zh, high(ramstart)
- clearloop:
-00fa7c 9221 st Z+, zerol
-00fa7d 30e0 cpi zl, low(sram_size+ramstart)
-00fa7e f7e9 brne clearloop
-00fa7f 34f1 cpi zh, high(sram_size+ramstart)
-00fa80 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000143 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-00fa81 e4e3 ldi zl, low(ram_user1)
-00fa82 e0f1 ldi zh, high(ram_user1)
-00fa83 012f movw upl, zl
- ; init return stack pointer
-00fa84 ef0f ldi temp0,low(rstackstart)
-00fa85 bf0d out_ SPL,temp0
-00fa86 8304 std Z+4, temp0
-00fa87 e410 ldi temp1,high(rstackstart)
-00fa88 bf1e out_ SPH,temp1
-00fa89 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-00fa8a eacf ldi yl,low(stackstart)
-00fa8b 83c6 std Z+6, yl
-00fa8c e4d0 ldi yh,high(stackstart)
-00fa8d 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-00fa8e e9a7 ldi XL, low(PFA_WARM)
-00fa8f efba ldi XH, high(PFA_WARM)
- ; its a far jump...
-00fa90 940c f005 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-00fa92 ff04 .dw $ff04
-00fa93 6177
-00fa94 6d72 .db "warm"
-00fa95 fa70 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-00fa96 f001 .dw DO_COLON
- PFA_WARM:
- .endif
-00fa97 fd6b .dw XT_INIT_RAM
-00fa98 f046 .dw XT_DOLITERAL
-00fa99 fb9a .dw XT_NOOP
-00fa9a f046 .dw XT_DOLITERAL
-00fa9b fa6c .dw XT_PAUSE
-00fa9c fc0e .dw XT_DEFERSTORE
-00fa9d 0365 .dw XT_LBRACKET
-00fa9e f613 .dw XT_TURNKEY
-00fa9f fa43 .dw XT_QUIT ; never returns
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-00faa0 ff03 .dw $ff03
-00faa1 7073
-00faa2 0030 .db "sp0",0
-00faa3 fa92 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-00faa4 f081 .dw PFA_DOVALUE1
- PFA_SP0:
-00faa5 0006 .dw USER_SP0
-00faa6 fbf7 .dw XT_UDEFERFETCH
-00faa7 fc03 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-00faa8 ff02 .dw $ff02
-00faa9 7073 .db "sp"
-00faaa faa0 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-00faab f067 .dw PFA_DOUSER
- PFA_SP:
-00faac 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-00faad ff03 .dw $ff03
-00faae 7072
-00faaf 0030 .db "rp0",0
-00fab0 faa8 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-00fab1 f001 .dw DO_COLON
- PFA_RP0:
-00fab2 fab5 .dw XT_DORP0
-00fab3 f08b .dw XT_FETCH
-00fab4 f026 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-00fab5 f067 .dw PFA_DOUSER
- PFA_DORP0:
-00fab6 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-00fab7 ff05 .dw $ff05
-00fab8 6564
-00fab9 7470
-00faba 0068 .db "depth",0
-00fabb faad .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-00fabc f001 .dw DO_COLON
- PFA_DEPTH:
- .endif
-00fabd faa4 .dw XT_SP0
-00fabe f29f .dw XT_SP_FETCH
-00fabf f1a5 .dw XT_MINUS
-00fac0 f216 .dw XT_2SLASH
-00fac1 f247 .dw XT_1MINUS
-00fac2 f026 .dw XT_EXIT
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-00fac3 ff09 .dw $ff09
-00fac4 6e69
-00fac5 6574
-00fac6 7072
-00fac7 6572
-00fac8 0074 .db "interpret",0
-00fac9 fab7 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-00faca f001 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-00facb f9cf .dw XT_PARSENAME ; ( -- addr len )
-00facc f0c3 .dw XT_DUP ; ( -- addr len flag)
-00facd f03f .dw XT_DOCONDBRANCH
-00face fadb DEST(PFA_INTERPRET2)
-00facf fae7 .dw XT_FORTHRECOGNIZER
-00fad0 faf2 .dw XT_RECOGNIZE
-00fad1 f566 .dw XT_STATE
-00fad2 f08b .dw XT_FETCH
-00fad3 f03f .dw XT_DOCONDBRANCH
-00fad4 fad6 DEST(PFA_INTERPRET1)
-00fad5 fbc6 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-00fad6 f3e3 .dw XT_FETCHI
-00fad7 f030 .dw XT_EXECUTE
-00fad8 fb72 .dw XT_QSTACK
-00fad9 f035 .dw XT_DOBRANCH
-00fada facb DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-00fadb f589 .dw XT_2DROP
-00fadc f026 .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-00fadd ff10 .dw $ff10
-00fade 6f66
-00fadf 7472
-00fae0 2d68
-00fae1 6572
-00fae2 6f63
-00fae3 6e67
-00fae4 7a69
-00fae5 7265 .db "forth-recognizer"
-00fae6 fac3 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-00fae7 f081 .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-00fae8 0050 .dw CFG_FORTHRECOGNIZER
-00fae9 fbcf .dw XT_EDEFERFETCH
-00faea fbd9 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-00faeb ff09 .dw $ff09
-00faec 6572
-00faed 6f63
-00faee 6e67
-00faef 7a69
-00faf0 0065 .db "recognize",0
-00faf1 fadd .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-00faf2 f001 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-00faf3 f046 .dw XT_DOLITERAL
-00faf4 fafd .dw XT_RECOGNIZE_A
-00faf5 f0d6 .dw XT_SWAP
-00faf6 041b .dw XT_MAPSTACK
-00faf7 f12c .dw XT_ZEROEQUAL
-00faf8 f03f .dw XT_DOCONDBRANCH
-00faf9 fafc DEST(PFA_RECOGNIZE1)
-00fafa f589 .dw XT_2DROP
-00fafb fb65 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-00fafc f026 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-00fafd f001 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-00fafe f0f3 .dw XT_ROT ; -- len xt addr
-00faff f0f3 .dw XT_ROT ; -- xt addr len
-00fb00 f580 .dw XT_2DUP
-00fb01 f330 .dw XT_2TO_R
-00fb02 f0f3 .dw XT_ROT ; -- addr len xt
-00fb03 f030 .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-00fb04 f33f .dw XT_2R_FROM
-00fb05 f0f3 .dw XT_ROT
-00fb06 f0c3 .dw XT_DUP
-00fb07 fb65 .dw XT_DT_NULL
-00fb08 fd9a .dw XT_EQUAL
-00fb09 f03f .dw XT_DOCONDBRANCH
-00fb0a fb0e DEST(PFA_RECOGNIZE_A1)
-00fb0b f0eb .dw XT_DROP
-00fb0c f166 .dw XT_ZERO
-00fb0d f026 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-00fb0e f102 .dw XT_NIP
-00fb0f f102 .dw XT_NIP
-00fb10 f15d .dw XT_TRUE
-00fb11 f026 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-00fb12 ff06 .dw $ff06
-00fb13 7464
-00fb14 6e3a
-00fb15 6d75 .db "dt:num"
-00fb16 faeb .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-00fb17 f061 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-00fb18 fb9a .dw XT_NOOP ; interpret
-00fb19 01f1 .dw XT_LITERAL ; compile
-00fb1a 01f1 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-00fb1b ff07 .dw $ff07
-00fb1c 7464
-00fb1d 643a
-00fb1e 756e
-00fb1f 006d .db "dt:dnum",0
-00fb20 fb12 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-00fb21 f061 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-00fb22 fb9a .dw XT_NOOP ; interpret
-00fb23 fd92 .dw XT_2LITERAL ; compile
-00fb24 fd92 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-00fb25 ff07 .dw $ff07
-00fb26 6572
-00fb27 3a63
-00fb28 756e
-00fb29 006d .db "rec:num",0
-00fb2a fb1b .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-00fb2b f001 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-00fb2c f90f .dw XT_NUMBER
-00fb2d f03f .dw XT_DOCONDBRANCH
-00fb2e fb37 DEST(PFA_REC_NONUMBER)
-00fb2f fda1 .dw XT_ONE
-00fb30 fd9a .dw XT_EQUAL
-00fb31 f03f .dw XT_DOCONDBRANCH
-00fb32 fb35 DEST(PFA_REC_INTNUM2)
-00fb33 fb17 .dw XT_DT_NUM
-00fb34 f026 .dw XT_EXIT
- PFA_REC_INTNUM2:
-00fb35 fb21 .dw XT_DT_DNUM
-00fb36 f026 .dw XT_EXIT
- PFA_REC_NONUMBER:
-00fb37 fb65 .dw XT_DT_NULL
-00fb38 f026 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00fb39 ff08 .dw $ff08
-00fb3a 6572
-00fb3b 3a63
-00fb3c 6966
-00fb3d 646e .db "rec:find"
-00fb3e fb25 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-00fb3f f001 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-00fb40 f9eb .DW XT_FINDXT
-00fb41 f0c3 .dw XT_DUP
-00fb42 f12c .dw XT_ZEROEQUAL
-00fb43 f03f .dw XT_DOCONDBRANCH
-00fb44 fb48 DEST(PFA_REC_WORD_FOUND)
-00fb45 f0eb .dw XT_DROP
-00fb46 fb65 .dw XT_DT_NULL
-00fb47 f026 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-00fb48 fb4f .dw XT_DT_XT
-
-00fb49 f026 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-00fb4a ff05 .dw $ff05
-00fb4b 7464
-00fb4c 783a
-00fb4d 0074 .db "dt:xt",0
-00fb4e fb39 .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-00fb4f f061 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-00fb50 fb53 .dw XT_R_WORD_INTERPRET
-00fb51 fb57 .dw XT_R_WORD_COMPILE
-00fb52 fd92 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-00fb53 f001 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-00fb54 f0eb .dw XT_DROP ; the flags are in the way
-00fb55 f030 .dw XT_EXECUTE
-00fb56 f026 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-00fb57 f001 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-00fb58 f133 .dw XT_ZEROLESS
-00fb59 f03f .dw XT_DOCONDBRANCH
-00fb5a fb5d DEST(PFA_R_WORD_COMPILE1)
-00fb5b 01db .dw XT_COMMA
-00fb5c f026 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-00fb5d f030 .dw XT_EXECUTE
-00fb5e f026 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-00fb5f ff07 .dw $ff07
-00fb60 7464
-00fb61 6e3a
-00fb62 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-00fb63 006c .db "dt:null"
-00fb64 fb4a .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-00fb65 f061 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-00fb66 fb69 .dw XT_FAIL ; interpret
-00fb67 fb69 .dw XT_FAIL ; compile
-00fb68 fb69 .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00fb69 f001 .dw DO_COLON
- PFA_FAIL:
- .endif
-00fb6a f046 .dw XT_DOLITERAL
-00fb6b fff3 .dw -13
-00fb6c f85c .dw XT_THROW
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-00fb6d ff06 .dw $ff06
-00fb6e 733f
-00fb6f 6174
-00fb70 6b63 .db "?stack"
-00fb71 fb5f .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-00fb72 f001 .dw DO_COLON
- PFA_QSTACK:
- .endif
-00fb73 fabc .dw XT_DEPTH
-00fb74 f133 .dw XT_ZEROLESS
-00fb75 f03f .dw XT_DOCONDBRANCH
-00fb76 fb7a DEST(PFA_QSTACK1)
-00fb77 f046 .dw XT_DOLITERAL
-00fb78 fffc .dw -4
-00fb79 f85c .dw XT_THROW
- PFA_QSTACK1:
-00fb7a f026 .dw XT_EXIT
- .include "words/ver.asm"
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-00fb7b ff03 .dw $ff03
-00fb7c 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-00fb7d 0072 .db "ver"
-00fb7e fb6d .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00fb7f f001 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-00fb80 f528 .dw XT_ENV_FORTHNAME
-00fb81 f7bb .dw XT_ITYPE
-00fb82 f7fd .dw XT_SPACE
-00fb83 f56c .dw XT_BASE
-00fb84 f08b .dw XT_FETCH
-
-00fb85 f536 .dw XT_ENV_FORTHVERSION
-00fb86 f5f8 .dw XT_DECIMAL
-00fb87 fd82 .dw XT_S2D
-00fb88 f6d9 .dw XT_L_SHARP
-00fb89 f6e1 .dw XT_SHARP
-00fb8a f046 .dw XT_DOLITERAL
-00fb8b 002e .dw '.'
-00fb8c f6ca .dw XT_HOLD
-00fb8d f6f7 .dw XT_SHARP_S
-00fb8e f702 .dw XT_SHARP_G
-00fb8f f816 .dw XT_TYPE
-00fb90 f56c .dw XT_BASE
-00fb91 f093 .dw XT_STORE
-00fb92 f7fd .dw XT_SPACE
-00fb93 f53e .dw XT_ENV_CPU
-00fb94 f7bb .dw XT_ITYPE
-
-00fb95 f026 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-00fb96 ff04 .dw $ff04
-00fb97 6f6e
-00fb98 706f .db "noop"
-00fb99 fb7b .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-00fb9a f001 .dw DO_COLON
- PFA_NOOP:
- .endif
-00fb9b f026 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-00fb9c ff06 .dw $ff06
-00fb9d 6e75
-00fb9e 7375
-00fb9f 6465 .db "unused"
-00fba0 fb96 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-00fba1 f001 .dw DO_COLON
- PFA_UNUSED:
-00fba2 f29f .dw XT_SP_FETCH
-00fba3 f5da .dw XT_HERE
-00fba4 f1a5 .dw XT_MINUS
-00fba5 f026 .dw XT_EXIT
-
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-00fba6 0002 .dw $0002
-00fba7 6f74 .db "to"
-00fba8 fb9c .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-00fba9 f001 .dw DO_COLON
- PFA_TO:
- .endif
-00fbaa f825 .dw XT_TICK
-00fbab fd8b .dw XT_TO_BODY
-00fbac f566 .dw XT_STATE
-00fbad f08b .dw XT_FETCH
-00fbae f03f .dw XT_DOCONDBRANCH
-00fbaf fbba DEST(PFA_TO1)
-00fbb0 01d0 .dw XT_COMPILE
-00fbb1 fbb4 .dw XT_DOTO
-00fbb2 01db .dw XT_COMMA
-00fbb3 f026 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-00fbb4 f001 .dw DO_COLON
- PFA_DOTO:
- .endif
-00fbb5 f108 .dw XT_R_FROM
-00fbb6 f0c3 .dw XT_DUP
-00fbb7 fbc6 .dw XT_ICELLPLUS
-00fbb8 f111 .dw XT_TO_R
-00fbb9 f3e3 .dw XT_FETCHI
- PFA_TO1:
-00fbba f0c3 .dw XT_DUP
-00fbbb fbc6 .dw XT_ICELLPLUS
-00fbbc fbc6 .dw XT_ICELLPLUS
-00fbbd f3e3 .dw XT_FETCHI
-00fbbe f030 .dw XT_EXECUTE
-00fbbf f026 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-00fbc0 ff07 .dw $FF07
-00fbc1 2d69
-00fbc2 6563
-00fbc3 6c6c
-00fbc4 002b .db "i-cell+",0
-00fbc5 fba6 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-00fbc6 f001 .dw DO_COLON
- PFA_ICELLPLUS:
-00fbc7 f241 .dw XT_1PLUS
-00fbc8 f026 .dw XT_EXIT
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-00fbc9 ff07 .dw $ff07
-00fbca 6445
-00fbcb 6665
-00fbcc 7265
-00fbcd 0040 .db "Edefer@",0
-00fbce fbc0 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-00fbcf f001 .dw DO_COLON
- PFA_EDEFERFETCH:
-00fbd0 f3e3 .dw XT_FETCHI
-00fbd1 f371 .dw XT_FETCHE
-00fbd2 f026 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-00fbd3 ff07 .dw $ff07
-00fbd4 6445
-00fbd5 6665
-00fbd6 7265
-00fbd7 0021 .db "Edefer!",0
-00fbd8 fbc9 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-00fbd9 f001 .dw DO_COLON
- PFA_EDEFERSTORE:
-00fbda f3e3 .dw XT_FETCHI
-00fbdb f34d .dw XT_STOREE
-00fbdc f026 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-00fbdd ff07 .dw $ff07
-00fbde 6452
-00fbdf 6665
-00fbe0 7265
-00fbe1 0040 .db "Rdefer@",0
-00fbe2 fbd3 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-00fbe3 f001 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-00fbe4 f3e3 .dw XT_FETCHI
-00fbe5 f08b .dw XT_FETCH
-00fbe6 f026 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-00fbe7 ff07 .dw $ff07
-00fbe8 6452
-00fbe9 6665
-00fbea 7265
-00fbeb 0021 .db "Rdefer!",0
-00fbec fbdd .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-00fbed f001 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-00fbee f3e3 .dw XT_FETCHI
-00fbef f093 .dw XT_STORE
-00fbf0 f026 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-00fbf1 ff07 .dw $ff07
-00fbf2 6455
-00fbf3 6665
-00fbf4 7265
-00fbf5 0040 .db "Udefer@",0
-00fbf6 fbe7 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-00fbf7 f001 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-00fbf8 f3e3 .dw XT_FETCHI
-00fbf9 f314 .dw XT_UP_FETCH
-00fbfa f1af .dw XT_PLUS
-00fbfb f08b .dw XT_FETCH
-00fbfc f026 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-00fbfd ff07 .dw $ff07
-00fbfe 6455
-00fbff 6665
-00fc00 7265
-00fc01 0021 .db "Udefer!",0
-00fc02 fbf1 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-00fc03 f001 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-00fc04 f3e3 .dw XT_FETCHI
-00fc05 f314 .dw XT_UP_FETCH
-00fc06 f1af .dw XT_PLUS
-00fc07 f093 .dw XT_STORE
-00fc08 f026 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-00fc09 ff06 .dw $ff06
-00fc0a 6564
-00fc0b 6566
-00fc0c 2172 .db "defer!"
-00fc0d fbfd .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-00fc0e f001 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-00fc0f fd8b .dw XT_TO_BODY
-00fc10 f0c3 .dw XT_DUP
-00fc11 fbc6 .dw XT_ICELLPLUS
-00fc12 fbc6 .dw XT_ICELLPLUS
-00fc13 f3e3 .dw XT_FETCHI
-00fc14 f030 .dw XT_EXECUTE
-00fc15 f026 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-00fc16 ff06 .dw $ff06
-00fc17 6564
-00fc18 6566
-00fc19 4072 .db "defer@"
-00fc1a fc09 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-00fc1b f001 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-00fc1c fd8b .dw XT_TO_BODY
-00fc1d f0c3 .dw XT_DUP
-00fc1e fbc6 .dw XT_ICELLPLUS
-00fc1f f3e3 .dw XT_FETCHI
-00fc20 f030 .dw XT_EXECUTE
-00fc21 f026 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-00fc22 ff07 .dw $ff07
-00fc23 6428
-00fc24 6665
-00fc25 7265
-00fc26 0029 .db "(defer)", 0
-00fc27 fc16 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-00fc28 f001 .dw DO_COLON
- PFA_DODEFER:
-00fc29 01ad .dw XT_DOCREATE
-00fc2a 030d .dw XT_REVEAL
-00fc2b 01d0 .dw XT_COMPILE
-00fc2c fc2e .dw PFA_DODEFER1
-00fc2d f026 .dw XT_EXIT
- PFA_DODEFER1:
-00fc2e 940e 0326 call_ DO_DODOES
-00fc30 f0c3 .dw XT_DUP
-00fc31 fbc6 .dw XT_ICELLPLUS
-00fc32 f3e3 .dw XT_FETCHI
-00fc33 f030 .dw XT_EXECUTE
-00fc34 f030 .dw XT_EXECUTE
-00fc35 f026 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-00fc36 ff0f .dw $ff0f
-00fc37 6573
-00fc38 7261
-00fc39 6863
-00fc3a 772d
-00fc3b 726f
-00fc3c 6c64
-00fc3d 7369
-00fc3e 0074 .db "search-wordlist",0
-00fc3f fc22 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00fc40 f001 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-00fc41 f111 .dw XT_TO_R
-00fc42 f166 .dw XT_ZERO
-00fc43 f046 .dw XT_DOLITERAL
-00fc44 fc55 .dw XT_ISWORD
-00fc45 f108 .dw XT_R_FROM
-00fc46 fc72 .dw XT_TRAVERSEWORDLIST
-00fc47 f0c3 .dw XT_DUP
-00fc48 f12c .dw XT_ZEROEQUAL
-00fc49 f03f .dw XT_DOCONDBRANCH
-00fc4a fc4f DEST(PFA_SEARCH_WORDLIST1)
-00fc4b f589 .dw XT_2DROP
-00fc4c f0eb .dw XT_DROP
-00fc4d f166 .dw XT_ZERO
-00fc4e f026 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-00fc4f f0c3 .dw XT_DUP
-00fc50 fc99 .dw XT_NFA2CFA
- ; .. and get the header flag
-00fc51 f0d6 .dw XT_SWAP
-00fc52 0193 .dw XT_NAME2FLAGS
-00fc53 0181 .dw XT_IMMEDIATEQ
-00fc54 f026 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-00fc55 f001 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-00fc56 f111 .dw XT_TO_R
-00fc57 f0eb .dw XT_DROP
-00fc58 f580 .dw XT_2DUP
-00fc59 f11a .dw XT_R_FETCH ; -- addr len addr len nt
-00fc5a fc8d .dw XT_NAME2STRING
-00fc5b fca3 .dw XT_ICOMPARE ; (-- addr len f )
-00fc5c f03f .dw XT_DOCONDBRANCH
-00fc5d fc63 DEST(PFA_ISWORD3)
- ; not now
-00fc5e f108 .dw XT_R_FROM
-00fc5f f0eb .dw XT_DROP
-00fc60 f166 .dw XT_ZERO
-00fc61 f15d .dw XT_TRUE ; maybe next word
-00fc62 f026 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-00fc63 f589 .dw XT_2DROP
-00fc64 f108 .dw XT_R_FROM
-00fc65 f166 .dw XT_ZERO ; finish traverse-wordlist
-00fc66 f026 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-00fc67 ff11 .dw $ff11
-00fc68 7274
-00fc69 7661
-00fc6a 7265
-00fc6b 6573
-00fc6c 772d
-00fc6d 726f
-00fc6e 6c64
-00fc6f 7369
-00fc70 0074 .db "traverse-wordlist",0
-00fc71 fc36 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-00fc72 f001 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-00fc73 f371 .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-00fc74 f0c3 .dw XT_DUP ; ( -- xt nt nt )
-00fc75 f03f .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-00fc76 fc83 DEST(PFA_TRAVERSEWORDLIST2)
-00fc77 f580 .dw XT_2DUP
-00fc78 f330 .dw XT_2TO_R
-00fc79 f0d6 .dw XT_SWAP
-00fc7a f030 .dw XT_EXECUTE
-00fc7b f33f .dw XT_2R_FROM
-00fc7c f0f3 .dw XT_ROT
-00fc7d f03f .dw XT_DOCONDBRANCH
-00fc7e fc83 DEST(PFA_TRAVERSEWORDLIST2)
-00fc7f 048a .dw XT_NFA2LFA
-00fc80 f3e3 .dw XT_FETCHI
-00fc81 f035 .dw XT_DOBRANCH ; ( -- addr )
-00fc82 fc74 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-00fc83 f589 .dw XT_2DROP
-00fc84 f026 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-00fc85 ff0b .dw $ff0b
-00fc86 616e
-00fc87 656d
-00fc88 733e
-00fc89 7274
-00fc8a 6e69
-00fc8b 0067 .db "name>string",0
-00fc8c fc67 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-00fc8d f001 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-00fc8e f7e7 .dw XT_ICOUNT ; ( -- addr n )
-00fc8f f046 .dw XT_DOLITERAL
-00fc90 00ff .dw 255
-00fc91 f225 .dw XT_AND ; mask immediate bit
-00fc92 f026 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-00fc93 ff07 .dw $ff07
-00fc94 666e
-00fc95 3e61
-00fc96 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-00fc97 0061 .db "nfa>cfa"
-00fc98 fc85 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-00fc99 f001 .dw DO_COLON
- PFA_NFA2CFA:
-00fc9a 048a .dw XT_NFA2LFA ; skip to link field
-00fc9b f241 .dw XT_1PLUS ; next is the execution token
-00fc9c f026 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-00fc9d ff08 .dw $ff08
-00fc9e 6369
-00fc9f 6d6f
-00fca0 6170
-00fca1 6572 .db "icompare"
-00fca2 fc93 .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-00fca3 f001 .dw DO_COLON
- PFA_ICOMPARE:
-00fca4 f111 .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-00fca5 f0e1 .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-00fca6 f108 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-00fca7 f125 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-00fca8 f03f .dw XT_DOCONDBRANCH
-00fca9 fcae .dw PFA_ICOMPARE_SAMELEN
-00fcaa f589 .dw XT_2DROP
-00fcab f0eb .dw XT_DROP
-00fcac f15d .dw XT_TRUE
-00fcad f026 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-00fcae f0d6 .dw XT_SWAP ; ( -- r-addr f-addr len )
-00fcaf f166 .dw XT_ZERO
-00fcb0 029a .dw XT_QDOCHECK
-00fcb1 f03f .dw XT_DOCONDBRANCH
-00fcb2 fcd1 .dw PFA_ICOMPARE_DONE
-00fcb3 f2ad .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-00fcb4 f0e1 .dw XT_OVER
-00fcb5 f08b .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-00fcb6 f0e1 .dw XT_OVER
-00fcb7 f3e3 .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-00fcb8 f0c3 .dw XT_DUP
- ;.dw XT_BYTESWAP
-00fcb9 f046 .dw XT_DOLITERAL
-00fcba 0100 .dw $100
-00fcbb f16e .dw XT_ULESS
-00fcbc f03f .dw XT_DOCONDBRANCH
-00fcbd fcc2 .dw PFA_ICOMPARE_LASTCELL
-00fcbe f0d6 .dw XT_SWAP
-00fcbf f046 .dw XT_DOLITERAL
-00fcc0 00ff .dw $00FF
-00fcc1 f225 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-00fcc2 f125 .dw XT_NOTEQUAL
-00fcc3 f03f .dw XT_DOCONDBRANCH
-00fcc4 fcc9 .dw PFA_ICOMPARE_NEXTLOOP
-00fcc5 f589 .dw XT_2DROP
-00fcc6 f15d .dw XT_TRUE
-00fcc7 f2e6 .dw XT_UNLOOP
-00fcc8 f026 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-00fcc9 f241 .dw XT_1PLUS
-00fcca f0d6 .dw XT_SWAP
-00fccb f579 .dw XT_CELLPLUS
-00fccc f0d6 .dw XT_SWAP
-00fccd f046 .dw XT_DOLITERAL
-00fcce 0002 .dw 2
-00fccf f2cc .dw XT_DOPLUSLOOP
-00fcd0 fcb4 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-00fcd1 f589 .dw XT_2DROP
-00fcd2 f166 .dw XT_ZERO
-00fcd3 f026 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
-
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-00fcd4 ff01 .dw $ff01
-00fcd5 002a .db "*",0
-00fcd6 fc9d .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-00fcd7 f001 .dw DO_COLON
- PFA_STAR:
- .endif
-
-00fcd8 f1b8 .dw XT_MSTAR
-00fcd9 f0eb .dw XT_DROP
-00fcda f026 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-00fcdb ff01 .dw $FF01
-00fcdc 006a .db "j",0
-00fcdd fcd4 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-00fcde f001 .dw DO_COLON
- PFA_J:
-00fcdf f288 .dw XT_RP_FETCH
-00fce0 f046 .dw XT_DOLITERAL
-00fce1 0007 .dw 7
-00fce2 f1af .dw XT_PLUS
-00fce3 f08b .dw XT_FETCH
-00fce4 f288 .dw XT_RP_FETCH
-00fce5 f046 .dw XT_DOLITERAL
-00fce6 0009 .dw 9
-00fce7 f1af .dw XT_PLUS
-00fce8 f08b .dw XT_FETCH
-00fce9 f1af .dw XT_PLUS
-00fcea f026 .dw XT_EXIT
-
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-00fceb ff04 .dw $ff04
-00fcec 6164
-00fced 7362 .db "dabs"
-00fcee fcdb .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-00fcef f001 .dw DO_COLON
- PFA_DABS:
-00fcf0 f0c3 .dw XT_DUP
-00fcf1 f133 .dw XT_ZEROLESS
-00fcf2 f03f .dw XT_DOCONDBRANCH
-00fcf3 fcf5 .dw PFA_DABS1
-00fcf4 fcfc .dw XT_DNEGATE
- PFA_DABS1:
-00fcf5 f026 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-00fcf6 ff07 .dw $ff07
-00fcf7 6e64
-00fcf8 6765
-00fcf9 7461
-00fcfa 0065 .db "dnegate",0
-00fcfb fceb .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-00fcfc f001 .dw DO_COLON
- PFA_DNEGATE:
-00fcfd f456 .dw XT_DINVERT
-00fcfe fda1 .dw XT_ONE
-00fcff f166 .dw XT_ZERO
-00fd00 f430 .dw XT_DPLUS
-00fd01 f026 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-00fd02 ff05 .dw $ff05
-00fd03 6d63
-00fd04 766f
-00fd05 0065 .db "cmove",0
-00fd06 fcf6 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-00fd07 fd08 .dw PFA_CMOVE
- PFA_CMOVE:
-00fd08 93bf push xh
-00fd09 93af push xl
-00fd0a 91e9 ld zl, Y+
-00fd0b 91f9 ld zh, Y+ ; addr-to
-00fd0c 91a9 ld xl, Y+
-00fd0d 91b9 ld xh, Y+ ; addr-from
-00fd0e 2f09 mov temp0, tosh
-00fd0f 2b08 or temp0, tosl
-00fd10 f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00fd11 911d ld temp1, X+
-00fd12 9311 st Z+, temp1
-00fd13 9701 sbiw tosl, 1
-00fd14 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-00fd15 91af pop xl
-00fd16 91bf pop xh
-00fd17 9189
-00fd18 9199 loadtos
-00fd19 940c f005 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-00fd1b ff05 .dw $ff05
-00fd1c 7332
-00fd1d 6177
-00fd1e 0070 .db "2swap",0
-00fd1f fd02 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00fd20 f001 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00fd21 f0f3 .dw XT_ROT
-00fd22 f111 .dw XT_TO_R
-00fd23 f0f3 .dw XT_ROT
-00fd24 f108 .dw XT_R_FROM
-00fd25 f026 .dw XT_EXIT
-
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-00fd26 ff0a .dw $ff0a
-00fd27 6572
-00fd28 6966
-00fd29 6c6c
-00fd2a 742d
-00fd2b 6269 .db "refill-tib"
-00fd2c fd1b .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-00fd2d f001 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-00fd2e fd49 .dw XT_TIB
-00fd2f f046 .dw XT_DOLITERAL
-00fd30 005a .dw TIB_SIZE
-00fd31 f8ac .dw XT_ACCEPT
-00fd32 fd4f .dw XT_NUMBERTIB
-00fd33 f093 .dw XT_STORE
-00fd34 f166 .dw XT_ZERO
-00fd35 f599 .dw XT_TO_IN
-00fd36 f093 .dw XT_STORE
-00fd37 f15d .dw XT_TRUE ; -1
-00fd38 f026 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-00fd39 ff0a .dw $FF0A
-00fd3a 6f73
-00fd3b 7275
-00fd3c 6563
-00fd3d 742d
-00fd3e 6269 .db "source-tib"
-00fd3f fd26 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00fd40 f001 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00fd41 fd49 .dw XT_TIB
-00fd42 fd4f .dw XT_NUMBERTIB
-00fd43 f08b .dw XT_FETCH
-00fd44 f026 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-00fd45 ff03 .dw $ff03
-00fd46 6974
-00fd47 0062 .db "tib",0
-00fd48 fd39 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-00fd49 f054 .dw PFA_DOVARIABLE
- PFA_TIB:
-00fd4a 016f .dw ram_tib
- .dseg
-00016f ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-00fd4b ff04 .dw $ff04
-00fd4c 7423
-00fd4d 6269 .db "#tib"
-00fd4e fd45 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00fd4f f054 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00fd50 01c9 .dw ram_sharptib
- .dseg
-0001c9 ram_sharptib: .byte 2
- .cseg
- .endif
-
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00fd51 ff06 .dw $ff06
-00fd52 6565
-00fd53 723e
-00fd54 6d61 .db "ee>ram"
-00fd55 fd4b .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-00fd56 f001 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-00fd57 f166 .dw XT_ZERO
-00fd58 f2ad .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-00fd59 f0e1 .dw XT_OVER
-00fd5a f371 .dw XT_FETCHE
-00fd5b f0e1 .dw XT_OVER
-00fd5c f093 .dw XT_STORE
-00fd5d f579 .dw XT_CELLPLUS
-00fd5e f0d6 .dw XT_SWAP
-00fd5f f579 .dw XT_CELLPLUS
-00fd60 f0d6 .dw XT_SWAP
-00fd61 f2db .dw XT_DOLOOP
-00fd62 fd59 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00fd63 f589 .dw XT_2DROP
-00fd64 f026 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-00fd65 ff08 .dw $ff08
-00fd66 6e69
-00fd67 7469
-00fd68 722d
-00fd69 6d61 .db "init-ram"
-00fd6a fd51 .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-00fd6b f001 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-00fd6c f046 .dw XT_DOLITERAL
-00fd6d 007c .dw EE_INITUSER
-00fd6e f314 .dw XT_UP_FETCH
-00fd6f f046 .dw XT_DOLITERAL
-00fd70 0022 .dw SYSUSERSIZE
-00fd71 f216 .dw XT_2SLASH
-00fd72 fd56 .dw XT_EE2RAM
-00fd73 f026 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .endif
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-00fd74 ff06 .dw $ff06
-00fd75 6f62
-00fd76 6e75
-00fd77 7364 .db "bounds"
-00fd78 fd65 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-00fd79 f001 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-00fd7a f0e1 .dw XT_OVER
-00fd7b f1af .dw XT_PLUS
-00fd7c f0d6 .dw XT_SWAP
-00fd7d f026 .dw XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-00fd7e ff03 .dw $ff03
-00fd7f 3e73
-00fd80 0064 .db "s>d",0
-00fd81 fd74 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-00fd82 f001 .dw DO_COLON
- PFA_S2D:
- .endif
-00fd83 f0c3 .dw XT_DUP
-00fd84 f133 .dw XT_ZEROLESS
-00fd85 f026 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-00fd86 ff05 .dw $ff05
-00fd87 623e
-00fd88 646f
-00fd89 0079 .db ">body",0
-00fd8a fd7e .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-00fd8b f242 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>4000
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-00fd8c 0008 .dw $0008
-00fd8d 6c32
-00fd8e 7469
-00fd8f 7265
-00fd90 6c61 .db "2literal"
-00fd91 fd86 .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-00fd92 f001 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-00fd93 f0d6 .dw XT_SWAP
-00fd94 01f1 .dw XT_LITERAL
-00fd95 01f1 .dw XT_LITERAL
-00fd96 f026 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-00fd97 ff01 .dw $ff01
-00fd98 003d .db "=",0
-00fd99 fd8c .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-00fd9a f001 .dw DO_COLON
- PFA_EQUAL:
-00fd9b f1a5 .dw XT_MINUS
-00fd9c f12c .dw XT_ZEROEQUAL
-00fd9d f026 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-00fd9e ff01 .dw $ff01
-00fd9f 0031 .db "1",0
-00fda0 fd97 .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-00fda1 f054 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-00fda2 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-00fda3 ff01 .dw $ff01
-00fda4 0032 .db "2",0
-00fda5 fd9e .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-00fda6 f054 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-00fda7 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-00fda8 ff02 .dw $ff02
-00fda9 312d .db "-1"
-00fdaa fda3 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-00fdab f054 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-00fdac ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000046 ff ff
- ; some configs
-000048 9a 05 CFG_DP: .dw DPSTART ; Dictionary Pointer
-00004a cb 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00004c a0 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00004e 42 04 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-000050 6e 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000052 b0 40 CFG_LP0: .dw stackstart+1
-000054 ec 04 CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000056 4d f5 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000058 5a 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-00005a a8 fd CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00005c 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00005e 5a 00 .dw CFG_FORTHWORDLIST ; get/set-order
-000060 .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00006e 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-000070 3f fb .dw XT_REC_FIND
-000072 2b fb .dw XT_REC_NUM
-000074 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-000078 90 f3 .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-00007a 7a 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00007c 00 00 .dw 0 ; USER_STATE
-00007e 00 00 .dw 0 ; USER_FOLLOWER
-000080 ff 40 .dw rstackstart ; USER_RP
-000082 af 40 .dw stackstart ; USER_SP0
-000084 af 40 .dw stackstart ; USER_SP
-
-000086 00 00 .dw 0 ; USER_HANDLER
-000088 0a 00 .dw 10 ; USER_BASE
-
-00008a b6 00 .dw XT_TX ; USER_EMIT
-00008c c4 00 .dw XT_TXQ ; USER_EMITQ
-00008e 8b 00 .dw XT_RX ; USER_KEY
-000090 a6 00 .dw XT_RXQ ; USER_KEYQ
-000092 40 fd .dw XT_SOURCETIB ; USER_SOURCE
-000094 00 00 .dw 0 ; USER_G_IN
-000096 2d fd .dw XT_REFILLTIB ; USER_REFILL
-000098 05 fa .dw XT_DEFAULT_PROMPTOK
-00009a 24 fa .dw XT_DEFAULT_PROMPTERROR
-00009c 14 fa .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-00009e 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega1284P" register use summary:
-r0 : 25 r1 : 5 r2 : 10 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 89 r17: 61 r18: 61 r19: 37 r20: 13 r21: 38 r22: 11 r23: 3
-r24: 212 r25: 145 r26: 28 r27: 17 r28: 7 r29: 4 r30: 90 r31: 49
-x : 4 y : 217 z : 50
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega1284P" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 22 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 1
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 23 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 elpm : 16 eor : 3 fmul : 0
-fmuls : 0 fmulsu: 0 icall : 0 ijmp : 1 in : 25 inc : 3
-jmp : 14 ld : 145 ldd : 4 ldi : 41 lds : 1 lpm : 0
-lsl : 14 lsr : 2 mov : 16 movw : 72 mul : 5 muls : 1
-mulsu : 2 neg : 0 nop : 0 or : 9 ori : 2 out : 31
-pop : 49 push : 43 rcall : 48 ret : 7 reti : 1 rjmp : 105
-rol : 32 ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3
-sbis : 0 sbiw : 16 sbr : 0 sbrc : 5 sbrs : 7 sec : 1
-seh : 0 sei : 1 sen : 0 ser : 4 ses : 0 set : 0
-sev : 0 sez : 0 sleep : 0 spm : 2 st : 81 std : 8
-sts : 1 sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-
-Instructions used: 72 out of 114 (63.2%)
-
-"ATmega1284P" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x01fb5a 2156 14646 16802 131072 12.8%
-[.dseg] 0x000100 0x0001cb 0 203 203 16384 1.2%
-[.eseg] 0x000000 0x0000a0 0 160 160 4096 3.9%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/eval-pollin/p1284-16.map b/amforth-6.5/appl/eval-pollin/p1284-16.map
deleted file mode 100644
index 81938c3..0000000
--- a/amforth-6.5/appl/eval-pollin/p1284-16.map
+++ /dev/null
@@ -1,2253 +0,0 @@
-
-AVRASM ver. 2.1.52 p1284-16.asm Sun Apr 30 20:10:15 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000097
-EQU SIGNATURE_002 00000005
-EQU UDR1 000000ce
-EQU UBRR1L 000000cc
-EQU UBRR1H 000000cd
-EQU UCSR1C 000000ca
-EQU UCSR1B 000000c9
-EQU UCSR1A 000000c8
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR3BL 0000009a
-EQU OCR3BH 0000009b
-EQU OCR3AL 00000098
-EQU OCR3AH 00000099
-EQU ICR3L 00000096
-EQU ICR3H 00000097
-EQU TCNT3L 00000094
-EQU TCNT3H 00000095
-EQU TCCR3C 00000092
-EQU TCCR3B 00000091
-EQU TCCR3A 00000090
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU PCMSK3 00000073
-EQU TIMSK3 00000071
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK2 0000006d
-EQU PCMSK1 0000006c
-EQU PCMSK0 0000006b
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR1 00000065
-EQU PRR0 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU RAMPZ 0000003b
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU OCDR 00000031
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR3 00000018
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU PORTA 00000002
-EQU DDRA 00000001
-EQU PINA 00000000
-EQU ACME 00000006
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSRSYNC 00000000
-EQU PSR10 00000000
-EQU TSM 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU PWM10 00000000
-EQU WGM11 00000001
-EQU PWM11 00000001
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU CTC1 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU TOIE3 00000000
-EQU OCIE3A 00000001
-EQU OCIE3B 00000002
-EQU ICIE3 00000005
-EQU TOV3 00000000
-EQU OCF3A 00000001
-EQU OCF3B 00000002
-EQU ICF3 00000005
-EQU WGM30 00000000
-EQU WGM31 00000001
-EQU COM3B0 00000004
-EQU COM3B1 00000005
-EQU COM3A0 00000006
-EQU COM3A1 00000007
-EQU CS30 00000000
-EQU CS31 00000001
-EQU CS32 00000002
-EQU WGM32 00000003
-EQU WGM33 00000004
-EQU ICES3 00000006
-EQU ICNC3 00000007
-EQU FOC3B 00000006
-EQU FOC3A 00000007
-EQU OCR3AH0 00000000
-EQU OCR3AH1 00000001
-EQU OCR3AH2 00000002
-EQU OCR3AH3 00000003
-EQU OCR3AH4 00000004
-EQU OCR3AH5 00000005
-EQU OCR3AH6 00000006
-EQU OCR3AH7 00000007
-EQU OCR3AL0 00000000
-EQU OCR3AL1 00000001
-EQU OCR3AL2 00000002
-EQU OCR3AL3 00000003
-EQU OCR3AL4 00000004
-EQU OCR3AL5 00000005
-EQU OCR3AL6 00000006
-EQU OCR3AL7 00000007
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU SIGRD 00000005
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC20 00000004
-EQU ISC21 00000005
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INT2 00000002
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU INTF2 00000002
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCIE3 00000003
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU PCIF3 00000003
-EQU PCINT24 00000000
-EQU PCINT25 00000001
-EQU PCINT26 00000002
-EQU PCINT27 00000003
-EQU PCINT28 00000004
-EQU PCINT29 00000005
-EQU PCINT30 00000006
-EQU PCINT31 00000007
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT15 00000007
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ADC6D 00000006
-EQU ADC7D 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU JTD 00000007
-EQU JTRF 00000004
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEAR10 00000002
-EQU EEAR11 00000003
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU UDR1_0 00000000
-EQU UDR1_1 00000001
-EQU UDR1_2 00000002
-EQU UDR1_3 00000003
-EQU UDR1_4 00000004
-EQU UDR1_5 00000005
-EQU UDR1_6 00000006
-EQU UDR1_7 00000007
-EQU MPCM1 00000000
-EQU U2X1 00000001
-EQU UPE1 00000002
-EQU DOR1 00000003
-EQU FE1 00000004
-EQU UDRE1 00000005
-EQU TXC1 00000006
-EQU RXC1 00000007
-EQU TXB81 00000000
-EQU RXB81 00000001
-EQU UCSZ12 00000002
-EQU TXEN1 00000003
-EQU RXEN1 00000004
-EQU UDRIE1 00000005
-EQU TXCIE1 00000006
-EQU RXCIE1 00000007
-EQU UCPOL1 00000000
-EQU UCSZ10 00000001
-EQU UCPHA1 00000001
-EQU UCSZ11 00000002
-EQU UDORD1 00000002
-EQU USBS1 00000003
-EQU UPM10 00000004
-EQU UPM11 00000005
-EQU UMSEL10 00000006
-EQU UMSEL11 00000007
-EQU UBRR_8 00000000
-EQU UBRR_9 00000001
-EQU UBRR_10 00000002
-EQU UBRR_11 00000003
-EQU UBRR_0 00000000
-EQU UBRR_1 00000001
-EQU UBRR_2 00000002
-EQU UBRR_3 00000003
-EQU UBRR_4 00000004
-EQU UBRR_5 00000005
-EQU UBRR_6 00000006
-EQU UBRR_7 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU BODSE 00000005
-EQU BODS 00000006
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU RAMPZ0 00000000
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRUSART1 00000004
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU PRTIM3 00000000
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 0000ffff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00004000
-EQU RAMEND 000040ff
-EQU XRAMEND 00000000
-EQU E2END 00000fff
-EQU EEPROMEND 00000fff
-EQU EEADRBITS 0000000c
-EQU NRWW_START_ADDR 0000f000
-EQU NRWW_STOP_ADDR 0000ffff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 0000efff
-EQU PAGESIZE 00000080
-EQU FIRSTBOOTSTART 0000fe00
-EQU SECONDBOOTSTART 0000fc00
-EQU THIRDBOOTSTART 0000f800
-EQU FOURTHBOOTSTART 0000f000
-EQU SMALLBOOTSTART 0000fe00
-EQU LARGEBOOTSTART 0000f000
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU PCI0addr 00000008
-EQU PCI1addr 0000000a
-EQU PCI2addr 0000000c
-EQU PCI3addr 0000000e
-EQU WDTaddr 00000010
-EQU OC2Aaddr 00000012
-EQU OC2Baddr 00000014
-EQU OVF2addr 00000016
-EQU ICP1addr 00000018
-EQU OC1Aaddr 0000001a
-EQU OC1Baddr 0000001c
-EQU OVF1addr 0000001e
-EQU OC0Aaddr 00000020
-EQU OC0Baddr 00000022
-EQU OVF0addr 00000024
-EQU SPIaddr 00000026
-EQU URXC0addr 00000028
-EQU UDRE0addr 0000002a
-EQU UTXC0addr 0000002c
-EQU ACIaddr 0000002e
-EQU ADCCaddr 00000030
-EQU ERDYaddr 00000032
-EQU TWIaddr 00000034
-EQU SPMRaddr 00000036
-EQU URXC1addr 00000038
-EQU UDRE1addr 0000003a
-EQU UTXC1addr 0000003c
-EQU ICP3addr 0000003e
-EQU OC3Aaddr 00000040
-EQU OC3Baddr 00000042
-EQU OVF3addr 00000044
-EQU INT_VECTORS_SIZE 00000046
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_USART0 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_TIMER_COUNTER_3 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_JTAG 00000000
-SET WANT_EEPROM 00000000
-SET WANT_TWI 00000000
-SET WANT_USART1 00000000
-SET WANT_SPI 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_CPU 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 0000013c
-EQU INTVECTORS 00000023
-CSEG mcu_info 00000045
-CSEG mcu_ramsize 00000045
-CSEG mcu_eepromsize 00000046
-CSEG mcu_maxdp 00000047
-CSEG mcu_numints 00000048
-CSEG mcu_name 00000049
-SET codestart 00000050
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000040ff
-SET stackstart 000040af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000001e
-SET VE_HEAD 0000fda8
-SET VE_ENVHEAD 0000f54d
-SET AMFORTH_RO_SEG 0000f001
-EQU F_CPU 00f42400
-EQU TIMER_INT 00000016
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU URXCaddr 00000028
-EQU UDREaddr 0000002a
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 00000050
-CSEG XT_TO_RXBUF 00000056
-CSEG PFA_rx_tobuf 00000057
-CSEG DO_NEXT 0000f005
-CSEG VE_ISR_RX 00000067
-CSEG XT_ISR_RX 0000006c
-CSEG DO_COLON 0000f001
-CSEG usart_rx_isr 0000006d
-CSEG XT_DOLITERAL 0000f046
-CSEG XT_CFETCH 0000f0aa
-CSEG XT_DUP 0000f0c3
-CSEG XT_EQUAL 0000fd9a
-CSEG XT_DOCONDBRANCH 0000f03f
-CSEG usart_rx_isr1 00000077
-CSEG XT_COLD 0000fa74
-CSEG XT_EXIT 0000f026
-CSEG XT_USART_INIT_RX_BUFFER 00000079
-CSEG PFA_USART_INIT_RX_BUFFER 0000007a
-CSEG XT_INTSTORE 0000f4a2
-CSEG XT_ZERO 0000f166
-CSEG XT_FILL 0000f4ea
-CSEG VE_RX_BUFFER 00000086
-CSEG XT_RX_BUFFER 0000008b
-CSEG PFA_RX_BUFFER 0000008c
-CSEG XT_RXQ_BUFFER 000000a6
-CSEG XT_PLUS 0000f1af
-CSEG XT_SWAP 0000f0d6
-CSEG XT_1PLUS 0000f241
-CSEG XT_AND 0000f225
-CSEG XT_CSTORE 0000f09f
-CSEG VE_RXQ_BUFFER 000000a0
-CSEG PFA_RXQ_BUFFER 000000a7
-CSEG XT_PAUSE 0000fa6c
-CSEG XT_NOTEQUAL 0000f125
-SET XT_RX 0000008b
-SET XT_RXQ 000000a6
-SET XT_USART_INIT_RX 00000079
-CSEG VE_TX_POLL 000000b0
-CSEG XT_TX_POLL 000000b6
-CSEG PFA_TX_POLL 000000b7
-CSEG XT_TXQ_POLL 000000c4
-CSEG VE_TXQ_POLL 000000be
-CSEG PFA_TXQ_POLL 000000c5
-SET XT_TX 000000b6
-SET XT_TXQ 000000c4
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000cd
-CSEG XT_UBRR 000000d1
-CSEG PFA_DOVALUE1 0000f081
-CSEG PFA_UBRR 000000d2
-ESEG EE_UBRRVAL 0000009e
-CSEG XT_EDEFERFETCH 0000fbcf
-CSEG XT_EDEFERSTORE 0000fbd9
-CSEG VE_USART 000000d5
-CSEG XT_USART 000000da
-CSEG PFA_USART 000000db
-CSEG XT_BYTESWAP 0000f30b
-EQU OW_PORT 00000005
-EQU OW_BIT 00000004
-SET OW_DDR 00000004
-SET OW_PIN 00000003
-CSEG VE_OW_RESET 000000f0
-CSEG XT_OW_RESET 000000f6
-CSEG PFA_OW_RESET 000000f7
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_OW_SLOT 00000114
-CSEG XT_OW_SLOT 0000011a
-CSEG PFA_OW_SLOT 0000011b
-CSEG PFA_OW_SLOT0 00000128
-SET AMFORTH_NRWW_SIZE 00001ffc
-SET corepc 0000013c
-CSEG PFA_COLD 0000fa75
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 00000153
-CSEG XT_MPLUS 00000156
-CSEG PFA_MPLUS 00000157
-CSEG XT_S2D 0000fd82
-CSEG XT_DPLUS 0000f430
-CSEG VE_UDSTAR 0000015a
-CSEG XT_UDSTAR 0000015e
-CSEG PFA_UDSTAR 0000015f
-CSEG XT_TO_R 0000f111
-CSEG XT_UMSTAR 0000f1f2
-CSEG XT_DROP 0000f0eb
-CSEG XT_R_FROM 0000f108
-CSEG XT_ROT 0000f0f3
-CSEG VE_UMAX 00000169
-CSEG XT_UMAX 0000016d
-CSEG PFA_UMAX 0000016e
-CSEG XT_2DUP 0000f580
-CSEG XT_ULESS 0000f16e
-CSEG UMAX1 00000173
-CSEG VE_UMIN 00000175
-CSEG XT_UMIN 00000179
-CSEG PFA_UMIN 0000017a
-CSEG XT_UGREATER 0000f179
-CSEG UMIN1 0000017f
-CSEG XT_IMMEDIATEQ 00000181
-CSEG PFA_IMMEDIATEQ 00000182
-CSEG XT_ZEROEQUAL 0000f12c
-CSEG IMMEDIATEQ1 0000018a
-CSEG XT_ONE 0000fda1
-CSEG XT_TRUE 0000f15d
-CSEG VE_NAME2FLAGS 0000018c
-CSEG XT_NAME2FLAGS 00000193
-CSEG PFA_NAME2FLAGS 00000194
-CSEG XT_FETCHI 0000f3e3
-CSEG VE_NEWEST 00000199
-CSEG XT_NEWEST 0000019e
-CSEG PFA_DOVARIABLE 0000f054
-CSEG PFA_NEWEST 0000019f
-DSEG ram_newest 00000135
-CSEG VE_LATEST 000001a0
-CSEG XT_LATEST 000001a5
-CSEG PFA_LATEST 000001a6
-DSEG ram_latest 00000139
-CSEG VE_DOCREATE 000001a7
-CSEG XT_DOCREATE 000001ad
-CSEG PFA_DOCREATE 000001ae
-CSEG XT_PARSENAME 0000f9cf
-CSEG XT_WLSCOPE 00000304
-CSEG XT_CELLPLUS 0000f579
-CSEG XT_STORE 0000f093
-CSEG XT_HEADER 000002e9
-CSEG VE_BACKSLASH 000001b8
-CSEG XT_BACKSLASH 000001bb
-CSEG PFA_BACKSLASH 000001bc
-CSEG XT_SOURCE 0000f9b6
-CSEG XT_NIP 0000f102
-CSEG XT_TO_IN 0000f599
-CSEG VE_LPAREN 000001c1
-CSEG XT_LPAREN 000001c4
-CSEG PFA_LPAREN 000001c5
-CSEG XT_PARSE 0000f9a2
-CSEG XT_2DROP 0000f589
-CSEG VE_COMPILE 000001ca
-CSEG XT_COMPILE 000001d0
-CSEG PFA_COMPILE 000001d1
-CSEG XT_ICELLPLUS 0000fbc6
-CSEG XT_COMMA 000001db
-CSEG VE_COMMA 000001d8
-CSEG PFA_COMMA 000001dc
-CSEG XT_DP 0000f5c9
-CSEG XT_STOREI 0000f385
-CSEG XT_DOTO 0000fbb4
-CSEG PFA_DP 0000f5ca
-CSEG VE_BRACKETTICK 000001e3
-CSEG XT_BRACKETTICK 000001e7
-CSEG PFA_BRACKETTICK 000001e8
-CSEG XT_TICK 0000f825
-CSEG XT_LITERAL 000001f1
-CSEG VE_LITERAL 000001eb
-CSEG PFA_LITERAL 000001f2
-CSEG VE_SLITERAL 000001f6
-CSEG XT_SLITERAL 000001fc
-CSEG PFA_SLITERAL 000001fd
-CSEG XT_DOSLITERAL 0000f788
-CSEG XT_SCOMMA 0000f796
-CSEG XT_GMARK 00000201
-CSEG PFA_GMARK 00000202
-CSEG XT_GRESOLVE 00000206
-CSEG PFA_GRESOLVE 00000207
-CSEG XT_QSTACK 0000fb72
-CSEG XT_LMARK 0000020c
-CSEG PFA_LMARK 0000020d
-CSEG XT_LRESOLVE 0000020f
-CSEG PFA_LRESOLVE 00000210
-CSEG VE_AHEAD 00000213
-CSEG XT_AHEAD 00000218
-CSEG PFA_AHEAD 00000219
-CSEG XT_DOBRANCH 0000f035
-CSEG VE_IF 0000021d
-CSEG XT_IF 00000220
-CSEG PFA_IF 00000221
-CSEG VE_ELSE 00000225
-CSEG XT_ELSE 00000229
-CSEG PFA_ELSE 0000022a
-CSEG VE_THEN 00000230
-CSEG XT_THEN 00000234
-CSEG PFA_THEN 00000235
-CSEG VE_BEGIN 00000237
-CSEG XT_BEGIN 0000023c
-CSEG PFA_BEGIN 0000023d
-CSEG VE_WHILE 0000023f
-CSEG XT_WHILE 00000244
-CSEG PFA_WHILE 00000245
-CSEG VE_REPEAT 00000248
-CSEG XT_REPEAT 0000024d
-CSEG PFA_REPEAT 0000024e
-CSEG XT_AGAIN 00000261
-CSEG VE_UNTIL 00000251
-CSEG XT_UNTIL 00000256
-CSEG PFA_UNTIL 00000257
-CSEG VE_AGAIN 0000025c
-CSEG PFA_AGAIN 00000262
-CSEG VE_DO 00000266
-CSEG XT_DO 00000269
-CSEG PFA_DO 0000026a
-CSEG XT_DODO 0000f2ad
-CSEG XT_TO_L 000002c4
-CSEG VE_LOOP 00000270
-CSEG XT_LOOP 00000274
-CSEG PFA_LOOP 00000275
-CSEG XT_DOLOOP 0000f2db
-CSEG XT_ENDLOOP 000002ab
-CSEG VE_PLUSLOOP 00000279
-CSEG XT_PLUSLOOP 0000027e
-CSEG PFA_PLUSLOOP 0000027f
-CSEG XT_DOPLUSLOOP 0000f2cc
-CSEG VE_LEAVE 00000283
-CSEG XT_LEAVE 00000288
-CSEG PFA_LEAVE 00000289
-CSEG XT_UNLOOP 0000f2e6
-CSEG VE_QDO 0000028e
-CSEG XT_QDO 00000292
-CSEG PFA_QDO 00000293
-CSEG XT_QDOCHECK 0000029a
-CSEG PFA_QDOCHECK 0000029b
-CSEG PFA_QDOCHECK1 000002a2
-CSEG XT_INVERT 0000f20f
-CSEG VE_ENDLOOP 000002a5
-CSEG PFA_ENDLOOP 000002ac
-CSEG LOOP1 000002ad
-CSEG XT_L_FROM 000002b8
-CSEG XT_QDUP 0000f0cb
-CSEG LOOP2 000002b4
-CSEG VE_L_FROM 000002b5
-CSEG PFA_L_FROM 000002b9
-CSEG XT_LP 000002d7
-CSEG XT_FETCH 0000f08b
-CSEG XT_PLUSSTORE 0000f277
-CSEG VE_TO_L 000002c1
-CSEG PFA_TO_L 000002c5
-CSEG XT_TWO 0000fda6
-CSEG VE_LP0 000002cc
-CSEG XT_LP0 000002d0
-CSEG PFA_LP0 000002d1
-ESEG CFG_LP0 00000052
-CSEG VE_LP 000002d4
-CSEG PFA_LP 000002d8
-DSEG ram_lp 0000013b
-CSEG VE_CREATE 000002d9
-CSEG XT_CREATE 000002de
-CSEG PFA_CREATE 000002df
-CSEG XT_REVEAL 0000030d
-CSEG PFA_DOCONSTANT 0000f061
-CSEG VE_HEADER 000002e4
-CSEG PFA_HEADER 000002ea
-CSEG XT_GREATERZERO 0000f13a
-CSEG PFA_HEADER1 000002fb
-CSEG XT_OR 0000f22e
-CSEG XT_DOSCOMMA 0000f79a
-CSEG XT_FETCHE 0000f371
-CSEG XT_THROW 0000f85c
-CSEG VE_WLSCOPE 000002fe
-CSEG PFA_DODEFER1 0000fc2e
-CSEG PFA_WLSCOPE 00000305
-ESEG CFG_WLSCOPE 0000004e
-CSEG VE_REVEAL 00000308
-CSEG PFA_REVEAL 0000030e
-CSEG REVEAL1 00000318
-CSEG XT_STOREE 0000f34d
-CSEG VE_DOES 00000319
-CSEG XT_DOES 0000031e
-CSEG PFA_DOES 0000031f
-CSEG XT_DODOES 00000331
-CSEG DO_DODOES 00000326
-CSEG PFA_DODOES 00000332
-CSEG XT_NFA2CFA 0000fc99
-CSEG VE_COLON 0000033a
-CSEG XT_COLON 0000033d
-CSEG PFA_COLON 0000033e
-CSEG XT_COLONNONAME 00000348
-CSEG VE_COLONNONAME 00000342
-CSEG PFA_COLONNONAME 00000349
-CSEG XT_RBRACKET 0000035d
-CSEG VE_SEMICOLON 00000351
-CSEG XT_SEMICOLON 00000354
-CSEG PFA_SEMICOLON 00000355
-CSEG XT_LBRACKET 00000365
-CSEG VE_RBRACKET 0000035a
-CSEG PFA_RBRACKET 0000035e
-CSEG XT_STATE 0000f566
-CSEG VE_LBRACKET 00000362
-CSEG PFA_LBRACKET 00000366
-CSEG VE_VARIABLE 0000036a
-CSEG XT_VARIABLE 00000370
-CSEG PFA_VARIABLE 00000371
-CSEG XT_HERE 0000f5da
-CSEG XT_CONSTANT 0000037c
-CSEG XT_ALLOT 0000f5e3
-CSEG VE_CONSTANT 00000376
-CSEG PFA_CONSTANT 0000037d
-CSEG VE_USER 00000383
-CSEG XT_USER 00000387
-CSEG PFA_USER 00000388
-CSEG PFA_DOUSER 0000f067
-CSEG VE_RECURSE 0000038e
-CSEG XT_RECURSE 00000394
-CSEG PFA_RECURSE 00000395
-CSEG VE_IMMEDIATE 00000399
-CSEG XT_IMMEDIATE 000003a0
-CSEG PFA_IMMEDIATE 000003a1
-CSEG XT_GET_CURRENT 00000442
-CSEG VE_BRACKETCHAR 000003ab
-CSEG XT_BRACKETCHAR 000003b0
-CSEG PFA_BRACKETCHAR 000003b1
-CSEG XT_CHAR 0000f905
-CSEG VE_ABORTQUOTE 000003b6
-CSEG XT_ABORTQUOTE 000003bb
-CSEG PFA_ABORTQUOTE 000003bc
-CSEG XT_SQUOTE 0000f4dc
-CSEG XT_QABORT 000003cd
-CSEG VE_ABORT 000003c0
-CSEG XT_ABORT 000003c5
-CSEG PFA_ABORT 000003c6
-CSEG VE_QABORT 000003c8
-CSEG PFA_QABORT 000003ce
-CSEG QABO1 000003d3
-CSEG XT_ITYPE 0000f7bb
-CSEG VE_GET_STACK 000003d5
-CSEG XT_GET_STACK 000003dc
-CSEG PFA_N_FETCH_E2 000003f3
-CSEG PFA_N_FETCH_E1 000003e9
-CSEG XT_I 0000f2be
-CSEG XT_1MINUS 0000f247
-CSEG XT_CELLS 0000f573
-CSEG XT_OVER 0000f0e1
-CSEG VE_SET_STACK 000003f6
-CSEG XT_SET_STACK 000003fd
-CSEG PFA_SET_STACK 000003fe
-CSEG XT_ZEROLESS 0000f133
-CSEG PFA_SET_STACK0 00000405
-CSEG PFA_SET_STACK2 00000412
-CSEG PFA_SET_STACK1 0000040d
-CSEG XT_TUCK 0000f591
-CSEG VE_MAPSTACK 00000414
-CSEG XT_MAPSTACK 0000041b
-CSEG PFA_MAPSTACK 0000041c
-CSEG XT_BOUNDS 0000fd79
-CSEG PFA_MAPSTACK3 00000437
-CSEG PFA_MAPSTACK1 00000426
-CSEG XT_R_FETCH 0000f11a
-CSEG XT_EXECUTE 0000f030
-CSEG PFA_MAPSTACK2 00000433
-CSEG VE_GET_CURRENT 0000043a
-CSEG PFA_GET_CURRENT 00000443
-ESEG CFG_CURRENT 00000058
-CSEG VE_GET_ORDER 00000447
-CSEG XT_GET_ORDER 0000044e
-CSEG PFA_GET_ORDER 0000044f
-ESEG CFG_ORDERLISTLEN 0000005c
-CSEG VE_CFG_ORDER 00000453
-CSEG XT_CFG_ORDER 0000045a
-CSEG PFA_CFG_ORDER 0000045b
-CSEG VE_COMPARE 0000045c
-CSEG XT_COMPARE 00000462
-CSEG PFA_COMPARE 00000463
-CSEG PFA_COMPARE_LOOP 0000046f
-CSEG PFA_COMPARE_NOTEQUAL 0000047d
-CSEG PFA_COMPARE_ENDREACHED2 00000478
-CSEG PFA_COMPARE_ENDREACHED 00000479
-CSEG PFA_COMPARE_CHECKLASTCHAR 0000047d
-CSEG PFA_COMPARE_DONE 0000047f
-CSEG VE_NFA2LFA 00000484
-CSEG XT_NFA2LFA 0000048a
-CSEG PFA_NFA2LFA 0000048b
-CSEG XT_NAME2STRING 0000fc8d
-CSEG XT_2SLASH 0000f216
-CSEG VE_DOTS 00000490
-CSEG XT_DOTS 00000493
-CSEG PFA_DOTS 00000494
-CSEG XT_DEPTH 0000fabc
-CSEG XT_UDOT 0000f463
-CSEG XT_SPACE 0000f7fd
-CSEG PFA_DOTS2 000004a2
-CSEG PFA_DOTS1 0000049d
-CSEG XT_PICK 0000f4ca
-CSEG VE_SPIRW 000004a3
-CSEG XT_SPIRW 000004a8
-CSEG PFA_SPIRW 000004a9
-CSEG do_spirw 000004ad
-CSEG do_spirw1 000004ae
-CSEG VE_N_SPIR 000004b6
-CSEG XT_N_SPIR 000004bb
-CSEG PFA_N_SPIR 000004bc
-CSEG PFA_N_SPIR_LOOP 000004c1
-CSEG PFA_N_SPIR_LOOP1 000004c2
-CSEG VE_N_SPIW 000004cd
-CSEG XT_N_SPIW 000004d2
-CSEG PFA_N_SPIW 000004d3
-CSEG PFA_N_SPIW_LOOP 000004d8
-CSEG PFA_N_SPIW_LOOP1 000004da
-CSEG VE_APPLTURNKEY 000004e4
-CSEG XT_APPLTURNKEY 000004ec
-CSEG PFA_APPLTURNKEY 000004ed
-CSEG XT_INTON 0000f494
-CSEG XT_DOT_VER 0000fb7f
-CSEG XT_F_CPU 0000f55b
-CSEG XT_UMSLASHMOD 0000f1d4
-CSEG XT_DECIMAL 0000f5f8
-CSEG XT_DOT 0000f73d
-CSEG VE_SET_CURRENT 000004fe
-CSEG XT_SET_CURRENT 00000506
-CSEG PFA_SET_CURRENT 00000507
-CSEG VE_WORDLIST 0000050b
-CSEG XT_WORDLIST 00000511
-CSEG PFA_WORDLIST 00000512
-CSEG XT_EHERE 0000f5d2
-CSEG PFA_EHERE 0000f5d3
-CSEG VE_FORTHWORDLIST 0000051b
-CSEG XT_FORTHWORDLIST 00000524
-CSEG PFA_FORTHWORDLIST 00000525
-ESEG CFG_FORTHWORDLIST 0000005a
-CSEG VE_SET_ORDER 00000526
-CSEG XT_SET_ORDER 0000052d
-CSEG PFA_SET_ORDER 0000052e
-CSEG VE_SET_RECOGNIZERS 00000532
-CSEG XT_SET_RECOGNIZERS 0000053c
-CSEG PFA_SET_RECOGNIZERS 0000053d
-ESEG CFG_RECOGNIZERLISTLEN 0000006e
-CSEG VE_GET_RECOGNIZERS 00000541
-CSEG XT_GET_RECOGNIZERS 0000054b
-CSEG PFA_GET_RECOGNIZERS 0000054c
-CSEG VE_CODE 00000550
-CSEG XT_CODE 00000554
-CSEG PFA_CODE 00000555
-CSEG VE_ENDCODE 0000055b
-CSEG XT_ENDCODE 00000561
-CSEG PFA_ENDCODE 00000562
-CSEG VE_MARKER 00000567
-CSEG XT_MARKER 0000056d
-CSEG PFA_MARKER 0000056e
-ESEG EE_MARKER 0000007a
-CSEG VE_POSTPONE 00000571
-CSEG XT_POSTPONE 00000577
-CSEG PFA_POSTPONE 00000578
-CSEG XT_FORTHRECOGNIZER 0000fae7
-CSEG XT_RECOGNIZE 0000faf2
-CSEG VE_2R_FETCH 00000586
-CSEG XT_2R_FETCH 0000058a
-CSEG PFA_2R_FETCH 0000058b
-SET DPSTART 0000059a
-CSEG DO_INTERRUPT 0000f01a
-CSEG DO_EXECUTE 0000f010
-CSEG XT_ISREXEC 0000f4bd
-CSEG VE_EXIT 0000f022
-CSEG PFA_EXIT 0000f027
-CSEG VE_EXECUTE 0000f02a
-CSEG PFA_EXECUTE 0000f031
-CSEG PFA_DOBRANCH 0000f036
-CSEG PFA_DOCONDBRANCH 0000f040
-CSEG PFA_DOLITERAL 0000f047
-CSEG XT_DOVARIABLE 0000f053
-CSEG XT_DOCONSTANT 0000f060
-CSEG XT_DOUSER 0000f066
-CSEG VE_DOVALUE 0000f075
-CSEG XT_DOVALUE 0000f07b
-CSEG PFA_DOVALUE 0000f07c
-CSEG VE_FETCH 0000f088
-CSEG PFA_FETCH 0000f08c
-CSEG PFA_FETCHRAM 0000f08c
-CSEG VE_STORE 0000f090
-CSEG PFA_STORE 0000f094
-CSEG PFA_STORERAM 0000f094
-CSEG VE_CSTORE 0000f09c
-CSEG PFA_CSTORE 0000f0a0
-CSEG VE_CFETCH 0000f0a7
-CSEG PFA_CFETCH 0000f0ab
-CSEG VE_FETCHU 0000f0af
-CSEG XT_FETCHU 0000f0b2
-CSEG PFA_FETCHU 0000f0b3
-CSEG XT_UP_FETCH 0000f314
-CSEG VE_STOREU 0000f0b7
-CSEG XT_STOREU 0000f0ba
-CSEG PFA_STOREU 0000f0bb
-CSEG VE_DUP 0000f0bf
-CSEG PFA_DUP 0000f0c4
-CSEG VE_QDUP 0000f0c7
-CSEG PFA_QDUP 0000f0cc
-CSEG PFA_QDUP1 0000f0d1
-CSEG VE_SWAP 0000f0d2
-CSEG PFA_SWAP 0000f0d7
-CSEG VE_OVER 0000f0dd
-CSEG PFA_OVER 0000f0e2
-CSEG VE_DROP 0000f0e7
-CSEG PFA_DROP 0000f0ec
-CSEG VE_ROT 0000f0ef
-CSEG PFA_ROT 0000f0f4
-CSEG VE_NIP 0000f0fe
-CSEG PFA_NIP 0000f103
-CSEG VE_R_FROM 0000f105
-CSEG PFA_R_FROM 0000f109
-CSEG VE_TO_R 0000f10e
-CSEG PFA_TO_R 0000f112
-CSEG VE_R_FETCH 0000f117
-CSEG PFA_R_FETCH 0000f11b
-CSEG VE_NOTEQUAL 0000f122
-CSEG PFA_NOTEQUAL 0000f126
-CSEG VE_ZEROEQUAL 0000f129
-CSEG PFA_ZEROEQUAL 0000f12d
-CSEG PFA_ZERO1 0000f169
-CSEG PFA_TRUE1 0000f160
-CSEG VE_ZEROLESS 0000f130
-CSEG PFA_ZEROLESS 0000f134
-CSEG VE_GREATERZERO 0000f137
-CSEG PFA_GREATERZERO 0000f13b
-CSEG VE_DGREATERZERO 0000f140
-CSEG XT_DGREATERZERO 0000f144
-CSEG PFA_DGREATERZERO 0000f145
-CSEG VE_DXT_ZEROLESS 0000f14e
-CSEG XT_DXT_ZEROLESS 0000f152
-CSEG PFA_DXT_ZEROLESS 0000f153
-CSEG VE_TRUE 0000f159
-CSEG PFA_TRUE 0000f15e
-CSEG VE_ZERO 0000f163
-CSEG PFA_ZERO 0000f167
-CSEG VE_ULESS 0000f16b
-CSEG PFA_ULESS 0000f16f
-CSEG VE_UGREATER 0000f176
-CSEG PFA_UGREATER 0000f17a
-CSEG VE_LESS 0000f17d
-CSEG XT_LESS 0000f180
-CSEG PFA_LESS 0000f181
-CSEG PFA_LESSDONE 0000f185
-CSEG VE_GREATER 0000f187
-CSEG XT_GREATER 0000f18a
-CSEG PFA_GREATER 0000f18b
-CSEG PFA_GREATERDONE 0000f18f
-CSEG VE_LOG2 0000f192
-CSEG XT_LOG2 0000f196
-CSEG PFA_LOG2 0000f197
-CSEG PFA_LOG2_1 0000f19a
-CSEG PFA_LOG2_2 0000f1a0
-CSEG VE_MINUS 0000f1a2
-CSEG XT_MINUS 0000f1a5
-CSEG PFA_MINUS 0000f1a6
-CSEG VE_PLUS 0000f1ac
-CSEG PFA_PLUS 0000f1b0
-CSEG VE_MSTAR 0000f1b5
-CSEG XT_MSTAR 0000f1b8
-CSEG PFA_MSTAR 0000f1b9
-CSEG VE_UMSLASHMOD 0000f1cf
-CSEG PFA_UMSLASHMOD 0000f1d5
-CSEG PFA_UMSLASHMODmod 0000f1da
-CSEG PFA_UMSLASHMODmod_loop 0000f1db
-CSEG PFA_UMSLASHMODmod_loop_control 0000f1e8
-CSEG PFA_UMSLASHMODmod_subtract 0000f1e5
-CSEG PFA_UMSLASHMODmod_done 0000f1ea
-CSEG VE_UMSTAR 0000f1ee
-CSEG PFA_UMSTAR 0000f1f3
-CSEG VE_INVERT 0000f20a
-CSEG PFA_INVERT 0000f210
-CSEG VE_2SLASH 0000f213
-CSEG PFA_2SLASH 0000f217
-CSEG VE_2STAR 0000f21a
-CSEG XT_2STAR 0000f21d
-CSEG PFA_2STAR 0000f21e
-CSEG VE_AND 0000f221
-CSEG PFA_AND 0000f226
-CSEG VE_OR 0000f22b
-CSEG PFA_OR 0000f22f
-CSEG VE_XOR 0000f234
-CSEG XT_XOR 0000f238
-CSEG PFA_XOR 0000f239
-CSEG VE_1PLUS 0000f23e
-CSEG PFA_1PLUS 0000f242
-CSEG VE_1MINUS 0000f244
-CSEG PFA_1MINUS 0000f248
-CSEG VE_QNEGATE 0000f24a
-CSEG XT_QNEGATE 0000f250
-CSEG PFA_QNEGATE 0000f251
-CSEG QNEG1 0000f255
-CSEG XT_NEGATE 0000f65a
-CSEG VE_LSHIFT 0000f256
-CSEG XT_LSHIFT 0000f25b
-CSEG PFA_LSHIFT 0000f25c
-CSEG PFA_LSHIFT1 0000f25f
-CSEG PFA_LSHIFT2 0000f264
-CSEG VE_RSHIFT 0000f265
-CSEG XT_RSHIFT 0000f26a
-CSEG PFA_RSHIFT 0000f26b
-CSEG PFA_RSHIFT1 0000f26e
-CSEG PFA_RSHIFT2 0000f273
-CSEG VE_PLUSSTORE 0000f274
-CSEG PFA_PLUSSTORE 0000f278
-CSEG VE_RP_FETCH 0000f284
-CSEG XT_RP_FETCH 0000f288
-CSEG PFA_RP_FETCH 0000f289
-CSEG VE_RP_STORE 0000f28e
-CSEG XT_RP_STORE 0000f292
-CSEG PFA_RP_STORE 0000f293
-CSEG VE_SP_FETCH 0000f29b
-CSEG XT_SP_FETCH 0000f29f
-CSEG PFA_SP_FETCH 0000f2a0
-CSEG VE_SP_STORE 0000f2a4
-CSEG XT_SP_STORE 0000f2a8
-CSEG PFA_SP_STORE 0000f2a9
-CSEG PFA_DODO 0000f2ae
-CSEG PFA_DODO1 0000f2b0
-CSEG VE_I 0000f2bb
-CSEG PFA_I 0000f2bf
-CSEG PFA_DOPLUSLOOP 0000f2cd
-CSEG PFA_DOPLUSLOOP_LEAVE 0000f2d7
-CSEG PFA_DOPLUSLOOP_NEXT 0000f2d4
-CSEG PFA_DOLOOP 0000f2dc
-CSEG VE_UNLOOP 0000f2e1
-CSEG PFA_UNLOOP 0000f2e7
-CSEG VE_CMOVE_G 0000f2ec
-CSEG XT_CMOVE_G 0000f2f1
-CSEG PFA_CMOVE_G 0000f2f2
-CSEG PFA_CMOVE_G1 0000f303
-CSEG PFA_CMOVE_G2 0000f2ff
-CSEG VE_BYTESWAP 0000f308
-CSEG PFA_BYTESWAP 0000f30c
-CSEG VE_UP_FETCH 0000f310
-CSEG PFA_UP_FETCH 0000f315
-CSEG VE_UP_STORE 0000f319
-CSEG XT_UP_STORE 0000f31d
-CSEG PFA_UP_STORE 0000f31e
-CSEG VE_1MS 0000f322
-CSEG XT_1MS 0000f326
-CSEG PFA_1MS 0000f327
-CSEG VE_2TO_R 0000f32c
-CSEG XT_2TO_R 0000f330
-CSEG PFA_2TO_R 0000f331
-CSEG VE_2R_FROM 0000f33b
-CSEG XT_2R_FROM 0000f33f
-CSEG PFA_2R_FROM 0000f340
-CSEG VE_STOREE 0000f34a
-CSEG PFA_STOREE 0000f34e
-CSEG PFA_STOREE0 0000f34e
-CSEG PFA_FETCHE2 0000f37c
-CSEG PFA_STOREE3 0000f358
-CSEG PFA_STOREE1 0000f363
-CSEG PFA_STOREE4 0000f35f
-CSEG PFA_STOREE2 0000f365
-CSEG VE_FETCHE 0000f36e
-CSEG PFA_FETCHE 0000f372
-CSEG PFA_FETCHE1 0000f372
-CSEG VE_STOREI 0000f382
-CSEG PFA_STOREI 0000f386
-ESEG EE_STOREI 00000078
-CSEG VE_DO_STOREI_NRWW 0000f389
-CSEG XT_DO_STOREI 0000f390
-CSEG PFA_DO_STOREI_NRWW 0000f391
-CSEG DO_STOREI_atmega 0000f3a5
-CSEG pageload 0000f3b6
-CSEG DO_STOREI_writepage 0000f3af
-CSEG dospm 0000f3d2
-EQU pagemask ffffff80
-CSEG pageload_loop 0000f3bc
-CSEG pageload_newdata 0000f3ca
-CSEG pageload_cont 0000f3cc
-CSEG pageload_done 0000f3d1
-CSEG dospm_wait_ee 0000f3d2
-CSEG dospm_wait_spm 0000f3d4
-CSEG VE_FETCHI 0000f3e0
-CSEG PFA_FETCHI 0000f3e4
-CSEG VE_N_TO_R 0000f3ed
-CSEG XT_N_TO_R 0000f3f1
-CSEG PFA_N_TO_R 0000f3f2
-CSEG PFA_N_TO_R1 0000f3f4
-CSEG VE_N_R_FROM 0000f3ff
-CSEG XT_N_R_FROM 0000f403
-CSEG PFA_N_R_FROM 0000f404
-CSEG PFA_N_R_FROM1 0000f409
-CSEG VE_D2STAR 0000f411
-CSEG XT_D2STAR 0000f415
-CSEG PFA_D2STAR 0000f416
-CSEG VE_D2SLASH 0000f41f
-CSEG XT_D2SLASH 0000f423
-CSEG PFA_D2SLASH 0000f424
-CSEG VE_DPLUS 0000f42d
-CSEG PFA_DPLUS 0000f431
-CSEG VE_DMINUS 0000f43e
-CSEG XT_DMINUS 0000f441
-CSEG PFA_DMINUS 0000f442
-CSEG VE_DINVERT 0000f450
-CSEG XT_DINVERT 0000f456
-CSEG PFA_DINVERT 0000f457
-CSEG VE_UDOT 0000f460
-CSEG PFA_UDOT 0000f464
-CSEG XT_UDDOT 0000f745
-CSEG VE_UDOTR 0000f467
-CSEG XT_UDOTR 0000f46b
-CSEG PFA_UDOTR 0000f46c
-CSEG XT_UDDOTR 0000f74e
-CSEG VE_SHOWWORDLIST 0000f470
-CSEG XT_SHOWWORDLIST 0000f479
-CSEG PFA_SHOWWORDLIST 0000f47a
-CSEG XT_SHOWWORD 0000f47f
-CSEG XT_TRAVERSEWORDLIST 0000fc72
-CSEG PFA_SHOWWORD 0000f480
-CSEG VE_WORDS 0000f485
-CSEG XT_WORDS 0000f48a
-CSEG PFA_WORDS 0000f48b
-CSEG VE_INTON 0000f490
-CSEG PFA_INTON 0000f495
-CSEG VE_INTOFF 0000f497
-CSEG XT_INTOFF 0000f49b
-CSEG PFA_INTOFF 0000f49c
-CSEG VE_INTSTORE 0000f49e
-CSEG PFA_INTSTORE 0000f4a3
-CSEG VE_INTFETCH 0000f4a8
-CSEG XT_INTFETCH 0000f4ac
-CSEG PFA_INTFETCH 0000f4ad
-CSEG VE_INTTRAP 0000f4b2
-CSEG XT_INTTRAP 0000f4b8
-CSEG PFA_INTTRAP 0000f4b9
-CSEG PFA_ISREXEC 0000f4be
-CSEG XT_ISREND 0000f4c2
-CSEG PFA_ISREND 0000f4c3
-CSEG PFA_ISREND1 0000f4c5
-CSEG VE_PICK 0000f4c6
-CSEG PFA_PICK 0000f4cb
-CSEG VE_DOTSTRING 0000f4d1
-CSEG XT_DOTSTRING 0000f4d4
-CSEG PFA_DOTSTRING 0000f4d5
-CSEG VE_SQUOTE 0000f4d9
-CSEG PFA_SQUOTE 0000f4dd
-CSEG PFA_SQUOTE1 0000f4e5
-CSEG VE_FILL 0000f4e6
-CSEG PFA_FILL 0000f4eb
-CSEG PFA_FILL2 0000f4f7
-CSEG PFA_FILL1 0000f4f2
-CSEG VE_ENVIRONMENT 0000f4f9
-CSEG XT_ENVIRONMENT 0000f501
-CSEG PFA_ENVIRONMENT 0000f502
-ESEG CFG_ENVIRONMENT 00000056
-CSEG VE_ENVWORDLISTS 0000f503
-CSEG XT_ENVWORDLISTS 0000f50a
-CSEG PFA_ENVWORDLISTS 0000f50b
-CSEG VE_ENVSLASHPAD 0000f50e
-CSEG XT_ENVSLASHPAD 0000f512
-CSEG PFA_ENVSLASHPAD 0000f513
-CSEG XT_PAD 0000f59f
-CSEG VE_ENVSLASHHOLD 0000f517
-CSEG XT_ENVSLASHHOLD 0000f51c
-CSEG PFA_ENVSLASHHOLD 0000f51d
-CSEG VE_ENV_FORTHNAME 0000f521
-CSEG XT_ENV_FORTHNAME 0000f528
-CSEG PFA_EN_FORTHNAME 0000f529
-CSEG VE_ENV_FORTHVERSION 0000f530
-CSEG XT_ENV_FORTHVERSION 0000f536
-CSEG PFA_EN_FORTHVERSION 0000f537
-CSEG VE_ENV_CPU 0000f53a
-CSEG XT_ENV_CPU 0000f53e
-CSEG PFA_EN_CPU 0000f53f
-CSEG XT_ICOUNT 0000f7e7
-CSEG VE_ENV_MCUINFO 0000f543
-CSEG XT_ENV_MCUINFO 0000f549
-CSEG PFA_EN_MCUINFO 0000f54a
-CSEG VE_ENVUSERSIZE 0000f54d
-CSEG XT_ENVUSERSIZE 0000f552
-CSEG PFA_ENVUSERSIZE 0000f553
-CSEG VE_F_CPU 0000f556
-CSEG PFA_F_CPU 0000f55c
-CSEG VE_STATE 0000f561
-CSEG PFA_STATE 0000f567
-DSEG ram_state 0000013d
-CSEG VE_BASE 0000f568
-CSEG XT_BASE 0000f56c
-CSEG PFA_BASE 0000f56d
-CSEG VE_CELLS 0000f56e
-CSEG VE_CELLPLUS 0000f574
-CSEG PFA_CELLPLUS 0000f57a
-CSEG VE_2DUP 0000f57c
-CSEG PFA_2DUP 0000f581
-CSEG VE_2DROP 0000f584
-CSEG PFA_2DROP 0000f58a
-CSEG VE_TUCK 0000f58d
-CSEG PFA_TUCK 0000f592
-CSEG VE_TO_IN 0000f595
-CSEG PFA_TO_IN 0000f59a
-CSEG VE_PAD 0000f59b
-CSEG PFA_PAD 0000f5a0
-CSEG VE_EMIT 0000f5a5
-CSEG XT_EMIT 0000f5a9
-CSEG PFA_EMIT 0000f5aa
-CSEG XT_UDEFERFETCH 0000fbf7
-CSEG XT_UDEFERSTORE 0000fc03
-CSEG VE_EMITQ 0000f5ad
-CSEG XT_EMITQ 0000f5b2
-CSEG PFA_EMITQ 0000f5b3
-CSEG VE_KEY 0000f5b6
-CSEG XT_KEY 0000f5ba
-CSEG PFA_KEY 0000f5bb
-CSEG VE_KEYQ 0000f5be
-CSEG XT_KEYQ 0000f5c2
-CSEG PFA_KEYQ 0000f5c3
-CSEG VE_DP 0000f5c6
-ESEG CFG_DP 00000048
-CSEG VE_EHERE 0000f5cd
-ESEG EE_EHERE 0000004c
-CSEG VE_HERE 0000f5d6
-CSEG PFA_HERE 0000f5db
-ESEG EE_HERE 0000004a
-CSEG VE_ALLOT 0000f5de
-CSEG PFA_ALLOT 0000f5e4
-CSEG VE_BIN 0000f5e9
-CSEG XT_BIN 0000f5ed
-CSEG PFA_BIN 0000f5ee
-CSEG VE_DECIMAL 0000f5f2
-CSEG PFA_DECIMAL 0000f5f9
-CSEG VE_HEX 0000f5fe
-CSEG XT_HEX 0000f602
-CSEG PFA_HEX 0000f603
-CSEG VE_BL 0000f608
-CSEG XT_BL 0000f60b
-CSEG PFA_BL 0000f60c
-CSEG VE_TURNKEY 0000f60d
-CSEG XT_TURNKEY 0000f613
-CSEG PFA_TURNKEY 0000f614
-ESEG CFG_TURNKEY 00000054
-CSEG VE_SLASHMOD 0000f617
-CSEG XT_SLASHMOD 0000f61b
-CSEG PFA_SLASHMOD 0000f61c
-CSEG PFA_SLASHMOD_1 0000f627
-CSEG PFA_SLASHMOD_2 0000f62d
-CSEG PFA_SLASHMOD_3 0000f630
-CSEG PFA_SLASHMOD_5 0000f63b
-CSEG PFA_SLASHMOD_4 0000f63a
-CSEG PFA_SLASHMODmod_done 0000f646
-CSEG PFA_SLASHMOD_6 0000f644
-CSEG VE_USLASHMOD 0000f64a
-CSEG XT_USLASHMOD 0000f64f
-CSEG PFA_USLASHMOD 0000f650
-CSEG VE_NEGATE 0000f655
-CSEG PFA_NEGATE 0000f65b
-CSEG VE_SLASH 0000f65e
-CSEG XT_SLASH 0000f661
-CSEG PFA_SLASH 0000f662
-CSEG VE_MOD 0000f665
-CSEG XT_MOD 0000f669
-CSEG PFA_MOD 0000f66a
-CSEG VE_ABS 0000f66d
-CSEG XT_ABS 0000f671
-CSEG PFA_ABS 0000f672
-CSEG VE_MIN 0000f675
-CSEG XT_MIN 0000f679
-CSEG PFA_MIN 0000f67a
-CSEG PFA_MIN1 0000f67f
-CSEG VE_MAX 0000f681
-CSEG XT_MAX 0000f685
-CSEG PFA_MAX 0000f686
-CSEG PFA_MAX1 0000f68b
-CSEG VE_WITHIN 0000f68d
-CSEG XT_WITHIN 0000f692
-CSEG PFA_WITHIN 0000f693
-CSEG VE_TOUPPER 0000f69a
-CSEG XT_TOUPPER 0000f6a0
-CSEG PFA_TOUPPER 0000f6a1
-CSEG PFA_TOUPPER0 0000f6ac
-CSEG VE_TOLOWER 0000f6ad
-CSEG XT_TOLOWER 0000f6b3
-CSEG PFA_TOLOWER 0000f6b4
-CSEG PFA_TOLOWER0 0000f6bf
-CSEG VE_HLD 0000f6c0
-CSEG XT_HLD 0000f6c4
-CSEG PFA_HLD 0000f6c5
-DSEG ram_hld 0000013f
-CSEG VE_HOLD 0000f6c6
-CSEG XT_HOLD 0000f6ca
-CSEG PFA_HOLD 0000f6cb
-CSEG VE_L_SHARP 0000f6d6
-CSEG XT_L_SHARP 0000f6d9
-CSEG PFA_L_SHARP 0000f6da
-CSEG VE_SHARP 0000f6de
-CSEG XT_SHARP 0000f6e1
-CSEG PFA_SHARP 0000f6e2
-CSEG XT_UDSLASHMOD 0000f75e
-CSEG PFA_SHARP1 0000f6ef
-CSEG VE_SHARP_S 0000f6f4
-CSEG XT_SHARP_S 0000f6f7
-CSEG PFA_SHARP_S 0000f6f8
-CSEG NUMS1 0000f6f8
-CSEG VE_SHARP_G 0000f6ff
-CSEG XT_SHARP_G 0000f702
-CSEG PFA_SHARP_G 0000f703
-CSEG VE_SIGN 0000f70a
-CSEG XT_SIGN 0000f70e
-CSEG PFA_SIGN 0000f70f
-CSEG PFA_SIGN1 0000f715
-CSEG VE_DDOTR 0000f716
-CSEG XT_DDOTR 0000f71a
-CSEG PFA_DDOTR 0000f71b
-CSEG XT_DABS 0000fcef
-CSEG XT_SPACES 0000f806
-CSEG XT_TYPE 0000f816
-CSEG VE_DOTR 0000f729
-CSEG XT_DOTR 0000f72c
-CSEG PFA_DOTR 0000f72d
-CSEG VE_DDOT 0000f732
-CSEG XT_DDOT 0000f735
-CSEG PFA_DDOT 0000f736
-CSEG VE_DOT 0000f73a
-CSEG PFA_DOT 0000f73e
-CSEG VE_UDDOT 0000f741
-CSEG PFA_UDDOT 0000f746
-CSEG VE_UDDOTR 0000f74a
-CSEG PFA_UDDOTR 0000f74f
-CSEG VE_UDSLASHMOD 0000f759
-CSEG PFA_UDSLASHMOD 0000f75f
-CSEG VE_DIGITQ 0000f769
-CSEG XT_DIGITQ 0000f76e
-CSEG PFA_DIGITQ 0000f76f
-CSEG PFA_DOSLITERAL 0000f789
-CSEG VE_SCOMMA 0000f793
-CSEG PFA_SCOMMA 0000f797
-CSEG PFA_DOSCOMMA 0000f79b
-CSEG PFA_SCOMMA2 0000f7ad
-CSEG PFA_SCOMMA1 0000f7a7
-CSEG PFA_SCOMMA3 0000f7b4
-CSEG VE_ITYPE 0000f7b6
-CSEG PFA_ITYPE 0000f7bc
-CSEG PFA_ITYPE2 0000f7cf
-CSEG PFA_ITYPE1 0000f7c7
-CSEG XT_LOWEMIT 0000f7dc
-CSEG XT_HIEMIT 0000f7d8
-CSEG PFA_ITYPE3 0000f7d6
-CSEG PFA_HIEMIT 0000f7d9
-CSEG PFA_LOWEMIT 0000f7dd
-CSEG VE_ICOUNT 0000f7e2
-CSEG PFA_ICOUNT 0000f7e8
-CSEG VE_CR 0000f7ed
-CSEG XT_CR 0000f7f0
-CSEG PFA_CR 0000f7f1
-CSEG VE_SPACE 0000f7f8
-CSEG PFA_SPACE 0000f7fe
-CSEG VE_SPACES 0000f801
-CSEG PFA_SPACES 0000f807
-CSEG SPCS1 0000f809
-CSEG SPCS2 0000f810
-CSEG VE_TYPE 0000f812
-CSEG PFA_TYPE 0000f817
-CSEG PFA_TYPE2 0000f821
-CSEG PFA_TYPE1 0000f81c
-CSEG VE_TICK 0000f822
-CSEG PFA_TICK 0000f826
-CSEG XT_DT_NULL 0000fb65
-CSEG XT_NOOP 0000fb9a
-CSEG PFA_TICK1 0000f837
-CSEG VE_HANDLER 0000f839
-CSEG XT_HANDLER 0000f83f
-CSEG PFA_HANDLER 0000f840
-CSEG VE_CATCH 0000f841
-CSEG XT_CATCH 0000f846
-CSEG PFA_CATCH 0000f847
-CSEG VE_THROW 0000f857
-CSEG PFA_THROW 0000f85d
-CSEG PFA_THROW1 0000f863
-CSEG VE_CSKIP 0000f870
-CSEG XT_CSKIP 0000f875
-CSEG PFA_CSKIP 0000f876
-CSEG PFA_CSKIP1 0000f877
-CSEG PFA_CSKIP2 0000f884
-CSEG XT_SLASHSTRING 0000f9c0
-CSEG VE_CSCAN 0000f887
-CSEG XT_CSCAN 0000f88c
-CSEG PFA_CSCAN 0000f88d
-CSEG PFA_CSCAN1 0000f88f
-CSEG PFA_CSCAN2 0000f8a1
-CSEG VE_ACCEPT 0000f8a7
-CSEG XT_ACCEPT 0000f8ac
-CSEG PFA_ACCEPT 0000f8ad
-CSEG ACC1 0000f8b1
-CSEG XT_CRLFQ 0000f8ed
-CSEG ACC5 0000f8df
-CSEG ACC3 0000f8cf
-CSEG ACC6 0000f8cd
-CSEG XT_BS 0000f8e5
-CSEG ACC4 0000f8dd
-CSEG PFA_ACCEPT6 0000f8d6
-CSEG VE_REFILL 0000f8f8
-CSEG XT_REFILL 0000f8fd
-CSEG PFA_REFILL 0000f8fe
-CSEG VE_CHAR 0000f901
-CSEG PFA_CHAR 0000f906
-CSEG VE_NUMBER 0000f90a
-CSEG XT_NUMBER 0000f90f
-CSEG PFA_NUMBER 0000f910
-CSEG XT_QSIGN 0000f953
-CSEG XT_SET_BASE 0000f966
-CSEG PFA_NUMBER0 0000f926
-CSEG XT_TO_NUMBER 0000f984
-CSEG PFA_NUMBER1 0000f948
-CSEG PFA_NUMBER2 0000f93f
-CSEG PFA_NUMBER6 0000f940
-CSEG PFA_NUMBER3 0000f93c
-CSEG XT_DNEGATE 0000fcfc
-CSEG PFA_NUMBER5 0000f94e
-CSEG PFA_NUMBER4 0000f94d
-CSEG PFA_QSIGN 0000f954
-CSEG PFA_NUMBERSIGN_DONE 0000f95f
-CSEG XT_BASES 0000f961
-CSEG PFA_SET_BASE 0000f967
-CSEG SET_BASE1 0000f97c
-CSEG SET_BASE2 0000f97d
-CSEG VE_TO_NUMBER 0000f97e
-CSEG TONUM1 0000f985
-CSEG TONUM3 0000f99c
-CSEG TONUM2 0000f990
-CSEG XT_2SWAP 0000fd20
-CSEG VE_PARSE 0000f99d
-CSEG PFA_PARSE 0000f9a3
-CSEG VE_SOURCE 0000f9b1
-CSEG PFA_SOURCE 0000f9b7
-CSEG VE_SLASHSTRING 0000f9ba
-CSEG PFA_SLASHSTRING 0000f9c1
-CSEG VE_PARSENAME 0000f9c8
-CSEG PFA_PARSENAME 0000f9d0
-CSEG XT_SKIPSCANCHAR 0000f9d3
-CSEG PFA_SKIPSCANCHAR 0000f9d4
-CSEG VE_FINDXT 0000f9e5
-CSEG XT_FINDXT 0000f9eb
-CSEG PFA_FINDXT 0000f9ec
-CSEG XT_FINDXTA 0000f9f7
-CSEG PFA_FINDXT1 0000f9f6
-CSEG PFA_FINDXTA 0000f9f8
-CSEG XT_SEARCH_WORDLIST 0000fc40
-CSEG PFA_FINDXTA1 0000fa04
-CSEG XT_DEFAULT_PROMPTOK 0000fa05
-CSEG PFA_DEFAULT_PROMPTOK 0000fa06
-CSEG VE_PROMPTOK 0000fa0c
-CSEG XT_PROMPTOK 0000fa10
-CSEG PFA_PROMPTOK 0000fa11
-CSEG XT_DEFAULT_PROMPTREADY 0000fa14
-CSEG PFA_DEFAULT_PROMPTREADY 0000fa15
-CSEG VE_PROMPTREADY 0000fa1b
-CSEG XT_PROMPTREADY 0000fa20
-CSEG PFA_PROMPTREADY 0000fa21
-CSEG XT_DEFAULT_PROMPTERROR 0000fa24
-CSEG PFA_DEFAULT_PROMPTERROR 0000fa25
-CSEG VE_PROMPTERROR 0000fa36
-CSEG XT_PROMPTERROR 0000fa3b
-CSEG PFA_PROMPTERROR 0000fa3c
-CSEG VE_QUIT 0000fa3f
-CSEG XT_QUIT 0000fa43
-CSEG PFA_QUIT 0000fa44
-CSEG XT_SP0 0000faa4
-CSEG XT_RP0 0000fab1
-CSEG PFA_QUIT2 0000fa4c
-CSEG PFA_QUIT4 0000fa52
-CSEG PFA_QUIT3 0000fa64
-CSEG XT_INTERPRET 0000faca
-CSEG PFA_QUIT5 0000fa62
-CSEG VE_PAUSE 0000fa67
-CSEG PFA_PAUSE 0000fa6d
-DSEG ram_pause 00000141
-CSEG XT_RDEFERFETCH 0000fbe3
-CSEG XT_RDEFERSTORE 0000fbed
-CSEG VE_COLD 0000fa70
-CSEG clearloop 0000fa7c
-DSEG ram_user1 00000143
-CSEG PFA_WARM 0000fa97
-CSEG VE_WARM 0000fa92
-CSEG XT_WARM 0000fa96
-CSEG XT_INIT_RAM 0000fd6b
-CSEG XT_DEFERSTORE 0000fc0e
-CSEG VE_SP0 0000faa0
-CSEG PFA_SP0 0000faa5
-CSEG VE_SP 0000faa8
-CSEG XT_SP 0000faab
-CSEG PFA_SP 0000faac
-CSEG VE_RP0 0000faad
-CSEG PFA_RP0 0000fab2
-CSEG XT_DORP0 0000fab5
-CSEG PFA_DORP0 0000fab6
-CSEG VE_DEPTH 0000fab7
-CSEG PFA_DEPTH 0000fabd
-CSEG VE_INTERPRET 0000fac3
-CSEG PFA_INTERPRET 0000facb
-CSEG PFA_INTERPRET2 0000fadb
-CSEG PFA_INTERPRET1 0000fad6
-CSEG VE_FORTHRECOGNIZER 0000fadd
-CSEG PFA_FORTHRECOGNIZER 0000fae8
-ESEG CFG_FORTHRECOGNIZER 00000050
-CSEG VE_RECOGNIZE 0000faeb
-CSEG PFA_RECOGNIZE 0000faf3
-CSEG XT_RECOGNIZE_A 0000fafd
-CSEG PFA_RECOGNIZE1 0000fafc
-CSEG PFA_RECOGNIZE_A 0000fafe
-CSEG PFA_RECOGNIZE_A1 0000fb0e
-CSEG VE_DT_NUM 0000fb12
-CSEG XT_DT_NUM 0000fb17
-CSEG PFA_DT_NUM 0000fb18
-CSEG VE_DT_DNUM 0000fb1b
-CSEG XT_DT_DNUM 0000fb21
-CSEG PFA_DT_DNUM 0000fb22
-CSEG XT_2LITERAL 0000fd92
-CSEG VE_REC_NUM 0000fb25
-CSEG XT_REC_NUM 0000fb2b
-CSEG PFA_REC_NUM 0000fb2c
-CSEG PFA_REC_NONUMBER 0000fb37
-CSEG PFA_REC_INTNUM2 0000fb35
-CSEG VE_REC_FIND 0000fb39
-CSEG XT_REC_FIND 0000fb3f
-CSEG PFA_REC_FIND 0000fb40
-CSEG PFA_REC_WORD_FOUND 0000fb48
-CSEG XT_DT_XT 0000fb4f
-CSEG VE_DT_XT 0000fb4a
-CSEG PFA_DT_XT 0000fb50
-CSEG XT_R_WORD_INTERPRET 0000fb53
-CSEG XT_R_WORD_COMPILE 0000fb57
-CSEG PFA_R_WORD_INTERPRET 0000fb54
-CSEG PFA_R_WORD_COMPILE 0000fb58
-CSEG PFA_R_WORD_COMPILE1 0000fb5d
-CSEG VE_DT_NULL 0000fb5f
-CSEG PFA_DT_NULL 0000fb66
-CSEG XT_FAIL 0000fb69
-CSEG PFA_FAIL 0000fb6a
-CSEG VE_QSTACK 0000fb6d
-CSEG PFA_QSTACK 0000fb73
-CSEG PFA_QSTACK1 0000fb7a
-CSEG VE_DOT_VER 0000fb7b
-CSEG PFA_DOT_VER 0000fb80
-CSEG VE_NOOP 0000fb96
-CSEG PFA_NOOP 0000fb9b
-CSEG VE_UNUSED 0000fb9c
-CSEG XT_UNUSED 0000fba1
-CSEG PFA_UNUSED 0000fba2
-CSEG VE_TO 0000fba6
-CSEG XT_TO 0000fba9
-CSEG PFA_TO 0000fbaa
-CSEG XT_TO_BODY 0000fd8b
-CSEG PFA_TO1 0000fbba
-CSEG PFA_DOTO 0000fbb5
-CSEG VE_ICELLPLUS 0000fbc0
-CSEG PFA_ICELLPLUS 0000fbc7
-CSEG VE_EDEFERFETCH 0000fbc9
-CSEG PFA_EDEFERFETCH 0000fbd0
-CSEG VE_EDEFERSTORE 0000fbd3
-CSEG PFA_EDEFERSTORE 0000fbda
-CSEG VE_RDEFERFETCH 0000fbdd
-CSEG PFA_RDEFERFETCH 0000fbe4
-CSEG VE_RDEFERSTORE 0000fbe7
-CSEG PFA_RDEFERSTORE 0000fbee
-CSEG VE_UDEFERFETCH 0000fbf1
-CSEG PFA_UDEFERFETCH 0000fbf8
-CSEG VE_UDEFERSTORE 0000fbfd
-CSEG PFA_UDEFERSTORE 0000fc04
-CSEG VE_DEFERSTORE 0000fc09
-CSEG PFA_DEFERSTORE 0000fc0f
-CSEG VE_DEFERFETCH 0000fc16
-CSEG XT_DEFERFETCH 0000fc1b
-CSEG PFA_DEFERFETCH 0000fc1c
-CSEG VE_DODEFER 0000fc22
-CSEG XT_DODEFER 0000fc28
-CSEG PFA_DODEFER 0000fc29
-CSEG VE_SEARCH_WORDLIST 0000fc36
-CSEG PFA_SEARCH_WORDLIST 0000fc41
-CSEG XT_ISWORD 0000fc55
-CSEG PFA_SEARCH_WORDLIST1 0000fc4f
-CSEG PFA_ISWORD 0000fc56
-CSEG XT_ICOMPARE 0000fca3
-CSEG PFA_ISWORD3 0000fc63
-CSEG VE_TRAVERSEWORDLIST 0000fc67
-CSEG PFA_TRAVERSEWORDLIST 0000fc73
-CSEG PFA_TRAVERSEWORDLIST1 0000fc74
-CSEG PFA_TRAVERSEWORDLIST2 0000fc83
-CSEG VE_NAME2STRING 0000fc85
-CSEG PFA_NAME2STRING 0000fc8e
-CSEG VE_NFA2CFA 0000fc93
-CSEG PFA_NFA2CFA 0000fc9a
-CSEG VE_ICOMPARE 0000fc9d
-CSEG PFA_ICOMPARE 0000fca4
-CSEG PFA_ICOMPARE_SAMELEN 0000fcae
-CSEG PFA_ICOMPARE_DONE 0000fcd1
-CSEG PFA_ICOMPARE_LOOP 0000fcb4
-CSEG PFA_ICOMPARE_LASTCELL 0000fcc2
-CSEG PFA_ICOMPARE_NEXTLOOP 0000fcc9
-CSEG VE_STAR 0000fcd4
-CSEG XT_STAR 0000fcd7
-CSEG PFA_STAR 0000fcd8
-CSEG VE_J 0000fcdb
-CSEG XT_J 0000fcde
-CSEG PFA_J 0000fcdf
-CSEG VE_DABS 0000fceb
-CSEG PFA_DABS 0000fcf0
-CSEG PFA_DABS1 0000fcf5
-CSEG VE_DNEGATE 0000fcf6
-CSEG PFA_DNEGATE 0000fcfd
-CSEG VE_CMOVE 0000fd02
-CSEG XT_CMOVE 0000fd07
-CSEG PFA_CMOVE 0000fd08
-CSEG PFA_CMOVE1 0000fd15
-CSEG PFA_CMOVE2 0000fd11
-CSEG VE_2SWAP 0000fd1b
-CSEG PFA_2SWAP 0000fd21
-CSEG VE_REFILLTIB 0000fd26
-CSEG XT_REFILLTIB 0000fd2d
-CSEG PFA_REFILLTIB 0000fd2e
-CSEG XT_TIB 0000fd49
-CSEG XT_NUMBERTIB 0000fd4f
-CSEG VE_SOURCETIB 0000fd39
-CSEG XT_SOURCETIB 0000fd40
-CSEG PFA_SOURCETIB 0000fd41
-CSEG VE_TIB 0000fd45
-CSEG PFA_TIB 0000fd4a
-DSEG ram_tib 0000016f
-CSEG VE_NUMBERTIB 0000fd4b
-CSEG PFA_NUMBERTIB 0000fd50
-DSEG ram_sharptib 000001c9
-CSEG VE_EE2RAM 0000fd51
-CSEG XT_EE2RAM 0000fd56
-CSEG PFA_EE2RAM 0000fd57
-CSEG PFA_EE2RAM_1 0000fd59
-CSEG PFA_EE2RAM_2 0000fd63
-CSEG VE_INIT_RAM 0000fd65
-CSEG PFA_INI_RAM 0000fd6c
-ESEG EE_INITUSER 0000007c
-CSEG VE_BOUNDS 0000fd74
-CSEG PFA_BOUNDS 0000fd7a
-CSEG VE_S2D 0000fd7e
-CSEG PFA_S2D 0000fd83
-CSEG VE_TO_BODY 0000fd86
-CSEG VE_2LITERAL 0000fd8c
-CSEG PFA_2LITERAL 0000fd93
-CSEG VE_EQUAL 0000fd97
-CSEG PFA_EQUAL 0000fd9b
-CSEG VE_ONE 0000fd9e
-CSEG PFA_ONE 0000fda2
-CSEG VE_TWO 0000fda3
-CSEG PFA_TWO 0000fda7
-CSEG VE_MINUSONE 0000fda8
-CSEG XT_MINUSONE 0000fdab
-CSEG PFA_MINUSONE 0000fdac
-SET flashlast 0000fdad
-DSEG HERESTART 000001cb
-ESEG EHERESTART 000000a0
-ESEG CFG_ORDERLIST 0000005e
-ESEG CFG_RECOGNIZERLIST 00000070
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/eval-pollin/p1284-16.xml b/amforth-6.5/appl/eval-pollin/p1284-16.xml
deleted file mode 100644
index b712290..0000000
--- a/amforth-6.5/appl/eval-pollin/p1284-16.xml
+++ /dev/null
@@ -1,36 +0,0 @@
-<project name="pollins-1284-16" basedir="." default="Help">
- <target name="p1284-16.asm">
- <copy tofile="p1284-16.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="16000000"/>
- <filter token="USART" value="_0"/>
- </filterset>
- </copy>
- </target>
-
- <target name="p1284-16.hex" depends="p1284-16.asm" description="Hexfiles for p1284-16">
- <avrasm2 projectname="p1284-16" mcu="atmega1284p"/>
- <delete file="p1284-16.asm"/>
- </target>
-
- <target name="p1284-16" depends="p1284-16.hex" description="Atmega1284 @ 16 MHz">
- <echo>Uploading Hexfiles for p1284 - 16</echo>
- <avrdude
- type="stk200"
- mcu="atmega1284p"
- flashfile="p1284-16.hex"
- eepromfile="p1284-16.eep.hex"
- />
- </target>
- <target name="p1284-16.fuses" description="Set fuses for P16-8">
- <echo>Writing fuses</echo>
- <avrdude-3fuses
- type="${programmer}"
- mcu="${mcu}"
- efuse="0xff"
- hfuse="0x99"
- lfuse="0xc6"
- />
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/p16-8.eep.hex b/amforth-6.5/appl/eval-pollin/p16-8.eep.hex
deleted file mode 100644
index c6b7ad6..0000000
--- a/amforth-6.5/appl/eval-pollin/p16-8.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10002A00FFFF020F1D018400150552001004540E33
-:0A003A00B7053E00EE1F01003E0076
-:060052000200AB0B970B4E
-:10005C007E1F5E00000000005F040F040F04000010
-:10006C000A009800A6006D008800AC0D0000990DE8
-:08007C00990AB80AA80A0C0059
-:00000001FF
diff --git a/amforth-6.5/appl/eval-pollin/p16-8.hex b/amforth-6.5/appl/eval-pollin/p16-8.hex
deleted file mode 100644
index c9756f7..0000000
--- a/amforth-6.5/appl/eval-pollin/p16-8.hex
+++ /dev/null
@@ -1,625 +0,0 @@
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diff --git a/amforth-6.5/appl/eval-pollin/p16-8.lst b/amforth-6.5/appl/eval-pollin/p16-8.lst
deleted file mode 100644
index 4cb21fb..0000000
--- a/amforth-6.5/appl/eval-pollin/p16-8.lst
+++ /dev/null
@@ -1,10363 +0,0 @@
-
-AVRASM ver. 2.1.52 p16-8.asm Sun Apr 30 20:10:14 2017
-
-p16-8.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega16\device.asm'
-../../avr8/devices/atmega16\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m16def.inc'
-p16-8.asm(14): Including file '../../avr8\drivers/usart.asm'
-../../avr8\drivers/usart.asm(30): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-p16-8.asm(19): Including file '../../avr8\drivers/1wire.asm'
-p16-8.asm(21): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(13): Including file '../../avr8\dict/appl_2k.inc'
-../../avr8\dict/appl_2k.inc(1): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/appl_2k.inc(2): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/appl_2k.inc(3): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/appl_2k.inc(4): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/appl_2k.inc(5): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/appl_2k.inc(6): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/appl_2k.inc(7): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/appl_2k.inc(9): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/appl_2k.inc(10): Including file '../../common\words/words.asm'
-../../avr8\dict/appl_2k.inc(11): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/appl_2k.inc(13): Including file '../../common\words/pick.asm'
-../../avr8\dict/appl_2k.inc(14): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/appl_2k.inc(15): Including file '../../common\words/squote.asm'
-../../avr8\dict/appl_2k.inc(17): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/appl_2k.inc(18): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\dict/appl_2k.inc(20): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/appl_2k.inc(21): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/appl_2k.inc(22): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/appl_2k.inc(23): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/appl_2k.inc(24): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/appl_2k.inc(25): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/appl_2k.inc(26): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/appl_2k.inc(27): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/appl_2k.inc(28): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/appl_2k.inc(30): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/appl_2k.inc(31): Including file '../../avr8\words/state.asm'
-../../avr8\dict/appl_2k.inc(32): Including file '../../common\words/base.asm'
-../../avr8\dict/appl_2k.inc(34): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/appl_2k.inc(35): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/appl_2k.inc(37): Including file '../../common\words/2dup.asm'
-../../avr8\dict/appl_2k.inc(38): Including file '../../common\words/2drop.asm'
-../../avr8\dict/appl_2k.inc(40): Including file '../../common\words/tuck.asm'
-../../avr8\dict/appl_2k.inc(42): Including file '../../common\words/to-in.asm'
-../../avr8\dict/appl_2k.inc(43): Including file '../../common\words/pad.asm'
-../../avr8\dict/appl_2k.inc(44): Including file '../../common\words/emit.asm'
-../../avr8\dict/appl_2k.inc(45): Including file '../../common\words/emitq.asm'
-../../avr8\dict/appl_2k.inc(46): Including file '../../common\words/key.asm'
-../../avr8\dict/appl_2k.inc(47): Including file '../../common\words/keyq.asm'
-../../avr8\dict/appl_2k.inc(49): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/appl_2k.inc(50): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/appl_2k.inc(51): Including file '../../avr8\words/here.asm'
-../../avr8\dict/appl_2k.inc(52): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/appl_2k.inc(54): Including file '../../common\words/bin.asm'
-../../avr8\dict/appl_2k.inc(55): Including file '../../common\words/decimal.asm'
-../../avr8\dict/appl_2k.inc(56): Including file '../../common\words/hex.asm'
-../../avr8\dict/appl_2k.inc(57): Including file '../../common\words/bl.asm'
-../../avr8\dict/appl_2k.inc(59): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/appl_2k.inc(61): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/appl_2k.inc(62): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/appl_2k.inc(63): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/appl_2k.inc(64): Including file '../../common\words/slash.asm'
-../../avr8\dict/appl_2k.inc(65): Including file '../../common\words/mod.asm'
-../../avr8\dict/appl_2k.inc(66): Including file '../../common\words/abs.asm'
-../../avr8\dict/appl_2k.inc(67): Including file '../../common\words/min.asm'
-../../avr8\dict/appl_2k.inc(68): Including file '../../common\words/max.asm'
-../../avr8\dict/appl_2k.inc(69): Including file '../../common\words/within.asm'
-../../avr8\dict/appl_2k.inc(71): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/appl_2k.inc(72): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/appl_2k.inc(74): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/appl_2k.inc(75): Including file '../../common\words/hold.asm'
-../../avr8\dict/appl_2k.inc(76): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/appl_2k.inc(77): Including file '../../common\words/sharp.asm'
-../../avr8\dict/appl_2k.inc(78): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/appl_2k.inc(79): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/appl_2k.inc(80): Including file '../../common\words/sign.asm'
-../../avr8\dict/appl_2k.inc(81): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/appl_2k.inc(82): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/appl_2k.inc(83): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/appl_2k.inc(84): Including file '../../common\words/dot.asm'
-../../avr8\dict/appl_2k.inc(85): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/appl_2k.inc(86): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/appl_2k.inc(87): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/appl_2k.inc(88): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/appl_2k.inc(90): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/appl_2k.inc(91): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/appl_2k.inc(92): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/appl_2k.inc(93): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/appl_2k.inc(94): Including file '../../common\words/cr.asm'
-../../avr8\dict/appl_2k.inc(95): Including file '../../common\words/space.asm'
-../../avr8\dict/appl_2k.inc(96): Including file '../../common\words/spaces.asm'
-../../avr8\dict/appl_2k.inc(97): Including file '../../common\words/type.asm'
-../../avr8\dict/appl_2k.inc(98): Including file '../../common\words/tick.asm'
-../../avr8\dict/appl_2k.inc(100): Including file '../../common\words/handler.asm'
-../../avr8\dict/appl_2k.inc(101): Including file '../../common\words/catch.asm'
-../../avr8\dict/appl_2k.inc(102): Including file '../../common\words/throw.asm'
-../../avr8\dict/appl_2k.inc(104): Including file '../../common\words/cskip.asm'
-../../avr8\dict/appl_2k.inc(105): Including file '../../common\words/cscan.asm'
-../../avr8\dict/appl_2k.inc(106): Including file '../../common\words/accept.asm'
-../../avr8\dict/appl_2k.inc(107): Including file '../../common\words/refill.asm'
-../../avr8\dict/appl_2k.inc(108): Including file '../../common\words/char.asm'
-../../avr8\dict/appl_2k.inc(109): Including file '../../common\words/number.asm'
-../../avr8\dict/appl_2k.inc(110): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/appl_2k.inc(111): Including file '../../common\words/set-base.asm'
-../../avr8\dict/appl_2k.inc(112): Including file '../../common\words/to-number.asm'
-../../avr8\dict/appl_2k.inc(113): Including file '../../common\words/parse.asm'
-../../avr8\dict/appl_2k.inc(114): Including file '../../common\words/source.asm'
-../../avr8\dict/appl_2k.inc(115): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/appl_2k.inc(116): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/appl_2k.inc(117): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/appl_2k.inc(119): Including file '../../common\words/quit.asm'
-../../avr8\dict/appl_2k.inc(120): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/appl_2k.inc(121): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/appl_2k.inc(122): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/appl_2k.inc(123): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/appl_2k.inc(124): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/appl_2k.inc(125): Including file '../../common\words/warm.asm'
-../../avr8\dict/appl_2k.inc(127): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/appl_2k.inc(128): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/appl_2k.inc(129): Including file '../../common\words/depth.asm'
-../../avr8\dict/appl_2k.inc(130): Including file '../../common\words/recognize.asm'
-../../avr8\dict/appl_2k.inc(131): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/appl_2k.inc(132): Including file '../../common\words/interpret.asm'
-../../avr8\dict/appl_2k.inc(133): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/appl_2k.inc(134): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/appl_2k.inc(135): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/appl_2k.inc(137): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/appl_2k.inc(138): Including file '../../common\words/ver.asm'
-../../avr8\dict/appl_2k.inc(140): Including file '../../common\words/noop.asm'
-../../avr8\dict/appl_2k.inc(141): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/appl_2k.inc(143): Including file '../../common\words/to.asm'
-../../avr8\dict/appl_2k.inc(144): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/appl_2k.inc(146): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/appl_2k.inc(147): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/appl_2k.inc(148): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/appl_2k.inc(149): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/appl_2k.inc(150): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/appl_2k.inc(151): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/appl_2k.inc(152): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/appl_2k.inc(153): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/appl_2k.inc(154): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/appl_2k.inc(156): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/appl_2k.inc(157): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/appl_2k.inc(158): Including file '../../common\words/name2string.asm'
-../../avr8\dict/appl_2k.inc(159): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/appl_2k.inc(160): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/appl_2k.inc(162): Including file '../../common\words/star.asm'
-../../avr8\dict/appl_2k.inc(163): Including file '../../avr8\words/j.asm'
-../../avr8\dict/appl_2k.inc(165): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/appl_2k.inc(166): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/appl_2k.inc(167): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/appl_2k.inc(168): Including file '../../common\words/2swap.asm'
-../../avr8\dict/appl_2k.inc(170): Including file '../../common\words/tib.asm'
-../../avr8\dict/appl_2k.inc(172): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/appl_2k.inc(173): Including file '../../common\words/bounds.asm'
-../../avr8\dict/appl_2k.inc(174): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/appl_2k.inc(175): Including file '../../avr8\words/to-body.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(3): Including file '../../common\words/dot-s.asm'
-dict_appl.inc(4): Including file '../../avr8\words/spirw.asm'
-dict_appl.inc(5): Including file '../../avr8\words/n-spi.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-dict_appl.inc(7): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(8): Including file '../../avr8\words/2r_fetch.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(106): Including file '../../avr8\dict/core_2k.inc'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 96
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_EEPROM = 0
- .set WANT_CPU = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_SPI = 0
- .set WANT_USART = 0
- .set WANT_TWI = 0
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_JTAG = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_WATCHDOG = 0
- .equ intvecsize = 2 ; please verify; flash size: 16384 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d11b rcall isr ; External Interrupt Request 0
- .org 4
-000004 d119 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d117 rcall isr ; Timer/Counter2 Compare Match
- .org 8
-000008 d115 rcall isr ; Timer/Counter2 Overflow
- .org 10
-00000a d113 rcall isr ; Timer/Counter1 Capture Event
- .org 12
-00000c d111 rcall isr ; Timer/Counter1 Compare Match A
- .org 14
-00000e d10f rcall isr ; Timer/Counter1 Compare Match B
- .org 16
-000010 d10d rcall isr ; Timer/Counter1 Overflow
- .org 18
-000012 d10b rcall isr ; Timer/Counter0 Overflow
- .org 20
-000014 d109 rcall isr ; Serial Transfer Complete
- .org 22
-000016 d107 rcall isr ; USART, Rx Complete
- .org 24
-000018 d105 rcall isr ; USART Data Register Empty
- .org 26
-00001a d103 rcall isr ; USART, Tx Complete
- .org 28
-00001c d101 rcall isr ; ADC Conversion Complete
- .org 30
-00001e d0ff rcall isr ; EEPROM Ready
- .org 32
-000020 d0fd rcall isr ; Analog Comparator
- .org 34
-000022 d0fb rcall isr ; 2-wire Serial Interface
- .org 36
-000024 d0f9 rcall isr ; External Interrupt Request 2
- .org 38
-000026 d0f7 rcall isr ; Timer/Counter0 Compare Match
- .org 40
-000028 d0f5 rcall isr ; Store Program Memory Ready
- .equ INTVECTORS = 21
- .nooverlap
-
- ; compatability layer (maybe empty)
- .equ EEPE = EEWE
- .equ EEMPE = EEMWE
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000029 0400 .dw 1024
- mcu_eepromsize:
-00002a 0200 .dw 512
- mcu_maxdp:
-00002b 3800 .dw 14336
- mcu_numints:
-00002c 0015 .dw 21
- mcu_name:
-00002d 0008 .dw 8
-00002e 5441
-00002f 656d
-000030 6167
-000031 3631 .db "ATmega16"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set AMFORTH_RO_SEG = NRWW_START_ADDR+1
-
- ; cpu clock in hertz
- .equ F_CPU = 8000000
- .set BAUD_MAXERROR = 30
- .equ TIMER_INT = OVF2addr
-
- .include "drivers/usart.asm"
-
- .equ BAUDRATE_LOW = UBRRL+$20
- .equ BAUDRATE_HIGH = UBRRH+$20
- .equ USART_C = UCSRC+$20
- .equ USART_B = UCSRB+$20
- .equ USART_A = UCSRA+$20
- .equ USART_DATA = UDR+$20
- .equ bm_USARTC_en = 1 << 7
-
- ; some generic constants
- .equ bm_USART_RXRD = 1 << RXC
- .equ bm_USART_TXRD = 1 << UDRE
- .equ bm_ENABLE_TX = 1 << TXEN
- .equ bm_ENABLE_RX = 1 << RXEN
- .equ bm_ENABLE_INT_RX = 1<<RXCIE
- .equ bm_ENABLE_INT_TX = 1<<UDRE
-
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000060 usart_rx_data: .byte usart_rx_size
-000070 usart_rx_in: .byte 1
-000071 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-000032 ff07 .dw $ff07
-000033 723e
-000034 2d78
-000035 7562
-000036 0066 .db ">rx-buf",0
-000037 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000038 0039 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000039 2f08 mov temp0, tosl
-00003a 9110 0070 lds temp1, usart_rx_in
-00003c e6e0 ldi zl, low(usart_rx_data)
-00003d e0f0 ldi zh, high(usart_rx_data)
-00003e 0fe1 add zl, temp1
-00003f 1df3 adc zh, zeroh
-000040 8300 st Z, temp0
-000041 9513 inc temp1
-000042 701f andi temp1,usart_rx_mask
-000043 9310 0070 sts usart_rx_in, temp1
-000045 9189
-000046 9199 loadtos
-000047 940c 1c05 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000049 ff06 .dw $ff06
-00004a 7369
-00004b 2d72
-00004c 7872 .db "isr-rx"
-00004d 0032 .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-00004e 1c01 .dw DO_COLON
- usart_rx_isr:
-00004f 1c3d .dw XT_DOLITERAL
-000050 002c .dw usart_data
-000051 1c98 .dw XT_CFETCH
-000052 1cb1 .dw XT_DUP
-000053 1c3d .dw XT_DOLITERAL
-000054 0003 .dw 3
-000055 1fe0 .dw XT_EQUAL
-000056 1c36 .dw XT_DOCONDBRANCH
-000057 0059 .dw usart_rx_isr1
-000058 0ae0 .dw XT_COLD
- usart_rx_isr1:
-000059 0038 .dw XT_TO_RXBUF
-00005a 1c20 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-00005b 1c01 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-00005c 1c3d
-00005d 004e .dw XT_DOLITERAL, XT_ISR_RX
-00005e 1c3d
-00005f 0016 .dw XT_DOLITERAL, URXCaddr
-000060 0213 .dw XT_INTSTORE
-
-000061 1c3d .dw XT_DOLITERAL
-000062 0060 .dw usart_rx_data
-000063 1c3d .dw XT_DOLITERAL
-000064 0016 .dw usart_rx_size + 6
-000065 1d54 .dw XT_ZERO
-000066 025d .dw XT_FILL
-000067 1c20 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000068 ff06 .dw $ff06
-000069 7872
-00006a 622d
-00006b 6675 .db "rx-buf"
-00006c 0049 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-00006d 1c01 .dw DO_COLON
- PFA_RX_BUFFER:
-00006e 0088 .dw XT_RXQ_BUFFER
-00006f 1c36 .dw XT_DOCONDBRANCH
-000070 006e .dw PFA_RX_BUFFER
-000071 1c3d .dw XT_DOLITERAL
-000072 0071 .dw usart_rx_out
-000073 1c98 .dw XT_CFETCH
-000074 1cb1 .dw XT_DUP
-000075 1c3d .dw XT_DOLITERAL
-000076 0060 .dw usart_rx_data
-000077 1d9d .dw XT_PLUS
-000078 1c98 .dw XT_CFETCH
-000079 1cc4 .dw XT_SWAP
-00007a 1e2f .dw XT_1PLUS
-00007b 1c3d .dw XT_DOLITERAL
-00007c 000f .dw usart_rx_mask
-00007d 1e13 .dw XT_AND
-00007e 1c3d .dw XT_DOLITERAL
-00007f 0071 .dw usart_rx_out
-000080 1c8d .dw XT_CSTORE
-000081 1c20 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-000082 ff07 .dw $ff07
-000083 7872
-000084 2d3f
-000085 7562
-000086 0066 .db "rx?-buf",0
-000087 0068 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-000088 1c01 .dw DO_COLON
- PFA_RXQ_BUFFER:
-000089 0ad8 .dw XT_PAUSE
-00008a 1c3d .dw XT_DOLITERAL
-00008b 0071 .dw usart_rx_out
-00008c 1c98 .dw XT_CFETCH
-00008d 1c3d .dw XT_DOLITERAL
-00008e 0070 .dw usart_rx_in
-00008f 1c98 .dw XT_CFETCH
-000090 1d13 .dw XT_NOTEQUAL
-000091 1c20 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-000092 ff07 .dw $ff07
-000093 7874
-000094 702d
-000095 6c6f
-000096 006c .db "tx-poll",0
-000097 0082 .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-000098 1c01 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-000099 00a6 .dw XT_TXQ_POLL
-00009a 1c36 .dw XT_DOCONDBRANCH
-00009b 0099 .dw PFA_TX_POLL
- ; send to usart
-00009c 1c3d .dw XT_DOLITERAL
-00009d 002c .dw USART_DATA
-00009e 1c8d .dw XT_CSTORE
-00009f 1c20 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000a0 ff08 .dw $ff08
-0000a1 7874
-0000a2 2d3f
-0000a3 6f70
-0000a4 6c6c .db "tx?-poll"
-0000a5 0092 .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000a6 1c01 .dw DO_COLON
- PFA_TXQ_POLL:
-0000a7 0ad8 .dw XT_PAUSE
-0000a8 1c3d .dw XT_DOLITERAL
-0000a9 002b .dw USART_A
-0000aa 1c98 .dw XT_CFETCH
-0000ab 1c3d .dw XT_DOLITERAL
-0000ac 0020 .dw bm_USART_TXRD
-0000ad 1e13 .dw XT_AND
-0000ae 1c20 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000af ff04 .dw $ff04
-0000b0 6275
-0000b1 7272 .db "ubrr"
-0000b2 00a0 .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000b3 1c6f .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000b4 0082 .dw EE_UBRRVAL
-0000b5 0c3b .dw XT_EDEFERFETCH
-0000b6 0c45 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000b7 ff06 .dw $ff06
-0000b8 752b
-0000b9 6173
-0000ba 7472 .db "+usart"
-0000bb 00af .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000bc 1c01 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000bd 1c3d .dw XT_DOLITERAL
-0000be 0098 .dw USART_B_VALUE
-0000bf 1c3d .dw XT_DOLITERAL
-0000c0 002a .dw USART_B
-0000c1 1c8d .dw XT_CSTORE
-
-0000c2 1c3d .dw XT_DOLITERAL
-0000c3 0006 .dw USART_C_VALUE
-0000c4 1c3d .dw XT_DOLITERAL
-0000c5 00c0 .dw USART_C | bm_USARTC_en
-0000c6 1c8d .dw XT_CSTORE
-
-0000c7 00b3 .dw XT_UBRR
-0000c8 1cb1 .dw XT_DUP
-0000c9 1ef9 .dw XT_BYTESWAP
-0000ca 1c3d .dw XT_DOLITERAL
-0000cb 0040 .dw BAUDRATE_HIGH
-0000cc 1c8d .dw XT_CSTORE
-0000cd 1c3d .dw XT_DOLITERAL
-0000ce 0029 .dw BAUDRATE_LOW
-0000cf 1c8d .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000d0 005b .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000d1 1c20 .dw XT_EXIT
-
- ; settings for 1wire interface
- .equ OW_PORT=PORTB
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-0000d2 ff08 .dw $ff08
-0000d3 7731
-0000d4 722e
-0000d5 7365
-0000d6 7465 .db "1w.reset"
-0000d7 00b7 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-0000d8 00d9 .dw PFA_OW_RESET
- PFA_OW_RESET:
-0000d9 939a
-0000da 938a savetos
- ; setup to output
-0000db 9abc sbi OW_DDR, OW_BIT
- ; Pull output low
-0000dc 98c4 cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-0000dd ece0
-0000de e0f3
-0000df 9731
-0000e0 f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-0000e1 b71f in temp1, SREG
-0000e2 94f8 cli
- ; Pull output high
-0000e3 9ac4 sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-0000e4 98bc cbi OW_DDR, OW_BIT
-0000e5 e8e0
-0000e6 e0f0
-0000e7 9731
-0000e8 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-0000e9 b386 in tosl, OW_PIN
-0000ea ff84 sbrs tosl, OW_BIT
-0000eb ef9f ser tosh
- ; End critical timing period, enable interrupts
-0000ec bf1f out SREG, temp1
- ; release bus
-0000ed 98bc cbi OW_DDR, OW_BIT
-0000ee 98c4 cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-0000ef e4e0
-0000f0 e0f3
-0000f1 9731
-0000f2 f7f1 DELAY 416
- ; we now have the result flag in TOS
-0000f3 2f89 mov tosl, tosh
-0000f4 940c 1c05 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-0000f6 ff07 .dw $ff07
-0000f7 7731
-0000f8 732e
-0000f9 6f6c
-0000fa 0074 .db "1w.slot",0
-0000fb 00d2 .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-0000fc 00fd .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-0000fd 98c4 cbi OW_PORT, OW_BIT
-0000fe 9abc sbi OW_DDR, OW_BIT
- ; disable interrupts
-0000ff b71f in temp1, SREG
-000100 94f8 cli
-000101 e0ec
-000102 e0f0
-000103 9731
-000104 f7f1 DELAY 6 ; DELAY A
- ; check bit
-000105 9488 clc
-000106 9587 ror tosl
-000107 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000108 9ac4 sbi OW_PORT, OW_BIT
-000109 98bc cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-00010a e1e2
-00010b e0f0
-00010c 9731
-00010d f7f1 DELAY 9 ; wait DELAY E to sample
-00010e b306 in temp0, OW_PIN
-00010f fd04 sbrc temp0, OW_BIT
-000110 6880 ori tosl, $80
-
-000111 e6e6
-000112 e0f0
-000113 9731
-000114 f7f1 DELAY 51 ; DELAY B
-000115 9ac4 sbi OW_PORT, OW_BIT ; release bus
-000116 98bc cbi OW_DDR, OW_BIT
-000117 e0e4
-000118 e0f0
-000119 9731
-00011a f7f1 delay 2
- ; re-enable interrupts
-00011b bf1f out SREG, temp1
-00011c 940c 1c05 jmp_ DO_NEXT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 0ae1 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000072 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-00011e 920a st -Y, r0
-00011f b60f in r0, SREG
-000120 920a st -Y, r0
- .if (pclen==3)
- .endif
-000121 900f pop r0
-000122 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-000123 940a dec r0
- .if intvecsize == 1 ;
- .endif
-000124 2cb0 mov isrflag, r0
-000125 93ff push zh
-000126 93ef push zl
-000127 e7e2 ldi zl, low(intcnt)
-000128 e0f0 ldi zh, high(intcnt)
-000129 9406 lsr r0 ; we use byte addresses in the counter array, not words
-00012a 0de0 add zl, r0
-00012b 1df3 adc zh, zeroh
-00012c 8000 ld r0, Z
-00012d 9403 inc r0
-00012e 8200 st Z, r0
-00012f 91ef pop zl
-000130 91ff pop zh
-
-000131 9009 ld r0, Y+
-000132 be0f out SREG, r0
-000133 9009 ld r0, Y+
-000134 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000135 ff02 .dw $ff02
-000136 2b6d .db "m+"
-000137 00f6 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000138 1c01 .dw DO_COLON
- PFA_MPLUS:
-000139 0dee .dw XT_S2D
-00013a 019c .dw XT_DPLUS
-00013b 1c20 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00013c ff03 .dw $ff03
-00013d 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-00013e 002a .db "ud*"
-00013f 0135 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-000140 1c01 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000141 1cb1
-000142 1cff
-000143 1de0
-000144 1cd9 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000145 1cc4
-000146 1cf6
-000147 1de0
-000148 1ce1
-000149 1d9d
-00014a 1c20 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00014b ff04 .dw $ff04
-00014c 6d75
-00014d 7861 .db "umax"
-00014e 013c .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00014f 1c01 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-000150 05eb
-000151 1d5c .DW XT_2DUP,XT_ULESS
-000152 1c36 .dw XT_DOCONDBRANCH
-000153 0155 DEST(UMAX1)
-000154 1cc4 .DW XT_SWAP
-000155 1cd9 UMAX1: .DW XT_DROP
-000156 1c20 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000157 ff04 .dw $ff04
-000158 6d75
-000159 6e69 .db "umin"
-00015a 014b .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00015b 1c01 .dw DO_COLON
- PFA_UMIN:
- .endif
-00015c 05eb
-00015d 1d67 .DW XT_2DUP,XT_UGREATER
-00015e 1c36 .dw XT_DOCONDBRANCH
-00015f 0161 DEST(UMIN1)
-000160 1cc4 .DW XT_SWAP
-000161 1cd9 UMIN1: .DW XT_DROP
-000162 1c20 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000163 1c01 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000164 1c3d .dw XT_DOLITERAL
-000165 8000 .dw $8000
-000166 1e13 .dw XT_AND
-000167 1d1a .dw XT_ZEROEQUAL
-000168 1c36 .dw XT_DOCONDBRANCH
-000169 016c DEST(IMMEDIATEQ1)
-00016a 1fe7 .dw XT_ONE
-00016b 1c20 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00016c 1d4b .dw XT_TRUE
-00016d 1c20 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00016e ff0a .dw $ff0a
-00016f 616e
-000170 656d
-000171 663e
-000172 616c
-000173 7367 .db "name>flags"
-000174 0157 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000175 1c01 .dw DO_COLON
- PFA_NAME2FLAGS:
-000176 1fcb .dw XT_FETCHI ; skip to link field
-000177 1c3d .dw XT_DOLITERAL
-000178 ff00 .dw $ff00
-000179 1e13 .dw XT_AND
-00017a 1c20 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .elif AMFORTH_NRWW_SIZE > 4000
- .elif AMFORTH_NRWW_SIZE > 2000
- .include "dict/appl_2k.inc"
-
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-00017b ff03 .dw $ff03
-00017c 3264
-00017d 002a .db "d2*",0
-00017e 016e .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-00017f 0180 .dw PFA_D2STAR
- PFA_D2STAR:
-000180 9109 ld temp0, Y+
-000181 9119 ld temp1, Y+
-000182 0f00 lsl temp0
-000183 1f11 rol temp1
-000184 1f88 rol tosl
-000185 1f99 rol tosh
-000186 931a st -Y, temp1
-000187 930a st -Y, temp0
-000188 940c 1c05 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-00018a ff03 .dw $ff03
-00018b 3264
-00018c 002f .db "d2/",0
-00018d 017b .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-00018e 018f .dw PFA_D2SLASH
- PFA_D2SLASH:
-00018f 9109 ld temp0, Y+
-000190 9119 ld temp1, Y+
-000191 9595 asr tosh
-000192 9587 ror tosl
-000193 9517 ror temp1
-000194 9507 ror temp0
-000195 931a st -Y, temp1
-000196 930a st -Y, temp0
-000197 940c 1c05 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-000199 ff02 .dw $ff02
-00019a 2b64 .db "d+"
-00019b 018a .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-00019c 019d .dw PFA_DPLUS
- PFA_DPLUS:
-00019d 9129 ld temp2, Y+
-00019e 9139 ld temp3, Y+
-
-00019f 90e9 ld temp4, Y+
-0001a0 90f9 ld temp5, Y+
-0001a1 9149 ld temp6, Y+
-0001a2 9159 ld temp7, Y+
-
-0001a3 0f24 add temp2, temp6
-0001a4 1f35 adc temp3, temp7
-0001a5 1d8e adc tosl, temp4
-0001a6 1d9f adc tosh, temp5
-
-0001a7 933a st -Y, temp3
-0001a8 932a st -Y, temp2
-0001a9 940c 1c05 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-0001ab ff02 .dw $ff02
-0001ac 2d64 .db "d-"
-0001ad 0199 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-0001ae 01af .dw PFA_DMINUS
- PFA_DMINUS:
-0001af 9129 ld temp2, Y+
-0001b0 9139 ld temp3, Y+
-
-0001b1 90e9 ld temp4, Y+
-0001b2 90f9 ld temp5, Y+
-0001b3 9149 ld temp6, Y+
-0001b4 9159 ld temp7, Y+
-
-0001b5 1b42 sub temp6, temp2
-0001b6 0b53 sbc temp7, temp3
-0001b7 0ae8 sbc temp4, tosl
-0001b8 0af9 sbc temp5, tosh
-
-0001b9 935a st -Y, temp7
-0001ba 934a st -Y, temp6
-0001bb 01c7 movw tosl, temp4
-0001bc 940c 1c05 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-0001be ff07 .dw $ff07
-0001bf 6964
-0001c0 766e
-0001c1 7265
-0001c2 0074 .db "dinvert",0
-0001c3 01ab .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-0001c4 01c5 .dw PFA_DINVERT
- PFA_DINVERT:
-0001c5 9109 ld temp0, Y+
-0001c6 9119 ld temp1, Y+
-0001c7 9580 com tosl
-0001c8 9590 com tosh
-0001c9 9500 com temp0
-0001ca 9510 com temp1
-0001cb 931a st -Y, temp1
-0001cc 930a st -Y, temp0
-0001cd 940c 1c05 jmp_ DO_NEXT
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-0001cf ff02 .dw $ff02
-0001d0 2e75 .db "u."
-0001d1 01be .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-0001d2 1c01 .dw DO_COLON
- PFA_UDOT:
- .endif
-0001d3 1d54 .dw XT_ZERO
-0001d4 07b1 .dw XT_UDDOT
-0001d5 1c20 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-0001d6 ff03 .dw $ff03
-0001d7 2e75
-0001d8 0072 .db "u.r",0
-0001d9 01cf .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-0001da 1c01 .dw DO_COLON
- PFA_UDOTR:
- .endif
-0001db 1d54 .dw XT_ZERO
-0001dc 1cc4 .dw XT_SWAP
-0001dd 07ba .dw XT_UDDOTR
-0001de 1c20 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-0001df ff0d .dw $ff0d
-0001e0 6873
-0001e1 776f
-0001e2 772d
-0001e3 726f
-0001e4 6c64
-0001e5 7369
-0001e6 0074 .db "show-wordlist",0
-0001e7 01d6 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-0001e8 1c01 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-0001e9 1c3d .dw XT_DOLITERAL
-0001ea 01ee .dw XT_SHOWWORD
-0001eb 1cc4 .dw XT_SWAP
-0001ec 0cde .dw XT_TRAVERSEWORDLIST
-0001ed 1c20 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-0001ee 1c01 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-0001ef 0cf9 .dw XT_NAME2STRING
-0001f0 0827 .dw XT_ITYPE
-0001f1 0869 .dw XT_SPACE ; ( -- addr n)
-0001f2 1d4b .dw XT_TRUE
-0001f3 1c20 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-0001f4 ff05 .dw $ff05
-0001f5 6f77
-0001f6 6472
-0001f7 0073 .db "words",0
-0001f8 01df .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-0001f9 1c01 .dw DO_COLON
- PFA_WORDS:
- .endif
-0001fa 1c3d .dw XT_DOLITERAL
-0001fb 0042 .dw CFG_ORDERLISTLEN+2
-0001fc 1f5f .dw XT_FETCHE
-0001fd 01e8 .dw XT_SHOWWORDLIST
-0001fe 1c20 .dw XT_EXIT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-0001ff ff04 .dw $ff04
-000200 692b
-000201 746e .db "+int"
-000202 01f4 .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-000203 0204 .dw PFA_INTON
- PFA_INTON:
-000204 9478 sei
-000205 940c 1c05 jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-000207 ff04 .dw $ff04
-000208 692d
-000209 746e .db "-int"
-00020a 01ff .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-00020b 020c .dw PFA_INTOFF
- PFA_INTOFF:
-00020c 94f8 cli
-00020d 940c 1c05 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-00020f ff04 .dw $ff04
-000210 6e69
-000211 2174 .db "int!"
-000212 0207 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-000213 1c01 .dw DO_COLON
- PFA_INTSTORE:
-000214 1c3d .dw XT_DOLITERAL
-000215 0000 .dw intvec
-000216 1d9d .dw XT_PLUS
-000217 1f3b .dw XT_STOREE
-000218 1c20 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-000219 ff04 .dw $ff04
-00021a 6e69
-00021b 4074 .db "int@"
-00021c 020f .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-00021d 1c01 .dw DO_COLON
- PFA_INTFETCH:
-00021e 1c3d .dw XT_DOLITERAL
-00021f 0000 .dw intvec
-000220 1d9d .dw XT_PLUS
-000221 1f5f .dw XT_FETCHE
-000222 1c20 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-000223 ff08 .dw $ff08
-000224 6e69
-000225 2d74
-000226 7274
-000227 7061 .db "int-trap"
-000228 0219 .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-000229 022a .dw PFA_INTTRAP
- PFA_INTTRAP:
-00022a 2eb8 mov isrflag, tosl
-00022b 9189
-00022c 9199 loadtos
-00022d 940c 1c05 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-00022f 1c01 .dw DO_COLON
- PFA_ISREXEC:
-000230 021d .dw XT_INTFETCH
-000231 1c2a .dw XT_EXECUTE
-000232 0234 .dw XT_ISREND
-000233 1c20 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-000234 0235 .dw PFA_ISREND
- PFA_ISREND:
-000235 d002 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-000236 940c 1c05 jmp_ DO_NEXT
- PFA_ISREND1:
-000238 9518 reti
- .endif
-
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-000239 ff04 .dw $ff04
-00023a 6970
-00023b 6b63 .db "pick"
-00023c 0223 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-00023d 1c01 .dw DO_COLON
- PFA_PICK:
- .endif
-00023e 1e2f .dw XT_1PLUS
-00023f 05dd .dw XT_CELLS
-000240 1e8d .dw XT_SP_FETCH
-000241 1d9d .dw XT_PLUS
-000242 1c79 .dw XT_FETCH
-000243 1c20 .dw XT_EXIT
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-000244 0002 .dw $0002
-000245 222e .db ".",$22
-000246 0239 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-000247 1c01 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-000248 024f .dw XT_SQUOTE
-000249 02a3 .dw XT_COMPILE
-00024a 0827 .dw XT_ITYPE
-00024b 1c20 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-00024c 0002 .dw $0002
-00024d 2273 .db "s",$22
-00024e 0244 .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-00024f 1c01 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-000250 1c3d .dw XT_DOLITERAL
-000251 0022 .dw 34 ; 0x22
-000252 0a0e .dw XT_PARSE ; ( -- addr n)
-000253 05d0 .dw XT_STATE
-000254 1c79 .dw XT_FETCH
-000255 1c36 .dw XT_DOCONDBRANCH
-000256 0258 DEST(PFA_SQUOTE1)
-000257 02cf .dw XT_SLITERAL
- PFA_SQUOTE1:
-000258 1c20 .dw XT_EXIT
-
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-000259 ff04 .dw $ff04
-00025a 6966
-00025b 6c6c .db "fill"
-00025c 024c .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-00025d 1c01 .dw DO_COLON
- PFA_FILL:
-00025e 1ce1 .dw XT_ROT
-00025f 1ce1 .dw XT_ROT
-000260 1cb9
-000261 1c36 .dw XT_QDUP,XT_DOCONDBRANCH
-000262 026a DEST(PFA_FILL2)
-000263 0de5 .dw XT_BOUNDS
-000264 1e9b .dw XT_DODO
- PFA_FILL1:
-000265 1cb1 .dw XT_DUP
-000266 1eac .dw XT_I
-000267 1c8d .dw XT_CSTORE ; ( -- c c-addr)
-000268 1ec9 .dw XT_DOLOOP
-000269 0265 .dw PFA_FILL1
- PFA_FILL2:
-00026a 1cd9 .dw XT_DROP
-00026b 1c20 .dw XT_EXIT
- .include "dict/compiler1.inc"
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-00026c ff06 .dw $ff06
-00026d 656e
-00026e 6577
-00026f 7473 .db "newest"
-000270 0259 .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-000271 1c48 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-000272 0087 .dw ram_newest
-
- .dseg
-000087 ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-000273 ff06 .dw $ff06
-000274 616c
-000275 6574
-000276 7473 .db "latest"
-000277 026c .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000278 1c48 .dw PFA_DOVARIABLE
- PFA_LATEST:
-000279 008b .dw ram_latest
-
- .dseg
-00008b ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-00027a ff08 .dw $ff08
-00027b 6328
-00027c 6572
-00027d 7461
-00027e 2965 .db "(create)"
-00027f 0273 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-000280 1c01 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-000281 0a3b
-000282 03d7 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-000283 1cb1
-000284 0271
-000285 05e3
-000286 1c81 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000287 03bc
-000288 0271
-000289 1c81 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-00028a 1c20 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-00028b 0001 .dw $0001
-00028c 005c .db $5c,0
-00028d 027a .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-00028e 1c01 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-00028f 0a22 .dw XT_SOURCE
-000290 1cf0 .dw XT_NIP
-000291 0604 .dw XT_TO_IN
-000292 1c81 .dw XT_STORE
-000293 1c20 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-000294 0001 .dw $0001
-000295 0028 .db "(" ,0
-000296 028b .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000297 1c01 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000298 1c3d .dw XT_DOLITERAL
-000299 0029 .dw ')'
-00029a 0a0e .dw XT_PARSE
-00029b 05f4 .dw XT_2DROP
-00029c 1c20 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-00029d ff07 .dw $ff07
-00029e 6f63
-00029f 706d
-0002a0 6c69
-0002a1 0065 .db "compile",0
-0002a2 0294 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-0002a3 1c01 .dw DO_COLON
- PFA_COMPILE:
- .endif
-0002a4 1cf6 .dw XT_R_FROM
-0002a5 1cb1 .dw XT_DUP
-0002a6 0c32 .dw XT_ICELLPLUS
-0002a7 1cff .dw XT_TO_R
-0002a8 1fcb .dw XT_FETCHI
-0002a9 02ae .dw XT_COMMA
-0002aa 1c20 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-0002ab ff01 .dw $ff01
-0002ac 002c .db ',',0 ; ,
-0002ad 029d .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-0002ae 1c01 .dw DO_COLON
- PFA_COMMA:
-0002af 0634 .dw XT_DP
-0002b0 1f73 .dw XT_STOREI
-0002b1 0634 .dw XT_DP
-0002b2 1e2f .dw XT_1PLUS
-0002b3 0c20 .dw XT_DOTO
-0002b4 0635 .dw PFA_DP
-0002b5 1c20 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-0002b6 0003 .dw $0003
-0002b7 275b
-0002b8 005d .db "[']",0
-0002b9 02ab .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-0002ba 1c01 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-0002bb 0891 .dw XT_TICK
-0002bc 02c4 .dw XT_LITERAL
-0002bd 1c20 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-0002be 0007 .dw $0007
-0002bf 696c
-0002c0 6574
-0002c1 6172
-0002c2 006c .db "literal",0
-0002c3 02b6 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-0002c4 1c01 .dw DO_COLON
- PFA_LITERAL:
- .endif
-0002c5 02a3 .DW XT_COMPILE
-0002c6 1c3d .DW XT_DOLITERAL
-0002c7 02ae .DW XT_COMMA
-0002c8 1c20 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-0002c9 0008 .dw $0008
-0002ca 6c73
-0002cb 7469
-0002cc 7265
-0002cd 6c61 .db "sliteral"
-0002ce 02be .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-0002cf 1c01 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-0002d0 02a3 .dw XT_COMPILE
-0002d1 07f4 .dw XT_DOSLITERAL ; ( -- addr n)
-0002d2 0802 .dw XT_SCOMMA
-0002d3 1c20 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-0002d4 1c01 .dw DO_COLON
- PFA_GMARK:
-0002d5 0634 .dw XT_DP
-0002d6 02a3 .dw XT_COMPILE
-0002d7 ffff .dw -1 ; ffff does not erase flash
-0002d8 1c20 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-0002d9 1c01 .dw DO_COLON
- PFA_GRESOLVE:
-0002da 0bde .dw XT_QSTACK
-0002db 0634 .dw XT_DP
-0002dc 1cc4 .dw XT_SWAP
-0002dd 1f73 .dw XT_STOREI
-0002de 1c20 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-0002df 1c01 .dw DO_COLON
- PFA_LMARK:
-0002e0 0634 .dw XT_DP
-0002e1 1c20 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-0002e2 1c01 .dw DO_COLON
- PFA_LRESOLVE:
-0002e3 0bde .dw XT_QSTACK
-0002e4 02ae .dw XT_COMMA
-0002e5 1c20 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-0002e6 0005 .dw $0005
-0002e7 6861
-0002e8 6165
-0002e9 0064 .db "ahead",0
-0002ea 02c9 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-0002eb 1c01 .dw DO_COLON
- PFA_AHEAD:
- .endif
-0002ec 02a3 .dw XT_COMPILE
-0002ed 1c2f .dw XT_DOBRANCH
-0002ee 02d4 .dw XT_GMARK
-0002ef 1c20 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-0002f0 0002 .dw $0002
-0002f1 6669 .db "if"
-0002f2 02e6 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-0002f3 1c01 .dw DO_COLON
- PFA_IF:
- .endif
-0002f4 02a3 .dw XT_COMPILE
-0002f5 1c36 .dw XT_DOCONDBRANCH
-0002f6 02d4 .dw XT_GMARK
-0002f7 1c20 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-0002f8 0004 .dw $0004
-0002f9 6c65
-0002fa 6573 .db "else"
-0002fb 02f0 .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-0002fc 1c01 .dw DO_COLON
- PFA_ELSE:
- .endif
-0002fd 02a3 .dw XT_COMPILE
-0002fe 1c2f .dw XT_DOBRANCH
-0002ff 02d4 .dw XT_GMARK
-000300 1cc4 .dw XT_SWAP
-000301 02d9 .dw XT_GRESOLVE
-000302 1c20 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-000303 0004 .dw $0004
-000304 6874
-000305 6e65 .db "then"
-000306 02f8 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-000307 1c01 .dw DO_COLON
- PFA_THEN:
- .endif
-000308 02d9 .dw XT_GRESOLVE
-000309 1c20 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-00030a 0005 .dw $0005
-00030b 6562
-00030c 6967
-00030d 006e .db "begin",0
-00030e 0303 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-00030f 1c01 .dw DO_COLON
- PFA_BEGIN:
- .endif
-000310 02df .dw XT_LMARK
-000311 1c20 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-000312 0005 .dw $0005
-000313 6877
-000314 6c69
-000315 0065 .db "while",0
-000316 030a .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-000317 1c01 .dw DO_COLON
- PFA_WHILE:
- .endif
-000318 02f3 .dw XT_IF
-000319 1cc4 .dw XT_SWAP
-00031a 1c20 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-00031b 0006 .dw $0006
-00031c 6572
-00031d 6570
-00031e 7461 .db "repeat"
-00031f 0312 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-000320 1c01 .dw DO_COLON
- PFA_REPEAT:
- .endif
-000321 0334 .dw XT_AGAIN
-000322 0307 .dw XT_THEN
-000323 1c20 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-000324 0005 .dw $0005
-000325 6e75
-000326 6974
-000327 006c .db "until",0
-000328 031b .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-000329 1c01 .dw DO_COLON
- PFA_UNTIL:
- .endif
-00032a 1c3d .dw XT_DOLITERAL
-00032b 1c36 .dw XT_DOCONDBRANCH
-00032c 02ae .dw XT_COMMA
-
-00032d 02e2 .dw XT_LRESOLVE
-00032e 1c20 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-00032f 0005 .dw $0005
-000330 6761
-000331 6961
-000332 006e .db "again",0
-000333 0324 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-000334 1c01 .dw DO_COLON
- PFA_AGAIN:
- .endif
-000335 02a3 .dw XT_COMPILE
-000336 1c2f .dw XT_DOBRANCH
-000337 02e2 .dw XT_LRESOLVE
-000338 1c20 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-000339 0002 .dw $0002
-00033a 6f64 .db "do"
-00033b 032f .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-00033c 1c01 .dw DO_COLON
- PFA_DO:
-
- .endif
-00033d 02a3 .dw XT_COMPILE
-00033e 1e9b .dw XT_DODO
-00033f 02df .dw XT_LMARK
-000340 1d54 .dw XT_ZERO
-000341 0397 .dw XT_TO_L
-000342 1c20 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-000343 0004 .dw $0004
-000344 6f6c
-000345 706f .db "loop"
-000346 0339 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000347 1c01 .dw DO_COLON
- PFA_LOOP:
- .endif
-000348 02a3 .dw XT_COMPILE
-000349 1ec9 .dw XT_DOLOOP
-00034a 037e .dw XT_ENDLOOP
-00034b 1c20 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-00034c 0005 .dw $0005
-00034d 6c2b
-00034e 6f6f
-00034f 0070 .db "+loop",0
-000350 0343 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-000351 1c01 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-000352 02a3 .dw XT_COMPILE
-000353 1eba .dw XT_DOPLUSLOOP
-000354 037e .dw XT_ENDLOOP
-000355 1c20 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-000356 0005 .dw $0005
-000357 656c
-000358 7661
-000359 0065 .db "leave",0
-00035a 034c .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-00035b 1c01 .dw DO_COLON
- PFA_LEAVE:
- .endif
-00035c 02a3
-00035d 1ed4 .DW XT_COMPILE,XT_UNLOOP
-00035e 02eb
-00035f 0397
-000360 1c20 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-000361 0003 .dw $0003
-000362 643f
-000363 006f .db "?do",0
-000364 0356 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000365 1c01 .dw DO_COLON
- PFA_QDO:
- .endif
-000366 02a3 .dw XT_COMPILE
-000367 036d .dw XT_QDOCHECK
-000368 02f3 .dw XT_IF
-000369 033c .dw XT_DO
-00036a 1cc4 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-00036b 0397 .dw XT_TO_L ; then follows at the end.
-00036c 1c20 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00036d 1c01 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00036e 05eb .dw XT_2DUP
-00036f 1fe0 .dw XT_EQUAL
-000370 1cb1 .dw XT_DUP
-000371 1cff .dw XT_TO_R
-000372 1c36 .dw XT_DOCONDBRANCH
-000373 0375 DEST(PFA_QDOCHECK1)
-000374 05f4 .dw XT_2DROP
- PFA_QDOCHECK1:
-000375 1cf6 .dw XT_R_FROM
-000376 1dfd .dw XT_INVERT
-000377 1c20 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000378 ff07 .dw $ff07
-000379 6e65
-00037a 6c64
-00037b 6f6f
-00037c 0070 .db "endloop",0
-00037d 0361 .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-00037e 1c01 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-00037f 02e2 .DW XT_LRESOLVE
-000380 038b
-000381 1cb9
-000382 1c36 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-000383 0387 DEST(LOOP2)
-000384 0307 .DW XT_THEN
-000385 1c2f .dw XT_DOBRANCH
-000386 0380 DEST(LOOP1)
-000387 1c20 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000388 ff02 .dw $ff02
-000389 3e6c .db "l>"
-00038a 0378 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-00038b 1c01 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-00038c 03aa .dw XT_LP
-00038d 1c79 .dw XT_FETCH
-00038e 1c79 .dw XT_FETCH
-00038f 1c3d .dw XT_DOLITERAL
-000390 fffe .dw -2
-000391 03aa .dw XT_LP
-000392 1e65 .dw XT_PLUSSTORE
-000393 1c20 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-000394 ff02 .dw $ff02
-000395 6c3e .db ">l"
-000396 0388 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000397 1c01 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000398 1fec .dw XT_TWO
-000399 03aa .dw XT_LP
-00039a 1e65 .dw XT_PLUSSTORE
-00039b 03aa .dw XT_LP
-00039c 1c79 .dw XT_FETCH
-00039d 1c81 .dw XT_STORE
-00039e 1c20 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-00039f ff03 .dw $ff03
-0003a0 706c
-0003a1 0030 .db "lp0",0
-0003a2 0394 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-0003a3 1c6f .dw PFA_DOVALUE1
- PFA_LP0:
-0003a4 0036 .dw CFG_LP0
-0003a5 0c3b .dw XT_EDEFERFETCH
-0003a6 0c45 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-0003a7 ff02 .dw $ff02
-0003a8 706c .db "lp"
-0003a9 039f .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-0003aa 1c48 .dw PFA_DOVARIABLE
- PFA_LP:
-0003ab 008d .dw ram_lp
-
- .dseg
-00008d ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-0003ac ff06 .dw $ff06
-0003ad 7263
-0003ae 6165
-0003af 6574 .db "create"
-0003b0 03a7 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-0003b1 1c01 .dw DO_COLON
- PFA_CREATE:
- .endif
-0003b2 0280 .dw XT_DOCREATE
-0003b3 03e0 .dw XT_REVEAL
-0003b4 02a3 .dw XT_COMPILE
-0003b5 1c52 .dw PFA_DOCONSTANT
-0003b6 1c20 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-0003b7 ff06 .dw $ff06
-0003b8 6568
-0003b9 6461
-0003ba 7265 .db "header"
-0003bb 03ac .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-0003bc 1c01 .dw DO_COLON
- PFA_HEADER:
-0003bd 0634 .dw XT_DP ; the new Name Field
-0003be 1cff .dw XT_TO_R
-0003bf 1cff .dw XT_TO_R ; ( R: NFA WID )
-0003c0 1cb1 .dw XT_DUP
-0003c1 1d28 .dw XT_GREATERZERO
-0003c2 1c36 .dw XT_DOCONDBRANCH
-0003c3 03ce .dw PFA_HEADER1
-0003c4 1cb1 .dw XT_DUP
-0003c5 1c3d .dw XT_DOLITERAL
-0003c6 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-0003c7 1e1c .dw XT_OR
-0003c8 0806 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-0003c9 1cf6 .dw XT_R_FROM
-0003ca 1f5f .dw XT_FETCHE
-0003cb 02ae .dw XT_COMMA
-0003cc 1cf6 .dw XT_R_FROM
-0003cd 1c20 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-0003ce 1c3d .dw XT_DOLITERAL
-0003cf fff0 .dw -16
-0003d0 08c8 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-0003d1 ff07 .dw $ff07
-0003d2 6c77
-0003d3 6373
-0003d4 706f
-0003d5 0065 .db "wlscope",0
-0003d6 03b7 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-0003d7 0c9a .dw PFA_DODEFER1
- PFA_WLSCOPE:
-0003d8 0032 .dw CFG_WLSCOPE
-0003d9 0c3b .dw XT_EDEFERFETCH
-0003da 0c45 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-0003db ff06 .dw $ff06
-0003dc 6572
-0003dd 6576
-0003de 6c61 .db "reveal"
-0003df 03d1 .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-0003e0 1c01 .dw DO_COLON
- PFA_REVEAL:
- .endif
-0003e1 0271
-0003e2 05e3
-0003e3 1c79 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-0003e4 1cb9
-0003e5 1c36 .DW XT_QDUP,XT_DOCONDBRANCH
-0003e6 03eb DEST(REVEAL1)
-0003e7 0271
-0003e8 1c79
-0003e9 1cc4
-0003ea 1f3b .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-0003eb 1c20 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-0003ec 0005 .dw $0005
-0003ed 6f64
-0003ee 7365
-0003ef 003e .db "does>",0
-0003f0 03db .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-0003f1 1c01 .dw DO_COLON
- PFA_DOES:
-0003f2 02a3 .dw XT_COMPILE
-0003f3 0404 .dw XT_DODOES
-0003f4 02a3 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-0003f5 940e .dw $940e ; the address of this compiled
-0003f6 02a3 .dw XT_COMPILE ; code will replace the XT of the
-0003f7 03f9 .dw DO_DODOES ; word that CREATE created
-0003f8 1c20 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-0003f9 939a
-0003fa 938a savetos
-0003fb 01cb movw tosl, wl
-0003fc 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-0003fd 917f pop wh
-0003fe 916f pop wl
-
-0003ff 93bf push XH
-000400 93af push XL
-000401 01db movw XL, wl
-000402 940c 1c05 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-000404 1c01 .dw DO_COLON
- PFA_DODOES:
-000405 1cf6 .dw XT_R_FROM
-000406 0271 .dw XT_NEWEST
-000407 05e3 .dw XT_CELLPLUS
-000408 1c79 .dw XT_FETCH
-000409 1f5f .dw XT_FETCHE
-00040a 0d05 .dw XT_NFA2CFA
-00040b 1f73 .dw XT_STOREI
-00040c 1c20 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-00040d ff01 .dw $ff01
-00040e 003a .db ":",0
-00040f 03ec .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-000410 1c01 .dw DO_COLON
- PFA_COLON:
- .endif
-000411 0280 .dw XT_DOCREATE
-000412 041b .dw XT_COLONNONAME
-000413 1cd9 .dw XT_DROP
-000414 1c20 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-000415 ff07 .dw $ff07
-000416 6e3a
-000417 6e6f
-000418 6d61
-000419 0065 .db ":noname",0
-00041a 040d .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-00041b 1c01 .dw DO_COLON
- PFA_COLONNONAME:
-00041c 0634 .dw XT_DP
-00041d 1cb1 .dw XT_DUP
-00041e 0278 .dw XT_LATEST
-00041f 1c81 .dw XT_STORE
-
-000420 02a3 .dw XT_COMPILE
-000421 1c01 .dw DO_COLON
-
-000422 0430 .dw XT_RBRACKET
-000423 1c20 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-000424 0001 .dw $0001
-000425 003b .db $3b,0
-000426 0415 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-000427 1c01 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-000428 02a3 .dw XT_COMPILE
-000429 1c20 .dw XT_EXIT
-00042a 0438 .dw XT_LBRACKET
-00042b 03e0 .dw XT_REVEAL
-00042c 1c20 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-00042d ff01 .dw $ff01
-00042e 005d .db "]",0
-00042f 0424 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-000430 1c01 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-000431 1fe7 .dw XT_ONE
-000432 05d0 .dw XT_STATE
-000433 1c81 .dw XT_STORE
-000434 1c20 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-000435 0001 .dw $0001
-000436 005b .db "[",0
-000437 042d .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-000438 1c01 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-000439 1d54 .dw XT_ZERO
-00043a 05d0 .dw XT_STATE
-00043b 1c81 .dw XT_STORE
-00043c 1c20 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-00043d ff08 .dw $ff08
-00043e 6176
-00043f 6972
-000440 6261
-000441 656c .db "variable"
-000442 0435 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-000443 1c01 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-000444 0645 .dw XT_HERE
-000445 044f .dw XT_CONSTANT
-000446 1fec .dw XT_TWO
-000447 064e .dw XT_ALLOT
-000448 1c20 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-000449 ff08 .dw $ff08
-00044a 6f63
-00044b 736e
-00044c 6174
-00044d 746e .db "constant"
-00044e 043d .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-00044f 1c01 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-000450 0280 .dw XT_DOCREATE
-000451 03e0 .dw XT_REVEAL
-000452 02a3 .dw XT_COMPILE
-000453 1c48 .dw PFA_DOVARIABLE
-000454 02ae .dw XT_COMMA
-000455 1c20 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-000456 ff04 .dw $ff04
-000457 7375
-000458 7265 .db "user"
-000459 0449 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-00045a 1c01 .dw DO_COLON
- PFA_USER:
-00045b 0280 .dw XT_DOCREATE
-00045c 03e0 .dw XT_REVEAL
-
-00045d 02a3 .dw XT_COMPILE
-00045e 1c58 .dw PFA_DOUSER
-00045f 02ae .dw XT_COMMA
-000460 1c20 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-000461 0007 .dw $0007
-000462 6572
-000463 7563
-000464 7372
-000465 0065 .db "recurse",0
-000466 0456 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000467 1c01 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000468 0278 .dw XT_LATEST
-000469 1c79 .dw XT_FETCH
-00046a 02ae .dw XT_COMMA
-00046b 1c20 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-00046c ff09 .dw $ff09
-00046d 6d69
-00046e 656d
-00046f 6964
-000470 7461
-000471 0065 .db "immediate",0
-000472 0461 .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-000473 1c01 .dw DO_COLON
- PFA_IMMEDIATE:
-000474 0515 .dw XT_GET_CURRENT
-000475 1f5f .dw XT_FETCHE
-000476 1cb1 .dw XT_DUP
-000477 1fcb .dw XT_FETCHI
-000478 1c3d .dw XT_DOLITERAL
-000479 7fff .dw $7fff
-00047a 1e13 .dw XT_AND
-00047b 1cc4 .dw XT_SWAP
-00047c 1f73 .dw XT_STOREI
-00047d 1c20 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-00047e 0006 .dw $0006
-00047f 635b
-000480 6168
-000481 5d72 .db "[char]"
-000482 046c .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-000483 1c01 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-000484 02a3 .dw XT_COMPILE
-000485 1c3d .dw XT_DOLITERAL
-000486 0971 .dw XT_CHAR
-000487 02ae .dw XT_COMMA
-000488 1c20 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-000489 0006 .dw $0006
-00048a 6261
-00048b 726f
-00048c 2274 .db "abort",'"'
-00048d 047e .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-00048e 1c01 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-00048f 024f .dw XT_SQUOTE
-000490 02a3 .dw XT_COMPILE
-000491 04a0 .dw XT_QABORT
-000492 1c20 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-000493 ff05 .dw $ff05
-000494 6261
-000495 726f
-000496 0074 .db "abort",0
-000497 0489 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000498 1c01 .dw DO_COLON
- PFA_ABORT:
- .endif
-000499 1d4b .dw XT_TRUE
-00049a 08c8 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-00049b ff06 .dw $ff06
-00049c 613f
-00049d 6f62
-00049e 7472 .db "?abort"
-00049f 0493 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-0004a0 1c01 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-0004a1 1ce1
-0004a2 1c36 .DW XT_ROT,XT_DOCONDBRANCH
-0004a3 04a6 DEST(QABO1)
-0004a4 0827
-0004a5 0498 .DW XT_ITYPE,XT_ABORT
-0004a6 05f4
-0004a7 1c20 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-0004a8 ff09 .dw $ff09
-0004a9 6567
-0004aa 2d74
-0004ab 7473
-0004ac 6361
-0004ad 006b .db "get-stack",0
-0004ae 049b .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-0004af 1c01 .dw DO_COLON
- .endif
-0004b0 1cb1 .dw XT_DUP
-0004b1 05e3 .dw XT_CELLPLUS
-0004b2 1cc4 .dw XT_SWAP
-0004b3 1f5f .dw XT_FETCHE
-0004b4 1cb1 .dw XT_DUP
-0004b5 1cff .dw XT_TO_R
-0004b6 1d54 .dw XT_ZERO
-0004b7 1cc4 .dw XT_SWAP ; go from bigger to smaller addresses
-0004b8 036d .dw XT_QDOCHECK
-0004b9 1c36 .dw XT_DOCONDBRANCH
-0004ba 04c6 DEST(PFA_N_FETCH_E2)
-0004bb 1e9b .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-0004bc 1eac .dw XT_I
-0004bd 1e35 .dw XT_1MINUS
-0004be 05dd .dw XT_CELLS ; ( -- ee-addr i*2 )
-0004bf 1ccf .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-0004c0 1d9d .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-0004c1 1f5f .dw XT_FETCHE ;( -- ee-addr item_i )
-0004c2 1cc4 .dw XT_SWAP ;( -- item_i ee-addr )
-0004c3 1d4b .dw XT_TRUE ; shortcut for -1
-0004c4 1eba .dw XT_DOPLUSLOOP
-0004c5 04bc DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-0004c6 05f4 .dw XT_2DROP
-0004c7 1cf6 .dw XT_R_FROM
-0004c8 1c20 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-0004c9 ff09 .dw $ff09
-0004ca 6573
-0004cb 2d74
-0004cc 7473
-0004cd 6361
-0004ce 006b .db "set-stack",0
-0004cf 04a8 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-0004d0 1c01 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-0004d1 1ccf .dw XT_OVER
-0004d2 1d21 .dw XT_ZEROLESS
-0004d3 1c36 .dw XT_DOCONDBRANCH
-0004d4 04d8 DEST(PFA_SET_STACK0)
-0004d5 1c3d .dw XT_DOLITERAL
-0004d6 fffc .dw -4
-0004d7 08c8 .dw XT_THROW
- PFA_SET_STACK0:
-0004d8 05eb .dw XT_2DUP
-0004d9 1f3b .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-0004da 1cc4 .dw XT_SWAP
-0004db 1d54 .dw XT_ZERO
-0004dc 036d .dw XT_QDOCHECK
-0004dd 1c36 .dw XT_DOCONDBRANCH
-0004de 04e5 DEST(PFA_SET_STACK2)
-0004df 1e9b .dw XT_DODO
- PFA_SET_STACK1:
-0004e0 05e3 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-0004e1 05fc .dw XT_TUCK ; ( -- e-addr i_x e-addr
-0004e2 1f3b .dw XT_STOREE
-0004e3 1ec9 .dw XT_DOLOOP
-0004e4 04e0 DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-0004e5 1cd9 .dw XT_DROP
-0004e6 1c20 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-0004e7 ff09 .dw $ff09
-0004e8 616d
-0004e9 2d70
-0004ea 7473
-0004eb 6361
-0004ec 006b .db "map-stack",0
-0004ed 04c9 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-0004ee 1c01 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-0004ef 1cb1 .dw XT_DUP
-0004f0 05e3 .dw XT_CELLPLUS
-0004f1 1cc4 .dw XT_SWAP
-0004f2 1f5f .dw XT_FETCHE
-0004f3 05dd .dw XT_CELLS
-0004f4 0de5 .dw XT_BOUNDS
-0004f5 036d .dw XT_QDOCHECK
-0004f6 1c36 .dw XT_DOCONDBRANCH
-0004f7 050a DEST(PFA_MAPSTACK3)
-0004f8 1e9b .dw XT_DODO
- PFA_MAPSTACK1:
-0004f9 1eac .dw XT_I
-0004fa 1f5f .dw XT_FETCHE ; -- i*x XT id
-0004fb 1cc4 .dw XT_SWAP
-0004fc 1cff .dw XT_TO_R
-0004fd 1d08 .dw XT_R_FETCH
-0004fe 1c2a .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-0004ff 1cb9 .dw XT_QDUP
-000500 1c36 .dw XT_DOCONDBRANCH
-000501 0506 DEST(PFA_MAPSTACK2)
-000502 1cf6 .dw XT_R_FROM
-000503 1cd9 .dw XT_DROP
-000504 1ed4 .dw XT_UNLOOP
-000505 1c20 .dw XT_EXIT
- PFA_MAPSTACK2:
-000506 1cf6 .dw XT_R_FROM
-000507 1fec .dw XT_TWO
-000508 1eba .dw XT_DOPLUSLOOP
-000509 04f9 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-00050a 1cd9 .dw XT_DROP
-00050b 1d54 .dw XT_ZERO
-00050c 1c20 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-00050d ff0b .dw $ff0b
-00050e 6567
-00050f 2d74
-000510 7563
-000511 7272
-000512 6e65
-000513 0074 .db "get-current",0
-000514 04e7 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-000515 1c01 .dw DO_COLON
- PFA_GET_CURRENT:
-000516 1c3d .dw XT_DOLITERAL
-000517 003c .dw CFG_CURRENT
-000518 1f5f .dw XT_FETCHE
-000519 1c20 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-00051a ff09 .dw $ff09
-00051b 6567
-00051c 2d74
-00051d 726f
-00051e 6564
-00051f 0072 .db "get-order",0
-000520 050d .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-000521 1c01 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-000522 1c3d .dw XT_DOLITERAL
-000523 0040 .dw CFG_ORDERLISTLEN
-000524 04af .dw XT_GET_STACK
-000525 1c20 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-000526 ff09 .dw $ff09
-000527 6663
-000528 2d67
-000529 726f
-00052a 6564
-00052b 0072 .db "cfg-order",0
-00052c 051a .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-00052d 1c48 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-00052e 0040 .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-00052f ff07 .dw $ff07
-000530 6f63
-000531 706d
-000532 7261
-000533 0065 .db "compare",0
-000534 0526 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-000535 0536 .dw PFA_COMPARE
- PFA_COMPARE:
-000536 93bf push xh
-000537 93af push xl
-000538 018c movw temp0, tosl
-000539 9189
-00053a 9199 loadtos
-00053b 01dc movw xl, tosl
-00053c 9189
-00053d 9199 loadtos
-00053e 019c movw temp2, tosl
-00053f 9189
-000540 9199 loadtos
-000541 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-000542 90ed ld temp4, X+
-000543 90f1 ld temp5, Z+
-000544 14ef cp temp4, temp5
-000545 f451 brne PFA_COMPARE_NOTEQUAL
-000546 950a dec temp0
-000547 f019 breq PFA_COMPARE_ENDREACHED2
-000548 952a dec temp2
-000549 f7c1 brne PFA_COMPARE_LOOP
-00054a c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-00054b 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-00054c 2b02 or temp0, temp2
-00054d f411 brne PFA_COMPARE_CHECKLASTCHAR
-00054e 2788 clr tosl
-00054f c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-000550 ef8f ser tosl
-000551 c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000552 2f98 mov tosh, tosl
-000553 91af pop xl
-000554 91bf pop xh
-000555 940c 1c05 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000557 ff07 .dw $ff07
-000558 666e
-000559 3e61
-00055a 666c
-00055b 0061 .db "nfa>lfa",0
-00055c 052f .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-00055d 1c01 .dw DO_COLON
- PFA_NFA2LFA:
-00055e 0cf9 .dw XT_NAME2STRING
-00055f 1e2f .dw XT_1PLUS
-000560 1e04 .dw XT_2SLASH
-000561 1d9d .dw XT_PLUS
-000562 1c20 .dw XT_EXIT
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-000563 ff0b .dw $ff0b
-000564 6e65
-000565 6976
-000566 6f72
-000567 6d6e
-000568 6e65
-000569 0074 .db "environment",0
-00056a 0557 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-00056b 1c48 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-00056c 003a .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00056d ff09 .dw $ff09
-00056e 6f77
-00056f 6472
-000570 696c
-000571 7473
-000572 0073 .db "wordlists",0
-000573 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-000574 1c01 .dw DO_COLON
- PFA_ENVWORDLISTS:
-000575 1c3d .dw XT_DOLITERAL
-000576 0008 .dw NUMWORDLISTS
-000577 1c20 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-000578 ff04 .dw $ff04
-000579 702f
-00057a 6461 .db "/pad"
-00057b 056d .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-00057c 1c01 .dw DO_COLON
- PFA_ENVSLASHPAD:
-00057d 1e8d .dw XT_SP_FETCH
-00057e 060a .dw XT_PAD
-00057f 1d93 .dw XT_MINUS
-000580 1c20 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-000581 ff05 .dw $ff05
-000582 682f
-000583 6c6f
-000584 0064 .db "/hold",0
-000585 0578 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-000586 1c01 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-000587 060a .dw XT_PAD
-000588 0645 .dw XT_HERE
-000589 1d93 .dw XT_MINUS
-00058a 1c20 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-00058b ff0a .dw $ff0a
-00058c 6f66
-00058d 7472
-00058e 2d68
-00058f 616e
-000590 656d .db "forth-name"
-000591 0581 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-000592 1c01 .dw DO_COLON
- PFA_EN_FORTHNAME:
-000593 07f4 .dw XT_DOSLITERAL
-000594 0007 .dw 7
- .endif
-000595 6d61
-000596 6f66
-000597 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-000598 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-000599 1c20 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-00059a ff07 .dw $ff07
-00059b 6576
-00059c 7372
-00059d 6f69
-00059e 006e .db "version",0
-00059f 058b .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-0005a0 1c01 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-0005a1 1c3d .dw XT_DOLITERAL
-0005a2 0041 .dw 65
-0005a3 1c20 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-0005a4 ff03 .dw $ff03
-0005a5 7063
-0005a6 0075 .db "cpu",0
-0005a7 059a .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-0005a8 1c01 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-0005a9 1c3d .dw XT_DOLITERAL
-0005aa 002d .dw mcu_name
-0005ab 0853 .dw XT_ICOUNT
-0005ac 1c20 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-0005ad ff08 .dw $ff08
-0005ae 636d
-0005af 2d75
-0005b0 6e69
-0005b1 6f66 .db "mcu-info"
-0005b2 05a4 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-0005b3 1c01 .dw DO_COLON
- PFA_EN_MCUINFO:
-0005b4 1c3d .dw XT_DOLITERAL
-0005b5 0029 .dw mcu_info
-0005b6 1c20 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-0005b7 ff05 .dw $ff05
-0005b8 752f
-0005b9 6573
-0005ba 0072 .db "/user",0
-0005bb 05ad .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-0005bc 1c01 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-0005bd 1c3d .dw XT_DOLITERAL
-0005be 002c .dw SYSUSERSIZE + APPUSERSIZE
-0005bf 1c20 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-0005c0 ff05 .dw $ff05
-0005c1 5f66
-0005c2 7063
-0005c3 0075 .db "f_cpu",0
-0005c4 0563 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-0005c5 1c01 .dw DO_COLON
- PFA_F_CPU:
- .endif
-0005c6 1c3d .dw XT_DOLITERAL
-0005c7 1200 .dw (F_CPU % 65536)
-0005c8 1c3d .dw XT_DOLITERAL
-0005c9 007a .dw (F_CPU / 65536)
-0005ca 1c20 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-0005cb ff05 .dw $ff05
-0005cc 7473
-0005cd 7461
-0005ce 0065 .db "state",0
-0005cf 05c0 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-0005d0 1c48 .dw PFA_DOVARIABLE
- PFA_STATE:
-0005d1 008f .dw ram_state
-
- .dseg
-00008f ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-0005d2 ff04 .dw $ff04
-0005d3 6162
-0005d4 6573 .db "base"
-0005d5 05cb .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-0005d6 1c58 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-0005d7 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-0005d8 ff05 .dw $ff05
-0005d9 6563
-0005da 6c6c
-0005db 0073 .db "cells",0
-0005dc 05d2 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-0005dd 1e0c .dw PFA_2STAR
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-0005de ff05 .dw $ff05
-0005df 6563
-0005e0 6c6c
-0005e1 002b .db "cell+",0
-0005e2 05d8 .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-0005e3 05e4 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-0005e4 9602 adiw tosl, CELLSIZE
-0005e5 940c 1c05 jmp_ DO_NEXT
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-0005e7 ff04 .dw $ff04
-0005e8 6432
-0005e9 7075 .db "2dup"
-0005ea 05de .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-0005eb 1c01 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-0005ec 1ccf .dw XT_OVER
-0005ed 1ccf .dw XT_OVER
-0005ee 1c20 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-0005ef ff05 .dw $ff05
-0005f0 6432
-0005f1 6f72
-0005f2 0070 .db "2drop",0
-0005f3 05e7 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-0005f4 1c01 .dw DO_COLON
- PFA_2DROP:
- .endif
-0005f5 1cd9 .dw XT_DROP
-0005f6 1cd9 .dw XT_DROP
-0005f7 1c20 .dw XT_EXIT
-
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-0005f8 ff04 .dw $ff04
-0005f9 7574
-0005fa 6b63 .db "tuck"
-0005fb 05ef .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-0005fc 1c01 .dw DO_COLON
- PFA_TUCK:
- .endif
-0005fd 1cc4 .dw XT_SWAP
-0005fe 1ccf .dw XT_OVER
-0005ff 1c20 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-000600 ff03 .dw $ff03
-000601 693e
-000602 006e .db ">in",0
-000603 05f8 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-000604 1c58 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-000605 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-000606 ff03 .dw $ff03
-000607 6170
-000608 0064 .db "pad",0
-000609 0600 .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-00060a 1c01 .dw DO_COLON
- PFA_PAD:
- .endif
-00060b 0645 .dw XT_HERE
-00060c 1c3d .dw XT_DOLITERAL
-00060d 0028 .dw 40
-00060e 1d9d .dw XT_PLUS
-00060f 1c20 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-000610 ff04 .dw $ff04
-000611 6d65
-000612 7469 .db "emit"
-000613 0606 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-000614 0c9a .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-000615 000e .dw USER_EMIT
-000616 0c63 .dw XT_UDEFERFETCH
-000617 0c6f .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-000618 ff05 .dw $ff05
-000619 6d65
-00061a 7469
-00061b 003f .db "emit?",0
-00061c 0610 .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-00061d 0c9a .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-00061e 0010 .dw USER_EMITQ
-00061f 0c63 .dw XT_UDEFERFETCH
-000620 0c6f .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-000621 ff03 .dw $ff03
-000622 656b
-000623 0079 .db "key",0
-000624 0618 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-000625 0c9a .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-000626 0012 .dw USER_KEY
-000627 0c63 .dw XT_UDEFERFETCH
-000628 0c6f .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-000629 ff04 .dw $ff04
-00062a 656b
-00062b 3f79 .db "key?"
-00062c 0621 .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-00062d 0c9a .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-00062e 0014 .dw USER_KEYQ
-00062f 0c63 .dw XT_UDEFERFETCH
-000630 0c6f .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-000631 ff02 .dw $ff02
-000632 7064 .db "dp"
-000633 0629 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-000634 1c6f .dw PFA_DOVALUE1
- PFA_DP:
-000635 002c .dw CFG_DP
-000636 0c3b .dw XT_EDEFERFETCH
-000637 0c45 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-000638 ff05 .dw $ff05
-000639 6865
-00063a 7265
-00063b 0065 .db "ehere",0
-00063c 0631 .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-00063d 1c6f .dw PFA_DOVALUE1
- PFA_EHERE:
-00063e 0030 .dw EE_EHERE
-00063f 0c3b .dw XT_EDEFERFETCH
-000640 0c45 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-000641 ff04 .dw $ff04
-000642 6568
-000643 6572 .db "here"
-000644 0638 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-000645 1c6f .dw PFA_DOVALUE1
- PFA_HERE:
-000646 002e .dw EE_HERE
-000647 0c3b .dw XT_EDEFERFETCH
-000648 0c45 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-000649 ff05 .dw $ff05
-00064a 6c61
-00064b 6f6c
-00064c 0074 .db "allot",0
-00064d 0641 .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-00064e 1c01 .dw DO_COLON
- PFA_ALLOT:
-00064f 0645 .dw XT_HERE
-000650 1d9d .dw XT_PLUS
-000651 0c20 .dw XT_DOTO
-000652 0646 .dw PFA_HERE
-000653 1c20 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-000654 ff03 .dw $ff03
-000655 6962
-000656 006e .db "bin",0
-000657 0649 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-000658 1c01 .dw DO_COLON
- PFA_BIN:
- .endif
-000659 1fec .dw XT_TWO
-00065a 05d6 .dw XT_BASE
-00065b 1c81 .dw XT_STORE
-00065c 1c20 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-00065d ff07 .dw $ff07
-00065e 6564
-00065f 6963
-000660 616d
-000661 006c .db "decimal",0
-000662 0654 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-000663 1c01 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-000664 1c3d .dw XT_DOLITERAL
-000665 000a .dw 10
-000666 05d6 .dw XT_BASE
-000667 1c81 .dw XT_STORE
-000668 1c20 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-000669 ff03 .dw $ff03
-00066a 6568
-00066b 0078 .db "hex",0
-00066c 065d .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-00066d 1c01 .dw DO_COLON
- PFA_HEX:
- .endif
-00066e 1c3d .dw XT_DOLITERAL
-00066f 0010 .dw 16
-000670 05d6 .dw XT_BASE
-000671 1c81 .dw XT_STORE
-000672 1c20 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-000673 ff02 .dw $ff02
-000674 6c62 .db "bl"
-000675 0669 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-000676 1c48 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-000677 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-000678 ff07 .dw $ff07
-000679 7574
-00067a 6e72
-00067b 656b
-00067c 0079 .db "turnkey",0
-00067d 0673 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-00067e 0c9a .dw PFA_DODEFER1
- PFA_TURNKEY:
-00067f 0038 .dw CFG_TURNKEY
-000680 0c3b .dw XT_EDEFERFETCH
-000681 0c45 .dw XT_EDEFERSTORE
-
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-000682 ff04 .dw $ff04
-000683 6d2f
-000684 646f .db "/mod"
-000685 0678 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-000686 0687 .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-000687 019c movw temp2, tosl
-
-000688 9109 ld temp0, Y+
-000689 9119 ld temp1, Y+
-
-00068a 2f41 mov temp6,temp1 ;move dividend High to sign register
-00068b 2743 eor temp6,temp3 ;xor divisor High with sign register
-00068c ff17 sbrs temp1,7 ;if MSB in dividend set
-00068d c004 rjmp PFA_SLASHMOD_1
-00068e 9510 com temp1 ; change sign of dividend
-00068f 9500 com temp0
-000690 5f0f subi temp0,low(-1)
-000691 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-000692 ff37 sbrs temp3,7 ;if MSB in divisor set
-000693 c004 rjmp PFA_SLASHMOD_2
-000694 9530 com temp3 ; change sign of divisor
-000695 9520 com temp2
-000696 5f2f subi temp2,low(-1)
-000697 4f3f sbci temp3,high(-1)
-000698 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-000699 18ff sub temp5,temp5;clear remainder High byte and carry
-00069a e151 ldi temp7,17 ;init loop counter
-
-00069b 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-00069c 1f11 rol temp1
-00069d 955a dec temp7 ;decrement counter
-00069e f439 brne PFA_SLASHMOD_5 ;if done
-00069f ff47 sbrs temp6,7 ; if MSB in sign register set
-0006a0 c004 rjmp PFA_SLASHMOD_4
-0006a1 9510 com temp1 ; change sign of result
-0006a2 9500 com temp0
-0006a3 5f0f subi temp0,low(-1)
-0006a4 4f1f sbci temp1,high(-1)
-0006a5 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-0006a6 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-0006a7 1cff rol temp5
-0006a8 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-0006a9 0af3 sbc temp5,temp3 ;
-0006aa f420 brcc PFA_SLASHMOD_6 ;if result negative
-0006ab 0ee2 add temp4,temp2 ; restore remainder
-0006ac 1ef3 adc temp5,temp3
-0006ad 9488 clc ; clear carry to be shifted into result
-0006ae cfec rjmp PFA_SLASHMOD_3 ;else
-0006af 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-0006b0 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-0006b1 92fa st -Y,temp5
-0006b2 92ea st -Y,temp4
-
- ; put quotient on stack
-0006b3 01c8 movw tosl, temp0
-0006b4 940c 1c05 jmp_ DO_NEXT
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-0006b6 ff05 .dw $ff05
-0006b7 2f75
-0006b8 6f6d
-0006b9 0064 .db "u/mod",0
-0006ba 0682 .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-0006bb 1c01 .dw DO_COLON
- PFA_USLASHMOD:
-0006bc 1cff .dw XT_TO_R
-0006bd 1d54 .dw XT_ZERO
-0006be 1cf6 .dw XT_R_FROM
-0006bf 1dc2 .dw XT_UMSLASHMOD
-0006c0 1c20 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-0006c1 ff06 .dw $ff06
-0006c2 656e
-0006c3 6167
-0006c4 6574 .db "negate"
-0006c5 06b6 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-0006c6 1c01 .dw DO_COLON
- PFA_NEGATE:
-0006c7 1dfd .dw XT_INVERT
-0006c8 1e2f .dw XT_1PLUS
-0006c9 1c20 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-0006ca ff01 .dw $ff01
-0006cb 002f .db "/",0
-0006cc 06c1 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-0006cd 1c01 .dw DO_COLON
- PFA_SLASH:
- .endif
-0006ce 0686 .dw XT_SLASHMOD
-0006cf 1cf0 .dw XT_NIP
-0006d0 1c20 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-0006d1 ff03 .dw $ff03
-0006d2 6f6d
-0006d3 0064 .db "mod",0
-0006d4 06ca .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-0006d5 1c01 .dw DO_COLON
- PFA_MOD:
- .endif
-0006d6 0686 .dw XT_SLASHMOD
-0006d7 1cd9 .dw XT_DROP
-0006d8 1c20 .dw XT_EXIT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-0006d9 ff03 .dw $ff03
-0006da 6261
-0006db 0073 .db "abs",0
-0006dc 06d1 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-0006dd 1c01 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-0006de 1cb1
-0006df 1e3e
-0006e0 1c20 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-0006e1 ff03 .dw $ff03
-0006e2 696d
-0006e3 006e .db "min",0
-0006e4 06d9 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-0006e5 1c01 .dw DO_COLON
- PFA_MIN:
- .endif
-0006e6 05eb .dw XT_2DUP
-0006e7 1d78 .dw XT_GREATER
-0006e8 1c36 .dw XT_DOCONDBRANCH
-0006e9 06eb DEST(PFA_MIN1)
-0006ea 1cc4 .dw XT_SWAP
- PFA_MIN1:
-0006eb 1cd9 .dw XT_DROP
-0006ec 1c20 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-0006ed ff03 .dw $ff03
-0006ee 616d
-0006ef 0078 .db "max",0
-0006f0 06e1 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-0006f1 1c01 .dw DO_COLON
- PFA_MAX:
-
- .endif
-0006f2 05eb .dw XT_2DUP
-0006f3 1d6e .dw XT_LESS
-0006f4 1c36 .dw XT_DOCONDBRANCH
-0006f5 06f7 DEST(PFA_MAX1)
-0006f6 1cc4 .dw XT_SWAP
- PFA_MAX1:
-0006f7 1cd9 .dw XT_DROP
-0006f8 1c20 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-0006f9 ff06 .dw $ff06
-0006fa 6977
-0006fb 6874
-0006fc 6e69 .db "within"
-0006fd 06ed .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-0006fe 1c01 .dw DO_COLON
- PFA_WITHIN:
- .endif
-0006ff 1ccf .dw XT_OVER
-000700 1d93 .dw XT_MINUS
-000701 1cff .dw XT_TO_R
-000702 1d93 .dw XT_MINUS
-000703 1cf6 .dw XT_R_FROM
-000704 1d5c .dw XT_ULESS
-000705 1c20 .dw XT_EXIT
-
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-000706 ff07 .dw $ff07
-000707 6f74
-000708 7075
-000709 6570
-00070a 0072 .db "toupper",0
-00070b 06f9 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-00070c 1c01 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-00070d 1cb1 .dw XT_DUP
-00070e 1c3d .dw XT_DOLITERAL
-00070f 0061 .dw 'a'
-000710 1c3d .dw XT_DOLITERAL
-000711 007b .dw 'z'+1
-000712 06fe .dw XT_WITHIN
-000713 1c36 .dw XT_DOCONDBRANCH
-000714 0718 DEST(PFA_TOUPPER0)
-000715 1c3d .dw XT_DOLITERAL
-000716 00df .dw 223 ; inverse of 0x20: 0xdf
-000717 1e13 .dw XT_AND
- PFA_TOUPPER0:
-000718 1c20 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-000719 ff07 .dw $ff07
-00071a 6f74
-00071b 6f6c
-00071c 6577
-00071d 0072 .db "tolower",0
-00071e 0706 .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-00071f 1c01 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-000720 1cb1 .dw XT_DUP
-000721 1c3d .dw XT_DOLITERAL
-000722 0041 .dw 'A'
-000723 1c3d .dw XT_DOLITERAL
-000724 005b .dw 'Z'+1
-000725 06fe .dw XT_WITHIN
-000726 1c36 .dw XT_DOCONDBRANCH
-000727 072b DEST(PFA_TOLOWER0)
-000728 1c3d .dw XT_DOLITERAL
-000729 0020 .dw 32
-00072a 1e1c .dw XT_OR
- PFA_TOLOWER0:
-00072b 1c20 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-00072c ff03 .dw $ff03
-00072d 6c68
-00072e 0064 .db "hld",0
-00072f 0719 .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-000730 1c48 .dw PFA_DOVARIABLE
- PFA_HLD:
-000731 0091 .dw ram_hld
-
- .dseg
-000091 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-000732 ff04 .dw $ff04
-000733 6f68
-000734 646c .db "hold"
-000735 072c .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-000736 1c01 .dw DO_COLON
- PFA_HOLD:
- .endif
-000737 0730 .dw XT_HLD
-000738 1cb1 .dw XT_DUP
-000739 1c79 .dw XT_FETCH
-00073a 1e35 .dw XT_1MINUS
-00073b 1cb1 .dw XT_DUP
-00073c 1cff .dw XT_TO_R
-00073d 1cc4 .dw XT_SWAP
-00073e 1c81 .dw XT_STORE
-00073f 1cf6 .dw XT_R_FROM
-000740 1c8d .dw XT_CSTORE
-000741 1c20 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-000742 ff02 .dw $ff02
-000743 233c .db "<#"
-000744 0732 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-000745 1c01 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-000746 060a .dw XT_PAD
-000747 0730 .dw XT_HLD
-000748 1c81 .dw XT_STORE
-000749 1c20 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-00074a ff01 .dw $ff01
-00074b 0023 .db "#",0
-00074c 0742 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-00074d 1c01 .dw DO_COLON
- PFA_SHARP:
- .endif
-00074e 05d6 .dw XT_BASE
-00074f 1c79 .dw XT_FETCH
-000750 07ca .dw XT_UDSLASHMOD
-000751 1ce1 .dw XT_ROT
-000752 1c3d .dw XT_DOLITERAL
-000753 0009 .dw 9
-000754 1ccf .dw XT_OVER
-000755 1d6e .dw XT_LESS
-000756 1c36 .dw XT_DOCONDBRANCH
-000757 075b DEST(PFA_SHARP1)
-000758 1c3d .dw XT_DOLITERAL
-000759 0007 .dw 7
-00075a 1d9d .dw XT_PLUS
- PFA_SHARP1:
-00075b 1c3d .dw XT_DOLITERAL
-00075c 0030 .dw 48 ; ASCII 0
-00075d 1d9d .dw XT_PLUS
-00075e 0736 .dw XT_HOLD
-00075f 1c20 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-000760 ff02 .dw $ff02
-000761 7323 .db "#s"
-000762 074a .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-000763 1c01 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000764 074d .dw XT_SHARP
-000765 05eb .dw XT_2DUP
-000766 1e1c .dw XT_OR
-000767 1d1a .dw XT_ZEROEQUAL
-000768 1c36 .dw XT_DOCONDBRANCH
-000769 0764 DEST(NUMS1) ; PFA_SHARP_S
-00076a 1c20 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00076b ff02 .dw $ff02
-00076c 3e23 .db "#>"
-00076d 0760 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00076e 1c01 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-00076f 05f4 .dw XT_2DROP
-000770 0730 .dw XT_HLD
-000771 1c79 .dw XT_FETCH
-000772 060a .dw XT_PAD
-000773 1ccf .dw XT_OVER
-000774 1d93 .dw XT_MINUS
-000775 1c20 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000776 ff04 .dw $ff04
-000777 6973
-000778 6e67 .db "sign"
-000779 076b .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00077a 1c01 .dw DO_COLON
- PFA_SIGN:
- .endif
-00077b 1d21 .dw XT_ZEROLESS
-00077c 1c36 .dw XT_DOCONDBRANCH
-00077d 0781 DEST(PFA_SIGN1)
-00077e 1c3d .dw XT_DOLITERAL
-00077f 002d .dw 45 ; ascii -
-000780 0736 .dw XT_HOLD
- PFA_SIGN1:
-000781 1c20 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-000782 ff03 .dw $ff03
-000783 2e64
-000784 0072 .db "d.r",0
-000785 0776 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000786 1c01 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-000787 1cff .dw XT_TO_R
-000788 05fc .dw XT_TUCK
-000789 0d5b .dw XT_DABS
-00078a 0745 .dw XT_L_SHARP
-00078b 0763 .dw XT_SHARP_S
-00078c 1ce1 .dw XT_ROT
-00078d 077a .dw XT_SIGN
-00078e 076e .dw XT_SHARP_G
-00078f 1cf6 .dw XT_R_FROM
-000790 1ccf .dw XT_OVER
-000791 1d93 .dw XT_MINUS
-000792 0872 .dw XT_SPACES
-000793 0882 .dw XT_TYPE
-000794 1c20 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000795 ff02 .dw $ff02
-000796 722e .db ".r"
-000797 0782 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-000798 1c01 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-000799 1cff .dw XT_TO_R
-00079a 0dee .dw XT_S2D
-00079b 1cf6 .dw XT_R_FROM
-00079c 0786 .dw XT_DDOTR
-00079d 1c20 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00079e ff02 .dw $ff02
-00079f 2e64 .db "d."
-0007a0 0795 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-0007a1 1c01 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-0007a2 1d54 .dw XT_ZERO
-0007a3 0786 .dw XT_DDOTR
-0007a4 0869 .dw XT_SPACE
-0007a5 1c20 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-0007a6 ff01 .dw $ff01
-0007a7 002e .db ".",0
-0007a8 079e .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-0007a9 1c01 .dw DO_COLON
- PFA_DOT:
- .endif
-0007aa 0dee .dw XT_S2D
-0007ab 07a1 .dw XT_DDOT
-0007ac 1c20 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-0007ad ff03 .dw $ff03
-0007ae 6475
-0007af 002e .db "ud.",0
-0007b0 07a6 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-0007b1 1c01 .dw DO_COLON
- PFA_UDDOT:
- .endif
-0007b2 1d54 .dw XT_ZERO
-0007b3 07ba .dw XT_UDDOTR
-0007b4 0869 .dw XT_SPACE
-0007b5 1c20 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-0007b6 ff04 .dw $ff04
-0007b7 6475
-0007b8 722e .db "ud.r"
-0007b9 07ad .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-0007ba 1c01 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-0007bb 1cff .dw XT_TO_R
-0007bc 0745 .dw XT_L_SHARP
-0007bd 0763 .dw XT_SHARP_S
-0007be 076e .dw XT_SHARP_G
-0007bf 1cf6 .dw XT_R_FROM
-0007c0 1ccf .dw XT_OVER
-0007c1 1d93 .dw XT_MINUS
-0007c2 0872 .dw XT_SPACES
-0007c3 0882 .dw XT_TYPE
-0007c4 1c20 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-0007c5 ff06 .dw $ff06
-0007c6 6475
-0007c7 6d2f
-0007c8 646f .db "ud/mod"
-0007c9 07b6 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-0007ca 1c01 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-0007cb 1cff .dw XT_TO_R
-0007cc 1d54 .dw XT_ZERO
-0007cd 1d08 .dw XT_R_FETCH
-0007ce 1dc2 .dw XT_UMSLASHMOD
-0007cf 1cf6 .dw XT_R_FROM
-0007d0 1cc4 .dw XT_SWAP
-0007d1 1cff .dw XT_TO_R
-0007d2 1dc2 .dw XT_UMSLASHMOD
-0007d3 1cf6 .dw XT_R_FROM
-0007d4 1c20 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-0007d5 ff06 .dw $ff06
-0007d6 6964
-0007d7 6967
-0007d8 3f74 .db "digit?"
-0007d9 07c5 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-0007da 1c01 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-0007db 070c .dw XT_TOUPPER
-0007dc 1cb1
-0007dd 1c3d
-0007de 0039
-0007df 1d78
-0007e0 1c3d
-0007e1 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-0007e2 1e13
-0007e3 1d9d
-0007e4 1cb1
-0007e5 1c3d
-0007e6 0140
-0007e7 1d78 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-0007e8 1c3d
-0007e9 0107
-0007ea 1e13
-0007eb 1d93
-0007ec 1c3d
-0007ed 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-0007ee 1d93
-0007ef 1cb1
-0007f0 05d6
-0007f1 1c79
-0007f2 1d5c .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-0007f3 1c20 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-0007f4 1c01 .dw DO_COLON
- PFA_DOSLITERAL:
-0007f5 1d08 .dw XT_R_FETCH ; ( -- addr )
-0007f6 0853 .dw XT_ICOUNT
-0007f7 1cf6 .dw XT_R_FROM
-0007f8 1ccf .dw XT_OVER ; ( -- addr' n addr n)
-0007f9 1e2f .dw XT_1PLUS
-0007fa 1e04 .dw XT_2SLASH ; ( -- addr' n addr k )
-0007fb 1d9d .dw XT_PLUS ; ( -- addr' n addr'' )
-0007fc 1e2f .dw XT_1PLUS
-0007fd 1cff .dw XT_TO_R ; ( -- )
-0007fe 1c20 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-0007ff ff02 .dw $ff02
-000800 2c73 .db "s",$2c
-000801 07d5 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-000802 1c01 .dw DO_COLON
- PFA_SCOMMA:
-000803 1cb1 .dw XT_DUP
-000804 0806 .dw XT_DOSCOMMA
-000805 1c20 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-000806 1c01 .dw DO_COLON
- PFA_DOSCOMMA:
-000807 02ae .dw XT_COMMA
-000808 1cb1 .dw XT_DUP ; ( --addr len len)
-000809 1e04 .dw XT_2SLASH ; ( -- addr len len/2
-00080a 05fc .dw XT_TUCK ; ( -- addr len/2 len len/2
-00080b 1e0b .dw XT_2STAR ; ( -- addr len/2 len len'
-00080c 1d93 .dw XT_MINUS ; ( -- addr len/2 rem
-00080d 1cff .dw XT_TO_R
-00080e 1d54 .dw XT_ZERO
-00080f 036d .dw XT_QDOCHECK
-000810 1c36 .dw XT_DOCONDBRANCH
-000811 0819 .dw PFA_SCOMMA2
-000812 1e9b .dw XT_DODO
- PFA_SCOMMA1:
-000813 1cb1 .dw XT_DUP ; ( -- addr addr )
-000814 1c79 .dw XT_FETCH ; ( -- addr c1c2 )
-000815 02ae .dw XT_COMMA ; ( -- addr )
-000816 05e3 .dw XT_CELLPLUS ; ( -- addr+cell )
-000817 1ec9 .dw XT_DOLOOP
-000818 0813 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-000819 1cf6 .dw XT_R_FROM
-00081a 1d28 .dw XT_GREATERZERO
-00081b 1c36 .dw XT_DOCONDBRANCH
-00081c 0820 .dw PFA_SCOMMA3
-00081d 1cb1 .dw XT_DUP ; well, tricky
-00081e 1c98 .dw XT_CFETCH
-00081f 02ae .dw XT_COMMA
- PFA_SCOMMA3:
-000820 1cd9 .dw XT_DROP ; ( -- )
-000821 1c20 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-000822 ff05 .dw $ff05
-000823 7469
-000824 7079
-000825 0065 .db "itype",0
-000826 07ff .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-000827 1c01 .dw DO_COLON
- PFA_ITYPE:
-000828 1cb1 .dw XT_DUP ; ( --addr len len)
-000829 1e04 .dw XT_2SLASH ; ( -- addr len len/2
-00082a 05fc .dw XT_TUCK ; ( -- addr len/2 len len/2
-00082b 1e0b .dw XT_2STAR ; ( -- addr len/2 len len'
-00082c 1d93 .dw XT_MINUS ; ( -- addr len/2 rem
-00082d 1cff .dw XT_TO_R
-00082e 1d54 .dw XT_ZERO
-00082f 036d .dw XT_QDOCHECK
-000830 1c36 .dw XT_DOCONDBRANCH
-000831 083b .dw PFA_ITYPE2
-000832 1e9b .dw XT_DODO
- PFA_ITYPE1:
-000833 1cb1 .dw XT_DUP ; ( -- addr addr )
-000834 1fcb .dw XT_FETCHI ; ( -- addr c1c2 )
-000835 1cb1 .dw XT_DUP
-000836 0848 .dw XT_LOWEMIT
-000837 0844 .dw XT_HIEMIT
-000838 1e2f .dw XT_1PLUS ; ( -- addr+cell )
-000839 1ec9 .dw XT_DOLOOP
-00083a 0833 .dw PFA_ITYPE1
- PFA_ITYPE2:
-00083b 1cf6 .dw XT_R_FROM
-00083c 1d28 .dw XT_GREATERZERO
-00083d 1c36 .dw XT_DOCONDBRANCH
-00083e 0842 .dw PFA_ITYPE3
-00083f 1cb1 .dw XT_DUP ; make sure the drop below has always something to do
-000840 1fcb .dw XT_FETCHI
-000841 0848 .dw XT_LOWEMIT
- PFA_ITYPE3:
-000842 1cd9 .dw XT_DROP
-000843 1c20 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-000844 1c01 .dw DO_COLON
- PFA_HIEMIT:
-000845 1ef9 .dw XT_BYTESWAP
-000846 0848 .dw XT_LOWEMIT
-000847 1c20 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-000848 1c01 .dw DO_COLON
- PFA_LOWEMIT:
-000849 1c3d .dw XT_DOLITERAL
-00084a 00ff .dw $00ff
-00084b 1e13 .dw XT_AND
-00084c 0614 .dw XT_EMIT
-00084d 1c20 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00084e ff06 .dw $ff06
-00084f 6369
-000850 756f
-000851 746e .db "icount"
-000852 0822 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-000853 1c01 .dw DO_COLON
- PFA_ICOUNT:
-000854 1cb1 .dw XT_DUP
-000855 1e2f .dw XT_1PLUS
-000856 1cc4 .dw XT_SWAP
-000857 1fcb .dw XT_FETCHI
-000858 1c20 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-000859 ff02 .dw 0xff02
-00085a 7263 .db "cr"
-00085b 084e .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-00085c 1c01 .dw DO_COLON
- PFA_CR:
- .endif
-
-00085d 1c3d .dw XT_DOLITERAL
-00085e 000d .dw 13
-00085f 0614 .dw XT_EMIT
-000860 1c3d .dw XT_DOLITERAL
-000861 000a .dw 10
-000862 0614 .dw XT_EMIT
-000863 1c20 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-000864 ff05 .dw $ff05
-000865 7073
-000866 6361
-000867 0065 .db "space",0
-000868 0859 .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-000869 1c01 .dw DO_COLON
- PFA_SPACE:
- .endif
-00086a 0676 .dw XT_BL
-00086b 0614 .dw XT_EMIT
-00086c 1c20 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-00086d ff06 .dw $ff06
-00086e 7073
-00086f 6361
-000870 7365 .db "spaces"
-000871 0864 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-000872 1c01 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-000873 1d54
-000874 06f1 .DW XT_ZERO, XT_MAX
-000875 1cb1
-000876 1c36 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-000877 087c DEST(SPCS2)
-000878 0869
-000879 1e35
-00087a 1c2f .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-00087b 0875 DEST(SPCS1)
-00087c 1cd9
-00087d 1c20 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-00087e ff04 .dw $ff04
-00087f 7974
-000880 6570 .db "type"
-000881 086d .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-000882 1c01 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-000883 0de5 .dw XT_BOUNDS
-000884 036d .dw XT_QDOCHECK
-000885 1c36 .dw XT_DOCONDBRANCH
-000886 088d DEST(PFA_TYPE2)
-000887 1e9b .dw XT_DODO
- PFA_TYPE1:
-000888 1eac .dw XT_I
-000889 1c98 .dw XT_CFETCH
-00088a 0614 .dw XT_EMIT
-00088b 1ec9 .dw XT_DOLOOP
-00088c 0888 DEST(PFA_TYPE1)
- PFA_TYPE2:
-00088d 1c20 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00088e ff01 .dw $ff01
-00088f 0027 .db "'",0
-000890 087e .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-000891 1c01 .dw DO_COLON
- PFA_TICK:
- .endif
-000892 0a3b .dw XT_PARSENAME
-000893 0b60 .dw XT_FORTHRECOGNIZER
-000894 0b36 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-000895 1cb1 .dw XT_DUP
-000896 0bd1 .dw XT_DT_NULL
-000897 1fe0 .dw XT_EQUAL
-000898 1cc4 .dw XT_SWAP
-000899 1fcb .dw XT_FETCHI
-00089a 1c3d .dw XT_DOLITERAL
-00089b 0c06 .dw XT_NOOP
-00089c 1fe0 .dw XT_EQUAL
-00089d 1e1c .dw XT_OR
-00089e 1c36 .dw XT_DOCONDBRANCH
-00089f 08a3 DEST(PFA_TICK1)
-0008a0 1c3d .dw XT_DOLITERAL
-0008a1 fff3 .dw -13
-0008a2 08c8 .dw XT_THROW
- PFA_TICK1:
-0008a3 1cd9 .dw XT_DROP
-0008a4 1c20 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-0008a5 ff07 .dw $ff07
-0008a6 6168
-0008a7 646e
-0008a8 656c
-0008a9 0072 .db "handler",0
-0008aa 088e .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-0008ab 1c58 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-0008ac 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-0008ad ff05 .dw $ff05
-0008ae 6163
-0008af 6374
-0008b0 0068 .db "catch",0
-0008b1 08a5 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-0008b2 1c01 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-0008b3 1e8d .dw XT_SP_FETCH
-0008b4 1cff .dw XT_TO_R
- ; handler @ >r
-0008b5 08ab .dw XT_HANDLER
-0008b6 1c79 .dw XT_FETCH
-0008b7 1cff .dw XT_TO_R
- ; rp@ handler !
-0008b8 1e76 .dw XT_RP_FETCH
-0008b9 08ab .dw XT_HANDLER
-0008ba 1c81 .dw XT_STORE
-0008bb 1c2a .dw XT_EXECUTE
- ; r> handler !
-0008bc 1cf6 .dw XT_R_FROM
-0008bd 08ab .dw XT_HANDLER
-0008be 1c81 .dw XT_STORE
-0008bf 1cf6 .dw XT_R_FROM
-0008c0 1cd9 .dw XT_DROP
-0008c1 1d54 .dw XT_ZERO
-0008c2 1c20 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-0008c3 ff05 .dw $ff05
-0008c4 6874
-0008c5 6f72
-0008c6 0077 .db "throw",0
-0008c7 08ad .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-0008c8 1c01 .dw DO_COLON
- PFA_THROW:
- .endif
-0008c9 1cb1 .dw XT_DUP
-0008ca 1d1a .dw XT_ZEROEQUAL
-0008cb 1c36 .dw XT_DOCONDBRANCH
-0008cc 08cf DEST(PFA_THROW1)
-0008cd 1cd9 .dw XT_DROP
-0008ce 1c20 .dw XT_EXIT
- PFA_THROW1:
-0008cf 08ab .dw XT_HANDLER
-0008d0 1c79 .dw XT_FETCH
-0008d1 1e80 .dw XT_RP_STORE
-0008d2 1cf6 .dw XT_R_FROM
-0008d3 08ab .dw XT_HANDLER
-0008d4 1c81 .dw XT_STORE
-0008d5 1cf6 .dw XT_R_FROM
-0008d6 1cc4 .dw XT_SWAP
-0008d7 1cff .dw XT_TO_R
-0008d8 1e96 .dw XT_SP_STORE
-0008d9 1cd9 .dw XT_DROP
-0008da 1cf6 .dw XT_R_FROM
-0008db 1c20 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-0008dc ff05 .dw $ff05
-0008dd 7363
-0008de 696b
-0008df 0070 .db "cskip",0
-0008e0 08c3 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-0008e1 1c01 .dw DO_COLON
- PFA_CSKIP:
- .endif
-0008e2 1cff .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-0008e3 1cb1 .dw XT_DUP ; ( -- addr' n' n' )
-0008e4 1c36 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-0008e5 08f0 DEST(PFA_CSKIP2)
-0008e6 1ccf .dw XT_OVER ; ( -- addr' n' addr' )
-0008e7 1c98 .dw XT_CFETCH ; ( -- addr' n' c' )
-0008e8 1d08 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-0008e9 1fe0 .dw XT_EQUAL ; ( -- addr' n' f )
-0008ea 1c36 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-0008eb 08f0 DEST(PFA_CSKIP2)
-0008ec 1fe7 .dw XT_ONE
-0008ed 0a2c .dw XT_SLASHSTRING
-0008ee 1c2f .dw XT_DOBRANCH
-0008ef 08e3 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-0008f0 1cf6 .dw XT_R_FROM
-0008f1 1cd9 .dw XT_DROP ; ( -- addr2 n2)
-0008f2 1c20 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-0008f3 ff05 .dw $ff05
-0008f4 7363
-0008f5 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-0008f6 006e .db "cscan"
-0008f7 08dc .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-0008f8 1c01 .dw DO_COLON
- PFA_CSCAN:
- .endif
-0008f9 1cff .dw XT_TO_R
-0008fa 1ccf .dw XT_OVER
- PFA_CSCAN1:
-0008fb 1cb1 .dw XT_DUP
-0008fc 1c98 .dw XT_CFETCH
-0008fd 1d08 .dw XT_R_FETCH
-0008fe 1fe0 .dw XT_EQUAL
-0008ff 1d1a .dw XT_ZEROEQUAL
-000900 1c36 .dw XT_DOCONDBRANCH
-000901 090d DEST(PFA_CSCAN2)
-000902 1cc4 .dw XT_SWAP
-000903 1e35 .dw XT_1MINUS
-000904 1cc4 .dw XT_SWAP
-000905 1ccf .dw XT_OVER
-000906 1d21 .dw XT_ZEROLESS ; not negative
-000907 1d1a .dw XT_ZEROEQUAL
-000908 1c36 .dw XT_DOCONDBRANCH
-000909 090d DEST(PFA_CSCAN2)
-00090a 1e2f .dw XT_1PLUS
-00090b 1c2f .dw XT_DOBRANCH
-00090c 08fb DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-00090d 1cf0 .dw XT_NIP
-00090e 1ccf .dw XT_OVER
-00090f 1d93 .dw XT_MINUS
-000910 1cf6 .dw XT_R_FROM
-000911 1cd9 .dw XT_DROP
-000912 1c20 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-000913 ff06 .dw $ff06
-000914 6361
-000915 6563
-000916 7470 .db "accept"
-000917 08f3 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-000918 1c01 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-000919 1ccf
-00091a 1d9d
-00091b 1e35
-00091c 1ccf .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-00091d 0625
-00091e 1cb1
-00091f 0959
-000920 1d1a
-000921 1c36 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-000922 094b DEST(ACC5)
-000923 1cb1
-000924 1c3d
-000925 0008
-000926 1fe0
-000927 1c36 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-000928 093b DEST(ACC3)
-000929 1cd9
-00092a 1ce1
-00092b 05eb
-00092c 1d78
-00092d 1cff
-00092e 1ce1
-00092f 1ce1
-000930 1cf6
-000931 1c36 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-000932 0939 DEST(ACC6)
-000933 0951
-000934 1e35
-000935 1cff
-000936 1ccf
-000937 1cf6
-000938 014f .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-000939 1c2f ACC6: .DW XT_DOBRANCH
-00093a 0949 DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-00093b 1cb1 .dw XT_DUP ; ( -- addr k k )
-00093c 0676 .dw XT_BL
-00093d 1d6e .dw XT_LESS
-00093e 1c36 .dw XT_DOCONDBRANCH
-00093f 0942 DEST(PFA_ACCEPT6)
-000940 1cd9 .dw XT_DROP
-000941 0676 .dw XT_BL
- PFA_ACCEPT6:
-000942 1cb1
-000943 0614
-000944 1ccf
-000945 1c8d
-000946 1e2f
-000947 1ccf
-000948 015b .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-000949 1c2f ACC4: .DW XT_DOBRANCH
-00094a 091d DEST(ACC1)
-00094b 1cd9
-00094c 1cf0
-00094d 1cc4
-00094e 1d93
-00094f 085c
-000950 1c20 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-000951 1c01 .dw DO_COLON
- .endif
-000952 1c3d .dw XT_DOLITERAL
-000953 0008 .dw 8
-000954 1cb1 .dw XT_DUP
-000955 0614 .dw XT_EMIT
-000956 0869 .dw XT_SPACE
-000957 0614 .dw XT_EMIT
-000958 1c20 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-000959 1c01 .dw DO_COLON
- .endif
-00095a 1cb1 .dw XT_DUP
-00095b 1c3d .dw XT_DOLITERAL
-00095c 000d .dw 13
-00095d 1fe0 .dw XT_EQUAL
-00095e 1cc4 .dw XT_SWAP
-00095f 1c3d .dw XT_DOLITERAL
-000960 000a .dw 10
-000961 1fe0 .dw XT_EQUAL
-000962 1e1c .dw XT_OR
-000963 1c20 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-000964 ff06 .dw $ff06
-000965 6572
-000966 6966
-000967 6c6c .db "refill"
-000968 0913 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-000969 0c9a .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-00096a 001a .dw USER_REFILL
-00096b 0c63 .dw XT_UDEFERFETCH
-00096c 0c6f .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-00096d ff04 .dw $ff04
-00096e 6863
-00096f 7261 .db "char"
-000970 0964 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-000971 1c01 .dw DO_COLON
- PFA_CHAR:
- .endif
-000972 0a3b .dw XT_PARSENAME
-000973 1cd9 .dw XT_DROP
-000974 1c98 .dw XT_CFETCH
-000975 1c20 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-000976 ff06 .dw $ff06
-000977 756e
-000978 626d
-000979 7265 .db "number"
-00097a 096d .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-00097b 1c01 .dw DO_COLON
- PFA_NUMBER:
- .endif
-00097c 05d6 .dw XT_BASE
-00097d 1c79 .dw XT_FETCH
-00097e 1cff .dw XT_TO_R
-00097f 09bf .dw XT_QSIGN
-000980 1cff .dw XT_TO_R
-000981 09d2 .dw XT_SET_BASE
-000982 09bf .dw XT_QSIGN
-000983 1cf6 .dw XT_R_FROM
-000984 1e1c .dw XT_OR
-000985 1cff .dw XT_TO_R
- ; check whether something is left
-000986 1cb1 .dw XT_DUP
-000987 1d1a .dw XT_ZEROEQUAL
-000988 1c36 .dw XT_DOCONDBRANCH
-000989 0992 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-00098a 05f4 .dw XT_2DROP
-00098b 1cf6 .dw XT_R_FROM
-00098c 1cd9 .dw XT_DROP
-00098d 1cf6 .dw XT_R_FROM
-00098e 05d6 .dw XT_BASE
-00098f 1c81 .dw XT_STORE
-000990 1d54 .dw XT_ZERO
-000991 1c20 .dw XT_EXIT
- PFA_NUMBER0:
-000992 1f1e .dw XT_2TO_R
-000993 1d54 .dw XT_ZERO ; starting value
-000994 1d54 .dw XT_ZERO
-000995 1f2d .dw XT_2R_FROM
-000996 09f0 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-000997 1cb9 .dw XT_QDUP
-000998 1c36 .dw XT_DOCONDBRANCH
-000999 09b4 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00099a 1fe7 .dw XT_ONE
-00099b 1fe0 .dw XT_EQUAL
-00099c 1c36 .dw XT_DOCONDBRANCH
-00099d 09ab DEST(PFA_NUMBER2)
- ; excatly one character is left
-00099e 1c98 .dw XT_CFETCH
-00099f 1c3d .dw XT_DOLITERAL
-0009a0 002e .dw 46 ; .
-0009a1 1fe0 .dw XT_EQUAL
-0009a2 1c36 .dw XT_DOCONDBRANCH
-0009a3 09ac DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-0009a4 1cf6 .dw XT_R_FROM
-0009a5 1c36 .dw XT_DOCONDBRANCH
-0009a6 09a8 DEST(PFA_NUMBER3)
-0009a7 0d68 .dw XT_DNEGATE
- PFA_NUMBER3:
-0009a8 1fec .dw XT_TWO
-0009a9 1c2f .dw XT_DOBRANCH
-0009aa 09ba DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-0009ab 1cd9 .dw XT_DROP
- PFA_NUMBER6:
-0009ac 05f4 .dw XT_2DROP
-0009ad 1cf6 .dw XT_R_FROM
-0009ae 1cd9 .dw XT_DROP
-0009af 1cf6 .dw XT_R_FROM
-0009b0 05d6 .dw XT_BASE
-0009b1 1c81 .dw XT_STORE
-0009b2 1d54 .dw XT_ZERO
-0009b3 1c20 .dw XT_EXIT
- PFA_NUMBER1:
-0009b4 05f4 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-0009b5 1cf6 .dw XT_R_FROM
-0009b6 1c36 .dw XT_DOCONDBRANCH
-0009b7 09b9 DEST(PFA_NUMBER4)
-0009b8 06c6 .dw XT_NEGATE
- PFA_NUMBER4:
-0009b9 1fe7 .dw XT_ONE
- PFA_NUMBER5:
-0009ba 1cf6 .dw XT_R_FROM
-0009bb 05d6 .dw XT_BASE
-0009bc 1c81 .dw XT_STORE
-0009bd 1d4b .dw XT_TRUE
-0009be 1c20 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-0009bf 1c01 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-0009c0 1ccf .dw XT_OVER ; ( -- addr len addr )
-0009c1 1c98 .dw XT_CFETCH
-0009c2 1c3d .dw XT_DOLITERAL
-0009c3 002d .dw '-'
-0009c4 1fe0 .dw XT_EQUAL ; ( -- addr len flag )
-0009c5 1cb1 .dw XT_DUP
-0009c6 1cff .dw XT_TO_R
-0009c7 1c36 .dw XT_DOCONDBRANCH
-0009c8 09cb DEST(PFA_NUMBERSIGN_DONE)
-0009c9 1fe7 .dw XT_ONE ; skip sign character
-0009ca 0a2c .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-0009cb 1cf6 .dw XT_R_FROM
-0009cc 1c20 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-0009cd 1c52 .dw PFA_DOCONSTANT
- .endif
-0009ce 000a
-0009cf 0010
-0009d0 0002
-0009d1 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-0009d2 1c01 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-0009d3 1ccf .dw XT_OVER
-0009d4 1c98 .dw XT_CFETCH
-0009d5 1c3d .dw XT_DOLITERAL
-0009d6 0023 .dw 35
-0009d7 1d93 .dw XT_MINUS
-0009d8 1cb1 .dw XT_DUP
-0009d9 1d54 .dw XT_ZERO
-0009da 1c3d .dw XT_DOLITERAL
-0009db 0004 .dw 4
-0009dc 06fe .dw XT_WITHIN
-0009dd 1c36 .dw XT_DOCONDBRANCH
-0009de 09e8 DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-0009df 09cd .dw XT_BASES
-0009e0 1d9d .dw XT_PLUS
-0009e1 1fcb .dw XT_FETCHI
-0009e2 05d6 .dw XT_BASE
-0009e3 1c81 .dw XT_STORE
-0009e4 1fe7 .dw XT_ONE
-0009e5 0a2c .dw XT_SLASHSTRING
-0009e6 1c2f .dw XT_DOBRANCH
-0009e7 09e9 DEST(SET_BASE2)
- SET_BASE1:
-0009e8 1cd9 .dw XT_DROP
- SET_BASE2:
-0009e9 1c20 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-0009ea ff07 .dw $ff07
-0009eb 6e3e
-0009ec 6d75
-0009ed 6562
-0009ee 0072 .db ">number",0
-0009ef 0976 .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-0009f0 1c01 .dw DO_COLON
-
- .endif
-
-0009f1 1cb1
-0009f2 1c36 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-0009f3 0a08 DEST(TONUM3)
-0009f4 1ccf
-0009f5 1c98
-0009f6 07da .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-0009f7 1d1a
-0009f8 1c36 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-0009f9 09fc DEST(TONUM2)
-0009fa 1cd9
-0009fb 1c20 .DW XT_DROP,XT_EXIT
-0009fc 1cff
-0009fd 0d8c
-0009fe 05d6
-0009ff 1c79
-000a00 0140 TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000a01 1cf6
-000a02 0138
-000a03 0d8c .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-000a04 1fe7
-000a05 0a2c
-000a06 1c2f .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-000a07 09f1 DEST(TONUM1)
-000a08 1c20 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-000a09 ff05 .dw $ff05
-000a0a 6170
-000a0b 7372
-000a0c 0065 .db "parse",0
-000a0d 09ea .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-000a0e 1c01 .dw DO_COLON
- PFA_PARSE:
- .endif
-000a0f 1cff .dw XT_TO_R ; ( -- )
-000a10 0a22 .dw XT_SOURCE ; ( -- addr len)
-000a11 0604 .dw XT_TO_IN ; ( -- addr len >in)
-000a12 1c79 .dw XT_FETCH
-000a13 0a2c .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-000a14 1cf6 .dw XT_R_FROM ; ( -- addr' len' c)
-000a15 08f8 .dw XT_CSCAN ; ( -- addr' len'')
-000a16 1cb1 .dw XT_DUP ; ( -- addr' len'' len'')
-000a17 1e2f .dw XT_1PLUS
-000a18 0604 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-000a19 1e65 .dw XT_PLUSSTORE ; ( -- addr' len')
-000a1a 1fe7 .dw XT_ONE
-000a1b 0a2c .dw XT_SLASHSTRING
-000a1c 1c20 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-000a1d ff06 .dw $FF06
-000a1e 6f73
-000a1f 7275
-000a20 6563 .db "source"
-000a21 0a09 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-000a22 0c9a .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-000a23 0016 .dw USER_SOURCE
-000a24 0c63 .dw XT_UDEFERFETCH
-000a25 0c6f .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-000a26 ff07 .dw $ff07
-000a27 732f
-000a28 7274
-000a29 6e69
-000a2a 0067 .db "/string",0
-000a2b 0a1d .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-000a2c 1c01 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-000a2d 1ce1 .dw XT_ROT
-000a2e 1ccf .dw XT_OVER
-000a2f 1d9d .dw XT_PLUS
-000a30 1ce1 .dw XT_ROT
-000a31 1ce1 .dw XT_ROT
-000a32 1d93 .dw XT_MINUS
-000a33 1c20 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-000a34 ff0a .dw $FF0A
-000a35 6170
-000a36 7372
-000a37 2d65
-000a38 616e
-000a39 656d .db "parse-name"
-000a3a 0a26 .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-000a3b 1c01 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-000a3c 0676 .dw XT_BL
-000a3d 0a3f .dw XT_SKIPSCANCHAR
-000a3e 1c20 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-000a3f 1c01 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-000a40 1cff .dw XT_TO_R
-000a41 0a22 .dw XT_SOURCE
-000a42 0604 .dw XT_TO_IN
-000a43 1c79 .dw XT_FETCH
-000a44 0a2c .dw XT_SLASHSTRING
-
-000a45 1d08 .dw XT_R_FETCH
-000a46 08e1 .dw XT_CSKIP
-000a47 1cf6 .dw XT_R_FROM
-000a48 08f8 .dw XT_CSCAN
-
- ; adjust >IN
-000a49 05eb .dw XT_2DUP
-000a4a 1d9d .dw XT_PLUS
-000a4b 0a22 .dw XT_SOURCE
-000a4c 1cd9 .dw XT_DROP
-000a4d 1d93 .dw XT_MINUS
-000a4e 0604 .dw XT_TO_IN
-000a4f 1c81 .dw XT_STORE
-000a50 1c20 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-000a51 ff07 .dw $ff07
-000a52 6966
-000a53 646e
-000a54 782d
-000a55 0074 .db "find-xt",0
-000a56 0a34 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-000a57 1c01 .dw DO_COLON
- PFA_FINDXT:
- .endif
-000a58 1c3d .dw XT_DOLITERAL
-000a59 0a63 .dw XT_FINDXTA
-000a5a 1c3d .dw XT_DOLITERAL
-000a5b 0040 .dw CFG_ORDERLISTLEN
-000a5c 04ee .dw XT_MAPSTACK
-000a5d 1d1a .dw XT_ZEROEQUAL
-000a5e 1c36 .dw XT_DOCONDBRANCH
-000a5f 0a62 DEST(PFA_FINDXT1)
-000a60 05f4 .dw XT_2DROP
-000a61 1d54 .dw XT_ZERO
- PFA_FINDXT1:
-000a62 1c20 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-000a63 1c01 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-000a64 1cff .dw XT_TO_R
-000a65 05eb .dw XT_2DUP
-000a66 1cf6 .dw XT_R_FROM
-000a67 0cac .dw XT_SEARCH_WORDLIST
-000a68 1cb1 .dw XT_DUP
-000a69 1c36 .dw XT_DOCONDBRANCH
-000a6a 0a70 DEST(PFA_FINDXTA1)
-000a6b 1cff .dw XT_TO_R
-000a6c 1cf0 .dw XT_NIP
-000a6d 1cf0 .dw XT_NIP
-000a6e 1cf6 .dw XT_R_FROM
-000a6f 1d4b .dw XT_TRUE
- PFA_FINDXTA1:
-000a70 1c20 .dw XT_EXIT
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-000a71 ff04 .dw $ff04
-000a72 7571
-000a73 7469 .db "quit"
-000a74 0a51 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-000a75 1c01 .dw DO_COLON
- .endif
- PFA_QUIT:
-000a76 03a3
-000a77 03aa
-000a78 1c81 .dw XT_LP0,XT_LP,XT_STORE
-000a79 0b10 .dw XT_SP0
-000a7a 1e96 .dw XT_SP_STORE
-000a7b 0b1d .dw XT_RP0
-000a7c 1e80 .dw XT_RP_STORE
-000a7d 0438 .dw XT_LBRACKET
-
- PFA_QUIT2:
-000a7e 05d0 .dw XT_STATE
-000a7f 1c79 .dw XT_FETCH
-000a80 1d1a .dw XT_ZEROEQUAL
-000a81 1c36 .dw XT_DOCONDBRANCH
-000a82 0a84 DEST(PFA_QUIT4)
-000a83 0ab4 .dw XT_PROMPTREADY
- PFA_QUIT4:
-000a84 0969 .dw XT_REFILL
-000a85 1c36 .dw XT_DOCONDBRANCH
-000a86 0a96 DEST(PFA_QUIT3)
-000a87 1c3d .dw XT_DOLITERAL
-000a88 0b6b .dw XT_INTERPRET
-000a89 08b2 .dw XT_CATCH
-000a8a 1cb9 .dw XT_QDUP
-000a8b 1c36 .dw XT_DOCONDBRANCH
-000a8c 0a96 DEST(PFA_QUIT3)
-000a8d 1cb1 .dw XT_DUP
-000a8e 1c3d .dw XT_DOLITERAL
-000a8f fffe .dw -2
-000a90 1d6e .dw XT_LESS
-000a91 1c36 .dw XT_DOCONDBRANCH
-000a92 0a94 DEST(PFA_QUIT5)
-000a93 0acf .dw XT_PROMPTERROR
- PFA_QUIT5:
-000a94 1c2f .dw XT_DOBRANCH
-000a95 0a76 DEST(PFA_QUIT)
- PFA_QUIT3:
-000a96 0aa4 .dw XT_PROMPTOK
-000a97 1c2f .dw XT_DOBRANCH
-000a98 0a7e DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-000a99 1c01 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-000a9a 07f4 .dw XT_DOSLITERAL
-000a9b 0003 .dw 3
-000a9c 6f20
-000a9d 006b .db " ok",0
- .endif
-000a9e 0827 .dw XT_ITYPE
-000a9f 1c20 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-000aa0 ff03 .dw $FF03
-000aa1 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-000aa2 006b .db ".ok"
-000aa3 0a71 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-000aa4 0c9a .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-000aa5 001c .dw USER_P_OK
-000aa6 0c63 .dw XT_UDEFERFETCH
-000aa7 0c6f .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-000aa8 1c01 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-000aa9 07f4 .dw XT_DOSLITERAL
-000aaa 0002 .dw 2
-000aab 203e .db "> "
- .endif
-000aac 085c .dw XT_CR
-000aad 0827 .dw XT_ITYPE
-000aae 1c20 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-000aaf ff06 .dw $FF06
-000ab0 722e
-000ab1 6165
-000ab2 7964 .db ".ready"
-000ab3 0aa0 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-000ab4 0c9a .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-000ab5 0020 .dw USER_P_RDY
-000ab6 0c63 .dw XT_UDEFERFETCH
-000ab7 0c6f .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-000ab8 1c01 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-000ab9 07f4 .dw XT_DOSLITERAL
-000aba 0004 .dw 4
-000abb 3f20
-000abc 203f .db " ?? "
- .endif
-000abd 0827 .dw XT_ITYPE
-000abe 05d6 .dw XT_BASE
-000abf 1c79 .dw XT_FETCH
-000ac0 1cff .dw XT_TO_R
-000ac1 0663 .dw XT_DECIMAL
-000ac2 07a9 .dw XT_DOT
-000ac3 0604 .dw XT_TO_IN
-000ac4 1c79 .dw XT_FETCH
-000ac5 07a9 .dw XT_DOT
-000ac6 1cf6 .dw XT_R_FROM
-000ac7 05d6 .dw XT_BASE
-000ac8 1c81 .dw XT_STORE
-000ac9 1c20 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-000aca ff06 .dw $FF06
-000acb 652e
-000acc 7272
-000acd 726f .db ".error"
-000ace 0aaf .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-000acf 0c9a .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-000ad0 001e .dw USER_P_ERR
-000ad1 0c63 .dw XT_UDEFERFETCH
-000ad2 0c6f .dw XT_UDEFERSTORE
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-000ad3 ff05 .dw $ff05
-000ad4 6170
-000ad5 7375
-000ad6 0065 .db "pause",0
-000ad7 0aca .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-000ad8 0c9a .dw PFA_DODEFER1
- PFA_PAUSE:
-000ad9 0093 .dw ram_pause
-000ada 0c4f .dw XT_RDEFERFETCH
-000adb 0c59 .dw XT_RDEFERSTORE
-
- .dseg
-000093 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-000adc ff04 .dw $ff04
-000add 6f63
-000ade 646c .db "cold"
-000adf 0ad3 .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-000ae0 0ae1 .dw PFA_COLD
- PFA_COLD:
-000ae1 b6a4 in_ mcu_boot, MCUSR
-000ae2 2422 clr zerol
-000ae3 2433 clr zeroh
-000ae4 24bb clr isrflag
-000ae5 be24 out_ MCUSR, zerol
- ; clear RAM
-000ae6 e6e0 ldi zl, low(ramstart)
-000ae7 e0f0 ldi zh, high(ramstart)
- clearloop:
-000ae8 9221 st Z+, zerol
-000ae9 36e0 cpi zl, low(sram_size+ramstart)
-000aea f7e9 brne clearloop
-000aeb 30f4 cpi zh, high(sram_size+ramstart)
-000aec f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000095 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-000aed e9e5 ldi zl, low(ram_user1)
-000aee e0f0 ldi zh, high(ram_user1)
-000aef 012f movw upl, zl
- ; init return stack pointer
-000af0 e50f ldi temp0,low(rstackstart)
-000af1 bf0d out_ SPL,temp0
-000af2 8304 std Z+4, temp0
-000af3 e014 ldi temp1,high(rstackstart)
-000af4 bf1e out_ SPH,temp1
-000af5 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-000af6 e0cf ldi yl,low(stackstart)
-000af7 83c6 std Z+6, yl
-000af8 e0d4 ldi yh,high(stackstart)
-000af9 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-000afa e0a3 ldi XL, low(PFA_WARM)
-000afb e0bb ldi XH, high(PFA_WARM)
- ; its a far jump...
-000afc 940c 1c05 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-000afe ff04 .dw $ff04
-000aff 6177
-000b00 6d72 .db "warm"
-000b01 0adc .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-000b02 1c01 .dw DO_COLON
- PFA_WARM:
- .endif
-000b03 0dd7 .dw XT_INIT_RAM
-000b04 1c3d .dw XT_DOLITERAL
-000b05 0c06 .dw XT_NOOP
-000b06 1c3d .dw XT_DOLITERAL
-000b07 0ad8 .dw XT_PAUSE
-000b08 0c7a .dw XT_DEFERSTORE
-000b09 0438 .dw XT_LBRACKET
-000b0a 067e .dw XT_TURNKEY
-000b0b 0a75 .dw XT_QUIT ; never returns
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-000b0c ff03 .dw $ff03
-000b0d 7073
-000b0e 0030 .db "sp0",0
-000b0f 0afe .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-000b10 1c6f .dw PFA_DOVALUE1
- PFA_SP0:
-000b11 0006 .dw USER_SP0
-000b12 0c63 .dw XT_UDEFERFETCH
-000b13 0c6f .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-000b14 ff02 .dw $ff02
-000b15 7073 .db "sp"
-000b16 0b0c .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-000b17 1c58 .dw PFA_DOUSER
- PFA_SP:
-000b18 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-000b19 ff03 .dw $ff03
-000b1a 7072
-000b1b 0030 .db "rp0",0
-000b1c 0b14 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-000b1d 1c01 .dw DO_COLON
- PFA_RP0:
-000b1e 0b21 .dw XT_DORP0
-000b1f 1c79 .dw XT_FETCH
-000b20 1c20 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-000b21 1c58 .dw PFA_DOUSER
- PFA_DORP0:
-000b22 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-000b23 ff05 .dw $ff05
-000b24 6564
-000b25 7470
-000b26 0068 .db "depth",0
-000b27 0b19 .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-000b28 1c01 .dw DO_COLON
- PFA_DEPTH:
- .endif
-000b29 0b10 .dw XT_SP0
-000b2a 1e8d .dw XT_SP_FETCH
-000b2b 1d93 .dw XT_MINUS
-000b2c 1e04 .dw XT_2SLASH
-000b2d 1e35 .dw XT_1MINUS
-000b2e 1c20 .dw XT_EXIT
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-000b2f ff09 .dw $ff09
-000b30 6572
-000b31 6f63
-000b32 6e67
-000b33 7a69
-000b34 0065 .db "recognize",0
-000b35 0b23 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-000b36 1c01 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-000b37 1c3d .dw XT_DOLITERAL
-000b38 0b41 .dw XT_RECOGNIZE_A
-000b39 1cc4 .dw XT_SWAP
-000b3a 04ee .dw XT_MAPSTACK
-000b3b 1d1a .dw XT_ZEROEQUAL
-000b3c 1c36 .dw XT_DOCONDBRANCH
-000b3d 0b40 DEST(PFA_RECOGNIZE1)
-000b3e 05f4 .dw XT_2DROP
-000b3f 0bd1 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-000b40 1c20 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-000b41 1c01 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-000b42 1ce1 .dw XT_ROT ; -- len xt addr
-000b43 1ce1 .dw XT_ROT ; -- xt addr len
-000b44 05eb .dw XT_2DUP
-000b45 1f1e .dw XT_2TO_R
-000b46 1ce1 .dw XT_ROT ; -- addr len xt
-000b47 1c2a .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-000b48 1f2d .dw XT_2R_FROM
-000b49 1ce1 .dw XT_ROT
-000b4a 1cb1 .dw XT_DUP
-000b4b 0bd1 .dw XT_DT_NULL
-000b4c 1fe0 .dw XT_EQUAL
-000b4d 1c36 .dw XT_DOCONDBRANCH
-000b4e 0b52 DEST(PFA_RECOGNIZE_A1)
-000b4f 1cd9 .dw XT_DROP
-000b50 1d54 .dw XT_ZERO
-000b51 1c20 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-000b52 1cf0 .dw XT_NIP
-000b53 1cf0 .dw XT_NIP
-000b54 1d4b .dw XT_TRUE
-000b55 1c20 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-000b56 ff10 .dw $ff10
-000b57 6f66
-000b58 7472
-000b59 2d68
-000b5a 6572
-000b5b 6f63
-000b5c 6e67
-000b5d 7a69
-000b5e 7265 .db "forth-recognizer"
-000b5f 0b2f .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-000b60 1c6f .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-000b61 0034 .dw CFG_FORTHRECOGNIZER
-000b62 0c3b .dw XT_EDEFERFETCH
-000b63 0c45 .dw XT_EDEFERSTORE
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-000b64 ff09 .dw $ff09
-000b65 6e69
-000b66 6574
-000b67 7072
-000b68 6572
-000b69 0074 .db "interpret",0
-000b6a 0b56 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-000b6b 1c01 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-000b6c 0a3b .dw XT_PARSENAME ; ( -- addr len )
-000b6d 1cb1 .dw XT_DUP ; ( -- addr len flag)
-000b6e 1c36 .dw XT_DOCONDBRANCH
-000b6f 0b7c DEST(PFA_INTERPRET2)
-000b70 0b60 .dw XT_FORTHRECOGNIZER
-000b71 0b36 .dw XT_RECOGNIZE
-000b72 05d0 .dw XT_STATE
-000b73 1c79 .dw XT_FETCH
-000b74 1c36 .dw XT_DOCONDBRANCH
-000b75 0b77 DEST(PFA_INTERPRET1)
-000b76 0c32 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-000b77 1fcb .dw XT_FETCHI
-000b78 1c2a .dw XT_EXECUTE
-000b79 0bde .dw XT_QSTACK
-000b7a 1c2f .dw XT_DOBRANCH
-000b7b 0b6c DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000b7c 05f4 .dw XT_2DROP
-000b7d 1c20 .dw XT_EXIT
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-000b7e ff06 .dw $ff06
-000b7f 7464
-000b80 6e3a
-000b81 6d75 .db "dt:num"
-000b82 0b64 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-000b83 1c52 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-000b84 0c06 .dw XT_NOOP ; interpret
-000b85 02c4 .dw XT_LITERAL ; compile
-000b86 02c4 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-000b87 ff07 .dw $ff07
-000b88 7464
-000b89 643a
-000b8a 756e
-000b8b 006d .db "dt:dnum",0
-000b8c 0b7e .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000b8d 1c52 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-000b8e 0c06 .dw XT_NOOP ; interpret
-000b8f 1fd8 .dw XT_2LITERAL ; compile
-000b90 1fd8 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-000b91 ff07 .dw $ff07
-000b92 6572
-000b93 3a63
-000b94 756e
-000b95 006d .db "rec:num",0
-000b96 0b87 .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-000b97 1c01 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-000b98 097b .dw XT_NUMBER
-000b99 1c36 .dw XT_DOCONDBRANCH
-000b9a 0ba3 DEST(PFA_REC_NONUMBER)
-000b9b 1fe7 .dw XT_ONE
-000b9c 1fe0 .dw XT_EQUAL
-000b9d 1c36 .dw XT_DOCONDBRANCH
-000b9e 0ba1 DEST(PFA_REC_INTNUM2)
-000b9f 0b83 .dw XT_DT_NUM
-000ba0 1c20 .dw XT_EXIT
- PFA_REC_INTNUM2:
-000ba1 0b8d .dw XT_DT_DNUM
-000ba2 1c20 .dw XT_EXIT
- PFA_REC_NONUMBER:
-000ba3 0bd1 .dw XT_DT_NULL
-000ba4 1c20 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-000ba5 ff08 .dw $ff08
-000ba6 6572
-000ba7 3a63
-000ba8 6966
-000ba9 646e .db "rec:find"
-000baa 0b91 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000bab 1c01 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000bac 0a57 .DW XT_FINDXT
-000bad 1cb1 .dw XT_DUP
-000bae 1d1a .dw XT_ZEROEQUAL
-000baf 1c36 .dw XT_DOCONDBRANCH
-000bb0 0bb4 DEST(PFA_REC_WORD_FOUND)
-000bb1 1cd9 .dw XT_DROP
-000bb2 0bd1 .dw XT_DT_NULL
-000bb3 1c20 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-000bb4 0bbb .dw XT_DT_XT
-
-000bb5 1c20 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-000bb6 ff05 .dw $ff05
-000bb7 7464
-000bb8 783a
-000bb9 0074 .db "dt:xt",0
-000bba 0ba5 .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000bbb 1c52 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000bbc 0bbf .dw XT_R_WORD_INTERPRET
-000bbd 0bc3 .dw XT_R_WORD_COMPILE
-000bbe 1fd8 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-000bbf 1c01 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-000bc0 1cd9 .dw XT_DROP ; the flags are in the way
-000bc1 1c2a .dw XT_EXECUTE
-000bc2 1c20 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-000bc3 1c01 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-000bc4 1d21 .dw XT_ZEROLESS
-000bc5 1c36 .dw XT_DOCONDBRANCH
-000bc6 0bc9 DEST(PFA_R_WORD_COMPILE1)
-000bc7 02ae .dw XT_COMMA
-000bc8 1c20 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-000bc9 1c2a .dw XT_EXECUTE
-000bca 1c20 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000bcb ff07 .dw $ff07
-000bcc 7464
-000bcd 6e3a
-000bce 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-000bcf 006c .db "dt:null"
-000bd0 0bb6 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-000bd1 1c52 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-000bd2 0bd5 .dw XT_FAIL ; interpret
-000bd3 0bd5 .dw XT_FAIL ; compile
-000bd4 0bd5 .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-000bd5 1c01 .dw DO_COLON
- PFA_FAIL:
- .endif
-000bd6 1c3d .dw XT_DOLITERAL
-000bd7 fff3 .dw -13
-000bd8 08c8 .dw XT_THROW
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-000bd9 ff06 .dw $ff06
-000bda 733f
-000bdb 6174
-000bdc 6b63 .db "?stack"
-000bdd 0bcb .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-000bde 1c01 .dw DO_COLON
- PFA_QSTACK:
- .endif
-000bdf 0b28 .dw XT_DEPTH
-000be0 1d21 .dw XT_ZEROLESS
-000be1 1c36 .dw XT_DOCONDBRANCH
-000be2 0be6 DEST(PFA_QSTACK1)
-000be3 1c3d .dw XT_DOLITERAL
-000be4 fffc .dw -4
-000be5 08c8 .dw XT_THROW
- PFA_QSTACK1:
-000be6 1c20 .dw XT_EXIT
- .include "words/ver.asm"
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-000be7 ff03 .dw $ff03
-000be8 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-000be9 0072 .db "ver"
-000bea 0bd9 .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-000beb 1c01 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-000bec 0592 .dw XT_ENV_FORTHNAME
-000bed 0827 .dw XT_ITYPE
-000bee 0869 .dw XT_SPACE
-000bef 05d6 .dw XT_BASE
-000bf0 1c79 .dw XT_FETCH
-
-000bf1 05a0 .dw XT_ENV_FORTHVERSION
-000bf2 0663 .dw XT_DECIMAL
-000bf3 0dee .dw XT_S2D
-000bf4 0745 .dw XT_L_SHARP
-000bf5 074d .dw XT_SHARP
-000bf6 1c3d .dw XT_DOLITERAL
-000bf7 002e .dw '.'
-000bf8 0736 .dw XT_HOLD
-000bf9 0763 .dw XT_SHARP_S
-000bfa 076e .dw XT_SHARP_G
-000bfb 0882 .dw XT_TYPE
-000bfc 05d6 .dw XT_BASE
-000bfd 1c81 .dw XT_STORE
-000bfe 0869 .dw XT_SPACE
-000bff 05a8 .dw XT_ENV_CPU
-000c00 0827 .dw XT_ITYPE
-
-000c01 1c20 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-000c02 ff04 .dw $ff04
-000c03 6f6e
-000c04 706f .db "noop"
-000c05 0be7 .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-000c06 1c01 .dw DO_COLON
- PFA_NOOP:
- .endif
-000c07 1c20 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-000c08 ff06 .dw $ff06
-000c09 6e75
-000c0a 7375
-000c0b 6465 .db "unused"
-000c0c 0c02 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-000c0d 1c01 .dw DO_COLON
- PFA_UNUSED:
-000c0e 1e8d .dw XT_SP_FETCH
-000c0f 0645 .dw XT_HERE
-000c10 1d93 .dw XT_MINUS
-000c11 1c20 .dw XT_EXIT
-
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-000c12 0002 .dw $0002
-000c13 6f74 .db "to"
-000c14 0c08 .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-000c15 1c01 .dw DO_COLON
- PFA_TO:
- .endif
-000c16 0891 .dw XT_TICK
-000c17 0df7 .dw XT_TO_BODY
-000c18 05d0 .dw XT_STATE
-000c19 1c79 .dw XT_FETCH
-000c1a 1c36 .dw XT_DOCONDBRANCH
-000c1b 0c26 DEST(PFA_TO1)
-000c1c 02a3 .dw XT_COMPILE
-000c1d 0c20 .dw XT_DOTO
-000c1e 02ae .dw XT_COMMA
-000c1f 1c20 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-000c20 1c01 .dw DO_COLON
- PFA_DOTO:
- .endif
-000c21 1cf6 .dw XT_R_FROM
-000c22 1cb1 .dw XT_DUP
-000c23 0c32 .dw XT_ICELLPLUS
-000c24 1cff .dw XT_TO_R
-000c25 1fcb .dw XT_FETCHI
- PFA_TO1:
-000c26 1cb1 .dw XT_DUP
-000c27 0c32 .dw XT_ICELLPLUS
-000c28 0c32 .dw XT_ICELLPLUS
-000c29 1fcb .dw XT_FETCHI
-000c2a 1c2a .dw XT_EXECUTE
-000c2b 1c20 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-000c2c ff07 .dw $FF07
-000c2d 2d69
-000c2e 6563
-000c2f 6c6c
-000c30 002b .db "i-cell+",0
-000c31 0c12 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-000c32 1c01 .dw DO_COLON
- PFA_ICELLPLUS:
-000c33 1e2f .dw XT_1PLUS
-000c34 1c20 .dw XT_EXIT
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-000c35 ff07 .dw $ff07
-000c36 6445
-000c37 6665
-000c38 7265
-000c39 0040 .db "Edefer@",0
-000c3a 0c2c .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-000c3b 1c01 .dw DO_COLON
- PFA_EDEFERFETCH:
-000c3c 1fcb .dw XT_FETCHI
-000c3d 1f5f .dw XT_FETCHE
-000c3e 1c20 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-000c3f ff07 .dw $ff07
-000c40 6445
-000c41 6665
-000c42 7265
-000c43 0021 .db "Edefer!",0
-000c44 0c35 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-000c45 1c01 .dw DO_COLON
- PFA_EDEFERSTORE:
-000c46 1fcb .dw XT_FETCHI
-000c47 1f3b .dw XT_STOREE
-000c48 1c20 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-000c49 ff07 .dw $ff07
-000c4a 6452
-000c4b 6665
-000c4c 7265
-000c4d 0040 .db "Rdefer@",0
-000c4e 0c3f .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-000c4f 1c01 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-000c50 1fcb .dw XT_FETCHI
-000c51 1c79 .dw XT_FETCH
-000c52 1c20 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-000c53 ff07 .dw $ff07
-000c54 6452
-000c55 6665
-000c56 7265
-000c57 0021 .db "Rdefer!",0
-000c58 0c49 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-000c59 1c01 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-000c5a 1fcb .dw XT_FETCHI
-000c5b 1c81 .dw XT_STORE
-000c5c 1c20 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-000c5d ff07 .dw $ff07
-000c5e 6455
-000c5f 6665
-000c60 7265
-000c61 0040 .db "Udefer@",0
-000c62 0c53 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-000c63 1c01 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-000c64 1fcb .dw XT_FETCHI
-000c65 1f02 .dw XT_UP_FETCH
-000c66 1d9d .dw XT_PLUS
-000c67 1c79 .dw XT_FETCH
-000c68 1c20 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-000c69 ff07 .dw $ff07
-000c6a 6455
-000c6b 6665
-000c6c 7265
-000c6d 0021 .db "Udefer!",0
-000c6e 0c5d .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-000c6f 1c01 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-000c70 1fcb .dw XT_FETCHI
-000c71 1f02 .dw XT_UP_FETCH
-000c72 1d9d .dw XT_PLUS
-000c73 1c81 .dw XT_STORE
-000c74 1c20 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-000c75 ff06 .dw $ff06
-000c76 6564
-000c77 6566
-000c78 2172 .db "defer!"
-000c79 0c69 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-000c7a 1c01 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-000c7b 0df7 .dw XT_TO_BODY
-000c7c 1cb1 .dw XT_DUP
-000c7d 0c32 .dw XT_ICELLPLUS
-000c7e 0c32 .dw XT_ICELLPLUS
-000c7f 1fcb .dw XT_FETCHI
-000c80 1c2a .dw XT_EXECUTE
-000c81 1c20 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-000c82 ff06 .dw $ff06
-000c83 6564
-000c84 6566
-000c85 4072 .db "defer@"
-000c86 0c75 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-000c87 1c01 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-000c88 0df7 .dw XT_TO_BODY
-000c89 1cb1 .dw XT_DUP
-000c8a 0c32 .dw XT_ICELLPLUS
-000c8b 1fcb .dw XT_FETCHI
-000c8c 1c2a .dw XT_EXECUTE
-000c8d 1c20 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-000c8e ff07 .dw $ff07
-000c8f 6428
-000c90 6665
-000c91 7265
-000c92 0029 .db "(defer)", 0
-000c93 0c82 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-000c94 1c01 .dw DO_COLON
- PFA_DODEFER:
-000c95 0280 .dw XT_DOCREATE
-000c96 03e0 .dw XT_REVEAL
-000c97 02a3 .dw XT_COMPILE
-000c98 0c9a .dw PFA_DODEFER1
-000c99 1c20 .dw XT_EXIT
- PFA_DODEFER1:
-000c9a 940e 03f9 call_ DO_DODOES
-000c9c 1cb1 .dw XT_DUP
-000c9d 0c32 .dw XT_ICELLPLUS
-000c9e 1fcb .dw XT_FETCHI
-000c9f 1c2a .dw XT_EXECUTE
-000ca0 1c2a .dw XT_EXECUTE
-000ca1 1c20 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-000ca2 ff0f .dw $ff0f
-000ca3 6573
-000ca4 7261
-000ca5 6863
-000ca6 772d
-000ca7 726f
-000ca8 6c64
-000ca9 7369
-000caa 0074 .db "search-wordlist",0
-000cab 0c8e .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-000cac 1c01 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-000cad 1cff .dw XT_TO_R
-000cae 1d54 .dw XT_ZERO
-000caf 1c3d .dw XT_DOLITERAL
-000cb0 0cc1 .dw XT_ISWORD
-000cb1 1cf6 .dw XT_R_FROM
-000cb2 0cde .dw XT_TRAVERSEWORDLIST
-000cb3 1cb1 .dw XT_DUP
-000cb4 1d1a .dw XT_ZEROEQUAL
-000cb5 1c36 .dw XT_DOCONDBRANCH
-000cb6 0cbb DEST(PFA_SEARCH_WORDLIST1)
-000cb7 05f4 .dw XT_2DROP
-000cb8 1cd9 .dw XT_DROP
-000cb9 1d54 .dw XT_ZERO
-000cba 1c20 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-000cbb 1cb1 .dw XT_DUP
-000cbc 0d05 .dw XT_NFA2CFA
- ; .. and get the header flag
-000cbd 1cc4 .dw XT_SWAP
-000cbe 0175 .dw XT_NAME2FLAGS
-000cbf 0163 .dw XT_IMMEDIATEQ
-000cc0 1c20 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-000cc1 1c01 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-000cc2 1cff .dw XT_TO_R
-000cc3 1cd9 .dw XT_DROP
-000cc4 05eb .dw XT_2DUP
-000cc5 1d08 .dw XT_R_FETCH ; -- addr len addr len nt
-000cc6 0cf9 .dw XT_NAME2STRING
-000cc7 0d0f .dw XT_ICOMPARE ; (-- addr len f )
-000cc8 1c36 .dw XT_DOCONDBRANCH
-000cc9 0ccf DEST(PFA_ISWORD3)
- ; not now
-000cca 1cf6 .dw XT_R_FROM
-000ccb 1cd9 .dw XT_DROP
-000ccc 1d54 .dw XT_ZERO
-000ccd 1d4b .dw XT_TRUE ; maybe next word
-000cce 1c20 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-000ccf 05f4 .dw XT_2DROP
-000cd0 1cf6 .dw XT_R_FROM
-000cd1 1d54 .dw XT_ZERO ; finish traverse-wordlist
-000cd2 1c20 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-000cd3 ff11 .dw $ff11
-000cd4 7274
-000cd5 7661
-000cd6 7265
-000cd7 6573
-000cd8 772d
-000cd9 726f
-000cda 6c64
-000cdb 7369
-000cdc 0074 .db "traverse-wordlist",0
-000cdd 0ca2 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-000cde 1c01 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-000cdf 1f5f .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-000ce0 1cb1 .dw XT_DUP ; ( -- xt nt nt )
-000ce1 1c36 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-000ce2 0cef DEST(PFA_TRAVERSEWORDLIST2)
-000ce3 05eb .dw XT_2DUP
-000ce4 1f1e .dw XT_2TO_R
-000ce5 1cc4 .dw XT_SWAP
-000ce6 1c2a .dw XT_EXECUTE
-000ce7 1f2d .dw XT_2R_FROM
-000ce8 1ce1 .dw XT_ROT
-000ce9 1c36 .dw XT_DOCONDBRANCH
-000cea 0cef DEST(PFA_TRAVERSEWORDLIST2)
-000ceb 055d .dw XT_NFA2LFA
-000cec 1fcb .dw XT_FETCHI
-000ced 1c2f .dw XT_DOBRANCH ; ( -- addr )
-000cee 0ce0 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-000cef 05f4 .dw XT_2DROP
-000cf0 1c20 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-000cf1 ff0b .dw $ff0b
-000cf2 616e
-000cf3 656d
-000cf4 733e
-000cf5 7274
-000cf6 6e69
-000cf7 0067 .db "name>string",0
-000cf8 0cd3 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-000cf9 1c01 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-000cfa 0853 .dw XT_ICOUNT ; ( -- addr n )
-000cfb 1c3d .dw XT_DOLITERAL
-000cfc 00ff .dw 255
-000cfd 1e13 .dw XT_AND ; mask immediate bit
-000cfe 1c20 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-000cff ff07 .dw $ff07
-000d00 666e
-000d01 3e61
-000d02 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-000d03 0061 .db "nfa>cfa"
-000d04 0cf1 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-000d05 1c01 .dw DO_COLON
- PFA_NFA2CFA:
-000d06 055d .dw XT_NFA2LFA ; skip to link field
-000d07 1e2f .dw XT_1PLUS ; next is the execution token
-000d08 1c20 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-000d09 ff08 .dw $ff08
-000d0a 6369
-000d0b 6d6f
-000d0c 6170
-000d0d 6572 .db "icompare"
-000d0e 0cff .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-000d0f 1c01 .dw DO_COLON
- PFA_ICOMPARE:
-000d10 1cff .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-000d11 1ccf .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-000d12 1cf6 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-000d13 1d13 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-000d14 1c36 .dw XT_DOCONDBRANCH
-000d15 0d1a .dw PFA_ICOMPARE_SAMELEN
-000d16 05f4 .dw XT_2DROP
-000d17 1cd9 .dw XT_DROP
-000d18 1d4b .dw XT_TRUE
-000d19 1c20 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-000d1a 1cc4 .dw XT_SWAP ; ( -- r-addr f-addr len )
-000d1b 1d54 .dw XT_ZERO
-000d1c 036d .dw XT_QDOCHECK
-000d1d 1c36 .dw XT_DOCONDBRANCH
-000d1e 0d3d .dw PFA_ICOMPARE_DONE
-000d1f 1e9b .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-000d20 1ccf .dw XT_OVER
-000d21 1c79 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-000d22 1ccf .dw XT_OVER
-000d23 1fcb .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-000d24 1cb1 .dw XT_DUP
- ;.dw XT_BYTESWAP
-000d25 1c3d .dw XT_DOLITERAL
-000d26 0100 .dw $100
-000d27 1d5c .dw XT_ULESS
-000d28 1c36 .dw XT_DOCONDBRANCH
-000d29 0d2e .dw PFA_ICOMPARE_LASTCELL
-000d2a 1cc4 .dw XT_SWAP
-000d2b 1c3d .dw XT_DOLITERAL
-000d2c 00ff .dw $00FF
-000d2d 1e13 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-000d2e 1d13 .dw XT_NOTEQUAL
-000d2f 1c36 .dw XT_DOCONDBRANCH
-000d30 0d35 .dw PFA_ICOMPARE_NEXTLOOP
-000d31 05f4 .dw XT_2DROP
-000d32 1d4b .dw XT_TRUE
-000d33 1ed4 .dw XT_UNLOOP
-000d34 1c20 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-000d35 1e2f .dw XT_1PLUS
-000d36 1cc4 .dw XT_SWAP
-000d37 05e3 .dw XT_CELLPLUS
-000d38 1cc4 .dw XT_SWAP
-000d39 1c3d .dw XT_DOLITERAL
-000d3a 0002 .dw 2
-000d3b 1eba .dw XT_DOPLUSLOOP
-000d3c 0d20 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-000d3d 05f4 .dw XT_2DROP
-000d3e 1d54 .dw XT_ZERO
-000d3f 1c20 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
-
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-000d40 ff01 .dw $ff01
-000d41 002a .db "*",0
-000d42 0d09 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-000d43 1c01 .dw DO_COLON
- PFA_STAR:
- .endif
-
-000d44 1da6 .dw XT_MSTAR
-000d45 1cd9 .dw XT_DROP
-000d46 1c20 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-000d47 ff01 .dw $FF01
-000d48 006a .db "j",0
-000d49 0d40 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-000d4a 1c01 .dw DO_COLON
- PFA_J:
-000d4b 1e76 .dw XT_RP_FETCH
-000d4c 1c3d .dw XT_DOLITERAL
-000d4d 0007 .dw 7
-000d4e 1d9d .dw XT_PLUS
-000d4f 1c79 .dw XT_FETCH
-000d50 1e76 .dw XT_RP_FETCH
-000d51 1c3d .dw XT_DOLITERAL
-000d52 0009 .dw 9
-000d53 1d9d .dw XT_PLUS
-000d54 1c79 .dw XT_FETCH
-000d55 1d9d .dw XT_PLUS
-000d56 1c20 .dw XT_EXIT
-
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-000d57 ff04 .dw $ff04
-000d58 6164
-000d59 7362 .db "dabs"
-000d5a 0d47 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-000d5b 1c01 .dw DO_COLON
- PFA_DABS:
-000d5c 1cb1 .dw XT_DUP
-000d5d 1d21 .dw XT_ZEROLESS
-000d5e 1c36 .dw XT_DOCONDBRANCH
-000d5f 0d61 .dw PFA_DABS1
-000d60 0d68 .dw XT_DNEGATE
- PFA_DABS1:
-000d61 1c20 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-000d62 ff07 .dw $ff07
-000d63 6e64
-000d64 6765
-000d65 7461
-000d66 0065 .db "dnegate",0
-000d67 0d57 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-000d68 1c01 .dw DO_COLON
- PFA_DNEGATE:
-000d69 01c4 .dw XT_DINVERT
-000d6a 1fe7 .dw XT_ONE
-000d6b 1d54 .dw XT_ZERO
-000d6c 019c .dw XT_DPLUS
-000d6d 1c20 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-000d6e ff05 .dw $ff05
-000d6f 6d63
-000d70 766f
-000d71 0065 .db "cmove",0
-000d72 0d62 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-000d73 0d74 .dw PFA_CMOVE
- PFA_CMOVE:
-000d74 93bf push xh
-000d75 93af push xl
-000d76 91e9 ld zl, Y+
-000d77 91f9 ld zh, Y+ ; addr-to
-000d78 91a9 ld xl, Y+
-000d79 91b9 ld xh, Y+ ; addr-from
-000d7a 2f09 mov temp0, tosh
-000d7b 2b08 or temp0, tosl
-000d7c f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-000d7d 911d ld temp1, X+
-000d7e 9311 st Z+, temp1
-000d7f 9701 sbiw tosl, 1
-000d80 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-000d81 91af pop xl
-000d82 91bf pop xh
-000d83 9189
-000d84 9199 loadtos
-000d85 940c 1c05 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-000d87 ff05 .dw $ff05
-000d88 7332
-000d89 6177
-000d8a 0070 .db "2swap",0
-000d8b 0d6e .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-000d8c 1c01 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-000d8d 1ce1 .dw XT_ROT
-000d8e 1cff .dw XT_TO_R
-000d8f 1ce1 .dw XT_ROT
-000d90 1cf6 .dw XT_R_FROM
-000d91 1c20 .dw XT_EXIT
-
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-000d92 ff0a .dw $ff0a
-000d93 6572
-000d94 6966
-000d95 6c6c
-000d96 742d
-000d97 6269 .db "refill-tib"
-000d98 0d87 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-000d99 1c01 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-000d9a 0db5 .dw XT_TIB
-000d9b 1c3d .dw XT_DOLITERAL
-000d9c 005a .dw TIB_SIZE
-000d9d 0918 .dw XT_ACCEPT
-000d9e 0dbb .dw XT_NUMBERTIB
-000d9f 1c81 .dw XT_STORE
-000da0 1d54 .dw XT_ZERO
-000da1 0604 .dw XT_TO_IN
-000da2 1c81 .dw XT_STORE
-000da3 1d4b .dw XT_TRUE ; -1
-000da4 1c20 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-000da5 ff0a .dw $FF0A
-000da6 6f73
-000da7 7275
-000da8 6563
-000da9 742d
-000daa 6269 .db "source-tib"
-000dab 0d92 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-000dac 1c01 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-000dad 0db5 .dw XT_TIB
-000dae 0dbb .dw XT_NUMBERTIB
-000daf 1c79 .dw XT_FETCH
-000db0 1c20 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-000db1 ff03 .dw $ff03
-000db2 6974
-000db3 0062 .db "tib",0
-000db4 0da5 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-000db5 1c48 .dw PFA_DOVARIABLE
- PFA_TIB:
-000db6 00c1 .dw ram_tib
- .dseg
-0000c1 ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-000db7 ff04 .dw $ff04
-000db8 7423
-000db9 6269 .db "#tib"
-000dba 0db1 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-000dbb 1c48 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-000dbc 011b .dw ram_sharptib
- .dseg
-00011b ram_sharptib: .byte 2
- .cseg
- .endif
-
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-000dbd ff06 .dw $ff06
-000dbe 6565
-000dbf 723e
-000dc0 6d61 .db "ee>ram"
-000dc1 0db7 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-000dc2 1c01 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-000dc3 1d54 .dw XT_ZERO
-000dc4 1e9b .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-000dc5 1ccf .dw XT_OVER
-000dc6 1f5f .dw XT_FETCHE
-000dc7 1ccf .dw XT_OVER
-000dc8 1c81 .dw XT_STORE
-000dc9 05e3 .dw XT_CELLPLUS
-000dca 1cc4 .dw XT_SWAP
-000dcb 05e3 .dw XT_CELLPLUS
-000dcc 1cc4 .dw XT_SWAP
-000dcd 1ec9 .dw XT_DOLOOP
-000dce 0dc5 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-000dcf 05f4 .dw XT_2DROP
-000dd0 1c20 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-000dd1 ff08 .dw $ff08
-000dd2 6e69
-000dd3 7469
-000dd4 722d
-000dd5 6d61 .db "init-ram"
-000dd6 0dbd .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-000dd7 1c01 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-000dd8 1c3d .dw XT_DOLITERAL
-000dd9 0060 .dw EE_INITUSER
-000dda 1f02 .dw XT_UP_FETCH
-000ddb 1c3d .dw XT_DOLITERAL
-000ddc 0022 .dw SYSUSERSIZE
-000ddd 1e04 .dw XT_2SLASH
-000dde 0dc2 .dw XT_EE2RAM
-000ddf 1c20 .dw XT_EXIT
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-000de0 ff06 .dw $ff06
-000de1 6f62
-000de2 6e75
-000de3 7364 .db "bounds"
-000de4 0dd1 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-000de5 1c01 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-000de6 1ccf .dw XT_OVER
-000de7 1d9d .dw XT_PLUS
-000de8 1cc4 .dw XT_SWAP
-000de9 1c20 .dw XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-000dea ff03 .dw $ff03
-000deb 3e73
-000dec 0064 .db "s>d",0
-000ded 0de0 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-000dee 1c01 .dw DO_COLON
- PFA_S2D:
- .endif
-000def 1cb1 .dw XT_DUP
-000df0 1d21 .dw XT_ZEROLESS
-000df1 1c20 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-000df2 ff05 .dw $ff05
-000df3 623e
-000df4 646f
-000df5 0079 .db ">body",0
-000df6 0dea .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-000df7 1e30 .dw PFA_1PLUS
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
- .include "words/dot-s.asm"
-
- ; Tools
- ; stack dump
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTS:
-000df8 ff02 .dw $ff02
-000df9 732e .db ".s"
-000dfa 0df2 .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
- XT_DOTS:
-000dfb 1c01 .dw DO_COLON
- PFA_DOTS:
- .endif
-000dfc 0b28 .dw XT_DEPTH
-000dfd 01d2 .dw XT_UDOT
-000dfe 0869 .dw XT_SPACE
-000dff 0b28 .dw XT_DEPTH
-000e00 1d54 .dw XT_ZERO
-000e01 036d .dw XT_QDOCHECK
-000e02 1c36 .dw XT_DOCONDBRANCH
-000e03 0e0a DEST(PFA_DOTS2)
-000e04 1e9b .dw XT_DODO
- PFA_DOTS1:
-000e05 1eac .dw XT_I
-000e06 023d .dw XT_PICK
-000e07 01d2 .dw XT_UDOT
-000e08 1ec9 .dw XT_DOLOOP
-000e09 0e05 DEST(PFA_DOTS1)
- PFA_DOTS2:
-000e0a 1c20 .dw XT_EXIT
- .include "words/spirw.asm"
-
- ; MCU
- ; SPI exchange of 1 byte
- VE_SPIRW:
-000e0b ff06 .dw $ff06
-000e0c 2163
-000e0d 7340
-000e0e 6970 .db "c!@spi"
-000e0f 0df8 .dw VE_HEAD
- .set VE_HEAD = VE_SPIRW
- XT_SPIRW:
-000e10 0e11 .dw PFA_SPIRW
- PFA_SPIRW:
-000e11 d003 rcall do_spirw
-000e12 2799 clr tosh
-000e13 940c 1c05 jmp_ DO_NEXT
-
- do_spirw:
-000e15 b98f out_ SPDR, tosl
- do_spirw1:
-000e16 b10e in_ temp0, SPSR
-000e17 7f08 cbr temp0,7
-000e18 b90e out_ SPSR, temp0
-000e19 b10e in_ temp0, SPSR
-000e1a ff07 sbrs temp0, 7
-000e1b cffa rjmp do_spirw1 ; wait until complete
-000e1c b18f in_ tosl, SPDR
-000e1d 9508 ret
- .include "words/n-spi.asm"
-
- ; MCU
- ; read len bytes from SPI to addr
- VE_N_SPIR:
-000e1e ff05 .dw $ff05
-000e1f 406e
-000e20 7073
-000e21 0069 .db "n@spi",0
-000e22 0e0b .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIR
- XT_N_SPIR:
-000e23 0e24 .dw PFA_N_SPIR
- PFA_N_SPIR:
-000e24 018c movw temp0, tosl
-000e25 9189
-000e26 9199 loadtos
-000e27 01fc movw zl, tosl
-000e28 01c8 movw tosl, temp0
- PFA_N_SPIR_LOOP:
-000e29 b82f out_ SPDR, zerol
- PFA_N_SPIR_LOOP1:
-000e2a b12e in_ temp2, SPSR
-000e2b ff27 sbrs temp2, SPIF
-000e2c cffd rjmp PFA_N_SPIR_LOOP1
-000e2d b12f in_ temp2, SPDR
-000e2e 9321 st Z+, temp2
-000e2f 9701 sbiw tosl, 1
-000e30 f7c1 brne PFA_N_SPIR_LOOP
-000e31 9189
-000e32 9199 loadtos
-000e33 940c 1c05 jmp_ DO_NEXT
-
- ; ( addr len -- )
- ; MCU
- ; write len bytes to SPI from addr
- VE_N_SPIW:
-000e35 ff05 .dw $ff05
-000e36 216e
-000e37 7073
-000e38 0069 .db "n!spi",0
-000e39 0e1e .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIW
- XT_N_SPIW:
-000e3a 0e3b .dw PFA_N_SPIW
- PFA_N_SPIW:
-000e3b 018c movw temp0, tosl
-000e3c 9189
-000e3d 9199 loadtos
-000e3e 01fc movw zl, tosl
-000e3f 01c8 movw tosl, temp0
- PFA_N_SPIW_LOOP:
-000e40 9121 ld temp2, Z+
-000e41 b92f out_ SPDR, temp2
- PFA_N_SPIW_LOOP1:
-000e42 b12e in_ temp2, SPSR
-000e43 ff27 sbrs temp2, SPIF
-000e44 cffd rjmp PFA_N_SPIW_LOOP1
-000e45 b12f in_ temp2, SPDR ; ignore the data
-000e46 9701 sbiw tosl, 1
-000e47 f7c1 brne PFA_N_SPIW_LOOP
-000e48 9189
-000e49 9199 loadtos
-000e4a 940c 1c05 jmp_ DO_NEXT
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000e4c ff0b .dw $ff0b
-000e4d 7061
-000e4e 6c70
-000e4f 7574
-000e50 6e72
-000e51 656b
-000e52 0079 .db "applturnkey",0
-000e53 0e35 .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000e54 1c01 .dw DO_COLON
- PFA_APPLTURNKEY:
-000e55 00bc .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-000e56 0203 .dw XT_INTON
- .endif
-000e57 0beb .dw XT_DOT_VER
-000e58 0869 .dw XT_SPACE
-000e59 05c5 .dw XT_F_CPU
-000e5a 1c3d .dw XT_DOLITERAL
-000e5b 03e8 .dw 1000
-000e5c 1dc2 .dw XT_UMSLASHMOD
-000e5d 1cf0 .dw XT_NIP
-000e5e 0663 .dw XT_DECIMAL
-000e5f 07a9 .dw XT_DOT
-000e60 07f4 .dw XT_DOSLITERAL
-000e61 0004 .dw 4
-000e62 486b
-000e63 207a .db "kHz "
-000e64 0827 .dw XT_ITYPE
-000e65 1c20 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-000e66 ff0b .dw $ff0b
-000e67 6573
-000e68 2d74
-000e69 7563
-000e6a 7272
-000e6b 6e65
-000e6c 0074 .db "set-current",0
-000e6d 0e4c .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-000e6e 1c01 .dw DO_COLON
- PFA_SET_CURRENT:
-000e6f 1c3d .dw XT_DOLITERAL
-000e70 003c .dw CFG_CURRENT
-000e71 1f3b .dw XT_STOREE
-000e72 1c20 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-000e73 ff08 .dw $ff08
-000e74 6f77
-000e75 6472
-000e76 696c
-000e77 7473 .db "wordlist"
-000e78 0e66 .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000e79 1c01 .dw DO_COLON
- PFA_WORDLIST:
-000e7a 063d .dw XT_EHERE
-000e7b 1d54 .dw XT_ZERO
-000e7c 1ccf .dw XT_OVER
-000e7d 1f3b .dw XT_STOREE
-000e7e 1cb1 .dw XT_DUP
-000e7f 05e3 .dw XT_CELLPLUS
-000e80 0c20 .dw XT_DOTO
-000e81 063e .dw PFA_EHERE
-000e82 1c20 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-000e83 ff0e .dw $ff0e
-000e84 6f66
-000e85 7472
-000e86 2d68
-000e87 6f77
-000e88 6472
-000e89 696c
-000e8a 7473 .db "forth-wordlist"
-000e8b 0e73 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000e8c 1c48 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000e8d 003e .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000e8e ff09 .dw $ff09
-000e8f 6573
-000e90 2d74
-000e91 726f
-000e92 6564
-000e93 0072 .db "set-order",0
-000e94 0e83 .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000e95 1c01 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000e96 1c3d .dw XT_DOLITERAL
-000e97 0040 .dw CFG_ORDERLISTLEN
-000e98 04d0 .dw XT_SET_STACK
-000e99 1c20 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000e9a ff0f .dw $ff0f
-000e9b 6573
-000e9c 2d74
-000e9d 6572
-000e9e 6f63
-000e9f 6e67
-000ea0 7a69
-000ea1 7265
-000ea2 0073 .db "set-recognizers",0
-000ea3 0e8e .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000ea4 1c01 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000ea5 1c3d .dw XT_DOLITERAL
-000ea6 0052 .dw CFG_RECOGNIZERLISTLEN
-000ea7 04d0 .dw XT_SET_STACK
-000ea8 1c20 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000ea9 ff0f .dw $ff0f
-000eaa 6567
-000eab 2d74
-000eac 6572
-000ead 6f63
-000eae 6e67
-000eaf 7a69
-000eb0 7265
-000eb1 0073 .db "get-recognizers",0
-000eb2 0e9a .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000eb3 1c01 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000eb4 1c3d .dw XT_DOLITERAL
-000eb5 0052 .dw CFG_RECOGNIZERLISTLEN
-000eb6 04af .dw XT_GET_STACK
-000eb7 1c20 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000eb8 ff04 .dw $ff04
-000eb9 6f63
-000eba 6564 .db "code"
-000ebb 0ea9 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000ebc 1c01 .dw DO_COLON
- PFA_CODE:
-000ebd 0280 .dw XT_DOCREATE
-000ebe 03e0 .dw XT_REVEAL
-000ebf 0634 .dw XT_DP
-000ec0 0c32 .dw XT_ICELLPLUS
-000ec1 02ae .dw XT_COMMA
-000ec2 1c20 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000ec3 ff08 .dw $ff08
-000ec4 6e65
-000ec5 2d64
-000ec6 6f63
-000ec7 6564 .db "end-code"
-000ec8 0eb8 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000ec9 1c01 .dw DO_COLON
- PFA_ENDCODE:
-000eca 02a3 .dw XT_COMPILE
-000ecb 940c .dw $940c
-000ecc 02a3 .dw XT_COMPILE
-000ecd 1c05 .dw DO_NEXT
-000ece 1c20 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000ecf ff08 .dw $ff08
-000ed0 6d28
-000ed1 7261
-000ed2 656b
-000ed3 2972 .db "(marker)"
-000ed4 0ec3 .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-000ed5 1c6f .dw PFA_DOVALUE1
- PFA_MARKER:
-000ed6 005e .dw EE_MARKER
-000ed7 0c3b .dw XT_EDEFERFETCH
-000ed8 0c45 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000ed9 0008 .dw $0008
-000eda 6f70
-000edb 7473
-000edc 6f70
-000edd 656e .db "postpone"
-000ede 0ecf .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000edf 1c01 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000ee0 0a3b .dw XT_PARSENAME
-000ee1 0b60 .dw XT_FORTHRECOGNIZER
-000ee2 0b36 .dw XT_RECOGNIZE
-000ee3 1cb1 .dw XT_DUP
-000ee4 1cff .dw XT_TO_R
-000ee5 0c32 .dw XT_ICELLPLUS
-000ee6 0c32 .dw XT_ICELLPLUS
-000ee7 1fcb .dw XT_FETCHI
-000ee8 1c2a .dw XT_EXECUTE
-000ee9 1cf6 .dw XT_R_FROM
-000eea 0c32 .dw XT_ICELLPLUS
-000eeb 1fcb .dw XT_FETCHI
-000eec 02ae .dw XT_COMMA
-000eed 1c20 .dw XT_EXIT
- .endif
- .include "words/2r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_2R_FETCH:
-000eee ff03 .dw $ff03
-000eef 7232
-000ef0 0040 .db "2r@",0
-000ef1 0ed9 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FETCH
- XT_2R_FETCH:
-000ef2 0ef3 .dw PFA_2R_FETCH
- PFA_2R_FETCH:
-000ef3 939a
-000ef4 938a savetos
-000ef5 91ef pop zl
-000ef6 91ff pop zh
-000ef7 918f pop tosl
-000ef8 919f pop tosh
-000ef9 939f push tosh
-000efa 938f push tosl
-000efb 93ff push zh
-000efc 93ef push zl
-000efd 939a
-000efe 938a savetos
-000eff 01cf movw tosl, zl
-000f00 940c 1c05 jmp_ DO_NEXT
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-001c01 93bf push XH
-001c02 93af push XL ; PUSH IP
-001c03 01db movw XL, wl
-001c04 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-001c05 14b2 cp isrflag, zerol
-001c06 f469 brne DO_INTERRUPT
- .endif
-001c07 01fd movw zl, XL ; READ IP
-001c08 0fee
-001c09 1fff
-001c0a 9165
-001c0b 9175 readflashcell wl, wh
-001c0c 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-001c0d 01fb movw zl, wl
-001c0e 0fee
-001c0f 1fff
-001c10 9105
-001c11 9115 readflashcell temp0,temp1
-001c12 01f8 movw zl, temp0
-001c13 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-001c14 939a
-001c15 938a savetos
-001c16 2d8b mov tosl, isrflag
-001c17 2799 clr tosh
-001c18 24bb clr isrflag
-001c19 e26f ldi wl, LOW(XT_ISREXEC)
-001c1a e072 ldi wh, HIGH(XT_ISREXEC)
-001c1b cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-001c1c ff04 .dw $ff04
-001c1d 7865
-001c1e 7469 .db "exit"
-001c1f 0eee .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-001c20 1c21 .dw PFA_EXIT
- PFA_EXIT:
-001c21 91af pop XL
-001c22 91bf pop XH
-001c23 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-001c24 ff07 .dw $ff07
-001c25 7865
-001c26 6365
-001c27 7475
-001c28 0065 .db "execute",0
-001c29 1c1c .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-001c2a 1c2b .dw PFA_EXECUTE
- PFA_EXECUTE:
-001c2b 01bc movw wl, tosl
-001c2c 9189
-001c2d 9199 loadtos
-001c2e cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-001c2f 1c30 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-001c30 01fd movw zl, XL
-001c31 0fee
-001c32 1fff
-001c33 91a5
-001c34 91b5 readflashcell XL,XH
-001c35 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-001c36 1c37 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-001c37 2b98 or tosh, tosl
-001c38 9189
-001c39 9199 loadtos
-001c3a f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-001c3b 9611 adiw XL, 1
-001c3c cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-001c3d 1c3e .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-001c3e 939a
-001c3f 938a savetos
-001c40 01fd movw zl, xl
-001c41 0fee
-001c42 1fff
-001c43 9185
-001c44 9195 readflashcell tosl,tosh
-001c45 9611 adiw xl, 1
-001c46 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-001c47 1c48 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-001c48 939a
-001c49 938a savetos
-001c4a 01fb movw zl, wl
-001c4b 9631 adiw zl,1
-001c4c 0fee
-001c4d 1fff
-001c4e 9185
-001c4f 9195 readflashcell tosl,tosh
-001c50 cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-001c51 1c52 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-001c52 939a
-001c53 938a savetos
-001c54 01cb movw tosl, wl
-001c55 9601 adiw tosl, 1
-001c56 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-001c57 1c58 .dw PFA_DOUSER
- PFA_DOUSER:
-001c58 939a
-001c59 938a savetos
-001c5a 01fb movw zl, wl
-001c5b 9631 adiw zl, 1
-001c5c 0fee
-001c5d 1fff
-001c5e 9185
-001c5f 9195 readflashcell tosl,tosh
-001c60 0d84 add tosl, upl
-001c61 1d95 adc tosh, uph
-001c62 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-001c63 ff07 .dw $ff07
-001c64 7628
-001c65 6c61
-001c66 6575
-001c67 0029 .db "(value)", 0
-001c68 1c24 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-001c69 1c01 .dw DO_COLON
- PFA_DOVALUE:
-001c6a 0280 .dw XT_DOCREATE
-001c6b 03e0 .dw XT_REVEAL
-001c6c 02a3 .dw XT_COMPILE
-001c6d 1c6f .dw PFA_DOVALUE1
-001c6e 1c20 .dw XT_EXIT
- PFA_DOVALUE1:
-001c6f 940e 03f9 call_ DO_DODOES
-001c71 1cb1 .dw XT_DUP
-001c72 0c32 .dw XT_ICELLPLUS
-001c73 1fcb .dw XT_FETCHI
-001c74 1c2a .dw XT_EXECUTE
-001c75 1c20 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-001c76 ff01 .dw $ff01
-001c77 0040 .db "@",0
-001c78 1c63 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-001c79 1c7a .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-001c7a 01fc movw zl, tosl
- ; low byte is read before the high byte
-001c7b 9181 ld tosl, z+
-001c7c 9191 ld tosh, z+
-001c7d cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-001c7e ff01 .dw $ff01
-001c7f 0021 .db "!",0
-001c80 1c76 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-001c81 1c82 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-001c82 01fc movw zl, tosl
-001c83 9189
-001c84 9199 loadtos
- ; the high byte is written before the low byte
-001c85 8391 std Z+1, tosh
-001c86 8380 std Z+0, tosl
-001c87 9189
-001c88 9199 loadtos
-001c89 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-001c8a ff02 .dw $ff02
-001c8b 2163 .db "c!"
-001c8c 1c7e .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-001c8d 1c8e .dw PFA_CSTORE
- PFA_CSTORE:
-001c8e 01fc movw zl, tosl
-001c8f 9189
-001c90 9199 loadtos
-001c91 8380 st Z, tosl
-001c92 9189
-001c93 9199 loadtos
-001c94 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-001c95 ff02 .dw $ff02
-001c96 4063 .db "c@"
-001c97 1c8a .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-001c98 1c99 .dw PFA_CFETCH
- PFA_CFETCH:
-001c99 01fc movw zl, tosl
-001c9a 2799 clr tosh
-001c9b 8180 ld tosl, Z
-001c9c cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-001c9d ff02 .dw $ff02
-001c9e 7540 .db "@u"
-001c9f 1c95 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-001ca0 1c01 .dw DO_COLON
- PFA_FETCHU:
-001ca1 1f02 .dw XT_UP_FETCH
-001ca2 1d9d .dw XT_PLUS
-001ca3 1c79 .dw XT_FETCH
-001ca4 1c20 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-001ca5 ff02 .dw $ff02
-001ca6 7521 .db "!u"
-001ca7 1c9d .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-001ca8 1c01 .dw DO_COLON
- PFA_STOREU:
-001ca9 1f02 .dw XT_UP_FETCH
-001caa 1d9d .dw XT_PLUS
-001cab 1c81 .dw XT_STORE
-001cac 1c20 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-001cad ff03 .dw $ff03
-001cae 7564
-001caf 0070 .db "dup",0
-001cb0 1ca5 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-001cb1 1cb2 .dw PFA_DUP
- PFA_DUP:
-001cb2 939a
-001cb3 938a savetos
-001cb4 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-001cb5 ff04 .dw $ff04
-001cb6 643f
-001cb7 7075 .db "?dup"
-001cb8 1cad .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-001cb9 1cba .dw PFA_QDUP
- PFA_QDUP:
-001cba 2f08 mov temp0, tosl
-001cbb 2b09 or temp0, tosh
-001cbc f011 breq PFA_QDUP1
-001cbd 939a
-001cbe 938a savetos
- PFA_QDUP1:
-001cbf cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-001cc0 ff04 .dw $ff04
-001cc1 7773
-001cc2 7061 .db "swap"
-001cc3 1cb5 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-001cc4 1cc5 .dw PFA_SWAP
- PFA_SWAP:
-001cc5 018c movw temp0, tosl
-001cc6 9189
-001cc7 9199 loadtos
-001cc8 931a st -Y, temp1
-001cc9 930a st -Y, temp0
-001cca cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-001ccb ff04 .dw $ff04
-001ccc 766f
-001ccd 7265 .db "over"
-001cce 1cc0 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-001ccf 1cd0 .dw PFA_OVER
- PFA_OVER:
-001cd0 939a
-001cd1 938a savetos
-001cd2 818a ldd tosl, Y+2
-001cd3 819b ldd tosh, Y+3
-
-001cd4 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-001cd5 ff04 .dw $ff04
-001cd6 7264
-001cd7 706f .db "drop"
-001cd8 1ccb .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-001cd9 1cda .dw PFA_DROP
- PFA_DROP:
-001cda 9189
-001cdb 9199 loadtos
-001cdc cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-001cdd ff03 .dw $ff03
-001cde 6f72
-001cdf 0074 .db "rot",0
-001ce0 1cd5 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-001ce1 1ce2 .dw PFA_ROT
- PFA_ROT:
-001ce2 018c movw temp0, tosl
-001ce3 9129 ld temp2, Y+
-001ce4 9139 ld temp3, Y+
-001ce5 9189
-001ce6 9199 loadtos
-
-001ce7 933a st -Y, temp3
-001ce8 932a st -Y, temp2
-001ce9 931a st -Y, temp1
-001cea 930a st -Y, temp0
-
-001ceb cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-001cec ff03 .dw $ff03
-001ced 696e
-001cee 0070 .db "nip",0
-001cef 1cdd .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-001cf0 1cf1 .dw PFA_NIP
- PFA_NIP:
-001cf1 9622 adiw yl, 2
-001cf2 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-001cf3 ff02 .dw $ff02
-001cf4 3e72 .db "r>"
-001cf5 1cec .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-001cf6 1cf7 .dw PFA_R_FROM
- PFA_R_FROM:
-001cf7 939a
-001cf8 938a savetos
-001cf9 918f pop tosl
-001cfa 919f pop tosh
-001cfb cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-001cfc ff02 .dw $ff02
-001cfd 723e .db ">r"
-001cfe 1cf3 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-001cff 1d00 .dw PFA_TO_R
- PFA_TO_R:
-001d00 939f push tosh
-001d01 938f push tosl
-001d02 9189
-001d03 9199 loadtos
-001d04 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-001d05 ff02 .dw $ff02
-001d06 4072 .db "r@"
-001d07 1cfc .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-001d08 1d09 .dw PFA_R_FETCH
- PFA_R_FETCH:
-001d09 939a
-001d0a 938a savetos
-001d0b 918f pop tosl
-001d0c 919f pop tosh
-001d0d 939f push tosh
-001d0e 938f push tosl
-001d0f cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-001d10 ff02 .dw $ff02
-001d11 3e3c .db "<>"
-001d12 1d05 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-001d13 1c01 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-001d14 1fe0
-001d15 1d1a
-001d16 1c20 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-001d17 ff02 .dw $ff02
-001d18 3d30 .db "0="
-001d19 1d10 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-001d1a 1d1b .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-001d1b 2b98 or tosh, tosl
-001d1c f5d1 brne PFA_ZERO1
-001d1d c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-001d1e ff02 .dw $ff02
-001d1f 3c30 .db "0<"
-001d20 1d17 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-001d21 1d22 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-001d22 fd97 sbrc tosh,7
-001d23 c02a rjmp PFA_TRUE1
-001d24 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-001d25 ff02 .dw $ff02
-001d26 3e30 .db "0>"
-001d27 1d1e .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-001d28 1d29 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-001d29 1582 cp tosl, zerol
-001d2a 0593 cpc tosh, zeroh
-001d2b f15c brlt PFA_ZERO1
-001d2c f151 brbs 1, PFA_ZERO1
-001d2d c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-001d2e ff03 .dw $ff03
-001d2f 3064
-001d30 003e .db "d0>",0
-001d31 1d25 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-001d32 1d33 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-001d33 1582 cp tosl, zerol
-001d34 0593 cpc tosh, zeroh
-001d35 9189
-001d36 9199 loadtos
-001d37 0582 cpc tosl, zerol
-001d38 0593 cpc tosh, zeroh
-001d39 f0ec brlt PFA_ZERO1
-001d3a f0e1 brbs 1, PFA_ZERO1
-001d3b c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-001d3c ff03 .dw $ff03
-001d3d 3064
-001d3e 003c .db "d0<",0
-001d3f 1d2e .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-001d40 1d41 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-001d41 9622 adiw Y,2
-001d42 fd97 sbrc tosh,7
-001d43 940c 1d4e jmp PFA_TRUE1
-001d45 940c 1d57 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-001d47 ff04 .dw $ff04
-001d48 7274
-001d49 6575 .db "true"
-001d4a 1d3c .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-001d4b 1d4c .dw PFA_TRUE
- PFA_TRUE:
-001d4c 939a
-001d4d 938a savetos
- PFA_TRUE1:
-001d4e ef8f ser tosl
-001d4f ef9f ser tosh
-001d50 ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-001d51 ff01 .dw $ff01
-001d52 0030 .db "0",0
-001d53 1d47 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-001d54 1d55 .dw PFA_ZERO
- PFA_ZERO:
-001d55 939a
-001d56 938a savetos
- PFA_ZERO1:
-001d57 01c1 movw tosl, zerol
-001d58 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-001d59 ff02 .dw $ff02
-001d5a 3c75 .db "u<"
-001d5b 1d51 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-001d5c 1d5d .dw PFA_ULESS
- PFA_ULESS:
-001d5d 9129 ld temp2, Y+
-001d5e 9139 ld temp3, Y+
-001d5f 1782 cp tosl, temp2
-001d60 0793 cpc tosh, temp3
-001d61 f3a8 brlo PFA_ZERO1
-001d62 f3a1 brbs 1, PFA_ZERO1
-001d63 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-001d64 ff02 .dw $ff02
-001d65 3e75 .db "u>"
-001d66 1d59 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-001d67 1c01 .dw DO_COLON
- PFA_UGREATER:
- .endif
-001d68 1cc4 .DW XT_SWAP
-001d69 1d5c .dw XT_ULESS
-001d6a 1c20 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-001d6b ff01 .dw $ff01
-001d6c 003c .db "<",0
-001d6d 1d64 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-001d6e 1d6f .dw PFA_LESS
- PFA_LESS:
-001d6f 9129 ld temp2, Y+
-001d70 9139 ld temp3, Y+
-001d71 1728 cp temp2, tosl
-001d72 0739 cpc temp3, tosh
- PFA_LESSDONE:
-001d73 f71c brge PFA_ZERO1
-001d74 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-001d75 ff01 .dw $ff01
-001d76 003e .db ">",0
-001d77 1d6b .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-001d78 1d79 .dw PFA_GREATER
- PFA_GREATER:
-001d79 9129 ld temp2, Y+
-001d7a 9139 ld temp3, Y+
-001d7b 1728 cp temp2, tosl
-001d7c 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-001d7d f2cc brlt PFA_ZERO1
-001d7e f2c1 brbs 1, PFA_ZERO1
-001d7f cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-001d80 ff04 .dw $ff04
-001d81 6f6c
-001d82 3267 .db "log2"
-001d83 1d75 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-001d84 1d85 .dw PFA_LOG2
- PFA_LOG2:
-001d85 01fc movw zl, tosl
-001d86 2799 clr tosh
-001d87 e180 ldi tosl, 16
- PFA_LOG2_1:
-001d88 958a dec tosl
-001d89 f022 brmi PFA_LOG2_2 ; wrong data
-001d8a 0fee lsl zl
-001d8b 1fff rol zh
-001d8c f7d8 brcc PFA_LOG2_1
-001d8d ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-001d8e 959a dec tosh
-001d8f ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-001d90 ff01 .dw $ff01
-001d91 002d .db "-",0
-001d92 1d80 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-001d93 1d94 .dw PFA_MINUS
- PFA_MINUS:
-001d94 9109 ld temp0, Y+
-001d95 9119 ld temp1, Y+
-001d96 1b08 sub temp0, tosl
-001d97 0b19 sbc temp1, tosh
-001d98 01c8 movw tosl, temp0
-001d99 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-001d9a ff01 .dw $ff01
-001d9b 002b .db "+",0
-001d9c 1d90 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-001d9d 1d9e .dw PFA_PLUS
- PFA_PLUS:
-001d9e 9109 ld temp0, Y+
-001d9f 9119 ld temp1, Y+
-001da0 0f80 add tosl, temp0
-001da1 1f91 adc tosh, temp1
-001da2 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-001da3 ff02 .dw $ff02
-001da4 2a6d .db "m*"
-001da5 1d9a .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-001da6 1da7 .dw PFA_MSTAR
- PFA_MSTAR:
-001da7 018c movw temp0, tosl
-001da8 9189
-001da9 9199 loadtos
-001daa 019c movw temp2, tosl
- ; high cell ah*bh
-001dab 0231 muls temp3, temp1
-001dac 0170 movw temp4, r0
- ; low cell al*bl
-001dad 9f20 mul temp2, temp0
-001dae 01c0 movw tosl, r0
- ; signed ah*bl
-001daf 0330 mulsu temp3, temp0
-001db0 08f3 sbc temp5, zeroh
-001db1 0d90 add tosh, r0
-001db2 1ce1 adc temp4, r1
-001db3 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-001db4 0312 mulsu temp1, temp2
-001db5 08f3 sbc temp5, zeroh
-001db6 0d90 add tosh, r0
-001db7 1ce1 adc temp4, r1
-001db8 1cf3 adc temp5, zeroh
-
-001db9 939a
-001dba 938a savetos
-001dbb 01c7 movw tosl, temp4
-001dbc ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-001dbd ff06 .dw $ff06
-001dbe 6d75
-001dbf 6d2f
-001dc0 646f .db "um/mod"
-001dc1 1da3 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-001dc2 1dc3 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-001dc3 017c movw temp4, tosl
-
-001dc4 9129 ld temp2, Y+
-001dc5 9139 ld temp3, Y+
-
-001dc6 9109 ld temp0, Y+
-001dc7 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-001dc8 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-001dc9 2755 clr temp7
-001dca 0f00 lsl temp0
-001dcb 1f11 rol temp1
-001dcc 1f22 rol temp2
-001dcd 1f33 rol temp3
-001dce 1f55 rol temp7
-
- ; try subtracting divisor
-001dcf 152e cp temp2, temp4
-001dd0 053f cpc temp3, temp5
-001dd1 0552 cpc temp7,zerol
-
-001dd2 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-001dd3 9503 inc temp0
-001dd4 192e sub temp2, temp4
-001dd5 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-001dd6 954a dec temp6
-001dd7 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-001dd8 933a st -Y,temp3
-001dd9 932a st -Y,temp2
-
- ; put quotient on stack
-001dda 01c8 movw tosl, temp0
-001ddb ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-001ddc ff03 .dw $ff03
-001ddd 6d75
-001dde 002a .db "um*",0
-001ddf 1dbd .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-001de0 1de1 .dw PFA_UMSTAR
- PFA_UMSTAR:
-001de1 018c movw temp0, tosl
-001de2 9189
-001de3 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-001de4 9f80 mul tosl,temp0
-001de5 01f0 movw zl, r0
-001de6 2722 clr temp2
-001de7 2733 clr temp3
- ; middle bytes
-001de8 9f90 mul tosh, temp0
-001de9 0df0 add zh, r0
-001dea 1d21 adc temp2, r1
-001deb 1d33 adc temp3, zeroh
-
-001dec 9f81 mul tosl, temp1
-001ded 0df0 add zh, r0
-001dee 1d21 adc temp2, r1
-001def 1d33 adc temp3, zeroh
-
-001df0 9f91 mul tosh, temp1
-001df1 0d20 add temp2, r0
-001df2 1d31 adc temp3, r1
-001df3 01cf movw tosl, zl
-001df4 939a
-001df5 938a savetos
-001df6 01c9 movw tosl, temp2
-001df7 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-001df8 ff06 .dw $ff06
-001df9 6e69
-001dfa 6576
-001dfb 7472 .db "invert"
-001dfc 1ddc .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-001dfd 1dfe .dw PFA_INVERT
- PFA_INVERT:
-001dfe 9580 com tosl
-001dff 9590 com tosh
-001e00 ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-001e01 ff02 .dw $ff02
-001e02 2f32 .db "2/"
-001e03 1df8 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-001e04 1e05 .dw PFA_2SLASH
- PFA_2SLASH:
-001e05 9595 asr tosh
-001e06 9587 ror tosl
-001e07 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-001e08 ff02 .dw $ff02
-001e09 2a32 .db "2*"
-001e0a 1e01 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-001e0b 1e0c .dw PFA_2STAR
- PFA_2STAR:
-001e0c 0f88 lsl tosl
-001e0d 1f99 rol tosh
-001e0e cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-001e0f ff03 .dw $ff03
-001e10 6e61
-001e11 0064 .db "and",0
-001e12 1e08 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-001e13 1e14 .dw PFA_AND
- PFA_AND:
-001e14 9109 ld temp0, Y+
-001e15 9119 ld temp1, Y+
-001e16 2380 and tosl, temp0
-001e17 2391 and tosh, temp1
-001e18 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-001e19 ff02 .dw $ff02
-001e1a 726f .db "or"
-001e1b 1e0f .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-001e1c 1e1d .dw PFA_OR
- PFA_OR:
-001e1d 9109 ld temp0, Y+
-001e1e 9119 ld temp1, Y+
-001e1f 2b80 or tosl, temp0
-001e20 2b91 or tosh, temp1
-001e21 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-001e22 ff03 .dw $ff03
-001e23 6f78
-001e24 0072 .db "xor",0
-001e25 1e19 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-001e26 1e27 .dw PFA_XOR
- PFA_XOR:
-001e27 9109 ld temp0, Y+
-001e28 9119 ld temp1, Y+
-001e29 2780 eor tosl, temp0
-001e2a 2791 eor tosh, temp1
-001e2b cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-001e2c ff02 .dw $ff02
-001e2d 2b31 .db "1+"
-001e2e 1e22 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-001e2f 1e30 .dw PFA_1PLUS
- PFA_1PLUS:
-001e30 9601 adiw tosl,1
-001e31 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-001e32 ff02 .dw $ff02
-001e33 2d31 .db "1-"
-001e34 1e2c .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-001e35 1e36 .dw PFA_1MINUS
- PFA_1MINUS:
-001e36 9701 sbiw tosl, 1
-001e37 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-001e38 ff07 .dw $ff07
-001e39 6e3f
-001e3a 6765
-001e3b 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-001e3c 0065 .db "?negate"
-001e3d 1e32 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-001e3e 1c01 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-001e3f 1d21
-001e40 1c36 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-001e41 1e43 DEST(QNEG1)
-001e42 06c6 .DW XT_NEGATE
-001e43 1c20 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-001e44 ff06 .dw $ff06
-001e45 736c
-001e46 6968
-001e47 7466 .db "lshift"
-001e48 1e38 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-001e49 1e4a .dw PFA_LSHIFT
- PFA_LSHIFT:
-001e4a 01fc movw zl, tosl
-001e4b 9189
-001e4c 9199 loadtos
- PFA_LSHIFT1:
-001e4d 9731 sbiw zl, 1
-001e4e f01a brmi PFA_LSHIFT2
-001e4f 0f88 lsl tosl
-001e50 1f99 rol tosh
-001e51 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-001e52 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-001e53 ff06 .dw $ff06
-001e54 7372
-001e55 6968
-001e56 7466 .db "rshift"
-001e57 1e44 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-001e58 1e59 .dw PFA_RSHIFT
- PFA_RSHIFT:
-001e59 01fc movw zl, tosl
-001e5a 9189
-001e5b 9199 loadtos
- PFA_RSHIFT1:
-001e5c 9731 sbiw zl, 1
-001e5d f01a brmi PFA_RSHIFT2
-001e5e 9596 lsr tosh
-001e5f 9587 ror tosl
-001e60 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-001e61 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-001e62 ff02 .dw $ff02
-001e63 212b .db "+!"
-001e64 1e53 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-001e65 1e66 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-001e66 01fc movw zl, tosl
-001e67 9189
-001e68 9199 loadtos
-001e69 8120 ldd temp2, Z+0
-001e6a 8131 ldd temp3, Z+1
-001e6b 0f82 add tosl, temp2
-001e6c 1f93 adc tosh, temp3
-001e6d 8380 std Z+0, tosl
-001e6e 8391 std Z+1, tosh
-001e6f 9189
-001e70 9199 loadtos
-001e71 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-001e72 ff03 .dw $ff03
-001e73 7072
-001e74 0040 .db "rp@",0
-001e75 1e62 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-001e76 1e77 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-001e77 939a
-001e78 938a savetos
-001e79 b78d in tosl, SPL
-001e7a b79e in tosh, SPH
-001e7b cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-001e7c ff03 .dw $ff03
-001e7d 7072
-001e7e 0021 .db "rp!",0
-001e7f 1e72 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-001e80 1e81 .dw PFA_RP_STORE
- PFA_RP_STORE:
-001e81 b72f in temp2, SREG
-001e82 94f8 cli
-001e83 bf8d out SPL, tosl
-001e84 bf9e out SPH, tosh
-001e85 bf2f out SREG, temp2
-001e86 9189
-001e87 9199 loadtos
-001e88 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-001e89 ff03 .dw $ff03
-001e8a 7073
-001e8b 0040 .db "sp@",0
-001e8c 1e7c .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-001e8d 1e8e .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-001e8e 939a
-001e8f 938a savetos
-001e90 01ce movw tosl, yl
-001e91 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-001e92 ff03 .dw $ff03
-001e93 7073
-001e94 0021 .db "sp!",0
-001e95 1e89 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-001e96 1e97 .dw PFA_SP_STORE
- PFA_SP_STORE:
-001e97 01ec movw yl, tosl
-001e98 9189
-001e99 9199 loadtos
-001e9a cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-001e9b 1e9c .dw PFA_DODO
- PFA_DODO:
-001e9c 9129 ld temp2, Y+
-001e9d 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-001e9e e8e0 ldi zl, $80
-001e9f 0f3e add temp3, zl
-001ea0 1b82 sub tosl, temp2
-001ea1 0b93 sbc tosh, temp3
-
-001ea2 933f push temp3
-001ea3 932f push temp2 ; limit ( --> limit + $8000)
-001ea4 939f push tosh
-001ea5 938f push tosl ; start -> index ( --> index - (limit - $8000)
-001ea6 9189
-001ea7 9199 loadtos
-001ea8 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-001ea9 ff01 .dw $FF01
-001eaa 0069 .db "i",0
-001eab 1e92 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-001eac 1ead .dw PFA_I
- PFA_I:
-001ead 939a
-001eae 938a savetos
-001eaf 918f pop tosl
-001eb0 919f pop tosh ; index
-001eb1 91ef pop zl
-001eb2 91ff pop zh ; limit
-001eb3 93ff push zh
-001eb4 93ef push zl
-001eb5 939f push tosh
-001eb6 938f push tosl
-001eb7 0f8e add tosl, zl
-001eb8 1f9f adc tosh, zh
-001eb9 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-001eba 1ebb .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-001ebb 91ef pop zl
-001ebc 91ff pop zh
-001ebd 0fe8 add zl, tosl
-001ebe 1ff9 adc zh, tosh
-001ebf 9189
-001ec0 9199 loadtos
-001ec1 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-001ec2 93ff push zh
-001ec3 93ef push zl
-001ec4 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-001ec5 910f pop temp0
-001ec6 911f pop temp1 ; remove limit
-001ec7 9611 adiw xl, 1 ; skip branch-back address
-001ec8 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-001ec9 1eca .dw PFA_DOLOOP
- PFA_DOLOOP:
-001eca 91ef pop zl
-001ecb 91ff pop zh
-001ecc 9631 adiw zl,1
-001ecd f3bb brvs PFA_DOPLUSLOOP_LEAVE
-001ece cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-001ecf ff06 .dw $ff06
-001ed0 6e75
-001ed1 6f6c
-001ed2 706f .db "unloop"
-001ed3 1ea9 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-001ed4 1ed5 .dw PFA_UNLOOP
- PFA_UNLOOP:
-001ed5 911f pop temp1
-001ed6 910f pop temp0
-001ed7 911f pop temp1
-001ed8 910f pop temp0
-001ed9 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-001eda ff06 .dw $ff06
-001edb 6d63
-001edc 766f
-001edd 3e65 .db "cmove>"
-001ede 1ecf .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-001edf 1ee0 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-001ee0 93bf push xh
-001ee1 93af push xl
-001ee2 91e9 ld zl, Y+
-001ee3 91f9 ld zh, Y+ ; addr-to
-001ee4 91a9 ld xl, Y+
-001ee5 91b9 ld xh, Y+ ; addr-from
-001ee6 2f09 mov temp0, tosh
-001ee7 2b08 or temp0, tosl
-001ee8 f041 brbs 1, PFA_CMOVE_G1
-001ee9 0fe8 add zl, tosl
-001eea 1ff9 adc zh, tosh
-001eeb 0fa8 add xl, tosl
-001eec 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-001eed 911e ld temp1, -X
-001eee 9312 st -Z, temp1
-001eef 9701 sbiw tosl, 1
-001ef0 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-001ef1 91af pop xl
-001ef2 91bf pop xh
-001ef3 9189
-001ef4 9199 loadtos
-001ef5 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-001ef6 ff02 .dw $ff02
-001ef7 3c3e .db "><"
-001ef8 1eda .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-001ef9 1efa .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-001efa 2f09 mov temp0, tosh
-001efb 2f98 mov tosh, tosl
-001efc 2f80 mov tosl, temp0
-001efd cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-001efe ff03 .dw $ff03
-001eff 7075
-001f00 0040 .db "up@",0
-001f01 1ef6 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-001f02 1f03 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-001f03 939a
-001f04 938a savetos
-001f05 01c2 movw tosl, upl
-001f06 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-001f07 ff03 .dw $ff03
-001f08 7075
-001f09 0021 .db "up!",0
-001f0a 1efe .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-001f0b 1f0c .dw PFA_UP_STORE
- PFA_UP_STORE:
-001f0c 012c movw upl, tosl
-001f0d 9189
-001f0e 9199 loadtos
-001f0f ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-001f10 ff03 .dw $ff03
-001f11 6d31
-001f12 0073 .db "1ms",0
-001f13 1f07 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-001f14 1f15 .dw PFA_1MS
- PFA_1MS:
-001f15 ede0
-001f16 e0f7
-001f17 9731
-001f18 f7f1 delay 1000
-001f19 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-001f1a ff03 .dw $ff03
-001f1b 3e32
-001f1c 0072 .db "2>r",0
-001f1d 1f10 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-001f1e 1f1f .dw PFA_2TO_R
- PFA_2TO_R:
-001f1f 01fc movw zl, tosl
-001f20 9189
-001f21 9199 loadtos
-001f22 939f push tosh
-001f23 938f push tosl
-001f24 93ff push zh
-001f25 93ef push zl
-001f26 9189
-001f27 9199 loadtos
-001f28 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-001f29 ff03 .dw $ff03
-001f2a 7232
-001f2b 003e .db "2r>",0
-001f2c 1f1a .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-001f2d 1f2e .dw PFA_2R_FROM
- PFA_2R_FROM:
-001f2e 939a
-001f2f 938a savetos
-001f30 91ef pop zl
-001f31 91ff pop zh
-001f32 918f pop tosl
-001f33 919f pop tosh
-001f34 939a
-001f35 938a savetos
-001f36 01cf movw tosl, zl
-001f37 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-001f38 ff02 .dw $ff02
-001f39 6521 .db "!e"
-001f3a 1f29 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-001f3b 1f3c .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-001f3c 01fc movw zl, tosl
-001f3d 9189
-001f3e 9199 loadtos
-001f3f b72f in_ temp2, SREG
-001f40 94f8 cli
-001f41 d028 rcall PFA_FETCHE2
-001f42 b30d in_ temp0, EEDR
-001f43 1708 cp temp0,tosl
-001f44 f009 breq PFA_STOREE3
-001f45 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-001f46 9631 adiw zl,1
-001f47 d022 rcall PFA_FETCHE2
-001f48 b30d in_ temp0, EEDR
-001f49 1709 cp temp0,tosh
-001f4a f011 breq PFA_STOREE4
-001f4b 2f89 mov tosl, tosh
-001f4c d004 rcall PFA_STOREE1
- PFA_STOREE4:
-001f4d bf2f out_ SREG, temp2
-001f4e 9189
-001f4f 9199 loadtos
-001f50 ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-001f51 99e1 sbic EECR, EEPE
-001f52 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-001f53 b707 in_ temp0, SPMCSR
-001f54 fd00 sbrc temp0,SPMEN
-001f55 cffd rjmp PFA_STOREE2
-
-001f56 bbff out_ EEARH,zh
-001f57 bbee out_ EEARL,zl
-001f58 bb8d out_ EEDR, tosl
-001f59 9ae2 sbi EECR,EEMPE
-001f5a 9ae1 sbi EECR,EEPE
-
-001f5b 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-001f5c ff02 .dw $ff02
-001f5d 6540 .db "@e"
-001f5e 1f38 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-001f5f 1f60 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-001f60 b72f in_ temp2, SREG
-001f61 94f8 cli
-001f62 01fc movw zl, tosl
-001f63 d006 rcall PFA_FETCHE2
-001f64 b38d in_ tosl, EEDR
-
-001f65 9631 adiw zl,1
-
-001f66 d003 rcall PFA_FETCHE2
-001f67 b39d in_ tosh, EEDR
-001f68 bf2f out_ SREG, temp2
-001f69 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-001f6a 99e1 sbic EECR, EEPE
-001f6b cffe rjmp PFA_FETCHE2
-
-001f6c bbff out_ EEARH,zh
-001f6d bbee out_ EEARL,zl
-
-001f6e 9ae0 sbi EECR,EERE
-001f6f 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-001f70 ff02 .dw $ff02
-001f71 6921 .db "!i"
-001f72 1f5c .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-001f73 0c9a .dw PFA_DODEFER1
- PFA_STOREI:
-001f74 005c .dw EE_STOREI
-001f75 0c3b .dw XT_EDEFERFETCH
-001f76 0c45 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-001f77 ff09 .dw $ff09
-001f78 2128
-001f79 2d69
-001f7a 726e
-001f7b 7777
-001f7c 0029 .db "(!i-nrww)",0
-001f7d 1f70 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-001f7e 1f7f .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-001f7f b71f in temp1,SREG
-001f80 931f push temp1
-001f81 94f8 cli
-
-001f82 019c movw temp2, tosl ; save the (word) address
-001f83 9189
-001f84 9199 loadtos ; get the new value for the flash cell
-001f85 93af push xl
-001f86 93bf push xh
-001f87 93cf push yl
-001f88 93df push yh
-001f89 d009 rcall DO_STOREI_atmega
-001f8a 91df pop yh
-001f8b 91cf pop yl
-001f8c 91bf pop xh
-001f8d 91af pop xl
- ; finally clear the stack
-001f8e 9189
-001f8f 9199 loadtos
-001f90 911f pop temp1
- ; restore status register (and interrupt enable flag)
-001f91 bf1f out SREG,temp1
-
-001f92 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-001f93 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-001f94 94e0 com temp4
-001f95 94f0 com temp5
-001f96 218e and tosl, temp4
-001f97 219f and tosh, temp5
-001f98 2b98 or tosh, tosl
-001f99 f019 breq DO_STOREI_writepage
-001f9a 01f9 movw zl, temp2
-001f9b e002 ldi temp0,(1<<PGERS)
-001f9c d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-001f9d 01f9 movw zl, temp2
-001f9e e004 ldi temp0,(1<<PGWRT)
-001f9f d01d rcall dospm
-
- ; reenable RWW section
-001fa0 01f9 movw zl, temp2
-001fa1 e100 ldi temp0,(1<<RWWSRE)
-001fa2 d01a rcall dospm
-001fa3 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-001fa4 01f9 movw zl, temp2
- ; get the beginning of page
-001fa5 7ce0 andi zl,low(pagemask)
-001fa6 7fff andi zh,high(pagemask)
-001fa7 01ef movw y, z
- ; loop counter (in words)
-001fa8 e4a0 ldi xl,low(pagesize)
-001fa9 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-001faa 01fe movw z, y
-001fab 0fee
-001fac 1fff
-001fad 9145
-001fae 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-001faf 01fe movw z, y
-001fb0 17e2 cp zl, temp2
-001fb1 07f3 cpc zh, temp3
-001fb2 f011 breq pageload_newdata
-001fb3 010a movw r0, temp6
-001fb4 c002 rjmp pageload_cont
- pageload_newdata:
-001fb5 017a movw temp4, temp6
-001fb6 010c movw r0, tosl
- pageload_cont:
-001fb7 2700 clr temp0
-001fb8 d004 rcall dospm
-001fb9 9621 adiw y, 1
-001fba 9711 sbiw x, 1
-001fbb f771 brne pageload_loop
-
- pageload_done:
-001fbc 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-001fbd 99e1 sbic EECR, EEPE
-001fbe cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-001fbf b717 in_ temp1, SPMCSR
-001fc0 fd10 sbrc temp1, SPMEN
-001fc1 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-001fc2 0fee
-001fc3 1fff writeflashcell
- ; execute spm
-001fc4 6001 ori temp0, (1<<SPMEN)
-001fc5 bf07 out_ SPMCSR,temp0
-001fc6 95e8 spm
-001fc7 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-001fc8 ff02 .dw $ff02
-001fc9 6940 .db "@i"
-001fca 1f77 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-001fcb 1fcc .dw PFA_FETCHI
- PFA_FETCHI:
-001fcc 01fc movw zl, tosl
-001fcd 0fee
-001fce 1fff
-001fcf 9185
-001fd0 9195 readflashcell tosl,tosh
-001fd1 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .elif AMFORTH_NRWW_SIZE>4000
- .elif AMFORTH_NRWW_SIZE>2000
- .include "dict/core_2k.inc"
-
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-001fd2 0008 .dw $0008
-001fd3 6c32
-001fd4 7469
-001fd5 7265
-001fd6 6c61 .db "2literal"
-001fd7 1fc8 .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-001fd8 1c01 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-001fd9 1cc4 .dw XT_SWAP
-001fda 02c4 .dw XT_LITERAL
-001fdb 02c4 .dw XT_LITERAL
-001fdc 1c20 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-001fdd ff01 .dw $ff01
-001fde 003d .db "=",0
-001fdf 1fd2 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-001fe0 1c01 .dw DO_COLON
- PFA_EQUAL:
-001fe1 1d93 .dw XT_MINUS
-001fe2 1d1a .dw XT_ZEROEQUAL
-001fe3 1c20 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-001fe4 ff01 .dw $ff01
-001fe5 0031 .db "1",0
-001fe6 1fdd .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-001fe7 1c48 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-001fe8 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-001fe9 ff01 .dw $ff01
-001fea 0032 .db "2",0
-001feb 1fe4 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-001fec 1c48 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-001fed 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-001fee ff02 .dw $ff02
-001fef 312d .db "-1"
-001ff0 1fe9 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-001ff1 1c48 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-001ff2 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-00002a ff ff
- ; some configs
-00002c 02 0f CFG_DP: .dw DPSTART ; Dictionary Pointer
-00002e 1d 01 EE_HERE: .dw HERESTART ; Memory Allocation
-000030 84 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-000032 15 05 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-000034 52 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000036 10 04 CFG_LP0: .dw stackstart+1
-000038 54 0e CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-00003a b7 05 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-00003c 3e 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-00003e ee 1f CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-000040 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-000042 3e 00 .dw CFG_FORTHWORDLIST ; get/set-order
-000044 .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-000052 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-000054 ab 0b .dw XT_REC_FIND
-000056 97 0b .dw XT_REC_NUM
-000058 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-00005c 7e 1f .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-00005e 5e 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-000060 00 00 .dw 0 ; USER_STATE
-000062 00 00 .dw 0 ; USER_FOLLOWER
-000064 5f 04 .dw rstackstart ; USER_RP
-000066 0f 04 .dw stackstart ; USER_SP0
-000068 0f 04 .dw stackstart ; USER_SP
-
-00006a 00 00 .dw 0 ; USER_HANDLER
-00006c 0a 00 .dw 10 ; USER_BASE
-
-00006e 98 00 .dw XT_TX ; USER_EMIT
-000070 a6 00 .dw XT_TXQ ; USER_EMITQ
-000072 6d 00 .dw XT_RX ; USER_KEY
-000074 88 00 .dw XT_RXQ ; USER_KEYQ
-000076 ac 0d .dw XT_SOURCETIB ; USER_SOURCE
-000078 00 00 .dw 0 ; USER_G_IN
-00007a 99 0d .dw XT_REFILLTIB ; USER_REFILL
-00007c 99 0a .dw XT_DEFAULT_PROMPTOK
-00007e b8 0a .dw XT_DEFAULT_PROMPTERROR
-000080 a8 0a .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-000082 0c 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega16" register use summary:
-r0 : 25 r1 : 5 r2 : 10 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 85 r17: 61 r18: 61 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 203 r25: 139 r26: 28 r27: 17 r28: 7 r29: 4 r30: 85 r31: 47
-x : 4 y : 209 z : 50
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega16" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 20 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 1
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 14 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 8 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 25 inc : 3 jmp : 25
-ld : 141 ldd : 4 ldi : 41 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 14 movw : 70 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 2 out : 22 pop : 45
-push : 39 rcall : 34 ret : 7 reti : 1 rjmp : 92 rol : 23
-ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3 sbis : 0
-sbiw : 16 sbr : 0 sbrc : 5 sbrs : 7 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 4 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 77 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 72 out of 113 (63.7%)
-
-"ATmega16" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x003fe6 2044 9642 11686 16384 71.3%
-[.dseg] 0x000060 0x00011d 0 189 189 1024 18.5%
-[.eseg] 0x000000 0x000084 0 132 132 512 25.8%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/eval-pollin/p16-8.map b/amforth-6.5/appl/eval-pollin/p16-8.map
deleted file mode 100644
index 8e30021..0000000
--- a/amforth-6.5/appl/eval-pollin/p16-8.map
+++ /dev/null
@@ -1,1961 +0,0 @@
-
-AVRASM ver. 2.1.52 p16-8.asm Sun Apr 30 20:10:14 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000094
-EQU SIGNATURE_002 00000003
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU OCR0 0000003c
-EQU GICR 0000003b
-EQU GIFR 0000003a
-EQU TIMSK 00000039
-EQU TIFR 00000038
-EQU SPMCSR 00000037
-EQU TWCR 00000036
-EQU MCUCR 00000035
-EQU MCUCSR 00000034
-EQU TCCR0 00000033
-EQU TCNT0 00000032
-EQU OSCCAL 00000031
-EQU OCDR 00000031
-EQU SFIOR 00000030
-EQU TCCR1A 0000002f
-EQU TCCR1B 0000002e
-EQU TCNT1L 0000002c
-EQU TCNT1H 0000002d
-EQU OCR1AL 0000002a
-EQU OCR1AH 0000002b
-EQU OCR1BL 00000028
-EQU OCR1BH 00000029
-EQU ICR1L 00000026
-EQU ICR1H 00000027
-EQU TCCR2 00000025
-EQU TCNT2 00000024
-EQU OCR2 00000023
-EQU ASSR 00000022
-EQU WDTCR 00000021
-EQU UBRRH 00000020
-EQU UCSRC 00000020
-EQU EEARL 0000001e
-EQU EEARH 0000001f
-EQU EEDR 0000001d
-EQU EECR 0000001c
-EQU PORTA 0000001b
-EQU DDRA 0000001a
-EQU PINA 00000019
-EQU PORTB 00000018
-EQU DDRB 00000017
-EQU PINB 00000016
-EQU PORTC 00000015
-EQU DDRC 00000014
-EQU PINC 00000013
-EQU PORTD 00000012
-EQU DDRD 00000011
-EQU PIND 00000010
-EQU SPDR 0000000f
-EQU SPSR 0000000e
-EQU SPCR 0000000d
-EQU UDR 0000000c
-EQU UCSRA 0000000b
-EQU UCSRB 0000000a
-EQU UBRRL 00000009
-EQU ACSR 00000008
-EQU ADMUX 00000007
-EQU ADCSRA 00000006
-EQU ADCH 00000005
-EQU ADCL 00000004
-EQU TWDR 00000003
-EQU TWAR 00000002
-EQU TWSR 00000001
-EQU TWBR 00000000
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM01 00000003
-EQU CTC0 00000003
-EQU COM00 00000004
-EQU COM01 00000005
-EQU WGM00 00000006
-EQU PWM0 00000006
-EQU FOC0 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0_0 00000000
-EQU OCR0_1 00000001
-EQU OCR0_2 00000002
-EQU OCR0_3 00000003
-EQU OCR0_4 00000004
-EQU OCR0_5 00000005
-EQU OCR0_6 00000006
-EQU OCR0_7 00000007
-EQU TOIE0 00000000
-EQU OCIE0 00000001
-EQU TOV0 00000000
-EQU OCF0 00000001
-EQU PSR10 00000000
-EQU TOIE1 00000002
-EQU OCIE1B 00000003
-EQU OCIE1A 00000004
-EQU TICIE1 00000005
-EQU TOV1 00000002
-EQU OCF1B 00000003
-EQU OCF1A 00000004
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU PWM10 00000000
-EQU WGM11 00000001
-EQU PWM11 00000001
-EQU FOC1B 00000002
-EQU FOC1A 00000003
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU CTC10 00000003
-EQU CTC1 00000003
-EQU WGM13 00000004
-EQU CTC11 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU GIMSK 0000003b
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU INT2 00000005
-EQU INT0 00000006
-EQU INT1 00000007
-EQU INTF2 00000005
-EQU INTF0 00000006
-EQU INTF1 00000007
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC2 00000006
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEWE 00000001
-EQU EEMWE 00000002
-EQU EEWEE 00000002
-EQU EERIE 00000003
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU SM0 00000004
-EQU SM1 00000005
-EQU SE 00000006
-EQU SM2 00000007
-EQU MCUSR 00000034
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU EXTREF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU JTRF 00000004
-EQU JTD 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU PSR2 00000001
-EQU PUD 00000002
-EQU TOIE2 00000006
-EQU OCIE2 00000007
-EQU TOV2 00000006
-EQU OCF2 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM21 00000003
-EQU CTC2 00000003
-EQU COM20 00000004
-EQU COM21 00000005
-EQU WGM20 00000006
-EQU PWM2 00000006
-EQU FOC2 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2_0 00000000
-EQU OCR2_1 00000001
-EQU OCR2_2 00000002
-EQU OCR2_3 00000003
-EQU OCR2_4 00000004
-EQU OCR2_5 00000005
-EQU OCR2_6 00000006
-EQU OCR2_7 00000007
-EQU TCR2UB 00000000
-EQU OCR2UB 00000001
-EQU TCN2UB 00000002
-EQU AS2 00000003
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU UDR0 00000000
-EQU UDR1 00000001
-EQU UDR2 00000002
-EQU UDR3 00000003
-EQU UDR4 00000004
-EQU UDR5 00000005
-EQU UDR6 00000006
-EQU UDR7 00000007
-EQU USR 0000000b
-EQU MPCM 00000000
-EQU U2X 00000001
-EQU UPE 00000002
-EQU PE 00000002
-EQU DOR 00000003
-EQU FE 00000004
-EQU UDRE 00000005
-EQU TXC 00000006
-EQU RXC 00000007
-EQU UCR 0000000a
-EQU TXB8 00000000
-EQU RXB8 00000001
-EQU UCSZ2 00000002
-EQU CHR9 00000002
-EQU TXEN 00000003
-EQU RXEN 00000004
-EQU UDRIE 00000005
-EQU TXCIE 00000006
-EQU RXCIE 00000007
-EQU UCPOL 00000000
-EQU UCSZ0 00000001
-EQU UCSZ1 00000002
-EQU USBS 00000003
-EQU UPM0 00000004
-EQU UPM1 00000005
-EQU UMSEL 00000006
-EQU URSEL 00000007
-EQU UBRRHI 00000020
-EQU I2BR 00000000
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU I2CR 00000036
-EQU TWIE 00000000
-EQU I2IE 00000000
-EQU TWEN 00000002
-EQU I2EN 00000002
-EQU ENI2C 00000002
-EQU TWWC 00000003
-EQU I2WC 00000003
-EQU TWSTO 00000004
-EQU I2STO 00000004
-EQU TWSTA 00000005
-EQU I2STA 00000005
-EQU TWEA 00000006
-EQU I2EA 00000006
-EQU TWINT 00000007
-EQU I2INT 00000007
-EQU I2SR 00000001
-EQU TWPS0 00000000
-EQU TWS0 00000000
-EQU I2GCE 00000000
-EQU TWPS1 00000001
-EQU TWS1 00000001
-EQU TWS3 00000003
-EQU I2S3 00000003
-EQU TWS4 00000004
-EQU I2S4 00000004
-EQU TWS5 00000005
-EQU I2S5 00000005
-EQU TWS6 00000006
-EQU I2S6 00000006
-EQU TWS7 00000007
-EQU I2S7 00000007
-EQU I2DR 00000003
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU I2AR 00000002
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU ACME 00000003
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADCSR 00000006
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADFR 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADTS0 00000005
-EQU ADTS1 00000006
-EQU ADTS2 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU SPMCR 00000037
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU ASRE 00000004
-EQU RWWSB 00000006
-EQU ASB 00000006
-EQU SPMIE 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDTOE 00000004
-EQU WDDE 00000004
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU BODEN 00000006
-EQU BODLEVEL 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU CKOPT 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00001fff
-EQU IOEND 0000003f
-EQU SRAM_START 00000060
-EQU SRAM_SIZE 00000400
-EQU RAMEND 0000045f
-EQU XRAMEND 00000000
-EQU E2END 000001ff
-EQU EEPROMEND 000001ff
-EQU EEADRBITS 00000009
-EQU NRWW_START_ADDR 00001c00
-EQU NRWW_STOP_ADDR 00001fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 00001bff
-EQU PAGESIZE 00000040
-EQU FIRSTBOOTSTART 00001f80
-EQU SECONDBOOTSTART 00001f00
-EQU THIRDBOOTSTART 00001e00
-EQU FOURTHBOOTSTART 00001c00
-EQU SMALLBOOTSTART 00001f80
-EQU LARGEBOOTSTART 00001c00
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU OC2addr 00000006
-EQU OVF2addr 00000008
-EQU ICP1addr 0000000a
-EQU OC1Aaddr 0000000c
-EQU OC1Baddr 0000000e
-EQU OVF1addr 00000010
-EQU OVF0addr 00000012
-EQU SPIaddr 00000014
-EQU URXCaddr 00000016
-EQU UDREaddr 00000018
-EQU UTXCaddr 0000001a
-EQU ADCCaddr 0000001c
-EQU ERDYaddr 0000001e
-EQU ACIaddr 00000020
-EQU TWIaddr 00000022
-EQU INT2addr 00000024
-EQU OC0addr 00000026
-EQU SPMRaddr 00000028
-EQU INT_VECTORS_SIZE 0000002a
-EQU ramstart 00000060
-EQU CELLSIZE 00000002
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_EEPROM 00000000
-SET WANT_CPU 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_SPI 00000000
-SET WANT_USART 00000000
-SET WANT_TWI 00000000
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_JTAG 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_WATCHDOG 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 0000011e
-EQU INTVECTORS 00000015
-EQU EEPE 00000001
-EQU EEMPE 00000002
-CSEG mcu_info 00000029
-CSEG mcu_ramsize 00000029
-CSEG mcu_eepromsize 0000002a
-CSEG mcu_maxdp 0000002b
-CSEG mcu_numints 0000002c
-CSEG mcu_name 0000002d
-SET codestart 00000032
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 0000045f
-SET stackstart 0000040f
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000001e
-SET VE_HEAD 00001fee
-SET VE_ENVHEAD 000005b7
-SET AMFORTH_RO_SEG 00001c01
-EQU F_CPU 007a1200
-EQU TIMER_INT 00000008
-EQU BAUDRATE_LOW 00000029
-EQU BAUDRATE_HIGH 00000040
-EQU USART_C 00000040
-EQU USART_B 0000002a
-EQU USART_A 0000002b
-EQU USART_DATA 0000002c
-EQU bm_USARTC_en 00000080
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000060
-DSEG usart_rx_in 00000070
-DSEG usart_rx_out 00000071
-CSEG VE_TO_RXBUF 00000032
-CSEG XT_TO_RXBUF 00000038
-CSEG PFA_rx_tobuf 00000039
-CSEG DO_NEXT 00001c05
-CSEG VE_ISR_RX 00000049
-CSEG XT_ISR_RX 0000004e
-CSEG DO_COLON 00001c01
-CSEG usart_rx_isr 0000004f
-CSEG XT_DOLITERAL 00001c3d
-CSEG XT_CFETCH 00001c98
-CSEG XT_DUP 00001cb1
-CSEG XT_EQUAL 00001fe0
-CSEG XT_DOCONDBRANCH 00001c36
-CSEG usart_rx_isr1 00000059
-CSEG XT_COLD 00000ae0
-CSEG XT_EXIT 00001c20
-CSEG XT_USART_INIT_RX_BUFFER 0000005b
-CSEG PFA_USART_INIT_RX_BUFFER 0000005c
-CSEG XT_INTSTORE 00000213
-CSEG XT_ZERO 00001d54
-CSEG XT_FILL 0000025d
-CSEG VE_RX_BUFFER 00000068
-CSEG XT_RX_BUFFER 0000006d
-CSEG PFA_RX_BUFFER 0000006e
-CSEG XT_RXQ_BUFFER 00000088
-CSEG XT_PLUS 00001d9d
-CSEG XT_SWAP 00001cc4
-CSEG XT_1PLUS 00001e2f
-CSEG XT_AND 00001e13
-CSEG XT_CSTORE 00001c8d
-CSEG VE_RXQ_BUFFER 00000082
-CSEG PFA_RXQ_BUFFER 00000089
-CSEG XT_PAUSE 00000ad8
-CSEG XT_NOTEQUAL 00001d13
-SET XT_RX 0000006d
-SET XT_RXQ 00000088
-SET XT_USART_INIT_RX 0000005b
-CSEG VE_TX_POLL 00000092
-CSEG XT_TX_POLL 00000098
-CSEG PFA_TX_POLL 00000099
-CSEG XT_TXQ_POLL 000000a6
-CSEG VE_TXQ_POLL 000000a0
-CSEG PFA_TXQ_POLL 000000a7
-SET XT_TX 00000098
-SET XT_TXQ 000000a6
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000af
-CSEG XT_UBRR 000000b3
-CSEG PFA_DOVALUE1 00001c6f
-CSEG PFA_UBRR 000000b4
-ESEG EE_UBRRVAL 00000082
-CSEG XT_EDEFERFETCH 00000c3b
-CSEG XT_EDEFERSTORE 00000c45
-CSEG VE_USART 000000b7
-CSEG XT_USART 000000bc
-CSEG PFA_USART 000000bd
-CSEG XT_BYTESWAP 00001ef9
-EQU OW_PORT 00000018
-EQU OW_BIT 00000004
-SET OW_DDR 00000017
-SET OW_PIN 00000016
-CSEG VE_OW_RESET 000000d2
-CSEG XT_OW_RESET 000000d8
-CSEG PFA_OW_RESET 000000d9
-SET cycles 00000000
-SET loop_cycles 000007d0
-CSEG VE_OW_SLOT 000000f6
-CSEG XT_OW_SLOT 000000fc
-CSEG PFA_OW_SLOT 000000fd
-CSEG PFA_OW_SLOT0 0000010a
-SET AMFORTH_NRWW_SIZE 000007fc
-SET corepc 0000011e
-CSEG PFA_COLD 00000ae1
-ESEG intvec 00000000
-DSEG intcnt 00000072
-CSEG VE_MPLUS 00000135
-CSEG XT_MPLUS 00000138
-CSEG PFA_MPLUS 00000139
-CSEG XT_S2D 00000dee
-CSEG XT_DPLUS 0000019c
-CSEG VE_UDSTAR 0000013c
-CSEG XT_UDSTAR 00000140
-CSEG PFA_UDSTAR 00000141
-CSEG XT_TO_R 00001cff
-CSEG XT_UMSTAR 00001de0
-CSEG XT_DROP 00001cd9
-CSEG XT_R_FROM 00001cf6
-CSEG XT_ROT 00001ce1
-CSEG VE_UMAX 0000014b
-CSEG XT_UMAX 0000014f
-CSEG PFA_UMAX 00000150
-CSEG XT_2DUP 000005eb
-CSEG XT_ULESS 00001d5c
-CSEG UMAX1 00000155
-CSEG VE_UMIN 00000157
-CSEG XT_UMIN 0000015b
-CSEG PFA_UMIN 0000015c
-CSEG XT_UGREATER 00001d67
-CSEG UMIN1 00000161
-CSEG XT_IMMEDIATEQ 00000163
-CSEG PFA_IMMEDIATEQ 00000164
-CSEG XT_ZEROEQUAL 00001d1a
-CSEG IMMEDIATEQ1 0000016c
-CSEG XT_ONE 00001fe7
-CSEG XT_TRUE 00001d4b
-CSEG VE_NAME2FLAGS 0000016e
-CSEG XT_NAME2FLAGS 00000175
-CSEG PFA_NAME2FLAGS 00000176
-CSEG XT_FETCHI 00001fcb
-CSEG VE_D2STAR 0000017b
-CSEG XT_D2STAR 0000017f
-CSEG PFA_D2STAR 00000180
-CSEG VE_D2SLASH 0000018a
-CSEG XT_D2SLASH 0000018e
-CSEG PFA_D2SLASH 0000018f
-CSEG VE_DPLUS 00000199
-CSEG PFA_DPLUS 0000019d
-CSEG VE_DMINUS 000001ab
-CSEG XT_DMINUS 000001ae
-CSEG PFA_DMINUS 000001af
-CSEG VE_DINVERT 000001be
-CSEG XT_DINVERT 000001c4
-CSEG PFA_DINVERT 000001c5
-CSEG VE_UDOT 000001cf
-CSEG XT_UDOT 000001d2
-CSEG PFA_UDOT 000001d3
-CSEG XT_UDDOT 000007b1
-CSEG VE_UDOTR 000001d6
-CSEG XT_UDOTR 000001da
-CSEG PFA_UDOTR 000001db
-CSEG XT_UDDOTR 000007ba
-CSEG VE_SHOWWORDLIST 000001df
-CSEG XT_SHOWWORDLIST 000001e8
-CSEG PFA_SHOWWORDLIST 000001e9
-CSEG XT_SHOWWORD 000001ee
-CSEG XT_TRAVERSEWORDLIST 00000cde
-CSEG PFA_SHOWWORD 000001ef
-CSEG XT_NAME2STRING 00000cf9
-CSEG XT_ITYPE 00000827
-CSEG XT_SPACE 00000869
-CSEG VE_WORDS 000001f4
-CSEG XT_WORDS 000001f9
-CSEG PFA_WORDS 000001fa
-ESEG CFG_ORDERLISTLEN 00000040
-CSEG XT_FETCHE 00001f5f
-CSEG VE_INTON 000001ff
-CSEG XT_INTON 00000203
-CSEG PFA_INTON 00000204
-CSEG VE_INTOFF 00000207
-CSEG XT_INTOFF 0000020b
-CSEG PFA_INTOFF 0000020c
-CSEG VE_INTSTORE 0000020f
-CSEG PFA_INTSTORE 00000214
-CSEG XT_STOREE 00001f3b
-CSEG VE_INTFETCH 00000219
-CSEG XT_INTFETCH 0000021d
-CSEG PFA_INTFETCH 0000021e
-CSEG VE_INTTRAP 00000223
-CSEG XT_INTTRAP 00000229
-CSEG PFA_INTTRAP 0000022a
-CSEG XT_ISREXEC 0000022f
-CSEG PFA_ISREXEC 00000230
-CSEG XT_EXECUTE 00001c2a
-CSEG XT_ISREND 00000234
-CSEG PFA_ISREND 00000235
-CSEG PFA_ISREND1 00000238
-CSEG VE_PICK 00000239
-CSEG XT_PICK 0000023d
-CSEG PFA_PICK 0000023e
-CSEG XT_CELLS 000005dd
-CSEG XT_SP_FETCH 00001e8d
-CSEG XT_FETCH 00001c79
-CSEG VE_DOTSTRING 00000244
-CSEG XT_DOTSTRING 00000247
-CSEG PFA_DOTSTRING 00000248
-CSEG XT_SQUOTE 0000024f
-CSEG XT_COMPILE 000002a3
-CSEG VE_SQUOTE 0000024c
-CSEG PFA_SQUOTE 00000250
-CSEG XT_PARSE 00000a0e
-CSEG XT_STATE 000005d0
-CSEG PFA_SQUOTE1 00000258
-CSEG XT_SLITERAL 000002cf
-CSEG VE_FILL 00000259
-CSEG PFA_FILL 0000025e
-CSEG XT_QDUP 00001cb9
-CSEG PFA_FILL2 0000026a
-CSEG XT_BOUNDS 00000de5
-CSEG XT_DODO 00001e9b
-CSEG PFA_FILL1 00000265
-CSEG XT_I 00001eac
-CSEG XT_DOLOOP 00001ec9
-CSEG VE_NEWEST 0000026c
-CSEG XT_NEWEST 00000271
-CSEG PFA_DOVARIABLE 00001c48
-CSEG PFA_NEWEST 00000272
-DSEG ram_newest 00000087
-CSEG VE_LATEST 00000273
-CSEG XT_LATEST 00000278
-CSEG PFA_LATEST 00000279
-DSEG ram_latest 0000008b
-CSEG VE_DOCREATE 0000027a
-CSEG XT_DOCREATE 00000280
-CSEG PFA_DOCREATE 00000281
-CSEG XT_PARSENAME 00000a3b
-CSEG XT_WLSCOPE 000003d7
-CSEG XT_CELLPLUS 000005e3
-CSEG XT_STORE 00001c81
-CSEG XT_HEADER 000003bc
-CSEG VE_BACKSLASH 0000028b
-CSEG XT_BACKSLASH 0000028e
-CSEG PFA_BACKSLASH 0000028f
-CSEG XT_SOURCE 00000a22
-CSEG XT_NIP 00001cf0
-CSEG XT_TO_IN 00000604
-CSEG VE_LPAREN 00000294
-CSEG XT_LPAREN 00000297
-CSEG PFA_LPAREN 00000298
-CSEG XT_2DROP 000005f4
-CSEG VE_COMPILE 0000029d
-CSEG PFA_COMPILE 000002a4
-CSEG XT_ICELLPLUS 00000c32
-CSEG XT_COMMA 000002ae
-CSEG VE_COMMA 000002ab
-CSEG PFA_COMMA 000002af
-CSEG XT_DP 00000634
-CSEG XT_STOREI 00001f73
-CSEG XT_DOTO 00000c20
-CSEG PFA_DP 00000635
-CSEG VE_BRACKETTICK 000002b6
-CSEG XT_BRACKETTICK 000002ba
-CSEG PFA_BRACKETTICK 000002bb
-CSEG XT_TICK 00000891
-CSEG XT_LITERAL 000002c4
-CSEG VE_LITERAL 000002be
-CSEG PFA_LITERAL 000002c5
-CSEG VE_SLITERAL 000002c9
-CSEG PFA_SLITERAL 000002d0
-CSEG XT_DOSLITERAL 000007f4
-CSEG XT_SCOMMA 00000802
-CSEG XT_GMARK 000002d4
-CSEG PFA_GMARK 000002d5
-CSEG XT_GRESOLVE 000002d9
-CSEG PFA_GRESOLVE 000002da
-CSEG XT_QSTACK 00000bde
-CSEG XT_LMARK 000002df
-CSEG PFA_LMARK 000002e0
-CSEG XT_LRESOLVE 000002e2
-CSEG PFA_LRESOLVE 000002e3
-CSEG VE_AHEAD 000002e6
-CSEG XT_AHEAD 000002eb
-CSEG PFA_AHEAD 000002ec
-CSEG XT_DOBRANCH 00001c2f
-CSEG VE_IF 000002f0
-CSEG XT_IF 000002f3
-CSEG PFA_IF 000002f4
-CSEG VE_ELSE 000002f8
-CSEG XT_ELSE 000002fc
-CSEG PFA_ELSE 000002fd
-CSEG VE_THEN 00000303
-CSEG XT_THEN 00000307
-CSEG PFA_THEN 00000308
-CSEG VE_BEGIN 0000030a
-CSEG XT_BEGIN 0000030f
-CSEG PFA_BEGIN 00000310
-CSEG VE_WHILE 00000312
-CSEG XT_WHILE 00000317
-CSEG PFA_WHILE 00000318
-CSEG VE_REPEAT 0000031b
-CSEG XT_REPEAT 00000320
-CSEG PFA_REPEAT 00000321
-CSEG XT_AGAIN 00000334
-CSEG VE_UNTIL 00000324
-CSEG XT_UNTIL 00000329
-CSEG PFA_UNTIL 0000032a
-CSEG VE_AGAIN 0000032f
-CSEG PFA_AGAIN 00000335
-CSEG VE_DO 00000339
-CSEG XT_DO 0000033c
-CSEG PFA_DO 0000033d
-CSEG XT_TO_L 00000397
-CSEG VE_LOOP 00000343
-CSEG XT_LOOP 00000347
-CSEG PFA_LOOP 00000348
-CSEG XT_ENDLOOP 0000037e
-CSEG VE_PLUSLOOP 0000034c
-CSEG XT_PLUSLOOP 00000351
-CSEG PFA_PLUSLOOP 00000352
-CSEG XT_DOPLUSLOOP 00001eba
-CSEG VE_LEAVE 00000356
-CSEG XT_LEAVE 0000035b
-CSEG PFA_LEAVE 0000035c
-CSEG XT_UNLOOP 00001ed4
-CSEG VE_QDO 00000361
-CSEG XT_QDO 00000365
-CSEG PFA_QDO 00000366
-CSEG XT_QDOCHECK 0000036d
-CSEG PFA_QDOCHECK 0000036e
-CSEG PFA_QDOCHECK1 00000375
-CSEG XT_INVERT 00001dfd
-CSEG VE_ENDLOOP 00000378
-CSEG PFA_ENDLOOP 0000037f
-CSEG LOOP1 00000380
-CSEG XT_L_FROM 0000038b
-CSEG LOOP2 00000387
-CSEG VE_L_FROM 00000388
-CSEG PFA_L_FROM 0000038c
-CSEG XT_LP 000003aa
-CSEG XT_PLUSSTORE 00001e65
-CSEG VE_TO_L 00000394
-CSEG PFA_TO_L 00000398
-CSEG XT_TWO 00001fec
-CSEG VE_LP0 0000039f
-CSEG XT_LP0 000003a3
-CSEG PFA_LP0 000003a4
-ESEG CFG_LP0 00000036
-CSEG VE_LP 000003a7
-CSEG PFA_LP 000003ab
-DSEG ram_lp 0000008d
-CSEG VE_CREATE 000003ac
-CSEG XT_CREATE 000003b1
-CSEG PFA_CREATE 000003b2
-CSEG XT_REVEAL 000003e0
-CSEG PFA_DOCONSTANT 00001c52
-CSEG VE_HEADER 000003b7
-CSEG PFA_HEADER 000003bd
-CSEG XT_GREATERZERO 00001d28
-CSEG PFA_HEADER1 000003ce
-CSEG XT_OR 00001e1c
-CSEG XT_DOSCOMMA 00000806
-CSEG XT_THROW 000008c8
-CSEG VE_WLSCOPE 000003d1
-CSEG PFA_DODEFER1 00000c9a
-CSEG PFA_WLSCOPE 000003d8
-ESEG CFG_WLSCOPE 00000032
-CSEG VE_REVEAL 000003db
-CSEG PFA_REVEAL 000003e1
-CSEG REVEAL1 000003eb
-CSEG VE_DOES 000003ec
-CSEG XT_DOES 000003f1
-CSEG PFA_DOES 000003f2
-CSEG XT_DODOES 00000404
-CSEG DO_DODOES 000003f9
-CSEG PFA_DODOES 00000405
-CSEG XT_NFA2CFA 00000d05
-CSEG VE_COLON 0000040d
-CSEG XT_COLON 00000410
-CSEG PFA_COLON 00000411
-CSEG XT_COLONNONAME 0000041b
-CSEG VE_COLONNONAME 00000415
-CSEG PFA_COLONNONAME 0000041c
-CSEG XT_RBRACKET 00000430
-CSEG VE_SEMICOLON 00000424
-CSEG XT_SEMICOLON 00000427
-CSEG PFA_SEMICOLON 00000428
-CSEG XT_LBRACKET 00000438
-CSEG VE_RBRACKET 0000042d
-CSEG PFA_RBRACKET 00000431
-CSEG VE_LBRACKET 00000435
-CSEG PFA_LBRACKET 00000439
-CSEG VE_VARIABLE 0000043d
-CSEG XT_VARIABLE 00000443
-CSEG PFA_VARIABLE 00000444
-CSEG XT_HERE 00000645
-CSEG XT_CONSTANT 0000044f
-CSEG XT_ALLOT 0000064e
-CSEG VE_CONSTANT 00000449
-CSEG PFA_CONSTANT 00000450
-CSEG VE_USER 00000456
-CSEG XT_USER 0000045a
-CSEG PFA_USER 0000045b
-CSEG PFA_DOUSER 00001c58
-CSEG VE_RECURSE 00000461
-CSEG XT_RECURSE 00000467
-CSEG PFA_RECURSE 00000468
-CSEG VE_IMMEDIATE 0000046c
-CSEG XT_IMMEDIATE 00000473
-CSEG PFA_IMMEDIATE 00000474
-CSEG XT_GET_CURRENT 00000515
-CSEG VE_BRACKETCHAR 0000047e
-CSEG XT_BRACKETCHAR 00000483
-CSEG PFA_BRACKETCHAR 00000484
-CSEG XT_CHAR 00000971
-CSEG VE_ABORTQUOTE 00000489
-CSEG XT_ABORTQUOTE 0000048e
-CSEG PFA_ABORTQUOTE 0000048f
-CSEG XT_QABORT 000004a0
-CSEG VE_ABORT 00000493
-CSEG XT_ABORT 00000498
-CSEG PFA_ABORT 00000499
-CSEG VE_QABORT 0000049b
-CSEG PFA_QABORT 000004a1
-CSEG QABO1 000004a6
-CSEG VE_GET_STACK 000004a8
-CSEG XT_GET_STACK 000004af
-CSEG PFA_N_FETCH_E2 000004c6
-CSEG PFA_N_FETCH_E1 000004bc
-CSEG XT_1MINUS 00001e35
-CSEG XT_OVER 00001ccf
-CSEG VE_SET_STACK 000004c9
-CSEG XT_SET_STACK 000004d0
-CSEG PFA_SET_STACK 000004d1
-CSEG XT_ZEROLESS 00001d21
-CSEG PFA_SET_STACK0 000004d8
-CSEG PFA_SET_STACK2 000004e5
-CSEG PFA_SET_STACK1 000004e0
-CSEG XT_TUCK 000005fc
-CSEG VE_MAPSTACK 000004e7
-CSEG XT_MAPSTACK 000004ee
-CSEG PFA_MAPSTACK 000004ef
-CSEG PFA_MAPSTACK3 0000050a
-CSEG PFA_MAPSTACK1 000004f9
-CSEG XT_R_FETCH 00001d08
-CSEG PFA_MAPSTACK2 00000506
-CSEG VE_GET_CURRENT 0000050d
-CSEG PFA_GET_CURRENT 00000516
-ESEG CFG_CURRENT 0000003c
-CSEG VE_GET_ORDER 0000051a
-CSEG XT_GET_ORDER 00000521
-CSEG PFA_GET_ORDER 00000522
-CSEG VE_CFG_ORDER 00000526
-CSEG XT_CFG_ORDER 0000052d
-CSEG PFA_CFG_ORDER 0000052e
-CSEG VE_COMPARE 0000052f
-CSEG XT_COMPARE 00000535
-CSEG PFA_COMPARE 00000536
-CSEG PFA_COMPARE_LOOP 00000542
-CSEG PFA_COMPARE_NOTEQUAL 00000550
-CSEG PFA_COMPARE_ENDREACHED2 0000054b
-CSEG PFA_COMPARE_ENDREACHED 0000054c
-CSEG PFA_COMPARE_CHECKLASTCHAR 00000550
-CSEG PFA_COMPARE_DONE 00000552
-CSEG VE_NFA2LFA 00000557
-CSEG XT_NFA2LFA 0000055d
-CSEG PFA_NFA2LFA 0000055e
-CSEG XT_2SLASH 00001e04
-CSEG VE_ENVIRONMENT 00000563
-CSEG XT_ENVIRONMENT 0000056b
-CSEG PFA_ENVIRONMENT 0000056c
-ESEG CFG_ENVIRONMENT 0000003a
-CSEG VE_ENVWORDLISTS 0000056d
-CSEG XT_ENVWORDLISTS 00000574
-CSEG PFA_ENVWORDLISTS 00000575
-CSEG VE_ENVSLASHPAD 00000578
-CSEG XT_ENVSLASHPAD 0000057c
-CSEG PFA_ENVSLASHPAD 0000057d
-CSEG XT_PAD 0000060a
-CSEG XT_MINUS 00001d93
-CSEG VE_ENVSLASHHOLD 00000581
-CSEG XT_ENVSLASHHOLD 00000586
-CSEG PFA_ENVSLASHHOLD 00000587
-CSEG VE_ENV_FORTHNAME 0000058b
-CSEG XT_ENV_FORTHNAME 00000592
-CSEG PFA_EN_FORTHNAME 00000593
-CSEG VE_ENV_FORTHVERSION 0000059a
-CSEG XT_ENV_FORTHVERSION 000005a0
-CSEG PFA_EN_FORTHVERSION 000005a1
-CSEG VE_ENV_CPU 000005a4
-CSEG XT_ENV_CPU 000005a8
-CSEG PFA_EN_CPU 000005a9
-CSEG XT_ICOUNT 00000853
-CSEG VE_ENV_MCUINFO 000005ad
-CSEG XT_ENV_MCUINFO 000005b3
-CSEG PFA_EN_MCUINFO 000005b4
-CSEG VE_ENVUSERSIZE 000005b7
-CSEG XT_ENVUSERSIZE 000005bc
-CSEG PFA_ENVUSERSIZE 000005bd
-CSEG VE_F_CPU 000005c0
-CSEG XT_F_CPU 000005c5
-CSEG PFA_F_CPU 000005c6
-CSEG VE_STATE 000005cb
-CSEG PFA_STATE 000005d1
-DSEG ram_state 0000008f
-CSEG VE_BASE 000005d2
-CSEG XT_BASE 000005d6
-CSEG PFA_BASE 000005d7
-CSEG VE_CELLS 000005d8
-CSEG PFA_2STAR 00001e0c
-CSEG VE_CELLPLUS 000005de
-CSEG PFA_CELLPLUS 000005e4
-CSEG VE_2DUP 000005e7
-CSEG PFA_2DUP 000005ec
-CSEG VE_2DROP 000005ef
-CSEG PFA_2DROP 000005f5
-CSEG VE_TUCK 000005f8
-CSEG PFA_TUCK 000005fd
-CSEG VE_TO_IN 00000600
-CSEG PFA_TO_IN 00000605
-CSEG VE_PAD 00000606
-CSEG PFA_PAD 0000060b
-CSEG VE_EMIT 00000610
-CSEG XT_EMIT 00000614
-CSEG PFA_EMIT 00000615
-CSEG XT_UDEFERFETCH 00000c63
-CSEG XT_UDEFERSTORE 00000c6f
-CSEG VE_EMITQ 00000618
-CSEG XT_EMITQ 0000061d
-CSEG PFA_EMITQ 0000061e
-CSEG VE_KEY 00000621
-CSEG XT_KEY 00000625
-CSEG PFA_KEY 00000626
-CSEG VE_KEYQ 00000629
-CSEG XT_KEYQ 0000062d
-CSEG PFA_KEYQ 0000062e
-CSEG VE_DP 00000631
-ESEG CFG_DP 0000002c
-CSEG VE_EHERE 00000638
-CSEG XT_EHERE 0000063d
-CSEG PFA_EHERE 0000063e
-ESEG EE_EHERE 00000030
-CSEG VE_HERE 00000641
-CSEG PFA_HERE 00000646
-ESEG EE_HERE 0000002e
-CSEG VE_ALLOT 00000649
-CSEG PFA_ALLOT 0000064f
-CSEG VE_BIN 00000654
-CSEG XT_BIN 00000658
-CSEG PFA_BIN 00000659
-CSEG VE_DECIMAL 0000065d
-CSEG XT_DECIMAL 00000663
-CSEG PFA_DECIMAL 00000664
-CSEG VE_HEX 00000669
-CSEG XT_HEX 0000066d
-CSEG PFA_HEX 0000066e
-CSEG VE_BL 00000673
-CSEG XT_BL 00000676
-CSEG PFA_BL 00000677
-CSEG VE_TURNKEY 00000678
-CSEG XT_TURNKEY 0000067e
-CSEG PFA_TURNKEY 0000067f
-ESEG CFG_TURNKEY 00000038
-CSEG VE_SLASHMOD 00000682
-CSEG XT_SLASHMOD 00000686
-CSEG PFA_SLASHMOD 00000687
-CSEG PFA_SLASHMOD_1 00000692
-CSEG PFA_SLASHMOD_2 00000698
-CSEG PFA_SLASHMOD_3 0000069b
-CSEG PFA_SLASHMOD_5 000006a6
-CSEG PFA_SLASHMOD_4 000006a5
-CSEG PFA_SLASHMODmod_done 000006b1
-CSEG PFA_SLASHMOD_6 000006af
-CSEG VE_USLASHMOD 000006b6
-CSEG XT_USLASHMOD 000006bb
-CSEG PFA_USLASHMOD 000006bc
-CSEG XT_UMSLASHMOD 00001dc2
-CSEG VE_NEGATE 000006c1
-CSEG XT_NEGATE 000006c6
-CSEG PFA_NEGATE 000006c7
-CSEG VE_SLASH 000006ca
-CSEG XT_SLASH 000006cd
-CSEG PFA_SLASH 000006ce
-CSEG VE_MOD 000006d1
-CSEG XT_MOD 000006d5
-CSEG PFA_MOD 000006d6
-CSEG VE_ABS 000006d9
-CSEG XT_ABS 000006dd
-CSEG PFA_ABS 000006de
-CSEG XT_QNEGATE 00001e3e
-CSEG VE_MIN 000006e1
-CSEG XT_MIN 000006e5
-CSEG PFA_MIN 000006e6
-CSEG XT_GREATER 00001d78
-CSEG PFA_MIN1 000006eb
-CSEG VE_MAX 000006ed
-CSEG XT_MAX 000006f1
-CSEG PFA_MAX 000006f2
-CSEG XT_LESS 00001d6e
-CSEG PFA_MAX1 000006f7
-CSEG VE_WITHIN 000006f9
-CSEG XT_WITHIN 000006fe
-CSEG PFA_WITHIN 000006ff
-CSEG VE_TOUPPER 00000706
-CSEG XT_TOUPPER 0000070c
-CSEG PFA_TOUPPER 0000070d
-CSEG PFA_TOUPPER0 00000718
-CSEG VE_TOLOWER 00000719
-CSEG XT_TOLOWER 0000071f
-CSEG PFA_TOLOWER 00000720
-CSEG PFA_TOLOWER0 0000072b
-CSEG VE_HLD 0000072c
-CSEG XT_HLD 00000730
-CSEG PFA_HLD 00000731
-DSEG ram_hld 00000091
-CSEG VE_HOLD 00000732
-CSEG XT_HOLD 00000736
-CSEG PFA_HOLD 00000737
-CSEG VE_L_SHARP 00000742
-CSEG XT_L_SHARP 00000745
-CSEG PFA_L_SHARP 00000746
-CSEG VE_SHARP 0000074a
-CSEG XT_SHARP 0000074d
-CSEG PFA_SHARP 0000074e
-CSEG XT_UDSLASHMOD 000007ca
-CSEG PFA_SHARP1 0000075b
-CSEG VE_SHARP_S 00000760
-CSEG XT_SHARP_S 00000763
-CSEG PFA_SHARP_S 00000764
-CSEG NUMS1 00000764
-CSEG VE_SHARP_G 0000076b
-CSEG XT_SHARP_G 0000076e
-CSEG PFA_SHARP_G 0000076f
-CSEG VE_SIGN 00000776
-CSEG XT_SIGN 0000077a
-CSEG PFA_SIGN 0000077b
-CSEG PFA_SIGN1 00000781
-CSEG VE_DDOTR 00000782
-CSEG XT_DDOTR 00000786
-CSEG PFA_DDOTR 00000787
-CSEG XT_DABS 00000d5b
-CSEG XT_SPACES 00000872
-CSEG XT_TYPE 00000882
-CSEG VE_DOTR 00000795
-CSEG XT_DOTR 00000798
-CSEG PFA_DOTR 00000799
-CSEG VE_DDOT 0000079e
-CSEG XT_DDOT 000007a1
-CSEG PFA_DDOT 000007a2
-CSEG VE_DOT 000007a6
-CSEG XT_DOT 000007a9
-CSEG PFA_DOT 000007aa
-CSEG VE_UDDOT 000007ad
-CSEG PFA_UDDOT 000007b2
-CSEG VE_UDDOTR 000007b6
-CSEG PFA_UDDOTR 000007bb
-CSEG VE_UDSLASHMOD 000007c5
-CSEG PFA_UDSLASHMOD 000007cb
-CSEG VE_DIGITQ 000007d5
-CSEG XT_DIGITQ 000007da
-CSEG PFA_DIGITQ 000007db
-CSEG PFA_DOSLITERAL 000007f5
-CSEG VE_SCOMMA 000007ff
-CSEG PFA_SCOMMA 00000803
-CSEG PFA_DOSCOMMA 00000807
-CSEG XT_2STAR 00001e0b
-CSEG PFA_SCOMMA2 00000819
-CSEG PFA_SCOMMA1 00000813
-CSEG PFA_SCOMMA3 00000820
-CSEG VE_ITYPE 00000822
-CSEG PFA_ITYPE 00000828
-CSEG PFA_ITYPE2 0000083b
-CSEG PFA_ITYPE1 00000833
-CSEG XT_LOWEMIT 00000848
-CSEG XT_HIEMIT 00000844
-CSEG PFA_ITYPE3 00000842
-CSEG PFA_HIEMIT 00000845
-CSEG PFA_LOWEMIT 00000849
-CSEG VE_ICOUNT 0000084e
-CSEG PFA_ICOUNT 00000854
-CSEG VE_CR 00000859
-CSEG XT_CR 0000085c
-CSEG PFA_CR 0000085d
-CSEG VE_SPACE 00000864
-CSEG PFA_SPACE 0000086a
-CSEG VE_SPACES 0000086d
-CSEG PFA_SPACES 00000873
-CSEG SPCS1 00000875
-CSEG SPCS2 0000087c
-CSEG VE_TYPE 0000087e
-CSEG PFA_TYPE 00000883
-CSEG PFA_TYPE2 0000088d
-CSEG PFA_TYPE1 00000888
-CSEG VE_TICK 0000088e
-CSEG PFA_TICK 00000892
-CSEG XT_FORTHRECOGNIZER 00000b60
-CSEG XT_RECOGNIZE 00000b36
-CSEG XT_DT_NULL 00000bd1
-CSEG XT_NOOP 00000c06
-CSEG PFA_TICK1 000008a3
-CSEG VE_HANDLER 000008a5
-CSEG XT_HANDLER 000008ab
-CSEG PFA_HANDLER 000008ac
-CSEG VE_CATCH 000008ad
-CSEG XT_CATCH 000008b2
-CSEG PFA_CATCH 000008b3
-CSEG XT_RP_FETCH 00001e76
-CSEG VE_THROW 000008c3
-CSEG PFA_THROW 000008c9
-CSEG PFA_THROW1 000008cf
-CSEG XT_RP_STORE 00001e80
-CSEG XT_SP_STORE 00001e96
-CSEG VE_CSKIP 000008dc
-CSEG XT_CSKIP 000008e1
-CSEG PFA_CSKIP 000008e2
-CSEG PFA_CSKIP1 000008e3
-CSEG PFA_CSKIP2 000008f0
-CSEG XT_SLASHSTRING 00000a2c
-CSEG VE_CSCAN 000008f3
-CSEG XT_CSCAN 000008f8
-CSEG PFA_CSCAN 000008f9
-CSEG PFA_CSCAN1 000008fb
-CSEG PFA_CSCAN2 0000090d
-CSEG VE_ACCEPT 00000913
-CSEG XT_ACCEPT 00000918
-CSEG PFA_ACCEPT 00000919
-CSEG ACC1 0000091d
-CSEG XT_CRLFQ 00000959
-CSEG ACC5 0000094b
-CSEG ACC3 0000093b
-CSEG ACC6 00000939
-CSEG XT_BS 00000951
-CSEG ACC4 00000949
-CSEG PFA_ACCEPT6 00000942
-CSEG VE_REFILL 00000964
-CSEG XT_REFILL 00000969
-CSEG PFA_REFILL 0000096a
-CSEG VE_CHAR 0000096d
-CSEG PFA_CHAR 00000972
-CSEG VE_NUMBER 00000976
-CSEG XT_NUMBER 0000097b
-CSEG PFA_NUMBER 0000097c
-CSEG XT_QSIGN 000009bf
-CSEG XT_SET_BASE 000009d2
-CSEG PFA_NUMBER0 00000992
-CSEG XT_2TO_R 00001f1e
-CSEG XT_2R_FROM 00001f2d
-CSEG XT_TO_NUMBER 000009f0
-CSEG PFA_NUMBER1 000009b4
-CSEG PFA_NUMBER2 000009ab
-CSEG PFA_NUMBER6 000009ac
-CSEG PFA_NUMBER3 000009a8
-CSEG XT_DNEGATE 00000d68
-CSEG PFA_NUMBER5 000009ba
-CSEG PFA_NUMBER4 000009b9
-CSEG PFA_QSIGN 000009c0
-CSEG PFA_NUMBERSIGN_DONE 000009cb
-CSEG XT_BASES 000009cd
-CSEG PFA_SET_BASE 000009d3
-CSEG SET_BASE1 000009e8
-CSEG SET_BASE2 000009e9
-CSEG VE_TO_NUMBER 000009ea
-CSEG TONUM1 000009f1
-CSEG TONUM3 00000a08
-CSEG TONUM2 000009fc
-CSEG XT_2SWAP 00000d8c
-CSEG VE_PARSE 00000a09
-CSEG PFA_PARSE 00000a0f
-CSEG VE_SOURCE 00000a1d
-CSEG PFA_SOURCE 00000a23
-CSEG VE_SLASHSTRING 00000a26
-CSEG PFA_SLASHSTRING 00000a2d
-CSEG VE_PARSENAME 00000a34
-CSEG PFA_PARSENAME 00000a3c
-CSEG XT_SKIPSCANCHAR 00000a3f
-CSEG PFA_SKIPSCANCHAR 00000a40
-CSEG VE_FINDXT 00000a51
-CSEG XT_FINDXT 00000a57
-CSEG PFA_FINDXT 00000a58
-CSEG XT_FINDXTA 00000a63
-CSEG PFA_FINDXT1 00000a62
-CSEG PFA_FINDXTA 00000a64
-CSEG XT_SEARCH_WORDLIST 00000cac
-CSEG PFA_FINDXTA1 00000a70
-CSEG VE_QUIT 00000a71
-CSEG XT_QUIT 00000a75
-CSEG PFA_QUIT 00000a76
-CSEG XT_SP0 00000b10
-CSEG XT_RP0 00000b1d
-CSEG PFA_QUIT2 00000a7e
-CSEG PFA_QUIT4 00000a84
-CSEG XT_PROMPTREADY 00000ab4
-CSEG PFA_QUIT3 00000a96
-CSEG XT_INTERPRET 00000b6b
-CSEG PFA_QUIT5 00000a94
-CSEG XT_PROMPTERROR 00000acf
-CSEG XT_PROMPTOK 00000aa4
-CSEG XT_DEFAULT_PROMPTOK 00000a99
-CSEG PFA_DEFAULT_PROMPTOK 00000a9a
-CSEG VE_PROMPTOK 00000aa0
-CSEG PFA_PROMPTOK 00000aa5
-CSEG XT_DEFAULT_PROMPTREADY 00000aa8
-CSEG PFA_DEFAULT_PROMPTREADY 00000aa9
-CSEG VE_PROMPTREADY 00000aaf
-CSEG PFA_PROMPTREADY 00000ab5
-CSEG XT_DEFAULT_PROMPTERROR 00000ab8
-CSEG PFA_DEFAULT_PROMPTERROR 00000ab9
-CSEG VE_PROMPTERROR 00000aca
-CSEG PFA_PROMPTERROR 00000ad0
-CSEG VE_PAUSE 00000ad3
-CSEG PFA_PAUSE 00000ad9
-DSEG ram_pause 00000093
-CSEG XT_RDEFERFETCH 00000c4f
-CSEG XT_RDEFERSTORE 00000c59
-CSEG VE_COLD 00000adc
-CSEG clearloop 00000ae8
-DSEG ram_user1 00000095
-CSEG PFA_WARM 00000b03
-CSEG VE_WARM 00000afe
-CSEG XT_WARM 00000b02
-CSEG XT_INIT_RAM 00000dd7
-CSEG XT_DEFERSTORE 00000c7a
-CSEG VE_SP0 00000b0c
-CSEG PFA_SP0 00000b11
-CSEG VE_SP 00000b14
-CSEG XT_SP 00000b17
-CSEG PFA_SP 00000b18
-CSEG VE_RP0 00000b19
-CSEG PFA_RP0 00000b1e
-CSEG XT_DORP0 00000b21
-CSEG PFA_DORP0 00000b22
-CSEG VE_DEPTH 00000b23
-CSEG XT_DEPTH 00000b28
-CSEG PFA_DEPTH 00000b29
-CSEG VE_RECOGNIZE 00000b2f
-CSEG PFA_RECOGNIZE 00000b37
-CSEG XT_RECOGNIZE_A 00000b41
-CSEG PFA_RECOGNIZE1 00000b40
-CSEG PFA_RECOGNIZE_A 00000b42
-CSEG PFA_RECOGNIZE_A1 00000b52
-CSEG VE_FORTHRECOGNIZER 00000b56
-CSEG PFA_FORTHRECOGNIZER 00000b61
-ESEG CFG_FORTHRECOGNIZER 00000034
-CSEG VE_INTERPRET 00000b64
-CSEG PFA_INTERPRET 00000b6c
-CSEG PFA_INTERPRET2 00000b7c
-CSEG PFA_INTERPRET1 00000b77
-CSEG VE_DT_NUM 00000b7e
-CSEG XT_DT_NUM 00000b83
-CSEG PFA_DT_NUM 00000b84
-CSEG VE_DT_DNUM 00000b87
-CSEG XT_DT_DNUM 00000b8d
-CSEG PFA_DT_DNUM 00000b8e
-CSEG XT_2LITERAL 00001fd8
-CSEG VE_REC_NUM 00000b91
-CSEG XT_REC_NUM 00000b97
-CSEG PFA_REC_NUM 00000b98
-CSEG PFA_REC_NONUMBER 00000ba3
-CSEG PFA_REC_INTNUM2 00000ba1
-CSEG VE_REC_FIND 00000ba5
-CSEG XT_REC_FIND 00000bab
-CSEG PFA_REC_FIND 00000bac
-CSEG PFA_REC_WORD_FOUND 00000bb4
-CSEG XT_DT_XT 00000bbb
-CSEG VE_DT_XT 00000bb6
-CSEG PFA_DT_XT 00000bbc
-CSEG XT_R_WORD_INTERPRET 00000bbf
-CSEG XT_R_WORD_COMPILE 00000bc3
-CSEG PFA_R_WORD_INTERPRET 00000bc0
-CSEG PFA_R_WORD_COMPILE 00000bc4
-CSEG PFA_R_WORD_COMPILE1 00000bc9
-CSEG VE_DT_NULL 00000bcb
-CSEG PFA_DT_NULL 00000bd2
-CSEG XT_FAIL 00000bd5
-CSEG PFA_FAIL 00000bd6
-CSEG VE_QSTACK 00000bd9
-CSEG PFA_QSTACK 00000bdf
-CSEG PFA_QSTACK1 00000be6
-CSEG VE_DOT_VER 00000be7
-CSEG XT_DOT_VER 00000beb
-CSEG PFA_DOT_VER 00000bec
-CSEG VE_NOOP 00000c02
-CSEG PFA_NOOP 00000c07
-CSEG VE_UNUSED 00000c08
-CSEG XT_UNUSED 00000c0d
-CSEG PFA_UNUSED 00000c0e
-CSEG VE_TO 00000c12
-CSEG XT_TO 00000c15
-CSEG PFA_TO 00000c16
-CSEG XT_TO_BODY 00000df7
-CSEG PFA_TO1 00000c26
-CSEG PFA_DOTO 00000c21
-CSEG VE_ICELLPLUS 00000c2c
-CSEG PFA_ICELLPLUS 00000c33
-CSEG VE_EDEFERFETCH 00000c35
-CSEG PFA_EDEFERFETCH 00000c3c
-CSEG VE_EDEFERSTORE 00000c3f
-CSEG PFA_EDEFERSTORE 00000c46
-CSEG VE_RDEFERFETCH 00000c49
-CSEG PFA_RDEFERFETCH 00000c50
-CSEG VE_RDEFERSTORE 00000c53
-CSEG PFA_RDEFERSTORE 00000c5a
-CSEG VE_UDEFERFETCH 00000c5d
-CSEG PFA_UDEFERFETCH 00000c64
-CSEG XT_UP_FETCH 00001f02
-CSEG VE_UDEFERSTORE 00000c69
-CSEG PFA_UDEFERSTORE 00000c70
-CSEG VE_DEFERSTORE 00000c75
-CSEG PFA_DEFERSTORE 00000c7b
-CSEG VE_DEFERFETCH 00000c82
-CSEG XT_DEFERFETCH 00000c87
-CSEG PFA_DEFERFETCH 00000c88
-CSEG VE_DODEFER 00000c8e
-CSEG XT_DODEFER 00000c94
-CSEG PFA_DODEFER 00000c95
-CSEG VE_SEARCH_WORDLIST 00000ca2
-CSEG PFA_SEARCH_WORDLIST 00000cad
-CSEG XT_ISWORD 00000cc1
-CSEG PFA_SEARCH_WORDLIST1 00000cbb
-CSEG PFA_ISWORD 00000cc2
-CSEG XT_ICOMPARE 00000d0f
-CSEG PFA_ISWORD3 00000ccf
-CSEG VE_TRAVERSEWORDLIST 00000cd3
-CSEG PFA_TRAVERSEWORDLIST 00000cdf
-CSEG PFA_TRAVERSEWORDLIST1 00000ce0
-CSEG PFA_TRAVERSEWORDLIST2 00000cef
-CSEG VE_NAME2STRING 00000cf1
-CSEG PFA_NAME2STRING 00000cfa
-CSEG VE_NFA2CFA 00000cff
-CSEG PFA_NFA2CFA 00000d06
-CSEG VE_ICOMPARE 00000d09
-CSEG PFA_ICOMPARE 00000d10
-CSEG PFA_ICOMPARE_SAMELEN 00000d1a
-CSEG PFA_ICOMPARE_DONE 00000d3d
-CSEG PFA_ICOMPARE_LOOP 00000d20
-CSEG PFA_ICOMPARE_LASTCELL 00000d2e
-CSEG PFA_ICOMPARE_NEXTLOOP 00000d35
-CSEG VE_STAR 00000d40
-CSEG XT_STAR 00000d43
-CSEG PFA_STAR 00000d44
-CSEG XT_MSTAR 00001da6
-CSEG VE_J 00000d47
-CSEG XT_J 00000d4a
-CSEG PFA_J 00000d4b
-CSEG VE_DABS 00000d57
-CSEG PFA_DABS 00000d5c
-CSEG PFA_DABS1 00000d61
-CSEG VE_DNEGATE 00000d62
-CSEG PFA_DNEGATE 00000d69
-CSEG VE_CMOVE 00000d6e
-CSEG XT_CMOVE 00000d73
-CSEG PFA_CMOVE 00000d74
-CSEG PFA_CMOVE1 00000d81
-CSEG PFA_CMOVE2 00000d7d
-CSEG VE_2SWAP 00000d87
-CSEG PFA_2SWAP 00000d8d
-CSEG VE_REFILLTIB 00000d92
-CSEG XT_REFILLTIB 00000d99
-CSEG PFA_REFILLTIB 00000d9a
-CSEG XT_TIB 00000db5
-CSEG XT_NUMBERTIB 00000dbb
-CSEG VE_SOURCETIB 00000da5
-CSEG XT_SOURCETIB 00000dac
-CSEG PFA_SOURCETIB 00000dad
-CSEG VE_TIB 00000db1
-CSEG PFA_TIB 00000db6
-DSEG ram_tib 000000c1
-CSEG VE_NUMBERTIB 00000db7
-CSEG PFA_NUMBERTIB 00000dbc
-DSEG ram_sharptib 0000011b
-CSEG VE_EE2RAM 00000dbd
-CSEG XT_EE2RAM 00000dc2
-CSEG PFA_EE2RAM 00000dc3
-CSEG PFA_EE2RAM_1 00000dc5
-CSEG PFA_EE2RAM_2 00000dcf
-CSEG VE_INIT_RAM 00000dd1
-CSEG PFA_INI_RAM 00000dd8
-ESEG EE_INITUSER 00000060
-CSEG VE_BOUNDS 00000de0
-CSEG PFA_BOUNDS 00000de6
-CSEG VE_S2D 00000dea
-CSEG PFA_S2D 00000def
-CSEG VE_TO_BODY 00000df2
-CSEG PFA_1PLUS 00001e30
-CSEG VE_DOTS 00000df8
-CSEG XT_DOTS 00000dfb
-CSEG PFA_DOTS 00000dfc
-CSEG PFA_DOTS2 00000e0a
-CSEG PFA_DOTS1 00000e05
-CSEG VE_SPIRW 00000e0b
-CSEG XT_SPIRW 00000e10
-CSEG PFA_SPIRW 00000e11
-CSEG do_spirw 00000e15
-CSEG do_spirw1 00000e16
-CSEG VE_N_SPIR 00000e1e
-CSEG XT_N_SPIR 00000e23
-CSEG PFA_N_SPIR 00000e24
-CSEG PFA_N_SPIR_LOOP 00000e29
-CSEG PFA_N_SPIR_LOOP1 00000e2a
-CSEG VE_N_SPIW 00000e35
-CSEG XT_N_SPIW 00000e3a
-CSEG PFA_N_SPIW 00000e3b
-CSEG PFA_N_SPIW_LOOP 00000e40
-CSEG PFA_N_SPIW_LOOP1 00000e42
-CSEG VE_APPLTURNKEY 00000e4c
-CSEG XT_APPLTURNKEY 00000e54
-CSEG PFA_APPLTURNKEY 00000e55
-CSEG VE_SET_CURRENT 00000e66
-CSEG XT_SET_CURRENT 00000e6e
-CSEG PFA_SET_CURRENT 00000e6f
-CSEG VE_WORDLIST 00000e73
-CSEG XT_WORDLIST 00000e79
-CSEG PFA_WORDLIST 00000e7a
-CSEG VE_FORTHWORDLIST 00000e83
-CSEG XT_FORTHWORDLIST 00000e8c
-CSEG PFA_FORTHWORDLIST 00000e8d
-ESEG CFG_FORTHWORDLIST 0000003e
-CSEG VE_SET_ORDER 00000e8e
-CSEG XT_SET_ORDER 00000e95
-CSEG PFA_SET_ORDER 00000e96
-CSEG VE_SET_RECOGNIZERS 00000e9a
-CSEG XT_SET_RECOGNIZERS 00000ea4
-CSEG PFA_SET_RECOGNIZERS 00000ea5
-ESEG CFG_RECOGNIZERLISTLEN 00000052
-CSEG VE_GET_RECOGNIZERS 00000ea9
-CSEG XT_GET_RECOGNIZERS 00000eb3
-CSEG PFA_GET_RECOGNIZERS 00000eb4
-CSEG VE_CODE 00000eb8
-CSEG XT_CODE 00000ebc
-CSEG PFA_CODE 00000ebd
-CSEG VE_ENDCODE 00000ec3
-CSEG XT_ENDCODE 00000ec9
-CSEG PFA_ENDCODE 00000eca
-CSEG VE_MARKER 00000ecf
-CSEG XT_MARKER 00000ed5
-CSEG PFA_MARKER 00000ed6
-ESEG EE_MARKER 0000005e
-CSEG VE_POSTPONE 00000ed9
-CSEG XT_POSTPONE 00000edf
-CSEG PFA_POSTPONE 00000ee0
-CSEG VE_2R_FETCH 00000eee
-CSEG XT_2R_FETCH 00000ef2
-CSEG PFA_2R_FETCH 00000ef3
-SET DPSTART 00000f02
-CSEG DO_INTERRUPT 00001c14
-CSEG DO_EXECUTE 00001c0d
-CSEG VE_EXIT 00001c1c
-CSEG PFA_EXIT 00001c21
-CSEG VE_EXECUTE 00001c24
-CSEG PFA_EXECUTE 00001c2b
-CSEG PFA_DOBRANCH 00001c30
-CSEG PFA_DOCONDBRANCH 00001c37
-CSEG PFA_DOLITERAL 00001c3e
-CSEG XT_DOVARIABLE 00001c47
-CSEG XT_DOCONSTANT 00001c51
-CSEG XT_DOUSER 00001c57
-CSEG VE_DOVALUE 00001c63
-CSEG XT_DOVALUE 00001c69
-CSEG PFA_DOVALUE 00001c6a
-CSEG VE_FETCH 00001c76
-CSEG PFA_FETCH 00001c7a
-CSEG PFA_FETCHRAM 00001c7a
-CSEG VE_STORE 00001c7e
-CSEG PFA_STORE 00001c82
-CSEG PFA_STORERAM 00001c82
-CSEG VE_CSTORE 00001c8a
-CSEG PFA_CSTORE 00001c8e
-CSEG VE_CFETCH 00001c95
-CSEG PFA_CFETCH 00001c99
-CSEG VE_FETCHU 00001c9d
-CSEG XT_FETCHU 00001ca0
-CSEG PFA_FETCHU 00001ca1
-CSEG VE_STOREU 00001ca5
-CSEG XT_STOREU 00001ca8
-CSEG PFA_STOREU 00001ca9
-CSEG VE_DUP 00001cad
-CSEG PFA_DUP 00001cb2
-CSEG VE_QDUP 00001cb5
-CSEG PFA_QDUP 00001cba
-CSEG PFA_QDUP1 00001cbf
-CSEG VE_SWAP 00001cc0
-CSEG PFA_SWAP 00001cc5
-CSEG VE_OVER 00001ccb
-CSEG PFA_OVER 00001cd0
-CSEG VE_DROP 00001cd5
-CSEG PFA_DROP 00001cda
-CSEG VE_ROT 00001cdd
-CSEG PFA_ROT 00001ce2
-CSEG VE_NIP 00001cec
-CSEG PFA_NIP 00001cf1
-CSEG VE_R_FROM 00001cf3
-CSEG PFA_R_FROM 00001cf7
-CSEG VE_TO_R 00001cfc
-CSEG PFA_TO_R 00001d00
-CSEG VE_R_FETCH 00001d05
-CSEG PFA_R_FETCH 00001d09
-CSEG VE_NOTEQUAL 00001d10
-CSEG PFA_NOTEQUAL 00001d14
-CSEG VE_ZEROEQUAL 00001d17
-CSEG PFA_ZEROEQUAL 00001d1b
-CSEG PFA_ZERO1 00001d57
-CSEG PFA_TRUE1 00001d4e
-CSEG VE_ZEROLESS 00001d1e
-CSEG PFA_ZEROLESS 00001d22
-CSEG VE_GREATERZERO 00001d25
-CSEG PFA_GREATERZERO 00001d29
-CSEG VE_DGREATERZERO 00001d2e
-CSEG XT_DGREATERZERO 00001d32
-CSEG PFA_DGREATERZERO 00001d33
-CSEG VE_DXT_ZEROLESS 00001d3c
-CSEG XT_DXT_ZEROLESS 00001d40
-CSEG PFA_DXT_ZEROLESS 00001d41
-CSEG VE_TRUE 00001d47
-CSEG PFA_TRUE 00001d4c
-CSEG VE_ZERO 00001d51
-CSEG PFA_ZERO 00001d55
-CSEG VE_ULESS 00001d59
-CSEG PFA_ULESS 00001d5d
-CSEG VE_UGREATER 00001d64
-CSEG PFA_UGREATER 00001d68
-CSEG VE_LESS 00001d6b
-CSEG PFA_LESS 00001d6f
-CSEG PFA_LESSDONE 00001d73
-CSEG VE_GREATER 00001d75
-CSEG PFA_GREATER 00001d79
-CSEG PFA_GREATERDONE 00001d7d
-CSEG VE_LOG2 00001d80
-CSEG XT_LOG2 00001d84
-CSEG PFA_LOG2 00001d85
-CSEG PFA_LOG2_1 00001d88
-CSEG PFA_LOG2_2 00001d8e
-CSEG VE_MINUS 00001d90
-CSEG PFA_MINUS 00001d94
-CSEG VE_PLUS 00001d9a
-CSEG PFA_PLUS 00001d9e
-CSEG VE_MSTAR 00001da3
-CSEG PFA_MSTAR 00001da7
-CSEG VE_UMSLASHMOD 00001dbd
-CSEG PFA_UMSLASHMOD 00001dc3
-CSEG PFA_UMSLASHMODmod 00001dc8
-CSEG PFA_UMSLASHMODmod_loop 00001dc9
-CSEG PFA_UMSLASHMODmod_loop_control 00001dd6
-CSEG PFA_UMSLASHMODmod_subtract 00001dd3
-CSEG PFA_UMSLASHMODmod_done 00001dd8
-CSEG VE_UMSTAR 00001ddc
-CSEG PFA_UMSTAR 00001de1
-CSEG VE_INVERT 00001df8
-CSEG PFA_INVERT 00001dfe
-CSEG VE_2SLASH 00001e01
-CSEG PFA_2SLASH 00001e05
-CSEG VE_2STAR 00001e08
-CSEG VE_AND 00001e0f
-CSEG PFA_AND 00001e14
-CSEG VE_OR 00001e19
-CSEG PFA_OR 00001e1d
-CSEG VE_XOR 00001e22
-CSEG XT_XOR 00001e26
-CSEG PFA_XOR 00001e27
-CSEG VE_1PLUS 00001e2c
-CSEG VE_1MINUS 00001e32
-CSEG PFA_1MINUS 00001e36
-CSEG VE_QNEGATE 00001e38
-CSEG PFA_QNEGATE 00001e3f
-CSEG QNEG1 00001e43
-CSEG VE_LSHIFT 00001e44
-CSEG XT_LSHIFT 00001e49
-CSEG PFA_LSHIFT 00001e4a
-CSEG PFA_LSHIFT1 00001e4d
-CSEG PFA_LSHIFT2 00001e52
-CSEG VE_RSHIFT 00001e53
-CSEG XT_RSHIFT 00001e58
-CSEG PFA_RSHIFT 00001e59
-CSEG PFA_RSHIFT1 00001e5c
-CSEG PFA_RSHIFT2 00001e61
-CSEG VE_PLUSSTORE 00001e62
-CSEG PFA_PLUSSTORE 00001e66
-CSEG VE_RP_FETCH 00001e72
-CSEG PFA_RP_FETCH 00001e77
-CSEG VE_RP_STORE 00001e7c
-CSEG PFA_RP_STORE 00001e81
-CSEG VE_SP_FETCH 00001e89
-CSEG PFA_SP_FETCH 00001e8e
-CSEG VE_SP_STORE 00001e92
-CSEG PFA_SP_STORE 00001e97
-CSEG PFA_DODO 00001e9c
-CSEG PFA_DODO1 00001e9e
-CSEG VE_I 00001ea9
-CSEG PFA_I 00001ead
-CSEG PFA_DOPLUSLOOP 00001ebb
-CSEG PFA_DOPLUSLOOP_LEAVE 00001ec5
-CSEG PFA_DOPLUSLOOP_NEXT 00001ec2
-CSEG PFA_DOLOOP 00001eca
-CSEG VE_UNLOOP 00001ecf
-CSEG PFA_UNLOOP 00001ed5
-CSEG VE_CMOVE_G 00001eda
-CSEG XT_CMOVE_G 00001edf
-CSEG PFA_CMOVE_G 00001ee0
-CSEG PFA_CMOVE_G1 00001ef1
-CSEG PFA_CMOVE_G2 00001eed
-CSEG VE_BYTESWAP 00001ef6
-CSEG PFA_BYTESWAP 00001efa
-CSEG VE_UP_FETCH 00001efe
-CSEG PFA_UP_FETCH 00001f03
-CSEG VE_UP_STORE 00001f07
-CSEG XT_UP_STORE 00001f0b
-CSEG PFA_UP_STORE 00001f0c
-CSEG VE_1MS 00001f10
-CSEG XT_1MS 00001f14
-CSEG PFA_1MS 00001f15
-CSEG VE_2TO_R 00001f1a
-CSEG PFA_2TO_R 00001f1f
-CSEG VE_2R_FROM 00001f29
-CSEG PFA_2R_FROM 00001f2e
-CSEG VE_STOREE 00001f38
-CSEG PFA_STOREE 00001f3c
-CSEG PFA_STOREE0 00001f3c
-CSEG PFA_FETCHE2 00001f6a
-CSEG PFA_STOREE3 00001f46
-CSEG PFA_STOREE1 00001f51
-CSEG PFA_STOREE4 00001f4d
-CSEG PFA_STOREE2 00001f53
-CSEG VE_FETCHE 00001f5c
-CSEG PFA_FETCHE 00001f60
-CSEG PFA_FETCHE1 00001f60
-CSEG VE_STOREI 00001f70
-CSEG PFA_STOREI 00001f74
-ESEG EE_STOREI 0000005c
-CSEG VE_DO_STOREI_NRWW 00001f77
-CSEG XT_DO_STOREI 00001f7e
-CSEG PFA_DO_STOREI_NRWW 00001f7f
-CSEG DO_STOREI_atmega 00001f93
-CSEG pageload 00001fa4
-CSEG DO_STOREI_writepage 00001f9d
-CSEG dospm 00001fbd
-EQU pagemask ffffffc0
-CSEG pageload_loop 00001faa
-CSEG pageload_newdata 00001fb5
-CSEG pageload_cont 00001fb7
-CSEG pageload_done 00001fbc
-CSEG dospm_wait_ee 00001fbd
-CSEG dospm_wait_spm 00001fbf
-CSEG VE_FETCHI 00001fc8
-CSEG PFA_FETCHI 00001fcc
-CSEG VE_2LITERAL 00001fd2
-CSEG PFA_2LITERAL 00001fd9
-CSEG VE_EQUAL 00001fdd
-CSEG PFA_EQUAL 00001fe1
-CSEG VE_ONE 00001fe4
-CSEG PFA_ONE 00001fe8
-CSEG VE_TWO 00001fe9
-CSEG PFA_TWO 00001fed
-CSEG VE_MINUSONE 00001fee
-CSEG XT_MINUSONE 00001ff1
-CSEG PFA_MINUSONE 00001ff2
-SET flashlast 00001ff3
-DSEG HERESTART 0000011d
-ESEG EHERESTART 00000084
-ESEG CFG_ORDERLIST 00000042
-ESEG CFG_RECOGNIZERLIST 00000054
-EQU UBRR_VAL 0000000c
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/eval-pollin/p16-8.xml b/amforth-6.5/appl/eval-pollin/p16-8.xml
deleted file mode 100644
index eba211c..0000000
--- a/amforth-6.5/appl/eval-pollin/p16-8.xml
+++ /dev/null
@@ -1,36 +0,0 @@
-<project name="pollins-16-8" basedir="." default="Help">
-
- <target name="p16-8.asm">
- <copy tofile="p16-8.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="8000000"/>
- <filter token="USART" value=""/>
- </filterset>
- </copy>
- </target>
-
- <target name="p16-8.hex" depends="p16-8.asm" description="Hexfiles for p16-8">
- <avrasm2 projectname="p16-8" mcu="atmega16"/>
- <delete file="p16-8.asm"/>
-
- </target>
-
- <target name="p16-8" depends="p16-8.hex" description="Atmega16 @ 8 MHz">
- <echo>Uploading Hexfiles for p16-8</echo>
- <avrdude
- type="stk200"
- mcu="atmega16"
- flashfile="p16-8.hex"
- eepromfile="p16-8.eep.hex" />
- </target>
- <target name="p16-8.fuses" description="Set fuses for P16-8">
- <echo>Writing fuses</echo>
- <avrdude-2fuses
- type="stk200"
- mcu="atmega16"
- hfuse="0x99"
- lfuse="0xff"
- />
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/p32-16.xml b/amforth-6.5/appl/eval-pollin/p32-16.xml
deleted file mode 100644
index 59444f3..0000000
--- a/amforth-6.5/appl/eval-pollin/p32-16.xml
+++ /dev/null
@@ -1,45 +0,0 @@
-<project name="pollins-32-16" basedir="." default="Help">
-
- <target name="p32-16.asm">
- <copy tofile="p32-16.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="16000000"/>
- <filter token="USART" value=""/>
- </filterset>
- </copy>
- </target>
-
- <target name="p32-16.hex" depends="p32-16.asm" description="Hexfiles for p32-16">
- <avrasm2 projectname="p32-16" mcu="atmega32"/>
- <delete file="p32-16.asm"/>
- </target>
-
- <target name="p32-16" depends="p32-16.hex" description="Atmega32 @ 16 MHz">
- <echo>Uploading Hexfiles for p32-16</echo>
- <avrdude
- type="stk200"
- mcu="atmega32"
- flashfile="p32-16.hex"
- eepromfile="p32-16.eep.hex"
- />
- </target>
- <target name="p32-16.back" description="Atmega32 @ 16 MHz">
- <echo>Download Hexfiles from p32-16</echo>
- <avrdude-back
- type="stk200"
- mcu="atmega32"
- flashfile="p32-16.hex"
- eepromfile="p32-16.eep.hex"
- />
- </target>
- <target name="p32-16.fuses" description="Set fuses for P32-16">
- <echo>Writing fuses</echo>
- <avrdude-2fuses
- type="stk200"
- mcu="atmega32"
- hfuse="0x99"
- lfuse="0xff"
- />
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/p32-8.eep.hex b/amforth-6.5/appl/eval-pollin/p32-8.eep.hex
deleted file mode 100644
index a59fb2c..0000000
--- a/amforth-6.5/appl/eval-pollin/p32-8.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10002A00FFFF1B0B1D018400C309520010086D0A53
-:0A003A00F4023E00ED3F01003E001D
-:06005200020065065106E4
-:10005C007E3B5E00000000005F080F080F080000E8
-:10006C000A009800A6006D0088006C02000059027E
-:08007C00C93CE83CD83C0C0033
-:00000001FF
diff --git a/amforth-6.5/appl/eval-pollin/p32-8.hex b/amforth-6.5/appl/eval-pollin/p32-8.hex
deleted file mode 100644
index 91b0f2b..0000000
--- a/amforth-6.5/appl/eval-pollin/p32-8.hex
+++ /dev/null
@@ -1,628 +0,0 @@
-:020000020000FC
-:020004001BD10E
-:0200080019D10C
-:02000C0017D10A
-:0200100015D108
-:0200140013D106
-:0200180011D104
-:02001C000FD102
-:020020000DD100
-:020024000BD1FE
-:0200280009D1FC
-:02002C0007D1FA
-:0200300005D1F8
-:0200340003D1F6
-:0200380001D1F4
-:02003C00FFD0F3
-:02004000FDD0F1
-:02004400FBD0EF
-:02004800F9D0ED
-:02004C00F7D0EB
-:10005000F5D00008000400701500080041546D65DB
-:100060006761333207FF3E72782D627566000000CB
-:100070003900082F10917000E0E6F0E0E10FF31D69
-:10008000008313951F7010937000899199910C94BF
-:10009000053806FF6973722D7278320001383D38D9
-:1000A0002C009838B1383D380300DF3F363859000E
-:1000B000383D3800203801383D384E003D381A00B0
-:1000C000A53C3D3860003D3816005439983E203834
-:1000D00006FF72782D62756649000138880036384F
-:1000E0006E003D3871009838B1383D3860009D3958
-:1000F0009838C4382F3A3D380F00133A3D38710014
-:100100008D38203807FF72783F2D627566006800D1
-:100110000138303D3D38710098383D3870009838CE
-:100120001339203807FF74782D706F6C6C008200D3
-:100130000138A600363899003D382C008D3820381B
-:1001400008FF74783F2D706F6C6C92000138303D61
-:100150003D382B0098383D382000133A203804FFF2
-:1001600075627272A0006F388200A03DAA3D06FF42
-:100170002B7573617274AF0001383D3898003D38BB
-:100180002A008D383D3806003D38C0008D38B30058
-:10019000B138F93A3D3840008D383D3829008D3866
-:1001A0005B00203808FF31772E7265736574B700E5
-:1001B000D9009A938A93BC9AC498E0ECF3E0319703
-:1001C000F1F71FB7F894C49ABC98E0E8F0E03197D3
-:1001D000F1F786B384FF9FEF1FBFBC98C498E0E49B
-:1001E000F3E03197F1F7892F0C94053807FF317749
-:1001F0002E736C6F7400D200FD00C498BC9A1FB7B8
-:10020000F894ECE0F0E03197F1F78894879510F4DA
-:10021000C49ABC98E2E1F0E03197F1F706B304FD2F
-:100220008068E6E6F0E03197F1F7C49ABC98E4E024
-:0C023000F0E03197F1F71FBF0C94053887
-:040000000C94393DE6
-:10023C000A920FB60A920F900F900A94B02CFF936B
-:10024C00EF93E2E7F0E00694E00DF31D00800394D9
-:10025C000082EF91FF9109900FBE0990089502FF63
-:10026C006D2BF6000138C73F153C203803FF756431
-:10027C002A0035010138B138FF38E039D938C43893
-:10028C00F638E039E1389D39203804FF756D617816
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-:1002AC00203804FF756D696E4B010138C93E673902
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-:1002CC00133A1A3936386C01E63F20384B3920384E
-:1002DC000AFF6E616D653E666C616773570101388C
-:1002EC00CB3B3D3800FF133A203803FF7665720094
-:1002FC006E010138CF02F803AE3FBD3E7938DD0206
-:10030C00413FC73F16031E033D382E00070334033D
-:10031C003F032E04BD3E8138AE3FE502F803203882
-:10032C0004FF6E6F6F707B010138203806FF756E0D
-:10033C0075736564960101388D3A233F93392038E3
-:10034C000200746F9C0101383D04D03FB73E7938F0
-:10035C003638BA015107B4015C0720380138F63839
-:10036C00B138C601FF38CB3BB138C601C601CB3B17
-:10037C002A38203807FF692D63656C6C2B00A601A9
-:10038C0001382F3A203808FF69636F6D7061726510
-:10039C00C0010138FF38CF38F63813393638DA0156
-:1003AC00D23ED9384B392038C43854391B0836382A
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-:1003CC0000015C393638EE01C4383D38FF00133A71
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-:1003FC005439203801FF2A00C9010138A639D938EF
-:10040C00203801FF6A0000020138763A3D380700B7
-:10041C009D397938763A3D3809009D3979389D39BE
-:10042C00203804FF6461627307020138B138213946
-:10043C00363821022802203807FF646E6567617424
-:10044C006500170201383B3CE63F5439153C203817
-:10045C0005FF636D6F76650022023402BF93AF9384
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-:1004BC007B0281385439E23E81384B3920380AFFAF
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-:10056C002F706164AA0201388D3AE83E9339203825
-:10057C0005FF2F686F6C6400B5020138E83E233F1D
-:10058C00933920380AFF666F7274682D6E616D6541
-:10059C00BE020138C5030700616D666F7274680096
-:1005AC00203807FF76657273696F6E00C8020138D8
-:1005BC003D384100203803FF63707500D7020138C5
-:1005CC003D382D002404203808FF6D63752D696EAD
-:1005DC00666FE10201383D382900203805FF2F7580
-:1005EC0073657200EA0201383D382C00203803FF95
-:1005FC00686C6400A0024838E30004FF686F6C6408
-:10060C00FD0201380103B1387938353AB138FF3879
-:10061C00C4388138F6388D38203802FF3C23030368
-:10062C000138E83E01038138203801FF2300130311
-:10063C000138BD3E79389B03E1383D380900CF388D
-:10064C006E3936382C033D3807009D393D38300063
-:10065C009D390703203802FF23731B0301381E0347
-:10066C00C93E1C3A1A3936383503203802FF233E6E
-:10067C0031030138D23E01037938E83ECF38933943
-:10068C00203804FF7369676E3C0301382139363812
-:10069C0052033D382D000703203803FF642E7200EF
-:1006AC0047030138FF38DA3E1B0216033403E138E6
-:1006BC004B033F03F638CF389339B73F2E0420381D
-:1006CC0002FF2E7253030138FF38C73FF638570329
-:1006DC00203802FF642E6603013854395703AE3FAD
-:1006EC00203801FF2E006F030138C73F72032038FA
-:1006FC0003FF75642E007703013854398B03AE3F2A
-:10070C00203804FF75642E727E030138FF381603FF
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diff --git a/amforth-6.5/appl/eval-pollin/p32-8.lst b/amforth-6.5/appl/eval-pollin/p32-8.lst
deleted file mode 100644
index 0922f73..0000000
--- a/amforth-6.5/appl/eval-pollin/p32-8.lst
+++ /dev/null
@@ -1,10420 +0,0 @@
-
-AVRASM ver. 2.1.52 p32-8.asm Sun Apr 30 20:10:14 2017
-
-p32-8.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega32\device.asm'
-../../avr8/devices/atmega32\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m32def.inc'
-p32-8.asm(14): Including file '../../avr8\drivers/usart.asm'
-../../avr8\drivers/usart.asm(30): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-p32-8.asm(19): Including file '../../avr8\drivers/1wire.asm'
-p32-8.asm(21): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(11): Including file '../../avr8\dict/appl_4k.inc'
-../../avr8\dict/appl_4k.inc(1): Including file '../../common\words/ver.asm'
-../../avr8\dict/appl_4k.inc(4): Including file '../../common\words/noop.asm'
-../../avr8\dict/appl_4k.inc(5): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/appl_4k.inc(6): Including file '../../common\words/to.asm'
-../../avr8\dict/appl_4k.inc(7): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/appl_4k.inc(8): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/appl_4k.inc(9): Including file '../../common\words/star.asm'
-../../avr8\dict/appl_4k.inc(10): Including file '../../avr8\words/j.asm'
-../../avr8\dict/appl_4k.inc(11): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/appl_4k.inc(12): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/appl_4k.inc(13): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/appl_4k.inc(14): Including file '../../common\words/2swap.asm'
-../../avr8\dict/appl_4k.inc(15): Including file '../../common\words/tib.asm'
-../../avr8\dict/appl_4k.inc(16): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/appl_4k.inc(20): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/appl_4k.inc(21): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/appl_4k.inc(22): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/appl_4k.inc(23): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/appl_4k.inc(24): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/appl_4k.inc(25): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/appl_4k.inc(26): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/appl_4k.inc(27): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/appl_4k.inc(28): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/appl_4k.inc(30): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/appl_4k.inc(31): Including file '../../common\words/hold.asm'
-../../avr8\dict/appl_4k.inc(32): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/appl_4k.inc(33): Including file '../../common\words/sharp.asm'
-../../avr8\dict/appl_4k.inc(34): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/appl_4k.inc(35): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/appl_4k.inc(36): Including file '../../common\words/sign.asm'
-../../avr8\dict/appl_4k.inc(37): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/appl_4k.inc(38): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/appl_4k.inc(39): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/appl_4k.inc(40): Including file '../../common\words/dot.asm'
-../../avr8\dict/appl_4k.inc(41): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/appl_4k.inc(42): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/appl_4k.inc(43): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/appl_4k.inc(44): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/appl_4k.inc(46): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/appl_4k.inc(47): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/appl_4k.inc(48): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/appl_4k.inc(49): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/appl_4k.inc(50): Including file '../../common\words/type.asm'
-../../avr8\dict/appl_4k.inc(51): Including file '../../common\words/tick.asm'
-../../avr8\dict/appl_4k.inc(53): Including file '../../common\words/cskip.asm'
-../../avr8\dict/appl_4k.inc(54): Including file '../../common\words/cscan.asm'
-../../avr8\dict/appl_4k.inc(55): Including file '../../common\words/accept.asm'
-../../avr8\dict/appl_4k.inc(56): Including file '../../common\words/refill.asm'
-../../avr8\dict/appl_4k.inc(57): Including file '../../common\words/char.asm'
-../../avr8\dict/appl_4k.inc(58): Including file '../../common\words/number.asm'
-../../avr8\dict/appl_4k.inc(59): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/appl_4k.inc(60): Including file '../../common\words/set-base.asm'
-../../avr8\dict/appl_4k.inc(61): Including file '../../common\words/to-number.asm'
-../../avr8\dict/appl_4k.inc(62): Including file '../../common\words/parse.asm'
-../../avr8\dict/appl_4k.inc(63): Including file '../../common\words/source.asm'
-../../avr8\dict/appl_4k.inc(64): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/appl_4k.inc(65): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/appl_4k.inc(66): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/appl_4k.inc(67): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/appl_4k.inc(68): Including file '../../common\words/depth.asm'
-../../avr8\dict/appl_4k.inc(69): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/appl_4k.inc(70): Including file '../../common\words/recognize.asm'
-../../avr8\dict/appl_4k.inc(71): Including file '../../common\words/interpret.asm'
-../../avr8\dict/appl_4k.inc(72): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/appl_4k.inc(73): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/appl_4k.inc(74): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/appl_4k.inc(75): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/appl_4k.inc(76): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/appl_4k.inc(77): Including file '../../common\words/name2string.asm'
-../../avr8\dict/appl_4k.inc(78): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/appl_4k.inc(79): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/appl_4k.inc(81): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(3): Including file '../../common\words/dot-s.asm'
-dict_appl.inc(4): Including file '../../avr8\words/spirw.asm'
-dict_appl.inc(5): Including file '../../avr8\words/n-spi.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-dict_appl.inc(7): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(8): Including file '../../avr8\words/2r_fetch.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(104): Including file '../../avr8\dict/core_4k.inc'
-../../avr8\dict/core_4k.inc(3): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_4k.inc(4): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_4k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_4k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_4k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_4k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_4k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_4k.inc(10): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_4k.inc(11): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_4k.inc(12): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_4k.inc(13): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_4k.inc(14): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_4k.inc(17): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_4k.inc(18): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_4k.inc(19): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_4k.inc(21): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_4k.inc(22): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_4k.inc(23): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_4k.inc(24): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_4k.inc(26): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_4k.inc(27): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_4k.inc(28): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_4k.inc(31): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_4k.inc(32): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_4k.inc(33): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_4k.inc(34): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_4k.inc(35): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_4k.inc(36): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_4k.inc(37): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_4k.inc(38): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_4k.inc(39): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_4k.inc(41): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_4k.inc(42): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_4k.inc(45): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_4k.inc(46): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_4k.inc(47): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_4k.inc(48): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_4k.inc(50): Including file '../../common\words/min.asm'
-../../avr8\dict/core_4k.inc(51): Including file '../../common\words/max.asm'
-../../avr8\dict/core_4k.inc(52): Including file '../../common\words/within.asm'
-../../avr8\dict/core_4k.inc(54): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_4k.inc(55): Including file '../../common\words/words.asm'
-../../avr8\dict/core_4k.inc(57): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_4k.inc(58): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_4k.inc(59): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_4k.inc(61): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_4k.inc(62): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_4k.inc(63): Including file '../../common\words/base.asm'
-../../avr8\dict/core_4k.inc(65): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_4k.inc(67): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_4k.inc(68): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_4k.inc(69): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_4k.inc(71): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_4k.inc(72): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_4k.inc(73): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_4k.inc(74): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_4k.inc(75): Including file '../../common\words/key.asm'
-../../avr8\dict/core_4k.inc(76): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_4k.inc(78): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_4k.inc(79): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_4k.inc(80): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_4k.inc(81): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_4k.inc(83): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_4k.inc(84): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_4k.inc(85): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_4k.inc(86): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_4k.inc(88): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_4k.inc(89): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_4k.inc(90): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_4k.inc(92): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_4k.inc(93): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_4k.inc(94): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_4k.inc(95): Including file '../../common\words/space.asm'
-../../avr8\dict/core_4k.inc(96): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_4k.inc(97): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_4k.inc(98): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 96
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_EEPROM = 0
- .set WANT_WATCHDOG = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_SPI = 0
- .set WANT_USART = 0
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_CPU = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_TWI = 0
- .equ intvecsize = 2 ; please verify; flash size: 32768 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d11b rcall isr ; External Interrupt Request 0
- .org 4
-000004 d119 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d117 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d115 rcall isr ; Timer/Counter2 Compare Match
- .org 10
-00000a d113 rcall isr ; Timer/Counter2 Overflow
- .org 12
-00000c d111 rcall isr ; Timer/Counter1 Capture Event
- .org 14
-00000e d10f rcall isr ; Timer/Counter1 Compare Match A
- .org 16
-000010 d10d rcall isr ; Timer/Counter1 Compare Match B
- .org 18
-000012 d10b rcall isr ; Timer/Counter1 Overflow
- .org 20
-000014 d109 rcall isr ; Timer/Counter0 Compare Match
- .org 22
-000016 d107 rcall isr ; Timer/Counter0 Overflow
- .org 24
-000018 d105 rcall isr ; Serial Transfer Complete
- .org 26
-00001a d103 rcall isr ; USART, Rx Complete
- .org 28
-00001c d101 rcall isr ; USART Data Register Empty
- .org 30
-00001e d0ff rcall isr ; USART, Tx Complete
- .org 32
-000020 d0fd rcall isr ; ADC Conversion Complete
- .org 34
-000022 d0fb rcall isr ; EEPROM Ready
- .org 36
-000024 d0f9 rcall isr ; Analog Comparator
- .org 38
-000026 d0f7 rcall isr ; 2-wire Serial Interface
- .org 40
-000028 d0f5 rcall isr ; Store Program Memory Ready
- .equ INTVECTORS = 21
- .nooverlap
-
- ; compatability layer (maybe empty)
- .equ SPMCSR = SPMCR
- .equ EEPE = EEWE
- .equ EEMPE = EEMWE
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000029 0800 .dw 2048
- mcu_eepromsize:
-00002a 0400 .dw 1024
- mcu_maxdp:
-00002b 7000 .dw 28672
- mcu_numints:
-00002c 0015 .dw 21
- mcu_name:
-00002d 0008 .dw 8
-00002e 5441
-00002f 656d
-000030 6167
-000031 3233 .db "ATmega32"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set AMFORTH_RO_SEG = NRWW_START_ADDR+1
-
- ; cpu clock in hertz
- .equ F_CPU = 8000000
- .set BAUD_MAXERROR = 30
- .equ TIMER_INT = OVF2addr
-
- .include "drivers/usart.asm"
-
- .equ BAUDRATE_LOW = UBRRL+$20
- .equ BAUDRATE_HIGH = UBRRH+$20
- .equ USART_C = UCSRC+$20
- .equ USART_B = UCSRB+$20
- .equ USART_A = UCSRA+$20
- .equ USART_DATA = UDR+$20
- .equ bm_USARTC_en = 1 << 7
-
- ; some generic constants
- .equ bm_USART_RXRD = 1 << RXC
- .equ bm_USART_TXRD = 1 << UDRE
- .equ bm_ENABLE_TX = 1 << TXEN
- .equ bm_ENABLE_RX = 1 << RXEN
- .equ bm_ENABLE_INT_RX = 1<<RXCIE
- .equ bm_ENABLE_INT_TX = 1<<UDRE
-
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000060 usart_rx_data: .byte usart_rx_size
-000070 usart_rx_in: .byte 1
-000071 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-000032 ff07 .dw $ff07
-000033 723e
-000034 2d78
-000035 7562
-000036 0066 .db ">rx-buf",0
-000037 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000038 0039 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000039 2f08 mov temp0, tosl
-00003a 9110 0070 lds temp1, usart_rx_in
-00003c e6e0 ldi zl, low(usart_rx_data)
-00003d e0f0 ldi zh, high(usart_rx_data)
-00003e 0fe1 add zl, temp1
-00003f 1df3 adc zh, zeroh
-000040 8300 st Z, temp0
-000041 9513 inc temp1
-000042 701f andi temp1,usart_rx_mask
-000043 9310 0070 sts usart_rx_in, temp1
-000045 9189
-000046 9199 loadtos
-000047 940c 3805 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000049 ff06 .dw $ff06
-00004a 7369
-00004b 2d72
-00004c 7872 .db "isr-rx"
-00004d 0032 .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-00004e 3801 .dw DO_COLON
- usart_rx_isr:
-00004f 383d .dw XT_DOLITERAL
-000050 002c .dw usart_data
-000051 3898 .dw XT_CFETCH
-000052 38b1 .dw XT_DUP
-000053 383d .dw XT_DOLITERAL
-000054 0003 .dw 3
-000055 3fdf .dw XT_EQUAL
-000056 3836 .dw XT_DOCONDBRANCH
-000057 0059 .dw usart_rx_isr1
-000058 3d38 .dw XT_COLD
- usart_rx_isr1:
-000059 0038 .dw XT_TO_RXBUF
-00005a 3820 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-00005b 3801 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-00005c 383d
-00005d 004e .dw XT_DOLITERAL, XT_ISR_RX
-00005e 383d
-00005f 001a .dw XT_DOLITERAL, URXCaddr
-000060 3ca5 .dw XT_INTSTORE
-
-000061 383d .dw XT_DOLITERAL
-000062 0060 .dw usart_rx_data
-000063 383d .dw XT_DOLITERAL
-000064 0016 .dw usart_rx_size + 6
-000065 3954 .dw XT_ZERO
-000066 3e98 .dw XT_FILL
-000067 3820 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000068 ff06 .dw $ff06
-000069 7872
-00006a 622d
-00006b 6675 .db "rx-buf"
-00006c 0049 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-00006d 3801 .dw DO_COLON
- PFA_RX_BUFFER:
-00006e 0088 .dw XT_RXQ_BUFFER
-00006f 3836 .dw XT_DOCONDBRANCH
-000070 006e .dw PFA_RX_BUFFER
-000071 383d .dw XT_DOLITERAL
-000072 0071 .dw usart_rx_out
-000073 3898 .dw XT_CFETCH
-000074 38b1 .dw XT_DUP
-000075 383d .dw XT_DOLITERAL
-000076 0060 .dw usart_rx_data
-000077 399d .dw XT_PLUS
-000078 3898 .dw XT_CFETCH
-000079 38c4 .dw XT_SWAP
-00007a 3a2f .dw XT_1PLUS
-00007b 383d .dw XT_DOLITERAL
-00007c 000f .dw usart_rx_mask
-00007d 3a13 .dw XT_AND
-00007e 383d .dw XT_DOLITERAL
-00007f 0071 .dw usart_rx_out
-000080 388d .dw XT_CSTORE
-000081 3820 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-000082 ff07 .dw $ff07
-000083 7872
-000084 2d3f
-000085 7562
-000086 0066 .db "rx?-buf",0
-000087 0068 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-000088 3801 .dw DO_COLON
- PFA_RXQ_BUFFER:
-000089 3d30 .dw XT_PAUSE
-00008a 383d .dw XT_DOLITERAL
-00008b 0071 .dw usart_rx_out
-00008c 3898 .dw XT_CFETCH
-00008d 383d .dw XT_DOLITERAL
-00008e 0070 .dw usart_rx_in
-00008f 3898 .dw XT_CFETCH
-000090 3913 .dw XT_NOTEQUAL
-000091 3820 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-000092 ff07 .dw $ff07
-000093 7874
-000094 702d
-000095 6c6f
-000096 006c .db "tx-poll",0
-000097 0082 .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-000098 3801 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-000099 00a6 .dw XT_TXQ_POLL
-00009a 3836 .dw XT_DOCONDBRANCH
-00009b 0099 .dw PFA_TX_POLL
- ; send to usart
-00009c 383d .dw XT_DOLITERAL
-00009d 002c .dw USART_DATA
-00009e 388d .dw XT_CSTORE
-00009f 3820 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000a0 ff08 .dw $ff08
-0000a1 7874
-0000a2 2d3f
-0000a3 6f70
-0000a4 6c6c .db "tx?-poll"
-0000a5 0092 .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000a6 3801 .dw DO_COLON
- PFA_TXQ_POLL:
-0000a7 3d30 .dw XT_PAUSE
-0000a8 383d .dw XT_DOLITERAL
-0000a9 002b .dw USART_A
-0000aa 3898 .dw XT_CFETCH
-0000ab 383d .dw XT_DOLITERAL
-0000ac 0020 .dw bm_USART_TXRD
-0000ad 3a13 .dw XT_AND
-0000ae 3820 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000af ff04 .dw $ff04
-0000b0 6275
-0000b1 7272 .db "ubrr"
-0000b2 00a0 .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000b3 386f .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000b4 0082 .dw EE_UBRRVAL
-0000b5 3da0 .dw XT_EDEFERFETCH
-0000b6 3daa .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000b7 ff06 .dw $ff06
-0000b8 752b
-0000b9 6173
-0000ba 7472 .db "+usart"
-0000bb 00af .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000bc 3801 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000bd 383d .dw XT_DOLITERAL
-0000be 0098 .dw USART_B_VALUE
-0000bf 383d .dw XT_DOLITERAL
-0000c0 002a .dw USART_B
-0000c1 388d .dw XT_CSTORE
-
-0000c2 383d .dw XT_DOLITERAL
-0000c3 0006 .dw USART_C_VALUE
-0000c4 383d .dw XT_DOLITERAL
-0000c5 00c0 .dw USART_C | bm_USARTC_en
-0000c6 388d .dw XT_CSTORE
-
-0000c7 00b3 .dw XT_UBRR
-0000c8 38b1 .dw XT_DUP
-0000c9 3af9 .dw XT_BYTESWAP
-0000ca 383d .dw XT_DOLITERAL
-0000cb 0040 .dw BAUDRATE_HIGH
-0000cc 388d .dw XT_CSTORE
-0000cd 383d .dw XT_DOLITERAL
-0000ce 0029 .dw BAUDRATE_LOW
-0000cf 388d .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000d0 005b .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000d1 3820 .dw XT_EXIT
-
- ; settings for 1wire interface
- .equ OW_PORT=PORTB
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-0000d2 ff08 .dw $ff08
-0000d3 7731
-0000d4 722e
-0000d5 7365
-0000d6 7465 .db "1w.reset"
-0000d7 00b7 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-0000d8 00d9 .dw PFA_OW_RESET
- PFA_OW_RESET:
-0000d9 939a
-0000da 938a savetos
- ; setup to output
-0000db 9abc sbi OW_DDR, OW_BIT
- ; Pull output low
-0000dc 98c4 cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-0000dd ece0
-0000de e0f3
-0000df 9731
-0000e0 f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-0000e1 b71f in temp1, SREG
-0000e2 94f8 cli
- ; Pull output high
-0000e3 9ac4 sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-0000e4 98bc cbi OW_DDR, OW_BIT
-0000e5 e8e0
-0000e6 e0f0
-0000e7 9731
-0000e8 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-0000e9 b386 in tosl, OW_PIN
-0000ea ff84 sbrs tosl, OW_BIT
-0000eb ef9f ser tosh
- ; End critical timing period, enable interrupts
-0000ec bf1f out SREG, temp1
- ; release bus
-0000ed 98bc cbi OW_DDR, OW_BIT
-0000ee 98c4 cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-0000ef e4e0
-0000f0 e0f3
-0000f1 9731
-0000f2 f7f1 DELAY 416
- ; we now have the result flag in TOS
-0000f3 2f89 mov tosl, tosh
-0000f4 940c 3805 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-0000f6 ff07 .dw $ff07
-0000f7 7731
-0000f8 732e
-0000f9 6f6c
-0000fa 0074 .db "1w.slot",0
-0000fb 00d2 .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-0000fc 00fd .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-0000fd 98c4 cbi OW_PORT, OW_BIT
-0000fe 9abc sbi OW_DDR, OW_BIT
- ; disable interrupts
-0000ff b71f in temp1, SREG
-000100 94f8 cli
-000101 e0ec
-000102 e0f0
-000103 9731
-000104 f7f1 DELAY 6 ; DELAY A
- ; check bit
-000105 9488 clc
-000106 9587 ror tosl
-000107 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000108 9ac4 sbi OW_PORT, OW_BIT
-000109 98bc cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-00010a e1e2
-00010b e0f0
-00010c 9731
-00010d f7f1 DELAY 9 ; wait DELAY E to sample
-00010e b306 in temp0, OW_PIN
-00010f fd04 sbrc temp0, OW_BIT
-000110 6880 ori tosl, $80
-
-000111 e6e6
-000112 e0f0
-000113 9731
-000114 f7f1 DELAY 51 ; DELAY B
-000115 9ac4 sbi OW_PORT, OW_BIT ; release bus
-000116 98bc cbi OW_DDR, OW_BIT
-000117 e0e4
-000118 e0f0
-000119 9731
-00011a f7f1 delay 2
- ; re-enable interrupts
-00011b bf1f out SREG, temp1
-00011c 940c 3805 jmp_ DO_NEXT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 3d39 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000072 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-00011e 920a st -Y, r0
-00011f b60f in r0, SREG
-000120 920a st -Y, r0
- .if (pclen==3)
- .endif
-000121 900f pop r0
-000122 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-000123 940a dec r0
- .if intvecsize == 1 ;
- .endif
-000124 2cb0 mov isrflag, r0
-000125 93ff push zh
-000126 93ef push zl
-000127 e7e2 ldi zl, low(intcnt)
-000128 e0f0 ldi zh, high(intcnt)
-000129 9406 lsr r0 ; we use byte addresses in the counter array, not words
-00012a 0de0 add zl, r0
-00012b 1df3 adc zh, zeroh
-00012c 8000 ld r0, Z
-00012d 9403 inc r0
-00012e 8200 st Z, r0
-00012f 91ef pop zl
-000130 91ff pop zh
-
-000131 9009 ld r0, Y+
-000132 be0f out SREG, r0
-000133 9009 ld r0, Y+
-000134 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000135 ff02 .dw $ff02
-000136 2b6d .db "m+"
-000137 00f6 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000138 3801 .dw DO_COLON
- PFA_MPLUS:
-000139 3fc7 .dw XT_S2D
-00013a 3c15 .dw XT_DPLUS
-00013b 3820 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00013c ff03 .dw $ff03
-00013d 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-00013e 002a .db "ud*"
-00013f 0135 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-000140 3801 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000141 38b1
-000142 38ff
-000143 39e0
-000144 38d9 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000145 38c4
-000146 38f6
-000147 39e0
-000148 38e1
-000149 399d
-00014a 3820 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00014b ff04 .dw $ff04
-00014c 6d75
-00014d 7861 .db "umax"
-00014e 013c .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00014f 3801 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-000150 3ec9
-000151 395c .DW XT_2DUP,XT_ULESS
-000152 3836 .dw XT_DOCONDBRANCH
-000153 0155 DEST(UMAX1)
-000154 38c4 .DW XT_SWAP
-000155 38d9 UMAX1: .DW XT_DROP
-000156 3820 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000157 ff04 .dw $ff04
-000158 6d75
-000159 6e69 .db "umin"
-00015a 014b .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00015b 3801 .dw DO_COLON
- PFA_UMIN:
- .endif
-00015c 3ec9
-00015d 3967 .DW XT_2DUP,XT_UGREATER
-00015e 3836 .dw XT_DOCONDBRANCH
-00015f 0161 DEST(UMIN1)
-000160 38c4 .DW XT_SWAP
-000161 38d9 UMIN1: .DW XT_DROP
-000162 3820 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000163 3801 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000164 383d .dw XT_DOLITERAL
-000165 8000 .dw $8000
-000166 3a13 .dw XT_AND
-000167 391a .dw XT_ZEROEQUAL
-000168 3836 .dw XT_DOCONDBRANCH
-000169 016c DEST(IMMEDIATEQ1)
-00016a 3fe6 .dw XT_ONE
-00016b 3820 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00016c 394b .dw XT_TRUE
-00016d 3820 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00016e ff0a .dw $ff0a
-00016f 616e
-000170 656d
-000171 663e
-000172 616c
-000173 7367 .db "name>flags"
-000174 0157 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000175 3801 .dw DO_COLON
- PFA_NAME2FLAGS:
-000176 3bcb .dw XT_FETCHI ; skip to link field
-000177 383d .dw XT_DOLITERAL
-000178 ff00 .dw $ff00
-000179 3a13 .dw XT_AND
-00017a 3820 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .elif AMFORTH_NRWW_SIZE > 4000
- .include "dict/appl_4k.inc"
-
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-00017b ff03 .dw $ff03
-00017c 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-00017d 0072 .db "ver"
-00017e 016e .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00017f 3801 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-000180 02cf .dw XT_ENV_FORTHNAME
-000181 03f8 .dw XT_ITYPE
-000182 3fae .dw XT_SPACE
-000183 3ebd .dw XT_BASE
-000184 3879 .dw XT_FETCH
-
-000185 02dd .dw XT_ENV_FORTHVERSION
-000186 3f41 .dw XT_DECIMAL
-000187 3fc7 .dw XT_S2D
-000188 0316 .dw XT_L_SHARP
-000189 031e .dw XT_SHARP
-00018a 383d .dw XT_DOLITERAL
-00018b 002e .dw '.'
-00018c 0307 .dw XT_HOLD
-00018d 0334 .dw XT_SHARP_S
-00018e 033f .dw XT_SHARP_G
-00018f 042e .dw XT_TYPE
-000190 3ebd .dw XT_BASE
-000191 3881 .dw XT_STORE
-000192 3fae .dw XT_SPACE
-000193 02e5 .dw XT_ENV_CPU
-000194 03f8 .dw XT_ITYPE
-
-000195 3820 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-000196 ff04 .dw $ff04
-000197 6f6e
-000198 706f .db "noop"
-000199 017b .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-00019a 3801 .dw DO_COLON
- PFA_NOOP:
- .endif
-00019b 3820 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-00019c ff06 .dw $ff06
-00019d 6e75
-00019e 7375
-00019f 6465 .db "unused"
-0001a0 0196 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-0001a1 3801 .dw DO_COLON
- PFA_UNUSED:
-0001a2 3a8d .dw XT_SP_FETCH
-0001a3 3f23 .dw XT_HERE
-0001a4 3993 .dw XT_MINUS
-0001a5 3820 .dw XT_EXIT
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-0001a6 0002 .dw $0002
-0001a7 6f74 .db "to"
-0001a8 019c .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-0001a9 3801 .dw DO_COLON
- PFA_TO:
- .endif
-0001aa 043d .dw XT_TICK
-0001ab 3fd0 .dw XT_TO_BODY
-0001ac 3eb7 .dw XT_STATE
-0001ad 3879 .dw XT_FETCH
-0001ae 3836 .dw XT_DOCONDBRANCH
-0001af 01ba DEST(PFA_TO1)
-0001b0 0751 .dw XT_COMPILE
-0001b1 01b4 .dw XT_DOTO
-0001b2 075c .dw XT_COMMA
-0001b3 3820 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-0001b4 3801 .dw DO_COLON
- PFA_DOTO:
- .endif
-0001b5 38f6 .dw XT_R_FROM
-0001b6 38b1 .dw XT_DUP
-0001b7 01c6 .dw XT_ICELLPLUS
-0001b8 38ff .dw XT_TO_R
-0001b9 3bcb .dw XT_FETCHI
- PFA_TO1:
-0001ba 38b1 .dw XT_DUP
-0001bb 01c6 .dw XT_ICELLPLUS
-0001bc 01c6 .dw XT_ICELLPLUS
-0001bd 3bcb .dw XT_FETCHI
-0001be 382a .dw XT_EXECUTE
-0001bf 3820 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-0001c0 ff07 .dw $FF07
-0001c1 2d69
-0001c2 6563
-0001c3 6c6c
-0001c4 002b .db "i-cell+",0
-0001c5 01a6 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-0001c6 3801 .dw DO_COLON
- PFA_ICELLPLUS:
-0001c7 3a2f .dw XT_1PLUS
-0001c8 3820 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-0001c9 ff08 .dw $ff08
-0001ca 6369
-0001cb 6d6f
-0001cc 6170
-0001cd 6572 .db "icompare"
-0001ce 01c0 .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-0001cf 3801 .dw DO_COLON
- PFA_ICOMPARE:
-0001d0 38ff .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-0001d1 38cf .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-0001d2 38f6 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-0001d3 3913 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-0001d4 3836 .dw XT_DOCONDBRANCH
-0001d5 01da .dw PFA_ICOMPARE_SAMELEN
-0001d6 3ed2 .dw XT_2DROP
-0001d7 38d9 .dw XT_DROP
-0001d8 394b .dw XT_TRUE
-0001d9 3820 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-0001da 38c4 .dw XT_SWAP ; ( -- r-addr f-addr len )
-0001db 3954 .dw XT_ZERO
-0001dc 081b .dw XT_QDOCHECK
-0001dd 3836 .dw XT_DOCONDBRANCH
-0001de 01fd .dw PFA_ICOMPARE_DONE
-0001df 3a9b .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-0001e0 38cf .dw XT_OVER
-0001e1 3879 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-0001e2 38cf .dw XT_OVER
-0001e3 3bcb .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-0001e4 38b1 .dw XT_DUP
- ;.dw XT_BYTESWAP
-0001e5 383d .dw XT_DOLITERAL
-0001e6 0100 .dw $100
-0001e7 395c .dw XT_ULESS
-0001e8 3836 .dw XT_DOCONDBRANCH
-0001e9 01ee .dw PFA_ICOMPARE_LASTCELL
-0001ea 38c4 .dw XT_SWAP
-0001eb 383d .dw XT_DOLITERAL
-0001ec 00ff .dw $00FF
-0001ed 3a13 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-0001ee 3913 .dw XT_NOTEQUAL
-0001ef 3836 .dw XT_DOCONDBRANCH
-0001f0 01f5 .dw PFA_ICOMPARE_NEXTLOOP
-0001f1 3ed2 .dw XT_2DROP
-0001f2 394b .dw XT_TRUE
-0001f3 3ad4 .dw XT_UNLOOP
-0001f4 3820 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-0001f5 3a2f .dw XT_1PLUS
-0001f6 38c4 .dw XT_SWAP
-0001f7 3c90 .dw XT_CELLPLUS
-0001f8 38c4 .dw XT_SWAP
-0001f9 383d .dw XT_DOLITERAL
-0001fa 0002 .dw 2
-0001fb 3aba .dw XT_DOPLUSLOOP
-0001fc 01e0 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-0001fd 3ed2 .dw XT_2DROP
-0001fe 3954 .dw XT_ZERO
-0001ff 3820 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-000200 ff01 .dw $ff01
-000201 002a .db "*",0
-000202 01c9 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-000203 3801 .dw DO_COLON
- PFA_STAR:
- .endif
-
-000204 39a6 .dw XT_MSTAR
-000205 38d9 .dw XT_DROP
-000206 3820 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-000207 ff01 .dw $FF01
-000208 006a .db "j",0
-000209 0200 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-00020a 3801 .dw DO_COLON
- PFA_J:
-00020b 3a76 .dw XT_RP_FETCH
-00020c 383d .dw XT_DOLITERAL
-00020d 0007 .dw 7
-00020e 399d .dw XT_PLUS
-00020f 3879 .dw XT_FETCH
-000210 3a76 .dw XT_RP_FETCH
-000211 383d .dw XT_DOLITERAL
-000212 0009 .dw 9
-000213 399d .dw XT_PLUS
-000214 3879 .dw XT_FETCH
-000215 399d .dw XT_PLUS
-000216 3820 .dw XT_EXIT
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-000217 ff04 .dw $ff04
-000218 6164
-000219 7362 .db "dabs"
-00021a 0207 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-00021b 3801 .dw DO_COLON
- PFA_DABS:
-00021c 38b1 .dw XT_DUP
-00021d 3921 .dw XT_ZEROLESS
-00021e 3836 .dw XT_DOCONDBRANCH
-00021f 0221 .dw PFA_DABS1
-000220 0228 .dw XT_DNEGATE
- PFA_DABS1:
-000221 3820 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-000222 ff07 .dw $ff07
-000223 6e64
-000224 6765
-000225 7461
-000226 0065 .db "dnegate",0
-000227 0217 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-000228 3801 .dw DO_COLON
- PFA_DNEGATE:
-000229 3c3b .dw XT_DINVERT
-00022a 3fe6 .dw XT_ONE
-00022b 3954 .dw XT_ZERO
-00022c 3c15 .dw XT_DPLUS
-00022d 3820 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-00022e ff05 .dw $ff05
-00022f 6d63
-000230 766f
-000231 0065 .db "cmove",0
-000232 0222 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-000233 0234 .dw PFA_CMOVE
- PFA_CMOVE:
-000234 93bf push xh
-000235 93af push xl
-000236 91e9 ld zl, Y+
-000237 91f9 ld zh, Y+ ; addr-to
-000238 91a9 ld xl, Y+
-000239 91b9 ld xh, Y+ ; addr-from
-00023a 2f09 mov temp0, tosh
-00023b 2b08 or temp0, tosl
-00023c f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00023d 911d ld temp1, X+
-00023e 9311 st Z+, temp1
-00023f 9701 sbiw tosl, 1
-000240 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-000241 91af pop xl
-000242 91bf pop xh
-000243 9189
-000244 9199 loadtos
-000245 940c 3805 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-000247 ff05 .dw $ff05
-000248 7332
-000249 6177
-00024a 0070 .db "2swap",0
-00024b 022e .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00024c 3801 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00024d 38e1 .dw XT_ROT
-00024e 38ff .dw XT_TO_R
-00024f 38e1 .dw XT_ROT
-000250 38f6 .dw XT_R_FROM
-000251 3820 .dw XT_EXIT
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-000252 ff0a .dw $ff0a
-000253 6572
-000254 6966
-000255 6c6c
-000256 742d
-000257 6269 .db "refill-tib"
-000258 0247 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-000259 3801 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-00025a 0275 .dw XT_TIB
-00025b 383d .dw XT_DOLITERAL
-00025c 005a .dw TIB_SIZE
-00025d 048d .dw XT_ACCEPT
-00025e 027b .dw XT_NUMBERTIB
-00025f 3881 .dw XT_STORE
-000260 3954 .dw XT_ZERO
-000261 3ee2 .dw XT_TO_IN
-000262 3881 .dw XT_STORE
-000263 394b .dw XT_TRUE ; -1
-000264 3820 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-000265 ff0a .dw $FF0A
-000266 6f73
-000267 7275
-000268 6563
-000269 742d
-00026a 6269 .db "source-tib"
-00026b 0252 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00026c 3801 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00026d 0275 .dw XT_TIB
-00026e 027b .dw XT_NUMBERTIB
-00026f 3879 .dw XT_FETCH
-000270 3820 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-000271 ff03 .dw $ff03
-000272 6974
-000273 0062 .db "tib",0
-000274 0265 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-000275 3848 .dw PFA_DOVARIABLE
- PFA_TIB:
-000276 0087 .dw ram_tib
- .dseg
-000087 ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-000277 ff04 .dw $ff04
-000278 7423
-000279 6269 .db "#tib"
-00027a 0271 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00027b 3848 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00027c 00e1 .dw ram_sharptib
- .dseg
-0000e1 ram_sharptib: .byte 2
- .cseg
- .endif
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00027d ff06 .dw $ff06
-00027e 6565
-00027f 723e
-000280 6d61 .db "ee>ram"
-000281 0277 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-000282 3801 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-000283 3954 .dw XT_ZERO
-000284 3a9b .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-000285 38cf .dw XT_OVER
-000286 3b5f .dw XT_FETCHE
-000287 38cf .dw XT_OVER
-000288 3881 .dw XT_STORE
-000289 3c90 .dw XT_CELLPLUS
-00028a 38c4 .dw XT_SWAP
-00028b 3c90 .dw XT_CELLPLUS
-00028c 38c4 .dw XT_SWAP
-00028d 3ac9 .dw XT_DOLOOP
-00028e 0285 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00028f 3ed2 .dw XT_2DROP
-000290 3820 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-000291 ff08 .dw $ff08
-000292 6e69
-000293 7469
-000294 722d
-000295 6d61 .db "init-ram"
-000296 027d .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-000297 3801 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-000298 383d .dw XT_DOLITERAL
-000299 0060 .dw EE_INITUSER
-00029a 3b02 .dw XT_UP_FETCH
-00029b 383d .dw XT_DOLITERAL
-00029c 0022 .dw SYSUSERSIZE
-00029d 3a04 .dw XT_2SLASH
-00029e 0282 .dw XT_EE2RAM
-00029f 3820 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-0002a0 ff0b .dw $ff0b
-0002a1 6e65
-0002a2 6976
-0002a3 6f72
-0002a4 6d6e
-0002a5 6e65
-0002a6 0074 .db "environment",0
-0002a7 0291 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-0002a8 3848 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-0002a9 003a .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-0002aa ff09 .dw $ff09
-0002ab 6f77
-0002ac 6472
-0002ad 696c
-0002ae 7473
-0002af 0073 .db "wordlists",0
-0002b0 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-0002b1 3801 .dw DO_COLON
- PFA_ENVWORDLISTS:
-0002b2 383d .dw XT_DOLITERAL
-0002b3 0008 .dw NUMWORDLISTS
-0002b4 3820 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-0002b5 ff04 .dw $ff04
-0002b6 702f
-0002b7 6461 .db "/pad"
-0002b8 02aa .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-0002b9 3801 .dw DO_COLON
- PFA_ENVSLASHPAD:
-0002ba 3a8d .dw XT_SP_FETCH
-0002bb 3ee8 .dw XT_PAD
-0002bc 3993 .dw XT_MINUS
-0002bd 3820 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-0002be ff05 .dw $ff05
-0002bf 682f
-0002c0 6c6f
-0002c1 0064 .db "/hold",0
-0002c2 02b5 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-0002c3 3801 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-0002c4 3ee8 .dw XT_PAD
-0002c5 3f23 .dw XT_HERE
-0002c6 3993 .dw XT_MINUS
-0002c7 3820 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-0002c8 ff0a .dw $ff0a
-0002c9 6f66
-0002ca 7472
-0002cb 2d68
-0002cc 616e
-0002cd 656d .db "forth-name"
-0002ce 02be .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-0002cf 3801 .dw DO_COLON
- PFA_EN_FORTHNAME:
-0002d0 03c5 .dw XT_DOSLITERAL
-0002d1 0007 .dw 7
- .endif
-0002d2 6d61
-0002d3 6f66
-0002d4 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-0002d5 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-0002d6 3820 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-0002d7 ff07 .dw $ff07
-0002d8 6576
-0002d9 7372
-0002da 6f69
-0002db 006e .db "version",0
-0002dc 02c8 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-0002dd 3801 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-0002de 383d .dw XT_DOLITERAL
-0002df 0041 .dw 65
-0002e0 3820 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-0002e1 ff03 .dw $ff03
-0002e2 7063
-0002e3 0075 .db "cpu",0
-0002e4 02d7 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-0002e5 3801 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-0002e6 383d .dw XT_DOLITERAL
-0002e7 002d .dw mcu_name
-0002e8 0424 .dw XT_ICOUNT
-0002e9 3820 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-0002ea ff08 .dw $ff08
-0002eb 636d
-0002ec 2d75
-0002ed 6e69
-0002ee 6f66 .db "mcu-info"
-0002ef 02e1 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-0002f0 3801 .dw DO_COLON
- PFA_EN_MCUINFO:
-0002f1 383d .dw XT_DOLITERAL
-0002f2 0029 .dw mcu_info
-0002f3 3820 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-0002f4 ff05 .dw $ff05
-0002f5 752f
-0002f6 6573
-0002f7 0072 .db "/user",0
-0002f8 02ea .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-0002f9 3801 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-0002fa 383d .dw XT_DOLITERAL
-0002fb 002c .dw SYSUSERSIZE + APPUSERSIZE
-0002fc 3820 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-0002fd ff03 .dw $ff03
-0002fe 6c68
-0002ff 0064 .db "hld",0
-000300 02a0 .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-000301 3848 .dw PFA_DOVARIABLE
- PFA_HLD:
-000302 00e3 .dw ram_hld
-
- .dseg
-0000e3 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-000303 ff04 .dw $ff04
-000304 6f68
-000305 646c .db "hold"
-000306 02fd .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-000307 3801 .dw DO_COLON
- PFA_HOLD:
- .endif
-000308 0301 .dw XT_HLD
-000309 38b1 .dw XT_DUP
-00030a 3879 .dw XT_FETCH
-00030b 3a35 .dw XT_1MINUS
-00030c 38b1 .dw XT_DUP
-00030d 38ff .dw XT_TO_R
-00030e 38c4 .dw XT_SWAP
-00030f 3881 .dw XT_STORE
-000310 38f6 .dw XT_R_FROM
-000311 388d .dw XT_CSTORE
-000312 3820 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-000313 ff02 .dw $ff02
-000314 233c .db "<#"
-000315 0303 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-000316 3801 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-000317 3ee8 .dw XT_PAD
-000318 0301 .dw XT_HLD
-000319 3881 .dw XT_STORE
-00031a 3820 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-00031b ff01 .dw $ff01
-00031c 0023 .db "#",0
-00031d 0313 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-00031e 3801 .dw DO_COLON
- PFA_SHARP:
- .endif
-00031f 3ebd .dw XT_BASE
-000320 3879 .dw XT_FETCH
-000321 039b .dw XT_UDSLASHMOD
-000322 38e1 .dw XT_ROT
-000323 383d .dw XT_DOLITERAL
-000324 0009 .dw 9
-000325 38cf .dw XT_OVER
-000326 396e .dw XT_LESS
-000327 3836 .dw XT_DOCONDBRANCH
-000328 032c DEST(PFA_SHARP1)
-000329 383d .dw XT_DOLITERAL
-00032a 0007 .dw 7
-00032b 399d .dw XT_PLUS
- PFA_SHARP1:
-00032c 383d .dw XT_DOLITERAL
-00032d 0030 .dw 48 ; ASCII 0
-00032e 399d .dw XT_PLUS
-00032f 0307 .dw XT_HOLD
-000330 3820 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-000331 ff02 .dw $ff02
-000332 7323 .db "#s"
-000333 031b .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-000334 3801 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000335 031e .dw XT_SHARP
-000336 3ec9 .dw XT_2DUP
-000337 3a1c .dw XT_OR
-000338 391a .dw XT_ZEROEQUAL
-000339 3836 .dw XT_DOCONDBRANCH
-00033a 0335 DEST(NUMS1) ; PFA_SHARP_S
-00033b 3820 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00033c ff02 .dw $ff02
-00033d 3e23 .db "#>"
-00033e 0331 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00033f 3801 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-000340 3ed2 .dw XT_2DROP
-000341 0301 .dw XT_HLD
-000342 3879 .dw XT_FETCH
-000343 3ee8 .dw XT_PAD
-000344 38cf .dw XT_OVER
-000345 3993 .dw XT_MINUS
-000346 3820 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000347 ff04 .dw $ff04
-000348 6973
-000349 6e67 .db "sign"
-00034a 033c .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00034b 3801 .dw DO_COLON
- PFA_SIGN:
- .endif
-00034c 3921 .dw XT_ZEROLESS
-00034d 3836 .dw XT_DOCONDBRANCH
-00034e 0352 DEST(PFA_SIGN1)
-00034f 383d .dw XT_DOLITERAL
-000350 002d .dw 45 ; ascii -
-000351 0307 .dw XT_HOLD
- PFA_SIGN1:
-000352 3820 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-000353 ff03 .dw $ff03
-000354 2e64
-000355 0072 .db "d.r",0
-000356 0347 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000357 3801 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-000358 38ff .dw XT_TO_R
-000359 3eda .dw XT_TUCK
-00035a 021b .dw XT_DABS
-00035b 0316 .dw XT_L_SHARP
-00035c 0334 .dw XT_SHARP_S
-00035d 38e1 .dw XT_ROT
-00035e 034b .dw XT_SIGN
-00035f 033f .dw XT_SHARP_G
-000360 38f6 .dw XT_R_FROM
-000361 38cf .dw XT_OVER
-000362 3993 .dw XT_MINUS
-000363 3fb7 .dw XT_SPACES
-000364 042e .dw XT_TYPE
-000365 3820 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000366 ff02 .dw $ff02
-000367 722e .db ".r"
-000368 0353 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-000369 3801 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-00036a 38ff .dw XT_TO_R
-00036b 3fc7 .dw XT_S2D
-00036c 38f6 .dw XT_R_FROM
-00036d 0357 .dw XT_DDOTR
-00036e 3820 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00036f ff02 .dw $ff02
-000370 2e64 .db "d."
-000371 0366 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-000372 3801 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-000373 3954 .dw XT_ZERO
-000374 0357 .dw XT_DDOTR
-000375 3fae .dw XT_SPACE
-000376 3820 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-000377 ff01 .dw $ff01
-000378 002e .db ".",0
-000379 036f .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-00037a 3801 .dw DO_COLON
- PFA_DOT:
- .endif
-00037b 3fc7 .dw XT_S2D
-00037c 0372 .dw XT_DDOT
-00037d 3820 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-00037e ff03 .dw $ff03
-00037f 6475
-000380 002e .db "ud.",0
-000381 0377 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-000382 3801 .dw DO_COLON
- PFA_UDDOT:
- .endif
-000383 3954 .dw XT_ZERO
-000384 038b .dw XT_UDDOTR
-000385 3fae .dw XT_SPACE
-000386 3820 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-000387 ff04 .dw $ff04
-000388 6475
-000389 722e .db "ud.r"
-00038a 037e .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-00038b 3801 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-00038c 38ff .dw XT_TO_R
-00038d 0316 .dw XT_L_SHARP
-00038e 0334 .dw XT_SHARP_S
-00038f 033f .dw XT_SHARP_G
-000390 38f6 .dw XT_R_FROM
-000391 38cf .dw XT_OVER
-000392 3993 .dw XT_MINUS
-000393 3fb7 .dw XT_SPACES
-000394 042e .dw XT_TYPE
-000395 3820 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-000396 ff06 .dw $ff06
-000397 6475
-000398 6d2f
-000399 646f .db "ud/mod"
-00039a 0387 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-00039b 3801 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-00039c 38ff .dw XT_TO_R
-00039d 3954 .dw XT_ZERO
-00039e 3908 .dw XT_R_FETCH
-00039f 39c2 .dw XT_UMSLASHMOD
-0003a0 38f6 .dw XT_R_FROM
-0003a1 38c4 .dw XT_SWAP
-0003a2 38ff .dw XT_TO_R
-0003a3 39c2 .dw XT_UMSLASHMOD
-0003a4 38f6 .dw XT_R_FROM
-0003a5 3820 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-0003a6 ff06 .dw $ff06
-0003a7 6964
-0003a8 6967
-0003a9 3f74 .db "digit?"
-0003aa 0396 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-0003ab 3801 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-0003ac 3f66 .dw XT_TOUPPER
-0003ad 38b1
-0003ae 383d
-0003af 0039
-0003b0 3978
-0003b1 383d
-0003b2 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-0003b3 3a13
-0003b4 399d
-0003b5 38b1
-0003b6 383d
-0003b7 0140
-0003b8 3978 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-0003b9 383d
-0003ba 0107
-0003bb 3a13
-0003bc 3993
-0003bd 383d
-0003be 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-0003bf 3993
-0003c0 38b1
-0003c1 3ebd
-0003c2 3879
-0003c3 395c .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-0003c4 3820 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-0003c5 3801 .dw DO_COLON
- PFA_DOSLITERAL:
-0003c6 3908 .dw XT_R_FETCH ; ( -- addr )
-0003c7 0424 .dw XT_ICOUNT
-0003c8 38f6 .dw XT_R_FROM
-0003c9 38cf .dw XT_OVER ; ( -- addr' n addr n)
-0003ca 3a2f .dw XT_1PLUS
-0003cb 3a04 .dw XT_2SLASH ; ( -- addr' n addr k )
-0003cc 399d .dw XT_PLUS ; ( -- addr' n addr'' )
-0003cd 3a2f .dw XT_1PLUS
-0003ce 38ff .dw XT_TO_R ; ( -- )
-0003cf 3820 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-0003d0 ff02 .dw $ff02
-0003d1 2c73 .db "s",$2c
-0003d2 03a6 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-0003d3 3801 .dw DO_COLON
- PFA_SCOMMA:
-0003d4 38b1 .dw XT_DUP
-0003d5 03d7 .dw XT_DOSCOMMA
-0003d6 3820 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-0003d7 3801 .dw DO_COLON
- PFA_DOSCOMMA:
-0003d8 075c .dw XT_COMMA
-0003d9 38b1 .dw XT_DUP ; ( --addr len len)
-0003da 3a04 .dw XT_2SLASH ; ( -- addr len len/2
-0003db 3eda .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003dc 3a0b .dw XT_2STAR ; ( -- addr len/2 len len'
-0003dd 3993 .dw XT_MINUS ; ( -- addr len/2 rem
-0003de 38ff .dw XT_TO_R
-0003df 3954 .dw XT_ZERO
-0003e0 081b .dw XT_QDOCHECK
-0003e1 3836 .dw XT_DOCONDBRANCH
-0003e2 03ea .dw PFA_SCOMMA2
-0003e3 3a9b .dw XT_DODO
- PFA_SCOMMA1:
-0003e4 38b1 .dw XT_DUP ; ( -- addr addr )
-0003e5 3879 .dw XT_FETCH ; ( -- addr c1c2 )
-0003e6 075c .dw XT_COMMA ; ( -- addr )
-0003e7 3c90 .dw XT_CELLPLUS ; ( -- addr+cell )
-0003e8 3ac9 .dw XT_DOLOOP
-0003e9 03e4 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-0003ea 38f6 .dw XT_R_FROM
-0003eb 3928 .dw XT_GREATERZERO
-0003ec 3836 .dw XT_DOCONDBRANCH
-0003ed 03f1 .dw PFA_SCOMMA3
-0003ee 38b1 .dw XT_DUP ; well, tricky
-0003ef 3898 .dw XT_CFETCH
-0003f0 075c .dw XT_COMMA
- PFA_SCOMMA3:
-0003f1 38d9 .dw XT_DROP ; ( -- )
-0003f2 3820 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-0003f3 ff05 .dw $ff05
-0003f4 7469
-0003f5 7079
-0003f6 0065 .db "itype",0
-0003f7 03d0 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-0003f8 3801 .dw DO_COLON
- PFA_ITYPE:
-0003f9 38b1 .dw XT_DUP ; ( --addr len len)
-0003fa 3a04 .dw XT_2SLASH ; ( -- addr len len/2
-0003fb 3eda .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003fc 3a0b .dw XT_2STAR ; ( -- addr len/2 len len'
-0003fd 3993 .dw XT_MINUS ; ( -- addr len/2 rem
-0003fe 38ff .dw XT_TO_R
-0003ff 3954 .dw XT_ZERO
-000400 081b .dw XT_QDOCHECK
-000401 3836 .dw XT_DOCONDBRANCH
-000402 040c .dw PFA_ITYPE2
-000403 3a9b .dw XT_DODO
- PFA_ITYPE1:
-000404 38b1 .dw XT_DUP ; ( -- addr addr )
-000405 3bcb .dw XT_FETCHI ; ( -- addr c1c2 )
-000406 38b1 .dw XT_DUP
-000407 0419 .dw XT_LOWEMIT
-000408 0415 .dw XT_HIEMIT
-000409 3a2f .dw XT_1PLUS ; ( -- addr+cell )
-00040a 3ac9 .dw XT_DOLOOP
-00040b 0404 .dw PFA_ITYPE1
- PFA_ITYPE2:
-00040c 38f6 .dw XT_R_FROM
-00040d 3928 .dw XT_GREATERZERO
-00040e 3836 .dw XT_DOCONDBRANCH
-00040f 0413 .dw PFA_ITYPE3
-000410 38b1 .dw XT_DUP ; make sure the drop below has always something to do
-000411 3bcb .dw XT_FETCHI
-000412 0419 .dw XT_LOWEMIT
- PFA_ITYPE3:
-000413 38d9 .dw XT_DROP
-000414 3820 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-000415 3801 .dw DO_COLON
- PFA_HIEMIT:
-000416 3af9 .dw XT_BYTESWAP
-000417 0419 .dw XT_LOWEMIT
-000418 3820 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-000419 3801 .dw DO_COLON
- PFA_LOWEMIT:
-00041a 383d .dw XT_DOLITERAL
-00041b 00ff .dw $00ff
-00041c 3a13 .dw XT_AND
-00041d 3ef2 .dw XT_EMIT
-00041e 3820 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00041f ff06 .dw $ff06
-000420 6369
-000421 756f
-000422 746e .db "icount"
-000423 03f3 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-000424 3801 .dw DO_COLON
- PFA_ICOUNT:
-000425 38b1 .dw XT_DUP
-000426 3a2f .dw XT_1PLUS
-000427 38c4 .dw XT_SWAP
-000428 3bcb .dw XT_FETCHI
-000429 3820 .dw XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-00042a ff04 .dw $ff04
-00042b 7974
-00042c 6570 .db "type"
-00042d 041f .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-00042e 3801 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-00042f 3f99 .dw XT_BOUNDS
-000430 081b .dw XT_QDOCHECK
-000431 3836 .dw XT_DOCONDBRANCH
-000432 0439 DEST(PFA_TYPE2)
-000433 3a9b .dw XT_DODO
- PFA_TYPE1:
-000434 3aac .dw XT_I
-000435 3898 .dw XT_CFETCH
-000436 3ef2 .dw XT_EMIT
-000437 3ac9 .dw XT_DOLOOP
-000438 0434 DEST(PFA_TYPE1)
- PFA_TYPE2:
-000439 3820 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00043a ff01 .dw $ff01
-00043b 0027 .db "'",0
-00043c 042a .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00043d 3801 .dw DO_COLON
- PFA_TICK:
- .endif
-00043e 05b0 .dw XT_PARSENAME
-00043f 05f3 .dw XT_FORTHRECOGNIZER
-000440 05fe .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-000441 38b1 .dw XT_DUP
-000442 068b .dw XT_DT_NULL
-000443 3fdf .dw XT_EQUAL
-000444 38c4 .dw XT_SWAP
-000445 3bcb .dw XT_FETCHI
-000446 383d .dw XT_DOLITERAL
-000447 019a .dw XT_NOOP
-000448 3fdf .dw XT_EQUAL
-000449 3a1c .dw XT_OR
-00044a 3836 .dw XT_DOCONDBRANCH
-00044b 044f DEST(PFA_TICK1)
-00044c 383d .dw XT_DOLITERAL
-00044d fff3 .dw -13
-00044e 3d86 .dw XT_THROW
- PFA_TICK1:
-00044f 38d9 .dw XT_DROP
-000450 3820 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-000451 ff05 .dw $ff05
-000452 7363
-000453 696b
-000454 0070 .db "cskip",0
-000455 043a .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-000456 3801 .dw DO_COLON
- PFA_CSKIP:
- .endif
-000457 38ff .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-000458 38b1 .dw XT_DUP ; ( -- addr' n' n' )
-000459 3836 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00045a 0465 DEST(PFA_CSKIP2)
-00045b 38cf .dw XT_OVER ; ( -- addr' n' addr' )
-00045c 3898 .dw XT_CFETCH ; ( -- addr' n' c' )
-00045d 3908 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-00045e 3fdf .dw XT_EQUAL ; ( -- addr' n' f )
-00045f 3836 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000460 0465 DEST(PFA_CSKIP2)
-000461 3fe6 .dw XT_ONE
-000462 05a1 .dw XT_SLASHSTRING
-000463 382f .dw XT_DOBRANCH
-000464 0458 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-000465 38f6 .dw XT_R_FROM
-000466 38d9 .dw XT_DROP ; ( -- addr2 n2)
-000467 3820 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-000468 ff05 .dw $ff05
-000469 7363
-00046a 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00046b 006e .db "cscan"
-00046c 0451 .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-00046d 3801 .dw DO_COLON
- PFA_CSCAN:
- .endif
-00046e 38ff .dw XT_TO_R
-00046f 38cf .dw XT_OVER
- PFA_CSCAN1:
-000470 38b1 .dw XT_DUP
-000471 3898 .dw XT_CFETCH
-000472 3908 .dw XT_R_FETCH
-000473 3fdf .dw XT_EQUAL
-000474 391a .dw XT_ZEROEQUAL
-000475 3836 .dw XT_DOCONDBRANCH
-000476 0482 DEST(PFA_CSCAN2)
-000477 38c4 .dw XT_SWAP
-000478 3a35 .dw XT_1MINUS
-000479 38c4 .dw XT_SWAP
-00047a 38cf .dw XT_OVER
-00047b 3921 .dw XT_ZEROLESS ; not negative
-00047c 391a .dw XT_ZEROEQUAL
-00047d 3836 .dw XT_DOCONDBRANCH
-00047e 0482 DEST(PFA_CSCAN2)
-00047f 3a2f .dw XT_1PLUS
-000480 382f .dw XT_DOBRANCH
-000481 0470 DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-000482 38f0 .dw XT_NIP
-000483 38cf .dw XT_OVER
-000484 3993 .dw XT_MINUS
-000485 38f6 .dw XT_R_FROM
-000486 38d9 .dw XT_DROP
-000487 3820 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-000488 ff06 .dw $ff06
-000489 6361
-00048a 6563
-00048b 7470 .db "accept"
-00048c 0468 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-00048d 3801 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-00048e 38cf
-00048f 399d
-000490 3a35
-000491 38cf .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-000492 3f03
-000493 38b1
-000494 04ce
-000495 391a
-000496 3836 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-000497 04c0 DEST(ACC5)
-000498 38b1
-000499 383d
-00049a 0008
-00049b 3fdf
-00049c 3836 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-00049d 04b0 DEST(ACC3)
-00049e 38d9
-00049f 38e1
-0004a0 3ec9
-0004a1 3978
-0004a2 38ff
-0004a3 38e1
-0004a4 38e1
-0004a5 38f6
-0004a6 3836 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-0004a7 04ae DEST(ACC6)
-0004a8 04c6
-0004a9 3a35
-0004aa 38ff
-0004ab 38cf
-0004ac 38f6
-0004ad 014f .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-0004ae 382f ACC6: .DW XT_DOBRANCH
-0004af 04be DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-0004b0 38b1 .dw XT_DUP ; ( -- addr k k )
-0004b1 3f54 .dw XT_BL
-0004b2 396e .dw XT_LESS
-0004b3 3836 .dw XT_DOCONDBRANCH
-0004b4 04b7 DEST(PFA_ACCEPT6)
-0004b5 38d9 .dw XT_DROP
-0004b6 3f54 .dw XT_BL
- PFA_ACCEPT6:
-0004b7 38b1
-0004b8 3ef2
-0004b9 38cf
-0004ba 388d
-0004bb 3a2f
-0004bc 38cf
-0004bd 015b .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-0004be 382f ACC4: .DW XT_DOBRANCH
-0004bf 0492 DEST(ACC1)
-0004c0 38d9
-0004c1 38f0
-0004c2 38c4
-0004c3 3993
-0004c4 3fa1
-0004c5 3820 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-0004c6 3801 .dw DO_COLON
- .endif
-0004c7 383d .dw XT_DOLITERAL
-0004c8 0008 .dw 8
-0004c9 38b1 .dw XT_DUP
-0004ca 3ef2 .dw XT_EMIT
-0004cb 3fae .dw XT_SPACE
-0004cc 3ef2 .dw XT_EMIT
-0004cd 3820 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-0004ce 3801 .dw DO_COLON
- .endif
-0004cf 38b1 .dw XT_DUP
-0004d0 383d .dw XT_DOLITERAL
-0004d1 000d .dw 13
-0004d2 3fdf .dw XT_EQUAL
-0004d3 38c4 .dw XT_SWAP
-0004d4 383d .dw XT_DOLITERAL
-0004d5 000a .dw 10
-0004d6 3fdf .dw XT_EQUAL
-0004d7 3a1c .dw XT_OR
-0004d8 3820 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-0004d9 ff06 .dw $ff06
-0004da 6572
-0004db 6966
-0004dc 6c6c .db "refill"
-0004dd 0488 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-0004de 3dff .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-0004df 001a .dw USER_REFILL
-0004e0 3dc8 .dw XT_UDEFERFETCH
-0004e1 3dd4 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-0004e2 ff04 .dw $ff04
-0004e3 6863
-0004e4 7261 .db "char"
-0004e5 04d9 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-0004e6 3801 .dw DO_COLON
- PFA_CHAR:
- .endif
-0004e7 05b0 .dw XT_PARSENAME
-0004e8 38d9 .dw XT_DROP
-0004e9 3898 .dw XT_CFETCH
-0004ea 3820 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-0004eb ff06 .dw $ff06
-0004ec 756e
-0004ed 626d
-0004ee 7265 .db "number"
-0004ef 04e2 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-0004f0 3801 .dw DO_COLON
- PFA_NUMBER:
- .endif
-0004f1 3ebd .dw XT_BASE
-0004f2 3879 .dw XT_FETCH
-0004f3 38ff .dw XT_TO_R
-0004f4 0534 .dw XT_QSIGN
-0004f5 38ff .dw XT_TO_R
-0004f6 0547 .dw XT_SET_BASE
-0004f7 0534 .dw XT_QSIGN
-0004f8 38f6 .dw XT_R_FROM
-0004f9 3a1c .dw XT_OR
-0004fa 38ff .dw XT_TO_R
- ; check whether something is left
-0004fb 38b1 .dw XT_DUP
-0004fc 391a .dw XT_ZEROEQUAL
-0004fd 3836 .dw XT_DOCONDBRANCH
-0004fe 0507 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-0004ff 3ed2 .dw XT_2DROP
-000500 38f6 .dw XT_R_FROM
-000501 38d9 .dw XT_DROP
-000502 38f6 .dw XT_R_FROM
-000503 3ebd .dw XT_BASE
-000504 3881 .dw XT_STORE
-000505 3954 .dw XT_ZERO
-000506 3820 .dw XT_EXIT
- PFA_NUMBER0:
-000507 3b1e .dw XT_2TO_R
-000508 3954 .dw XT_ZERO ; starting value
-000509 3954 .dw XT_ZERO
-00050a 3b2d .dw XT_2R_FROM
-00050b 0565 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-00050c 38b9 .dw XT_QDUP
-00050d 3836 .dw XT_DOCONDBRANCH
-00050e 0529 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00050f 3fe6 .dw XT_ONE
-000510 3fdf .dw XT_EQUAL
-000511 3836 .dw XT_DOCONDBRANCH
-000512 0520 DEST(PFA_NUMBER2)
- ; excatly one character is left
-000513 3898 .dw XT_CFETCH
-000514 383d .dw XT_DOLITERAL
-000515 002e .dw 46 ; .
-000516 3fdf .dw XT_EQUAL
-000517 3836 .dw XT_DOCONDBRANCH
-000518 0521 DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-000519 38f6 .dw XT_R_FROM
-00051a 3836 .dw XT_DOCONDBRANCH
-00051b 051d DEST(PFA_NUMBER3)
-00051c 0228 .dw XT_DNEGATE
- PFA_NUMBER3:
-00051d 3feb .dw XT_TWO
-00051e 382f .dw XT_DOBRANCH
-00051f 052f DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-000520 38d9 .dw XT_DROP
- PFA_NUMBER6:
-000521 3ed2 .dw XT_2DROP
-000522 38f6 .dw XT_R_FROM
-000523 38d9 .dw XT_DROP
-000524 38f6 .dw XT_R_FROM
-000525 3ebd .dw XT_BASE
-000526 3881 .dw XT_STORE
-000527 3954 .dw XT_ZERO
-000528 3820 .dw XT_EXIT
- PFA_NUMBER1:
-000529 3ed2 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-00052a 38f6 .dw XT_R_FROM
-00052b 3836 .dw XT_DOCONDBRANCH
-00052c 052e DEST(PFA_NUMBER4)
-00052d 3e27 .dw XT_NEGATE
- PFA_NUMBER4:
-00052e 3fe6 .dw XT_ONE
- PFA_NUMBER5:
-00052f 38f6 .dw XT_R_FROM
-000530 3ebd .dw XT_BASE
-000531 3881 .dw XT_STORE
-000532 394b .dw XT_TRUE
-000533 3820 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-000534 3801 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-000535 38cf .dw XT_OVER ; ( -- addr len addr )
-000536 3898 .dw XT_CFETCH
-000537 383d .dw XT_DOLITERAL
-000538 002d .dw '-'
-000539 3fdf .dw XT_EQUAL ; ( -- addr len flag )
-00053a 38b1 .dw XT_DUP
-00053b 38ff .dw XT_TO_R
-00053c 3836 .dw XT_DOCONDBRANCH
-00053d 0540 DEST(PFA_NUMBERSIGN_DONE)
-00053e 3fe6 .dw XT_ONE ; skip sign character
-00053f 05a1 .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-000540 38f6 .dw XT_R_FROM
-000541 3820 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-000542 3852 .dw PFA_DOCONSTANT
- .endif
-000543 000a
-000544 0010
-000545 0002
-000546 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-000547 3801 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-000548 38cf .dw XT_OVER
-000549 3898 .dw XT_CFETCH
-00054a 383d .dw XT_DOLITERAL
-00054b 0023 .dw 35
-00054c 3993 .dw XT_MINUS
-00054d 38b1 .dw XT_DUP
-00054e 3954 .dw XT_ZERO
-00054f 383d .dw XT_DOLITERAL
-000550 0004 .dw 4
-000551 3e57 .dw XT_WITHIN
-000552 3836 .dw XT_DOCONDBRANCH
-000553 055d DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-000554 0542 .dw XT_BASES
-000555 399d .dw XT_PLUS
-000556 3bcb .dw XT_FETCHI
-000557 3ebd .dw XT_BASE
-000558 3881 .dw XT_STORE
-000559 3fe6 .dw XT_ONE
-00055a 05a1 .dw XT_SLASHSTRING
-00055b 382f .dw XT_DOBRANCH
-00055c 055e DEST(SET_BASE2)
- SET_BASE1:
-00055d 38d9 .dw XT_DROP
- SET_BASE2:
-00055e 3820 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00055f ff07 .dw $ff07
-000560 6e3e
-000561 6d75
-000562 6562
-000563 0072 .db ">number",0
-000564 04eb .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-000565 3801 .dw DO_COLON
-
- .endif
-
-000566 38b1
-000567 3836 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-000568 057d DEST(TONUM3)
-000569 38cf
-00056a 3898
-00056b 03ab .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-00056c 391a
-00056d 3836 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-00056e 0571 DEST(TONUM2)
-00056f 38d9
-000570 3820 .DW XT_DROP,XT_EXIT
-000571 38ff
-000572 024c
-000573 3ebd
-000574 3879
-000575 0140 TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000576 38f6
-000577 0138
-000578 024c .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-000579 3fe6
-00057a 05a1
-00057b 382f .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-00057c 0566 DEST(TONUM1)
-00057d 3820 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-00057e ff05 .dw $ff05
-00057f 6170
-000580 7372
-000581 0065 .db "parse",0
-000582 055f .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-000583 3801 .dw DO_COLON
- PFA_PARSE:
- .endif
-000584 38ff .dw XT_TO_R ; ( -- )
-000585 0597 .dw XT_SOURCE ; ( -- addr len)
-000586 3ee2 .dw XT_TO_IN ; ( -- addr len >in)
-000587 3879 .dw XT_FETCH
-000588 05a1 .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-000589 38f6 .dw XT_R_FROM ; ( -- addr' len' c)
-00058a 046d .dw XT_CSCAN ; ( -- addr' len'')
-00058b 38b1 .dw XT_DUP ; ( -- addr' len'' len'')
-00058c 3a2f .dw XT_1PLUS
-00058d 3ee2 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-00058e 3a65 .dw XT_PLUSSTORE ; ( -- addr' len')
-00058f 3fe6 .dw XT_ONE
-000590 05a1 .dw XT_SLASHSTRING
-000591 3820 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-000592 ff06 .dw $FF06
-000593 6f73
-000594 7275
-000595 6563 .db "source"
-000596 057e .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-000597 3dff .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-000598 0016 .dw USER_SOURCE
-000599 3dc8 .dw XT_UDEFERFETCH
-00059a 3dd4 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00059b ff07 .dw $ff07
-00059c 732f
-00059d 7274
-00059e 6e69
-00059f 0067 .db "/string",0
-0005a0 0592 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-0005a1 3801 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-0005a2 38e1 .dw XT_ROT
-0005a3 38cf .dw XT_OVER
-0005a4 399d .dw XT_PLUS
-0005a5 38e1 .dw XT_ROT
-0005a6 38e1 .dw XT_ROT
-0005a7 3993 .dw XT_MINUS
-0005a8 3820 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-0005a9 ff0a .dw $FF0A
-0005aa 6170
-0005ab 7372
-0005ac 2d65
-0005ad 616e
-0005ae 656d .db "parse-name"
-0005af 059b .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-0005b0 3801 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-0005b1 3f54 .dw XT_BL
-0005b2 05b4 .dw XT_SKIPSCANCHAR
-0005b3 3820 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-0005b4 3801 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-0005b5 38ff .dw XT_TO_R
-0005b6 0597 .dw XT_SOURCE
-0005b7 3ee2 .dw XT_TO_IN
-0005b8 3879 .dw XT_FETCH
-0005b9 05a1 .dw XT_SLASHSTRING
-
-0005ba 3908 .dw XT_R_FETCH
-0005bb 0456 .dw XT_CSKIP
-0005bc 38f6 .dw XT_R_FROM
-0005bd 046d .dw XT_CSCAN
-
- ; adjust >IN
-0005be 3ec9 .dw XT_2DUP
-0005bf 399d .dw XT_PLUS
-0005c0 0597 .dw XT_SOURCE
-0005c1 38d9 .dw XT_DROP
-0005c2 3993 .dw XT_MINUS
-0005c3 3ee2 .dw XT_TO_IN
-0005c4 3881 .dw XT_STORE
-0005c5 3820 .dw XT_EXIT
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-0005c6 ff03 .dw $ff03
-0005c7 7073
-0005c8 0030 .db "sp0",0
-0005c9 05a9 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-0005ca 386f .dw PFA_DOVALUE1
- PFA_SP0:
-0005cb 0006 .dw USER_SP0
-0005cc 3dc8 .dw XT_UDEFERFETCH
-0005cd 3dd4 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-0005ce ff02 .dw $ff02
-0005cf 7073 .db "sp"
-0005d0 05c6 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-0005d1 3858 .dw PFA_DOUSER
- PFA_SP:
-0005d2 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-0005d3 ff03 .dw $ff03
-0005d4 7072
-0005d5 0030 .db "rp0",0
-0005d6 05ce .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-0005d7 3801 .dw DO_COLON
- PFA_RP0:
-0005d8 05db .dw XT_DORP0
-0005d9 3879 .dw XT_FETCH
-0005da 3820 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-0005db 3858 .dw PFA_DOUSER
- PFA_DORP0:
-0005dc 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-0005dd ff05 .dw $ff05
-0005de 6564
-0005df 7470
-0005e0 0068 .db "depth",0
-0005e1 05d3 .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-0005e2 3801 .dw DO_COLON
- PFA_DEPTH:
- .endif
-0005e3 05ca .dw XT_SP0
-0005e4 3a8d .dw XT_SP_FETCH
-0005e5 3993 .dw XT_MINUS
-0005e6 3a04 .dw XT_2SLASH
-0005e7 3a35 .dw XT_1MINUS
-0005e8 3820 .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-0005e9 ff10 .dw $ff10
-0005ea 6f66
-0005eb 7472
-0005ec 2d68
-0005ed 6572
-0005ee 6f63
-0005ef 6e67
-0005f0 7a69
-0005f1 7265 .db "forth-recognizer"
-0005f2 05dd .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-0005f3 386f .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-0005f4 0034 .dw CFG_FORTHRECOGNIZER
-0005f5 3da0 .dw XT_EDEFERFETCH
-0005f6 3daa .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-0005f7 ff09 .dw $ff09
-0005f8 6572
-0005f9 6f63
-0005fa 6e67
-0005fb 7a69
-0005fc 0065 .db "recognize",0
-0005fd 05e9 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-0005fe 3801 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-0005ff 383d .dw XT_DOLITERAL
-000600 0609 .dw XT_RECOGNIZE_A
-000601 38c4 .dw XT_SWAP
-000602 099c .dw XT_MAPSTACK
-000603 391a .dw XT_ZEROEQUAL
-000604 3836 .dw XT_DOCONDBRANCH
-000605 0608 DEST(PFA_RECOGNIZE1)
-000606 3ed2 .dw XT_2DROP
-000607 068b .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-000608 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-000609 3801 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-00060a 38e1 .dw XT_ROT ; -- len xt addr
-00060b 38e1 .dw XT_ROT ; -- xt addr len
-00060c 3ec9 .dw XT_2DUP
-00060d 3b1e .dw XT_2TO_R
-00060e 38e1 .dw XT_ROT ; -- addr len xt
-00060f 382a .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-000610 3b2d .dw XT_2R_FROM
-000611 38e1 .dw XT_ROT
-000612 38b1 .dw XT_DUP
-000613 068b .dw XT_DT_NULL
-000614 3fdf .dw XT_EQUAL
-000615 3836 .dw XT_DOCONDBRANCH
-000616 061a DEST(PFA_RECOGNIZE_A1)
-000617 38d9 .dw XT_DROP
-000618 3954 .dw XT_ZERO
-000619 3820 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-00061a 38f0 .dw XT_NIP
-00061b 38f0 .dw XT_NIP
-00061c 394b .dw XT_TRUE
-00061d 3820 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-00061e ff09 .dw $ff09
-00061f 6e69
-000620 6574
-000621 7072
-000622 6572
-000623 0074 .db "interpret",0
-000624 05f7 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-000625 3801 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-000626 05b0 .dw XT_PARSENAME ; ( -- addr len )
-000627 38b1 .dw XT_DUP ; ( -- addr len flag)
-000628 3836 .dw XT_DOCONDBRANCH
-000629 0636 DEST(PFA_INTERPRET2)
-00062a 05f3 .dw XT_FORTHRECOGNIZER
-00062b 05fe .dw XT_RECOGNIZE
-00062c 3eb7 .dw XT_STATE
-00062d 3879 .dw XT_FETCH
-00062e 3836 .dw XT_DOCONDBRANCH
-00062f 0631 DEST(PFA_INTERPRET1)
-000630 01c6 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-000631 3bcb .dw XT_FETCHI
-000632 382a .dw XT_EXECUTE
-000633 3f8b .dw XT_QSTACK
-000634 382f .dw XT_DOBRANCH
-000635 0626 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000636 3ed2 .dw XT_2DROP
-000637 3820 .dw XT_EXIT
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-000638 ff06 .dw $ff06
-000639 7464
-00063a 6e3a
-00063b 6d75 .db "dt:num"
-00063c 061e .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-00063d 3852 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-00063e 019a .dw XT_NOOP ; interpret
-00063f 0772 .dw XT_LITERAL ; compile
-000640 0772 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-000641 ff07 .dw $ff07
-000642 7464
-000643 643a
-000644 756e
-000645 006d .db "dt:dnum",0
-000646 0638 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000647 3852 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-000648 019a .dw XT_NOOP ; interpret
-000649 3fd7 .dw XT_2LITERAL ; compile
-00064a 3fd7 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-00064b ff07 .dw $ff07
-00064c 6572
-00064d 3a63
-00064e 756e
-00064f 006d .db "rec:num",0
-000650 0641 .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-000651 3801 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-000652 04f0 .dw XT_NUMBER
-000653 3836 .dw XT_DOCONDBRANCH
-000654 065d DEST(PFA_REC_NONUMBER)
-000655 3fe6 .dw XT_ONE
-000656 3fdf .dw XT_EQUAL
-000657 3836 .dw XT_DOCONDBRANCH
-000658 065b DEST(PFA_REC_INTNUM2)
-000659 063d .dw XT_DT_NUM
-00065a 3820 .dw XT_EXIT
- PFA_REC_INTNUM2:
-00065b 0647 .dw XT_DT_DNUM
-00065c 3820 .dw XT_EXIT
- PFA_REC_NONUMBER:
-00065d 068b .dw XT_DT_NULL
-00065e 3820 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00065f ff08 .dw $ff08
-000660 6572
-000661 3a63
-000662 6966
-000663 646e .db "rec:find"
-000664 064b .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000665 3801 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000666 0700 .DW XT_FINDXT
-000667 38b1 .dw XT_DUP
-000668 391a .dw XT_ZEROEQUAL
-000669 3836 .dw XT_DOCONDBRANCH
-00066a 066e DEST(PFA_REC_WORD_FOUND)
-00066b 38d9 .dw XT_DROP
-00066c 068b .dw XT_DT_NULL
-00066d 3820 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-00066e 0675 .dw XT_DT_XT
-
-00066f 3820 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-000670 ff05 .dw $ff05
-000671 7464
-000672 783a
-000673 0074 .db "dt:xt",0
-000674 065f .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000675 3852 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000676 0679 .dw XT_R_WORD_INTERPRET
-000677 067d .dw XT_R_WORD_COMPILE
-000678 3fd7 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-000679 3801 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-00067a 38d9 .dw XT_DROP ; the flags are in the way
-00067b 382a .dw XT_EXECUTE
-00067c 3820 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-00067d 3801 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-00067e 3921 .dw XT_ZEROLESS
-00067f 3836 .dw XT_DOCONDBRANCH
-000680 0683 DEST(PFA_R_WORD_COMPILE1)
-000681 075c .dw XT_COMMA
-000682 3820 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-000683 382a .dw XT_EXECUTE
-000684 3820 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000685 ff07 .dw $ff07
-000686 7464
-000687 6e3a
-000688 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-000689 006c .db "dt:null"
-00068a 0670 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-00068b 3852 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-00068c 068f .dw XT_FAIL ; interpret
-00068d 068f .dw XT_FAIL ; compile
-00068e 068f .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00068f 3801 .dw DO_COLON
- PFA_FAIL:
- .endif
-000690 383d .dw XT_DOLITERAL
-000691 fff3 .dw -13
-000692 3d86 .dw XT_THROW
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-000693 ff0f .dw $ff0f
-000694 6573
-000695 7261
-000696 6863
-000697 772d
-000698 726f
-000699 6c64
-00069a 7369
-00069b 0074 .db "search-wordlist",0
-00069c 0685 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00069d 3801 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-00069e 38ff .dw XT_TO_R
-00069f 3954 .dw XT_ZERO
-0006a0 383d .dw XT_DOLITERAL
-0006a1 06b2 .dw XT_ISWORD
-0006a2 38f6 .dw XT_R_FROM
-0006a3 06cf .dw XT_TRAVERSEWORDLIST
-0006a4 38b1 .dw XT_DUP
-0006a5 391a .dw XT_ZEROEQUAL
-0006a6 3836 .dw XT_DOCONDBRANCH
-0006a7 06ac DEST(PFA_SEARCH_WORDLIST1)
-0006a8 3ed2 .dw XT_2DROP
-0006a9 38d9 .dw XT_DROP
-0006aa 3954 .dw XT_ZERO
-0006ab 3820 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-0006ac 38b1 .dw XT_DUP
-0006ad 06f6 .dw XT_NFA2CFA
- ; .. and get the header flag
-0006ae 38c4 .dw XT_SWAP
-0006af 0175 .dw XT_NAME2FLAGS
-0006b0 0163 .dw XT_IMMEDIATEQ
-0006b1 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-0006b2 3801 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-0006b3 38ff .dw XT_TO_R
-0006b4 38d9 .dw XT_DROP
-0006b5 3ec9 .dw XT_2DUP
-0006b6 3908 .dw XT_R_FETCH ; -- addr len addr len nt
-0006b7 06ea .dw XT_NAME2STRING
-0006b8 01cf .dw XT_ICOMPARE ; (-- addr len f )
-0006b9 3836 .dw XT_DOCONDBRANCH
-0006ba 06c0 DEST(PFA_ISWORD3)
- ; not now
-0006bb 38f6 .dw XT_R_FROM
-0006bc 38d9 .dw XT_DROP
-0006bd 3954 .dw XT_ZERO
-0006be 394b .dw XT_TRUE ; maybe next word
-0006bf 3820 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-0006c0 3ed2 .dw XT_2DROP
-0006c1 38f6 .dw XT_R_FROM
-0006c2 3954 .dw XT_ZERO ; finish traverse-wordlist
-0006c3 3820 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-0006c4 ff11 .dw $ff11
-0006c5 7274
-0006c6 7661
-0006c7 7265
-0006c8 6573
-0006c9 772d
-0006ca 726f
-0006cb 6c64
-0006cc 7369
-0006cd 0074 .db "traverse-wordlist",0
-0006ce 0693 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-0006cf 3801 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-0006d0 3b5f .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-0006d1 38b1 .dw XT_DUP ; ( -- xt nt nt )
-0006d2 3836 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-0006d3 06e0 DEST(PFA_TRAVERSEWORDLIST2)
-0006d4 3ec9 .dw XT_2DUP
-0006d5 3b1e .dw XT_2TO_R
-0006d6 38c4 .dw XT_SWAP
-0006d7 382a .dw XT_EXECUTE
-0006d8 3b2d .dw XT_2R_FROM
-0006d9 38e1 .dw XT_ROT
-0006da 3836 .dw XT_DOCONDBRANCH
-0006db 06e0 DEST(PFA_TRAVERSEWORDLIST2)
-0006dc 0a0b .dw XT_NFA2LFA
-0006dd 3bcb .dw XT_FETCHI
-0006de 382f .dw XT_DOBRANCH ; ( -- addr )
-0006df 06d1 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-0006e0 3ed2 .dw XT_2DROP
-0006e1 3820 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-0006e2 ff0b .dw $ff0b
-0006e3 616e
-0006e4 656d
-0006e5 733e
-0006e6 7274
-0006e7 6e69
-0006e8 0067 .db "name>string",0
-0006e9 06c4 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-0006ea 3801 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-0006eb 0424 .dw XT_ICOUNT ; ( -- addr n )
-0006ec 383d .dw XT_DOLITERAL
-0006ed 00ff .dw 255
-0006ee 3a13 .dw XT_AND ; mask immediate bit
-0006ef 3820 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-0006f0 ff07 .dw $ff07
-0006f1 666e
-0006f2 3e61
-0006f3 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-0006f4 0061 .db "nfa>cfa"
-0006f5 06e2 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-0006f6 3801 .dw DO_COLON
- PFA_NFA2CFA:
-0006f7 0a0b .dw XT_NFA2LFA ; skip to link field
-0006f8 3a2f .dw XT_1PLUS ; next is the execution token
-0006f9 3820 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-0006fa ff07 .dw $ff07
-0006fb 6966
-0006fc 646e
-0006fd 782d
-0006fe 0074 .db "find-xt",0
-0006ff 06f0 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-000700 3801 .dw DO_COLON
- PFA_FINDXT:
- .endif
-000701 383d .dw XT_DOLITERAL
-000702 070c .dw XT_FINDXTA
-000703 383d .dw XT_DOLITERAL
-000704 0040 .dw CFG_ORDERLISTLEN
-000705 099c .dw XT_MAPSTACK
-000706 391a .dw XT_ZEROEQUAL
-000707 3836 .dw XT_DOCONDBRANCH
-000708 070b DEST(PFA_FINDXT1)
-000709 3ed2 .dw XT_2DROP
-00070a 3954 .dw XT_ZERO
- PFA_FINDXT1:
-00070b 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-00070c 3801 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-00070d 38ff .dw XT_TO_R
-00070e 3ec9 .dw XT_2DUP
-00070f 38f6 .dw XT_R_FROM
-000710 069d .dw XT_SEARCH_WORDLIST
-000711 38b1 .dw XT_DUP
-000712 3836 .dw XT_DOCONDBRANCH
-000713 0719 DEST(PFA_FINDXTA1)
-000714 38ff .dw XT_TO_R
-000715 38f0 .dw XT_NIP
-000716 38f0 .dw XT_NIP
-000717 38f6 .dw XT_R_FROM
-000718 394b .dw XT_TRUE
- PFA_FINDXTA1:
-000719 3820 .dw XT_EXIT
-
- .include "dict/compiler1.inc"
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-00071a ff06 .dw $ff06
-00071b 656e
-00071c 6577
-00071d 7473 .db "newest"
-00071e 06fa .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-00071f 3848 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-000720 00e5 .dw ram_newest
-
- .dseg
-0000e5 ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-000721 ff06 .dw $ff06
-000722 616c
-000723 6574
-000724 7473 .db "latest"
-000725 071a .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000726 3848 .dw PFA_DOVARIABLE
- PFA_LATEST:
-000727 00e9 .dw ram_latest
-
- .dseg
-0000e9 ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-000728 ff08 .dw $ff08
-000729 6328
-00072a 6572
-00072b 7461
-00072c 2965 .db "(create)"
-00072d 0721 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-00072e 3801 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-00072f 05b0
-000730 0885 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-000731 38b1
-000732 071f
-000733 3c90
-000734 3881 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000735 086a
-000736 071f
-000737 3881 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-000738 3820 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-000739 0001 .dw $0001
-00073a 005c .db $5c,0
-00073b 0728 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-00073c 3801 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-00073d 0597 .dw XT_SOURCE
-00073e 38f0 .dw XT_NIP
-00073f 3ee2 .dw XT_TO_IN
-000740 3881 .dw XT_STORE
-000741 3820 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-000742 0001 .dw $0001
-000743 0028 .db "(" ,0
-000744 0739 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000745 3801 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000746 383d .dw XT_DOLITERAL
-000747 0029 .dw ')'
-000748 0583 .dw XT_PARSE
-000749 3ed2 .dw XT_2DROP
-00074a 3820 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-00074b ff07 .dw $ff07
-00074c 6f63
-00074d 706d
-00074e 6c69
-00074f 0065 .db "compile",0
-000750 0742 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-000751 3801 .dw DO_COLON
- PFA_COMPILE:
- .endif
-000752 38f6 .dw XT_R_FROM
-000753 38b1 .dw XT_DUP
-000754 01c6 .dw XT_ICELLPLUS
-000755 38ff .dw XT_TO_R
-000756 3bcb .dw XT_FETCHI
-000757 075c .dw XT_COMMA
-000758 3820 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-000759 ff01 .dw $ff01
-00075a 002c .db ',',0 ; ,
-00075b 074b .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-00075c 3801 .dw DO_COLON
- PFA_COMMA:
-00075d 3f12 .dw XT_DP
-00075e 3b73 .dw XT_STOREI
-00075f 3f12 .dw XT_DP
-000760 3a2f .dw XT_1PLUS
-000761 01b4 .dw XT_DOTO
-000762 3f13 .dw PFA_DP
-000763 3820 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-000764 0003 .dw $0003
-000765 275b
-000766 005d .db "[']",0
-000767 0759 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-000768 3801 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-000769 043d .dw XT_TICK
-00076a 0772 .dw XT_LITERAL
-00076b 3820 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-00076c 0007 .dw $0007
-00076d 696c
-00076e 6574
-00076f 6172
-000770 006c .db "literal",0
-000771 0764 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-000772 3801 .dw DO_COLON
- PFA_LITERAL:
- .endif
-000773 0751 .DW XT_COMPILE
-000774 383d .DW XT_DOLITERAL
-000775 075c .DW XT_COMMA
-000776 3820 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-000777 0008 .dw $0008
-000778 6c73
-000779 7469
-00077a 7265
-00077b 6c61 .db "sliteral"
-00077c 076c .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-00077d 3801 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-00077e 0751 .dw XT_COMPILE
-00077f 03c5 .dw XT_DOSLITERAL ; ( -- addr n)
-000780 03d3 .dw XT_SCOMMA
-000781 3820 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-000782 3801 .dw DO_COLON
- PFA_GMARK:
-000783 3f12 .dw XT_DP
-000784 0751 .dw XT_COMPILE
-000785 ffff .dw -1 ; ffff does not erase flash
-000786 3820 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000787 3801 .dw DO_COLON
- PFA_GRESOLVE:
-000788 3f8b .dw XT_QSTACK
-000789 3f12 .dw XT_DP
-00078a 38c4 .dw XT_SWAP
-00078b 3b73 .dw XT_STOREI
-00078c 3820 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-00078d 3801 .dw DO_COLON
- PFA_LMARK:
-00078e 3f12 .dw XT_DP
-00078f 3820 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-000790 3801 .dw DO_COLON
- PFA_LRESOLVE:
-000791 3f8b .dw XT_QSTACK
-000792 075c .dw XT_COMMA
-000793 3820 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-000794 0005 .dw $0005
-000795 6861
-000796 6165
-000797 0064 .db "ahead",0
-000798 0777 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-000799 3801 .dw DO_COLON
- PFA_AHEAD:
- .endif
-00079a 0751 .dw XT_COMPILE
-00079b 382f .dw XT_DOBRANCH
-00079c 0782 .dw XT_GMARK
-00079d 3820 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-00079e 0002 .dw $0002
-00079f 6669 .db "if"
-0007a0 0794 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-0007a1 3801 .dw DO_COLON
- PFA_IF:
- .endif
-0007a2 0751 .dw XT_COMPILE
-0007a3 3836 .dw XT_DOCONDBRANCH
-0007a4 0782 .dw XT_GMARK
-0007a5 3820 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-0007a6 0004 .dw $0004
-0007a7 6c65
-0007a8 6573 .db "else"
-0007a9 079e .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-0007aa 3801 .dw DO_COLON
- PFA_ELSE:
- .endif
-0007ab 0751 .dw XT_COMPILE
-0007ac 382f .dw XT_DOBRANCH
-0007ad 0782 .dw XT_GMARK
-0007ae 38c4 .dw XT_SWAP
-0007af 0787 .dw XT_GRESOLVE
-0007b0 3820 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-0007b1 0004 .dw $0004
-0007b2 6874
-0007b3 6e65 .db "then"
-0007b4 07a6 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-0007b5 3801 .dw DO_COLON
- PFA_THEN:
- .endif
-0007b6 0787 .dw XT_GRESOLVE
-0007b7 3820 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-0007b8 0005 .dw $0005
-0007b9 6562
-0007ba 6967
-0007bb 006e .db "begin",0
-0007bc 07b1 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-0007bd 3801 .dw DO_COLON
- PFA_BEGIN:
- .endif
-0007be 078d .dw XT_LMARK
-0007bf 3820 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-0007c0 0005 .dw $0005
-0007c1 6877
-0007c2 6c69
-0007c3 0065 .db "while",0
-0007c4 07b8 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-0007c5 3801 .dw DO_COLON
- PFA_WHILE:
- .endif
-0007c6 07a1 .dw XT_IF
-0007c7 38c4 .dw XT_SWAP
-0007c8 3820 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-0007c9 0006 .dw $0006
-0007ca 6572
-0007cb 6570
-0007cc 7461 .db "repeat"
-0007cd 07c0 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-0007ce 3801 .dw DO_COLON
- PFA_REPEAT:
- .endif
-0007cf 07e2 .dw XT_AGAIN
-0007d0 07b5 .dw XT_THEN
-0007d1 3820 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-0007d2 0005 .dw $0005
-0007d3 6e75
-0007d4 6974
-0007d5 006c .db "until",0
-0007d6 07c9 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-0007d7 3801 .dw DO_COLON
- PFA_UNTIL:
- .endif
-0007d8 383d .dw XT_DOLITERAL
-0007d9 3836 .dw XT_DOCONDBRANCH
-0007da 075c .dw XT_COMMA
-
-0007db 0790 .dw XT_LRESOLVE
-0007dc 3820 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-0007dd 0005 .dw $0005
-0007de 6761
-0007df 6961
-0007e0 006e .db "again",0
-0007e1 07d2 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-0007e2 3801 .dw DO_COLON
- PFA_AGAIN:
- .endif
-0007e3 0751 .dw XT_COMPILE
-0007e4 382f .dw XT_DOBRANCH
-0007e5 0790 .dw XT_LRESOLVE
-0007e6 3820 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-0007e7 0002 .dw $0002
-0007e8 6f64 .db "do"
-0007e9 07dd .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-0007ea 3801 .dw DO_COLON
- PFA_DO:
-
- .endif
-0007eb 0751 .dw XT_COMPILE
-0007ec 3a9b .dw XT_DODO
-0007ed 078d .dw XT_LMARK
-0007ee 3954 .dw XT_ZERO
-0007ef 0845 .dw XT_TO_L
-0007f0 3820 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-0007f1 0004 .dw $0004
-0007f2 6f6c
-0007f3 706f .db "loop"
-0007f4 07e7 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-0007f5 3801 .dw DO_COLON
- PFA_LOOP:
- .endif
-0007f6 0751 .dw XT_COMPILE
-0007f7 3ac9 .dw XT_DOLOOP
-0007f8 082c .dw XT_ENDLOOP
-0007f9 3820 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-0007fa 0005 .dw $0005
-0007fb 6c2b
-0007fc 6f6f
-0007fd 0070 .db "+loop",0
-0007fe 07f1 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-0007ff 3801 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-000800 0751 .dw XT_COMPILE
-000801 3aba .dw XT_DOPLUSLOOP
-000802 082c .dw XT_ENDLOOP
-000803 3820 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-000804 0005 .dw $0005
-000805 656c
-000806 7661
-000807 0065 .db "leave",0
-000808 07fa .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-000809 3801 .dw DO_COLON
- PFA_LEAVE:
- .endif
-00080a 0751
-00080b 3ad4 .DW XT_COMPILE,XT_UNLOOP
-00080c 0799
-00080d 0845
-00080e 3820 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-00080f 0003 .dw $0003
-000810 643f
-000811 006f .db "?do",0
-000812 0804 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000813 3801 .dw DO_COLON
- PFA_QDO:
- .endif
-000814 0751 .dw XT_COMPILE
-000815 081b .dw XT_QDOCHECK
-000816 07a1 .dw XT_IF
-000817 07ea .dw XT_DO
-000818 38c4 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-000819 0845 .dw XT_TO_L ; then follows at the end.
-00081a 3820 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00081b 3801 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00081c 3ec9 .dw XT_2DUP
-00081d 3fdf .dw XT_EQUAL
-00081e 38b1 .dw XT_DUP
-00081f 38ff .dw XT_TO_R
-000820 3836 .dw XT_DOCONDBRANCH
-000821 0823 DEST(PFA_QDOCHECK1)
-000822 3ed2 .dw XT_2DROP
- PFA_QDOCHECK1:
-000823 38f6 .dw XT_R_FROM
-000824 39fd .dw XT_INVERT
-000825 3820 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000826 ff07 .dw $ff07
-000827 6e65
-000828 6c64
-000829 6f6f
-00082a 0070 .db "endloop",0
-00082b 080f .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-00082c 3801 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-00082d 0790 .DW XT_LRESOLVE
-00082e 0839
-00082f 38b9
-000830 3836 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-000831 0835 DEST(LOOP2)
-000832 07b5 .DW XT_THEN
-000833 382f .dw XT_DOBRANCH
-000834 082e DEST(LOOP1)
-000835 3820 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000836 ff02 .dw $ff02
-000837 3e6c .db "l>"
-000838 0826 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-000839 3801 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-00083a 0858 .dw XT_LP
-00083b 3879 .dw XT_FETCH
-00083c 3879 .dw XT_FETCH
-00083d 383d .dw XT_DOLITERAL
-00083e fffe .dw -2
-00083f 0858 .dw XT_LP
-000840 3a65 .dw XT_PLUSSTORE
-000841 3820 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-000842 ff02 .dw $ff02
-000843 6c3e .db ">l"
-000844 0836 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000845 3801 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000846 3feb .dw XT_TWO
-000847 0858 .dw XT_LP
-000848 3a65 .dw XT_PLUSSTORE
-000849 0858 .dw XT_LP
-00084a 3879 .dw XT_FETCH
-00084b 3881 .dw XT_STORE
-00084c 3820 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-00084d ff03 .dw $ff03
-00084e 706c
-00084f 0030 .db "lp0",0
-000850 0842 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-000851 386f .dw PFA_DOVALUE1
- PFA_LP0:
-000852 0036 .dw CFG_LP0
-000853 3da0 .dw XT_EDEFERFETCH
-000854 3daa .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-000855 ff02 .dw $ff02
-000856 706c .db "lp"
-000857 084d .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-000858 3848 .dw PFA_DOVARIABLE
- PFA_LP:
-000859 00eb .dw ram_lp
-
- .dseg
-0000eb ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-00085a ff06 .dw $ff06
-00085b 7263
-00085c 6165
-00085d 6574 .db "create"
-00085e 0855 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-00085f 3801 .dw DO_COLON
- PFA_CREATE:
- .endif
-000860 072e .dw XT_DOCREATE
-000861 088e .dw XT_REVEAL
-000862 0751 .dw XT_COMPILE
-000863 3852 .dw PFA_DOCONSTANT
-000864 3820 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-000865 ff06 .dw $ff06
-000866 6568
-000867 6461
-000868 7265 .db "header"
-000869 085a .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-00086a 3801 .dw DO_COLON
- PFA_HEADER:
-00086b 3f12 .dw XT_DP ; the new Name Field
-00086c 38ff .dw XT_TO_R
-00086d 38ff .dw XT_TO_R ; ( R: NFA WID )
-00086e 38b1 .dw XT_DUP
-00086f 3928 .dw XT_GREATERZERO
-000870 3836 .dw XT_DOCONDBRANCH
-000871 087c .dw PFA_HEADER1
-000872 38b1 .dw XT_DUP
-000873 383d .dw XT_DOLITERAL
-000874 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-000875 3a1c .dw XT_OR
-000876 03d7 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-000877 38f6 .dw XT_R_FROM
-000878 3b5f .dw XT_FETCHE
-000879 075c .dw XT_COMMA
-00087a 38f6 .dw XT_R_FROM
-00087b 3820 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-00087c 383d .dw XT_DOLITERAL
-00087d fff0 .dw -16
-00087e 3d86 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-00087f ff07 .dw $ff07
-000880 6c77
-000881 6373
-000882 706f
-000883 0065 .db "wlscope",0
-000884 0865 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000885 3dff .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000886 0032 .dw CFG_WLSCOPE
-000887 3da0 .dw XT_EDEFERFETCH
-000888 3daa .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000889 ff06 .dw $ff06
-00088a 6572
-00088b 6576
-00088c 6c61 .db "reveal"
-00088d 087f .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-00088e 3801 .dw DO_COLON
- PFA_REVEAL:
- .endif
-00088f 071f
-000890 3c90
-000891 3879 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-000892 38b9
-000893 3836 .DW XT_QDUP,XT_DOCONDBRANCH
-000894 0899 DEST(REVEAL1)
-000895 071f
-000896 3879
-000897 38c4
-000898 3b3b .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-000899 3820 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-00089a 0005 .dw $0005
-00089b 6f64
-00089c 7365
-00089d 003e .db "does>",0
-00089e 0889 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-00089f 3801 .dw DO_COLON
- PFA_DOES:
-0008a0 0751 .dw XT_COMPILE
-0008a1 08b2 .dw XT_DODOES
-0008a2 0751 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-0008a3 940e .dw $940e ; the address of this compiled
-0008a4 0751 .dw XT_COMPILE ; code will replace the XT of the
-0008a5 08a7 .dw DO_DODOES ; word that CREATE created
-0008a6 3820 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-0008a7 939a
-0008a8 938a savetos
-0008a9 01cb movw tosl, wl
-0008aa 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-0008ab 917f pop wh
-0008ac 916f pop wl
-
-0008ad 93bf push XH
-0008ae 93af push XL
-0008af 01db movw XL, wl
-0008b0 940c 3805 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-0008b2 3801 .dw DO_COLON
- PFA_DODOES:
-0008b3 38f6 .dw XT_R_FROM
-0008b4 071f .dw XT_NEWEST
-0008b5 3c90 .dw XT_CELLPLUS
-0008b6 3879 .dw XT_FETCH
-0008b7 3b5f .dw XT_FETCHE
-0008b8 06f6 .dw XT_NFA2CFA
-0008b9 3b73 .dw XT_STOREI
-0008ba 3820 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-0008bb ff01 .dw $ff01
-0008bc 003a .db ":",0
-0008bd 089a .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-0008be 3801 .dw DO_COLON
- PFA_COLON:
- .endif
-0008bf 072e .dw XT_DOCREATE
-0008c0 08c9 .dw XT_COLONNONAME
-0008c1 38d9 .dw XT_DROP
-0008c2 3820 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-0008c3 ff07 .dw $ff07
-0008c4 6e3a
-0008c5 6e6f
-0008c6 6d61
-0008c7 0065 .db ":noname",0
-0008c8 08bb .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-0008c9 3801 .dw DO_COLON
- PFA_COLONNONAME:
-0008ca 3f12 .dw XT_DP
-0008cb 38b1 .dw XT_DUP
-0008cc 0726 .dw XT_LATEST
-0008cd 3881 .dw XT_STORE
-
-0008ce 0751 .dw XT_COMPILE
-0008cf 3801 .dw DO_COLON
-
-0008d0 08de .dw XT_RBRACKET
-0008d1 3820 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-0008d2 0001 .dw $0001
-0008d3 003b .db $3b,0
-0008d4 08c3 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-0008d5 3801 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-0008d6 0751 .dw XT_COMPILE
-0008d7 3820 .dw XT_EXIT
-0008d8 08e6 .dw XT_LBRACKET
-0008d9 088e .dw XT_REVEAL
-0008da 3820 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-0008db ff01 .dw $ff01
-0008dc 005d .db "]",0
-0008dd 08d2 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-0008de 3801 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-0008df 3fe6 .dw XT_ONE
-0008e0 3eb7 .dw XT_STATE
-0008e1 3881 .dw XT_STORE
-0008e2 3820 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-0008e3 0001 .dw $0001
-0008e4 005b .db "[",0
-0008e5 08db .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-0008e6 3801 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-0008e7 3954 .dw XT_ZERO
-0008e8 3eb7 .dw XT_STATE
-0008e9 3881 .dw XT_STORE
-0008ea 3820 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-0008eb ff08 .dw $ff08
-0008ec 6176
-0008ed 6972
-0008ee 6261
-0008ef 656c .db "variable"
-0008f0 08e3 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-0008f1 3801 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-0008f2 3f23 .dw XT_HERE
-0008f3 08fd .dw XT_CONSTANT
-0008f4 3feb .dw XT_TWO
-0008f5 3f2c .dw XT_ALLOT
-0008f6 3820 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-0008f7 ff08 .dw $ff08
-0008f8 6f63
-0008f9 736e
-0008fa 6174
-0008fb 746e .db "constant"
-0008fc 08eb .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-0008fd 3801 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-0008fe 072e .dw XT_DOCREATE
-0008ff 088e .dw XT_REVEAL
-000900 0751 .dw XT_COMPILE
-000901 3848 .dw PFA_DOVARIABLE
-000902 075c .dw XT_COMMA
-000903 3820 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-000904 ff04 .dw $ff04
-000905 7375
-000906 7265 .db "user"
-000907 08f7 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-000908 3801 .dw DO_COLON
- PFA_USER:
-000909 072e .dw XT_DOCREATE
-00090a 088e .dw XT_REVEAL
-
-00090b 0751 .dw XT_COMPILE
-00090c 3858 .dw PFA_DOUSER
-00090d 075c .dw XT_COMMA
-00090e 3820 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-00090f 0007 .dw $0007
-000910 6572
-000911 7563
-000912 7372
-000913 0065 .db "recurse",0
-000914 0904 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000915 3801 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000916 0726 .dw XT_LATEST
-000917 3879 .dw XT_FETCH
-000918 075c .dw XT_COMMA
-000919 3820 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-00091a ff09 .dw $ff09
-00091b 6d69
-00091c 656d
-00091d 6964
-00091e 7461
-00091f 0065 .db "immediate",0
-000920 090f .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-000921 3801 .dw DO_COLON
- PFA_IMMEDIATE:
-000922 09c3 .dw XT_GET_CURRENT
-000923 3b5f .dw XT_FETCHE
-000924 38b1 .dw XT_DUP
-000925 3bcb .dw XT_FETCHI
-000926 383d .dw XT_DOLITERAL
-000927 7fff .dw $7fff
-000928 3a13 .dw XT_AND
-000929 38c4 .dw XT_SWAP
-00092a 3b73 .dw XT_STOREI
-00092b 3820 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-00092c 0006 .dw $0006
-00092d 635b
-00092e 6168
-00092f 5d72 .db "[char]"
-000930 091a .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-000931 3801 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-000932 0751 .dw XT_COMPILE
-000933 383d .dw XT_DOLITERAL
-000934 04e6 .dw XT_CHAR
-000935 075c .dw XT_COMMA
-000936 3820 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-000937 0006 .dw $0006
-000938 6261
-000939 726f
-00093a 2274 .db "abort",'"'
-00093b 092c .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-00093c 3801 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-00093d 3e8a .dw XT_SQUOTE
-00093e 0751 .dw XT_COMPILE
-00093f 094e .dw XT_QABORT
-000940 3820 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-000941 ff05 .dw $ff05
-000942 6261
-000943 726f
-000944 0074 .db "abort",0
-000945 0937 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000946 3801 .dw DO_COLON
- PFA_ABORT:
- .endif
-000947 394b .dw XT_TRUE
-000948 3d86 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-000949 ff06 .dw $ff06
-00094a 613f
-00094b 6f62
-00094c 7472 .db "?abort"
-00094d 0941 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-00094e 3801 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-00094f 38e1
-000950 3836 .DW XT_ROT,XT_DOCONDBRANCH
-000951 0954 DEST(QABO1)
-000952 03f8
-000953 0946 .DW XT_ITYPE,XT_ABORT
-000954 3ed2
-000955 3820 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000956 ff09 .dw $ff09
-000957 6567
-000958 2d74
-000959 7473
-00095a 6361
-00095b 006b .db "get-stack",0
-00095c 0949 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-00095d 3801 .dw DO_COLON
- .endif
-00095e 38b1 .dw XT_DUP
-00095f 3c90 .dw XT_CELLPLUS
-000960 38c4 .dw XT_SWAP
-000961 3b5f .dw XT_FETCHE
-000962 38b1 .dw XT_DUP
-000963 38ff .dw XT_TO_R
-000964 3954 .dw XT_ZERO
-000965 38c4 .dw XT_SWAP ; go from bigger to smaller addresses
-000966 081b .dw XT_QDOCHECK
-000967 3836 .dw XT_DOCONDBRANCH
-000968 0974 DEST(PFA_N_FETCH_E2)
-000969 3a9b .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-00096a 3aac .dw XT_I
-00096b 3a35 .dw XT_1MINUS
-00096c 3ec4 .dw XT_CELLS ; ( -- ee-addr i*2 )
-00096d 38cf .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-00096e 399d .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-00096f 3b5f .dw XT_FETCHE ;( -- ee-addr item_i )
-000970 38c4 .dw XT_SWAP ;( -- item_i ee-addr )
-000971 394b .dw XT_TRUE ; shortcut for -1
-000972 3aba .dw XT_DOPLUSLOOP
-000973 096a DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-000974 3ed2 .dw XT_2DROP
-000975 38f6 .dw XT_R_FROM
-000976 3820 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-000977 ff09 .dw $ff09
-000978 6573
-000979 2d74
-00097a 7473
-00097b 6361
-00097c 006b .db "set-stack",0
-00097d 0956 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-00097e 3801 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-00097f 38cf .dw XT_OVER
-000980 3921 .dw XT_ZEROLESS
-000981 3836 .dw XT_DOCONDBRANCH
-000982 0986 DEST(PFA_SET_STACK0)
-000983 383d .dw XT_DOLITERAL
-000984 fffc .dw -4
-000985 3d86 .dw XT_THROW
- PFA_SET_STACK0:
-000986 3ec9 .dw XT_2DUP
-000987 3b3b .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000988 38c4 .dw XT_SWAP
-000989 3954 .dw XT_ZERO
-00098a 081b .dw XT_QDOCHECK
-00098b 3836 .dw XT_DOCONDBRANCH
-00098c 0993 DEST(PFA_SET_STACK2)
-00098d 3a9b .dw XT_DODO
- PFA_SET_STACK1:
-00098e 3c90 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-00098f 3eda .dw XT_TUCK ; ( -- e-addr i_x e-addr
-000990 3b3b .dw XT_STOREE
-000991 3ac9 .dw XT_DOLOOP
-000992 098e DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-000993 38d9 .dw XT_DROP
-000994 3820 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-000995 ff09 .dw $ff09
-000996 616d
-000997 2d70
-000998 7473
-000999 6361
-00099a 006b .db "map-stack",0
-00099b 0977 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-00099c 3801 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-00099d 38b1 .dw XT_DUP
-00099e 3c90 .dw XT_CELLPLUS
-00099f 38c4 .dw XT_SWAP
-0009a0 3b5f .dw XT_FETCHE
-0009a1 3ec4 .dw XT_CELLS
-0009a2 3f99 .dw XT_BOUNDS
-0009a3 081b .dw XT_QDOCHECK
-0009a4 3836 .dw XT_DOCONDBRANCH
-0009a5 09b8 DEST(PFA_MAPSTACK3)
-0009a6 3a9b .dw XT_DODO
- PFA_MAPSTACK1:
-0009a7 3aac .dw XT_I
-0009a8 3b5f .dw XT_FETCHE ; -- i*x XT id
-0009a9 38c4 .dw XT_SWAP
-0009aa 38ff .dw XT_TO_R
-0009ab 3908 .dw XT_R_FETCH
-0009ac 382a .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-0009ad 38b9 .dw XT_QDUP
-0009ae 3836 .dw XT_DOCONDBRANCH
-0009af 09b4 DEST(PFA_MAPSTACK2)
-0009b0 38f6 .dw XT_R_FROM
-0009b1 38d9 .dw XT_DROP
-0009b2 3ad4 .dw XT_UNLOOP
-0009b3 3820 .dw XT_EXIT
- PFA_MAPSTACK2:
-0009b4 38f6 .dw XT_R_FROM
-0009b5 3feb .dw XT_TWO
-0009b6 3aba .dw XT_DOPLUSLOOP
-0009b7 09a7 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-0009b8 38d9 .dw XT_DROP
-0009b9 3954 .dw XT_ZERO
-0009ba 3820 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-0009bb ff0b .dw $ff0b
-0009bc 6567
-0009bd 2d74
-0009be 7563
-0009bf 7272
-0009c0 6e65
-0009c1 0074 .db "get-current",0
-0009c2 0995 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-0009c3 3801 .dw DO_COLON
- PFA_GET_CURRENT:
-0009c4 383d .dw XT_DOLITERAL
-0009c5 003c .dw CFG_CURRENT
-0009c6 3b5f .dw XT_FETCHE
-0009c7 3820 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-0009c8 ff09 .dw $ff09
-0009c9 6567
-0009ca 2d74
-0009cb 726f
-0009cc 6564
-0009cd 0072 .db "get-order",0
-0009ce 09bb .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-0009cf 3801 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-0009d0 383d .dw XT_DOLITERAL
-0009d1 0040 .dw CFG_ORDERLISTLEN
-0009d2 095d .dw XT_GET_STACK
-0009d3 3820 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-0009d4 ff09 .dw $ff09
-0009d5 6663
-0009d6 2d67
-0009d7 726f
-0009d8 6564
-0009d9 0072 .db "cfg-order",0
-0009da 09c8 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-0009db 3848 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-0009dc 0040 .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-0009dd ff07 .dw $ff07
-0009de 6f63
-0009df 706d
-0009e0 7261
-0009e1 0065 .db "compare",0
-0009e2 09d4 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-0009e3 09e4 .dw PFA_COMPARE
- PFA_COMPARE:
-0009e4 93bf push xh
-0009e5 93af push xl
-0009e6 018c movw temp0, tosl
-0009e7 9189
-0009e8 9199 loadtos
-0009e9 01dc movw xl, tosl
-0009ea 9189
-0009eb 9199 loadtos
-0009ec 019c movw temp2, tosl
-0009ed 9189
-0009ee 9199 loadtos
-0009ef 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-0009f0 90ed ld temp4, X+
-0009f1 90f1 ld temp5, Z+
-0009f2 14ef cp temp4, temp5
-0009f3 f451 brne PFA_COMPARE_NOTEQUAL
-0009f4 950a dec temp0
-0009f5 f019 breq PFA_COMPARE_ENDREACHED2
-0009f6 952a dec temp2
-0009f7 f7c1 brne PFA_COMPARE_LOOP
-0009f8 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-0009f9 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-0009fa 2b02 or temp0, temp2
-0009fb f411 brne PFA_COMPARE_CHECKLASTCHAR
-0009fc 2788 clr tosl
-0009fd c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-0009fe ef8f ser tosl
-0009ff c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000a00 2f98 mov tosh, tosl
-000a01 91af pop xl
-000a02 91bf pop xh
-000a03 940c 3805 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000a05 ff07 .dw $ff07
-000a06 666e
-000a07 3e61
-000a08 666c
-000a09 0061 .db "nfa>lfa",0
-000a0a 09dd .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-000a0b 3801 .dw DO_COLON
- PFA_NFA2LFA:
-000a0c 06ea .dw XT_NAME2STRING
-000a0d 3a2f .dw XT_1PLUS
-000a0e 3a04 .dw XT_2SLASH
-000a0f 399d .dw XT_PLUS
-000a10 3820 .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
- .include "words/dot-s.asm"
-
- ; Tools
- ; stack dump
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTS:
-000a11 ff02 .dw $ff02
-000a12 732e .db ".s"
-000a13 0a05 .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
- XT_DOTS:
-000a14 3801 .dw DO_COLON
- PFA_DOTS:
- .endif
-000a15 05e2 .dw XT_DEPTH
-000a16 3e0a .dw XT_UDOT
-000a17 3fae .dw XT_SPACE
-000a18 05e2 .dw XT_DEPTH
-000a19 3954 .dw XT_ZERO
-000a1a 081b .dw XT_QDOCHECK
-000a1b 3836 .dw XT_DOCONDBRANCH
-000a1c 0a23 DEST(PFA_DOTS2)
-000a1d 3a9b .dw XT_DODO
- PFA_DOTS1:
-000a1e 3aac .dw XT_I
-000a1f 3c84 .dw XT_PICK
-000a20 3e0a .dw XT_UDOT
-000a21 3ac9 .dw XT_DOLOOP
-000a22 0a1e DEST(PFA_DOTS1)
- PFA_DOTS2:
-000a23 3820 .dw XT_EXIT
- .include "words/spirw.asm"
-
- ; MCU
- ; SPI exchange of 1 byte
- VE_SPIRW:
-000a24 ff06 .dw $ff06
-000a25 2163
-000a26 7340
-000a27 6970 .db "c!@spi"
-000a28 0a11 .dw VE_HEAD
- .set VE_HEAD = VE_SPIRW
- XT_SPIRW:
-000a29 0a2a .dw PFA_SPIRW
- PFA_SPIRW:
-000a2a d003 rcall do_spirw
-000a2b 2799 clr tosh
-000a2c 940c 3805 jmp_ DO_NEXT
-
- do_spirw:
-000a2e b98f out_ SPDR, tosl
- do_spirw1:
-000a2f b10e in_ temp0, SPSR
-000a30 7f08 cbr temp0,7
-000a31 b90e out_ SPSR, temp0
-000a32 b10e in_ temp0, SPSR
-000a33 ff07 sbrs temp0, 7
-000a34 cffa rjmp do_spirw1 ; wait until complete
-000a35 b18f in_ tosl, SPDR
-000a36 9508 ret
- .include "words/n-spi.asm"
-
- ; MCU
- ; read len bytes from SPI to addr
- VE_N_SPIR:
-000a37 ff05 .dw $ff05
-000a38 406e
-000a39 7073
-000a3a 0069 .db "n@spi",0
-000a3b 0a24 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIR
- XT_N_SPIR:
-000a3c 0a3d .dw PFA_N_SPIR
- PFA_N_SPIR:
-000a3d 018c movw temp0, tosl
-000a3e 9189
-000a3f 9199 loadtos
-000a40 01fc movw zl, tosl
-000a41 01c8 movw tosl, temp0
- PFA_N_SPIR_LOOP:
-000a42 b82f out_ SPDR, zerol
- PFA_N_SPIR_LOOP1:
-000a43 b12e in_ temp2, SPSR
-000a44 ff27 sbrs temp2, SPIF
-000a45 cffd rjmp PFA_N_SPIR_LOOP1
-000a46 b12f in_ temp2, SPDR
-000a47 9321 st Z+, temp2
-000a48 9701 sbiw tosl, 1
-000a49 f7c1 brne PFA_N_SPIR_LOOP
-000a4a 9189
-000a4b 9199 loadtos
-000a4c 940c 3805 jmp_ DO_NEXT
-
- ; ( addr len -- )
- ; MCU
- ; write len bytes to SPI from addr
- VE_N_SPIW:
-000a4e ff05 .dw $ff05
-000a4f 216e
-000a50 7073
-000a51 0069 .db "n!spi",0
-000a52 0a37 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIW
- XT_N_SPIW:
-000a53 0a54 .dw PFA_N_SPIW
- PFA_N_SPIW:
-000a54 018c movw temp0, tosl
-000a55 9189
-000a56 9199 loadtos
-000a57 01fc movw zl, tosl
-000a58 01c8 movw tosl, temp0
- PFA_N_SPIW_LOOP:
-000a59 9121 ld temp2, Z+
-000a5a b92f out_ SPDR, temp2
- PFA_N_SPIW_LOOP1:
-000a5b b12e in_ temp2, SPSR
-000a5c ff27 sbrs temp2, SPIF
-000a5d cffd rjmp PFA_N_SPIW_LOOP1
-000a5e b12f in_ temp2, SPDR ; ignore the data
-000a5f 9701 sbiw tosl, 1
-000a60 f7c1 brne PFA_N_SPIW_LOOP
-000a61 9189
-000a62 9199 loadtos
-000a63 940c 3805 jmp_ DO_NEXT
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000a65 ff0b .dw $ff0b
-000a66 7061
-000a67 6c70
-000a68 7574
-000a69 6e72
-000a6a 656b
-000a6b 0079 .db "applturnkey",0
-000a6c 0a4e .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000a6d 3801 .dw DO_COLON
- PFA_APPLTURNKEY:
-000a6e 00bc .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-000a6f 3c97 .dw XT_INTON
- .endif
-000a70 017f .dw XT_DOT_VER
-000a71 3fae .dw XT_SPACE
-000a72 3eac .dw XT_F_CPU
-000a73 383d .dw XT_DOLITERAL
-000a74 03e8 .dw 1000
-000a75 39c2 .dw XT_UMSLASHMOD
-000a76 38f0 .dw XT_NIP
-000a77 3f41 .dw XT_DECIMAL
-000a78 037a .dw XT_DOT
-000a79 03c5 .dw XT_DOSLITERAL
-000a7a 0004 .dw 4
-000a7b 486b
-000a7c 207a .db "kHz "
-000a7d 03f8 .dw XT_ITYPE
-000a7e 3820 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-000a7f ff0b .dw $ff0b
-000a80 6573
-000a81 2d74
-000a82 7563
-000a83 7272
-000a84 6e65
-000a85 0074 .db "set-current",0
-000a86 0a65 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-000a87 3801 .dw DO_COLON
- PFA_SET_CURRENT:
-000a88 383d .dw XT_DOLITERAL
-000a89 003c .dw CFG_CURRENT
-000a8a 3b3b .dw XT_STOREE
-000a8b 3820 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-000a8c ff08 .dw $ff08
-000a8d 6f77
-000a8e 6472
-000a8f 696c
-000a90 7473 .db "wordlist"
-000a91 0a7f .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000a92 3801 .dw DO_COLON
- PFA_WORDLIST:
-000a93 3f1b .dw XT_EHERE
-000a94 3954 .dw XT_ZERO
-000a95 38cf .dw XT_OVER
-000a96 3b3b .dw XT_STOREE
-000a97 38b1 .dw XT_DUP
-000a98 3c90 .dw XT_CELLPLUS
-000a99 01b4 .dw XT_DOTO
-000a9a 3f1c .dw PFA_EHERE
-000a9b 3820 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-000a9c ff0e .dw $ff0e
-000a9d 6f66
-000a9e 7472
-000a9f 2d68
-000aa0 6f77
-000aa1 6472
-000aa2 696c
-000aa3 7473 .db "forth-wordlist"
-000aa4 0a8c .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000aa5 3848 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000aa6 003e .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000aa7 ff09 .dw $ff09
-000aa8 6573
-000aa9 2d74
-000aaa 726f
-000aab 6564
-000aac 0072 .db "set-order",0
-000aad 0a9c .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000aae 3801 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000aaf 383d .dw XT_DOLITERAL
-000ab0 0040 .dw CFG_ORDERLISTLEN
-000ab1 097e .dw XT_SET_STACK
-000ab2 3820 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000ab3 ff0f .dw $ff0f
-000ab4 6573
-000ab5 2d74
-000ab6 6572
-000ab7 6f63
-000ab8 6e67
-000ab9 7a69
-000aba 7265
-000abb 0073 .db "set-recognizers",0
-000abc 0aa7 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000abd 3801 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000abe 383d .dw XT_DOLITERAL
-000abf 0052 .dw CFG_RECOGNIZERLISTLEN
-000ac0 097e .dw XT_SET_STACK
-000ac1 3820 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000ac2 ff0f .dw $ff0f
-000ac3 6567
-000ac4 2d74
-000ac5 6572
-000ac6 6f63
-000ac7 6e67
-000ac8 7a69
-000ac9 7265
-000aca 0073 .db "get-recognizers",0
-000acb 0ab3 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000acc 3801 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000acd 383d .dw XT_DOLITERAL
-000ace 0052 .dw CFG_RECOGNIZERLISTLEN
-000acf 095d .dw XT_GET_STACK
-000ad0 3820 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000ad1 ff04 .dw $ff04
-000ad2 6f63
-000ad3 6564 .db "code"
-000ad4 0ac2 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000ad5 3801 .dw DO_COLON
- PFA_CODE:
-000ad6 072e .dw XT_DOCREATE
-000ad7 088e .dw XT_REVEAL
-000ad8 3f12 .dw XT_DP
-000ad9 01c6 .dw XT_ICELLPLUS
-000ada 075c .dw XT_COMMA
-000adb 3820 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000adc ff08 .dw $ff08
-000add 6e65
-000ade 2d64
-000adf 6f63
-000ae0 6564 .db "end-code"
-000ae1 0ad1 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000ae2 3801 .dw DO_COLON
- PFA_ENDCODE:
-000ae3 0751 .dw XT_COMPILE
-000ae4 940c .dw $940c
-000ae5 0751 .dw XT_COMPILE
-000ae6 3805 .dw DO_NEXT
-000ae7 3820 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000ae8 ff08 .dw $ff08
-000ae9 6d28
-000aea 7261
-000aeb 656b
-000aec 2972 .db "(marker)"
-000aed 0adc .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-000aee 386f .dw PFA_DOVALUE1
- PFA_MARKER:
-000aef 005e .dw EE_MARKER
-000af0 3da0 .dw XT_EDEFERFETCH
-000af1 3daa .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000af2 0008 .dw $0008
-000af3 6f70
-000af4 7473
-000af5 6f70
-000af6 656e .db "postpone"
-000af7 0ae8 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000af8 3801 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000af9 05b0 .dw XT_PARSENAME
-000afa 05f3 .dw XT_FORTHRECOGNIZER
-000afb 05fe .dw XT_RECOGNIZE
-000afc 38b1 .dw XT_DUP
-000afd 38ff .dw XT_TO_R
-000afe 01c6 .dw XT_ICELLPLUS
-000aff 01c6 .dw XT_ICELLPLUS
-000b00 3bcb .dw XT_FETCHI
-000b01 382a .dw XT_EXECUTE
-000b02 38f6 .dw XT_R_FROM
-000b03 01c6 .dw XT_ICELLPLUS
-000b04 3bcb .dw XT_FETCHI
-000b05 075c .dw XT_COMMA
-000b06 3820 .dw XT_EXIT
- .endif
- .include "words/2r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_2R_FETCH:
-000b07 ff03 .dw $ff03
-000b08 7232
-000b09 0040 .db "2r@",0
-000b0a 0af2 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FETCH
- XT_2R_FETCH:
-000b0b 0b0c .dw PFA_2R_FETCH
- PFA_2R_FETCH:
-000b0c 939a
-000b0d 938a savetos
-000b0e 91ef pop zl
-000b0f 91ff pop zh
-000b10 918f pop tosl
-000b11 919f pop tosh
-000b12 939f push tosh
-000b13 938f push tosl
-000b14 93ff push zh
-000b15 93ef push zl
-000b16 939a
-000b17 938a savetos
-000b18 01cf movw tosl, zl
-000b19 940c 3805 jmp_ DO_NEXT
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-003801 93bf push XH
-003802 93af push XL ; PUSH IP
-003803 01db movw XL, wl
-003804 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-003805 14b2 cp isrflag, zerol
-003806 f469 brne DO_INTERRUPT
- .endif
-003807 01fd movw zl, XL ; READ IP
-003808 0fee
-003809 1fff
-00380a 9165
-00380b 9175 readflashcell wl, wh
-00380c 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00380d 01fb movw zl, wl
-00380e 0fee
-00380f 1fff
-003810 9105
-003811 9115 readflashcell temp0,temp1
-003812 01f8 movw zl, temp0
-003813 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-003814 939a
-003815 938a savetos
-003816 2d8b mov tosl, isrflag
-003817 2799 clr tosh
-003818 24bb clr isrflag
-003819 ec60 ldi wl, LOW(XT_ISREXEC)
-00381a e37c ldi wh, HIGH(XT_ISREXEC)
-00381b cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00381c ff04 .dw $ff04
-00381d 7865
-00381e 7469 .db "exit"
-00381f 0b07 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-003820 3821 .dw PFA_EXIT
- PFA_EXIT:
-003821 91af pop XL
-003822 91bf pop XH
-003823 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-003824 ff07 .dw $ff07
-003825 7865
-003826 6365
-003827 7475
-003828 0065 .db "execute",0
-003829 381c .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-00382a 382b .dw PFA_EXECUTE
- PFA_EXECUTE:
-00382b 01bc movw wl, tosl
-00382c 9189
-00382d 9199 loadtos
-00382e cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00382f 3830 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-003830 01fd movw zl, XL
-003831 0fee
-003832 1fff
-003833 91a5
-003834 91b5 readflashcell XL,XH
-003835 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-003836 3837 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-003837 2b98 or tosh, tosl
-003838 9189
-003839 9199 loadtos
-00383a f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00383b 9611 adiw XL, 1
-00383c cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00383d 383e .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00383e 939a
-00383f 938a savetos
-003840 01fd movw zl, xl
-003841 0fee
-003842 1fff
-003843 9185
-003844 9195 readflashcell tosl,tosh
-003845 9611 adiw xl, 1
-003846 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-003847 3848 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-003848 939a
-003849 938a savetos
-00384a 01fb movw zl, wl
-00384b 9631 adiw zl,1
-00384c 0fee
-00384d 1fff
-00384e 9185
-00384f 9195 readflashcell tosl,tosh
-003850 cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-003851 3852 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-003852 939a
-003853 938a savetos
-003854 01cb movw tosl, wl
-003855 9601 adiw tosl, 1
-003856 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-003857 3858 .dw PFA_DOUSER
- PFA_DOUSER:
-003858 939a
-003859 938a savetos
-00385a 01fb movw zl, wl
-00385b 9631 adiw zl, 1
-00385c 0fee
-00385d 1fff
-00385e 9185
-00385f 9195 readflashcell tosl,tosh
-003860 0d84 add tosl, upl
-003861 1d95 adc tosh, uph
-003862 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-003863 ff07 .dw $ff07
-003864 7628
-003865 6c61
-003866 6575
-003867 0029 .db "(value)", 0
-003868 3824 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-003869 3801 .dw DO_COLON
- PFA_DOVALUE:
-00386a 072e .dw XT_DOCREATE
-00386b 088e .dw XT_REVEAL
-00386c 0751 .dw XT_COMPILE
-00386d 386f .dw PFA_DOVALUE1
-00386e 3820 .dw XT_EXIT
- PFA_DOVALUE1:
-00386f 940e 08a7 call_ DO_DODOES
-003871 38b1 .dw XT_DUP
-003872 01c6 .dw XT_ICELLPLUS
-003873 3bcb .dw XT_FETCHI
-003874 382a .dw XT_EXECUTE
-003875 3820 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-003876 ff01 .dw $ff01
-003877 0040 .db "@",0
-003878 3863 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-003879 387a .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-00387a 01fc movw zl, tosl
- ; low byte is read before the high byte
-00387b 9181 ld tosl, z+
-00387c 9191 ld tosh, z+
-00387d cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00387e ff01 .dw $ff01
-00387f 0021 .db "!",0
-003880 3876 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-003881 3882 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-003882 01fc movw zl, tosl
-003883 9189
-003884 9199 loadtos
- ; the high byte is written before the low byte
-003885 8391 std Z+1, tosh
-003886 8380 std Z+0, tosl
-003887 9189
-003888 9199 loadtos
-003889 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-00388a ff02 .dw $ff02
-00388b 2163 .db "c!"
-00388c 387e .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00388d 388e .dw PFA_CSTORE
- PFA_CSTORE:
-00388e 01fc movw zl, tosl
-00388f 9189
-003890 9199 loadtos
-003891 8380 st Z, tosl
-003892 9189
-003893 9199 loadtos
-003894 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-003895 ff02 .dw $ff02
-003896 4063 .db "c@"
-003897 388a .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-003898 3899 .dw PFA_CFETCH
- PFA_CFETCH:
-003899 01fc movw zl, tosl
-00389a 2799 clr tosh
-00389b 8180 ld tosl, Z
-00389c cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00389d ff02 .dw $ff02
-00389e 7540 .db "@u"
-00389f 3895 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-0038a0 3801 .dw DO_COLON
- PFA_FETCHU:
-0038a1 3b02 .dw XT_UP_FETCH
-0038a2 399d .dw XT_PLUS
-0038a3 3879 .dw XT_FETCH
-0038a4 3820 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-0038a5 ff02 .dw $ff02
-0038a6 7521 .db "!u"
-0038a7 389d .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-0038a8 3801 .dw DO_COLON
- PFA_STOREU:
-0038a9 3b02 .dw XT_UP_FETCH
-0038aa 399d .dw XT_PLUS
-0038ab 3881 .dw XT_STORE
-0038ac 3820 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-0038ad ff03 .dw $ff03
-0038ae 7564
-0038af 0070 .db "dup",0
-0038b0 38a5 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-0038b1 38b2 .dw PFA_DUP
- PFA_DUP:
-0038b2 939a
-0038b3 938a savetos
-0038b4 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-0038b5 ff04 .dw $ff04
-0038b6 643f
-0038b7 7075 .db "?dup"
-0038b8 38ad .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-0038b9 38ba .dw PFA_QDUP
- PFA_QDUP:
-0038ba 2f08 mov temp0, tosl
-0038bb 2b09 or temp0, tosh
-0038bc f011 breq PFA_QDUP1
-0038bd 939a
-0038be 938a savetos
- PFA_QDUP1:
-0038bf cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-0038c0 ff04 .dw $ff04
-0038c1 7773
-0038c2 7061 .db "swap"
-0038c3 38b5 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-0038c4 38c5 .dw PFA_SWAP
- PFA_SWAP:
-0038c5 018c movw temp0, tosl
-0038c6 9189
-0038c7 9199 loadtos
-0038c8 931a st -Y, temp1
-0038c9 930a st -Y, temp0
-0038ca cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-0038cb ff04 .dw $ff04
-0038cc 766f
-0038cd 7265 .db "over"
-0038ce 38c0 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-0038cf 38d0 .dw PFA_OVER
- PFA_OVER:
-0038d0 939a
-0038d1 938a savetos
-0038d2 818a ldd tosl, Y+2
-0038d3 819b ldd tosh, Y+3
-
-0038d4 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-0038d5 ff04 .dw $ff04
-0038d6 7264
-0038d7 706f .db "drop"
-0038d8 38cb .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-0038d9 38da .dw PFA_DROP
- PFA_DROP:
-0038da 9189
-0038db 9199 loadtos
-0038dc cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-0038dd ff03 .dw $ff03
-0038de 6f72
-0038df 0074 .db "rot",0
-0038e0 38d5 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-0038e1 38e2 .dw PFA_ROT
- PFA_ROT:
-0038e2 018c movw temp0, tosl
-0038e3 9129 ld temp2, Y+
-0038e4 9139 ld temp3, Y+
-0038e5 9189
-0038e6 9199 loadtos
-
-0038e7 933a st -Y, temp3
-0038e8 932a st -Y, temp2
-0038e9 931a st -Y, temp1
-0038ea 930a st -Y, temp0
-
-0038eb cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-0038ec ff03 .dw $ff03
-0038ed 696e
-0038ee 0070 .db "nip",0
-0038ef 38dd .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-0038f0 38f1 .dw PFA_NIP
- PFA_NIP:
-0038f1 9622 adiw yl, 2
-0038f2 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-0038f3 ff02 .dw $ff02
-0038f4 3e72 .db "r>"
-0038f5 38ec .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-0038f6 38f7 .dw PFA_R_FROM
- PFA_R_FROM:
-0038f7 939a
-0038f8 938a savetos
-0038f9 918f pop tosl
-0038fa 919f pop tosh
-0038fb cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-0038fc ff02 .dw $ff02
-0038fd 723e .db ">r"
-0038fe 38f3 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-0038ff 3900 .dw PFA_TO_R
- PFA_TO_R:
-003900 939f push tosh
-003901 938f push tosl
-003902 9189
-003903 9199 loadtos
-003904 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-003905 ff02 .dw $ff02
-003906 4072 .db "r@"
-003907 38fc .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-003908 3909 .dw PFA_R_FETCH
- PFA_R_FETCH:
-003909 939a
-00390a 938a savetos
-00390b 918f pop tosl
-00390c 919f pop tosh
-00390d 939f push tosh
-00390e 938f push tosl
-00390f cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-003910 ff02 .dw $ff02
-003911 3e3c .db "<>"
-003912 3905 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-003913 3801 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-003914 3fdf
-003915 391a
-003916 3820 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-003917 ff02 .dw $ff02
-003918 3d30 .db "0="
-003919 3910 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-00391a 391b .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00391b 2b98 or tosh, tosl
-00391c f5d1 brne PFA_ZERO1
-00391d c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00391e ff02 .dw $ff02
-00391f 3c30 .db "0<"
-003920 3917 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-003921 3922 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-003922 fd97 sbrc tosh,7
-003923 c02a rjmp PFA_TRUE1
-003924 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-003925 ff02 .dw $ff02
-003926 3e30 .db "0>"
-003927 391e .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-003928 3929 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-003929 1582 cp tosl, zerol
-00392a 0593 cpc tosh, zeroh
-00392b f15c brlt PFA_ZERO1
-00392c f151 brbs 1, PFA_ZERO1
-00392d c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00392e ff03 .dw $ff03
-00392f 3064
-003930 003e .db "d0>",0
-003931 3925 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-003932 3933 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-003933 1582 cp tosl, zerol
-003934 0593 cpc tosh, zeroh
-003935 9189
-003936 9199 loadtos
-003937 0582 cpc tosl, zerol
-003938 0593 cpc tosh, zeroh
-003939 f0ec brlt PFA_ZERO1
-00393a f0e1 brbs 1, PFA_ZERO1
-00393b c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00393c ff03 .dw $ff03
-00393d 3064
-00393e 003c .db "d0<",0
-00393f 392e .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-003940 3941 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-003941 9622 adiw Y,2
-003942 fd97 sbrc tosh,7
-003943 940c 394e jmp PFA_TRUE1
-003945 940c 3957 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-003947 ff04 .dw $ff04
-003948 7274
-003949 6575 .db "true"
-00394a 393c .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00394b 394c .dw PFA_TRUE
- PFA_TRUE:
-00394c 939a
-00394d 938a savetos
- PFA_TRUE1:
-00394e ef8f ser tosl
-00394f ef9f ser tosh
-003950 ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-003951 ff01 .dw $ff01
-003952 0030 .db "0",0
-003953 3947 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-003954 3955 .dw PFA_ZERO
- PFA_ZERO:
-003955 939a
-003956 938a savetos
- PFA_ZERO1:
-003957 01c1 movw tosl, zerol
-003958 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-003959 ff02 .dw $ff02
-00395a 3c75 .db "u<"
-00395b 3951 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00395c 395d .dw PFA_ULESS
- PFA_ULESS:
-00395d 9129 ld temp2, Y+
-00395e 9139 ld temp3, Y+
-00395f 1782 cp tosl, temp2
-003960 0793 cpc tosh, temp3
-003961 f3a8 brlo PFA_ZERO1
-003962 f3a1 brbs 1, PFA_ZERO1
-003963 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-003964 ff02 .dw $ff02
-003965 3e75 .db "u>"
-003966 3959 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-003967 3801 .dw DO_COLON
- PFA_UGREATER:
- .endif
-003968 38c4 .DW XT_SWAP
-003969 395c .dw XT_ULESS
-00396a 3820 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00396b ff01 .dw $ff01
-00396c 003c .db "<",0
-00396d 3964 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00396e 396f .dw PFA_LESS
- PFA_LESS:
-00396f 9129 ld temp2, Y+
-003970 9139 ld temp3, Y+
-003971 1728 cp temp2, tosl
-003972 0739 cpc temp3, tosh
- PFA_LESSDONE:
-003973 f71c brge PFA_ZERO1
-003974 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-003975 ff01 .dw $ff01
-003976 003e .db ">",0
-003977 396b .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-003978 3979 .dw PFA_GREATER
- PFA_GREATER:
-003979 9129 ld temp2, Y+
-00397a 9139 ld temp3, Y+
-00397b 1728 cp temp2, tosl
-00397c 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00397d f2cc brlt PFA_ZERO1
-00397e f2c1 brbs 1, PFA_ZERO1
-00397f cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-003980 ff04 .dw $ff04
-003981 6f6c
-003982 3267 .db "log2"
-003983 3975 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-003984 3985 .dw PFA_LOG2
- PFA_LOG2:
-003985 01fc movw zl, tosl
-003986 2799 clr tosh
-003987 e180 ldi tosl, 16
- PFA_LOG2_1:
-003988 958a dec tosl
-003989 f022 brmi PFA_LOG2_2 ; wrong data
-00398a 0fee lsl zl
-00398b 1fff rol zh
-00398c f7d8 brcc PFA_LOG2_1
-00398d ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00398e 959a dec tosh
-00398f ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-003990 ff01 .dw $ff01
-003991 002d .db "-",0
-003992 3980 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-003993 3994 .dw PFA_MINUS
- PFA_MINUS:
-003994 9109 ld temp0, Y+
-003995 9119 ld temp1, Y+
-003996 1b08 sub temp0, tosl
-003997 0b19 sbc temp1, tosh
-003998 01c8 movw tosl, temp0
-003999 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-00399a ff01 .dw $ff01
-00399b 002b .db "+",0
-00399c 3990 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00399d 399e .dw PFA_PLUS
- PFA_PLUS:
-00399e 9109 ld temp0, Y+
-00399f 9119 ld temp1, Y+
-0039a0 0f80 add tosl, temp0
-0039a1 1f91 adc tosh, temp1
-0039a2 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-0039a3 ff02 .dw $ff02
-0039a4 2a6d .db "m*"
-0039a5 399a .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-0039a6 39a7 .dw PFA_MSTAR
- PFA_MSTAR:
-0039a7 018c movw temp0, tosl
-0039a8 9189
-0039a9 9199 loadtos
-0039aa 019c movw temp2, tosl
- ; high cell ah*bh
-0039ab 0231 muls temp3, temp1
-0039ac 0170 movw temp4, r0
- ; low cell al*bl
-0039ad 9f20 mul temp2, temp0
-0039ae 01c0 movw tosl, r0
- ; signed ah*bl
-0039af 0330 mulsu temp3, temp0
-0039b0 08f3 sbc temp5, zeroh
-0039b1 0d90 add tosh, r0
-0039b2 1ce1 adc temp4, r1
-0039b3 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-0039b4 0312 mulsu temp1, temp2
-0039b5 08f3 sbc temp5, zeroh
-0039b6 0d90 add tosh, r0
-0039b7 1ce1 adc temp4, r1
-0039b8 1cf3 adc temp5, zeroh
-
-0039b9 939a
-0039ba 938a savetos
-0039bb 01c7 movw tosl, temp4
-0039bc ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-0039bd ff06 .dw $ff06
-0039be 6d75
-0039bf 6d2f
-0039c0 646f .db "um/mod"
-0039c1 39a3 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-0039c2 39c3 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-0039c3 017c movw temp4, tosl
-
-0039c4 9129 ld temp2, Y+
-0039c5 9139 ld temp3, Y+
-
-0039c6 9109 ld temp0, Y+
-0039c7 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-0039c8 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-0039c9 2755 clr temp7
-0039ca 0f00 lsl temp0
-0039cb 1f11 rol temp1
-0039cc 1f22 rol temp2
-0039cd 1f33 rol temp3
-0039ce 1f55 rol temp7
-
- ; try subtracting divisor
-0039cf 152e cp temp2, temp4
-0039d0 053f cpc temp3, temp5
-0039d1 0552 cpc temp7,zerol
-
-0039d2 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-0039d3 9503 inc temp0
-0039d4 192e sub temp2, temp4
-0039d5 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-0039d6 954a dec temp6
-0039d7 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-0039d8 933a st -Y,temp3
-0039d9 932a st -Y,temp2
-
- ; put quotient on stack
-0039da 01c8 movw tosl, temp0
-0039db ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-0039dc ff03 .dw $ff03
-0039dd 6d75
-0039de 002a .db "um*",0
-0039df 39bd .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-0039e0 39e1 .dw PFA_UMSTAR
- PFA_UMSTAR:
-0039e1 018c movw temp0, tosl
-0039e2 9189
-0039e3 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-0039e4 9f80 mul tosl,temp0
-0039e5 01f0 movw zl, r0
-0039e6 2722 clr temp2
-0039e7 2733 clr temp3
- ; middle bytes
-0039e8 9f90 mul tosh, temp0
-0039e9 0df0 add zh, r0
-0039ea 1d21 adc temp2, r1
-0039eb 1d33 adc temp3, zeroh
-
-0039ec 9f81 mul tosl, temp1
-0039ed 0df0 add zh, r0
-0039ee 1d21 adc temp2, r1
-0039ef 1d33 adc temp3, zeroh
-
-0039f0 9f91 mul tosh, temp1
-0039f1 0d20 add temp2, r0
-0039f2 1d31 adc temp3, r1
-0039f3 01cf movw tosl, zl
-0039f4 939a
-0039f5 938a savetos
-0039f6 01c9 movw tosl, temp2
-0039f7 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-0039f8 ff06 .dw $ff06
-0039f9 6e69
-0039fa 6576
-0039fb 7472 .db "invert"
-0039fc 39dc .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-0039fd 39fe .dw PFA_INVERT
- PFA_INVERT:
-0039fe 9580 com tosl
-0039ff 9590 com tosh
-003a00 ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-003a01 ff02 .dw $ff02
-003a02 2f32 .db "2/"
-003a03 39f8 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-003a04 3a05 .dw PFA_2SLASH
- PFA_2SLASH:
-003a05 9595 asr tosh
-003a06 9587 ror tosl
-003a07 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-003a08 ff02 .dw $ff02
-003a09 2a32 .db "2*"
-003a0a 3a01 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-003a0b 3a0c .dw PFA_2STAR
- PFA_2STAR:
-003a0c 0f88 lsl tosl
-003a0d 1f99 rol tosh
-003a0e cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-003a0f ff03 .dw $ff03
-003a10 6e61
-003a11 0064 .db "and",0
-003a12 3a08 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-003a13 3a14 .dw PFA_AND
- PFA_AND:
-003a14 9109 ld temp0, Y+
-003a15 9119 ld temp1, Y+
-003a16 2380 and tosl, temp0
-003a17 2391 and tosh, temp1
-003a18 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-003a19 ff02 .dw $ff02
-003a1a 726f .db "or"
-003a1b 3a0f .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-003a1c 3a1d .dw PFA_OR
- PFA_OR:
-003a1d 9109 ld temp0, Y+
-003a1e 9119 ld temp1, Y+
-003a1f 2b80 or tosl, temp0
-003a20 2b91 or tosh, temp1
-003a21 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-003a22 ff03 .dw $ff03
-003a23 6f78
-003a24 0072 .db "xor",0
-003a25 3a19 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-003a26 3a27 .dw PFA_XOR
- PFA_XOR:
-003a27 9109 ld temp0, Y+
-003a28 9119 ld temp1, Y+
-003a29 2780 eor tosl, temp0
-003a2a 2791 eor tosh, temp1
-003a2b cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-003a2c ff02 .dw $ff02
-003a2d 2b31 .db "1+"
-003a2e 3a22 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-003a2f 3a30 .dw PFA_1PLUS
- PFA_1PLUS:
-003a30 9601 adiw tosl,1
-003a31 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-003a32 ff02 .dw $ff02
-003a33 2d31 .db "1-"
-003a34 3a2c .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-003a35 3a36 .dw PFA_1MINUS
- PFA_1MINUS:
-003a36 9701 sbiw tosl, 1
-003a37 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-003a38 ff07 .dw $ff07
-003a39 6e3f
-003a3a 6765
-003a3b 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-003a3c 0065 .db "?negate"
-003a3d 3a32 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-003a3e 3801 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-003a3f 3921
-003a40 3836 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-003a41 3a43 DEST(QNEG1)
-003a42 3e27 .DW XT_NEGATE
-003a43 3820 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-003a44 ff06 .dw $ff06
-003a45 736c
-003a46 6968
-003a47 7466 .db "lshift"
-003a48 3a38 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-003a49 3a4a .dw PFA_LSHIFT
- PFA_LSHIFT:
-003a4a 01fc movw zl, tosl
-003a4b 9189
-003a4c 9199 loadtos
- PFA_LSHIFT1:
-003a4d 9731 sbiw zl, 1
-003a4e f01a brmi PFA_LSHIFT2
-003a4f 0f88 lsl tosl
-003a50 1f99 rol tosh
-003a51 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-003a52 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-003a53 ff06 .dw $ff06
-003a54 7372
-003a55 6968
-003a56 7466 .db "rshift"
-003a57 3a44 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-003a58 3a59 .dw PFA_RSHIFT
- PFA_RSHIFT:
-003a59 01fc movw zl, tosl
-003a5a 9189
-003a5b 9199 loadtos
- PFA_RSHIFT1:
-003a5c 9731 sbiw zl, 1
-003a5d f01a brmi PFA_RSHIFT2
-003a5e 9596 lsr tosh
-003a5f 9587 ror tosl
-003a60 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-003a61 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-003a62 ff02 .dw $ff02
-003a63 212b .db "+!"
-003a64 3a53 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-003a65 3a66 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-003a66 01fc movw zl, tosl
-003a67 9189
-003a68 9199 loadtos
-003a69 8120 ldd temp2, Z+0
-003a6a 8131 ldd temp3, Z+1
-003a6b 0f82 add tosl, temp2
-003a6c 1f93 adc tosh, temp3
-003a6d 8380 std Z+0, tosl
-003a6e 8391 std Z+1, tosh
-003a6f 9189
-003a70 9199 loadtos
-003a71 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-003a72 ff03 .dw $ff03
-003a73 7072
-003a74 0040 .db "rp@",0
-003a75 3a62 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-003a76 3a77 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-003a77 939a
-003a78 938a savetos
-003a79 b78d in tosl, SPL
-003a7a b79e in tosh, SPH
-003a7b cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-003a7c ff03 .dw $ff03
-003a7d 7072
-003a7e 0021 .db "rp!",0
-003a7f 3a72 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-003a80 3a81 .dw PFA_RP_STORE
- PFA_RP_STORE:
-003a81 b72f in temp2, SREG
-003a82 94f8 cli
-003a83 bf8d out SPL, tosl
-003a84 bf9e out SPH, tosh
-003a85 bf2f out SREG, temp2
-003a86 9189
-003a87 9199 loadtos
-003a88 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-003a89 ff03 .dw $ff03
-003a8a 7073
-003a8b 0040 .db "sp@",0
-003a8c 3a7c .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-003a8d 3a8e .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-003a8e 939a
-003a8f 938a savetos
-003a90 01ce movw tosl, yl
-003a91 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-003a92 ff03 .dw $ff03
-003a93 7073
-003a94 0021 .db "sp!",0
-003a95 3a89 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-003a96 3a97 .dw PFA_SP_STORE
- PFA_SP_STORE:
-003a97 01ec movw yl, tosl
-003a98 9189
-003a99 9199 loadtos
-003a9a cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-003a9b 3a9c .dw PFA_DODO
- PFA_DODO:
-003a9c 9129 ld temp2, Y+
-003a9d 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-003a9e e8e0 ldi zl, $80
-003a9f 0f3e add temp3, zl
-003aa0 1b82 sub tosl, temp2
-003aa1 0b93 sbc tosh, temp3
-
-003aa2 933f push temp3
-003aa3 932f push temp2 ; limit ( --> limit + $8000)
-003aa4 939f push tosh
-003aa5 938f push tosl ; start -> index ( --> index - (limit - $8000)
-003aa6 9189
-003aa7 9199 loadtos
-003aa8 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-003aa9 ff01 .dw $FF01
-003aaa 0069 .db "i",0
-003aab 3a92 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-003aac 3aad .dw PFA_I
- PFA_I:
-003aad 939a
-003aae 938a savetos
-003aaf 918f pop tosl
-003ab0 919f pop tosh ; index
-003ab1 91ef pop zl
-003ab2 91ff pop zh ; limit
-003ab3 93ff push zh
-003ab4 93ef push zl
-003ab5 939f push tosh
-003ab6 938f push tosl
-003ab7 0f8e add tosl, zl
-003ab8 1f9f adc tosh, zh
-003ab9 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-003aba 3abb .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-003abb 91ef pop zl
-003abc 91ff pop zh
-003abd 0fe8 add zl, tosl
-003abe 1ff9 adc zh, tosh
-003abf 9189
-003ac0 9199 loadtos
-003ac1 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-003ac2 93ff push zh
-003ac3 93ef push zl
-003ac4 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-003ac5 910f pop temp0
-003ac6 911f pop temp1 ; remove limit
-003ac7 9611 adiw xl, 1 ; skip branch-back address
-003ac8 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-003ac9 3aca .dw PFA_DOLOOP
- PFA_DOLOOP:
-003aca 91ef pop zl
-003acb 91ff pop zh
-003acc 9631 adiw zl,1
-003acd f3bb brvs PFA_DOPLUSLOOP_LEAVE
-003ace cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-003acf ff06 .dw $ff06
-003ad0 6e75
-003ad1 6f6c
-003ad2 706f .db "unloop"
-003ad3 3aa9 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-003ad4 3ad5 .dw PFA_UNLOOP
- PFA_UNLOOP:
-003ad5 911f pop temp1
-003ad6 910f pop temp0
-003ad7 911f pop temp1
-003ad8 910f pop temp0
-003ad9 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-003ada ff06 .dw $ff06
-003adb 6d63
-003adc 766f
-003add 3e65 .db "cmove>"
-003ade 3acf .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-003adf 3ae0 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-003ae0 93bf push xh
-003ae1 93af push xl
-003ae2 91e9 ld zl, Y+
-003ae3 91f9 ld zh, Y+ ; addr-to
-003ae4 91a9 ld xl, Y+
-003ae5 91b9 ld xh, Y+ ; addr-from
-003ae6 2f09 mov temp0, tosh
-003ae7 2b08 or temp0, tosl
-003ae8 f041 brbs 1, PFA_CMOVE_G1
-003ae9 0fe8 add zl, tosl
-003aea 1ff9 adc zh, tosh
-003aeb 0fa8 add xl, tosl
-003aec 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-003aed 911e ld temp1, -X
-003aee 9312 st -Z, temp1
-003aef 9701 sbiw tosl, 1
-003af0 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-003af1 91af pop xl
-003af2 91bf pop xh
-003af3 9189
-003af4 9199 loadtos
-003af5 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-003af6 ff02 .dw $ff02
-003af7 3c3e .db "><"
-003af8 3ada .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-003af9 3afa .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-003afa 2f09 mov temp0, tosh
-003afb 2f98 mov tosh, tosl
-003afc 2f80 mov tosl, temp0
-003afd cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-003afe ff03 .dw $ff03
-003aff 7075
-003b00 0040 .db "up@",0
-003b01 3af6 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-003b02 3b03 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-003b03 939a
-003b04 938a savetos
-003b05 01c2 movw tosl, upl
-003b06 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-003b07 ff03 .dw $ff03
-003b08 7075
-003b09 0021 .db "up!",0
-003b0a 3afe .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-003b0b 3b0c .dw PFA_UP_STORE
- PFA_UP_STORE:
-003b0c 012c movw upl, tosl
-003b0d 9189
-003b0e 9199 loadtos
-003b0f ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-003b10 ff03 .dw $ff03
-003b11 6d31
-003b12 0073 .db "1ms",0
-003b13 3b07 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-003b14 3b15 .dw PFA_1MS
- PFA_1MS:
-003b15 ede0
-003b16 e0f7
-003b17 9731
-003b18 f7f1 delay 1000
-003b19 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-003b1a ff03 .dw $ff03
-003b1b 3e32
-003b1c 0072 .db "2>r",0
-003b1d 3b10 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-003b1e 3b1f .dw PFA_2TO_R
- PFA_2TO_R:
-003b1f 01fc movw zl, tosl
-003b20 9189
-003b21 9199 loadtos
-003b22 939f push tosh
-003b23 938f push tosl
-003b24 93ff push zh
-003b25 93ef push zl
-003b26 9189
-003b27 9199 loadtos
-003b28 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-003b29 ff03 .dw $ff03
-003b2a 7232
-003b2b 003e .db "2r>",0
-003b2c 3b1a .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-003b2d 3b2e .dw PFA_2R_FROM
- PFA_2R_FROM:
-003b2e 939a
-003b2f 938a savetos
-003b30 91ef pop zl
-003b31 91ff pop zh
-003b32 918f pop tosl
-003b33 919f pop tosh
-003b34 939a
-003b35 938a savetos
-003b36 01cf movw tosl, zl
-003b37 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-003b38 ff02 .dw $ff02
-003b39 6521 .db "!e"
-003b3a 3b29 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-003b3b 3b3c .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-003b3c 01fc movw zl, tosl
-003b3d 9189
-003b3e 9199 loadtos
-003b3f b72f in_ temp2, SREG
-003b40 94f8 cli
-003b41 d028 rcall PFA_FETCHE2
-003b42 b30d in_ temp0, EEDR
-003b43 1708 cp temp0,tosl
-003b44 f009 breq PFA_STOREE3
-003b45 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-003b46 9631 adiw zl,1
-003b47 d022 rcall PFA_FETCHE2
-003b48 b30d in_ temp0, EEDR
-003b49 1709 cp temp0,tosh
-003b4a f011 breq PFA_STOREE4
-003b4b 2f89 mov tosl, tosh
-003b4c d004 rcall PFA_STOREE1
- PFA_STOREE4:
-003b4d bf2f out_ SREG, temp2
-003b4e 9189
-003b4f 9199 loadtos
-003b50 ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-003b51 99e1 sbic EECR, EEPE
-003b52 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-003b53 b707 in_ temp0, SPMCSR
-003b54 fd00 sbrc temp0,SPMEN
-003b55 cffd rjmp PFA_STOREE2
-
-003b56 bbff out_ EEARH,zh
-003b57 bbee out_ EEARL,zl
-003b58 bb8d out_ EEDR, tosl
-003b59 9ae2 sbi EECR,EEMPE
-003b5a 9ae1 sbi EECR,EEPE
-
-003b5b 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-003b5c ff02 .dw $ff02
-003b5d 6540 .db "@e"
-003b5e 3b38 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-003b5f 3b60 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-003b60 b72f in_ temp2, SREG
-003b61 94f8 cli
-003b62 01fc movw zl, tosl
-003b63 d006 rcall PFA_FETCHE2
-003b64 b38d in_ tosl, EEDR
-
-003b65 9631 adiw zl,1
-
-003b66 d003 rcall PFA_FETCHE2
-003b67 b39d in_ tosh, EEDR
-003b68 bf2f out_ SREG, temp2
-003b69 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-003b6a 99e1 sbic EECR, EEPE
-003b6b cffe rjmp PFA_FETCHE2
-
-003b6c bbff out_ EEARH,zh
-003b6d bbee out_ EEARL,zl
-
-003b6e 9ae0 sbi EECR,EERE
-003b6f 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-003b70 ff02 .dw $ff02
-003b71 6921 .db "!i"
-003b72 3b5c .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-003b73 3dff .dw PFA_DODEFER1
- PFA_STOREI:
-003b74 005c .dw EE_STOREI
-003b75 3da0 .dw XT_EDEFERFETCH
-003b76 3daa .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-003b77 ff09 .dw $ff09
-003b78 2128
-003b79 2d69
-003b7a 726e
-003b7b 7777
-003b7c 0029 .db "(!i-nrww)",0
-003b7d 3b70 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-003b7e 3b7f .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-003b7f b71f in temp1,SREG
-003b80 931f push temp1
-003b81 94f8 cli
-
-003b82 019c movw temp2, tosl ; save the (word) address
-003b83 9189
-003b84 9199 loadtos ; get the new value for the flash cell
-003b85 93af push xl
-003b86 93bf push xh
-003b87 93cf push yl
-003b88 93df push yh
-003b89 d009 rcall DO_STOREI_atmega
-003b8a 91df pop yh
-003b8b 91cf pop yl
-003b8c 91bf pop xh
-003b8d 91af pop xl
- ; finally clear the stack
-003b8e 9189
-003b8f 9199 loadtos
-003b90 911f pop temp1
- ; restore status register (and interrupt enable flag)
-003b91 bf1f out SREG,temp1
-
-003b92 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-003b93 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-003b94 94e0 com temp4
-003b95 94f0 com temp5
-003b96 218e and tosl, temp4
-003b97 219f and tosh, temp5
-003b98 2b98 or tosh, tosl
-003b99 f019 breq DO_STOREI_writepage
-003b9a 01f9 movw zl, temp2
-003b9b e002 ldi temp0,(1<<PGERS)
-003b9c d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-003b9d 01f9 movw zl, temp2
-003b9e e004 ldi temp0,(1<<PGWRT)
-003b9f d01d rcall dospm
-
- ; reenable RWW section
-003ba0 01f9 movw zl, temp2
-003ba1 e100 ldi temp0,(1<<RWWSRE)
-003ba2 d01a rcall dospm
-003ba3 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-003ba4 01f9 movw zl, temp2
- ; get the beginning of page
-003ba5 7ce0 andi zl,low(pagemask)
-003ba6 7fff andi zh,high(pagemask)
-003ba7 01ef movw y, z
- ; loop counter (in words)
-003ba8 e4a0 ldi xl,low(pagesize)
-003ba9 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-003baa 01fe movw z, y
-003bab 0fee
-003bac 1fff
-003bad 9145
-003bae 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-003baf 01fe movw z, y
-003bb0 17e2 cp zl, temp2
-003bb1 07f3 cpc zh, temp3
-003bb2 f011 breq pageload_newdata
-003bb3 010a movw r0, temp6
-003bb4 c002 rjmp pageload_cont
- pageload_newdata:
-003bb5 017a movw temp4, temp6
-003bb6 010c movw r0, tosl
- pageload_cont:
-003bb7 2700 clr temp0
-003bb8 d004 rcall dospm
-003bb9 9621 adiw y, 1
-003bba 9711 sbiw x, 1
-003bbb f771 brne pageload_loop
-
- pageload_done:
-003bbc 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-003bbd 99e1 sbic EECR, EEPE
-003bbe cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-003bbf b717 in_ temp1, SPMCSR
-003bc0 fd10 sbrc temp1, SPMEN
-003bc1 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-003bc2 0fee
-003bc3 1fff writeflashcell
- ; execute spm
-003bc4 6001 ori temp0, (1<<SPMEN)
-003bc5 bf07 out_ SPMCSR,temp0
-003bc6 95e8 spm
-003bc7 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-003bc8 ff02 .dw $ff02
-003bc9 6940 .db "@i"
-003bca 3b77 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-003bcb 3bcc .dw PFA_FETCHI
- PFA_FETCHI:
-003bcc 01fc movw zl, tosl
-003bcd 0fee
-003bce 1fff
-003bcf 9185
-003bd0 9195 readflashcell tosl,tosh
-003bd1 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .elif AMFORTH_NRWW_SIZE>4000
- .include "dict/core_4k.inc"
-
- ; in a short distance to DO_NEXT
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-003bd2 ff03 .dw $ff03
-003bd3 3e6e
-003bd4 0072 .db "n>r",0
-003bd5 3bc8 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-003bd6 3bd7 .dw PFA_N_TO_R
- PFA_N_TO_R:
-003bd7 01fc movw zl, tosl
-003bd8 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-003bd9 9189
-003bda 9199 loadtos
-003bdb 939f push tosh
-003bdc 938f push tosl
-003bdd 950a dec temp0
-003bde f7d1 brne PFA_N_TO_R1
-003bdf 93ef push zl
-003be0 93ff push zh
-003be1 9189
-003be2 9199 loadtos
-003be3 cc21 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-003be4 ff03 .dw $ff03
-003be5 726e
-003be6 003e .db "nr>",0
-003be7 3bd2 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-003be8 3be9 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-003be9 939a
-003bea 938a savetos
-003beb 91ff pop zh
-003bec 91ef pop zl
-003bed 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-003bee 918f pop tosl
-003bef 919f pop tosh
-003bf0 939a
-003bf1 938a savetos
-003bf2 950a dec temp0
-003bf3 f7d1 brne PFA_N_R_FROM1
-003bf4 01cf movw tosl, zl
-003bf5 cc0f jmp_ DO_NEXT
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-003bf6 ff03 .dw $ff03
-003bf7 3264
-003bf8 002a .db "d2*",0
-003bf9 3be4 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-003bfa 3bfb .dw PFA_D2STAR
- PFA_D2STAR:
-003bfb 9109 ld temp0, Y+
-003bfc 9119 ld temp1, Y+
-003bfd 0f00 lsl temp0
-003bfe 1f11 rol temp1
-003bff 1f88 rol tosl
-003c00 1f99 rol tosh
-003c01 931a st -Y, temp1
-003c02 930a st -Y, temp0
-003c03 cc01 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-003c04 ff03 .dw $ff03
-003c05 3264
-003c06 002f .db "d2/",0
-003c07 3bf6 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-003c08 3c09 .dw PFA_D2SLASH
- PFA_D2SLASH:
-003c09 9109 ld temp0, Y+
-003c0a 9119 ld temp1, Y+
-003c0b 9595 asr tosh
-003c0c 9587 ror tosl
-003c0d 9517 ror temp1
-003c0e 9507 ror temp0
-003c0f 931a st -Y, temp1
-003c10 930a st -Y, temp0
-003c11 cbf3 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-003c12 ff02 .dw $ff02
-003c13 2b64 .db "d+"
-003c14 3c04 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-003c15 3c16 .dw PFA_DPLUS
- PFA_DPLUS:
-003c16 9129 ld temp2, Y+
-003c17 9139 ld temp3, Y+
-
-003c18 90e9 ld temp4, Y+
-003c19 90f9 ld temp5, Y+
-003c1a 9149 ld temp6, Y+
-003c1b 9159 ld temp7, Y+
-
-003c1c 0f24 add temp2, temp6
-003c1d 1f35 adc temp3, temp7
-003c1e 1d8e adc tosl, temp4
-003c1f 1d9f adc tosh, temp5
-
-003c20 933a st -Y, temp3
-003c21 932a st -Y, temp2
-003c22 cbe2 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-003c23 ff02 .dw $ff02
-003c24 2d64 .db "d-"
-003c25 3c12 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-003c26 3c27 .dw PFA_DMINUS
- PFA_DMINUS:
-003c27 9129 ld temp2, Y+
-003c28 9139 ld temp3, Y+
-
-003c29 90e9 ld temp4, Y+
-003c2a 90f9 ld temp5, Y+
-003c2b 9149 ld temp6, Y+
-003c2c 9159 ld temp7, Y+
-
-003c2d 1b42 sub temp6, temp2
-003c2e 0b53 sbc temp7, temp3
-003c2f 0ae8 sbc temp4, tosl
-003c30 0af9 sbc temp5, tosh
-
-003c31 935a st -Y, temp7
-003c32 934a st -Y, temp6
-003c33 01c7 movw tosl, temp4
-003c34 cbd0 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-003c35 ff07 .dw $ff07
-003c36 6964
-003c37 766e
-003c38 7265
-003c39 0074 .db "dinvert",0
-003c3a 3c23 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-003c3b 3c3c .dw PFA_DINVERT
- PFA_DINVERT:
-003c3c 9109 ld temp0, Y+
-003c3d 9119 ld temp1, Y+
-003c3e 9580 com tosl
-003c3f 9590 com tosh
-003c40 9500 com temp0
-003c41 9510 com temp1
-003c42 931a st -Y, temp1
-003c43 930a st -Y, temp0
-003c44 cbc0 jmp_ DO_NEXT
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-003c45 ff04 .dw $ff04
-003c46 6d2f
-003c47 646f .db "/mod"
-003c48 3c35 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-003c49 3c4a .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-003c4a 019c movw temp2, tosl
-
-003c4b 9109 ld temp0, Y+
-003c4c 9119 ld temp1, Y+
-
-003c4d 2f41 mov temp6,temp1 ;move dividend High to sign register
-003c4e 2743 eor temp6,temp3 ;xor divisor High with sign register
-003c4f ff17 sbrs temp1,7 ;if MSB in dividend set
-003c50 c004 rjmp PFA_SLASHMOD_1
-003c51 9510 com temp1 ; change sign of dividend
-003c52 9500 com temp0
-003c53 5f0f subi temp0,low(-1)
-003c54 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-003c55 ff37 sbrs temp3,7 ;if MSB in divisor set
-003c56 c004 rjmp PFA_SLASHMOD_2
-003c57 9530 com temp3 ; change sign of divisor
-003c58 9520 com temp2
-003c59 5f2f subi temp2,low(-1)
-003c5a 4f3f sbci temp3,high(-1)
-003c5b 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-003c5c 18ff sub temp5,temp5;clear remainder High byte and carry
-003c5d e151 ldi temp7,17 ;init loop counter
-
-003c5e 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-003c5f 1f11 rol temp1
-003c60 955a dec temp7 ;decrement counter
-003c61 f439 brne PFA_SLASHMOD_5 ;if done
-003c62 ff47 sbrs temp6,7 ; if MSB in sign register set
-003c63 c004 rjmp PFA_SLASHMOD_4
-003c64 9510 com temp1 ; change sign of result
-003c65 9500 com temp0
-003c66 5f0f subi temp0,low(-1)
-003c67 4f1f sbci temp1,high(-1)
-003c68 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-003c69 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-003c6a 1cff rol temp5
-003c6b 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-003c6c 0af3 sbc temp5,temp3 ;
-003c6d f420 brcc PFA_SLASHMOD_6 ;if result negative
-003c6e 0ee2 add temp4,temp2 ; restore remainder
-003c6f 1ef3 adc temp5,temp3
-003c70 9488 clc ; clear carry to be shifted into result
-003c71 cfec rjmp PFA_SLASHMOD_3 ;else
-003c72 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-003c73 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-003c74 92fa st -Y,temp5
-003c75 92ea st -Y,temp4
-
- ; put quotient on stack
-003c76 01c8 movw tosl, temp0
-003c77 cb8d jmp_ DO_NEXT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-003c78 ff03 .dw $ff03
-003c79 6261
-003c7a 0073 .db "abs",0
-003c7b 3c45 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-003c7c 3801 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-003c7d 38b1
-003c7e 3a3e
-003c7f 3820 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-003c80 ff04 .dw $ff04
-003c81 6970
-003c82 6b63 .db "pick"
-003c83 3c78 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-003c84 3801 .dw DO_COLON
- PFA_PICK:
- .endif
-003c85 3a2f .dw XT_1PLUS
-003c86 3ec4 .dw XT_CELLS
-003c87 3a8d .dw XT_SP_FETCH
-003c88 399d .dw XT_PLUS
-003c89 3879 .dw XT_FETCH
-003c8a 3820 .dw XT_EXIT
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-003c8b ff05 .dw $ff05
-003c8c 6563
-003c8d 6c6c
-003c8e 002b .db "cell+",0
-003c8f 3c80 .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-003c90 3c91 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-003c91 9602 adiw tosl, CELLSIZE
-003c92 cb72 jmp_ DO_NEXT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-003c93 ff04 .dw $ff04
-003c94 692b
-003c95 746e .db "+int"
-003c96 3c8b .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-003c97 3c98 .dw PFA_INTON
- PFA_INTON:
-003c98 9478 sei
-003c99 cb6b jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-003c9a ff04 .dw $ff04
-003c9b 692d
-003c9c 746e .db "-int"
-003c9d 3c93 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-003c9e 3c9f .dw PFA_INTOFF
- PFA_INTOFF:
-003c9f 94f8 cli
-003ca0 cb64 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-003ca1 ff04 .dw $ff04
-003ca2 6e69
-003ca3 2174 .db "int!"
-003ca4 3c9a .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-003ca5 3801 .dw DO_COLON
- PFA_INTSTORE:
-003ca6 383d .dw XT_DOLITERAL
-003ca7 0000 .dw intvec
-003ca8 399d .dw XT_PLUS
-003ca9 3b3b .dw XT_STOREE
-003caa 3820 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-003cab ff04 .dw $ff04
-003cac 6e69
-003cad 4074 .db "int@"
-003cae 3ca1 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-003caf 3801 .dw DO_COLON
- PFA_INTFETCH:
-003cb0 383d .dw XT_DOLITERAL
-003cb1 0000 .dw intvec
-003cb2 399d .dw XT_PLUS
-003cb3 3b5f .dw XT_FETCHE
-003cb4 3820 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-003cb5 ff08 .dw $ff08
-003cb6 6e69
-003cb7 2d74
-003cb8 7274
-003cb9 7061 .db "int-trap"
-003cba 3cab .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-003cbb 3cbc .dw PFA_INTTRAP
- PFA_INTTRAP:
-003cbc 2eb8 mov isrflag, tosl
-003cbd 9189
-003cbe 9199 loadtos
-003cbf cb45 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-003cc0 3801 .dw DO_COLON
- PFA_ISREXEC:
-003cc1 3caf .dw XT_INTFETCH
-003cc2 382a .dw XT_EXECUTE
-003cc3 3cc5 .dw XT_ISREND
-003cc4 3820 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-003cc5 3cc6 .dw PFA_ISREND
- PFA_ISREND:
-003cc6 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-003cc7 cb3d jmp_ DO_NEXT
- PFA_ISREND1:
-003cc8 9518 reti
- .endif
-
- ; now the relocatable colon words
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-003cc9 3801 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-003cca 03c5 .dw XT_DOSLITERAL
-003ccb 0003 .dw 3
-003ccc 6f20
-003ccd 006b .db " ok",0
- .endif
-003cce 03f8 .dw XT_ITYPE
-003ccf 3820 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-003cd0 ff03 .dw $FF03
-003cd1 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-003cd2 006b .db ".ok"
-003cd3 3cb5 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-003cd4 3dff .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-003cd5 001c .dw USER_P_OK
-003cd6 3dc8 .dw XT_UDEFERFETCH
-003cd7 3dd4 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-003cd8 3801 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-003cd9 03c5 .dw XT_DOSLITERAL
-003cda 0002 .dw 2
-003cdb 203e .db "> "
- .endif
-003cdc 3fa1 .dw XT_CR
-003cdd 03f8 .dw XT_ITYPE
-003cde 3820 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-003cdf ff06 .dw $FF06
-003ce0 722e
-003ce1 6165
-003ce2 7964 .db ".ready"
-003ce3 3cd0 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-003ce4 3dff .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-003ce5 0020 .dw USER_P_RDY
-003ce6 3dc8 .dw XT_UDEFERFETCH
-003ce7 3dd4 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-003ce8 3801 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-003ce9 03c5 .dw XT_DOSLITERAL
-003cea 0004 .dw 4
-003ceb 3f20
-003cec 203f .db " ?? "
- .endif
-003ced 03f8 .dw XT_ITYPE
-003cee 3ebd .dw XT_BASE
-003cef 3879 .dw XT_FETCH
-003cf0 38ff .dw XT_TO_R
-003cf1 3f41 .dw XT_DECIMAL
-003cf2 037a .dw XT_DOT
-003cf3 3ee2 .dw XT_TO_IN
-003cf4 3879 .dw XT_FETCH
-003cf5 037a .dw XT_DOT
-003cf6 38f6 .dw XT_R_FROM
-003cf7 3ebd .dw XT_BASE
-003cf8 3881 .dw XT_STORE
-003cf9 3820 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-003cfa ff06 .dw $FF06
-003cfb 652e
-003cfc 7272
-003cfd 726f .db ".error"
-003cfe 3cdf .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-003cff 3dff .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-003d00 001e .dw USER_P_ERR
-003d01 3dc8 .dw XT_UDEFERFETCH
-003d02 3dd4 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-003d03 ff04 .dw $ff04
-003d04 7571
-003d05 7469 .db "quit"
-003d06 3cfa .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-003d07 3801 .dw DO_COLON
- .endif
- PFA_QUIT:
-003d08 0851
-003d09 0858
-003d0a 3881 .dw XT_LP0,XT_LP,XT_STORE
-003d0b 05ca .dw XT_SP0
-003d0c 3a96 .dw XT_SP_STORE
-003d0d 05d7 .dw XT_RP0
-003d0e 3a80 .dw XT_RP_STORE
-003d0f 08e6 .dw XT_LBRACKET
-
- PFA_QUIT2:
-003d10 3eb7 .dw XT_STATE
-003d11 3879 .dw XT_FETCH
-003d12 391a .dw XT_ZEROEQUAL
-003d13 3836 .dw XT_DOCONDBRANCH
-003d14 3d16 DEST(PFA_QUIT4)
-003d15 3ce4 .dw XT_PROMPTREADY
- PFA_QUIT4:
-003d16 04de .dw XT_REFILL
-003d17 3836 .dw XT_DOCONDBRANCH
-003d18 3d28 DEST(PFA_QUIT3)
-003d19 383d .dw XT_DOLITERAL
-003d1a 0625 .dw XT_INTERPRET
-003d1b 3d70 .dw XT_CATCH
-003d1c 38b9 .dw XT_QDUP
-003d1d 3836 .dw XT_DOCONDBRANCH
-003d1e 3d28 DEST(PFA_QUIT3)
-003d1f 38b1 .dw XT_DUP
-003d20 383d .dw XT_DOLITERAL
-003d21 fffe .dw -2
-003d22 396e .dw XT_LESS
-003d23 3836 .dw XT_DOCONDBRANCH
-003d24 3d26 DEST(PFA_QUIT5)
-003d25 3cff .dw XT_PROMPTERROR
- PFA_QUIT5:
-003d26 382f .dw XT_DOBRANCH
-003d27 3d08 DEST(PFA_QUIT)
- PFA_QUIT3:
-003d28 3cd4 .dw XT_PROMPTOK
-003d29 382f .dw XT_DOBRANCH
-003d2a 3d10 DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-003d2b ff05 .dw $ff05
-003d2c 6170
-003d2d 7375
-003d2e 0065 .db "pause",0
-003d2f 3d03 .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-003d30 3dff .dw PFA_DODEFER1
- PFA_PAUSE:
-003d31 00ed .dw ram_pause
-003d32 3db4 .dw XT_RDEFERFETCH
-003d33 3dbe .dw XT_RDEFERSTORE
-
- .dseg
-0000ed ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-003d34 ff04 .dw $ff04
-003d35 6f63
-003d36 646c .db "cold"
-003d37 3d2b .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-003d38 3d39 .dw PFA_COLD
- PFA_COLD:
-003d39 b6a4 in_ mcu_boot, MCUSR
-003d3a 2422 clr zerol
-003d3b 2433 clr zeroh
-003d3c 24bb clr isrflag
-003d3d be24 out_ MCUSR, zerol
- ; clear RAM
-003d3e e6e0 ldi zl, low(ramstart)
-003d3f e0f0 ldi zh, high(ramstart)
- clearloop:
-003d40 9221 st Z+, zerol
-003d41 36e0 cpi zl, low(sram_size+ramstart)
-003d42 f7e9 brne clearloop
-003d43 30f8 cpi zh, high(sram_size+ramstart)
-003d44 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-0000ef ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-003d45 eeef ldi zl, low(ram_user1)
-003d46 e0f0 ldi zh, high(ram_user1)
-003d47 012f movw upl, zl
- ; init return stack pointer
-003d48 e50f ldi temp0,low(rstackstart)
-003d49 bf0d out_ SPL,temp0
-003d4a 8304 std Z+4, temp0
-003d4b e018 ldi temp1,high(rstackstart)
-003d4c bf1e out_ SPH,temp1
-003d4d 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-003d4e e0cf ldi yl,low(stackstart)
-003d4f 83c6 std Z+6, yl
-003d50 e0d8 ldi yh,high(stackstart)
-003d51 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-003d52 e5aa ldi XL, low(PFA_WARM)
-003d53 e3bd ldi XH, high(PFA_WARM)
- ; its a far jump...
-003d54 cab0 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-003d55 ff04 .dw $ff04
-003d56 6177
-003d57 6d72 .db "warm"
-003d58 3d34 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-003d59 3801 .dw DO_COLON
- PFA_WARM:
- .endif
-003d5a 0297 .dw XT_INIT_RAM
-003d5b 383d .dw XT_DOLITERAL
-003d5c 019a .dw XT_NOOP
-003d5d 383d .dw XT_DOLITERAL
-003d5e 3d30 .dw XT_PAUSE
-003d5f 3ddf .dw XT_DEFERSTORE
-003d60 08e6 .dw XT_LBRACKET
-003d61 3f5c .dw XT_TURNKEY
-003d62 3d07 .dw XT_QUIT ; never returns
-
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-003d63 ff07 .dw $ff07
-003d64 6168
-003d65 646e
-003d66 656c
-003d67 0072 .db "handler",0
-003d68 3d55 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-003d69 3858 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-003d6a 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-003d6b ff05 .dw $ff05
-003d6c 6163
-003d6d 6374
-003d6e 0068 .db "catch",0
-003d6f 3d63 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-003d70 3801 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-003d71 3a8d .dw XT_SP_FETCH
-003d72 38ff .dw XT_TO_R
- ; handler @ >r
-003d73 3d69 .dw XT_HANDLER
-003d74 3879 .dw XT_FETCH
-003d75 38ff .dw XT_TO_R
- ; rp@ handler !
-003d76 3a76 .dw XT_RP_FETCH
-003d77 3d69 .dw XT_HANDLER
-003d78 3881 .dw XT_STORE
-003d79 382a .dw XT_EXECUTE
- ; r> handler !
-003d7a 38f6 .dw XT_R_FROM
-003d7b 3d69 .dw XT_HANDLER
-003d7c 3881 .dw XT_STORE
-003d7d 38f6 .dw XT_R_FROM
-003d7e 38d9 .dw XT_DROP
-003d7f 3954 .dw XT_ZERO
-003d80 3820 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-003d81 ff05 .dw $ff05
-003d82 6874
-003d83 6f72
-003d84 0077 .db "throw",0
-003d85 3d6b .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-003d86 3801 .dw DO_COLON
- PFA_THROW:
- .endif
-003d87 38b1 .dw XT_DUP
-003d88 391a .dw XT_ZEROEQUAL
-003d89 3836 .dw XT_DOCONDBRANCH
-003d8a 3d8d DEST(PFA_THROW1)
-003d8b 38d9 .dw XT_DROP
-003d8c 3820 .dw XT_EXIT
- PFA_THROW1:
-003d8d 3d69 .dw XT_HANDLER
-003d8e 3879 .dw XT_FETCH
-003d8f 3a80 .dw XT_RP_STORE
-003d90 38f6 .dw XT_R_FROM
-003d91 3d69 .dw XT_HANDLER
-003d92 3881 .dw XT_STORE
-003d93 38f6 .dw XT_R_FROM
-003d94 38c4 .dw XT_SWAP
-003d95 38ff .dw XT_TO_R
-003d96 3a96 .dw XT_SP_STORE
-003d97 38d9 .dw XT_DROP
-003d98 38f6 .dw XT_R_FROM
-003d99 3820 .dw XT_EXIT
-
-
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-003d9a ff07 .dw $ff07
-003d9b 6445
-003d9c 6665
-003d9d 7265
-003d9e 0040 .db "Edefer@",0
-003d9f 3d81 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-003da0 3801 .dw DO_COLON
- PFA_EDEFERFETCH:
-003da1 3bcb .dw XT_FETCHI
-003da2 3b5f .dw XT_FETCHE
-003da3 3820 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-003da4 ff07 .dw $ff07
-003da5 6445
-003da6 6665
-003da7 7265
-003da8 0021 .db "Edefer!",0
-003da9 3d9a .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-003daa 3801 .dw DO_COLON
- PFA_EDEFERSTORE:
-003dab 3bcb .dw XT_FETCHI
-003dac 3b3b .dw XT_STOREE
-003dad 3820 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-003dae ff07 .dw $ff07
-003daf 6452
-003db0 6665
-003db1 7265
-003db2 0040 .db "Rdefer@",0
-003db3 3da4 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-003db4 3801 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-003db5 3bcb .dw XT_FETCHI
-003db6 3879 .dw XT_FETCH
-003db7 3820 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-003db8 ff07 .dw $ff07
-003db9 6452
-003dba 6665
-003dbb 7265
-003dbc 0021 .db "Rdefer!",0
-003dbd 3dae .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-003dbe 3801 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-003dbf 3bcb .dw XT_FETCHI
-003dc0 3881 .dw XT_STORE
-003dc1 3820 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-003dc2 ff07 .dw $ff07
-003dc3 6455
-003dc4 6665
-003dc5 7265
-003dc6 0040 .db "Udefer@",0
-003dc7 3db8 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-003dc8 3801 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-003dc9 3bcb .dw XT_FETCHI
-003dca 3b02 .dw XT_UP_FETCH
-003dcb 399d .dw XT_PLUS
-003dcc 3879 .dw XT_FETCH
-003dcd 3820 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-003dce ff07 .dw $ff07
-003dcf 6455
-003dd0 6665
-003dd1 7265
-003dd2 0021 .db "Udefer!",0
-003dd3 3dc2 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-003dd4 3801 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-003dd5 3bcb .dw XT_FETCHI
-003dd6 3b02 .dw XT_UP_FETCH
-003dd7 399d .dw XT_PLUS
-003dd8 3881 .dw XT_STORE
-003dd9 3820 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-003dda ff06 .dw $ff06
-003ddb 6564
-003ddc 6566
-003ddd 2172 .db "defer!"
-003dde 3dce .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-003ddf 3801 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-003de0 3fd0 .dw XT_TO_BODY
-003de1 38b1 .dw XT_DUP
-003de2 01c6 .dw XT_ICELLPLUS
-003de3 01c6 .dw XT_ICELLPLUS
-003de4 3bcb .dw XT_FETCHI
-003de5 382a .dw XT_EXECUTE
-003de6 3820 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-003de7 ff06 .dw $ff06
-003de8 6564
-003de9 6566
-003dea 4072 .db "defer@"
-003deb 3dda .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-003dec 3801 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-003ded 3fd0 .dw XT_TO_BODY
-003dee 38b1 .dw XT_DUP
-003def 01c6 .dw XT_ICELLPLUS
-003df0 3bcb .dw XT_FETCHI
-003df1 382a .dw XT_EXECUTE
-003df2 3820 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-003df3 ff07 .dw $ff07
-003df4 6428
-003df5 6665
-003df6 7265
-003df7 0029 .db "(defer)", 0
-003df8 3de7 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-003df9 3801 .dw DO_COLON
- PFA_DODEFER:
-003dfa 072e .dw XT_DOCREATE
-003dfb 088e .dw XT_REVEAL
-003dfc 0751 .dw XT_COMPILE
-003dfd 3dff .dw PFA_DODEFER1
-003dfe 3820 .dw XT_EXIT
- PFA_DODEFER1:
-003dff 940e 08a7 call_ DO_DODOES
-003e01 38b1 .dw XT_DUP
-003e02 01c6 .dw XT_ICELLPLUS
-003e03 3bcb .dw XT_FETCHI
-003e04 382a .dw XT_EXECUTE
-003e05 382a .dw XT_EXECUTE
-003e06 3820 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-003e07 ff02 .dw $ff02
-003e08 2e75 .db "u."
-003e09 3df3 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-003e0a 3801 .dw DO_COLON
- PFA_UDOT:
- .endif
-003e0b 3954 .dw XT_ZERO
-003e0c 0382 .dw XT_UDDOT
-003e0d 3820 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-003e0e ff03 .dw $ff03
-003e0f 2e75
-003e10 0072 .db "u.r",0
-003e11 3e07 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-003e12 3801 .dw DO_COLON
- PFA_UDOTR:
- .endif
-003e13 3954 .dw XT_ZERO
-003e14 38c4 .dw XT_SWAP
-003e15 038b .dw XT_UDDOTR
-003e16 3820 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-003e17 ff05 .dw $ff05
-003e18 2f75
-003e19 6f6d
-003e1a 0064 .db "u/mod",0
-003e1b 3e0e .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-003e1c 3801 .dw DO_COLON
- PFA_USLASHMOD:
-003e1d 38ff .dw XT_TO_R
-003e1e 3954 .dw XT_ZERO
-003e1f 38f6 .dw XT_R_FROM
-003e20 39c2 .dw XT_UMSLASHMOD
-003e21 3820 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-003e22 ff06 .dw $ff06
-003e23 656e
-003e24 6167
-003e25 6574 .db "negate"
-003e26 3e17 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-003e27 3801 .dw DO_COLON
- PFA_NEGATE:
-003e28 39fd .dw XT_INVERT
-003e29 3a2f .dw XT_1PLUS
-003e2a 3820 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-003e2b ff01 .dw $ff01
-003e2c 002f .db "/",0
-003e2d 3e22 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-003e2e 3801 .dw DO_COLON
- PFA_SLASH:
- .endif
-003e2f 3c49 .dw XT_SLASHMOD
-003e30 38f0 .dw XT_NIP
-003e31 3820 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-003e32 ff03 .dw $ff03
-003e33 6f6d
-003e34 0064 .db "mod",0
-003e35 3e2b .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-003e36 3801 .dw DO_COLON
- PFA_MOD:
- .endif
-003e37 3c49 .dw XT_SLASHMOD
-003e38 38d9 .dw XT_DROP
-003e39 3820 .dw XT_EXIT
-
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-003e3a ff03 .dw $ff03
-003e3b 696d
-003e3c 006e .db "min",0
-003e3d 3e32 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-003e3e 3801 .dw DO_COLON
- PFA_MIN:
- .endif
-003e3f 3ec9 .dw XT_2DUP
-003e40 3978 .dw XT_GREATER
-003e41 3836 .dw XT_DOCONDBRANCH
-003e42 3e44 DEST(PFA_MIN1)
-003e43 38c4 .dw XT_SWAP
- PFA_MIN1:
-003e44 38d9 .dw XT_DROP
-003e45 3820 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-003e46 ff03 .dw $ff03
-003e47 616d
-003e48 0078 .db "max",0
-003e49 3e3a .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-003e4a 3801 .dw DO_COLON
- PFA_MAX:
-
- .endif
-003e4b 3ec9 .dw XT_2DUP
-003e4c 396e .dw XT_LESS
-003e4d 3836 .dw XT_DOCONDBRANCH
-003e4e 3e50 DEST(PFA_MAX1)
-003e4f 38c4 .dw XT_SWAP
- PFA_MAX1:
-003e50 38d9 .dw XT_DROP
-003e51 3820 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-003e52 ff06 .dw $ff06
-003e53 6977
-003e54 6874
-003e55 6e69 .db "within"
-003e56 3e46 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-003e57 3801 .dw DO_COLON
- PFA_WITHIN:
- .endif
-003e58 38cf .dw XT_OVER
-003e59 3993 .dw XT_MINUS
-003e5a 38ff .dw XT_TO_R
-003e5b 3993 .dw XT_MINUS
-003e5c 38f6 .dw XT_R_FROM
-003e5d 395c .dw XT_ULESS
-003e5e 3820 .dw XT_EXIT
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-003e5f ff0d .dw $ff0d
-003e60 6873
-003e61 776f
-003e62 772d
-003e63 726f
-003e64 6c64
-003e65 7369
-003e66 0074 .db "show-wordlist",0
-003e67 3e52 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-003e68 3801 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-003e69 383d .dw XT_DOLITERAL
-003e6a 3e6e .dw XT_SHOWWORD
-003e6b 38c4 .dw XT_SWAP
-003e6c 06cf .dw XT_TRAVERSEWORDLIST
-003e6d 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-003e6e 3801 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-003e6f 06ea .dw XT_NAME2STRING
-003e70 03f8 .dw XT_ITYPE
-003e71 3fae .dw XT_SPACE ; ( -- addr n)
-003e72 394b .dw XT_TRUE
-003e73 3820 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-003e74 ff05 .dw $ff05
-003e75 6f77
-003e76 6472
-003e77 0073 .db "words",0
-003e78 3e5f .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-003e79 3801 .dw DO_COLON
- PFA_WORDS:
- .endif
-003e7a 383d .dw XT_DOLITERAL
-003e7b 0042 .dw CFG_ORDERLISTLEN+2
-003e7c 3b5f .dw XT_FETCHE
-003e7d 3e68 .dw XT_SHOWWORDLIST
-003e7e 3820 .dw XT_EXIT
-
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-003e7f 0002 .dw $0002
-003e80 222e .db ".",$22
-003e81 3e74 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-003e82 3801 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-003e83 3e8a .dw XT_SQUOTE
-003e84 0751 .dw XT_COMPILE
-003e85 03f8 .dw XT_ITYPE
-003e86 3820 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-003e87 0002 .dw $0002
-003e88 2273 .db "s",$22
-003e89 3e7f .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-003e8a 3801 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-003e8b 383d .dw XT_DOLITERAL
-003e8c 0022 .dw 34 ; 0x22
-003e8d 0583 .dw XT_PARSE ; ( -- addr n)
-003e8e 3eb7 .dw XT_STATE
-003e8f 3879 .dw XT_FETCH
-003e90 3836 .dw XT_DOCONDBRANCH
-003e91 3e93 DEST(PFA_SQUOTE1)
-003e92 077d .dw XT_SLITERAL
- PFA_SQUOTE1:
-003e93 3820 .dw XT_EXIT
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-003e94 ff04 .dw $ff04
-003e95 6966
-003e96 6c6c .db "fill"
-003e97 3e87 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-003e98 3801 .dw DO_COLON
- PFA_FILL:
-003e99 38e1 .dw XT_ROT
-003e9a 38e1 .dw XT_ROT
-003e9b 38b9
-003e9c 3836 .dw XT_QDUP,XT_DOCONDBRANCH
-003e9d 3ea5 DEST(PFA_FILL2)
-003e9e 3f99 .dw XT_BOUNDS
-003e9f 3a9b .dw XT_DODO
- PFA_FILL1:
-003ea0 38b1 .dw XT_DUP
-003ea1 3aac .dw XT_I
-003ea2 388d .dw XT_CSTORE ; ( -- c c-addr)
-003ea3 3ac9 .dw XT_DOLOOP
-003ea4 3ea0 .dw PFA_FILL1
- PFA_FILL2:
-003ea5 38d9 .dw XT_DROP
-003ea6 3820 .dw XT_EXIT
-
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-003ea7 ff05 .dw $ff05
-003ea8 5f66
-003ea9 7063
-003eaa 0075 .db "f_cpu",0
-003eab 3e94 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-003eac 3801 .dw DO_COLON
- PFA_F_CPU:
- .endif
-003ead 383d .dw XT_DOLITERAL
-003eae 1200 .dw (F_CPU % 65536)
-003eaf 383d .dw XT_DOLITERAL
-003eb0 007a .dw (F_CPU / 65536)
-003eb1 3820 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-003eb2 ff05 .dw $ff05
-003eb3 7473
-003eb4 7461
-003eb5 0065 .db "state",0
-003eb6 3ea7 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-003eb7 3848 .dw PFA_DOVARIABLE
- PFA_STATE:
-003eb8 011b .dw ram_state
-
- .dseg
-00011b ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-003eb9 ff04 .dw $ff04
-003eba 6162
-003ebb 6573 .db "base"
-003ebc 3eb2 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-003ebd 3858 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-003ebe 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-003ebf ff05 .dw $ff05
-003ec0 6563
-003ec1 6c6c
-003ec2 0073 .db "cells",0
-003ec3 3eb9 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-003ec4 3a0c .dw PFA_2STAR
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-003ec5 ff04 .dw $ff04
-003ec6 6432
-003ec7 7075 .db "2dup"
-003ec8 3ebf .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-003ec9 3801 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-003eca 38cf .dw XT_OVER
-003ecb 38cf .dw XT_OVER
-003ecc 3820 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-003ecd ff05 .dw $ff05
-003ece 6432
-003ecf 6f72
-003ed0 0070 .db "2drop",0
-003ed1 3ec5 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-003ed2 3801 .dw DO_COLON
- PFA_2DROP:
- .endif
-003ed3 38d9 .dw XT_DROP
-003ed4 38d9 .dw XT_DROP
-003ed5 3820 .dw XT_EXIT
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-003ed6 ff04 .dw $ff04
-003ed7 7574
-003ed8 6b63 .db "tuck"
-003ed9 3ecd .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-003eda 3801 .dw DO_COLON
- PFA_TUCK:
- .endif
-003edb 38c4 .dw XT_SWAP
-003edc 38cf .dw XT_OVER
-003edd 3820 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-003ede ff03 .dw $ff03
-003edf 693e
-003ee0 006e .db ">in",0
-003ee1 3ed6 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-003ee2 3858 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-003ee3 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-003ee4 ff03 .dw $ff03
-003ee5 6170
-003ee6 0064 .db "pad",0
-003ee7 3ede .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-003ee8 3801 .dw DO_COLON
- PFA_PAD:
- .endif
-003ee9 3f23 .dw XT_HERE
-003eea 383d .dw XT_DOLITERAL
-003eeb 0028 .dw 40
-003eec 399d .dw XT_PLUS
-003eed 3820 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-003eee ff04 .dw $ff04
-003eef 6d65
-003ef0 7469 .db "emit"
-003ef1 3ee4 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-003ef2 3dff .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-003ef3 000e .dw USER_EMIT
-003ef4 3dc8 .dw XT_UDEFERFETCH
-003ef5 3dd4 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-003ef6 ff05 .dw $ff05
-003ef7 6d65
-003ef8 7469
-003ef9 003f .db "emit?",0
-003efa 3eee .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-003efb 3dff .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-003efc 0010 .dw USER_EMITQ
-003efd 3dc8 .dw XT_UDEFERFETCH
-003efe 3dd4 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-003eff ff03 .dw $ff03
-003f00 656b
-003f01 0079 .db "key",0
-003f02 3ef6 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-003f03 3dff .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-003f04 0012 .dw USER_KEY
-003f05 3dc8 .dw XT_UDEFERFETCH
-003f06 3dd4 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-003f07 ff04 .dw $ff04
-003f08 656b
-003f09 3f79 .db "key?"
-003f0a 3eff .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-003f0b 3dff .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-003f0c 0014 .dw USER_KEYQ
-003f0d 3dc8 .dw XT_UDEFERFETCH
-003f0e 3dd4 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-003f0f ff02 .dw $ff02
-003f10 7064 .db "dp"
-003f11 3f07 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-003f12 386f .dw PFA_DOVALUE1
- PFA_DP:
-003f13 002c .dw CFG_DP
-003f14 3da0 .dw XT_EDEFERFETCH
-003f15 3daa .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-003f16 ff05 .dw $ff05
-003f17 6865
-003f18 7265
-003f19 0065 .db "ehere",0
-003f1a 3f0f .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-003f1b 386f .dw PFA_DOVALUE1
- PFA_EHERE:
-003f1c 0030 .dw EE_EHERE
-003f1d 3da0 .dw XT_EDEFERFETCH
-003f1e 3daa .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-003f1f ff04 .dw $ff04
-003f20 6568
-003f21 6572 .db "here"
-003f22 3f16 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-003f23 386f .dw PFA_DOVALUE1
- PFA_HERE:
-003f24 002e .dw EE_HERE
-003f25 3da0 .dw XT_EDEFERFETCH
-003f26 3daa .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-003f27 ff05 .dw $ff05
-003f28 6c61
-003f29 6f6c
-003f2a 0074 .db "allot",0
-003f2b 3f1f .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-003f2c 3801 .dw DO_COLON
- PFA_ALLOT:
-003f2d 3f23 .dw XT_HERE
-003f2e 399d .dw XT_PLUS
-003f2f 01b4 .dw XT_DOTO
-003f30 3f24 .dw PFA_HERE
-003f31 3820 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-003f32 ff03 .dw $ff03
-003f33 6962
-003f34 006e .db "bin",0
-003f35 3f27 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-003f36 3801 .dw DO_COLON
- PFA_BIN:
- .endif
-003f37 3feb .dw XT_TWO
-003f38 3ebd .dw XT_BASE
-003f39 3881 .dw XT_STORE
-003f3a 3820 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-003f3b ff07 .dw $ff07
-003f3c 6564
-003f3d 6963
-003f3e 616d
-003f3f 006c .db "decimal",0
-003f40 3f32 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-003f41 3801 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-003f42 383d .dw XT_DOLITERAL
-003f43 000a .dw 10
-003f44 3ebd .dw XT_BASE
-003f45 3881 .dw XT_STORE
-003f46 3820 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-003f47 ff03 .dw $ff03
-003f48 6568
-003f49 0078 .db "hex",0
-003f4a 3f3b .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-003f4b 3801 .dw DO_COLON
- PFA_HEX:
- .endif
-003f4c 383d .dw XT_DOLITERAL
-003f4d 0010 .dw 16
-003f4e 3ebd .dw XT_BASE
-003f4f 3881 .dw XT_STORE
-003f50 3820 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-003f51 ff02 .dw $ff02
-003f52 6c62 .db "bl"
-003f53 3f47 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-003f54 3848 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-003f55 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-003f56 ff07 .dw $ff07
-003f57 7574
-003f58 6e72
-003f59 656b
-003f5a 0079 .db "turnkey",0
-003f5b 3f51 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-003f5c 3dff .dw PFA_DODEFER1
- PFA_TURNKEY:
-003f5d 0038 .dw CFG_TURNKEY
-003f5e 3da0 .dw XT_EDEFERFETCH
-003f5f 3daa .dw XT_EDEFERSTORE
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-003f60 ff07 .dw $ff07
-003f61 6f74
-003f62 7075
-003f63 6570
-003f64 0072 .db "toupper",0
-003f65 3f56 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-003f66 3801 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-003f67 38b1 .dw XT_DUP
-003f68 383d .dw XT_DOLITERAL
-003f69 0061 .dw 'a'
-003f6a 383d .dw XT_DOLITERAL
-003f6b 007b .dw 'z'+1
-003f6c 3e57 .dw XT_WITHIN
-003f6d 3836 .dw XT_DOCONDBRANCH
-003f6e 3f72 DEST(PFA_TOUPPER0)
-003f6f 383d .dw XT_DOLITERAL
-003f70 00df .dw 223 ; inverse of 0x20: 0xdf
-003f71 3a13 .dw XT_AND
- PFA_TOUPPER0:
-003f72 3820 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-003f73 ff07 .dw $ff07
-003f74 6f74
-003f75 6f6c
-003f76 6577
-003f77 0072 .db "tolower",0
-003f78 3f60 .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-003f79 3801 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-003f7a 38b1 .dw XT_DUP
-003f7b 383d .dw XT_DOLITERAL
-003f7c 0041 .dw 'A'
-003f7d 383d .dw XT_DOLITERAL
-003f7e 005b .dw 'Z'+1
-003f7f 3e57 .dw XT_WITHIN
-003f80 3836 .dw XT_DOCONDBRANCH
-003f81 3f85 DEST(PFA_TOLOWER0)
-003f82 383d .dw XT_DOLITERAL
-003f83 0020 .dw 32
-003f84 3a1c .dw XT_OR
- PFA_TOLOWER0:
-003f85 3820 .dw XT_EXIT
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-003f86 ff06 .dw $ff06
-003f87 733f
-003f88 6174
-003f89 6b63 .db "?stack"
-003f8a 3f73 .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-003f8b 3801 .dw DO_COLON
- PFA_QSTACK:
- .endif
-003f8c 05e2 .dw XT_DEPTH
-003f8d 3921 .dw XT_ZEROLESS
-003f8e 3836 .dw XT_DOCONDBRANCH
-003f8f 3f93 DEST(PFA_QSTACK1)
-003f90 383d .dw XT_DOLITERAL
-003f91 fffc .dw -4
-003f92 3d86 .dw XT_THROW
- PFA_QSTACK1:
-003f93 3820 .dw XT_EXIT
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-003f94 ff06 .dw $ff06
-003f95 6f62
-003f96 6e75
-003f97 7364 .db "bounds"
-003f98 3f86 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-003f99 3801 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-003f9a 38cf .dw XT_OVER
-003f9b 399d .dw XT_PLUS
-003f9c 38c4 .dw XT_SWAP
-003f9d 3820 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-003f9e ff02 .dw 0xff02
-003f9f 7263 .db "cr"
-003fa0 3f94 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-003fa1 3801 .dw DO_COLON
- PFA_CR:
- .endif
-
-003fa2 383d .dw XT_DOLITERAL
-003fa3 000d .dw 13
-003fa4 3ef2 .dw XT_EMIT
-003fa5 383d .dw XT_DOLITERAL
-003fa6 000a .dw 10
-003fa7 3ef2 .dw XT_EMIT
-003fa8 3820 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-003fa9 ff05 .dw $ff05
-003faa 7073
-003fab 6361
-003fac 0065 .db "space",0
-003fad 3f9e .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-003fae 3801 .dw DO_COLON
- PFA_SPACE:
- .endif
-003faf 3f54 .dw XT_BL
-003fb0 3ef2 .dw XT_EMIT
-003fb1 3820 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-003fb2 ff06 .dw $ff06
-003fb3 7073
-003fb4 6361
-003fb5 7365 .db "spaces"
-003fb6 3fa9 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-003fb7 3801 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-003fb8 3954
-003fb9 3e4a .DW XT_ZERO, XT_MAX
-003fba 38b1
-003fbb 3836 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-003fbc 3fc1 DEST(SPCS2)
-003fbd 3fae
-003fbe 3a35
-003fbf 382f .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-003fc0 3fba DEST(SPCS1)
-003fc1 38d9
-003fc2 3820 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-003fc3 ff03 .dw $ff03
-003fc4 3e73
-003fc5 0064 .db "s>d",0
-003fc6 3fb2 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-003fc7 3801 .dw DO_COLON
- PFA_S2D:
- .endif
-003fc8 38b1 .dw XT_DUP
-003fc9 3921 .dw XT_ZEROLESS
-003fca 3820 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-003fcb ff05 .dw $ff05
-003fcc 623e
-003fcd 646f
-003fce 0079 .db ">body",0
-003fcf 3fc3 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-003fd0 3a30 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-003fd1 0008 .dw $0008
-003fd2 6c32
-003fd3 7469
-003fd4 7265
-003fd5 6c61 .db "2literal"
-003fd6 3fcb .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-003fd7 3801 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-003fd8 38c4 .dw XT_SWAP
-003fd9 0772 .dw XT_LITERAL
-003fda 0772 .dw XT_LITERAL
-003fdb 3820 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-003fdc ff01 .dw $ff01
-003fdd 003d .db "=",0
-003fde 3fd1 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-003fdf 3801 .dw DO_COLON
- PFA_EQUAL:
-003fe0 3993 .dw XT_MINUS
-003fe1 391a .dw XT_ZEROEQUAL
-003fe2 3820 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-003fe3 ff01 .dw $ff01
-003fe4 0031 .db "1",0
-003fe5 3fdc .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-003fe6 3848 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-003fe7 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-003fe8 ff01 .dw $ff01
-003fe9 0032 .db "2",0
-003fea 3fe3 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-003feb 3848 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-003fec 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-003fed ff02 .dw $ff02
-003fee 312d .db "-1"
-003fef 3fe8 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-003ff0 3848 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-003ff1 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-00002a ff ff
- ; some configs
-00002c 1b 0b CFG_DP: .dw DPSTART ; Dictionary Pointer
-00002e 1d 01 EE_HERE: .dw HERESTART ; Memory Allocation
-000030 84 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-000032 c3 09 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-000034 52 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000036 10 08 CFG_LP0: .dw stackstart+1
-000038 6d 0a CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-00003a f4 02 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-00003c 3e 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-00003e ed 3f CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-000040 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-000042 3e 00 .dw CFG_FORTHWORDLIST ; get/set-order
-000044 .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-000052 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-000054 65 06 .dw XT_REC_FIND
-000056 51 06 .dw XT_REC_NUM
-000058 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-00005c 7e 3b .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-00005e 5e 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-000060 00 00 .dw 0 ; USER_STATE
-000062 00 00 .dw 0 ; USER_FOLLOWER
-000064 5f 08 .dw rstackstart ; USER_RP
-000066 0f 08 .dw stackstart ; USER_SP0
-000068 0f 08 .dw stackstart ; USER_SP
-
-00006a 00 00 .dw 0 ; USER_HANDLER
-00006c 0a 00 .dw 10 ; USER_BASE
-
-00006e 98 00 .dw XT_TX ; USER_EMIT
-000070 a6 00 .dw XT_TXQ ; USER_EMITQ
-000072 6d 00 .dw XT_RX ; USER_KEY
-000074 88 00 .dw XT_RXQ ; USER_KEYQ
-000076 6c 02 .dw XT_SOURCETIB ; USER_SOURCE
-000078 00 00 .dw 0 ; USER_G_IN
-00007a 59 02 .dw XT_REFILLTIB ; USER_REFILL
-00007c c9 3c .dw XT_DEFAULT_PROMPTOK
-00007e e8 3c .dw XT_DEFAULT_PROMPTERROR
-000080 d8 3c .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-000082 0c 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega32" register use summary:
-r0 : 25 r1 : 5 r2 : 10 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 89 r17: 61 r18: 61 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 212 r25: 145 r26: 28 r27: 17 r28: 7 r29: 4 r30: 90 r31: 49
-x : 4 y : 217 z : 50
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega32" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 22 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 1
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 14 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 25 inc : 3 jmp : 13
-ld : 145 ldd : 4 ldi : 41 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 16 movw : 72 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 2 out : 22 pop : 49
-push : 43 rcall : 34 ret : 7 reti : 1 rjmp : 106 rol : 23
-ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3 sbis : 0
-sbiw : 16 sbr : 0 sbrc : 5 sbrs : 7 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 4 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 81 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 72 out of 113 (63.7%)
-
-"ATmega32" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x007fe4 2072 11708 13780 32768 42.1%
-[.dseg] 0x000060 0x00011d 0 189 189 2048 9.2%
-[.eseg] 0x000000 0x000084 0 132 132 1024 12.9%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/eval-pollin/p32-8.map b/amforth-6.5/appl/eval-pollin/p32-8.map
deleted file mode 100644
index 8968a65..0000000
--- a/amforth-6.5/appl/eval-pollin/p32-8.map
+++ /dev/null
@@ -1,1933 +0,0 @@
-
-AVRASM ver. 2.1.52 p32-8.asm Sun Apr 30 20:10:14 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000095
-EQU SIGNATURE_002 00000002
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU OCR0 0000003c
-EQU GICR 0000003b
-EQU GIFR 0000003a
-EQU TIMSK 00000039
-EQU TIFR 00000038
-EQU SPMCR 00000037
-EQU TWCR 00000036
-EQU MCUCR 00000035
-EQU MCUCSR 00000034
-EQU TCCR0 00000033
-EQU TCNT0 00000032
-EQU OSCCAL 00000031
-EQU OCDR 00000031
-EQU SFIOR 00000030
-EQU TCCR1A 0000002f
-EQU TCCR1B 0000002e
-EQU TCNT1L 0000002c
-EQU TCNT1H 0000002d
-EQU OCR1AL 0000002a
-EQU OCR1AH 0000002b
-EQU OCR1BL 00000028
-EQU OCR1BH 00000029
-EQU ICR1L 00000026
-EQU ICR1H 00000027
-EQU TCCR2 00000025
-EQU TCNT2 00000024
-EQU OCR2 00000023
-EQU ASSR 00000022
-EQU WDTCR 00000021
-EQU UBRRH 00000020
-EQU UCSRC 00000020
-EQU EEARL 0000001e
-EQU EEARH 0000001f
-EQU EEDR 0000001d
-EQU EECR 0000001c
-EQU PORTA 0000001b
-EQU DDRA 0000001a
-EQU PINA 00000019
-EQU PORTB 00000018
-EQU DDRB 00000017
-EQU PINB 00000016
-EQU PORTC 00000015
-EQU DDRC 00000014
-EQU PINC 00000013
-EQU PORTD 00000012
-EQU DDRD 00000011
-EQU PIND 00000010
-EQU SPDR 0000000f
-EQU SPSR 0000000e
-EQU SPCR 0000000d
-EQU UDR 0000000c
-EQU UCSRA 0000000b
-EQU UCSRB 0000000a
-EQU UBRRL 00000009
-EQU ACSR 00000008
-EQU ADMUX 00000007
-EQU ADCSRA 00000006
-EQU ADCH 00000005
-EQU ADCL 00000004
-EQU TWDR 00000003
-EQU TWAR 00000002
-EQU TWSR 00000001
-EQU TWBR 00000000
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEWE 00000001
-EQU EEMWE 00000002
-EQU EERIE 00000003
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDTOE 00000004
-EQU WDDE 00000004
-EQU GIMSK 0000003b
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU INT2 00000005
-EQU INT0 00000006
-EQU INT1 00000007
-EQU INTF2 00000005
-EQU INTF0 00000006
-EQU INTF1 00000007
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC2 00000006
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM01 00000003
-EQU CTC0 00000003
-EQU COM00 00000004
-EQU COM01 00000005
-EQU WGM00 00000006
-EQU PWM0 00000006
-EQU FOC0 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0_0 00000000
-EQU OCR0_1 00000001
-EQU OCR0_2 00000002
-EQU OCR0_3 00000003
-EQU OCR0_4 00000004
-EQU OCR0_5 00000005
-EQU OCR0_6 00000006
-EQU OCR0_7 00000007
-EQU TOIE0 00000000
-EQU OCIE0 00000001
-EQU TOV0 00000000
-EQU OCF0 00000001
-EQU TOIE2 00000006
-EQU OCIE2 00000007
-EQU TOV2 00000006
-EQU OCF2 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM21 00000003
-EQU CTC2 00000003
-EQU COM20 00000004
-EQU COM21 00000005
-EQU WGM20 00000006
-EQU PWM2 00000006
-EQU FOC2 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2_0 00000000
-EQU OCR2_1 00000001
-EQU OCR2_2 00000002
-EQU OCR2_3 00000003
-EQU OCR2_4 00000004
-EQU OCR2_5 00000005
-EQU OCR2_6 00000006
-EQU OCR2_7 00000007
-EQU TCR2UB 00000000
-EQU OCR2UB 00000001
-EQU TCN2UB 00000002
-EQU AS2 00000003
-EQU TOIE1 00000002
-EQU OCIE1B 00000003
-EQU OCIE1A 00000004
-EQU TICIE1 00000005
-EQU TOV1 00000002
-EQU OCF1B 00000003
-EQU OCF1A 00000004
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU PWM10 00000000
-EQU WGM11 00000001
-EQU PWM11 00000001
-EQU FOC1B 00000002
-EQU FOC1A 00000003
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU CTC10 00000003
-EQU CTC1 00000003
-EQU WGM13 00000004
-EQU CTC11 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU UDR0 00000000
-EQU UDR1 00000001
-EQU UDR2 00000002
-EQU UDR3 00000003
-EQU UDR4 00000004
-EQU UDR5 00000005
-EQU UDR6 00000006
-EQU UDR7 00000007
-EQU USR 0000000b
-EQU MPCM 00000000
-EQU U2X 00000001
-EQU UPE 00000002
-EQU PE 00000002
-EQU DOR 00000003
-EQU FE 00000004
-EQU UDRE 00000005
-EQU TXC 00000006
-EQU RXC 00000007
-EQU UCR 0000000a
-EQU TXB8 00000000
-EQU RXB8 00000001
-EQU UCSZ2 00000002
-EQU CHR9 00000002
-EQU TXEN 00000003
-EQU RXEN 00000004
-EQU UDRIE 00000005
-EQU TXCIE 00000006
-EQU RXCIE 00000007
-EQU UCPOL 00000000
-EQU UCSZ0 00000001
-EQU UCSZ1 00000002
-EQU USBS 00000003
-EQU UPM0 00000004
-EQU UPM1 00000005
-EQU UMSEL 00000006
-EQU URSEL 00000007
-EQU UBRRHI 00000020
-EQU ACME 00000003
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADCSR 00000006
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADFR 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADTS0 00000005
-EQU ADTS1 00000006
-EQU ADTS2 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU SM0 00000004
-EQU SM1 00000005
-EQU SM2 00000006
-EQU SE 00000007
-EQU MCUSR 00000034
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU JTRF 00000004
-EQU JTD 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU PSR10 00000000
-EQU PSR2 00000001
-EQU PUD 00000002
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU ASRE 00000004
-EQU RWWSB 00000006
-EQU ASB 00000006
-EQU SPMIE 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU BODEN 00000006
-EQU BODLEVEL 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00003fff
-EQU IOEND 0000003f
-EQU SRAM_START 00000060
-EQU SRAM_SIZE 00000800
-EQU RAMEND 0000085f
-EQU XRAMEND 00000000
-EQU E2END 000003ff
-EQU EEPROMEND 000003ff
-EQU EEADRBITS 0000000a
-EQU NRWW_START_ADDR 00003800
-EQU NRWW_STOP_ADDR 00003fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 000037ff
-EQU PAGESIZE 00000040
-EQU FIRSTBOOTSTART 00003f00
-EQU SECONDBOOTSTART 00003e00
-EQU THIRDBOOTSTART 00003c00
-EQU FOURTHBOOTSTART 00003800
-EQU SMALLBOOTSTART 00003f00
-EQU LARGEBOOTSTART 00003800
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU OC2addr 00000008
-EQU OVF2addr 0000000a
-EQU ICP1addr 0000000c
-EQU OC1Aaddr 0000000e
-EQU OC1Baddr 00000010
-EQU OVF1addr 00000012
-EQU OC0addr 00000014
-EQU OVF0addr 00000016
-EQU SPIaddr 00000018
-EQU URXCaddr 0000001a
-EQU UDREaddr 0000001c
-EQU UTXCaddr 0000001e
-EQU ADCCaddr 00000020
-EQU ERDYaddr 00000022
-EQU ACIaddr 00000024
-EQU TWIaddr 00000026
-EQU SPMRaddr 00000028
-EQU INT_VECTORS_SIZE 0000002a
-EQU ramstart 00000060
-EQU CELLSIZE 00000002
-SET WANT_EEPROM 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_SPI 00000000
-SET WANT_USART 00000000
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_CPU 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_TWI 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 0000011e
-EQU INTVECTORS 00000015
-EQU SPMCSR 00000037
-EQU EEPE 00000001
-EQU EEMPE 00000002
-CSEG mcu_info 00000029
-CSEG mcu_ramsize 00000029
-CSEG mcu_eepromsize 0000002a
-CSEG mcu_maxdp 0000002b
-CSEG mcu_numints 0000002c
-CSEG mcu_name 0000002d
-SET codestart 00000032
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 0000085f
-SET stackstart 0000080f
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000001e
-SET VE_HEAD 00003fed
-SET VE_ENVHEAD 000002f4
-SET AMFORTH_RO_SEG 00003801
-EQU F_CPU 007a1200
-EQU TIMER_INT 0000000a
-EQU BAUDRATE_LOW 00000029
-EQU BAUDRATE_HIGH 00000040
-EQU USART_C 00000040
-EQU USART_B 0000002a
-EQU USART_A 0000002b
-EQU USART_DATA 0000002c
-EQU bm_USARTC_en 00000080
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000060
-DSEG usart_rx_in 00000070
-DSEG usart_rx_out 00000071
-CSEG VE_TO_RXBUF 00000032
-CSEG XT_TO_RXBUF 00000038
-CSEG PFA_rx_tobuf 00000039
-CSEG DO_NEXT 00003805
-CSEG VE_ISR_RX 00000049
-CSEG XT_ISR_RX 0000004e
-CSEG DO_COLON 00003801
-CSEG usart_rx_isr 0000004f
-CSEG XT_DOLITERAL 0000383d
-CSEG XT_CFETCH 00003898
-CSEG XT_DUP 000038b1
-CSEG XT_EQUAL 00003fdf
-CSEG XT_DOCONDBRANCH 00003836
-CSEG usart_rx_isr1 00000059
-CSEG XT_COLD 00003d38
-CSEG XT_EXIT 00003820
-CSEG XT_USART_INIT_RX_BUFFER 0000005b
-CSEG PFA_USART_INIT_RX_BUFFER 0000005c
-CSEG XT_INTSTORE 00003ca5
-CSEG XT_ZERO 00003954
-CSEG XT_FILL 00003e98
-CSEG VE_RX_BUFFER 00000068
-CSEG XT_RX_BUFFER 0000006d
-CSEG PFA_RX_BUFFER 0000006e
-CSEG XT_RXQ_BUFFER 00000088
-CSEG XT_PLUS 0000399d
-CSEG XT_SWAP 000038c4
-CSEG XT_1PLUS 00003a2f
-CSEG XT_AND 00003a13
-CSEG XT_CSTORE 0000388d
-CSEG VE_RXQ_BUFFER 00000082
-CSEG PFA_RXQ_BUFFER 00000089
-CSEG XT_PAUSE 00003d30
-CSEG XT_NOTEQUAL 00003913
-SET XT_RX 0000006d
-SET XT_RXQ 00000088
-SET XT_USART_INIT_RX 0000005b
-CSEG VE_TX_POLL 00000092
-CSEG XT_TX_POLL 00000098
-CSEG PFA_TX_POLL 00000099
-CSEG XT_TXQ_POLL 000000a6
-CSEG VE_TXQ_POLL 000000a0
-CSEG PFA_TXQ_POLL 000000a7
-SET XT_TX 00000098
-SET XT_TXQ 000000a6
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000af
-CSEG XT_UBRR 000000b3
-CSEG PFA_DOVALUE1 0000386f
-CSEG PFA_UBRR 000000b4
-ESEG EE_UBRRVAL 00000082
-CSEG XT_EDEFERFETCH 00003da0
-CSEG XT_EDEFERSTORE 00003daa
-CSEG VE_USART 000000b7
-CSEG XT_USART 000000bc
-CSEG PFA_USART 000000bd
-CSEG XT_BYTESWAP 00003af9
-EQU OW_PORT 00000018
-EQU OW_BIT 00000004
-SET OW_DDR 00000017
-SET OW_PIN 00000016
-CSEG VE_OW_RESET 000000d2
-CSEG XT_OW_RESET 000000d8
-CSEG PFA_OW_RESET 000000d9
-SET cycles 00000000
-SET loop_cycles 000007d0
-CSEG VE_OW_SLOT 000000f6
-CSEG XT_OW_SLOT 000000fc
-CSEG PFA_OW_SLOT 000000fd
-CSEG PFA_OW_SLOT0 0000010a
-SET AMFORTH_NRWW_SIZE 00000ffc
-SET corepc 0000011e
-CSEG PFA_COLD 00003d39
-ESEG intvec 00000000
-DSEG intcnt 00000072
-CSEG VE_MPLUS 00000135
-CSEG XT_MPLUS 00000138
-CSEG PFA_MPLUS 00000139
-CSEG XT_S2D 00003fc7
-CSEG XT_DPLUS 00003c15
-CSEG VE_UDSTAR 0000013c
-CSEG XT_UDSTAR 00000140
-CSEG PFA_UDSTAR 00000141
-CSEG XT_TO_R 000038ff
-CSEG XT_UMSTAR 000039e0
-CSEG XT_DROP 000038d9
-CSEG XT_R_FROM 000038f6
-CSEG XT_ROT 000038e1
-CSEG VE_UMAX 0000014b
-CSEG XT_UMAX 0000014f
-CSEG PFA_UMAX 00000150
-CSEG XT_2DUP 00003ec9
-CSEG XT_ULESS 0000395c
-CSEG UMAX1 00000155
-CSEG VE_UMIN 00000157
-CSEG XT_UMIN 0000015b
-CSEG PFA_UMIN 0000015c
-CSEG XT_UGREATER 00003967
-CSEG UMIN1 00000161
-CSEG XT_IMMEDIATEQ 00000163
-CSEG PFA_IMMEDIATEQ 00000164
-CSEG XT_ZEROEQUAL 0000391a
-CSEG IMMEDIATEQ1 0000016c
-CSEG XT_ONE 00003fe6
-CSEG XT_TRUE 0000394b
-CSEG VE_NAME2FLAGS 0000016e
-CSEG XT_NAME2FLAGS 00000175
-CSEG PFA_NAME2FLAGS 00000176
-CSEG XT_FETCHI 00003bcb
-CSEG VE_DOT_VER 0000017b
-CSEG XT_DOT_VER 0000017f
-CSEG PFA_DOT_VER 00000180
-CSEG XT_ENV_FORTHNAME 000002cf
-CSEG XT_ITYPE 000003f8
-CSEG XT_SPACE 00003fae
-CSEG XT_BASE 00003ebd
-CSEG XT_FETCH 00003879
-CSEG XT_ENV_FORTHVERSION 000002dd
-CSEG XT_DECIMAL 00003f41
-CSEG XT_L_SHARP 00000316
-CSEG XT_SHARP 0000031e
-CSEG XT_HOLD 00000307
-CSEG XT_SHARP_S 00000334
-CSEG XT_SHARP_G 0000033f
-CSEG XT_TYPE 0000042e
-CSEG XT_STORE 00003881
-CSEG XT_ENV_CPU 000002e5
-CSEG VE_NOOP 00000196
-CSEG XT_NOOP 0000019a
-CSEG PFA_NOOP 0000019b
-CSEG VE_UNUSED 0000019c
-CSEG XT_UNUSED 000001a1
-CSEG PFA_UNUSED 000001a2
-CSEG XT_SP_FETCH 00003a8d
-CSEG XT_HERE 00003f23
-CSEG XT_MINUS 00003993
-CSEG VE_TO 000001a6
-CSEG XT_TO 000001a9
-CSEG PFA_TO 000001aa
-CSEG XT_TICK 0000043d
-CSEG XT_TO_BODY 00003fd0
-CSEG XT_STATE 00003eb7
-CSEG PFA_TO1 000001ba
-CSEG XT_COMPILE 00000751
-CSEG XT_DOTO 000001b4
-CSEG XT_COMMA 0000075c
-CSEG PFA_DOTO 000001b5
-CSEG XT_ICELLPLUS 000001c6
-CSEG XT_EXECUTE 0000382a
-CSEG VE_ICELLPLUS 000001c0
-CSEG PFA_ICELLPLUS 000001c7
-CSEG VE_ICOMPARE 000001c9
-CSEG XT_ICOMPARE 000001cf
-CSEG PFA_ICOMPARE 000001d0
-CSEG XT_OVER 000038cf
-CSEG PFA_ICOMPARE_SAMELEN 000001da
-CSEG XT_2DROP 00003ed2
-CSEG XT_QDOCHECK 0000081b
-CSEG PFA_ICOMPARE_DONE 000001fd
-CSEG XT_DODO 00003a9b
-CSEG PFA_ICOMPARE_LOOP 000001e0
-CSEG PFA_ICOMPARE_LASTCELL 000001ee
-CSEG PFA_ICOMPARE_NEXTLOOP 000001f5
-CSEG XT_UNLOOP 00003ad4
-CSEG XT_CELLPLUS 00003c90
-CSEG XT_DOPLUSLOOP 00003aba
-CSEG VE_STAR 00000200
-CSEG XT_STAR 00000203
-CSEG PFA_STAR 00000204
-CSEG XT_MSTAR 000039a6
-CSEG VE_J 00000207
-CSEG XT_J 0000020a
-CSEG PFA_J 0000020b
-CSEG XT_RP_FETCH 00003a76
-CSEG VE_DABS 00000217
-CSEG XT_DABS 0000021b
-CSEG PFA_DABS 0000021c
-CSEG XT_ZEROLESS 00003921
-CSEG PFA_DABS1 00000221
-CSEG XT_DNEGATE 00000228
-CSEG VE_DNEGATE 00000222
-CSEG PFA_DNEGATE 00000229
-CSEG XT_DINVERT 00003c3b
-CSEG VE_CMOVE 0000022e
-CSEG XT_CMOVE 00000233
-CSEG PFA_CMOVE 00000234
-CSEG PFA_CMOVE1 00000241
-CSEG PFA_CMOVE2 0000023d
-CSEG VE_2SWAP 00000247
-CSEG XT_2SWAP 0000024c
-CSEG PFA_2SWAP 0000024d
-CSEG VE_REFILLTIB 00000252
-CSEG XT_REFILLTIB 00000259
-CSEG PFA_REFILLTIB 0000025a
-CSEG XT_TIB 00000275
-CSEG XT_ACCEPT 0000048d
-CSEG XT_NUMBERTIB 0000027b
-CSEG XT_TO_IN 00003ee2
-CSEG VE_SOURCETIB 00000265
-CSEG XT_SOURCETIB 0000026c
-CSEG PFA_SOURCETIB 0000026d
-CSEG VE_TIB 00000271
-CSEG PFA_DOVARIABLE 00003848
-CSEG PFA_TIB 00000276
-DSEG ram_tib 00000087
-CSEG VE_NUMBERTIB 00000277
-CSEG PFA_NUMBERTIB 0000027c
-DSEG ram_sharptib 000000e1
-CSEG VE_EE2RAM 0000027d
-CSEG XT_EE2RAM 00000282
-CSEG PFA_EE2RAM 00000283
-CSEG PFA_EE2RAM_1 00000285
-CSEG XT_FETCHE 00003b5f
-CSEG XT_DOLOOP 00003ac9
-CSEG PFA_EE2RAM_2 0000028f
-CSEG VE_INIT_RAM 00000291
-CSEG XT_INIT_RAM 00000297
-CSEG PFA_INI_RAM 00000298
-ESEG EE_INITUSER 00000060
-CSEG XT_UP_FETCH 00003b02
-CSEG XT_2SLASH 00003a04
-CSEG VE_ENVIRONMENT 000002a0
-CSEG XT_ENVIRONMENT 000002a8
-CSEG PFA_ENVIRONMENT 000002a9
-ESEG CFG_ENVIRONMENT 0000003a
-CSEG VE_ENVWORDLISTS 000002aa
-CSEG XT_ENVWORDLISTS 000002b1
-CSEG PFA_ENVWORDLISTS 000002b2
-CSEG VE_ENVSLASHPAD 000002b5
-CSEG XT_ENVSLASHPAD 000002b9
-CSEG PFA_ENVSLASHPAD 000002ba
-CSEG XT_PAD 00003ee8
-CSEG VE_ENVSLASHHOLD 000002be
-CSEG XT_ENVSLASHHOLD 000002c3
-CSEG PFA_ENVSLASHHOLD 000002c4
-CSEG VE_ENV_FORTHNAME 000002c8
-CSEG PFA_EN_FORTHNAME 000002d0
-CSEG XT_DOSLITERAL 000003c5
-CSEG VE_ENV_FORTHVERSION 000002d7
-CSEG PFA_EN_FORTHVERSION 000002de
-CSEG VE_ENV_CPU 000002e1
-CSEG PFA_EN_CPU 000002e6
-CSEG XT_ICOUNT 00000424
-CSEG VE_ENV_MCUINFO 000002ea
-CSEG XT_ENV_MCUINFO 000002f0
-CSEG PFA_EN_MCUINFO 000002f1
-CSEG VE_ENVUSERSIZE 000002f4
-CSEG XT_ENVUSERSIZE 000002f9
-CSEG PFA_ENVUSERSIZE 000002fa
-CSEG VE_HLD 000002fd
-CSEG XT_HLD 00000301
-CSEG PFA_HLD 00000302
-DSEG ram_hld 000000e3
-CSEG VE_HOLD 00000303
-CSEG PFA_HOLD 00000308
-CSEG XT_1MINUS 00003a35
-CSEG VE_L_SHARP 00000313
-CSEG PFA_L_SHARP 00000317
-CSEG VE_SHARP 0000031b
-CSEG PFA_SHARP 0000031f
-CSEG XT_UDSLASHMOD 0000039b
-CSEG XT_LESS 0000396e
-CSEG PFA_SHARP1 0000032c
-CSEG VE_SHARP_S 00000331
-CSEG PFA_SHARP_S 00000335
-CSEG NUMS1 00000335
-CSEG XT_OR 00003a1c
-CSEG VE_SHARP_G 0000033c
-CSEG PFA_SHARP_G 00000340
-CSEG VE_SIGN 00000347
-CSEG XT_SIGN 0000034b
-CSEG PFA_SIGN 0000034c
-CSEG PFA_SIGN1 00000352
-CSEG VE_DDOTR 00000353
-CSEG XT_DDOTR 00000357
-CSEG PFA_DDOTR 00000358
-CSEG XT_TUCK 00003eda
-CSEG XT_SPACES 00003fb7
-CSEG VE_DOTR 00000366
-CSEG XT_DOTR 00000369
-CSEG PFA_DOTR 0000036a
-CSEG VE_DDOT 0000036f
-CSEG XT_DDOT 00000372
-CSEG PFA_DDOT 00000373
-CSEG VE_DOT 00000377
-CSEG XT_DOT 0000037a
-CSEG PFA_DOT 0000037b
-CSEG VE_UDDOT 0000037e
-CSEG XT_UDDOT 00000382
-CSEG PFA_UDDOT 00000383
-CSEG XT_UDDOTR 0000038b
-CSEG VE_UDDOTR 00000387
-CSEG PFA_UDDOTR 0000038c
-CSEG VE_UDSLASHMOD 00000396
-CSEG PFA_UDSLASHMOD 0000039c
-CSEG XT_R_FETCH 00003908
-CSEG XT_UMSLASHMOD 000039c2
-CSEG VE_DIGITQ 000003a6
-CSEG XT_DIGITQ 000003ab
-CSEG PFA_DIGITQ 000003ac
-CSEG XT_TOUPPER 00003f66
-CSEG XT_GREATER 00003978
-CSEG PFA_DOSLITERAL 000003c6
-CSEG VE_SCOMMA 000003d0
-CSEG XT_SCOMMA 000003d3
-CSEG PFA_SCOMMA 000003d4
-CSEG XT_DOSCOMMA 000003d7
-CSEG PFA_DOSCOMMA 000003d8
-CSEG XT_2STAR 00003a0b
-CSEG PFA_SCOMMA2 000003ea
-CSEG PFA_SCOMMA1 000003e4
-CSEG XT_GREATERZERO 00003928
-CSEG PFA_SCOMMA3 000003f1
-CSEG VE_ITYPE 000003f3
-CSEG PFA_ITYPE 000003f9
-CSEG PFA_ITYPE2 0000040c
-CSEG PFA_ITYPE1 00000404
-CSEG XT_LOWEMIT 00000419
-CSEG XT_HIEMIT 00000415
-CSEG PFA_ITYPE3 00000413
-CSEG PFA_HIEMIT 00000416
-CSEG PFA_LOWEMIT 0000041a
-CSEG XT_EMIT 00003ef2
-CSEG VE_ICOUNT 0000041f
-CSEG PFA_ICOUNT 00000425
-CSEG VE_TYPE 0000042a
-CSEG PFA_TYPE 0000042f
-CSEG XT_BOUNDS 00003f99
-CSEG PFA_TYPE2 00000439
-CSEG PFA_TYPE1 00000434
-CSEG XT_I 00003aac
-CSEG VE_TICK 0000043a
-CSEG PFA_TICK 0000043e
-CSEG XT_PARSENAME 000005b0
-CSEG XT_FORTHRECOGNIZER 000005f3
-CSEG XT_RECOGNIZE 000005fe
-CSEG XT_DT_NULL 0000068b
-CSEG PFA_TICK1 0000044f
-CSEG XT_THROW 00003d86
-CSEG VE_CSKIP 00000451
-CSEG XT_CSKIP 00000456
-CSEG PFA_CSKIP 00000457
-CSEG PFA_CSKIP1 00000458
-CSEG PFA_CSKIP2 00000465
-CSEG XT_SLASHSTRING 000005a1
-CSEG XT_DOBRANCH 0000382f
-CSEG VE_CSCAN 00000468
-CSEG XT_CSCAN 0000046d
-CSEG PFA_CSCAN 0000046e
-CSEG PFA_CSCAN1 00000470
-CSEG PFA_CSCAN2 00000482
-CSEG XT_NIP 000038f0
-CSEG VE_ACCEPT 00000488
-CSEG PFA_ACCEPT 0000048e
-CSEG ACC1 00000492
-CSEG XT_KEY 00003f03
-CSEG XT_CRLFQ 000004ce
-CSEG ACC5 000004c0
-CSEG ACC3 000004b0
-CSEG ACC6 000004ae
-CSEG XT_BS 000004c6
-CSEG ACC4 000004be
-CSEG XT_BL 00003f54
-CSEG PFA_ACCEPT6 000004b7
-CSEG XT_CR 00003fa1
-CSEG VE_REFILL 000004d9
-CSEG XT_REFILL 000004de
-CSEG PFA_DODEFER1 00003dff
-CSEG PFA_REFILL 000004df
-CSEG XT_UDEFERFETCH 00003dc8
-CSEG XT_UDEFERSTORE 00003dd4
-CSEG VE_CHAR 000004e2
-CSEG XT_CHAR 000004e6
-CSEG PFA_CHAR 000004e7
-CSEG VE_NUMBER 000004eb
-CSEG XT_NUMBER 000004f0
-CSEG PFA_NUMBER 000004f1
-CSEG XT_QSIGN 00000534
-CSEG XT_SET_BASE 00000547
-CSEG PFA_NUMBER0 00000507
-CSEG XT_2TO_R 00003b1e
-CSEG XT_2R_FROM 00003b2d
-CSEG XT_TO_NUMBER 00000565
-CSEG XT_QDUP 000038b9
-CSEG PFA_NUMBER1 00000529
-CSEG PFA_NUMBER2 00000520
-CSEG PFA_NUMBER6 00000521
-CSEG PFA_NUMBER3 0000051d
-CSEG XT_TWO 00003feb
-CSEG PFA_NUMBER5 0000052f
-CSEG PFA_NUMBER4 0000052e
-CSEG XT_NEGATE 00003e27
-CSEG PFA_QSIGN 00000535
-CSEG PFA_NUMBERSIGN_DONE 00000540
-CSEG XT_BASES 00000542
-CSEG PFA_DOCONSTANT 00003852
-CSEG PFA_SET_BASE 00000548
-CSEG XT_WITHIN 00003e57
-CSEG SET_BASE1 0000055d
-CSEG SET_BASE2 0000055e
-CSEG VE_TO_NUMBER 0000055f
-CSEG TONUM1 00000566
-CSEG TONUM3 0000057d
-CSEG TONUM2 00000571
-CSEG VE_PARSE 0000057e
-CSEG XT_PARSE 00000583
-CSEG PFA_PARSE 00000584
-CSEG XT_SOURCE 00000597
-CSEG XT_PLUSSTORE 00003a65
-CSEG VE_SOURCE 00000592
-CSEG PFA_SOURCE 00000598
-CSEG VE_SLASHSTRING 0000059b
-CSEG PFA_SLASHSTRING 000005a2
-CSEG VE_PARSENAME 000005a9
-CSEG PFA_PARSENAME 000005b1
-CSEG XT_SKIPSCANCHAR 000005b4
-CSEG PFA_SKIPSCANCHAR 000005b5
-CSEG VE_SP0 000005c6
-CSEG XT_SP0 000005ca
-CSEG PFA_SP0 000005cb
-CSEG VE_SP 000005ce
-CSEG XT_SP 000005d1
-CSEG PFA_DOUSER 00003858
-CSEG PFA_SP 000005d2
-CSEG VE_RP0 000005d3
-CSEG XT_RP0 000005d7
-CSEG PFA_RP0 000005d8
-CSEG XT_DORP0 000005db
-CSEG PFA_DORP0 000005dc
-CSEG VE_DEPTH 000005dd
-CSEG XT_DEPTH 000005e2
-CSEG PFA_DEPTH 000005e3
-CSEG VE_FORTHRECOGNIZER 000005e9
-CSEG PFA_FORTHRECOGNIZER 000005f4
-ESEG CFG_FORTHRECOGNIZER 00000034
-CSEG VE_RECOGNIZE 000005f7
-CSEG PFA_RECOGNIZE 000005ff
-CSEG XT_RECOGNIZE_A 00000609
-CSEG XT_MAPSTACK 0000099c
-CSEG PFA_RECOGNIZE1 00000608
-CSEG PFA_RECOGNIZE_A 0000060a
-CSEG PFA_RECOGNIZE_A1 0000061a
-CSEG VE_INTERPRET 0000061e
-CSEG XT_INTERPRET 00000625
-CSEG PFA_INTERPRET 00000626
-CSEG PFA_INTERPRET2 00000636
-CSEG PFA_INTERPRET1 00000631
-CSEG XT_QSTACK 00003f8b
-CSEG VE_DT_NUM 00000638
-CSEG XT_DT_NUM 0000063d
-CSEG PFA_DT_NUM 0000063e
-CSEG XT_LITERAL 00000772
-CSEG VE_DT_DNUM 00000641
-CSEG XT_DT_DNUM 00000647
-CSEG PFA_DT_DNUM 00000648
-CSEG XT_2LITERAL 00003fd7
-CSEG VE_REC_NUM 0000064b
-CSEG XT_REC_NUM 00000651
-CSEG PFA_REC_NUM 00000652
-CSEG PFA_REC_NONUMBER 0000065d
-CSEG PFA_REC_INTNUM2 0000065b
-CSEG VE_REC_FIND 0000065f
-CSEG XT_REC_FIND 00000665
-CSEG PFA_REC_FIND 00000666
-CSEG XT_FINDXT 00000700
-CSEG PFA_REC_WORD_FOUND 0000066e
-CSEG XT_DT_XT 00000675
-CSEG VE_DT_XT 00000670
-CSEG PFA_DT_XT 00000676
-CSEG XT_R_WORD_INTERPRET 00000679
-CSEG XT_R_WORD_COMPILE 0000067d
-CSEG PFA_R_WORD_INTERPRET 0000067a
-CSEG PFA_R_WORD_COMPILE 0000067e
-CSEG PFA_R_WORD_COMPILE1 00000683
-CSEG VE_DT_NULL 00000685
-CSEG PFA_DT_NULL 0000068c
-CSEG XT_FAIL 0000068f
-CSEG PFA_FAIL 00000690
-CSEG VE_SEARCH_WORDLIST 00000693
-CSEG XT_SEARCH_WORDLIST 0000069d
-CSEG PFA_SEARCH_WORDLIST 0000069e
-CSEG XT_ISWORD 000006b2
-CSEG XT_TRAVERSEWORDLIST 000006cf
-CSEG PFA_SEARCH_WORDLIST1 000006ac
-CSEG XT_NFA2CFA 000006f6
-CSEG PFA_ISWORD 000006b3
-CSEG XT_NAME2STRING 000006ea
-CSEG PFA_ISWORD3 000006c0
-CSEG VE_TRAVERSEWORDLIST 000006c4
-CSEG PFA_TRAVERSEWORDLIST 000006d0
-CSEG PFA_TRAVERSEWORDLIST1 000006d1
-CSEG PFA_TRAVERSEWORDLIST2 000006e0
-CSEG XT_NFA2LFA 00000a0b
-CSEG VE_NAME2STRING 000006e2
-CSEG PFA_NAME2STRING 000006eb
-CSEG VE_NFA2CFA 000006f0
-CSEG PFA_NFA2CFA 000006f7
-CSEG VE_FINDXT 000006fa
-CSEG PFA_FINDXT 00000701
-CSEG XT_FINDXTA 0000070c
-ESEG CFG_ORDERLISTLEN 00000040
-CSEG PFA_FINDXT1 0000070b
-CSEG PFA_FINDXTA 0000070d
-CSEG PFA_FINDXTA1 00000719
-CSEG VE_NEWEST 0000071a
-CSEG XT_NEWEST 0000071f
-CSEG PFA_NEWEST 00000720
-DSEG ram_newest 000000e5
-CSEG VE_LATEST 00000721
-CSEG XT_LATEST 00000726
-CSEG PFA_LATEST 00000727
-DSEG ram_latest 000000e9
-CSEG VE_DOCREATE 00000728
-CSEG XT_DOCREATE 0000072e
-CSEG PFA_DOCREATE 0000072f
-CSEG XT_WLSCOPE 00000885
-CSEG XT_HEADER 0000086a
-CSEG VE_BACKSLASH 00000739
-CSEG XT_BACKSLASH 0000073c
-CSEG PFA_BACKSLASH 0000073d
-CSEG VE_LPAREN 00000742
-CSEG XT_LPAREN 00000745
-CSEG PFA_LPAREN 00000746
-CSEG VE_COMPILE 0000074b
-CSEG PFA_COMPILE 00000752
-CSEG VE_COMMA 00000759
-CSEG PFA_COMMA 0000075d
-CSEG XT_DP 00003f12
-CSEG XT_STOREI 00003b73
-CSEG PFA_DP 00003f13
-CSEG VE_BRACKETTICK 00000764
-CSEG XT_BRACKETTICK 00000768
-CSEG PFA_BRACKETTICK 00000769
-CSEG VE_LITERAL 0000076c
-CSEG PFA_LITERAL 00000773
-CSEG VE_SLITERAL 00000777
-CSEG XT_SLITERAL 0000077d
-CSEG PFA_SLITERAL 0000077e
-CSEG XT_GMARK 00000782
-CSEG PFA_GMARK 00000783
-CSEG XT_GRESOLVE 00000787
-CSEG PFA_GRESOLVE 00000788
-CSEG XT_LMARK 0000078d
-CSEG PFA_LMARK 0000078e
-CSEG XT_LRESOLVE 00000790
-CSEG PFA_LRESOLVE 00000791
-CSEG VE_AHEAD 00000794
-CSEG XT_AHEAD 00000799
-CSEG PFA_AHEAD 0000079a
-CSEG VE_IF 0000079e
-CSEG XT_IF 000007a1
-CSEG PFA_IF 000007a2
-CSEG VE_ELSE 000007a6
-CSEG XT_ELSE 000007aa
-CSEG PFA_ELSE 000007ab
-CSEG VE_THEN 000007b1
-CSEG XT_THEN 000007b5
-CSEG PFA_THEN 000007b6
-CSEG VE_BEGIN 000007b8
-CSEG XT_BEGIN 000007bd
-CSEG PFA_BEGIN 000007be
-CSEG VE_WHILE 000007c0
-CSEG XT_WHILE 000007c5
-CSEG PFA_WHILE 000007c6
-CSEG VE_REPEAT 000007c9
-CSEG XT_REPEAT 000007ce
-CSEG PFA_REPEAT 000007cf
-CSEG XT_AGAIN 000007e2
-CSEG VE_UNTIL 000007d2
-CSEG XT_UNTIL 000007d7
-CSEG PFA_UNTIL 000007d8
-CSEG VE_AGAIN 000007dd
-CSEG PFA_AGAIN 000007e3
-CSEG VE_DO 000007e7
-CSEG XT_DO 000007ea
-CSEG PFA_DO 000007eb
-CSEG XT_TO_L 00000845
-CSEG VE_LOOP 000007f1
-CSEG XT_LOOP 000007f5
-CSEG PFA_LOOP 000007f6
-CSEG XT_ENDLOOP 0000082c
-CSEG VE_PLUSLOOP 000007fa
-CSEG XT_PLUSLOOP 000007ff
-CSEG PFA_PLUSLOOP 00000800
-CSEG VE_LEAVE 00000804
-CSEG XT_LEAVE 00000809
-CSEG PFA_LEAVE 0000080a
-CSEG VE_QDO 0000080f
-CSEG XT_QDO 00000813
-CSEG PFA_QDO 00000814
-CSEG PFA_QDOCHECK 0000081c
-CSEG PFA_QDOCHECK1 00000823
-CSEG XT_INVERT 000039fd
-CSEG VE_ENDLOOP 00000826
-CSEG PFA_ENDLOOP 0000082d
-CSEG LOOP1 0000082e
-CSEG XT_L_FROM 00000839
-CSEG LOOP2 00000835
-CSEG VE_L_FROM 00000836
-CSEG PFA_L_FROM 0000083a
-CSEG XT_LP 00000858
-CSEG VE_TO_L 00000842
-CSEG PFA_TO_L 00000846
-CSEG VE_LP0 0000084d
-CSEG XT_LP0 00000851
-CSEG PFA_LP0 00000852
-ESEG CFG_LP0 00000036
-CSEG VE_LP 00000855
-CSEG PFA_LP 00000859
-DSEG ram_lp 000000eb
-CSEG VE_CREATE 0000085a
-CSEG XT_CREATE 0000085f
-CSEG PFA_CREATE 00000860
-CSEG XT_REVEAL 0000088e
-CSEG VE_HEADER 00000865
-CSEG PFA_HEADER 0000086b
-CSEG PFA_HEADER1 0000087c
-CSEG VE_WLSCOPE 0000087f
-CSEG PFA_WLSCOPE 00000886
-ESEG CFG_WLSCOPE 00000032
-CSEG VE_REVEAL 00000889
-CSEG PFA_REVEAL 0000088f
-CSEG REVEAL1 00000899
-CSEG XT_STOREE 00003b3b
-CSEG VE_DOES 0000089a
-CSEG XT_DOES 0000089f
-CSEG PFA_DOES 000008a0
-CSEG XT_DODOES 000008b2
-CSEG DO_DODOES 000008a7
-CSEG PFA_DODOES 000008b3
-CSEG VE_COLON 000008bb
-CSEG XT_COLON 000008be
-CSEG PFA_COLON 000008bf
-CSEG XT_COLONNONAME 000008c9
-CSEG VE_COLONNONAME 000008c3
-CSEG PFA_COLONNONAME 000008ca
-CSEG XT_RBRACKET 000008de
-CSEG VE_SEMICOLON 000008d2
-CSEG XT_SEMICOLON 000008d5
-CSEG PFA_SEMICOLON 000008d6
-CSEG XT_LBRACKET 000008e6
-CSEG VE_RBRACKET 000008db
-CSEG PFA_RBRACKET 000008df
-CSEG VE_LBRACKET 000008e3
-CSEG PFA_LBRACKET 000008e7
-CSEG VE_VARIABLE 000008eb
-CSEG XT_VARIABLE 000008f1
-CSEG PFA_VARIABLE 000008f2
-CSEG XT_CONSTANT 000008fd
-CSEG XT_ALLOT 00003f2c
-CSEG VE_CONSTANT 000008f7
-CSEG PFA_CONSTANT 000008fe
-CSEG VE_USER 00000904
-CSEG XT_USER 00000908
-CSEG PFA_USER 00000909
-CSEG VE_RECURSE 0000090f
-CSEG XT_RECURSE 00000915
-CSEG PFA_RECURSE 00000916
-CSEG VE_IMMEDIATE 0000091a
-CSEG XT_IMMEDIATE 00000921
-CSEG PFA_IMMEDIATE 00000922
-CSEG XT_GET_CURRENT 000009c3
-CSEG VE_BRACKETCHAR 0000092c
-CSEG XT_BRACKETCHAR 00000931
-CSEG PFA_BRACKETCHAR 00000932
-CSEG VE_ABORTQUOTE 00000937
-CSEG XT_ABORTQUOTE 0000093c
-CSEG PFA_ABORTQUOTE 0000093d
-CSEG XT_SQUOTE 00003e8a
-CSEG XT_QABORT 0000094e
-CSEG VE_ABORT 00000941
-CSEG XT_ABORT 00000946
-CSEG PFA_ABORT 00000947
-CSEG VE_QABORT 00000949
-CSEG PFA_QABORT 0000094f
-CSEG QABO1 00000954
-CSEG VE_GET_STACK 00000956
-CSEG XT_GET_STACK 0000095d
-CSEG PFA_N_FETCH_E2 00000974
-CSEG PFA_N_FETCH_E1 0000096a
-CSEG XT_CELLS 00003ec4
-CSEG VE_SET_STACK 00000977
-CSEG XT_SET_STACK 0000097e
-CSEG PFA_SET_STACK 0000097f
-CSEG PFA_SET_STACK0 00000986
-CSEG PFA_SET_STACK2 00000993
-CSEG PFA_SET_STACK1 0000098e
-CSEG VE_MAPSTACK 00000995
-CSEG PFA_MAPSTACK 0000099d
-CSEG PFA_MAPSTACK3 000009b8
-CSEG PFA_MAPSTACK1 000009a7
-CSEG PFA_MAPSTACK2 000009b4
-CSEG VE_GET_CURRENT 000009bb
-CSEG PFA_GET_CURRENT 000009c4
-ESEG CFG_CURRENT 0000003c
-CSEG VE_GET_ORDER 000009c8
-CSEG XT_GET_ORDER 000009cf
-CSEG PFA_GET_ORDER 000009d0
-CSEG VE_CFG_ORDER 000009d4
-CSEG XT_CFG_ORDER 000009db
-CSEG PFA_CFG_ORDER 000009dc
-CSEG VE_COMPARE 000009dd
-CSEG XT_COMPARE 000009e3
-CSEG PFA_COMPARE 000009e4
-CSEG PFA_COMPARE_LOOP 000009f0
-CSEG PFA_COMPARE_NOTEQUAL 000009fe
-CSEG PFA_COMPARE_ENDREACHED2 000009f9
-CSEG PFA_COMPARE_ENDREACHED 000009fa
-CSEG PFA_COMPARE_CHECKLASTCHAR 000009fe
-CSEG PFA_COMPARE_DONE 00000a00
-CSEG VE_NFA2LFA 00000a05
-CSEG PFA_NFA2LFA 00000a0c
-CSEG VE_DOTS 00000a11
-CSEG XT_DOTS 00000a14
-CSEG PFA_DOTS 00000a15
-CSEG XT_UDOT 00003e0a
-CSEG PFA_DOTS2 00000a23
-CSEG PFA_DOTS1 00000a1e
-CSEG XT_PICK 00003c84
-CSEG VE_SPIRW 00000a24
-CSEG XT_SPIRW 00000a29
-CSEG PFA_SPIRW 00000a2a
-CSEG do_spirw 00000a2e
-CSEG do_spirw1 00000a2f
-CSEG VE_N_SPIR 00000a37
-CSEG XT_N_SPIR 00000a3c
-CSEG PFA_N_SPIR 00000a3d
-CSEG PFA_N_SPIR_LOOP 00000a42
-CSEG PFA_N_SPIR_LOOP1 00000a43
-CSEG VE_N_SPIW 00000a4e
-CSEG XT_N_SPIW 00000a53
-CSEG PFA_N_SPIW 00000a54
-CSEG PFA_N_SPIW_LOOP 00000a59
-CSEG PFA_N_SPIW_LOOP1 00000a5b
-CSEG VE_APPLTURNKEY 00000a65
-CSEG XT_APPLTURNKEY 00000a6d
-CSEG PFA_APPLTURNKEY 00000a6e
-CSEG XT_INTON 00003c97
-CSEG XT_F_CPU 00003eac
-CSEG VE_SET_CURRENT 00000a7f
-CSEG XT_SET_CURRENT 00000a87
-CSEG PFA_SET_CURRENT 00000a88
-CSEG VE_WORDLIST 00000a8c
-CSEG XT_WORDLIST 00000a92
-CSEG PFA_WORDLIST 00000a93
-CSEG XT_EHERE 00003f1b
-CSEG PFA_EHERE 00003f1c
-CSEG VE_FORTHWORDLIST 00000a9c
-CSEG XT_FORTHWORDLIST 00000aa5
-CSEG PFA_FORTHWORDLIST 00000aa6
-ESEG CFG_FORTHWORDLIST 0000003e
-CSEG VE_SET_ORDER 00000aa7
-CSEG XT_SET_ORDER 00000aae
-CSEG PFA_SET_ORDER 00000aaf
-CSEG VE_SET_RECOGNIZERS 00000ab3
-CSEG XT_SET_RECOGNIZERS 00000abd
-CSEG PFA_SET_RECOGNIZERS 00000abe
-ESEG CFG_RECOGNIZERLISTLEN 00000052
-CSEG VE_GET_RECOGNIZERS 00000ac2
-CSEG XT_GET_RECOGNIZERS 00000acc
-CSEG PFA_GET_RECOGNIZERS 00000acd
-CSEG VE_CODE 00000ad1
-CSEG XT_CODE 00000ad5
-CSEG PFA_CODE 00000ad6
-CSEG VE_ENDCODE 00000adc
-CSEG XT_ENDCODE 00000ae2
-CSEG PFA_ENDCODE 00000ae3
-CSEG VE_MARKER 00000ae8
-CSEG XT_MARKER 00000aee
-CSEG PFA_MARKER 00000aef
-ESEG EE_MARKER 0000005e
-CSEG VE_POSTPONE 00000af2
-CSEG XT_POSTPONE 00000af8
-CSEG PFA_POSTPONE 00000af9
-CSEG VE_2R_FETCH 00000b07
-CSEG XT_2R_FETCH 00000b0b
-CSEG PFA_2R_FETCH 00000b0c
-SET DPSTART 00000b1b
-CSEG DO_INTERRUPT 00003814
-CSEG DO_EXECUTE 0000380d
-CSEG XT_ISREXEC 00003cc0
-CSEG VE_EXIT 0000381c
-CSEG PFA_EXIT 00003821
-CSEG VE_EXECUTE 00003824
-CSEG PFA_EXECUTE 0000382b
-CSEG PFA_DOBRANCH 00003830
-CSEG PFA_DOCONDBRANCH 00003837
-CSEG PFA_DOLITERAL 0000383e
-CSEG XT_DOVARIABLE 00003847
-CSEG XT_DOCONSTANT 00003851
-CSEG XT_DOUSER 00003857
-CSEG VE_DOVALUE 00003863
-CSEG XT_DOVALUE 00003869
-CSEG PFA_DOVALUE 0000386a
-CSEG VE_FETCH 00003876
-CSEG PFA_FETCH 0000387a
-CSEG PFA_FETCHRAM 0000387a
-CSEG VE_STORE 0000387e
-CSEG PFA_STORE 00003882
-CSEG PFA_STORERAM 00003882
-CSEG VE_CSTORE 0000388a
-CSEG PFA_CSTORE 0000388e
-CSEG VE_CFETCH 00003895
-CSEG PFA_CFETCH 00003899
-CSEG VE_FETCHU 0000389d
-CSEG XT_FETCHU 000038a0
-CSEG PFA_FETCHU 000038a1
-CSEG VE_STOREU 000038a5
-CSEG XT_STOREU 000038a8
-CSEG PFA_STOREU 000038a9
-CSEG VE_DUP 000038ad
-CSEG PFA_DUP 000038b2
-CSEG VE_QDUP 000038b5
-CSEG PFA_QDUP 000038ba
-CSEG PFA_QDUP1 000038bf
-CSEG VE_SWAP 000038c0
-CSEG PFA_SWAP 000038c5
-CSEG VE_OVER 000038cb
-CSEG PFA_OVER 000038d0
-CSEG VE_DROP 000038d5
-CSEG PFA_DROP 000038da
-CSEG VE_ROT 000038dd
-CSEG PFA_ROT 000038e2
-CSEG VE_NIP 000038ec
-CSEG PFA_NIP 000038f1
-CSEG VE_R_FROM 000038f3
-CSEG PFA_R_FROM 000038f7
-CSEG VE_TO_R 000038fc
-CSEG PFA_TO_R 00003900
-CSEG VE_R_FETCH 00003905
-CSEG PFA_R_FETCH 00003909
-CSEG VE_NOTEQUAL 00003910
-CSEG PFA_NOTEQUAL 00003914
-CSEG VE_ZEROEQUAL 00003917
-CSEG PFA_ZEROEQUAL 0000391b
-CSEG PFA_ZERO1 00003957
-CSEG PFA_TRUE1 0000394e
-CSEG VE_ZEROLESS 0000391e
-CSEG PFA_ZEROLESS 00003922
-CSEG VE_GREATERZERO 00003925
-CSEG PFA_GREATERZERO 00003929
-CSEG VE_DGREATERZERO 0000392e
-CSEG XT_DGREATERZERO 00003932
-CSEG PFA_DGREATERZERO 00003933
-CSEG VE_DXT_ZEROLESS 0000393c
-CSEG XT_DXT_ZEROLESS 00003940
-CSEG PFA_DXT_ZEROLESS 00003941
-CSEG VE_TRUE 00003947
-CSEG PFA_TRUE 0000394c
-CSEG VE_ZERO 00003951
-CSEG PFA_ZERO 00003955
-CSEG VE_ULESS 00003959
-CSEG PFA_ULESS 0000395d
-CSEG VE_UGREATER 00003964
-CSEG PFA_UGREATER 00003968
-CSEG VE_LESS 0000396b
-CSEG PFA_LESS 0000396f
-CSEG PFA_LESSDONE 00003973
-CSEG VE_GREATER 00003975
-CSEG PFA_GREATER 00003979
-CSEG PFA_GREATERDONE 0000397d
-CSEG VE_LOG2 00003980
-CSEG XT_LOG2 00003984
-CSEG PFA_LOG2 00003985
-CSEG PFA_LOG2_1 00003988
-CSEG PFA_LOG2_2 0000398e
-CSEG VE_MINUS 00003990
-CSEG PFA_MINUS 00003994
-CSEG VE_PLUS 0000399a
-CSEG PFA_PLUS 0000399e
-CSEG VE_MSTAR 000039a3
-CSEG PFA_MSTAR 000039a7
-CSEG VE_UMSLASHMOD 000039bd
-CSEG PFA_UMSLASHMOD 000039c3
-CSEG PFA_UMSLASHMODmod 000039c8
-CSEG PFA_UMSLASHMODmod_loop 000039c9
-CSEG PFA_UMSLASHMODmod_loop_control 000039d6
-CSEG PFA_UMSLASHMODmod_subtract 000039d3
-CSEG PFA_UMSLASHMODmod_done 000039d8
-CSEG VE_UMSTAR 000039dc
-CSEG PFA_UMSTAR 000039e1
-CSEG VE_INVERT 000039f8
-CSEG PFA_INVERT 000039fe
-CSEG VE_2SLASH 00003a01
-CSEG PFA_2SLASH 00003a05
-CSEG VE_2STAR 00003a08
-CSEG PFA_2STAR 00003a0c
-CSEG VE_AND 00003a0f
-CSEG PFA_AND 00003a14
-CSEG VE_OR 00003a19
-CSEG PFA_OR 00003a1d
-CSEG VE_XOR 00003a22
-CSEG XT_XOR 00003a26
-CSEG PFA_XOR 00003a27
-CSEG VE_1PLUS 00003a2c
-CSEG PFA_1PLUS 00003a30
-CSEG VE_1MINUS 00003a32
-CSEG PFA_1MINUS 00003a36
-CSEG VE_QNEGATE 00003a38
-CSEG XT_QNEGATE 00003a3e
-CSEG PFA_QNEGATE 00003a3f
-CSEG QNEG1 00003a43
-CSEG VE_LSHIFT 00003a44
-CSEG XT_LSHIFT 00003a49
-CSEG PFA_LSHIFT 00003a4a
-CSEG PFA_LSHIFT1 00003a4d
-CSEG PFA_LSHIFT2 00003a52
-CSEG VE_RSHIFT 00003a53
-CSEG XT_RSHIFT 00003a58
-CSEG PFA_RSHIFT 00003a59
-CSEG PFA_RSHIFT1 00003a5c
-CSEG PFA_RSHIFT2 00003a61
-CSEG VE_PLUSSTORE 00003a62
-CSEG PFA_PLUSSTORE 00003a66
-CSEG VE_RP_FETCH 00003a72
-CSEG PFA_RP_FETCH 00003a77
-CSEG VE_RP_STORE 00003a7c
-CSEG XT_RP_STORE 00003a80
-CSEG PFA_RP_STORE 00003a81
-CSEG VE_SP_FETCH 00003a89
-CSEG PFA_SP_FETCH 00003a8e
-CSEG VE_SP_STORE 00003a92
-CSEG XT_SP_STORE 00003a96
-CSEG PFA_SP_STORE 00003a97
-CSEG PFA_DODO 00003a9c
-CSEG PFA_DODO1 00003a9e
-CSEG VE_I 00003aa9
-CSEG PFA_I 00003aad
-CSEG PFA_DOPLUSLOOP 00003abb
-CSEG PFA_DOPLUSLOOP_LEAVE 00003ac5
-CSEG PFA_DOPLUSLOOP_NEXT 00003ac2
-CSEG PFA_DOLOOP 00003aca
-CSEG VE_UNLOOP 00003acf
-CSEG PFA_UNLOOP 00003ad5
-CSEG VE_CMOVE_G 00003ada
-CSEG XT_CMOVE_G 00003adf
-CSEG PFA_CMOVE_G 00003ae0
-CSEG PFA_CMOVE_G1 00003af1
-CSEG PFA_CMOVE_G2 00003aed
-CSEG VE_BYTESWAP 00003af6
-CSEG PFA_BYTESWAP 00003afa
-CSEG VE_UP_FETCH 00003afe
-CSEG PFA_UP_FETCH 00003b03
-CSEG VE_UP_STORE 00003b07
-CSEG XT_UP_STORE 00003b0b
-CSEG PFA_UP_STORE 00003b0c
-CSEG VE_1MS 00003b10
-CSEG XT_1MS 00003b14
-CSEG PFA_1MS 00003b15
-CSEG VE_2TO_R 00003b1a
-CSEG PFA_2TO_R 00003b1f
-CSEG VE_2R_FROM 00003b29
-CSEG PFA_2R_FROM 00003b2e
-CSEG VE_STOREE 00003b38
-CSEG PFA_STOREE 00003b3c
-CSEG PFA_STOREE0 00003b3c
-CSEG PFA_FETCHE2 00003b6a
-CSEG PFA_STOREE3 00003b46
-CSEG PFA_STOREE1 00003b51
-CSEG PFA_STOREE4 00003b4d
-CSEG PFA_STOREE2 00003b53
-CSEG VE_FETCHE 00003b5c
-CSEG PFA_FETCHE 00003b60
-CSEG PFA_FETCHE1 00003b60
-CSEG VE_STOREI 00003b70
-CSEG PFA_STOREI 00003b74
-ESEG EE_STOREI 0000005c
-CSEG VE_DO_STOREI_NRWW 00003b77
-CSEG XT_DO_STOREI 00003b7e
-CSEG PFA_DO_STOREI_NRWW 00003b7f
-CSEG DO_STOREI_atmega 00003b93
-CSEG pageload 00003ba4
-CSEG DO_STOREI_writepage 00003b9d
-CSEG dospm 00003bbd
-EQU pagemask ffffffc0
-CSEG pageload_loop 00003baa
-CSEG pageload_newdata 00003bb5
-CSEG pageload_cont 00003bb7
-CSEG pageload_done 00003bbc
-CSEG dospm_wait_ee 00003bbd
-CSEG dospm_wait_spm 00003bbf
-CSEG VE_FETCHI 00003bc8
-CSEG PFA_FETCHI 00003bcc
-CSEG VE_N_TO_R 00003bd2
-CSEG XT_N_TO_R 00003bd6
-CSEG PFA_N_TO_R 00003bd7
-CSEG PFA_N_TO_R1 00003bd9
-CSEG VE_N_R_FROM 00003be4
-CSEG XT_N_R_FROM 00003be8
-CSEG PFA_N_R_FROM 00003be9
-CSEG PFA_N_R_FROM1 00003bee
-CSEG VE_D2STAR 00003bf6
-CSEG XT_D2STAR 00003bfa
-CSEG PFA_D2STAR 00003bfb
-CSEG VE_D2SLASH 00003c04
-CSEG XT_D2SLASH 00003c08
-CSEG PFA_D2SLASH 00003c09
-CSEG VE_DPLUS 00003c12
-CSEG PFA_DPLUS 00003c16
-CSEG VE_DMINUS 00003c23
-CSEG XT_DMINUS 00003c26
-CSEG PFA_DMINUS 00003c27
-CSEG VE_DINVERT 00003c35
-CSEG PFA_DINVERT 00003c3c
-CSEG VE_SLASHMOD 00003c45
-CSEG XT_SLASHMOD 00003c49
-CSEG PFA_SLASHMOD 00003c4a
-CSEG PFA_SLASHMOD_1 00003c55
-CSEG PFA_SLASHMOD_2 00003c5b
-CSEG PFA_SLASHMOD_3 00003c5e
-CSEG PFA_SLASHMOD_5 00003c69
-CSEG PFA_SLASHMOD_4 00003c68
-CSEG PFA_SLASHMODmod_done 00003c74
-CSEG PFA_SLASHMOD_6 00003c72
-CSEG VE_ABS 00003c78
-CSEG XT_ABS 00003c7c
-CSEG PFA_ABS 00003c7d
-CSEG VE_PICK 00003c80
-CSEG PFA_PICK 00003c85
-CSEG VE_CELLPLUS 00003c8b
-CSEG PFA_CELLPLUS 00003c91
-CSEG VE_INTON 00003c93
-CSEG PFA_INTON 00003c98
-CSEG VE_INTOFF 00003c9a
-CSEG XT_INTOFF 00003c9e
-CSEG PFA_INTOFF 00003c9f
-CSEG VE_INTSTORE 00003ca1
-CSEG PFA_INTSTORE 00003ca6
-CSEG VE_INTFETCH 00003cab
-CSEG XT_INTFETCH 00003caf
-CSEG PFA_INTFETCH 00003cb0
-CSEG VE_INTTRAP 00003cb5
-CSEG XT_INTTRAP 00003cbb
-CSEG PFA_INTTRAP 00003cbc
-CSEG PFA_ISREXEC 00003cc1
-CSEG XT_ISREND 00003cc5
-CSEG PFA_ISREND 00003cc6
-CSEG PFA_ISREND1 00003cc8
-CSEG XT_DEFAULT_PROMPTOK 00003cc9
-CSEG PFA_DEFAULT_PROMPTOK 00003cca
-CSEG VE_PROMPTOK 00003cd0
-CSEG XT_PROMPTOK 00003cd4
-CSEG PFA_PROMPTOK 00003cd5
-CSEG XT_DEFAULT_PROMPTREADY 00003cd8
-CSEG PFA_DEFAULT_PROMPTREADY 00003cd9
-CSEG VE_PROMPTREADY 00003cdf
-CSEG XT_PROMPTREADY 00003ce4
-CSEG PFA_PROMPTREADY 00003ce5
-CSEG XT_DEFAULT_PROMPTERROR 00003ce8
-CSEG PFA_DEFAULT_PROMPTERROR 00003ce9
-CSEG VE_PROMPTERROR 00003cfa
-CSEG XT_PROMPTERROR 00003cff
-CSEG PFA_PROMPTERROR 00003d00
-CSEG VE_QUIT 00003d03
-CSEG XT_QUIT 00003d07
-CSEG PFA_QUIT 00003d08
-CSEG PFA_QUIT2 00003d10
-CSEG PFA_QUIT4 00003d16
-CSEG PFA_QUIT3 00003d28
-CSEG XT_CATCH 00003d70
-CSEG PFA_QUIT5 00003d26
-CSEG VE_PAUSE 00003d2b
-CSEG PFA_PAUSE 00003d31
-DSEG ram_pause 000000ed
-CSEG XT_RDEFERFETCH 00003db4
-CSEG XT_RDEFERSTORE 00003dbe
-CSEG VE_COLD 00003d34
-CSEG clearloop 00003d40
-DSEG ram_user1 000000ef
-CSEG PFA_WARM 00003d5a
-CSEG VE_WARM 00003d55
-CSEG XT_WARM 00003d59
-CSEG XT_DEFERSTORE 00003ddf
-CSEG XT_TURNKEY 00003f5c
-CSEG VE_HANDLER 00003d63
-CSEG XT_HANDLER 00003d69
-CSEG PFA_HANDLER 00003d6a
-CSEG VE_CATCH 00003d6b
-CSEG PFA_CATCH 00003d71
-CSEG VE_THROW 00003d81
-CSEG PFA_THROW 00003d87
-CSEG PFA_THROW1 00003d8d
-CSEG VE_EDEFERFETCH 00003d9a
-CSEG PFA_EDEFERFETCH 00003da1
-CSEG VE_EDEFERSTORE 00003da4
-CSEG PFA_EDEFERSTORE 00003dab
-CSEG VE_RDEFERFETCH 00003dae
-CSEG PFA_RDEFERFETCH 00003db5
-CSEG VE_RDEFERSTORE 00003db8
-CSEG PFA_RDEFERSTORE 00003dbf
-CSEG VE_UDEFERFETCH 00003dc2
-CSEG PFA_UDEFERFETCH 00003dc9
-CSEG VE_UDEFERSTORE 00003dce
-CSEG PFA_UDEFERSTORE 00003dd5
-CSEG VE_DEFERSTORE 00003dda
-CSEG PFA_DEFERSTORE 00003de0
-CSEG VE_DEFERFETCH 00003de7
-CSEG XT_DEFERFETCH 00003dec
-CSEG PFA_DEFERFETCH 00003ded
-CSEG VE_DODEFER 00003df3
-CSEG XT_DODEFER 00003df9
-CSEG PFA_DODEFER 00003dfa
-CSEG VE_UDOT 00003e07
-CSEG PFA_UDOT 00003e0b
-CSEG VE_UDOTR 00003e0e
-CSEG XT_UDOTR 00003e12
-CSEG PFA_UDOTR 00003e13
-CSEG VE_USLASHMOD 00003e17
-CSEG XT_USLASHMOD 00003e1c
-CSEG PFA_USLASHMOD 00003e1d
-CSEG VE_NEGATE 00003e22
-CSEG PFA_NEGATE 00003e28
-CSEG VE_SLASH 00003e2b
-CSEG XT_SLASH 00003e2e
-CSEG PFA_SLASH 00003e2f
-CSEG VE_MOD 00003e32
-CSEG XT_MOD 00003e36
-CSEG PFA_MOD 00003e37
-CSEG VE_MIN 00003e3a
-CSEG XT_MIN 00003e3e
-CSEG PFA_MIN 00003e3f
-CSEG PFA_MIN1 00003e44
-CSEG VE_MAX 00003e46
-CSEG XT_MAX 00003e4a
-CSEG PFA_MAX 00003e4b
-CSEG PFA_MAX1 00003e50
-CSEG VE_WITHIN 00003e52
-CSEG PFA_WITHIN 00003e58
-CSEG VE_SHOWWORDLIST 00003e5f
-CSEG XT_SHOWWORDLIST 00003e68
-CSEG PFA_SHOWWORDLIST 00003e69
-CSEG XT_SHOWWORD 00003e6e
-CSEG PFA_SHOWWORD 00003e6f
-CSEG VE_WORDS 00003e74
-CSEG XT_WORDS 00003e79
-CSEG PFA_WORDS 00003e7a
-CSEG VE_DOTSTRING 00003e7f
-CSEG XT_DOTSTRING 00003e82
-CSEG PFA_DOTSTRING 00003e83
-CSEG VE_SQUOTE 00003e87
-CSEG PFA_SQUOTE 00003e8b
-CSEG PFA_SQUOTE1 00003e93
-CSEG VE_FILL 00003e94
-CSEG PFA_FILL 00003e99
-CSEG PFA_FILL2 00003ea5
-CSEG PFA_FILL1 00003ea0
-CSEG VE_F_CPU 00003ea7
-CSEG PFA_F_CPU 00003ead
-CSEG VE_STATE 00003eb2
-CSEG PFA_STATE 00003eb8
-DSEG ram_state 0000011b
-CSEG VE_BASE 00003eb9
-CSEG PFA_BASE 00003ebe
-CSEG VE_CELLS 00003ebf
-CSEG VE_2DUP 00003ec5
-CSEG PFA_2DUP 00003eca
-CSEG VE_2DROP 00003ecd
-CSEG PFA_2DROP 00003ed3
-CSEG VE_TUCK 00003ed6
-CSEG PFA_TUCK 00003edb
-CSEG VE_TO_IN 00003ede
-CSEG PFA_TO_IN 00003ee3
-CSEG VE_PAD 00003ee4
-CSEG PFA_PAD 00003ee9
-CSEG VE_EMIT 00003eee
-CSEG PFA_EMIT 00003ef3
-CSEG VE_EMITQ 00003ef6
-CSEG XT_EMITQ 00003efb
-CSEG PFA_EMITQ 00003efc
-CSEG VE_KEY 00003eff
-CSEG PFA_KEY 00003f04
-CSEG VE_KEYQ 00003f07
-CSEG XT_KEYQ 00003f0b
-CSEG PFA_KEYQ 00003f0c
-CSEG VE_DP 00003f0f
-ESEG CFG_DP 0000002c
-CSEG VE_EHERE 00003f16
-ESEG EE_EHERE 00000030
-CSEG VE_HERE 00003f1f
-CSEG PFA_HERE 00003f24
-ESEG EE_HERE 0000002e
-CSEG VE_ALLOT 00003f27
-CSEG PFA_ALLOT 00003f2d
-CSEG VE_BIN 00003f32
-CSEG XT_BIN 00003f36
-CSEG PFA_BIN 00003f37
-CSEG VE_DECIMAL 00003f3b
-CSEG PFA_DECIMAL 00003f42
-CSEG VE_HEX 00003f47
-CSEG XT_HEX 00003f4b
-CSEG PFA_HEX 00003f4c
-CSEG VE_BL 00003f51
-CSEG PFA_BL 00003f55
-CSEG VE_TURNKEY 00003f56
-CSEG PFA_TURNKEY 00003f5d
-ESEG CFG_TURNKEY 00000038
-CSEG VE_TOUPPER 00003f60
-CSEG PFA_TOUPPER 00003f67
-CSEG PFA_TOUPPER0 00003f72
-CSEG VE_TOLOWER 00003f73
-CSEG XT_TOLOWER 00003f79
-CSEG PFA_TOLOWER 00003f7a
-CSEG PFA_TOLOWER0 00003f85
-CSEG VE_QSTACK 00003f86
-CSEG PFA_QSTACK 00003f8c
-CSEG PFA_QSTACK1 00003f93
-CSEG VE_BOUNDS 00003f94
-CSEG PFA_BOUNDS 00003f9a
-CSEG VE_CR 00003f9e
-CSEG PFA_CR 00003fa2
-CSEG VE_SPACE 00003fa9
-CSEG PFA_SPACE 00003faf
-CSEG VE_SPACES 00003fb2
-CSEG PFA_SPACES 00003fb8
-CSEG SPCS1 00003fba
-CSEG SPCS2 00003fc1
-CSEG VE_S2D 00003fc3
-CSEG PFA_S2D 00003fc8
-CSEG VE_TO_BODY 00003fcb
-CSEG VE_2LITERAL 00003fd1
-CSEG PFA_2LITERAL 00003fd8
-CSEG VE_EQUAL 00003fdc
-CSEG PFA_EQUAL 00003fe0
-CSEG VE_ONE 00003fe3
-CSEG PFA_ONE 00003fe7
-CSEG VE_TWO 00003fe8
-CSEG PFA_TWO 00003fec
-CSEG VE_MINUSONE 00003fed
-CSEG XT_MINUSONE 00003ff0
-CSEG PFA_MINUSONE 00003ff1
-SET flashlast 00003ff2
-DSEG HERESTART 0000011d
-ESEG EHERESTART 00000084
-ESEG CFG_ORDERLIST 00000042
-ESEG CFG_RECOGNIZERLIST 00000054
-EQU UBRR_VAL 0000000c
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/eval-pollin/p32-8.xml b/amforth-6.5/appl/eval-pollin/p32-8.xml
deleted file mode 100644
index 1fa114a..0000000
--- a/amforth-6.5/appl/eval-pollin/p32-8.xml
+++ /dev/null
@@ -1,35 +0,0 @@
-<project name="pollins-32-8" basedir="." default="Help">
- <target name="p32-8.asm">
- <copy tofile="p32-8.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="8000000"/>
- <filter token="USART" value=""/>
- </filterset>
- </copy>
- </target>
-
- <target name="p32-8.hex" depends="p32-8.asm" description="Hexfiles for p32-8">
- <avrasm2 projectname="p32-8" mcu="atmega32"/>
- <delete file="p32-8.asm"/>
- </target>
-
- <target name="p32-8" depends="p32-8.hex" description="Atmega32 @ 8 MHz">
- <echo>Uploading Hexfiles for p32-8</echo>
- <avrdude
- type="stk200"
- mcu="atmega32"
- flashfile="p32-8.hex"
- eepromfile="p32-8.eep.hex"
- />
- </target>
- <target name="p32-8.fuses" description="Set fuses for P32-8">
- <echo>Writing fuses</echo>
- <avrdude-2fuses
- type="${programmer}"
- mcu="${mcu}"
- hfuse="0x99"
- lfuse="0xff"
- />
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/p328-16.eep.hex b/amforth-6.5/appl/eval-pollin/p328-16.eep.hex
deleted file mode 100644
index ae05b64..0000000
--- a/amforth-6.5/appl/eval-pollin/p328-16.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
-:10003400FFFF260BC2018E00CE095C00B008780ACF
-:0A004400FF024800ED3F01004800F4
-:06005C00020070065C06C4
-:100066007E3B680000000000FF08AF08AF080000F4
-:100076000A00A300B1007800930077020000640232
-:08008600C93CE83CD83C19001C
-:00000001FF
diff --git a/amforth-6.5/appl/eval-pollin/p328-16.hex b/amforth-6.5/appl/eval-pollin/p328-16.hex
deleted file mode 100644
index b754f68..0000000
--- a/amforth-6.5/appl/eval-pollin/p328-16.hex
+++ /dev/null
@@ -1,633 +0,0 @@
-:020000020000FC
-:0200040026D103
-:0200080024D101
-:02000C0022D1FF
-:0200100020D1FD
-:020014001ED1FB
-:020018001CD1F9
-:02001C001AD1F7
-:0200200018D1F5
-:0200240016D1F3
-:0200280014D1F1
-:02002C0012D1EF
-:0200300010D1ED
-:020034000ED1EB
-:020038000CD1E9
-:02003C000AD1E7
-:0200400008D1E5
-:0200440006D1E3
-:0200480004D1E1
-:02004C0002D1DF
-:0200500000D1DD
-:02005400FED0DC
-:02005800FCD0DA
-:02005C00FAD0D8
-:02006000F8D0D6
-:10006400F6D00008000400701A000A0041546D65BF
-:1000740067613332385007FF3E72782D627566002F
-:1000840000004400082F10911001E0E0F1E0E10FBE
-:10009400F31D008313951F7010931001899199919A
-:1000A4000C94053806FF6973722D72783D0001388F
-:1000B4003D38C6009838B1383D380300DF3F363844
-:1000C4006400383D4300203801383D3859003D383C
-:1000D4002400A53C3D3800013D3816005439983EB3
-:1000E400203806FF72782D6275665400013893003B
-:1000F400363879003D3811019838B1383D3800015F
-:100104009D399838C4382F3A3D380F00133A3D389A
-:1001140011018D38203807FF72783F2D6275660013
-:1001240073000138303D3D38110198383D381001D5
-:1001340098381339203807FF74782D706F6C6C0071
-:100144008D000138B1003638A4003D38C6008D3822
-:10015400203808FF74783F2D706F6C6C9D00013857
-:10016400303D3D38C00098383D382000133A2038DF
-:1001740004FF75627272AB006F388C00A03DAA3D1B
-:1001840006FF2B7573617274BA0001383D3898000C
-:100194003D38C1008D383D3806003D38C2008D38E9
-:1001A400BE00B138F93A3D38C5008D383D38C40039
-:1001B4008D386600203808FF31772E7265736574B8
-:1001C400C200E4009A938A93249A2C98E0E8F7E01A
-:1001D4003197F1F71FB7F8942C9A2498E0E0F1E0F6
-:1001E4003197F1F783B184FF9FEF1FBF24982C98B8
-:1001F400E0E8F6E03197F1F7892F0C94053807FF12
-:1002040031772E736C6F7400DD0008012C98249AEA
-:100214001FB7F894E8E1F0E03197F1F788948795F7
-:1002240010F42C9A2498E4E2F0E03197F1F703B14A
-:1002340004FD8068ECECF0E03197F1F72C9A2498F7
-:0E024400E8E0F0E03197F1F71FBF0C940538A9
-:040000000C94393DE6
-:100252000A920FB60A920F900F900A94B02CFF9355
-:10026200EF93E2E1F1E00694E00DF31D00800394C8
-:100272000082EF91FF9109900FBE0990089502FF4D
-:100282006D2B01010138C73F153C203803FF75640F
-:100292002A0040010138B138FF38E039D938C43872
-:1002A200F638E039E1389D39203804FF756D617800
-:1002B20047010138C93E5C3936386001C438D93843
-:1002C200203804FF756D696E56010138C93E6739E1
-:1002D20036386C01C438D938203801383D380080AE
-:1002E200133A1A3936387701E63F20384B3920382D
-:1002F2000AFF6E616D653E666C616773620101386B
-:10030200CB3B3D3800FF133A203803FF766572007D
-:1003120079010138DA020304AE3FBD3E7938E802C2
-:10032200413FC73F210329033D382E0012033F03FB
-:100332004A033904BD3E8138AE3FF002030420383F
-:1003420004FF6E6F6F7086010138203806FF756EEC
-:1003520075736564A10101388D3A233F93392038C2
-:100362000200746FA70101384804D03FB73E7938C4
-:100372003638C5015C07BF01670720380138F638F7
-:10038200B138D101FF38CB3BB138D101D101CB3BE0
-:100392002A38203807FF692D63656C6C2B00B10188
-:1003A20001382F3A203808FF69636F6D70617265FA
-:1003B200CB010138FF38CF38F63813393638E5012A
-:1003C200D23ED9384B392038C43854392608363809
-:1003D20008029B3ACF387938CF38CB3BB1383D3819
-:1003E20000015C393638F901C4383D38FF00133A50
-:1003F200133936380002D23E4B39D43A20382F3ADC
-:10040200C438903CC4383D380200BA3AEB01D23EBF
-:100412005439203801FF2A00D4010138A639D938CD
-:10042200203801FF6A000B020138763A3D38070096
-:100432009D397938763A3D3809009D3979389D39A8
-:10044200203804FF6461627312020138B138213925
-:1004520036382C023302203807FF646E65676174F8
-:100462006500220201383B3CE63F5439153C2038F6
-:1004720005FF636D6F7665002D023F02BF93AF9358
-:10048200E991F991A991B991092F082B21F01D91B8
-:1004920011930197E1F7AF91BF91899199910C94D2
-:1004A200053805FF32737761700039020138E1388F
-:1004B200FF38E138F63820380AFF726566696C6CDD
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diff --git a/amforth-6.5/appl/eval-pollin/p328-16.lst b/amforth-6.5/appl/eval-pollin/p328-16.lst
deleted file mode 100644
index da486f0..0000000
--- a/amforth-6.5/appl/eval-pollin/p328-16.lst
+++ /dev/null
@@ -1,10427 +0,0 @@
-
-AVRASM ver. 2.1.52 p328-16.asm Sun Apr 30 20:10:15 2017
-
-p328-16.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega328p\device.asm'
-../../avr8/devices/atmega328p\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m328Pdef.inc'
-p328-16.asm(14): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-p328-16.asm(19): Including file '../../avr8\drivers/1wire.asm'
-p328-16.asm(21): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(11): Including file '../../avr8\dict/appl_4k.inc'
-../../avr8\dict/appl_4k.inc(1): Including file '../../common\words/ver.asm'
-../../avr8\dict/appl_4k.inc(4): Including file '../../common\words/noop.asm'
-../../avr8\dict/appl_4k.inc(5): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/appl_4k.inc(6): Including file '../../common\words/to.asm'
-../../avr8\dict/appl_4k.inc(7): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/appl_4k.inc(8): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/appl_4k.inc(9): Including file '../../common\words/star.asm'
-../../avr8\dict/appl_4k.inc(10): Including file '../../avr8\words/j.asm'
-../../avr8\dict/appl_4k.inc(11): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/appl_4k.inc(12): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/appl_4k.inc(13): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/appl_4k.inc(14): Including file '../../common\words/2swap.asm'
-../../avr8\dict/appl_4k.inc(15): Including file '../../common\words/tib.asm'
-../../avr8\dict/appl_4k.inc(16): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/appl_4k.inc(20): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/appl_4k.inc(21): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/appl_4k.inc(22): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/appl_4k.inc(23): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/appl_4k.inc(24): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/appl_4k.inc(25): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/appl_4k.inc(26): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/appl_4k.inc(27): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/appl_4k.inc(28): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/appl_4k.inc(30): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/appl_4k.inc(31): Including file '../../common\words/hold.asm'
-../../avr8\dict/appl_4k.inc(32): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/appl_4k.inc(33): Including file '../../common\words/sharp.asm'
-../../avr8\dict/appl_4k.inc(34): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/appl_4k.inc(35): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/appl_4k.inc(36): Including file '../../common\words/sign.asm'
-../../avr8\dict/appl_4k.inc(37): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/appl_4k.inc(38): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/appl_4k.inc(39): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/appl_4k.inc(40): Including file '../../common\words/dot.asm'
-../../avr8\dict/appl_4k.inc(41): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/appl_4k.inc(42): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/appl_4k.inc(43): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/appl_4k.inc(44): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/appl_4k.inc(46): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/appl_4k.inc(47): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/appl_4k.inc(48): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/appl_4k.inc(49): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/appl_4k.inc(50): Including file '../../common\words/type.asm'
-../../avr8\dict/appl_4k.inc(51): Including file '../../common\words/tick.asm'
-../../avr8\dict/appl_4k.inc(53): Including file '../../common\words/cskip.asm'
-../../avr8\dict/appl_4k.inc(54): Including file '../../common\words/cscan.asm'
-../../avr8\dict/appl_4k.inc(55): Including file '../../common\words/accept.asm'
-../../avr8\dict/appl_4k.inc(56): Including file '../../common\words/refill.asm'
-../../avr8\dict/appl_4k.inc(57): Including file '../../common\words/char.asm'
-../../avr8\dict/appl_4k.inc(58): Including file '../../common\words/number.asm'
-../../avr8\dict/appl_4k.inc(59): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/appl_4k.inc(60): Including file '../../common\words/set-base.asm'
-../../avr8\dict/appl_4k.inc(61): Including file '../../common\words/to-number.asm'
-../../avr8\dict/appl_4k.inc(62): Including file '../../common\words/parse.asm'
-../../avr8\dict/appl_4k.inc(63): Including file '../../common\words/source.asm'
-../../avr8\dict/appl_4k.inc(64): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/appl_4k.inc(65): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/appl_4k.inc(66): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/appl_4k.inc(67): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/appl_4k.inc(68): Including file '../../common\words/depth.asm'
-../../avr8\dict/appl_4k.inc(69): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/appl_4k.inc(70): Including file '../../common\words/recognize.asm'
-../../avr8\dict/appl_4k.inc(71): Including file '../../common\words/interpret.asm'
-../../avr8\dict/appl_4k.inc(72): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/appl_4k.inc(73): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/appl_4k.inc(74): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/appl_4k.inc(75): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/appl_4k.inc(76): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/appl_4k.inc(77): Including file '../../common\words/name2string.asm'
-../../avr8\dict/appl_4k.inc(78): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/appl_4k.inc(79): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/appl_4k.inc(81): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(3): Including file '../../common\words/dot-s.asm'
-dict_appl.inc(4): Including file '../../avr8\words/spirw.asm'
-dict_appl.inc(5): Including file '../../avr8\words/n-spi.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-dict_appl.inc(7): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(8): Including file '../../avr8\words/2r_fetch.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(104): Including file '../../avr8\dict/core_4k.inc'
-../../avr8\dict/core_4k.inc(3): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_4k.inc(4): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_4k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_4k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_4k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_4k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_4k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_4k.inc(10): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_4k.inc(11): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_4k.inc(12): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_4k.inc(13): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_4k.inc(14): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_4k.inc(17): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_4k.inc(18): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_4k.inc(19): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_4k.inc(21): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_4k.inc(22): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_4k.inc(23): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_4k.inc(24): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_4k.inc(26): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_4k.inc(27): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_4k.inc(28): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_4k.inc(31): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_4k.inc(32): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_4k.inc(33): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_4k.inc(34): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_4k.inc(35): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_4k.inc(36): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_4k.inc(37): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_4k.inc(38): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_4k.inc(39): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_4k.inc(41): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_4k.inc(42): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_4k.inc(45): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_4k.inc(46): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_4k.inc(47): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_4k.inc(48): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_4k.inc(50): Including file '../../common\words/min.asm'
-../../avr8\dict/core_4k.inc(51): Including file '../../common\words/max.asm'
-../../avr8\dict/core_4k.inc(52): Including file '../../common\words/within.asm'
-../../avr8\dict/core_4k.inc(54): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_4k.inc(55): Including file '../../common\words/words.asm'
-../../avr8\dict/core_4k.inc(57): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_4k.inc(58): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_4k.inc(59): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_4k.inc(61): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_4k.inc(62): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_4k.inc(63): Including file '../../common\words/base.asm'
-../../avr8\dict/core_4k.inc(65): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_4k.inc(67): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_4k.inc(68): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_4k.inc(69): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_4k.inc(71): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_4k.inc(72): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_4k.inc(73): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_4k.inc(74): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_4k.inc(75): Including file '../../common\words/key.asm'
-../../avr8\dict/core_4k.inc(76): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_4k.inc(78): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_4k.inc(79): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_4k.inc(80): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_4k.inc(81): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_4k.inc(83): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_4k.inc(84): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_4k.inc(85): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_4k.inc(86): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_4k.inc(88): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_4k.inc(89): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_4k.inc(90): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_4k.inc(92): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_4k.inc(93): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_4k.inc(94): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_4k.inc(95): Including file '../../common\words/space.asm'
-../../avr8\dict/core_4k.inc(96): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_4k.inc(97): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_4k.inc(98): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_USART0 = 0
- .set WANT_TWI = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_SPI = 0
- .set WANT_WATCHDOG = 0
- .set WANT_CPU = 0
- .set WANT_EEPROM = 0
- .equ intvecsize = 2 ; please verify; flash size: 32768 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d126 rcall isr ; External Interrupt Request 0
- .org 4
-000004 d124 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d122 rcall isr ; Pin Change Interrupt Request 0
- .org 8
-000008 d120 rcall isr ; Pin Change Interrupt Request 0
- .org 10
-00000a d11e rcall isr ; Pin Change Interrupt Request 1
- .org 12
-00000c d11c rcall isr ; Watchdog Time-out Interrupt
- .org 14
-00000e d11a rcall isr ; Timer/Counter2 Compare Match A
- .org 16
-000010 d118 rcall isr ; Timer/Counter2 Compare Match A
- .org 18
-000012 d116 rcall isr ; Timer/Counter2 Overflow
- .org 20
-000014 d114 rcall isr ; Timer/Counter1 Capture Event
- .org 22
-000016 d112 rcall isr ; Timer/Counter1 Compare Match A
- .org 24
-000018 d110 rcall isr ; Timer/Counter1 Compare Match B
- .org 26
-00001a d10e rcall isr ; Timer/Counter1 Overflow
- .org 28
-00001c d10c rcall isr ; TimerCounter0 Compare Match A
- .org 30
-00001e d10a rcall isr ; TimerCounter0 Compare Match B
- .org 32
-000020 d108 rcall isr ; Timer/Couner0 Overflow
- .org 34
-000022 d106 rcall isr ; SPI Serial Transfer Complete
- .org 36
-000024 d104 rcall isr ; USART Rx Complete
- .org 38
-000026 d102 rcall isr ; USART, Data Register Empty
- .org 40
-000028 d100 rcall isr ; USART Tx Complete
- .org 42
-00002a d0fe rcall isr ; ADC Conversion Complete
- .org 44
-00002c d0fc rcall isr ; EEPROM Ready
- .org 46
-00002e d0fa rcall isr ; Analog Comparator
- .org 48
-000030 d0f8 rcall isr ; Two-wire Serial Interface
- .org 50
-000032 d0f6 rcall isr ; Store Program Memory Read
- .equ INTVECTORS = 26
- .nooverlap
-
- ; compatability layer (maybe empty)
- .equ SPMEN = SELFPRGEN
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000033 0800 .dw 2048
- mcu_eepromsize:
-000034 0400 .dw 1024
- mcu_maxdp:
-000035 7000 .dw 28672
- mcu_numints:
-000036 001a .dw 26
- mcu_name:
-000037 000a .dw 10
-000038 5441
-000039 656d
-00003a 6167
-00003b 3233
-00003c 5038 .db "ATmega328P"
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set AMFORTH_RO_SEG = NRWW_START_ADDR+1
-
- ; cpu clock in hertz
- .equ F_CPU = 16000000
- .set BAUD_MAXERROR = 30
- .equ TIMER_INT = OVF2addr
-
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-00003d ff07 .dw $ff07
-00003e 723e
-00003f 2d78
-000040 7562
-000041 0066 .db ">rx-buf",0
-000042 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000043 0044 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000044 2f08 mov temp0, tosl
-000045 9110 0110 lds temp1, usart_rx_in
-000047 e0e0 ldi zl, low(usart_rx_data)
-000048 e0f1 ldi zh, high(usart_rx_data)
-000049 0fe1 add zl, temp1
-00004a 1df3 adc zh, zeroh
-00004b 8300 st Z, temp0
-00004c 9513 inc temp1
-00004d 701f andi temp1,usart_rx_mask
-00004e 9310 0110 sts usart_rx_in, temp1
-000050 9189
-000051 9199 loadtos
-000052 940c 3805 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000054 ff06 .dw $ff06
-000055 7369
-000056 2d72
-000057 7872 .db "isr-rx"
-000058 003d .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-000059 3801 .dw DO_COLON
- usart_rx_isr:
-00005a 383d .dw XT_DOLITERAL
-00005b 00c6 .dw usart_data
-00005c 3898 .dw XT_CFETCH
-00005d 38b1 .dw XT_DUP
-00005e 383d .dw XT_DOLITERAL
-00005f 0003 .dw 3
-000060 3fdf .dw XT_EQUAL
-000061 3836 .dw XT_DOCONDBRANCH
-000062 0064 .dw usart_rx_isr1
-000063 3d38 .dw XT_COLD
- usart_rx_isr1:
-000064 0043 .dw XT_TO_RXBUF
-000065 3820 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-000066 3801 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-000067 383d
-000068 0059 .dw XT_DOLITERAL, XT_ISR_RX
-000069 383d
-00006a 0024 .dw XT_DOLITERAL, URXCaddr
-00006b 3ca5 .dw XT_INTSTORE
-
-00006c 383d .dw XT_DOLITERAL
-00006d 0100 .dw usart_rx_data
-00006e 383d .dw XT_DOLITERAL
-00006f 0016 .dw usart_rx_size + 6
-000070 3954 .dw XT_ZERO
-000071 3e98 .dw XT_FILL
-000072 3820 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000073 ff06 .dw $ff06
-000074 7872
-000075 622d
-000076 6675 .db "rx-buf"
-000077 0054 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-000078 3801 .dw DO_COLON
- PFA_RX_BUFFER:
-000079 0093 .dw XT_RXQ_BUFFER
-00007a 3836 .dw XT_DOCONDBRANCH
-00007b 0079 .dw PFA_RX_BUFFER
-00007c 383d .dw XT_DOLITERAL
-00007d 0111 .dw usart_rx_out
-00007e 3898 .dw XT_CFETCH
-00007f 38b1 .dw XT_DUP
-000080 383d .dw XT_DOLITERAL
-000081 0100 .dw usart_rx_data
-000082 399d .dw XT_PLUS
-000083 3898 .dw XT_CFETCH
-000084 38c4 .dw XT_SWAP
-000085 3a2f .dw XT_1PLUS
-000086 383d .dw XT_DOLITERAL
-000087 000f .dw usart_rx_mask
-000088 3a13 .dw XT_AND
-000089 383d .dw XT_DOLITERAL
-00008a 0111 .dw usart_rx_out
-00008b 388d .dw XT_CSTORE
-00008c 3820 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-00008d ff07 .dw $ff07
-00008e 7872
-00008f 2d3f
-000090 7562
-000091 0066 .db "rx?-buf",0
-000092 0073 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-000093 3801 .dw DO_COLON
- PFA_RXQ_BUFFER:
-000094 3d30 .dw XT_PAUSE
-000095 383d .dw XT_DOLITERAL
-000096 0111 .dw usart_rx_out
-000097 3898 .dw XT_CFETCH
-000098 383d .dw XT_DOLITERAL
-000099 0110 .dw usart_rx_in
-00009a 3898 .dw XT_CFETCH
-00009b 3913 .dw XT_NOTEQUAL
-00009c 3820 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-00009d ff07 .dw $ff07
-00009e 7874
-00009f 702d
-0000a0 6c6f
-0000a1 006c .db "tx-poll",0
-0000a2 008d .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000a3 3801 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000a4 00b1 .dw XT_TXQ_POLL
-0000a5 3836 .dw XT_DOCONDBRANCH
-0000a6 00a4 .dw PFA_TX_POLL
- ; send to usart
-0000a7 383d .dw XT_DOLITERAL
-0000a8 00c6 .dw USART_DATA
-0000a9 388d .dw XT_CSTORE
-0000aa 3820 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000ab ff08 .dw $ff08
-0000ac 7874
-0000ad 2d3f
-0000ae 6f70
-0000af 6c6c .db "tx?-poll"
-0000b0 009d .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000b1 3801 .dw DO_COLON
- PFA_TXQ_POLL:
-0000b2 3d30 .dw XT_PAUSE
-0000b3 383d .dw XT_DOLITERAL
-0000b4 00c0 .dw USART_A
-0000b5 3898 .dw XT_CFETCH
-0000b6 383d .dw XT_DOLITERAL
-0000b7 0020 .dw bm_USART_TXRD
-0000b8 3a13 .dw XT_AND
-0000b9 3820 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000ba ff04 .dw $ff04
-0000bb 6275
-0000bc 7272 .db "ubrr"
-0000bd 00ab .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000be 386f .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000bf 008c .dw EE_UBRRVAL
-0000c0 3da0 .dw XT_EDEFERFETCH
-0000c1 3daa .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000c2 ff06 .dw $ff06
-0000c3 752b
-0000c4 6173
-0000c5 7472 .db "+usart"
-0000c6 00ba .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000c7 3801 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000c8 383d .dw XT_DOLITERAL
-0000c9 0098 .dw USART_B_VALUE
-0000ca 383d .dw XT_DOLITERAL
-0000cb 00c1 .dw USART_B
-0000cc 388d .dw XT_CSTORE
-
-0000cd 383d .dw XT_DOLITERAL
-0000ce 0006 .dw USART_C_VALUE
-0000cf 383d .dw XT_DOLITERAL
-0000d0 00c2 .dw USART_C | bm_USARTC_en
-0000d1 388d .dw XT_CSTORE
-
-0000d2 00be .dw XT_UBRR
-0000d3 38b1 .dw XT_DUP
-0000d4 3af9 .dw XT_BYTESWAP
-0000d5 383d .dw XT_DOLITERAL
-0000d6 00c5 .dw BAUDRATE_HIGH
-0000d7 388d .dw XT_CSTORE
-0000d8 383d .dw XT_DOLITERAL
-0000d9 00c4 .dw BAUDRATE_LOW
-0000da 388d .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000db 0066 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000dc 3820 .dw XT_EXIT
-
- ; settings for 1wire interface
- .equ OW_PORT=PORTB
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-0000dd ff08 .dw $ff08
-0000de 7731
-0000df 722e
-0000e0 7365
-0000e1 7465 .db "1w.reset"
-0000e2 00c2 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-0000e3 00e4 .dw PFA_OW_RESET
- PFA_OW_RESET:
-0000e4 939a
-0000e5 938a savetos
- ; setup to output
-0000e6 9a24 sbi OW_DDR, OW_BIT
- ; Pull output low
-0000e7 982c cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-0000e8 e8e0
-0000e9 e0f7
-0000ea 9731
-0000eb f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-0000ec b71f in temp1, SREG
-0000ed 94f8 cli
- ; Pull output high
-0000ee 9a2c sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-0000ef 9824 cbi OW_DDR, OW_BIT
-0000f0 e0e0
-0000f1 e0f1
-0000f2 9731
-0000f3 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-0000f4 b183 in tosl, OW_PIN
-0000f5 ff84 sbrs tosl, OW_BIT
-0000f6 ef9f ser tosh
- ; End critical timing period, enable interrupts
-0000f7 bf1f out SREG, temp1
- ; release bus
-0000f8 9824 cbi OW_DDR, OW_BIT
-0000f9 982c cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-0000fa e8e0
-0000fb e0f6
-0000fc 9731
-0000fd f7f1 DELAY 416
- ; we now have the result flag in TOS
-0000fe 2f89 mov tosl, tosh
-0000ff 940c 3805 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-000101 ff07 .dw $ff07
-000102 7731
-000103 732e
-000104 6f6c
-000105 0074 .db "1w.slot",0
-000106 00dd .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-000107 0108 .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-000108 982c cbi OW_PORT, OW_BIT
-000109 9a24 sbi OW_DDR, OW_BIT
- ; disable interrupts
-00010a b71f in temp1, SREG
-00010b 94f8 cli
-00010c e1e8
-00010d e0f0
-00010e 9731
-00010f f7f1 DELAY 6 ; DELAY A
- ; check bit
-000110 9488 clc
-000111 9587 ror tosl
-000112 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000113 9a2c sbi OW_PORT, OW_BIT
-000114 9824 cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-000115 e2e4
-000116 e0f0
-000117 9731
-000118 f7f1 DELAY 9 ; wait DELAY E to sample
-000119 b103 in temp0, OW_PIN
-00011a fd04 sbrc temp0, OW_BIT
-00011b 6880 ori tosl, $80
-
-00011c ecec
-00011d e0f0
-00011e 9731
-00011f f7f1 DELAY 51 ; DELAY B
-000120 9a2c sbi OW_PORT, OW_BIT ; release bus
-000121 9824 cbi OW_DDR, OW_BIT
-000122 e0e8
-000123 e0f0
-000124 9731
-000125 f7f1 delay 2
- ; re-enable interrupts
-000126 bf1f out SREG, temp1
-000127 940c 3805 jmp_ DO_NEXT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 3d39 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-000129 920a st -Y, r0
-00012a b60f in r0, SREG
-00012b 920a st -Y, r0
- .if (pclen==3)
- .endif
-00012c 900f pop r0
-00012d 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-00012e 940a dec r0
- .if intvecsize == 1 ;
- .endif
-00012f 2cb0 mov isrflag, r0
-000130 93ff push zh
-000131 93ef push zl
-000132 e1e2 ldi zl, low(intcnt)
-000133 e0f1 ldi zh, high(intcnt)
-000134 9406 lsr r0 ; we use byte addresses in the counter array, not words
-000135 0de0 add zl, r0
-000136 1df3 adc zh, zeroh
-000137 8000 ld r0, Z
-000138 9403 inc r0
-000139 8200 st Z, r0
-00013a 91ef pop zl
-00013b 91ff pop zh
-
-00013c 9009 ld r0, Y+
-00013d be0f out SREG, r0
-00013e 9009 ld r0, Y+
-00013f 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000140 ff02 .dw $ff02
-000141 2b6d .db "m+"
-000142 0101 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000143 3801 .dw DO_COLON
- PFA_MPLUS:
-000144 3fc7 .dw XT_S2D
-000145 3c15 .dw XT_DPLUS
-000146 3820 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-000147 ff03 .dw $ff03
-000148 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-000149 002a .db "ud*"
-00014a 0140 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-00014b 3801 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-00014c 38b1
-00014d 38ff
-00014e 39e0
-00014f 38d9 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000150 38c4
-000151 38f6
-000152 39e0
-000153 38e1
-000154 399d
-000155 3820 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-000156 ff04 .dw $ff04
-000157 6d75
-000158 7861 .db "umax"
-000159 0147 .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00015a 3801 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-00015b 3ec9
-00015c 395c .DW XT_2DUP,XT_ULESS
-00015d 3836 .dw XT_DOCONDBRANCH
-00015e 0160 DEST(UMAX1)
-00015f 38c4 .DW XT_SWAP
-000160 38d9 UMAX1: .DW XT_DROP
-000161 3820 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000162 ff04 .dw $ff04
-000163 6d75
-000164 6e69 .db "umin"
-000165 0156 .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-000166 3801 .dw DO_COLON
- PFA_UMIN:
- .endif
-000167 3ec9
-000168 3967 .DW XT_2DUP,XT_UGREATER
-000169 3836 .dw XT_DOCONDBRANCH
-00016a 016c DEST(UMIN1)
-00016b 38c4 .DW XT_SWAP
-00016c 38d9 UMIN1: .DW XT_DROP
-00016d 3820 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-00016e 3801 .dw DO_COLON
- PFA_IMMEDIATEQ:
-00016f 383d .dw XT_DOLITERAL
-000170 8000 .dw $8000
-000171 3a13 .dw XT_AND
-000172 391a .dw XT_ZEROEQUAL
-000173 3836 .dw XT_DOCONDBRANCH
-000174 0177 DEST(IMMEDIATEQ1)
-000175 3fe6 .dw XT_ONE
-000176 3820 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-000177 394b .dw XT_TRUE
-000178 3820 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-000179 ff0a .dw $ff0a
-00017a 616e
-00017b 656d
-00017c 663e
-00017d 616c
-00017e 7367 .db "name>flags"
-00017f 0162 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000180 3801 .dw DO_COLON
- PFA_NAME2FLAGS:
-000181 3bcb .dw XT_FETCHI ; skip to link field
-000182 383d .dw XT_DOLITERAL
-000183 ff00 .dw $ff00
-000184 3a13 .dw XT_AND
-000185 3820 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .elif AMFORTH_NRWW_SIZE > 4000
- .include "dict/appl_4k.inc"
-
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-000186 ff03 .dw $ff03
-000187 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-000188 0072 .db "ver"
-000189 0179 .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00018a 3801 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-00018b 02da .dw XT_ENV_FORTHNAME
-00018c 0403 .dw XT_ITYPE
-00018d 3fae .dw XT_SPACE
-00018e 3ebd .dw XT_BASE
-00018f 3879 .dw XT_FETCH
-
-000190 02e8 .dw XT_ENV_FORTHVERSION
-000191 3f41 .dw XT_DECIMAL
-000192 3fc7 .dw XT_S2D
-000193 0321 .dw XT_L_SHARP
-000194 0329 .dw XT_SHARP
-000195 383d .dw XT_DOLITERAL
-000196 002e .dw '.'
-000197 0312 .dw XT_HOLD
-000198 033f .dw XT_SHARP_S
-000199 034a .dw XT_SHARP_G
-00019a 0439 .dw XT_TYPE
-00019b 3ebd .dw XT_BASE
-00019c 3881 .dw XT_STORE
-00019d 3fae .dw XT_SPACE
-00019e 02f0 .dw XT_ENV_CPU
-00019f 0403 .dw XT_ITYPE
-
-0001a0 3820 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-0001a1 ff04 .dw $ff04
-0001a2 6f6e
-0001a3 706f .db "noop"
-0001a4 0186 .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-0001a5 3801 .dw DO_COLON
- PFA_NOOP:
- .endif
-0001a6 3820 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-0001a7 ff06 .dw $ff06
-0001a8 6e75
-0001a9 7375
-0001aa 6465 .db "unused"
-0001ab 01a1 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-0001ac 3801 .dw DO_COLON
- PFA_UNUSED:
-0001ad 3a8d .dw XT_SP_FETCH
-0001ae 3f23 .dw XT_HERE
-0001af 3993 .dw XT_MINUS
-0001b0 3820 .dw XT_EXIT
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-0001b1 0002 .dw $0002
-0001b2 6f74 .db "to"
-0001b3 01a7 .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-0001b4 3801 .dw DO_COLON
- PFA_TO:
- .endif
-0001b5 0448 .dw XT_TICK
-0001b6 3fd0 .dw XT_TO_BODY
-0001b7 3eb7 .dw XT_STATE
-0001b8 3879 .dw XT_FETCH
-0001b9 3836 .dw XT_DOCONDBRANCH
-0001ba 01c5 DEST(PFA_TO1)
-0001bb 075c .dw XT_COMPILE
-0001bc 01bf .dw XT_DOTO
-0001bd 0767 .dw XT_COMMA
-0001be 3820 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-0001bf 3801 .dw DO_COLON
- PFA_DOTO:
- .endif
-0001c0 38f6 .dw XT_R_FROM
-0001c1 38b1 .dw XT_DUP
-0001c2 01d1 .dw XT_ICELLPLUS
-0001c3 38ff .dw XT_TO_R
-0001c4 3bcb .dw XT_FETCHI
- PFA_TO1:
-0001c5 38b1 .dw XT_DUP
-0001c6 01d1 .dw XT_ICELLPLUS
-0001c7 01d1 .dw XT_ICELLPLUS
-0001c8 3bcb .dw XT_FETCHI
-0001c9 382a .dw XT_EXECUTE
-0001ca 3820 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-0001cb ff07 .dw $FF07
-0001cc 2d69
-0001cd 6563
-0001ce 6c6c
-0001cf 002b .db "i-cell+",0
-0001d0 01b1 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-0001d1 3801 .dw DO_COLON
- PFA_ICELLPLUS:
-0001d2 3a2f .dw XT_1PLUS
-0001d3 3820 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-0001d4 ff08 .dw $ff08
-0001d5 6369
-0001d6 6d6f
-0001d7 6170
-0001d8 6572 .db "icompare"
-0001d9 01cb .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-0001da 3801 .dw DO_COLON
- PFA_ICOMPARE:
-0001db 38ff .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-0001dc 38cf .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-0001dd 38f6 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-0001de 3913 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-0001df 3836 .dw XT_DOCONDBRANCH
-0001e0 01e5 .dw PFA_ICOMPARE_SAMELEN
-0001e1 3ed2 .dw XT_2DROP
-0001e2 38d9 .dw XT_DROP
-0001e3 394b .dw XT_TRUE
-0001e4 3820 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-0001e5 38c4 .dw XT_SWAP ; ( -- r-addr f-addr len )
-0001e6 3954 .dw XT_ZERO
-0001e7 0826 .dw XT_QDOCHECK
-0001e8 3836 .dw XT_DOCONDBRANCH
-0001e9 0208 .dw PFA_ICOMPARE_DONE
-0001ea 3a9b .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-0001eb 38cf .dw XT_OVER
-0001ec 3879 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-0001ed 38cf .dw XT_OVER
-0001ee 3bcb .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-0001ef 38b1 .dw XT_DUP
- ;.dw XT_BYTESWAP
-0001f0 383d .dw XT_DOLITERAL
-0001f1 0100 .dw $100
-0001f2 395c .dw XT_ULESS
-0001f3 3836 .dw XT_DOCONDBRANCH
-0001f4 01f9 .dw PFA_ICOMPARE_LASTCELL
-0001f5 38c4 .dw XT_SWAP
-0001f6 383d .dw XT_DOLITERAL
-0001f7 00ff .dw $00FF
-0001f8 3a13 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-0001f9 3913 .dw XT_NOTEQUAL
-0001fa 3836 .dw XT_DOCONDBRANCH
-0001fb 0200 .dw PFA_ICOMPARE_NEXTLOOP
-0001fc 3ed2 .dw XT_2DROP
-0001fd 394b .dw XT_TRUE
-0001fe 3ad4 .dw XT_UNLOOP
-0001ff 3820 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-000200 3a2f .dw XT_1PLUS
-000201 38c4 .dw XT_SWAP
-000202 3c90 .dw XT_CELLPLUS
-000203 38c4 .dw XT_SWAP
-000204 383d .dw XT_DOLITERAL
-000205 0002 .dw 2
-000206 3aba .dw XT_DOPLUSLOOP
-000207 01eb .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-000208 3ed2 .dw XT_2DROP
-000209 3954 .dw XT_ZERO
-00020a 3820 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-00020b ff01 .dw $ff01
-00020c 002a .db "*",0
-00020d 01d4 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-00020e 3801 .dw DO_COLON
- PFA_STAR:
- .endif
-
-00020f 39a6 .dw XT_MSTAR
-000210 38d9 .dw XT_DROP
-000211 3820 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-000212 ff01 .dw $FF01
-000213 006a .db "j",0
-000214 020b .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-000215 3801 .dw DO_COLON
- PFA_J:
-000216 3a76 .dw XT_RP_FETCH
-000217 383d .dw XT_DOLITERAL
-000218 0007 .dw 7
-000219 399d .dw XT_PLUS
-00021a 3879 .dw XT_FETCH
-00021b 3a76 .dw XT_RP_FETCH
-00021c 383d .dw XT_DOLITERAL
-00021d 0009 .dw 9
-00021e 399d .dw XT_PLUS
-00021f 3879 .dw XT_FETCH
-000220 399d .dw XT_PLUS
-000221 3820 .dw XT_EXIT
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-000222 ff04 .dw $ff04
-000223 6164
-000224 7362 .db "dabs"
-000225 0212 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-000226 3801 .dw DO_COLON
- PFA_DABS:
-000227 38b1 .dw XT_DUP
-000228 3921 .dw XT_ZEROLESS
-000229 3836 .dw XT_DOCONDBRANCH
-00022a 022c .dw PFA_DABS1
-00022b 0233 .dw XT_DNEGATE
- PFA_DABS1:
-00022c 3820 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-00022d ff07 .dw $ff07
-00022e 6e64
-00022f 6765
-000230 7461
-000231 0065 .db "dnegate",0
-000232 0222 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-000233 3801 .dw DO_COLON
- PFA_DNEGATE:
-000234 3c3b .dw XT_DINVERT
-000235 3fe6 .dw XT_ONE
-000236 3954 .dw XT_ZERO
-000237 3c15 .dw XT_DPLUS
-000238 3820 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-000239 ff05 .dw $ff05
-00023a 6d63
-00023b 766f
-00023c 0065 .db "cmove",0
-00023d 022d .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-00023e 023f .dw PFA_CMOVE
- PFA_CMOVE:
-00023f 93bf push xh
-000240 93af push xl
-000241 91e9 ld zl, Y+
-000242 91f9 ld zh, Y+ ; addr-to
-000243 91a9 ld xl, Y+
-000244 91b9 ld xh, Y+ ; addr-from
-000245 2f09 mov temp0, tosh
-000246 2b08 or temp0, tosl
-000247 f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-000248 911d ld temp1, X+
-000249 9311 st Z+, temp1
-00024a 9701 sbiw tosl, 1
-00024b f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-00024c 91af pop xl
-00024d 91bf pop xh
-00024e 9189
-00024f 9199 loadtos
-000250 940c 3805 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-000252 ff05 .dw $ff05
-000253 7332
-000254 6177
-000255 0070 .db "2swap",0
-000256 0239 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-000257 3801 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-000258 38e1 .dw XT_ROT
-000259 38ff .dw XT_TO_R
-00025a 38e1 .dw XT_ROT
-00025b 38f6 .dw XT_R_FROM
-00025c 3820 .dw XT_EXIT
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-00025d ff0a .dw $ff0a
-00025e 6572
-00025f 6966
-000260 6c6c
-000261 742d
-000262 6269 .db "refill-tib"
-000263 0252 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-000264 3801 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-000265 0280 .dw XT_TIB
-000266 383d .dw XT_DOLITERAL
-000267 005a .dw TIB_SIZE
-000268 0498 .dw XT_ACCEPT
-000269 0286 .dw XT_NUMBERTIB
-00026a 3881 .dw XT_STORE
-00026b 3954 .dw XT_ZERO
-00026c 3ee2 .dw XT_TO_IN
-00026d 3881 .dw XT_STORE
-00026e 394b .dw XT_TRUE ; -1
-00026f 3820 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-000270 ff0a .dw $FF0A
-000271 6f73
-000272 7275
-000273 6563
-000274 742d
-000275 6269 .db "source-tib"
-000276 025d .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-000277 3801 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-000278 0280 .dw XT_TIB
-000279 0286 .dw XT_NUMBERTIB
-00027a 3879 .dw XT_FETCH
-00027b 3820 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-00027c ff03 .dw $ff03
-00027d 6974
-00027e 0062 .db "tib",0
-00027f 0270 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-000280 3848 .dw PFA_DOVARIABLE
- PFA_TIB:
-000281 012c .dw ram_tib
- .dseg
-00012c ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-000282 ff04 .dw $ff04
-000283 7423
-000284 6269 .db "#tib"
-000285 027c .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-000286 3848 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-000287 0186 .dw ram_sharptib
- .dseg
-000186 ram_sharptib: .byte 2
- .cseg
- .endif
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-000288 ff06 .dw $ff06
-000289 6565
-00028a 723e
-00028b 6d61 .db "ee>ram"
-00028c 0282 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-00028d 3801 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-00028e 3954 .dw XT_ZERO
-00028f 3a9b .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-000290 38cf .dw XT_OVER
-000291 3b5f .dw XT_FETCHE
-000292 38cf .dw XT_OVER
-000293 3881 .dw XT_STORE
-000294 3c90 .dw XT_CELLPLUS
-000295 38c4 .dw XT_SWAP
-000296 3c90 .dw XT_CELLPLUS
-000297 38c4 .dw XT_SWAP
-000298 3ac9 .dw XT_DOLOOP
-000299 0290 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00029a 3ed2 .dw XT_2DROP
-00029b 3820 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-00029c ff08 .dw $ff08
-00029d 6e69
-00029e 7469
-00029f 722d
-0002a0 6d61 .db "init-ram"
-0002a1 0288 .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-0002a2 3801 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-0002a3 383d .dw XT_DOLITERAL
-0002a4 006a .dw EE_INITUSER
-0002a5 3b02 .dw XT_UP_FETCH
-0002a6 383d .dw XT_DOLITERAL
-0002a7 0022 .dw SYSUSERSIZE
-0002a8 3a04 .dw XT_2SLASH
-0002a9 028d .dw XT_EE2RAM
-0002aa 3820 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-0002ab ff0b .dw $ff0b
-0002ac 6e65
-0002ad 6976
-0002ae 6f72
-0002af 6d6e
-0002b0 6e65
-0002b1 0074 .db "environment",0
-0002b2 029c .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-0002b3 3848 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-0002b4 0044 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-0002b5 ff09 .dw $ff09
-0002b6 6f77
-0002b7 6472
-0002b8 696c
-0002b9 7473
-0002ba 0073 .db "wordlists",0
-0002bb 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-0002bc 3801 .dw DO_COLON
- PFA_ENVWORDLISTS:
-0002bd 383d .dw XT_DOLITERAL
-0002be 0008 .dw NUMWORDLISTS
-0002bf 3820 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-0002c0 ff04 .dw $ff04
-0002c1 702f
-0002c2 6461 .db "/pad"
-0002c3 02b5 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-0002c4 3801 .dw DO_COLON
- PFA_ENVSLASHPAD:
-0002c5 3a8d .dw XT_SP_FETCH
-0002c6 3ee8 .dw XT_PAD
-0002c7 3993 .dw XT_MINUS
-0002c8 3820 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-0002c9 ff05 .dw $ff05
-0002ca 682f
-0002cb 6c6f
-0002cc 0064 .db "/hold",0
-0002cd 02c0 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-0002ce 3801 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-0002cf 3ee8 .dw XT_PAD
-0002d0 3f23 .dw XT_HERE
-0002d1 3993 .dw XT_MINUS
-0002d2 3820 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-0002d3 ff0a .dw $ff0a
-0002d4 6f66
-0002d5 7472
-0002d6 2d68
-0002d7 616e
-0002d8 656d .db "forth-name"
-0002d9 02c9 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-0002da 3801 .dw DO_COLON
- PFA_EN_FORTHNAME:
-0002db 03d0 .dw XT_DOSLITERAL
-0002dc 0007 .dw 7
- .endif
-0002dd 6d61
-0002de 6f66
-0002df 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-0002e0 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-0002e1 3820 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-0002e2 ff07 .dw $ff07
-0002e3 6576
-0002e4 7372
-0002e5 6f69
-0002e6 006e .db "version",0
-0002e7 02d3 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-0002e8 3801 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-0002e9 383d .dw XT_DOLITERAL
-0002ea 0041 .dw 65
-0002eb 3820 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-0002ec ff03 .dw $ff03
-0002ed 7063
-0002ee 0075 .db "cpu",0
-0002ef 02e2 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-0002f0 3801 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-0002f1 383d .dw XT_DOLITERAL
-0002f2 0037 .dw mcu_name
-0002f3 042f .dw XT_ICOUNT
-0002f4 3820 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-0002f5 ff08 .dw $ff08
-0002f6 636d
-0002f7 2d75
-0002f8 6e69
-0002f9 6f66 .db "mcu-info"
-0002fa 02ec .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-0002fb 3801 .dw DO_COLON
- PFA_EN_MCUINFO:
-0002fc 383d .dw XT_DOLITERAL
-0002fd 0033 .dw mcu_info
-0002fe 3820 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-0002ff ff05 .dw $ff05
-000300 752f
-000301 6573
-000302 0072 .db "/user",0
-000303 02f5 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-000304 3801 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-000305 383d .dw XT_DOLITERAL
-000306 002c .dw SYSUSERSIZE + APPUSERSIZE
-000307 3820 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-000308 ff03 .dw $ff03
-000309 6c68
-00030a 0064 .db "hld",0
-00030b 02ab .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-00030c 3848 .dw PFA_DOVARIABLE
- PFA_HLD:
-00030d 0188 .dw ram_hld
-
- .dseg
-000188 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-00030e ff04 .dw $ff04
-00030f 6f68
-000310 646c .db "hold"
-000311 0308 .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-000312 3801 .dw DO_COLON
- PFA_HOLD:
- .endif
-000313 030c .dw XT_HLD
-000314 38b1 .dw XT_DUP
-000315 3879 .dw XT_FETCH
-000316 3a35 .dw XT_1MINUS
-000317 38b1 .dw XT_DUP
-000318 38ff .dw XT_TO_R
-000319 38c4 .dw XT_SWAP
-00031a 3881 .dw XT_STORE
-00031b 38f6 .dw XT_R_FROM
-00031c 388d .dw XT_CSTORE
-00031d 3820 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-00031e ff02 .dw $ff02
-00031f 233c .db "<#"
-000320 030e .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-000321 3801 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-000322 3ee8 .dw XT_PAD
-000323 030c .dw XT_HLD
-000324 3881 .dw XT_STORE
-000325 3820 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-000326 ff01 .dw $ff01
-000327 0023 .db "#",0
-000328 031e .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-000329 3801 .dw DO_COLON
- PFA_SHARP:
- .endif
-00032a 3ebd .dw XT_BASE
-00032b 3879 .dw XT_FETCH
-00032c 03a6 .dw XT_UDSLASHMOD
-00032d 38e1 .dw XT_ROT
-00032e 383d .dw XT_DOLITERAL
-00032f 0009 .dw 9
-000330 38cf .dw XT_OVER
-000331 396e .dw XT_LESS
-000332 3836 .dw XT_DOCONDBRANCH
-000333 0337 DEST(PFA_SHARP1)
-000334 383d .dw XT_DOLITERAL
-000335 0007 .dw 7
-000336 399d .dw XT_PLUS
- PFA_SHARP1:
-000337 383d .dw XT_DOLITERAL
-000338 0030 .dw 48 ; ASCII 0
-000339 399d .dw XT_PLUS
-00033a 0312 .dw XT_HOLD
-00033b 3820 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-00033c ff02 .dw $ff02
-00033d 7323 .db "#s"
-00033e 0326 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-00033f 3801 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-000340 0329 .dw XT_SHARP
-000341 3ec9 .dw XT_2DUP
-000342 3a1c .dw XT_OR
-000343 391a .dw XT_ZEROEQUAL
-000344 3836 .dw XT_DOCONDBRANCH
-000345 0340 DEST(NUMS1) ; PFA_SHARP_S
-000346 3820 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-000347 ff02 .dw $ff02
-000348 3e23 .db "#>"
-000349 033c .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00034a 3801 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-00034b 3ed2 .dw XT_2DROP
-00034c 030c .dw XT_HLD
-00034d 3879 .dw XT_FETCH
-00034e 3ee8 .dw XT_PAD
-00034f 38cf .dw XT_OVER
-000350 3993 .dw XT_MINUS
-000351 3820 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-000352 ff04 .dw $ff04
-000353 6973
-000354 6e67 .db "sign"
-000355 0347 .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-000356 3801 .dw DO_COLON
- PFA_SIGN:
- .endif
-000357 3921 .dw XT_ZEROLESS
-000358 3836 .dw XT_DOCONDBRANCH
-000359 035d DEST(PFA_SIGN1)
-00035a 383d .dw XT_DOLITERAL
-00035b 002d .dw 45 ; ascii -
-00035c 0312 .dw XT_HOLD
- PFA_SIGN1:
-00035d 3820 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-00035e ff03 .dw $ff03
-00035f 2e64
-000360 0072 .db "d.r",0
-000361 0352 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-000362 3801 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-000363 38ff .dw XT_TO_R
-000364 3eda .dw XT_TUCK
-000365 0226 .dw XT_DABS
-000366 0321 .dw XT_L_SHARP
-000367 033f .dw XT_SHARP_S
-000368 38e1 .dw XT_ROT
-000369 0356 .dw XT_SIGN
-00036a 034a .dw XT_SHARP_G
-00036b 38f6 .dw XT_R_FROM
-00036c 38cf .dw XT_OVER
-00036d 3993 .dw XT_MINUS
-00036e 3fb7 .dw XT_SPACES
-00036f 0439 .dw XT_TYPE
-000370 3820 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-000371 ff02 .dw $ff02
-000372 722e .db ".r"
-000373 035e .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-000374 3801 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-000375 38ff .dw XT_TO_R
-000376 3fc7 .dw XT_S2D
-000377 38f6 .dw XT_R_FROM
-000378 0362 .dw XT_DDOTR
-000379 3820 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00037a ff02 .dw $ff02
-00037b 2e64 .db "d."
-00037c 0371 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-00037d 3801 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-00037e 3954 .dw XT_ZERO
-00037f 0362 .dw XT_DDOTR
-000380 3fae .dw XT_SPACE
-000381 3820 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-000382 ff01 .dw $ff01
-000383 002e .db ".",0
-000384 037a .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-000385 3801 .dw DO_COLON
- PFA_DOT:
- .endif
-000386 3fc7 .dw XT_S2D
-000387 037d .dw XT_DDOT
-000388 3820 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-000389 ff03 .dw $ff03
-00038a 6475
-00038b 002e .db "ud.",0
-00038c 0382 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-00038d 3801 .dw DO_COLON
- PFA_UDDOT:
- .endif
-00038e 3954 .dw XT_ZERO
-00038f 0396 .dw XT_UDDOTR
-000390 3fae .dw XT_SPACE
-000391 3820 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-000392 ff04 .dw $ff04
-000393 6475
-000394 722e .db "ud.r"
-000395 0389 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-000396 3801 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-000397 38ff .dw XT_TO_R
-000398 0321 .dw XT_L_SHARP
-000399 033f .dw XT_SHARP_S
-00039a 034a .dw XT_SHARP_G
-00039b 38f6 .dw XT_R_FROM
-00039c 38cf .dw XT_OVER
-00039d 3993 .dw XT_MINUS
-00039e 3fb7 .dw XT_SPACES
-00039f 0439 .dw XT_TYPE
-0003a0 3820 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-0003a1 ff06 .dw $ff06
-0003a2 6475
-0003a3 6d2f
-0003a4 646f .db "ud/mod"
-0003a5 0392 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-0003a6 3801 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-0003a7 38ff .dw XT_TO_R
-0003a8 3954 .dw XT_ZERO
-0003a9 3908 .dw XT_R_FETCH
-0003aa 39c2 .dw XT_UMSLASHMOD
-0003ab 38f6 .dw XT_R_FROM
-0003ac 38c4 .dw XT_SWAP
-0003ad 38ff .dw XT_TO_R
-0003ae 39c2 .dw XT_UMSLASHMOD
-0003af 38f6 .dw XT_R_FROM
-0003b0 3820 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-0003b1 ff06 .dw $ff06
-0003b2 6964
-0003b3 6967
-0003b4 3f74 .db "digit?"
-0003b5 03a1 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-0003b6 3801 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-0003b7 3f66 .dw XT_TOUPPER
-0003b8 38b1
-0003b9 383d
-0003ba 0039
-0003bb 3978
-0003bc 383d
-0003bd 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-0003be 3a13
-0003bf 399d
-0003c0 38b1
-0003c1 383d
-0003c2 0140
-0003c3 3978 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-0003c4 383d
-0003c5 0107
-0003c6 3a13
-0003c7 3993
-0003c8 383d
-0003c9 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-0003ca 3993
-0003cb 38b1
-0003cc 3ebd
-0003cd 3879
-0003ce 395c .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-0003cf 3820 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-0003d0 3801 .dw DO_COLON
- PFA_DOSLITERAL:
-0003d1 3908 .dw XT_R_FETCH ; ( -- addr )
-0003d2 042f .dw XT_ICOUNT
-0003d3 38f6 .dw XT_R_FROM
-0003d4 38cf .dw XT_OVER ; ( -- addr' n addr n)
-0003d5 3a2f .dw XT_1PLUS
-0003d6 3a04 .dw XT_2SLASH ; ( -- addr' n addr k )
-0003d7 399d .dw XT_PLUS ; ( -- addr' n addr'' )
-0003d8 3a2f .dw XT_1PLUS
-0003d9 38ff .dw XT_TO_R ; ( -- )
-0003da 3820 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-0003db ff02 .dw $ff02
-0003dc 2c73 .db "s",$2c
-0003dd 03b1 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-0003de 3801 .dw DO_COLON
- PFA_SCOMMA:
-0003df 38b1 .dw XT_DUP
-0003e0 03e2 .dw XT_DOSCOMMA
-0003e1 3820 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-0003e2 3801 .dw DO_COLON
- PFA_DOSCOMMA:
-0003e3 0767 .dw XT_COMMA
-0003e4 38b1 .dw XT_DUP ; ( --addr len len)
-0003e5 3a04 .dw XT_2SLASH ; ( -- addr len len/2
-0003e6 3eda .dw XT_TUCK ; ( -- addr len/2 len len/2
-0003e7 3a0b .dw XT_2STAR ; ( -- addr len/2 len len'
-0003e8 3993 .dw XT_MINUS ; ( -- addr len/2 rem
-0003e9 38ff .dw XT_TO_R
-0003ea 3954 .dw XT_ZERO
-0003eb 0826 .dw XT_QDOCHECK
-0003ec 3836 .dw XT_DOCONDBRANCH
-0003ed 03f5 .dw PFA_SCOMMA2
-0003ee 3a9b .dw XT_DODO
- PFA_SCOMMA1:
-0003ef 38b1 .dw XT_DUP ; ( -- addr addr )
-0003f0 3879 .dw XT_FETCH ; ( -- addr c1c2 )
-0003f1 0767 .dw XT_COMMA ; ( -- addr )
-0003f2 3c90 .dw XT_CELLPLUS ; ( -- addr+cell )
-0003f3 3ac9 .dw XT_DOLOOP
-0003f4 03ef .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-0003f5 38f6 .dw XT_R_FROM
-0003f6 3928 .dw XT_GREATERZERO
-0003f7 3836 .dw XT_DOCONDBRANCH
-0003f8 03fc .dw PFA_SCOMMA3
-0003f9 38b1 .dw XT_DUP ; well, tricky
-0003fa 3898 .dw XT_CFETCH
-0003fb 0767 .dw XT_COMMA
- PFA_SCOMMA3:
-0003fc 38d9 .dw XT_DROP ; ( -- )
-0003fd 3820 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-0003fe ff05 .dw $ff05
-0003ff 7469
-000400 7079
-000401 0065 .db "itype",0
-000402 03db .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-000403 3801 .dw DO_COLON
- PFA_ITYPE:
-000404 38b1 .dw XT_DUP ; ( --addr len len)
-000405 3a04 .dw XT_2SLASH ; ( -- addr len len/2
-000406 3eda .dw XT_TUCK ; ( -- addr len/2 len len/2
-000407 3a0b .dw XT_2STAR ; ( -- addr len/2 len len'
-000408 3993 .dw XT_MINUS ; ( -- addr len/2 rem
-000409 38ff .dw XT_TO_R
-00040a 3954 .dw XT_ZERO
-00040b 0826 .dw XT_QDOCHECK
-00040c 3836 .dw XT_DOCONDBRANCH
-00040d 0417 .dw PFA_ITYPE2
-00040e 3a9b .dw XT_DODO
- PFA_ITYPE1:
-00040f 38b1 .dw XT_DUP ; ( -- addr addr )
-000410 3bcb .dw XT_FETCHI ; ( -- addr c1c2 )
-000411 38b1 .dw XT_DUP
-000412 0424 .dw XT_LOWEMIT
-000413 0420 .dw XT_HIEMIT
-000414 3a2f .dw XT_1PLUS ; ( -- addr+cell )
-000415 3ac9 .dw XT_DOLOOP
-000416 040f .dw PFA_ITYPE1
- PFA_ITYPE2:
-000417 38f6 .dw XT_R_FROM
-000418 3928 .dw XT_GREATERZERO
-000419 3836 .dw XT_DOCONDBRANCH
-00041a 041e .dw PFA_ITYPE3
-00041b 38b1 .dw XT_DUP ; make sure the drop below has always something to do
-00041c 3bcb .dw XT_FETCHI
-00041d 0424 .dw XT_LOWEMIT
- PFA_ITYPE3:
-00041e 38d9 .dw XT_DROP
-00041f 3820 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-000420 3801 .dw DO_COLON
- PFA_HIEMIT:
-000421 3af9 .dw XT_BYTESWAP
-000422 0424 .dw XT_LOWEMIT
-000423 3820 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-000424 3801 .dw DO_COLON
- PFA_LOWEMIT:
-000425 383d .dw XT_DOLITERAL
-000426 00ff .dw $00ff
-000427 3a13 .dw XT_AND
-000428 3ef2 .dw XT_EMIT
-000429 3820 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00042a ff06 .dw $ff06
-00042b 6369
-00042c 756f
-00042d 746e .db "icount"
-00042e 03fe .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-00042f 3801 .dw DO_COLON
- PFA_ICOUNT:
-000430 38b1 .dw XT_DUP
-000431 3a2f .dw XT_1PLUS
-000432 38c4 .dw XT_SWAP
-000433 3bcb .dw XT_FETCHI
-000434 3820 .dw XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-000435 ff04 .dw $ff04
-000436 7974
-000437 6570 .db "type"
-000438 042a .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-000439 3801 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-00043a 3f99 .dw XT_BOUNDS
-00043b 0826 .dw XT_QDOCHECK
-00043c 3836 .dw XT_DOCONDBRANCH
-00043d 0444 DEST(PFA_TYPE2)
-00043e 3a9b .dw XT_DODO
- PFA_TYPE1:
-00043f 3aac .dw XT_I
-000440 3898 .dw XT_CFETCH
-000441 3ef2 .dw XT_EMIT
-000442 3ac9 .dw XT_DOLOOP
-000443 043f DEST(PFA_TYPE1)
- PFA_TYPE2:
-000444 3820 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-000445 ff01 .dw $ff01
-000446 0027 .db "'",0
-000447 0435 .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-000448 3801 .dw DO_COLON
- PFA_TICK:
- .endif
-000449 05bb .dw XT_PARSENAME
-00044a 05fe .dw XT_FORTHRECOGNIZER
-00044b 0609 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-00044c 38b1 .dw XT_DUP
-00044d 0696 .dw XT_DT_NULL
-00044e 3fdf .dw XT_EQUAL
-00044f 38c4 .dw XT_SWAP
-000450 3bcb .dw XT_FETCHI
-000451 383d .dw XT_DOLITERAL
-000452 01a5 .dw XT_NOOP
-000453 3fdf .dw XT_EQUAL
-000454 3a1c .dw XT_OR
-000455 3836 .dw XT_DOCONDBRANCH
-000456 045a DEST(PFA_TICK1)
-000457 383d .dw XT_DOLITERAL
-000458 fff3 .dw -13
-000459 3d86 .dw XT_THROW
- PFA_TICK1:
-00045a 38d9 .dw XT_DROP
-00045b 3820 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-00045c ff05 .dw $ff05
-00045d 7363
-00045e 696b
-00045f 0070 .db "cskip",0
-000460 0445 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-000461 3801 .dw DO_COLON
- PFA_CSKIP:
- .endif
-000462 38ff .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-000463 38b1 .dw XT_DUP ; ( -- addr' n' n' )
-000464 3836 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-000465 0470 DEST(PFA_CSKIP2)
-000466 38cf .dw XT_OVER ; ( -- addr' n' addr' )
-000467 3898 .dw XT_CFETCH ; ( -- addr' n' c' )
-000468 3908 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-000469 3fdf .dw XT_EQUAL ; ( -- addr' n' f )
-00046a 3836 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00046b 0470 DEST(PFA_CSKIP2)
-00046c 3fe6 .dw XT_ONE
-00046d 05ac .dw XT_SLASHSTRING
-00046e 382f .dw XT_DOBRANCH
-00046f 0463 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-000470 38f6 .dw XT_R_FROM
-000471 38d9 .dw XT_DROP ; ( -- addr2 n2)
-000472 3820 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-000473 ff05 .dw $ff05
-000474 7363
-000475 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-000476 006e .db "cscan"
-000477 045c .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-000478 3801 .dw DO_COLON
- PFA_CSCAN:
- .endif
-000479 38ff .dw XT_TO_R
-00047a 38cf .dw XT_OVER
- PFA_CSCAN1:
-00047b 38b1 .dw XT_DUP
-00047c 3898 .dw XT_CFETCH
-00047d 3908 .dw XT_R_FETCH
-00047e 3fdf .dw XT_EQUAL
-00047f 391a .dw XT_ZEROEQUAL
-000480 3836 .dw XT_DOCONDBRANCH
-000481 048d DEST(PFA_CSCAN2)
-000482 38c4 .dw XT_SWAP
-000483 3a35 .dw XT_1MINUS
-000484 38c4 .dw XT_SWAP
-000485 38cf .dw XT_OVER
-000486 3921 .dw XT_ZEROLESS ; not negative
-000487 391a .dw XT_ZEROEQUAL
-000488 3836 .dw XT_DOCONDBRANCH
-000489 048d DEST(PFA_CSCAN2)
-00048a 3a2f .dw XT_1PLUS
-00048b 382f .dw XT_DOBRANCH
-00048c 047b DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-00048d 38f0 .dw XT_NIP
-00048e 38cf .dw XT_OVER
-00048f 3993 .dw XT_MINUS
-000490 38f6 .dw XT_R_FROM
-000491 38d9 .dw XT_DROP
-000492 3820 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-000493 ff06 .dw $ff06
-000494 6361
-000495 6563
-000496 7470 .db "accept"
-000497 0473 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-000498 3801 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-000499 38cf
-00049a 399d
-00049b 3a35
-00049c 38cf .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-00049d 3f03
-00049e 38b1
-00049f 04d9
-0004a0 391a
-0004a1 3836 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-0004a2 04cb DEST(ACC5)
-0004a3 38b1
-0004a4 383d
-0004a5 0008
-0004a6 3fdf
-0004a7 3836 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-0004a8 04bb DEST(ACC3)
-0004a9 38d9
-0004aa 38e1
-0004ab 3ec9
-0004ac 3978
-0004ad 38ff
-0004ae 38e1
-0004af 38e1
-0004b0 38f6
-0004b1 3836 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-0004b2 04b9 DEST(ACC6)
-0004b3 04d1
-0004b4 3a35
-0004b5 38ff
-0004b6 38cf
-0004b7 38f6
-0004b8 015a .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-0004b9 382f ACC6: .DW XT_DOBRANCH
-0004ba 04c9 DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-0004bb 38b1 .dw XT_DUP ; ( -- addr k k )
-0004bc 3f54 .dw XT_BL
-0004bd 396e .dw XT_LESS
-0004be 3836 .dw XT_DOCONDBRANCH
-0004bf 04c2 DEST(PFA_ACCEPT6)
-0004c0 38d9 .dw XT_DROP
-0004c1 3f54 .dw XT_BL
- PFA_ACCEPT6:
-0004c2 38b1
-0004c3 3ef2
-0004c4 38cf
-0004c5 388d
-0004c6 3a2f
-0004c7 38cf
-0004c8 0166 .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-0004c9 382f ACC4: .DW XT_DOBRANCH
-0004ca 049d DEST(ACC1)
-0004cb 38d9
-0004cc 38f0
-0004cd 38c4
-0004ce 3993
-0004cf 3fa1
-0004d0 3820 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-0004d1 3801 .dw DO_COLON
- .endif
-0004d2 383d .dw XT_DOLITERAL
-0004d3 0008 .dw 8
-0004d4 38b1 .dw XT_DUP
-0004d5 3ef2 .dw XT_EMIT
-0004d6 3fae .dw XT_SPACE
-0004d7 3ef2 .dw XT_EMIT
-0004d8 3820 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-0004d9 3801 .dw DO_COLON
- .endif
-0004da 38b1 .dw XT_DUP
-0004db 383d .dw XT_DOLITERAL
-0004dc 000d .dw 13
-0004dd 3fdf .dw XT_EQUAL
-0004de 38c4 .dw XT_SWAP
-0004df 383d .dw XT_DOLITERAL
-0004e0 000a .dw 10
-0004e1 3fdf .dw XT_EQUAL
-0004e2 3a1c .dw XT_OR
-0004e3 3820 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-0004e4 ff06 .dw $ff06
-0004e5 6572
-0004e6 6966
-0004e7 6c6c .db "refill"
-0004e8 0493 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-0004e9 3dff .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-0004ea 001a .dw USER_REFILL
-0004eb 3dc8 .dw XT_UDEFERFETCH
-0004ec 3dd4 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-0004ed ff04 .dw $ff04
-0004ee 6863
-0004ef 7261 .db "char"
-0004f0 04e4 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-0004f1 3801 .dw DO_COLON
- PFA_CHAR:
- .endif
-0004f2 05bb .dw XT_PARSENAME
-0004f3 38d9 .dw XT_DROP
-0004f4 3898 .dw XT_CFETCH
-0004f5 3820 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-0004f6 ff06 .dw $ff06
-0004f7 756e
-0004f8 626d
-0004f9 7265 .db "number"
-0004fa 04ed .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-0004fb 3801 .dw DO_COLON
- PFA_NUMBER:
- .endif
-0004fc 3ebd .dw XT_BASE
-0004fd 3879 .dw XT_FETCH
-0004fe 38ff .dw XT_TO_R
-0004ff 053f .dw XT_QSIGN
-000500 38ff .dw XT_TO_R
-000501 0552 .dw XT_SET_BASE
-000502 053f .dw XT_QSIGN
-000503 38f6 .dw XT_R_FROM
-000504 3a1c .dw XT_OR
-000505 38ff .dw XT_TO_R
- ; check whether something is left
-000506 38b1 .dw XT_DUP
-000507 391a .dw XT_ZEROEQUAL
-000508 3836 .dw XT_DOCONDBRANCH
-000509 0512 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-00050a 3ed2 .dw XT_2DROP
-00050b 38f6 .dw XT_R_FROM
-00050c 38d9 .dw XT_DROP
-00050d 38f6 .dw XT_R_FROM
-00050e 3ebd .dw XT_BASE
-00050f 3881 .dw XT_STORE
-000510 3954 .dw XT_ZERO
-000511 3820 .dw XT_EXIT
- PFA_NUMBER0:
-000512 3b1e .dw XT_2TO_R
-000513 3954 .dw XT_ZERO ; starting value
-000514 3954 .dw XT_ZERO
-000515 3b2d .dw XT_2R_FROM
-000516 0570 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-000517 38b9 .dw XT_QDUP
-000518 3836 .dw XT_DOCONDBRANCH
-000519 0534 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00051a 3fe6 .dw XT_ONE
-00051b 3fdf .dw XT_EQUAL
-00051c 3836 .dw XT_DOCONDBRANCH
-00051d 052b DEST(PFA_NUMBER2)
- ; excatly one character is left
-00051e 3898 .dw XT_CFETCH
-00051f 383d .dw XT_DOLITERAL
-000520 002e .dw 46 ; .
-000521 3fdf .dw XT_EQUAL
-000522 3836 .dw XT_DOCONDBRANCH
-000523 052c DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-000524 38f6 .dw XT_R_FROM
-000525 3836 .dw XT_DOCONDBRANCH
-000526 0528 DEST(PFA_NUMBER3)
-000527 0233 .dw XT_DNEGATE
- PFA_NUMBER3:
-000528 3feb .dw XT_TWO
-000529 382f .dw XT_DOBRANCH
-00052a 053a DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-00052b 38d9 .dw XT_DROP
- PFA_NUMBER6:
-00052c 3ed2 .dw XT_2DROP
-00052d 38f6 .dw XT_R_FROM
-00052e 38d9 .dw XT_DROP
-00052f 38f6 .dw XT_R_FROM
-000530 3ebd .dw XT_BASE
-000531 3881 .dw XT_STORE
-000532 3954 .dw XT_ZERO
-000533 3820 .dw XT_EXIT
- PFA_NUMBER1:
-000534 3ed2 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-000535 38f6 .dw XT_R_FROM
-000536 3836 .dw XT_DOCONDBRANCH
-000537 0539 DEST(PFA_NUMBER4)
-000538 3e27 .dw XT_NEGATE
- PFA_NUMBER4:
-000539 3fe6 .dw XT_ONE
- PFA_NUMBER5:
-00053a 38f6 .dw XT_R_FROM
-00053b 3ebd .dw XT_BASE
-00053c 3881 .dw XT_STORE
-00053d 394b .dw XT_TRUE
-00053e 3820 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-00053f 3801 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-000540 38cf .dw XT_OVER ; ( -- addr len addr )
-000541 3898 .dw XT_CFETCH
-000542 383d .dw XT_DOLITERAL
-000543 002d .dw '-'
-000544 3fdf .dw XT_EQUAL ; ( -- addr len flag )
-000545 38b1 .dw XT_DUP
-000546 38ff .dw XT_TO_R
-000547 3836 .dw XT_DOCONDBRANCH
-000548 054b DEST(PFA_NUMBERSIGN_DONE)
-000549 3fe6 .dw XT_ONE ; skip sign character
-00054a 05ac .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-00054b 38f6 .dw XT_R_FROM
-00054c 3820 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-00054d 3852 .dw PFA_DOCONSTANT
- .endif
-00054e 000a
-00054f 0010
-000550 0002
-000551 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-000552 3801 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-000553 38cf .dw XT_OVER
-000554 3898 .dw XT_CFETCH
-000555 383d .dw XT_DOLITERAL
-000556 0023 .dw 35
-000557 3993 .dw XT_MINUS
-000558 38b1 .dw XT_DUP
-000559 3954 .dw XT_ZERO
-00055a 383d .dw XT_DOLITERAL
-00055b 0004 .dw 4
-00055c 3e57 .dw XT_WITHIN
-00055d 3836 .dw XT_DOCONDBRANCH
-00055e 0568 DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-00055f 054d .dw XT_BASES
-000560 399d .dw XT_PLUS
-000561 3bcb .dw XT_FETCHI
-000562 3ebd .dw XT_BASE
-000563 3881 .dw XT_STORE
-000564 3fe6 .dw XT_ONE
-000565 05ac .dw XT_SLASHSTRING
-000566 382f .dw XT_DOBRANCH
-000567 0569 DEST(SET_BASE2)
- SET_BASE1:
-000568 38d9 .dw XT_DROP
- SET_BASE2:
-000569 3820 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00056a ff07 .dw $ff07
-00056b 6e3e
-00056c 6d75
-00056d 6562
-00056e 0072 .db ">number",0
-00056f 04f6 .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-000570 3801 .dw DO_COLON
-
- .endif
-
-000571 38b1
-000572 3836 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-000573 0588 DEST(TONUM3)
-000574 38cf
-000575 3898
-000576 03b6 .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-000577 391a
-000578 3836 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-000579 057c DEST(TONUM2)
-00057a 38d9
-00057b 3820 .DW XT_DROP,XT_EXIT
-00057c 38ff
-00057d 0257
-00057e 3ebd
-00057f 3879
-000580 014b TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-000581 38f6
-000582 0143
-000583 0257 .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-000584 3fe6
-000585 05ac
-000586 382f .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-000587 0571 DEST(TONUM1)
-000588 3820 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-000589 ff05 .dw $ff05
-00058a 6170
-00058b 7372
-00058c 0065 .db "parse",0
-00058d 056a .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-00058e 3801 .dw DO_COLON
- PFA_PARSE:
- .endif
-00058f 38ff .dw XT_TO_R ; ( -- )
-000590 05a2 .dw XT_SOURCE ; ( -- addr len)
-000591 3ee2 .dw XT_TO_IN ; ( -- addr len >in)
-000592 3879 .dw XT_FETCH
-000593 05ac .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-000594 38f6 .dw XT_R_FROM ; ( -- addr' len' c)
-000595 0478 .dw XT_CSCAN ; ( -- addr' len'')
-000596 38b1 .dw XT_DUP ; ( -- addr' len'' len'')
-000597 3a2f .dw XT_1PLUS
-000598 3ee2 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-000599 3a65 .dw XT_PLUSSTORE ; ( -- addr' len')
-00059a 3fe6 .dw XT_ONE
-00059b 05ac .dw XT_SLASHSTRING
-00059c 3820 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-00059d ff06 .dw $FF06
-00059e 6f73
-00059f 7275
-0005a0 6563 .db "source"
-0005a1 0589 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-0005a2 3dff .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-0005a3 0016 .dw USER_SOURCE
-0005a4 3dc8 .dw XT_UDEFERFETCH
-0005a5 3dd4 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-0005a6 ff07 .dw $ff07
-0005a7 732f
-0005a8 7274
-0005a9 6e69
-0005aa 0067 .db "/string",0
-0005ab 059d .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-0005ac 3801 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-0005ad 38e1 .dw XT_ROT
-0005ae 38cf .dw XT_OVER
-0005af 399d .dw XT_PLUS
-0005b0 38e1 .dw XT_ROT
-0005b1 38e1 .dw XT_ROT
-0005b2 3993 .dw XT_MINUS
-0005b3 3820 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-0005b4 ff0a .dw $FF0A
-0005b5 6170
-0005b6 7372
-0005b7 2d65
-0005b8 616e
-0005b9 656d .db "parse-name"
-0005ba 05a6 .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-0005bb 3801 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-0005bc 3f54 .dw XT_BL
-0005bd 05bf .dw XT_SKIPSCANCHAR
-0005be 3820 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-0005bf 3801 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-0005c0 38ff .dw XT_TO_R
-0005c1 05a2 .dw XT_SOURCE
-0005c2 3ee2 .dw XT_TO_IN
-0005c3 3879 .dw XT_FETCH
-0005c4 05ac .dw XT_SLASHSTRING
-
-0005c5 3908 .dw XT_R_FETCH
-0005c6 0461 .dw XT_CSKIP
-0005c7 38f6 .dw XT_R_FROM
-0005c8 0478 .dw XT_CSCAN
-
- ; adjust >IN
-0005c9 3ec9 .dw XT_2DUP
-0005ca 399d .dw XT_PLUS
-0005cb 05a2 .dw XT_SOURCE
-0005cc 38d9 .dw XT_DROP
-0005cd 3993 .dw XT_MINUS
-0005ce 3ee2 .dw XT_TO_IN
-0005cf 3881 .dw XT_STORE
-0005d0 3820 .dw XT_EXIT
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-0005d1 ff03 .dw $ff03
-0005d2 7073
-0005d3 0030 .db "sp0",0
-0005d4 05b4 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-0005d5 386f .dw PFA_DOVALUE1
- PFA_SP0:
-0005d6 0006 .dw USER_SP0
-0005d7 3dc8 .dw XT_UDEFERFETCH
-0005d8 3dd4 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-0005d9 ff02 .dw $ff02
-0005da 7073 .db "sp"
-0005db 05d1 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-0005dc 3858 .dw PFA_DOUSER
- PFA_SP:
-0005dd 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-0005de ff03 .dw $ff03
-0005df 7072
-0005e0 0030 .db "rp0",0
-0005e1 05d9 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-0005e2 3801 .dw DO_COLON
- PFA_RP0:
-0005e3 05e6 .dw XT_DORP0
-0005e4 3879 .dw XT_FETCH
-0005e5 3820 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-0005e6 3858 .dw PFA_DOUSER
- PFA_DORP0:
-0005e7 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-0005e8 ff05 .dw $ff05
-0005e9 6564
-0005ea 7470
-0005eb 0068 .db "depth",0
-0005ec 05de .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-0005ed 3801 .dw DO_COLON
- PFA_DEPTH:
- .endif
-0005ee 05d5 .dw XT_SP0
-0005ef 3a8d .dw XT_SP_FETCH
-0005f0 3993 .dw XT_MINUS
-0005f1 3a04 .dw XT_2SLASH
-0005f2 3a35 .dw XT_1MINUS
-0005f3 3820 .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-0005f4 ff10 .dw $ff10
-0005f5 6f66
-0005f6 7472
-0005f7 2d68
-0005f8 6572
-0005f9 6f63
-0005fa 6e67
-0005fb 7a69
-0005fc 7265 .db "forth-recognizer"
-0005fd 05e8 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-0005fe 386f .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-0005ff 003e .dw CFG_FORTHRECOGNIZER
-000600 3da0 .dw XT_EDEFERFETCH
-000601 3daa .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-000602 ff09 .dw $ff09
-000603 6572
-000604 6f63
-000605 6e67
-000606 7a69
-000607 0065 .db "recognize",0
-000608 05f4 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-000609 3801 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-00060a 383d .dw XT_DOLITERAL
-00060b 0614 .dw XT_RECOGNIZE_A
-00060c 38c4 .dw XT_SWAP
-00060d 09a7 .dw XT_MAPSTACK
-00060e 391a .dw XT_ZEROEQUAL
-00060f 3836 .dw XT_DOCONDBRANCH
-000610 0613 DEST(PFA_RECOGNIZE1)
-000611 3ed2 .dw XT_2DROP
-000612 0696 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-000613 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-000614 3801 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-000615 38e1 .dw XT_ROT ; -- len xt addr
-000616 38e1 .dw XT_ROT ; -- xt addr len
-000617 3ec9 .dw XT_2DUP
-000618 3b1e .dw XT_2TO_R
-000619 38e1 .dw XT_ROT ; -- addr len xt
-00061a 382a .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-00061b 3b2d .dw XT_2R_FROM
-00061c 38e1 .dw XT_ROT
-00061d 38b1 .dw XT_DUP
-00061e 0696 .dw XT_DT_NULL
-00061f 3fdf .dw XT_EQUAL
-000620 3836 .dw XT_DOCONDBRANCH
-000621 0625 DEST(PFA_RECOGNIZE_A1)
-000622 38d9 .dw XT_DROP
-000623 3954 .dw XT_ZERO
-000624 3820 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-000625 38f0 .dw XT_NIP
-000626 38f0 .dw XT_NIP
-000627 394b .dw XT_TRUE
-000628 3820 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-000629 ff09 .dw $ff09
-00062a 6e69
-00062b 6574
-00062c 7072
-00062d 6572
-00062e 0074 .db "interpret",0
-00062f 0602 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-000630 3801 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-000631 05bb .dw XT_PARSENAME ; ( -- addr len )
-000632 38b1 .dw XT_DUP ; ( -- addr len flag)
-000633 3836 .dw XT_DOCONDBRANCH
-000634 0641 DEST(PFA_INTERPRET2)
-000635 05fe .dw XT_FORTHRECOGNIZER
-000636 0609 .dw XT_RECOGNIZE
-000637 3eb7 .dw XT_STATE
-000638 3879 .dw XT_FETCH
-000639 3836 .dw XT_DOCONDBRANCH
-00063a 063c DEST(PFA_INTERPRET1)
-00063b 01d1 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-00063c 3bcb .dw XT_FETCHI
-00063d 382a .dw XT_EXECUTE
-00063e 3f8b .dw XT_QSTACK
-00063f 382f .dw XT_DOBRANCH
-000640 0631 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-000641 3ed2 .dw XT_2DROP
-000642 3820 .dw XT_EXIT
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-000643 ff06 .dw $ff06
-000644 7464
-000645 6e3a
-000646 6d75 .db "dt:num"
-000647 0629 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-000648 3852 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-000649 01a5 .dw XT_NOOP ; interpret
-00064a 077d .dw XT_LITERAL ; compile
-00064b 077d .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-00064c ff07 .dw $ff07
-00064d 7464
-00064e 643a
-00064f 756e
-000650 006d .db "dt:dnum",0
-000651 0643 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-000652 3852 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-000653 01a5 .dw XT_NOOP ; interpret
-000654 3fd7 .dw XT_2LITERAL ; compile
-000655 3fd7 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-000656 ff07 .dw $ff07
-000657 6572
-000658 3a63
-000659 756e
-00065a 006d .db "rec:num",0
-00065b 064c .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-00065c 3801 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-00065d 04fb .dw XT_NUMBER
-00065e 3836 .dw XT_DOCONDBRANCH
-00065f 0668 DEST(PFA_REC_NONUMBER)
-000660 3fe6 .dw XT_ONE
-000661 3fdf .dw XT_EQUAL
-000662 3836 .dw XT_DOCONDBRANCH
-000663 0666 DEST(PFA_REC_INTNUM2)
-000664 0648 .dw XT_DT_NUM
-000665 3820 .dw XT_EXIT
- PFA_REC_INTNUM2:
-000666 0652 .dw XT_DT_DNUM
-000667 3820 .dw XT_EXIT
- PFA_REC_NONUMBER:
-000668 0696 .dw XT_DT_NULL
-000669 3820 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00066a ff08 .dw $ff08
-00066b 6572
-00066c 3a63
-00066d 6966
-00066e 646e .db "rec:find"
-00066f 0656 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-000670 3801 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-000671 070b .DW XT_FINDXT
-000672 38b1 .dw XT_DUP
-000673 391a .dw XT_ZEROEQUAL
-000674 3836 .dw XT_DOCONDBRANCH
-000675 0679 DEST(PFA_REC_WORD_FOUND)
-000676 38d9 .dw XT_DROP
-000677 0696 .dw XT_DT_NULL
-000678 3820 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-000679 0680 .dw XT_DT_XT
-
-00067a 3820 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-00067b ff05 .dw $ff05
-00067c 7464
-00067d 783a
-00067e 0074 .db "dt:xt",0
-00067f 066a .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-000680 3852 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-000681 0684 .dw XT_R_WORD_INTERPRET
-000682 0688 .dw XT_R_WORD_COMPILE
-000683 3fd7 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-000684 3801 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-000685 38d9 .dw XT_DROP ; the flags are in the way
-000686 382a .dw XT_EXECUTE
-000687 3820 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-000688 3801 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-000689 3921 .dw XT_ZEROLESS
-00068a 3836 .dw XT_DOCONDBRANCH
-00068b 068e DEST(PFA_R_WORD_COMPILE1)
-00068c 0767 .dw XT_COMMA
-00068d 3820 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-00068e 382a .dw XT_EXECUTE
-00068f 3820 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-000690 ff07 .dw $ff07
-000691 7464
-000692 6e3a
-000693 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-000694 006c .db "dt:null"
-000695 067b .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-000696 3852 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-000697 069a .dw XT_FAIL ; interpret
-000698 069a .dw XT_FAIL ; compile
-000699 069a .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00069a 3801 .dw DO_COLON
- PFA_FAIL:
- .endif
-00069b 383d .dw XT_DOLITERAL
-00069c fff3 .dw -13
-00069d 3d86 .dw XT_THROW
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-00069e ff0f .dw $ff0f
-00069f 6573
-0006a0 7261
-0006a1 6863
-0006a2 772d
-0006a3 726f
-0006a4 6c64
-0006a5 7369
-0006a6 0074 .db "search-wordlist",0
-0006a7 0690 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-0006a8 3801 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-0006a9 38ff .dw XT_TO_R
-0006aa 3954 .dw XT_ZERO
-0006ab 383d .dw XT_DOLITERAL
-0006ac 06bd .dw XT_ISWORD
-0006ad 38f6 .dw XT_R_FROM
-0006ae 06da .dw XT_TRAVERSEWORDLIST
-0006af 38b1 .dw XT_DUP
-0006b0 391a .dw XT_ZEROEQUAL
-0006b1 3836 .dw XT_DOCONDBRANCH
-0006b2 06b7 DEST(PFA_SEARCH_WORDLIST1)
-0006b3 3ed2 .dw XT_2DROP
-0006b4 38d9 .dw XT_DROP
-0006b5 3954 .dw XT_ZERO
-0006b6 3820 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-0006b7 38b1 .dw XT_DUP
-0006b8 0701 .dw XT_NFA2CFA
- ; .. and get the header flag
-0006b9 38c4 .dw XT_SWAP
-0006ba 0180 .dw XT_NAME2FLAGS
-0006bb 016e .dw XT_IMMEDIATEQ
-0006bc 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-0006bd 3801 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-0006be 38ff .dw XT_TO_R
-0006bf 38d9 .dw XT_DROP
-0006c0 3ec9 .dw XT_2DUP
-0006c1 3908 .dw XT_R_FETCH ; -- addr len addr len nt
-0006c2 06f5 .dw XT_NAME2STRING
-0006c3 01da .dw XT_ICOMPARE ; (-- addr len f )
-0006c4 3836 .dw XT_DOCONDBRANCH
-0006c5 06cb DEST(PFA_ISWORD3)
- ; not now
-0006c6 38f6 .dw XT_R_FROM
-0006c7 38d9 .dw XT_DROP
-0006c8 3954 .dw XT_ZERO
-0006c9 394b .dw XT_TRUE ; maybe next word
-0006ca 3820 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-0006cb 3ed2 .dw XT_2DROP
-0006cc 38f6 .dw XT_R_FROM
-0006cd 3954 .dw XT_ZERO ; finish traverse-wordlist
-0006ce 3820 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-0006cf ff11 .dw $ff11
-0006d0 7274
-0006d1 7661
-0006d2 7265
-0006d3 6573
-0006d4 772d
-0006d5 726f
-0006d6 6c64
-0006d7 7369
-0006d8 0074 .db "traverse-wordlist",0
-0006d9 069e .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-0006da 3801 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-0006db 3b5f .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-0006dc 38b1 .dw XT_DUP ; ( -- xt nt nt )
-0006dd 3836 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-0006de 06eb DEST(PFA_TRAVERSEWORDLIST2)
-0006df 3ec9 .dw XT_2DUP
-0006e0 3b1e .dw XT_2TO_R
-0006e1 38c4 .dw XT_SWAP
-0006e2 382a .dw XT_EXECUTE
-0006e3 3b2d .dw XT_2R_FROM
-0006e4 38e1 .dw XT_ROT
-0006e5 3836 .dw XT_DOCONDBRANCH
-0006e6 06eb DEST(PFA_TRAVERSEWORDLIST2)
-0006e7 0a16 .dw XT_NFA2LFA
-0006e8 3bcb .dw XT_FETCHI
-0006e9 382f .dw XT_DOBRANCH ; ( -- addr )
-0006ea 06dc DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-0006eb 3ed2 .dw XT_2DROP
-0006ec 3820 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-0006ed ff0b .dw $ff0b
-0006ee 616e
-0006ef 656d
-0006f0 733e
-0006f1 7274
-0006f2 6e69
-0006f3 0067 .db "name>string",0
-0006f4 06cf .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-0006f5 3801 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-0006f6 042f .dw XT_ICOUNT ; ( -- addr n )
-0006f7 383d .dw XT_DOLITERAL
-0006f8 00ff .dw 255
-0006f9 3a13 .dw XT_AND ; mask immediate bit
-0006fa 3820 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-0006fb ff07 .dw $ff07
-0006fc 666e
-0006fd 3e61
-0006fe 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-0006ff 0061 .db "nfa>cfa"
-000700 06ed .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-000701 3801 .dw DO_COLON
- PFA_NFA2CFA:
-000702 0a16 .dw XT_NFA2LFA ; skip to link field
-000703 3a2f .dw XT_1PLUS ; next is the execution token
-000704 3820 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-000705 ff07 .dw $ff07
-000706 6966
-000707 646e
-000708 782d
-000709 0074 .db "find-xt",0
-00070a 06fb .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-00070b 3801 .dw DO_COLON
- PFA_FINDXT:
- .endif
-00070c 383d .dw XT_DOLITERAL
-00070d 0717 .dw XT_FINDXTA
-00070e 383d .dw XT_DOLITERAL
-00070f 004a .dw CFG_ORDERLISTLEN
-000710 09a7 .dw XT_MAPSTACK
-000711 391a .dw XT_ZEROEQUAL
-000712 3836 .dw XT_DOCONDBRANCH
-000713 0716 DEST(PFA_FINDXT1)
-000714 3ed2 .dw XT_2DROP
-000715 3954 .dw XT_ZERO
- PFA_FINDXT1:
-000716 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-000717 3801 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-000718 38ff .dw XT_TO_R
-000719 3ec9 .dw XT_2DUP
-00071a 38f6 .dw XT_R_FROM
-00071b 06a8 .dw XT_SEARCH_WORDLIST
-00071c 38b1 .dw XT_DUP
-00071d 3836 .dw XT_DOCONDBRANCH
-00071e 0724 DEST(PFA_FINDXTA1)
-00071f 38ff .dw XT_TO_R
-000720 38f0 .dw XT_NIP
-000721 38f0 .dw XT_NIP
-000722 38f6 .dw XT_R_FROM
-000723 394b .dw XT_TRUE
- PFA_FINDXTA1:
-000724 3820 .dw XT_EXIT
-
- .include "dict/compiler1.inc"
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-000725 ff06 .dw $ff06
-000726 656e
-000727 6577
-000728 7473 .db "newest"
-000729 0705 .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-00072a 3848 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-00072b 018a .dw ram_newest
-
- .dseg
-00018a ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-00072c ff06 .dw $ff06
-00072d 616c
-00072e 6574
-00072f 7473 .db "latest"
-000730 0725 .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000731 3848 .dw PFA_DOVARIABLE
- PFA_LATEST:
-000732 018e .dw ram_latest
-
- .dseg
-00018e ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-000733 ff08 .dw $ff08
-000734 6328
-000735 6572
-000736 7461
-000737 2965 .db "(create)"
-000738 072c .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-000739 3801 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-00073a 05bb
-00073b 0890 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-00073c 38b1
-00073d 072a
-00073e 3c90
-00073f 3881 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000740 0875
-000741 072a
-000742 3881 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-000743 3820 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-000744 0001 .dw $0001
-000745 005c .db $5c,0
-000746 0733 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-000747 3801 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-000748 05a2 .dw XT_SOURCE
-000749 38f0 .dw XT_NIP
-00074a 3ee2 .dw XT_TO_IN
-00074b 3881 .dw XT_STORE
-00074c 3820 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-00074d 0001 .dw $0001
-00074e 0028 .db "(" ,0
-00074f 0744 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000750 3801 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000751 383d .dw XT_DOLITERAL
-000752 0029 .dw ')'
-000753 058e .dw XT_PARSE
-000754 3ed2 .dw XT_2DROP
-000755 3820 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-000756 ff07 .dw $ff07
-000757 6f63
-000758 706d
-000759 6c69
-00075a 0065 .db "compile",0
-00075b 074d .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-00075c 3801 .dw DO_COLON
- PFA_COMPILE:
- .endif
-00075d 38f6 .dw XT_R_FROM
-00075e 38b1 .dw XT_DUP
-00075f 01d1 .dw XT_ICELLPLUS
-000760 38ff .dw XT_TO_R
-000761 3bcb .dw XT_FETCHI
-000762 0767 .dw XT_COMMA
-000763 3820 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-000764 ff01 .dw $ff01
-000765 002c .db ',',0 ; ,
-000766 0756 .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-000767 3801 .dw DO_COLON
- PFA_COMMA:
-000768 3f12 .dw XT_DP
-000769 3b73 .dw XT_STOREI
-00076a 3f12 .dw XT_DP
-00076b 3a2f .dw XT_1PLUS
-00076c 01bf .dw XT_DOTO
-00076d 3f13 .dw PFA_DP
-00076e 3820 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-00076f 0003 .dw $0003
-000770 275b
-000771 005d .db "[']",0
-000772 0764 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-000773 3801 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-000774 0448 .dw XT_TICK
-000775 077d .dw XT_LITERAL
-000776 3820 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-000777 0007 .dw $0007
-000778 696c
-000779 6574
-00077a 6172
-00077b 006c .db "literal",0
-00077c 076f .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-00077d 3801 .dw DO_COLON
- PFA_LITERAL:
- .endif
-00077e 075c .DW XT_COMPILE
-00077f 383d .DW XT_DOLITERAL
-000780 0767 .DW XT_COMMA
-000781 3820 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-000782 0008 .dw $0008
-000783 6c73
-000784 7469
-000785 7265
-000786 6c61 .db "sliteral"
-000787 0777 .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-000788 3801 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-000789 075c .dw XT_COMPILE
-00078a 03d0 .dw XT_DOSLITERAL ; ( -- addr n)
-00078b 03de .dw XT_SCOMMA
-00078c 3820 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-00078d 3801 .dw DO_COLON
- PFA_GMARK:
-00078e 3f12 .dw XT_DP
-00078f 075c .dw XT_COMPILE
-000790 ffff .dw -1 ; ffff does not erase flash
-000791 3820 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-000792 3801 .dw DO_COLON
- PFA_GRESOLVE:
-000793 3f8b .dw XT_QSTACK
-000794 3f12 .dw XT_DP
-000795 38c4 .dw XT_SWAP
-000796 3b73 .dw XT_STOREI
-000797 3820 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-000798 3801 .dw DO_COLON
- PFA_LMARK:
-000799 3f12 .dw XT_DP
-00079a 3820 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-00079b 3801 .dw DO_COLON
- PFA_LRESOLVE:
-00079c 3f8b .dw XT_QSTACK
-00079d 0767 .dw XT_COMMA
-00079e 3820 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-00079f 0005 .dw $0005
-0007a0 6861
-0007a1 6165
-0007a2 0064 .db "ahead",0
-0007a3 0782 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-0007a4 3801 .dw DO_COLON
- PFA_AHEAD:
- .endif
-0007a5 075c .dw XT_COMPILE
-0007a6 382f .dw XT_DOBRANCH
-0007a7 078d .dw XT_GMARK
-0007a8 3820 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-0007a9 0002 .dw $0002
-0007aa 6669 .db "if"
-0007ab 079f .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-0007ac 3801 .dw DO_COLON
- PFA_IF:
- .endif
-0007ad 075c .dw XT_COMPILE
-0007ae 3836 .dw XT_DOCONDBRANCH
-0007af 078d .dw XT_GMARK
-0007b0 3820 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-0007b1 0004 .dw $0004
-0007b2 6c65
-0007b3 6573 .db "else"
-0007b4 07a9 .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-0007b5 3801 .dw DO_COLON
- PFA_ELSE:
- .endif
-0007b6 075c .dw XT_COMPILE
-0007b7 382f .dw XT_DOBRANCH
-0007b8 078d .dw XT_GMARK
-0007b9 38c4 .dw XT_SWAP
-0007ba 0792 .dw XT_GRESOLVE
-0007bb 3820 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-0007bc 0004 .dw $0004
-0007bd 6874
-0007be 6e65 .db "then"
-0007bf 07b1 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-0007c0 3801 .dw DO_COLON
- PFA_THEN:
- .endif
-0007c1 0792 .dw XT_GRESOLVE
-0007c2 3820 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-0007c3 0005 .dw $0005
-0007c4 6562
-0007c5 6967
-0007c6 006e .db "begin",0
-0007c7 07bc .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-0007c8 3801 .dw DO_COLON
- PFA_BEGIN:
- .endif
-0007c9 0798 .dw XT_LMARK
-0007ca 3820 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-0007cb 0005 .dw $0005
-0007cc 6877
-0007cd 6c69
-0007ce 0065 .db "while",0
-0007cf 07c3 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-0007d0 3801 .dw DO_COLON
- PFA_WHILE:
- .endif
-0007d1 07ac .dw XT_IF
-0007d2 38c4 .dw XT_SWAP
-0007d3 3820 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-0007d4 0006 .dw $0006
-0007d5 6572
-0007d6 6570
-0007d7 7461 .db "repeat"
-0007d8 07cb .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-0007d9 3801 .dw DO_COLON
- PFA_REPEAT:
- .endif
-0007da 07ed .dw XT_AGAIN
-0007db 07c0 .dw XT_THEN
-0007dc 3820 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-0007dd 0005 .dw $0005
-0007de 6e75
-0007df 6974
-0007e0 006c .db "until",0
-0007e1 07d4 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-0007e2 3801 .dw DO_COLON
- PFA_UNTIL:
- .endif
-0007e3 383d .dw XT_DOLITERAL
-0007e4 3836 .dw XT_DOCONDBRANCH
-0007e5 0767 .dw XT_COMMA
-
-0007e6 079b .dw XT_LRESOLVE
-0007e7 3820 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-0007e8 0005 .dw $0005
-0007e9 6761
-0007ea 6961
-0007eb 006e .db "again",0
-0007ec 07dd .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-0007ed 3801 .dw DO_COLON
- PFA_AGAIN:
- .endif
-0007ee 075c .dw XT_COMPILE
-0007ef 382f .dw XT_DOBRANCH
-0007f0 079b .dw XT_LRESOLVE
-0007f1 3820 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-0007f2 0002 .dw $0002
-0007f3 6f64 .db "do"
-0007f4 07e8 .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-0007f5 3801 .dw DO_COLON
- PFA_DO:
-
- .endif
-0007f6 075c .dw XT_COMPILE
-0007f7 3a9b .dw XT_DODO
-0007f8 0798 .dw XT_LMARK
-0007f9 3954 .dw XT_ZERO
-0007fa 0850 .dw XT_TO_L
-0007fb 3820 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-0007fc 0004 .dw $0004
-0007fd 6f6c
-0007fe 706f .db "loop"
-0007ff 07f2 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000800 3801 .dw DO_COLON
- PFA_LOOP:
- .endif
-000801 075c .dw XT_COMPILE
-000802 3ac9 .dw XT_DOLOOP
-000803 0837 .dw XT_ENDLOOP
-000804 3820 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-000805 0005 .dw $0005
-000806 6c2b
-000807 6f6f
-000808 0070 .db "+loop",0
-000809 07fc .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-00080a 3801 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-00080b 075c .dw XT_COMPILE
-00080c 3aba .dw XT_DOPLUSLOOP
-00080d 0837 .dw XT_ENDLOOP
-00080e 3820 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-00080f 0005 .dw $0005
-000810 656c
-000811 7661
-000812 0065 .db "leave",0
-000813 0805 .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-000814 3801 .dw DO_COLON
- PFA_LEAVE:
- .endif
-000815 075c
-000816 3ad4 .DW XT_COMPILE,XT_UNLOOP
-000817 07a4
-000818 0850
-000819 3820 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-00081a 0003 .dw $0003
-00081b 643f
-00081c 006f .db "?do",0
-00081d 080f .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-00081e 3801 .dw DO_COLON
- PFA_QDO:
- .endif
-00081f 075c .dw XT_COMPILE
-000820 0826 .dw XT_QDOCHECK
-000821 07ac .dw XT_IF
-000822 07f5 .dw XT_DO
-000823 38c4 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-000824 0850 .dw XT_TO_L ; then follows at the end.
-000825 3820 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-000826 3801 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-000827 3ec9 .dw XT_2DUP
-000828 3fdf .dw XT_EQUAL
-000829 38b1 .dw XT_DUP
-00082a 38ff .dw XT_TO_R
-00082b 3836 .dw XT_DOCONDBRANCH
-00082c 082e DEST(PFA_QDOCHECK1)
-00082d 3ed2 .dw XT_2DROP
- PFA_QDOCHECK1:
-00082e 38f6 .dw XT_R_FROM
-00082f 39fd .dw XT_INVERT
-000830 3820 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000831 ff07 .dw $ff07
-000832 6e65
-000833 6c64
-000834 6f6f
-000835 0070 .db "endloop",0
-000836 081a .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-000837 3801 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-000838 079b .DW XT_LRESOLVE
-000839 0844
-00083a 38b9
-00083b 3836 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-00083c 0840 DEST(LOOP2)
-00083d 07c0 .DW XT_THEN
-00083e 382f .dw XT_DOBRANCH
-00083f 0839 DEST(LOOP1)
-000840 3820 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000841 ff02 .dw $ff02
-000842 3e6c .db "l>"
-000843 0831 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-000844 3801 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-000845 0863 .dw XT_LP
-000846 3879 .dw XT_FETCH
-000847 3879 .dw XT_FETCH
-000848 383d .dw XT_DOLITERAL
-000849 fffe .dw -2
-00084a 0863 .dw XT_LP
-00084b 3a65 .dw XT_PLUSSTORE
-00084c 3820 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-00084d ff02 .dw $ff02
-00084e 6c3e .db ">l"
-00084f 0841 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000850 3801 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000851 3feb .dw XT_TWO
-000852 0863 .dw XT_LP
-000853 3a65 .dw XT_PLUSSTORE
-000854 0863 .dw XT_LP
-000855 3879 .dw XT_FETCH
-000856 3881 .dw XT_STORE
-000857 3820 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-000858 ff03 .dw $ff03
-000859 706c
-00085a 0030 .db "lp0",0
-00085b 084d .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-00085c 386f .dw PFA_DOVALUE1
- PFA_LP0:
-00085d 0040 .dw CFG_LP0
-00085e 3da0 .dw XT_EDEFERFETCH
-00085f 3daa .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-000860 ff02 .dw $ff02
-000861 706c .db "lp"
-000862 0858 .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-000863 3848 .dw PFA_DOVARIABLE
- PFA_LP:
-000864 0190 .dw ram_lp
-
- .dseg
-000190 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-000865 ff06 .dw $ff06
-000866 7263
-000867 6165
-000868 6574 .db "create"
-000869 0860 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-00086a 3801 .dw DO_COLON
- PFA_CREATE:
- .endif
-00086b 0739 .dw XT_DOCREATE
-00086c 0899 .dw XT_REVEAL
-00086d 075c .dw XT_COMPILE
-00086e 3852 .dw PFA_DOCONSTANT
-00086f 3820 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-000870 ff06 .dw $ff06
-000871 6568
-000872 6461
-000873 7265 .db "header"
-000874 0865 .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-000875 3801 .dw DO_COLON
- PFA_HEADER:
-000876 3f12 .dw XT_DP ; the new Name Field
-000877 38ff .dw XT_TO_R
-000878 38ff .dw XT_TO_R ; ( R: NFA WID )
-000879 38b1 .dw XT_DUP
-00087a 3928 .dw XT_GREATERZERO
-00087b 3836 .dw XT_DOCONDBRANCH
-00087c 0887 .dw PFA_HEADER1
-00087d 38b1 .dw XT_DUP
-00087e 383d .dw XT_DOLITERAL
-00087f ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-000880 3a1c .dw XT_OR
-000881 03e2 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-000882 38f6 .dw XT_R_FROM
-000883 3b5f .dw XT_FETCHE
-000884 0767 .dw XT_COMMA
-000885 38f6 .dw XT_R_FROM
-000886 3820 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-000887 383d .dw XT_DOLITERAL
-000888 fff0 .dw -16
-000889 3d86 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-00088a ff07 .dw $ff07
-00088b 6c77
-00088c 6373
-00088d 706f
-00088e 0065 .db "wlscope",0
-00088f 0870 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-000890 3dff .dw PFA_DODEFER1
- PFA_WLSCOPE:
-000891 003c .dw CFG_WLSCOPE
-000892 3da0 .dw XT_EDEFERFETCH
-000893 3daa .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-000894 ff06 .dw $ff06
-000895 6572
-000896 6576
-000897 6c61 .db "reveal"
-000898 088a .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-000899 3801 .dw DO_COLON
- PFA_REVEAL:
- .endif
-00089a 072a
-00089b 3c90
-00089c 3879 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-00089d 38b9
-00089e 3836 .DW XT_QDUP,XT_DOCONDBRANCH
-00089f 08a4 DEST(REVEAL1)
-0008a0 072a
-0008a1 3879
-0008a2 38c4
-0008a3 3b3b .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-0008a4 3820 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-0008a5 0005 .dw $0005
-0008a6 6f64
-0008a7 7365
-0008a8 003e .db "does>",0
-0008a9 0894 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-0008aa 3801 .dw DO_COLON
- PFA_DOES:
-0008ab 075c .dw XT_COMPILE
-0008ac 08bd .dw XT_DODOES
-0008ad 075c .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-0008ae 940e .dw $940e ; the address of this compiled
-0008af 075c .dw XT_COMPILE ; code will replace the XT of the
-0008b0 08b2 .dw DO_DODOES ; word that CREATE created
-0008b1 3820 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-0008b2 939a
-0008b3 938a savetos
-0008b4 01cb movw tosl, wl
-0008b5 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-0008b6 917f pop wh
-0008b7 916f pop wl
-
-0008b8 93bf push XH
-0008b9 93af push XL
-0008ba 01db movw XL, wl
-0008bb 940c 3805 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-0008bd 3801 .dw DO_COLON
- PFA_DODOES:
-0008be 38f6 .dw XT_R_FROM
-0008bf 072a .dw XT_NEWEST
-0008c0 3c90 .dw XT_CELLPLUS
-0008c1 3879 .dw XT_FETCH
-0008c2 3b5f .dw XT_FETCHE
-0008c3 0701 .dw XT_NFA2CFA
-0008c4 3b73 .dw XT_STOREI
-0008c5 3820 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-0008c6 ff01 .dw $ff01
-0008c7 003a .db ":",0
-0008c8 08a5 .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-0008c9 3801 .dw DO_COLON
- PFA_COLON:
- .endif
-0008ca 0739 .dw XT_DOCREATE
-0008cb 08d4 .dw XT_COLONNONAME
-0008cc 38d9 .dw XT_DROP
-0008cd 3820 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-0008ce ff07 .dw $ff07
-0008cf 6e3a
-0008d0 6e6f
-0008d1 6d61
-0008d2 0065 .db ":noname",0
-0008d3 08c6 .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-0008d4 3801 .dw DO_COLON
- PFA_COLONNONAME:
-0008d5 3f12 .dw XT_DP
-0008d6 38b1 .dw XT_DUP
-0008d7 0731 .dw XT_LATEST
-0008d8 3881 .dw XT_STORE
-
-0008d9 075c .dw XT_COMPILE
-0008da 3801 .dw DO_COLON
-
-0008db 08e9 .dw XT_RBRACKET
-0008dc 3820 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-0008dd 0001 .dw $0001
-0008de 003b .db $3b,0
-0008df 08ce .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-0008e0 3801 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-0008e1 075c .dw XT_COMPILE
-0008e2 3820 .dw XT_EXIT
-0008e3 08f1 .dw XT_LBRACKET
-0008e4 0899 .dw XT_REVEAL
-0008e5 3820 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-0008e6 ff01 .dw $ff01
-0008e7 005d .db "]",0
-0008e8 08dd .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-0008e9 3801 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-0008ea 3fe6 .dw XT_ONE
-0008eb 3eb7 .dw XT_STATE
-0008ec 3881 .dw XT_STORE
-0008ed 3820 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-0008ee 0001 .dw $0001
-0008ef 005b .db "[",0
-0008f0 08e6 .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-0008f1 3801 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-0008f2 3954 .dw XT_ZERO
-0008f3 3eb7 .dw XT_STATE
-0008f4 3881 .dw XT_STORE
-0008f5 3820 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-0008f6 ff08 .dw $ff08
-0008f7 6176
-0008f8 6972
-0008f9 6261
-0008fa 656c .db "variable"
-0008fb 08ee .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-0008fc 3801 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-0008fd 3f23 .dw XT_HERE
-0008fe 0908 .dw XT_CONSTANT
-0008ff 3feb .dw XT_TWO
-000900 3f2c .dw XT_ALLOT
-000901 3820 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-000902 ff08 .dw $ff08
-000903 6f63
-000904 736e
-000905 6174
-000906 746e .db "constant"
-000907 08f6 .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-000908 3801 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-000909 0739 .dw XT_DOCREATE
-00090a 0899 .dw XT_REVEAL
-00090b 075c .dw XT_COMPILE
-00090c 3848 .dw PFA_DOVARIABLE
-00090d 0767 .dw XT_COMMA
-00090e 3820 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-00090f ff04 .dw $ff04
-000910 7375
-000911 7265 .db "user"
-000912 0902 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-000913 3801 .dw DO_COLON
- PFA_USER:
-000914 0739 .dw XT_DOCREATE
-000915 0899 .dw XT_REVEAL
-
-000916 075c .dw XT_COMPILE
-000917 3858 .dw PFA_DOUSER
-000918 0767 .dw XT_COMMA
-000919 3820 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-00091a 0007 .dw $0007
-00091b 6572
-00091c 7563
-00091d 7372
-00091e 0065 .db "recurse",0
-00091f 090f .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000920 3801 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000921 0731 .dw XT_LATEST
-000922 3879 .dw XT_FETCH
-000923 0767 .dw XT_COMMA
-000924 3820 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-000925 ff09 .dw $ff09
-000926 6d69
-000927 656d
-000928 6964
-000929 7461
-00092a 0065 .db "immediate",0
-00092b 091a .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-00092c 3801 .dw DO_COLON
- PFA_IMMEDIATE:
-00092d 09ce .dw XT_GET_CURRENT
-00092e 3b5f .dw XT_FETCHE
-00092f 38b1 .dw XT_DUP
-000930 3bcb .dw XT_FETCHI
-000931 383d .dw XT_DOLITERAL
-000932 7fff .dw $7fff
-000933 3a13 .dw XT_AND
-000934 38c4 .dw XT_SWAP
-000935 3b73 .dw XT_STOREI
-000936 3820 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-000937 0006 .dw $0006
-000938 635b
-000939 6168
-00093a 5d72 .db "[char]"
-00093b 0925 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-00093c 3801 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-00093d 075c .dw XT_COMPILE
-00093e 383d .dw XT_DOLITERAL
-00093f 04f1 .dw XT_CHAR
-000940 0767 .dw XT_COMMA
-000941 3820 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-000942 0006 .dw $0006
-000943 6261
-000944 726f
-000945 2274 .db "abort",'"'
-000946 0937 .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-000947 3801 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-000948 3e8a .dw XT_SQUOTE
-000949 075c .dw XT_COMPILE
-00094a 0959 .dw XT_QABORT
-00094b 3820 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-00094c ff05 .dw $ff05
-00094d 6261
-00094e 726f
-00094f 0074 .db "abort",0
-000950 0942 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000951 3801 .dw DO_COLON
- PFA_ABORT:
- .endif
-000952 394b .dw XT_TRUE
-000953 3d86 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-000954 ff06 .dw $ff06
-000955 613f
-000956 6f62
-000957 7472 .db "?abort"
-000958 094c .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-000959 3801 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-00095a 38e1
-00095b 3836 .DW XT_ROT,XT_DOCONDBRANCH
-00095c 095f DEST(QABO1)
-00095d 0403
-00095e 0951 .DW XT_ITYPE,XT_ABORT
-00095f 3ed2
-000960 3820 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000961 ff09 .dw $ff09
-000962 6567
-000963 2d74
-000964 7473
-000965 6361
-000966 006b .db "get-stack",0
-000967 0954 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-000968 3801 .dw DO_COLON
- .endif
-000969 38b1 .dw XT_DUP
-00096a 3c90 .dw XT_CELLPLUS
-00096b 38c4 .dw XT_SWAP
-00096c 3b5f .dw XT_FETCHE
-00096d 38b1 .dw XT_DUP
-00096e 38ff .dw XT_TO_R
-00096f 3954 .dw XT_ZERO
-000970 38c4 .dw XT_SWAP ; go from bigger to smaller addresses
-000971 0826 .dw XT_QDOCHECK
-000972 3836 .dw XT_DOCONDBRANCH
-000973 097f DEST(PFA_N_FETCH_E2)
-000974 3a9b .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-000975 3aac .dw XT_I
-000976 3a35 .dw XT_1MINUS
-000977 3ec4 .dw XT_CELLS ; ( -- ee-addr i*2 )
-000978 38cf .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-000979 399d .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-00097a 3b5f .dw XT_FETCHE ;( -- ee-addr item_i )
-00097b 38c4 .dw XT_SWAP ;( -- item_i ee-addr )
-00097c 394b .dw XT_TRUE ; shortcut for -1
-00097d 3aba .dw XT_DOPLUSLOOP
-00097e 0975 DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-00097f 3ed2 .dw XT_2DROP
-000980 38f6 .dw XT_R_FROM
-000981 3820 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-000982 ff09 .dw $ff09
-000983 6573
-000984 2d74
-000985 7473
-000986 6361
-000987 006b .db "set-stack",0
-000988 0961 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-000989 3801 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-00098a 38cf .dw XT_OVER
-00098b 3921 .dw XT_ZEROLESS
-00098c 3836 .dw XT_DOCONDBRANCH
-00098d 0991 DEST(PFA_SET_STACK0)
-00098e 383d .dw XT_DOLITERAL
-00098f fffc .dw -4
-000990 3d86 .dw XT_THROW
- PFA_SET_STACK0:
-000991 3ec9 .dw XT_2DUP
-000992 3b3b .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-000993 38c4 .dw XT_SWAP
-000994 3954 .dw XT_ZERO
-000995 0826 .dw XT_QDOCHECK
-000996 3836 .dw XT_DOCONDBRANCH
-000997 099e DEST(PFA_SET_STACK2)
-000998 3a9b .dw XT_DODO
- PFA_SET_STACK1:
-000999 3c90 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-00099a 3eda .dw XT_TUCK ; ( -- e-addr i_x e-addr
-00099b 3b3b .dw XT_STOREE
-00099c 3ac9 .dw XT_DOLOOP
-00099d 0999 DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-00099e 38d9 .dw XT_DROP
-00099f 3820 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-0009a0 ff09 .dw $ff09
-0009a1 616d
-0009a2 2d70
-0009a3 7473
-0009a4 6361
-0009a5 006b .db "map-stack",0
-0009a6 0982 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-0009a7 3801 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-0009a8 38b1 .dw XT_DUP
-0009a9 3c90 .dw XT_CELLPLUS
-0009aa 38c4 .dw XT_SWAP
-0009ab 3b5f .dw XT_FETCHE
-0009ac 3ec4 .dw XT_CELLS
-0009ad 3f99 .dw XT_BOUNDS
-0009ae 0826 .dw XT_QDOCHECK
-0009af 3836 .dw XT_DOCONDBRANCH
-0009b0 09c3 DEST(PFA_MAPSTACK3)
-0009b1 3a9b .dw XT_DODO
- PFA_MAPSTACK1:
-0009b2 3aac .dw XT_I
-0009b3 3b5f .dw XT_FETCHE ; -- i*x XT id
-0009b4 38c4 .dw XT_SWAP
-0009b5 38ff .dw XT_TO_R
-0009b6 3908 .dw XT_R_FETCH
-0009b7 382a .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-0009b8 38b9 .dw XT_QDUP
-0009b9 3836 .dw XT_DOCONDBRANCH
-0009ba 09bf DEST(PFA_MAPSTACK2)
-0009bb 38f6 .dw XT_R_FROM
-0009bc 38d9 .dw XT_DROP
-0009bd 3ad4 .dw XT_UNLOOP
-0009be 3820 .dw XT_EXIT
- PFA_MAPSTACK2:
-0009bf 38f6 .dw XT_R_FROM
-0009c0 3feb .dw XT_TWO
-0009c1 3aba .dw XT_DOPLUSLOOP
-0009c2 09b2 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-0009c3 38d9 .dw XT_DROP
-0009c4 3954 .dw XT_ZERO
-0009c5 3820 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-0009c6 ff0b .dw $ff0b
-0009c7 6567
-0009c8 2d74
-0009c9 7563
-0009ca 7272
-0009cb 6e65
-0009cc 0074 .db "get-current",0
-0009cd 09a0 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-0009ce 3801 .dw DO_COLON
- PFA_GET_CURRENT:
-0009cf 383d .dw XT_DOLITERAL
-0009d0 0046 .dw CFG_CURRENT
-0009d1 3b5f .dw XT_FETCHE
-0009d2 3820 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-0009d3 ff09 .dw $ff09
-0009d4 6567
-0009d5 2d74
-0009d6 726f
-0009d7 6564
-0009d8 0072 .db "get-order",0
-0009d9 09c6 .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-0009da 3801 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-0009db 383d .dw XT_DOLITERAL
-0009dc 004a .dw CFG_ORDERLISTLEN
-0009dd 0968 .dw XT_GET_STACK
-0009de 3820 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-0009df ff09 .dw $ff09
-0009e0 6663
-0009e1 2d67
-0009e2 726f
-0009e3 6564
-0009e4 0072 .db "cfg-order",0
-0009e5 09d3 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-0009e6 3848 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-0009e7 004a .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-0009e8 ff07 .dw $ff07
-0009e9 6f63
-0009ea 706d
-0009eb 7261
-0009ec 0065 .db "compare",0
-0009ed 09df .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-0009ee 09ef .dw PFA_COMPARE
- PFA_COMPARE:
-0009ef 93bf push xh
-0009f0 93af push xl
-0009f1 018c movw temp0, tosl
-0009f2 9189
-0009f3 9199 loadtos
-0009f4 01dc movw xl, tosl
-0009f5 9189
-0009f6 9199 loadtos
-0009f7 019c movw temp2, tosl
-0009f8 9189
-0009f9 9199 loadtos
-0009fa 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-0009fb 90ed ld temp4, X+
-0009fc 90f1 ld temp5, Z+
-0009fd 14ef cp temp4, temp5
-0009fe f451 brne PFA_COMPARE_NOTEQUAL
-0009ff 950a dec temp0
-000a00 f019 breq PFA_COMPARE_ENDREACHED2
-000a01 952a dec temp2
-000a02 f7c1 brne PFA_COMPARE_LOOP
-000a03 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-000a04 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-000a05 2b02 or temp0, temp2
-000a06 f411 brne PFA_COMPARE_CHECKLASTCHAR
-000a07 2788 clr tosl
-000a08 c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-000a09 ef8f ser tosl
-000a0a c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000a0b 2f98 mov tosh, tosl
-000a0c 91af pop xl
-000a0d 91bf pop xh
-000a0e 940c 3805 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000a10 ff07 .dw $ff07
-000a11 666e
-000a12 3e61
-000a13 666c
-000a14 0061 .db "nfa>lfa",0
-000a15 09e8 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-000a16 3801 .dw DO_COLON
- PFA_NFA2LFA:
-000a17 06f5 .dw XT_NAME2STRING
-000a18 3a2f .dw XT_1PLUS
-000a19 3a04 .dw XT_2SLASH
-000a1a 399d .dw XT_PLUS
-000a1b 3820 .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
- .include "words/dot-s.asm"
-
- ; Tools
- ; stack dump
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTS:
-000a1c ff02 .dw $ff02
-000a1d 732e .db ".s"
-000a1e 0a10 .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
- XT_DOTS:
-000a1f 3801 .dw DO_COLON
- PFA_DOTS:
- .endif
-000a20 05ed .dw XT_DEPTH
-000a21 3e0a .dw XT_UDOT
-000a22 3fae .dw XT_SPACE
-000a23 05ed .dw XT_DEPTH
-000a24 3954 .dw XT_ZERO
-000a25 0826 .dw XT_QDOCHECK
-000a26 3836 .dw XT_DOCONDBRANCH
-000a27 0a2e DEST(PFA_DOTS2)
-000a28 3a9b .dw XT_DODO
- PFA_DOTS1:
-000a29 3aac .dw XT_I
-000a2a 3c84 .dw XT_PICK
-000a2b 3e0a .dw XT_UDOT
-000a2c 3ac9 .dw XT_DOLOOP
-000a2d 0a29 DEST(PFA_DOTS1)
- PFA_DOTS2:
-000a2e 3820 .dw XT_EXIT
- .include "words/spirw.asm"
-
- ; MCU
- ; SPI exchange of 1 byte
- VE_SPIRW:
-000a2f ff06 .dw $ff06
-000a30 2163
-000a31 7340
-000a32 6970 .db "c!@spi"
-000a33 0a1c .dw VE_HEAD
- .set VE_HEAD = VE_SPIRW
- XT_SPIRW:
-000a34 0a35 .dw PFA_SPIRW
- PFA_SPIRW:
-000a35 d003 rcall do_spirw
-000a36 2799 clr tosh
-000a37 940c 3805 jmp_ DO_NEXT
-
- do_spirw:
-000a39 bd8e out_ SPDR, tosl
- do_spirw1:
-000a3a b50d in_ temp0, SPSR
-000a3b 7f08 cbr temp0,7
-000a3c bd0d out_ SPSR, temp0
-000a3d b50d in_ temp0, SPSR
-000a3e ff07 sbrs temp0, 7
-000a3f cffa rjmp do_spirw1 ; wait until complete
-000a40 b58e in_ tosl, SPDR
-000a41 9508 ret
- .include "words/n-spi.asm"
-
- ; MCU
- ; read len bytes from SPI to addr
- VE_N_SPIR:
-000a42 ff05 .dw $ff05
-000a43 406e
-000a44 7073
-000a45 0069 .db "n@spi",0
-000a46 0a2f .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIR
- XT_N_SPIR:
-000a47 0a48 .dw PFA_N_SPIR
- PFA_N_SPIR:
-000a48 018c movw temp0, tosl
-000a49 9189
-000a4a 9199 loadtos
-000a4b 01fc movw zl, tosl
-000a4c 01c8 movw tosl, temp0
- PFA_N_SPIR_LOOP:
-000a4d bc2e out_ SPDR, zerol
- PFA_N_SPIR_LOOP1:
-000a4e b52d in_ temp2, SPSR
-000a4f ff27 sbrs temp2, SPIF
-000a50 cffd rjmp PFA_N_SPIR_LOOP1
-000a51 b52e in_ temp2, SPDR
-000a52 9321 st Z+, temp2
-000a53 9701 sbiw tosl, 1
-000a54 f7c1 brne PFA_N_SPIR_LOOP
-000a55 9189
-000a56 9199 loadtos
-000a57 940c 3805 jmp_ DO_NEXT
-
- ; ( addr len -- )
- ; MCU
- ; write len bytes to SPI from addr
- VE_N_SPIW:
-000a59 ff05 .dw $ff05
-000a5a 216e
-000a5b 7073
-000a5c 0069 .db "n!spi",0
-000a5d 0a42 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIW
- XT_N_SPIW:
-000a5e 0a5f .dw PFA_N_SPIW
- PFA_N_SPIW:
-000a5f 018c movw temp0, tosl
-000a60 9189
-000a61 9199 loadtos
-000a62 01fc movw zl, tosl
-000a63 01c8 movw tosl, temp0
- PFA_N_SPIW_LOOP:
-000a64 9121 ld temp2, Z+
-000a65 bd2e out_ SPDR, temp2
- PFA_N_SPIW_LOOP1:
-000a66 b52d in_ temp2, SPSR
-000a67 ff27 sbrs temp2, SPIF
-000a68 cffd rjmp PFA_N_SPIW_LOOP1
-000a69 b52e in_ temp2, SPDR ; ignore the data
-000a6a 9701 sbiw tosl, 1
-000a6b f7c1 brne PFA_N_SPIW_LOOP
-000a6c 9189
-000a6d 9199 loadtos
-000a6e 940c 3805 jmp_ DO_NEXT
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-000a70 ff0b .dw $ff0b
-000a71 7061
-000a72 6c70
-000a73 7574
-000a74 6e72
-000a75 656b
-000a76 0079 .db "applturnkey",0
-000a77 0a59 .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-000a78 3801 .dw DO_COLON
- PFA_APPLTURNKEY:
-000a79 00c7 .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-000a7a 3c97 .dw XT_INTON
- .endif
-000a7b 018a .dw XT_DOT_VER
-000a7c 3fae .dw XT_SPACE
-000a7d 3eac .dw XT_F_CPU
-000a7e 383d .dw XT_DOLITERAL
-000a7f 03e8 .dw 1000
-000a80 39c2 .dw XT_UMSLASHMOD
-000a81 38f0 .dw XT_NIP
-000a82 3f41 .dw XT_DECIMAL
-000a83 0385 .dw XT_DOT
-000a84 03d0 .dw XT_DOSLITERAL
-000a85 0004 .dw 4
-000a86 486b
-000a87 207a .db "kHz "
-000a88 0403 .dw XT_ITYPE
-000a89 3820 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-000a8a ff0b .dw $ff0b
-000a8b 6573
-000a8c 2d74
-000a8d 7563
-000a8e 7272
-000a8f 6e65
-000a90 0074 .db "set-current",0
-000a91 0a70 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-000a92 3801 .dw DO_COLON
- PFA_SET_CURRENT:
-000a93 383d .dw XT_DOLITERAL
-000a94 0046 .dw CFG_CURRENT
-000a95 3b3b .dw XT_STOREE
-000a96 3820 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-000a97 ff08 .dw $ff08
-000a98 6f77
-000a99 6472
-000a9a 696c
-000a9b 7473 .db "wordlist"
-000a9c 0a8a .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000a9d 3801 .dw DO_COLON
- PFA_WORDLIST:
-000a9e 3f1b .dw XT_EHERE
-000a9f 3954 .dw XT_ZERO
-000aa0 38cf .dw XT_OVER
-000aa1 3b3b .dw XT_STOREE
-000aa2 38b1 .dw XT_DUP
-000aa3 3c90 .dw XT_CELLPLUS
-000aa4 01bf .dw XT_DOTO
-000aa5 3f1c .dw PFA_EHERE
-000aa6 3820 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-000aa7 ff0e .dw $ff0e
-000aa8 6f66
-000aa9 7472
-000aaa 2d68
-000aab 6f77
-000aac 6472
-000aad 696c
-000aae 7473 .db "forth-wordlist"
-000aaf 0a97 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000ab0 3848 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000ab1 0048 .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000ab2 ff09 .dw $ff09
-000ab3 6573
-000ab4 2d74
-000ab5 726f
-000ab6 6564
-000ab7 0072 .db "set-order",0
-000ab8 0aa7 .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000ab9 3801 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000aba 383d .dw XT_DOLITERAL
-000abb 004a .dw CFG_ORDERLISTLEN
-000abc 0989 .dw XT_SET_STACK
-000abd 3820 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000abe ff0f .dw $ff0f
-000abf 6573
-000ac0 2d74
-000ac1 6572
-000ac2 6f63
-000ac3 6e67
-000ac4 7a69
-000ac5 7265
-000ac6 0073 .db "set-recognizers",0
-000ac7 0ab2 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000ac8 3801 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000ac9 383d .dw XT_DOLITERAL
-000aca 005c .dw CFG_RECOGNIZERLISTLEN
-000acb 0989 .dw XT_SET_STACK
-000acc 3820 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000acd ff0f .dw $ff0f
-000ace 6567
-000acf 2d74
-000ad0 6572
-000ad1 6f63
-000ad2 6e67
-000ad3 7a69
-000ad4 7265
-000ad5 0073 .db "get-recognizers",0
-000ad6 0abe .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000ad7 3801 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000ad8 383d .dw XT_DOLITERAL
-000ad9 005c .dw CFG_RECOGNIZERLISTLEN
-000ada 0968 .dw XT_GET_STACK
-000adb 3820 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000adc ff04 .dw $ff04
-000add 6f63
-000ade 6564 .db "code"
-000adf 0acd .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000ae0 3801 .dw DO_COLON
- PFA_CODE:
-000ae1 0739 .dw XT_DOCREATE
-000ae2 0899 .dw XT_REVEAL
-000ae3 3f12 .dw XT_DP
-000ae4 01d1 .dw XT_ICELLPLUS
-000ae5 0767 .dw XT_COMMA
-000ae6 3820 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-000ae7 ff08 .dw $ff08
-000ae8 6e65
-000ae9 2d64
-000aea 6f63
-000aeb 6564 .db "end-code"
-000aec 0adc .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000aed 3801 .dw DO_COLON
- PFA_ENDCODE:
-000aee 075c .dw XT_COMPILE
-000aef 940c .dw $940c
-000af0 075c .dw XT_COMPILE
-000af1 3805 .dw DO_NEXT
-000af2 3820 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000af3 ff08 .dw $ff08
-000af4 6d28
-000af5 7261
-000af6 656b
-000af7 2972 .db "(marker)"
-000af8 0ae7 .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-000af9 386f .dw PFA_DOVALUE1
- PFA_MARKER:
-000afa 0068 .dw EE_MARKER
-000afb 3da0 .dw XT_EDEFERFETCH
-000afc 3daa .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000afd 0008 .dw $0008
-000afe 6f70
-000aff 7473
-000b00 6f70
-000b01 656e .db "postpone"
-000b02 0af3 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000b03 3801 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000b04 05bb .dw XT_PARSENAME
-000b05 05fe .dw XT_FORTHRECOGNIZER
-000b06 0609 .dw XT_RECOGNIZE
-000b07 38b1 .dw XT_DUP
-000b08 38ff .dw XT_TO_R
-000b09 01d1 .dw XT_ICELLPLUS
-000b0a 01d1 .dw XT_ICELLPLUS
-000b0b 3bcb .dw XT_FETCHI
-000b0c 382a .dw XT_EXECUTE
-000b0d 38f6 .dw XT_R_FROM
-000b0e 01d1 .dw XT_ICELLPLUS
-000b0f 3bcb .dw XT_FETCHI
-000b10 0767 .dw XT_COMMA
-000b11 3820 .dw XT_EXIT
- .endif
- .include "words/2r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_2R_FETCH:
-000b12 ff03 .dw $ff03
-000b13 7232
-000b14 0040 .db "2r@",0
-000b15 0afd .dw VE_HEAD
- .set VE_HEAD = VE_2R_FETCH
- XT_2R_FETCH:
-000b16 0b17 .dw PFA_2R_FETCH
- PFA_2R_FETCH:
-000b17 939a
-000b18 938a savetos
-000b19 91ef pop zl
-000b1a 91ff pop zh
-000b1b 918f pop tosl
-000b1c 919f pop tosh
-000b1d 939f push tosh
-000b1e 938f push tosl
-000b1f 93ff push zh
-000b20 93ef push zl
-000b21 939a
-000b22 938a savetos
-000b23 01cf movw tosl, zl
-000b24 940c 3805 jmp_ DO_NEXT
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-003801 93bf push XH
-003802 93af push XL ; PUSH IP
-003803 01db movw XL, wl
-003804 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-003805 14b2 cp isrflag, zerol
-003806 f469 brne DO_INTERRUPT
- .endif
-003807 01fd movw zl, XL ; READ IP
-003808 0fee
-003809 1fff
-00380a 9165
-00380b 9175 readflashcell wl, wh
-00380c 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00380d 01fb movw zl, wl
-00380e 0fee
-00380f 1fff
-003810 9105
-003811 9115 readflashcell temp0,temp1
-003812 01f8 movw zl, temp0
-003813 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-003814 939a
-003815 938a savetos
-003816 2d8b mov tosl, isrflag
-003817 2799 clr tosh
-003818 24bb clr isrflag
-003819 ec60 ldi wl, LOW(XT_ISREXEC)
-00381a e37c ldi wh, HIGH(XT_ISREXEC)
-00381b cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00381c ff04 .dw $ff04
-00381d 7865
-00381e 7469 .db "exit"
-00381f 0b12 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-003820 3821 .dw PFA_EXIT
- PFA_EXIT:
-003821 91af pop XL
-003822 91bf pop XH
-003823 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-003824 ff07 .dw $ff07
-003825 7865
-003826 6365
-003827 7475
-003828 0065 .db "execute",0
-003829 381c .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-00382a 382b .dw PFA_EXECUTE
- PFA_EXECUTE:
-00382b 01bc movw wl, tosl
-00382c 9189
-00382d 9199 loadtos
-00382e cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00382f 3830 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-003830 01fd movw zl, XL
-003831 0fee
-003832 1fff
-003833 91a5
-003834 91b5 readflashcell XL,XH
-003835 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-003836 3837 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-003837 2b98 or tosh, tosl
-003838 9189
-003839 9199 loadtos
-00383a f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00383b 9611 adiw XL, 1
-00383c cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00383d 383e .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00383e 939a
-00383f 938a savetos
-003840 01fd movw zl, xl
-003841 0fee
-003842 1fff
-003843 9185
-003844 9195 readflashcell tosl,tosh
-003845 9611 adiw xl, 1
-003846 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-003847 3848 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-003848 939a
-003849 938a savetos
-00384a 01fb movw zl, wl
-00384b 9631 adiw zl,1
-00384c 0fee
-00384d 1fff
-00384e 9185
-00384f 9195 readflashcell tosl,tosh
-003850 cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-003851 3852 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-003852 939a
-003853 938a savetos
-003854 01cb movw tosl, wl
-003855 9601 adiw tosl, 1
-003856 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-003857 3858 .dw PFA_DOUSER
- PFA_DOUSER:
-003858 939a
-003859 938a savetos
-00385a 01fb movw zl, wl
-00385b 9631 adiw zl, 1
-00385c 0fee
-00385d 1fff
-00385e 9185
-00385f 9195 readflashcell tosl,tosh
-003860 0d84 add tosl, upl
-003861 1d95 adc tosh, uph
-003862 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-003863 ff07 .dw $ff07
-003864 7628
-003865 6c61
-003866 6575
-003867 0029 .db "(value)", 0
-003868 3824 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-003869 3801 .dw DO_COLON
- PFA_DOVALUE:
-00386a 0739 .dw XT_DOCREATE
-00386b 0899 .dw XT_REVEAL
-00386c 075c .dw XT_COMPILE
-00386d 386f .dw PFA_DOVALUE1
-00386e 3820 .dw XT_EXIT
- PFA_DOVALUE1:
-00386f 940e 08b2 call_ DO_DODOES
-003871 38b1 .dw XT_DUP
-003872 01d1 .dw XT_ICELLPLUS
-003873 3bcb .dw XT_FETCHI
-003874 382a .dw XT_EXECUTE
-003875 3820 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-003876 ff01 .dw $ff01
-003877 0040 .db "@",0
-003878 3863 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-003879 387a .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-00387a 01fc movw zl, tosl
- ; low byte is read before the high byte
-00387b 9181 ld tosl, z+
-00387c 9191 ld tosh, z+
-00387d cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00387e ff01 .dw $ff01
-00387f 0021 .db "!",0
-003880 3876 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-003881 3882 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-003882 01fc movw zl, tosl
-003883 9189
-003884 9199 loadtos
- ; the high byte is written before the low byte
-003885 8391 std Z+1, tosh
-003886 8380 std Z+0, tosl
-003887 9189
-003888 9199 loadtos
-003889 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-00388a ff02 .dw $ff02
-00388b 2163 .db "c!"
-00388c 387e .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00388d 388e .dw PFA_CSTORE
- PFA_CSTORE:
-00388e 01fc movw zl, tosl
-00388f 9189
-003890 9199 loadtos
-003891 8380 st Z, tosl
-003892 9189
-003893 9199 loadtos
-003894 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-003895 ff02 .dw $ff02
-003896 4063 .db "c@"
-003897 388a .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-003898 3899 .dw PFA_CFETCH
- PFA_CFETCH:
-003899 01fc movw zl, tosl
-00389a 2799 clr tosh
-00389b 8180 ld tosl, Z
-00389c cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00389d ff02 .dw $ff02
-00389e 7540 .db "@u"
-00389f 3895 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-0038a0 3801 .dw DO_COLON
- PFA_FETCHU:
-0038a1 3b02 .dw XT_UP_FETCH
-0038a2 399d .dw XT_PLUS
-0038a3 3879 .dw XT_FETCH
-0038a4 3820 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-0038a5 ff02 .dw $ff02
-0038a6 7521 .db "!u"
-0038a7 389d .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-0038a8 3801 .dw DO_COLON
- PFA_STOREU:
-0038a9 3b02 .dw XT_UP_FETCH
-0038aa 399d .dw XT_PLUS
-0038ab 3881 .dw XT_STORE
-0038ac 3820 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-0038ad ff03 .dw $ff03
-0038ae 7564
-0038af 0070 .db "dup",0
-0038b0 38a5 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-0038b1 38b2 .dw PFA_DUP
- PFA_DUP:
-0038b2 939a
-0038b3 938a savetos
-0038b4 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-0038b5 ff04 .dw $ff04
-0038b6 643f
-0038b7 7075 .db "?dup"
-0038b8 38ad .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-0038b9 38ba .dw PFA_QDUP
- PFA_QDUP:
-0038ba 2f08 mov temp0, tosl
-0038bb 2b09 or temp0, tosh
-0038bc f011 breq PFA_QDUP1
-0038bd 939a
-0038be 938a savetos
- PFA_QDUP1:
-0038bf cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-0038c0 ff04 .dw $ff04
-0038c1 7773
-0038c2 7061 .db "swap"
-0038c3 38b5 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-0038c4 38c5 .dw PFA_SWAP
- PFA_SWAP:
-0038c5 018c movw temp0, tosl
-0038c6 9189
-0038c7 9199 loadtos
-0038c8 931a st -Y, temp1
-0038c9 930a st -Y, temp0
-0038ca cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-0038cb ff04 .dw $ff04
-0038cc 766f
-0038cd 7265 .db "over"
-0038ce 38c0 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-0038cf 38d0 .dw PFA_OVER
- PFA_OVER:
-0038d0 939a
-0038d1 938a savetos
-0038d2 818a ldd tosl, Y+2
-0038d3 819b ldd tosh, Y+3
-
-0038d4 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-0038d5 ff04 .dw $ff04
-0038d6 7264
-0038d7 706f .db "drop"
-0038d8 38cb .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-0038d9 38da .dw PFA_DROP
- PFA_DROP:
-0038da 9189
-0038db 9199 loadtos
-0038dc cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-0038dd ff03 .dw $ff03
-0038de 6f72
-0038df 0074 .db "rot",0
-0038e0 38d5 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-0038e1 38e2 .dw PFA_ROT
- PFA_ROT:
-0038e2 018c movw temp0, tosl
-0038e3 9129 ld temp2, Y+
-0038e4 9139 ld temp3, Y+
-0038e5 9189
-0038e6 9199 loadtos
-
-0038e7 933a st -Y, temp3
-0038e8 932a st -Y, temp2
-0038e9 931a st -Y, temp1
-0038ea 930a st -Y, temp0
-
-0038eb cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-0038ec ff03 .dw $ff03
-0038ed 696e
-0038ee 0070 .db "nip",0
-0038ef 38dd .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-0038f0 38f1 .dw PFA_NIP
- PFA_NIP:
-0038f1 9622 adiw yl, 2
-0038f2 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-0038f3 ff02 .dw $ff02
-0038f4 3e72 .db "r>"
-0038f5 38ec .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-0038f6 38f7 .dw PFA_R_FROM
- PFA_R_FROM:
-0038f7 939a
-0038f8 938a savetos
-0038f9 918f pop tosl
-0038fa 919f pop tosh
-0038fb cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-0038fc ff02 .dw $ff02
-0038fd 723e .db ">r"
-0038fe 38f3 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-0038ff 3900 .dw PFA_TO_R
- PFA_TO_R:
-003900 939f push tosh
-003901 938f push tosl
-003902 9189
-003903 9199 loadtos
-003904 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-003905 ff02 .dw $ff02
-003906 4072 .db "r@"
-003907 38fc .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-003908 3909 .dw PFA_R_FETCH
- PFA_R_FETCH:
-003909 939a
-00390a 938a savetos
-00390b 918f pop tosl
-00390c 919f pop tosh
-00390d 939f push tosh
-00390e 938f push tosl
-00390f cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-003910 ff02 .dw $ff02
-003911 3e3c .db "<>"
-003912 3905 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-003913 3801 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-003914 3fdf
-003915 391a
-003916 3820 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-003917 ff02 .dw $ff02
-003918 3d30 .db "0="
-003919 3910 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-00391a 391b .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00391b 2b98 or tosh, tosl
-00391c f5d1 brne PFA_ZERO1
-00391d c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00391e ff02 .dw $ff02
-00391f 3c30 .db "0<"
-003920 3917 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-003921 3922 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-003922 fd97 sbrc tosh,7
-003923 c02a rjmp PFA_TRUE1
-003924 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-003925 ff02 .dw $ff02
-003926 3e30 .db "0>"
-003927 391e .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-003928 3929 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-003929 1582 cp tosl, zerol
-00392a 0593 cpc tosh, zeroh
-00392b f15c brlt PFA_ZERO1
-00392c f151 brbs 1, PFA_ZERO1
-00392d c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00392e ff03 .dw $ff03
-00392f 3064
-003930 003e .db "d0>",0
-003931 3925 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-003932 3933 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-003933 1582 cp tosl, zerol
-003934 0593 cpc tosh, zeroh
-003935 9189
-003936 9199 loadtos
-003937 0582 cpc tosl, zerol
-003938 0593 cpc tosh, zeroh
-003939 f0ec brlt PFA_ZERO1
-00393a f0e1 brbs 1, PFA_ZERO1
-00393b c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00393c ff03 .dw $ff03
-00393d 3064
-00393e 003c .db "d0<",0
-00393f 392e .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-003940 3941 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-003941 9622 adiw Y,2
-003942 fd97 sbrc tosh,7
-003943 940c 394e jmp PFA_TRUE1
-003945 940c 3957 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-003947 ff04 .dw $ff04
-003948 7274
-003949 6575 .db "true"
-00394a 393c .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00394b 394c .dw PFA_TRUE
- PFA_TRUE:
-00394c 939a
-00394d 938a savetos
- PFA_TRUE1:
-00394e ef8f ser tosl
-00394f ef9f ser tosh
-003950 ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-003951 ff01 .dw $ff01
-003952 0030 .db "0",0
-003953 3947 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-003954 3955 .dw PFA_ZERO
- PFA_ZERO:
-003955 939a
-003956 938a savetos
- PFA_ZERO1:
-003957 01c1 movw tosl, zerol
-003958 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-003959 ff02 .dw $ff02
-00395a 3c75 .db "u<"
-00395b 3951 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00395c 395d .dw PFA_ULESS
- PFA_ULESS:
-00395d 9129 ld temp2, Y+
-00395e 9139 ld temp3, Y+
-00395f 1782 cp tosl, temp2
-003960 0793 cpc tosh, temp3
-003961 f3a8 brlo PFA_ZERO1
-003962 f3a1 brbs 1, PFA_ZERO1
-003963 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-003964 ff02 .dw $ff02
-003965 3e75 .db "u>"
-003966 3959 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-003967 3801 .dw DO_COLON
- PFA_UGREATER:
- .endif
-003968 38c4 .DW XT_SWAP
-003969 395c .dw XT_ULESS
-00396a 3820 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00396b ff01 .dw $ff01
-00396c 003c .db "<",0
-00396d 3964 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00396e 396f .dw PFA_LESS
- PFA_LESS:
-00396f 9129 ld temp2, Y+
-003970 9139 ld temp3, Y+
-003971 1728 cp temp2, tosl
-003972 0739 cpc temp3, tosh
- PFA_LESSDONE:
-003973 f71c brge PFA_ZERO1
-003974 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-003975 ff01 .dw $ff01
-003976 003e .db ">",0
-003977 396b .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-003978 3979 .dw PFA_GREATER
- PFA_GREATER:
-003979 9129 ld temp2, Y+
-00397a 9139 ld temp3, Y+
-00397b 1728 cp temp2, tosl
-00397c 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00397d f2cc brlt PFA_ZERO1
-00397e f2c1 brbs 1, PFA_ZERO1
-00397f cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-003980 ff04 .dw $ff04
-003981 6f6c
-003982 3267 .db "log2"
-003983 3975 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-003984 3985 .dw PFA_LOG2
- PFA_LOG2:
-003985 01fc movw zl, tosl
-003986 2799 clr tosh
-003987 e180 ldi tosl, 16
- PFA_LOG2_1:
-003988 958a dec tosl
-003989 f022 brmi PFA_LOG2_2 ; wrong data
-00398a 0fee lsl zl
-00398b 1fff rol zh
-00398c f7d8 brcc PFA_LOG2_1
-00398d ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00398e 959a dec tosh
-00398f ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-003990 ff01 .dw $ff01
-003991 002d .db "-",0
-003992 3980 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-003993 3994 .dw PFA_MINUS
- PFA_MINUS:
-003994 9109 ld temp0, Y+
-003995 9119 ld temp1, Y+
-003996 1b08 sub temp0, tosl
-003997 0b19 sbc temp1, tosh
-003998 01c8 movw tosl, temp0
-003999 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-00399a ff01 .dw $ff01
-00399b 002b .db "+",0
-00399c 3990 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00399d 399e .dw PFA_PLUS
- PFA_PLUS:
-00399e 9109 ld temp0, Y+
-00399f 9119 ld temp1, Y+
-0039a0 0f80 add tosl, temp0
-0039a1 1f91 adc tosh, temp1
-0039a2 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-0039a3 ff02 .dw $ff02
-0039a4 2a6d .db "m*"
-0039a5 399a .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-0039a6 39a7 .dw PFA_MSTAR
- PFA_MSTAR:
-0039a7 018c movw temp0, tosl
-0039a8 9189
-0039a9 9199 loadtos
-0039aa 019c movw temp2, tosl
- ; high cell ah*bh
-0039ab 0231 muls temp3, temp1
-0039ac 0170 movw temp4, r0
- ; low cell al*bl
-0039ad 9f20 mul temp2, temp0
-0039ae 01c0 movw tosl, r0
- ; signed ah*bl
-0039af 0330 mulsu temp3, temp0
-0039b0 08f3 sbc temp5, zeroh
-0039b1 0d90 add tosh, r0
-0039b2 1ce1 adc temp4, r1
-0039b3 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-0039b4 0312 mulsu temp1, temp2
-0039b5 08f3 sbc temp5, zeroh
-0039b6 0d90 add tosh, r0
-0039b7 1ce1 adc temp4, r1
-0039b8 1cf3 adc temp5, zeroh
-
-0039b9 939a
-0039ba 938a savetos
-0039bb 01c7 movw tosl, temp4
-0039bc ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-0039bd ff06 .dw $ff06
-0039be 6d75
-0039bf 6d2f
-0039c0 646f .db "um/mod"
-0039c1 39a3 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-0039c2 39c3 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-0039c3 017c movw temp4, tosl
-
-0039c4 9129 ld temp2, Y+
-0039c5 9139 ld temp3, Y+
-
-0039c6 9109 ld temp0, Y+
-0039c7 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-0039c8 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-0039c9 2755 clr temp7
-0039ca 0f00 lsl temp0
-0039cb 1f11 rol temp1
-0039cc 1f22 rol temp2
-0039cd 1f33 rol temp3
-0039ce 1f55 rol temp7
-
- ; try subtracting divisor
-0039cf 152e cp temp2, temp4
-0039d0 053f cpc temp3, temp5
-0039d1 0552 cpc temp7,zerol
-
-0039d2 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-0039d3 9503 inc temp0
-0039d4 192e sub temp2, temp4
-0039d5 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-0039d6 954a dec temp6
-0039d7 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-0039d8 933a st -Y,temp3
-0039d9 932a st -Y,temp2
-
- ; put quotient on stack
-0039da 01c8 movw tosl, temp0
-0039db ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-0039dc ff03 .dw $ff03
-0039dd 6d75
-0039de 002a .db "um*",0
-0039df 39bd .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-0039e0 39e1 .dw PFA_UMSTAR
- PFA_UMSTAR:
-0039e1 018c movw temp0, tosl
-0039e2 9189
-0039e3 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-0039e4 9f80 mul tosl,temp0
-0039e5 01f0 movw zl, r0
-0039e6 2722 clr temp2
-0039e7 2733 clr temp3
- ; middle bytes
-0039e8 9f90 mul tosh, temp0
-0039e9 0df0 add zh, r0
-0039ea 1d21 adc temp2, r1
-0039eb 1d33 adc temp3, zeroh
-
-0039ec 9f81 mul tosl, temp1
-0039ed 0df0 add zh, r0
-0039ee 1d21 adc temp2, r1
-0039ef 1d33 adc temp3, zeroh
-
-0039f0 9f91 mul tosh, temp1
-0039f1 0d20 add temp2, r0
-0039f2 1d31 adc temp3, r1
-0039f3 01cf movw tosl, zl
-0039f4 939a
-0039f5 938a savetos
-0039f6 01c9 movw tosl, temp2
-0039f7 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-0039f8 ff06 .dw $ff06
-0039f9 6e69
-0039fa 6576
-0039fb 7472 .db "invert"
-0039fc 39dc .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-0039fd 39fe .dw PFA_INVERT
- PFA_INVERT:
-0039fe 9580 com tosl
-0039ff 9590 com tosh
-003a00 ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-003a01 ff02 .dw $ff02
-003a02 2f32 .db "2/"
-003a03 39f8 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-003a04 3a05 .dw PFA_2SLASH
- PFA_2SLASH:
-003a05 9595 asr tosh
-003a06 9587 ror tosl
-003a07 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-003a08 ff02 .dw $ff02
-003a09 2a32 .db "2*"
-003a0a 3a01 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-003a0b 3a0c .dw PFA_2STAR
- PFA_2STAR:
-003a0c 0f88 lsl tosl
-003a0d 1f99 rol tosh
-003a0e cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-003a0f ff03 .dw $ff03
-003a10 6e61
-003a11 0064 .db "and",0
-003a12 3a08 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-003a13 3a14 .dw PFA_AND
- PFA_AND:
-003a14 9109 ld temp0, Y+
-003a15 9119 ld temp1, Y+
-003a16 2380 and tosl, temp0
-003a17 2391 and tosh, temp1
-003a18 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-003a19 ff02 .dw $ff02
-003a1a 726f .db "or"
-003a1b 3a0f .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-003a1c 3a1d .dw PFA_OR
- PFA_OR:
-003a1d 9109 ld temp0, Y+
-003a1e 9119 ld temp1, Y+
-003a1f 2b80 or tosl, temp0
-003a20 2b91 or tosh, temp1
-003a21 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-003a22 ff03 .dw $ff03
-003a23 6f78
-003a24 0072 .db "xor",0
-003a25 3a19 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-003a26 3a27 .dw PFA_XOR
- PFA_XOR:
-003a27 9109 ld temp0, Y+
-003a28 9119 ld temp1, Y+
-003a29 2780 eor tosl, temp0
-003a2a 2791 eor tosh, temp1
-003a2b cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-003a2c ff02 .dw $ff02
-003a2d 2b31 .db "1+"
-003a2e 3a22 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-003a2f 3a30 .dw PFA_1PLUS
- PFA_1PLUS:
-003a30 9601 adiw tosl,1
-003a31 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-003a32 ff02 .dw $ff02
-003a33 2d31 .db "1-"
-003a34 3a2c .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-003a35 3a36 .dw PFA_1MINUS
- PFA_1MINUS:
-003a36 9701 sbiw tosl, 1
-003a37 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-003a38 ff07 .dw $ff07
-003a39 6e3f
-003a3a 6765
-003a3b 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-003a3c 0065 .db "?negate"
-003a3d 3a32 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-003a3e 3801 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-003a3f 3921
-003a40 3836 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-003a41 3a43 DEST(QNEG1)
-003a42 3e27 .DW XT_NEGATE
-003a43 3820 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-003a44 ff06 .dw $ff06
-003a45 736c
-003a46 6968
-003a47 7466 .db "lshift"
-003a48 3a38 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-003a49 3a4a .dw PFA_LSHIFT
- PFA_LSHIFT:
-003a4a 01fc movw zl, tosl
-003a4b 9189
-003a4c 9199 loadtos
- PFA_LSHIFT1:
-003a4d 9731 sbiw zl, 1
-003a4e f01a brmi PFA_LSHIFT2
-003a4f 0f88 lsl tosl
-003a50 1f99 rol tosh
-003a51 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-003a52 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-003a53 ff06 .dw $ff06
-003a54 7372
-003a55 6968
-003a56 7466 .db "rshift"
-003a57 3a44 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-003a58 3a59 .dw PFA_RSHIFT
- PFA_RSHIFT:
-003a59 01fc movw zl, tosl
-003a5a 9189
-003a5b 9199 loadtos
- PFA_RSHIFT1:
-003a5c 9731 sbiw zl, 1
-003a5d f01a brmi PFA_RSHIFT2
-003a5e 9596 lsr tosh
-003a5f 9587 ror tosl
-003a60 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-003a61 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-003a62 ff02 .dw $ff02
-003a63 212b .db "+!"
-003a64 3a53 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-003a65 3a66 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-003a66 01fc movw zl, tosl
-003a67 9189
-003a68 9199 loadtos
-003a69 8120 ldd temp2, Z+0
-003a6a 8131 ldd temp3, Z+1
-003a6b 0f82 add tosl, temp2
-003a6c 1f93 adc tosh, temp3
-003a6d 8380 std Z+0, tosl
-003a6e 8391 std Z+1, tosh
-003a6f 9189
-003a70 9199 loadtos
-003a71 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-003a72 ff03 .dw $ff03
-003a73 7072
-003a74 0040 .db "rp@",0
-003a75 3a62 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-003a76 3a77 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-003a77 939a
-003a78 938a savetos
-003a79 b78d in tosl, SPL
-003a7a b79e in tosh, SPH
-003a7b cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-003a7c ff03 .dw $ff03
-003a7d 7072
-003a7e 0021 .db "rp!",0
-003a7f 3a72 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-003a80 3a81 .dw PFA_RP_STORE
- PFA_RP_STORE:
-003a81 b72f in temp2, SREG
-003a82 94f8 cli
-003a83 bf8d out SPL, tosl
-003a84 bf9e out SPH, tosh
-003a85 bf2f out SREG, temp2
-003a86 9189
-003a87 9199 loadtos
-003a88 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-003a89 ff03 .dw $ff03
-003a8a 7073
-003a8b 0040 .db "sp@",0
-003a8c 3a7c .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-003a8d 3a8e .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-003a8e 939a
-003a8f 938a savetos
-003a90 01ce movw tosl, yl
-003a91 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-003a92 ff03 .dw $ff03
-003a93 7073
-003a94 0021 .db "sp!",0
-003a95 3a89 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-003a96 3a97 .dw PFA_SP_STORE
- PFA_SP_STORE:
-003a97 01ec movw yl, tosl
-003a98 9189
-003a99 9199 loadtos
-003a9a cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-003a9b 3a9c .dw PFA_DODO
- PFA_DODO:
-003a9c 9129 ld temp2, Y+
-003a9d 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-003a9e e8e0 ldi zl, $80
-003a9f 0f3e add temp3, zl
-003aa0 1b82 sub tosl, temp2
-003aa1 0b93 sbc tosh, temp3
-
-003aa2 933f push temp3
-003aa3 932f push temp2 ; limit ( --> limit + $8000)
-003aa4 939f push tosh
-003aa5 938f push tosl ; start -> index ( --> index - (limit - $8000)
-003aa6 9189
-003aa7 9199 loadtos
-003aa8 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-003aa9 ff01 .dw $FF01
-003aaa 0069 .db "i",0
-003aab 3a92 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-003aac 3aad .dw PFA_I
- PFA_I:
-003aad 939a
-003aae 938a savetos
-003aaf 918f pop tosl
-003ab0 919f pop tosh ; index
-003ab1 91ef pop zl
-003ab2 91ff pop zh ; limit
-003ab3 93ff push zh
-003ab4 93ef push zl
-003ab5 939f push tosh
-003ab6 938f push tosl
-003ab7 0f8e add tosl, zl
-003ab8 1f9f adc tosh, zh
-003ab9 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-003aba 3abb .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-003abb 91ef pop zl
-003abc 91ff pop zh
-003abd 0fe8 add zl, tosl
-003abe 1ff9 adc zh, tosh
-003abf 9189
-003ac0 9199 loadtos
-003ac1 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-003ac2 93ff push zh
-003ac3 93ef push zl
-003ac4 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-003ac5 910f pop temp0
-003ac6 911f pop temp1 ; remove limit
-003ac7 9611 adiw xl, 1 ; skip branch-back address
-003ac8 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-003ac9 3aca .dw PFA_DOLOOP
- PFA_DOLOOP:
-003aca 91ef pop zl
-003acb 91ff pop zh
-003acc 9631 adiw zl,1
-003acd f3bb brvs PFA_DOPLUSLOOP_LEAVE
-003ace cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-003acf ff06 .dw $ff06
-003ad0 6e75
-003ad1 6f6c
-003ad2 706f .db "unloop"
-003ad3 3aa9 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-003ad4 3ad5 .dw PFA_UNLOOP
- PFA_UNLOOP:
-003ad5 911f pop temp1
-003ad6 910f pop temp0
-003ad7 911f pop temp1
-003ad8 910f pop temp0
-003ad9 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-003ada ff06 .dw $ff06
-003adb 6d63
-003adc 766f
-003add 3e65 .db "cmove>"
-003ade 3acf .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-003adf 3ae0 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-003ae0 93bf push xh
-003ae1 93af push xl
-003ae2 91e9 ld zl, Y+
-003ae3 91f9 ld zh, Y+ ; addr-to
-003ae4 91a9 ld xl, Y+
-003ae5 91b9 ld xh, Y+ ; addr-from
-003ae6 2f09 mov temp0, tosh
-003ae7 2b08 or temp0, tosl
-003ae8 f041 brbs 1, PFA_CMOVE_G1
-003ae9 0fe8 add zl, tosl
-003aea 1ff9 adc zh, tosh
-003aeb 0fa8 add xl, tosl
-003aec 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-003aed 911e ld temp1, -X
-003aee 9312 st -Z, temp1
-003aef 9701 sbiw tosl, 1
-003af0 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-003af1 91af pop xl
-003af2 91bf pop xh
-003af3 9189
-003af4 9199 loadtos
-003af5 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-003af6 ff02 .dw $ff02
-003af7 3c3e .db "><"
-003af8 3ada .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-003af9 3afa .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-003afa 2f09 mov temp0, tosh
-003afb 2f98 mov tosh, tosl
-003afc 2f80 mov tosl, temp0
-003afd cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-003afe ff03 .dw $ff03
-003aff 7075
-003b00 0040 .db "up@",0
-003b01 3af6 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-003b02 3b03 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-003b03 939a
-003b04 938a savetos
-003b05 01c2 movw tosl, upl
-003b06 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-003b07 ff03 .dw $ff03
-003b08 7075
-003b09 0021 .db "up!",0
-003b0a 3afe .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-003b0b 3b0c .dw PFA_UP_STORE
- PFA_UP_STORE:
-003b0c 012c movw upl, tosl
-003b0d 9189
-003b0e 9199 loadtos
-003b0f ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-003b10 ff03 .dw $ff03
-003b11 6d31
-003b12 0073 .db "1ms",0
-003b13 3b07 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-003b14 3b15 .dw PFA_1MS
- PFA_1MS:
-003b15 eae0
-003b16 e0ff
-003b17 9731
-003b18 f7f1 delay 1000
-003b19 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-003b1a ff03 .dw $ff03
-003b1b 3e32
-003b1c 0072 .db "2>r",0
-003b1d 3b10 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-003b1e 3b1f .dw PFA_2TO_R
- PFA_2TO_R:
-003b1f 01fc movw zl, tosl
-003b20 9189
-003b21 9199 loadtos
-003b22 939f push tosh
-003b23 938f push tosl
-003b24 93ff push zh
-003b25 93ef push zl
-003b26 9189
-003b27 9199 loadtos
-003b28 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-003b29 ff03 .dw $ff03
-003b2a 7232
-003b2b 003e .db "2r>",0
-003b2c 3b1a .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-003b2d 3b2e .dw PFA_2R_FROM
- PFA_2R_FROM:
-003b2e 939a
-003b2f 938a savetos
-003b30 91ef pop zl
-003b31 91ff pop zh
-003b32 918f pop tosl
-003b33 919f pop tosh
-003b34 939a
-003b35 938a savetos
-003b36 01cf movw tosl, zl
-003b37 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-003b38 ff02 .dw $ff02
-003b39 6521 .db "!e"
-003b3a 3b29 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-003b3b 3b3c .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-003b3c 01fc movw zl, tosl
-003b3d 9189
-003b3e 9199 loadtos
-003b3f b72f in_ temp2, SREG
-003b40 94f8 cli
-003b41 d028 rcall PFA_FETCHE2
-003b42 b500 in_ temp0, EEDR
-003b43 1708 cp temp0,tosl
-003b44 f009 breq PFA_STOREE3
-003b45 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-003b46 9631 adiw zl,1
-003b47 d022 rcall PFA_FETCHE2
-003b48 b500 in_ temp0, EEDR
-003b49 1709 cp temp0,tosh
-003b4a f011 breq PFA_STOREE4
-003b4b 2f89 mov tosl, tosh
-003b4c d004 rcall PFA_STOREE1
- PFA_STOREE4:
-003b4d bf2f out_ SREG, temp2
-003b4e 9189
-003b4f 9199 loadtos
-003b50 ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-003b51 99f9 sbic EECR, EEPE
-003b52 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-003b53 b707 in_ temp0, SPMCSR
-003b54 fd00 sbrc temp0,SPMEN
-003b55 cffd rjmp PFA_STOREE2
-
-003b56 bdf2 out_ EEARH,zh
-003b57 bde1 out_ EEARL,zl
-003b58 bd80 out_ EEDR, tosl
-003b59 9afa sbi EECR,EEMPE
-003b5a 9af9 sbi EECR,EEPE
-
-003b5b 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-003b5c ff02 .dw $ff02
-003b5d 6540 .db "@e"
-003b5e 3b38 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-003b5f 3b60 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-003b60 b72f in_ temp2, SREG
-003b61 94f8 cli
-003b62 01fc movw zl, tosl
-003b63 d006 rcall PFA_FETCHE2
-003b64 b580 in_ tosl, EEDR
-
-003b65 9631 adiw zl,1
-
-003b66 d003 rcall PFA_FETCHE2
-003b67 b590 in_ tosh, EEDR
-003b68 bf2f out_ SREG, temp2
-003b69 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-003b6a 99f9 sbic EECR, EEPE
-003b6b cffe rjmp PFA_FETCHE2
-
-003b6c bdf2 out_ EEARH,zh
-003b6d bde1 out_ EEARL,zl
-
-003b6e 9af8 sbi EECR,EERE
-003b6f 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-003b70 ff02 .dw $ff02
-003b71 6921 .db "!i"
-003b72 3b5c .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-003b73 3dff .dw PFA_DODEFER1
- PFA_STOREI:
-003b74 0066 .dw EE_STOREI
-003b75 3da0 .dw XT_EDEFERFETCH
-003b76 3daa .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-003b77 ff09 .dw $ff09
-003b78 2128
-003b79 2d69
-003b7a 726e
-003b7b 7777
-003b7c 0029 .db "(!i-nrww)",0
-003b7d 3b70 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-003b7e 3b7f .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-003b7f b71f in temp1,SREG
-003b80 931f push temp1
-003b81 94f8 cli
-
-003b82 019c movw temp2, tosl ; save the (word) address
-003b83 9189
-003b84 9199 loadtos ; get the new value for the flash cell
-003b85 93af push xl
-003b86 93bf push xh
-003b87 93cf push yl
-003b88 93df push yh
-003b89 d009 rcall DO_STOREI_atmega
-003b8a 91df pop yh
-003b8b 91cf pop yl
-003b8c 91bf pop xh
-003b8d 91af pop xl
- ; finally clear the stack
-003b8e 9189
-003b8f 9199 loadtos
-003b90 911f pop temp1
- ; restore status register (and interrupt enable flag)
-003b91 bf1f out SREG,temp1
-
-003b92 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-003b93 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-003b94 94e0 com temp4
-003b95 94f0 com temp5
-003b96 218e and tosl, temp4
-003b97 219f and tosh, temp5
-003b98 2b98 or tosh, tosl
-003b99 f019 breq DO_STOREI_writepage
-003b9a 01f9 movw zl, temp2
-003b9b e002 ldi temp0,(1<<PGERS)
-003b9c d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-003b9d 01f9 movw zl, temp2
-003b9e e004 ldi temp0,(1<<PGWRT)
-003b9f d01d rcall dospm
-
- ; reenable RWW section
-003ba0 01f9 movw zl, temp2
-003ba1 e100 ldi temp0,(1<<RWWSRE)
-003ba2 d01a rcall dospm
-003ba3 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-003ba4 01f9 movw zl, temp2
- ; get the beginning of page
-003ba5 7ce0 andi zl,low(pagemask)
-003ba6 7fff andi zh,high(pagemask)
-003ba7 01ef movw y, z
- ; loop counter (in words)
-003ba8 e4a0 ldi xl,low(pagesize)
-003ba9 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-003baa 01fe movw z, y
-003bab 0fee
-003bac 1fff
-003bad 9145
-003bae 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-003baf 01fe movw z, y
-003bb0 17e2 cp zl, temp2
-003bb1 07f3 cpc zh, temp3
-003bb2 f011 breq pageload_newdata
-003bb3 010a movw r0, temp6
-003bb4 c002 rjmp pageload_cont
- pageload_newdata:
-003bb5 017a movw temp4, temp6
-003bb6 010c movw r0, tosl
- pageload_cont:
-003bb7 2700 clr temp0
-003bb8 d004 rcall dospm
-003bb9 9621 adiw y, 1
-003bba 9711 sbiw x, 1
-003bbb f771 brne pageload_loop
-
- pageload_done:
-003bbc 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-003bbd 99f9 sbic EECR, EEPE
-003bbe cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-003bbf b717 in_ temp1, SPMCSR
-003bc0 fd10 sbrc temp1, SPMEN
-003bc1 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-003bc2 0fee
-003bc3 1fff writeflashcell
- ; execute spm
-003bc4 6001 ori temp0, (1<<SPMEN)
-003bc5 bf07 out_ SPMCSR,temp0
-003bc6 95e8 spm
-003bc7 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-003bc8 ff02 .dw $ff02
-003bc9 6940 .db "@i"
-003bca 3b77 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-003bcb 3bcc .dw PFA_FETCHI
- PFA_FETCHI:
-003bcc 01fc movw zl, tosl
-003bcd 0fee
-003bce 1fff
-003bcf 9185
-003bd0 9195 readflashcell tosl,tosh
-003bd1 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .elif AMFORTH_NRWW_SIZE>4000
- .include "dict/core_4k.inc"
-
- ; in a short distance to DO_NEXT
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-003bd2 ff03 .dw $ff03
-003bd3 3e6e
-003bd4 0072 .db "n>r",0
-003bd5 3bc8 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-003bd6 3bd7 .dw PFA_N_TO_R
- PFA_N_TO_R:
-003bd7 01fc movw zl, tosl
-003bd8 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-003bd9 9189
-003bda 9199 loadtos
-003bdb 939f push tosh
-003bdc 938f push tosl
-003bdd 950a dec temp0
-003bde f7d1 brne PFA_N_TO_R1
-003bdf 93ef push zl
-003be0 93ff push zh
-003be1 9189
-003be2 9199 loadtos
-003be3 cc21 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-003be4 ff03 .dw $ff03
-003be5 726e
-003be6 003e .db "nr>",0
-003be7 3bd2 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-003be8 3be9 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-003be9 939a
-003bea 938a savetos
-003beb 91ff pop zh
-003bec 91ef pop zl
-003bed 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-003bee 918f pop tosl
-003bef 919f pop tosh
-003bf0 939a
-003bf1 938a savetos
-003bf2 950a dec temp0
-003bf3 f7d1 brne PFA_N_R_FROM1
-003bf4 01cf movw tosl, zl
-003bf5 cc0f jmp_ DO_NEXT
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-003bf6 ff03 .dw $ff03
-003bf7 3264
-003bf8 002a .db "d2*",0
-003bf9 3be4 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-003bfa 3bfb .dw PFA_D2STAR
- PFA_D2STAR:
-003bfb 9109 ld temp0, Y+
-003bfc 9119 ld temp1, Y+
-003bfd 0f00 lsl temp0
-003bfe 1f11 rol temp1
-003bff 1f88 rol tosl
-003c00 1f99 rol tosh
-003c01 931a st -Y, temp1
-003c02 930a st -Y, temp0
-003c03 cc01 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-003c04 ff03 .dw $ff03
-003c05 3264
-003c06 002f .db "d2/",0
-003c07 3bf6 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-003c08 3c09 .dw PFA_D2SLASH
- PFA_D2SLASH:
-003c09 9109 ld temp0, Y+
-003c0a 9119 ld temp1, Y+
-003c0b 9595 asr tosh
-003c0c 9587 ror tosl
-003c0d 9517 ror temp1
-003c0e 9507 ror temp0
-003c0f 931a st -Y, temp1
-003c10 930a st -Y, temp0
-003c11 cbf3 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-003c12 ff02 .dw $ff02
-003c13 2b64 .db "d+"
-003c14 3c04 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-003c15 3c16 .dw PFA_DPLUS
- PFA_DPLUS:
-003c16 9129 ld temp2, Y+
-003c17 9139 ld temp3, Y+
-
-003c18 90e9 ld temp4, Y+
-003c19 90f9 ld temp5, Y+
-003c1a 9149 ld temp6, Y+
-003c1b 9159 ld temp7, Y+
-
-003c1c 0f24 add temp2, temp6
-003c1d 1f35 adc temp3, temp7
-003c1e 1d8e adc tosl, temp4
-003c1f 1d9f adc tosh, temp5
-
-003c20 933a st -Y, temp3
-003c21 932a st -Y, temp2
-003c22 cbe2 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-003c23 ff02 .dw $ff02
-003c24 2d64 .db "d-"
-003c25 3c12 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-003c26 3c27 .dw PFA_DMINUS
- PFA_DMINUS:
-003c27 9129 ld temp2, Y+
-003c28 9139 ld temp3, Y+
-
-003c29 90e9 ld temp4, Y+
-003c2a 90f9 ld temp5, Y+
-003c2b 9149 ld temp6, Y+
-003c2c 9159 ld temp7, Y+
-
-003c2d 1b42 sub temp6, temp2
-003c2e 0b53 sbc temp7, temp3
-003c2f 0ae8 sbc temp4, tosl
-003c30 0af9 sbc temp5, tosh
-
-003c31 935a st -Y, temp7
-003c32 934a st -Y, temp6
-003c33 01c7 movw tosl, temp4
-003c34 cbd0 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-003c35 ff07 .dw $ff07
-003c36 6964
-003c37 766e
-003c38 7265
-003c39 0074 .db "dinvert",0
-003c3a 3c23 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-003c3b 3c3c .dw PFA_DINVERT
- PFA_DINVERT:
-003c3c 9109 ld temp0, Y+
-003c3d 9119 ld temp1, Y+
-003c3e 9580 com tosl
-003c3f 9590 com tosh
-003c40 9500 com temp0
-003c41 9510 com temp1
-003c42 931a st -Y, temp1
-003c43 930a st -Y, temp0
-003c44 cbc0 jmp_ DO_NEXT
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-003c45 ff04 .dw $ff04
-003c46 6d2f
-003c47 646f .db "/mod"
-003c48 3c35 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-003c49 3c4a .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-003c4a 019c movw temp2, tosl
-
-003c4b 9109 ld temp0, Y+
-003c4c 9119 ld temp1, Y+
-
-003c4d 2f41 mov temp6,temp1 ;move dividend High to sign register
-003c4e 2743 eor temp6,temp3 ;xor divisor High with sign register
-003c4f ff17 sbrs temp1,7 ;if MSB in dividend set
-003c50 c004 rjmp PFA_SLASHMOD_1
-003c51 9510 com temp1 ; change sign of dividend
-003c52 9500 com temp0
-003c53 5f0f subi temp0,low(-1)
-003c54 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-003c55 ff37 sbrs temp3,7 ;if MSB in divisor set
-003c56 c004 rjmp PFA_SLASHMOD_2
-003c57 9530 com temp3 ; change sign of divisor
-003c58 9520 com temp2
-003c59 5f2f subi temp2,low(-1)
-003c5a 4f3f sbci temp3,high(-1)
-003c5b 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-003c5c 18ff sub temp5,temp5;clear remainder High byte and carry
-003c5d e151 ldi temp7,17 ;init loop counter
-
-003c5e 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-003c5f 1f11 rol temp1
-003c60 955a dec temp7 ;decrement counter
-003c61 f439 brne PFA_SLASHMOD_5 ;if done
-003c62 ff47 sbrs temp6,7 ; if MSB in sign register set
-003c63 c004 rjmp PFA_SLASHMOD_4
-003c64 9510 com temp1 ; change sign of result
-003c65 9500 com temp0
-003c66 5f0f subi temp0,low(-1)
-003c67 4f1f sbci temp1,high(-1)
-003c68 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-003c69 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-003c6a 1cff rol temp5
-003c6b 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-003c6c 0af3 sbc temp5,temp3 ;
-003c6d f420 brcc PFA_SLASHMOD_6 ;if result negative
-003c6e 0ee2 add temp4,temp2 ; restore remainder
-003c6f 1ef3 adc temp5,temp3
-003c70 9488 clc ; clear carry to be shifted into result
-003c71 cfec rjmp PFA_SLASHMOD_3 ;else
-003c72 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-003c73 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-003c74 92fa st -Y,temp5
-003c75 92ea st -Y,temp4
-
- ; put quotient on stack
-003c76 01c8 movw tosl, temp0
-003c77 cb8d jmp_ DO_NEXT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-003c78 ff03 .dw $ff03
-003c79 6261
-003c7a 0073 .db "abs",0
-003c7b 3c45 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-003c7c 3801 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-003c7d 38b1
-003c7e 3a3e
-003c7f 3820 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-003c80 ff04 .dw $ff04
-003c81 6970
-003c82 6b63 .db "pick"
-003c83 3c78 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-003c84 3801 .dw DO_COLON
- PFA_PICK:
- .endif
-003c85 3a2f .dw XT_1PLUS
-003c86 3ec4 .dw XT_CELLS
-003c87 3a8d .dw XT_SP_FETCH
-003c88 399d .dw XT_PLUS
-003c89 3879 .dw XT_FETCH
-003c8a 3820 .dw XT_EXIT
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-003c8b ff05 .dw $ff05
-003c8c 6563
-003c8d 6c6c
-003c8e 002b .db "cell+",0
-003c8f 3c80 .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-003c90 3c91 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-003c91 9602 adiw tosl, CELLSIZE
-003c92 cb72 jmp_ DO_NEXT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-003c93 ff04 .dw $ff04
-003c94 692b
-003c95 746e .db "+int"
-003c96 3c8b .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-003c97 3c98 .dw PFA_INTON
- PFA_INTON:
-003c98 9478 sei
-003c99 cb6b jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-003c9a ff04 .dw $ff04
-003c9b 692d
-003c9c 746e .db "-int"
-003c9d 3c93 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-003c9e 3c9f .dw PFA_INTOFF
- PFA_INTOFF:
-003c9f 94f8 cli
-003ca0 cb64 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-003ca1 ff04 .dw $ff04
-003ca2 6e69
-003ca3 2174 .db "int!"
-003ca4 3c9a .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-003ca5 3801 .dw DO_COLON
- PFA_INTSTORE:
-003ca6 383d .dw XT_DOLITERAL
-003ca7 0000 .dw intvec
-003ca8 399d .dw XT_PLUS
-003ca9 3b3b .dw XT_STOREE
-003caa 3820 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-003cab ff04 .dw $ff04
-003cac 6e69
-003cad 4074 .db "int@"
-003cae 3ca1 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-003caf 3801 .dw DO_COLON
- PFA_INTFETCH:
-003cb0 383d .dw XT_DOLITERAL
-003cb1 0000 .dw intvec
-003cb2 399d .dw XT_PLUS
-003cb3 3b5f .dw XT_FETCHE
-003cb4 3820 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-003cb5 ff08 .dw $ff08
-003cb6 6e69
-003cb7 2d74
-003cb8 7274
-003cb9 7061 .db "int-trap"
-003cba 3cab .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-003cbb 3cbc .dw PFA_INTTRAP
- PFA_INTTRAP:
-003cbc 2eb8 mov isrflag, tosl
-003cbd 9189
-003cbe 9199 loadtos
-003cbf cb45 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-003cc0 3801 .dw DO_COLON
- PFA_ISREXEC:
-003cc1 3caf .dw XT_INTFETCH
-003cc2 382a .dw XT_EXECUTE
-003cc3 3cc5 .dw XT_ISREND
-003cc4 3820 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-003cc5 3cc6 .dw PFA_ISREND
- PFA_ISREND:
-003cc6 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-003cc7 cb3d jmp_ DO_NEXT
- PFA_ISREND1:
-003cc8 9518 reti
- .endif
-
- ; now the relocatable colon words
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-003cc9 3801 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-003cca 03d0 .dw XT_DOSLITERAL
-003ccb 0003 .dw 3
-003ccc 6f20
-003ccd 006b .db " ok",0
- .endif
-003cce 0403 .dw XT_ITYPE
-003ccf 3820 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-003cd0 ff03 .dw $FF03
-003cd1 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-003cd2 006b .db ".ok"
-003cd3 3cb5 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-003cd4 3dff .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-003cd5 001c .dw USER_P_OK
-003cd6 3dc8 .dw XT_UDEFERFETCH
-003cd7 3dd4 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-003cd8 3801 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-003cd9 03d0 .dw XT_DOSLITERAL
-003cda 0002 .dw 2
-003cdb 203e .db "> "
- .endif
-003cdc 3fa1 .dw XT_CR
-003cdd 0403 .dw XT_ITYPE
-003cde 3820 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-003cdf ff06 .dw $FF06
-003ce0 722e
-003ce1 6165
-003ce2 7964 .db ".ready"
-003ce3 3cd0 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-003ce4 3dff .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-003ce5 0020 .dw USER_P_RDY
-003ce6 3dc8 .dw XT_UDEFERFETCH
-003ce7 3dd4 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-003ce8 3801 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-003ce9 03d0 .dw XT_DOSLITERAL
-003cea 0004 .dw 4
-003ceb 3f20
-003cec 203f .db " ?? "
- .endif
-003ced 0403 .dw XT_ITYPE
-003cee 3ebd .dw XT_BASE
-003cef 3879 .dw XT_FETCH
-003cf0 38ff .dw XT_TO_R
-003cf1 3f41 .dw XT_DECIMAL
-003cf2 0385 .dw XT_DOT
-003cf3 3ee2 .dw XT_TO_IN
-003cf4 3879 .dw XT_FETCH
-003cf5 0385 .dw XT_DOT
-003cf6 38f6 .dw XT_R_FROM
-003cf7 3ebd .dw XT_BASE
-003cf8 3881 .dw XT_STORE
-003cf9 3820 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-003cfa ff06 .dw $FF06
-003cfb 652e
-003cfc 7272
-003cfd 726f .db ".error"
-003cfe 3cdf .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-003cff 3dff .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-003d00 001e .dw USER_P_ERR
-003d01 3dc8 .dw XT_UDEFERFETCH
-003d02 3dd4 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-003d03 ff04 .dw $ff04
-003d04 7571
-003d05 7469 .db "quit"
-003d06 3cfa .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-003d07 3801 .dw DO_COLON
- .endif
- PFA_QUIT:
-003d08 085c
-003d09 0863
-003d0a 3881 .dw XT_LP0,XT_LP,XT_STORE
-003d0b 05d5 .dw XT_SP0
-003d0c 3a96 .dw XT_SP_STORE
-003d0d 05e2 .dw XT_RP0
-003d0e 3a80 .dw XT_RP_STORE
-003d0f 08f1 .dw XT_LBRACKET
-
- PFA_QUIT2:
-003d10 3eb7 .dw XT_STATE
-003d11 3879 .dw XT_FETCH
-003d12 391a .dw XT_ZEROEQUAL
-003d13 3836 .dw XT_DOCONDBRANCH
-003d14 3d16 DEST(PFA_QUIT4)
-003d15 3ce4 .dw XT_PROMPTREADY
- PFA_QUIT4:
-003d16 04e9 .dw XT_REFILL
-003d17 3836 .dw XT_DOCONDBRANCH
-003d18 3d28 DEST(PFA_QUIT3)
-003d19 383d .dw XT_DOLITERAL
-003d1a 0630 .dw XT_INTERPRET
-003d1b 3d70 .dw XT_CATCH
-003d1c 38b9 .dw XT_QDUP
-003d1d 3836 .dw XT_DOCONDBRANCH
-003d1e 3d28 DEST(PFA_QUIT3)
-003d1f 38b1 .dw XT_DUP
-003d20 383d .dw XT_DOLITERAL
-003d21 fffe .dw -2
-003d22 396e .dw XT_LESS
-003d23 3836 .dw XT_DOCONDBRANCH
-003d24 3d26 DEST(PFA_QUIT5)
-003d25 3cff .dw XT_PROMPTERROR
- PFA_QUIT5:
-003d26 382f .dw XT_DOBRANCH
-003d27 3d08 DEST(PFA_QUIT)
- PFA_QUIT3:
-003d28 3cd4 .dw XT_PROMPTOK
-003d29 382f .dw XT_DOBRANCH
-003d2a 3d10 DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-003d2b ff05 .dw $ff05
-003d2c 6170
-003d2d 7375
-003d2e 0065 .db "pause",0
-003d2f 3d03 .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-003d30 3dff .dw PFA_DODEFER1
- PFA_PAUSE:
-003d31 0192 .dw ram_pause
-003d32 3db4 .dw XT_RDEFERFETCH
-003d33 3dbe .dw XT_RDEFERSTORE
-
- .dseg
-000192 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-003d34 ff04 .dw $ff04
-003d35 6f63
-003d36 646c .db "cold"
-003d37 3d2b .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-003d38 3d39 .dw PFA_COLD
- PFA_COLD:
-003d39 b6a4 in_ mcu_boot, MCUSR
-003d3a 2422 clr zerol
-003d3b 2433 clr zeroh
-003d3c 24bb clr isrflag
-003d3d be24 out_ MCUSR, zerol
- ; clear RAM
-003d3e e0e0 ldi zl, low(ramstart)
-003d3f e0f1 ldi zh, high(ramstart)
- clearloop:
-003d40 9221 st Z+, zerol
-003d41 30e0 cpi zl, low(sram_size+ramstart)
-003d42 f7e9 brne clearloop
-003d43 30f9 cpi zh, high(sram_size+ramstart)
-003d44 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000194 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-003d45 e9e4 ldi zl, low(ram_user1)
-003d46 e0f1 ldi zh, high(ram_user1)
-003d47 012f movw upl, zl
- ; init return stack pointer
-003d48 ef0f ldi temp0,low(rstackstart)
-003d49 bf0d out_ SPL,temp0
-003d4a 8304 std Z+4, temp0
-003d4b e018 ldi temp1,high(rstackstart)
-003d4c bf1e out_ SPH,temp1
-003d4d 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-003d4e eacf ldi yl,low(stackstart)
-003d4f 83c6 std Z+6, yl
-003d50 e0d8 ldi yh,high(stackstart)
-003d51 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-003d52 e5aa ldi XL, low(PFA_WARM)
-003d53 e3bd ldi XH, high(PFA_WARM)
- ; its a far jump...
-003d54 cab0 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-003d55 ff04 .dw $ff04
-003d56 6177
-003d57 6d72 .db "warm"
-003d58 3d34 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-003d59 3801 .dw DO_COLON
- PFA_WARM:
- .endif
-003d5a 02a2 .dw XT_INIT_RAM
-003d5b 383d .dw XT_DOLITERAL
-003d5c 01a5 .dw XT_NOOP
-003d5d 383d .dw XT_DOLITERAL
-003d5e 3d30 .dw XT_PAUSE
-003d5f 3ddf .dw XT_DEFERSTORE
-003d60 08f1 .dw XT_LBRACKET
-003d61 3f5c .dw XT_TURNKEY
-003d62 3d07 .dw XT_QUIT ; never returns
-
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-003d63 ff07 .dw $ff07
-003d64 6168
-003d65 646e
-003d66 656c
-003d67 0072 .db "handler",0
-003d68 3d55 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-003d69 3858 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-003d6a 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-003d6b ff05 .dw $ff05
-003d6c 6163
-003d6d 6374
-003d6e 0068 .db "catch",0
-003d6f 3d63 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-003d70 3801 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-003d71 3a8d .dw XT_SP_FETCH
-003d72 38ff .dw XT_TO_R
- ; handler @ >r
-003d73 3d69 .dw XT_HANDLER
-003d74 3879 .dw XT_FETCH
-003d75 38ff .dw XT_TO_R
- ; rp@ handler !
-003d76 3a76 .dw XT_RP_FETCH
-003d77 3d69 .dw XT_HANDLER
-003d78 3881 .dw XT_STORE
-003d79 382a .dw XT_EXECUTE
- ; r> handler !
-003d7a 38f6 .dw XT_R_FROM
-003d7b 3d69 .dw XT_HANDLER
-003d7c 3881 .dw XT_STORE
-003d7d 38f6 .dw XT_R_FROM
-003d7e 38d9 .dw XT_DROP
-003d7f 3954 .dw XT_ZERO
-003d80 3820 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-003d81 ff05 .dw $ff05
-003d82 6874
-003d83 6f72
-003d84 0077 .db "throw",0
-003d85 3d6b .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-003d86 3801 .dw DO_COLON
- PFA_THROW:
- .endif
-003d87 38b1 .dw XT_DUP
-003d88 391a .dw XT_ZEROEQUAL
-003d89 3836 .dw XT_DOCONDBRANCH
-003d8a 3d8d DEST(PFA_THROW1)
-003d8b 38d9 .dw XT_DROP
-003d8c 3820 .dw XT_EXIT
- PFA_THROW1:
-003d8d 3d69 .dw XT_HANDLER
-003d8e 3879 .dw XT_FETCH
-003d8f 3a80 .dw XT_RP_STORE
-003d90 38f6 .dw XT_R_FROM
-003d91 3d69 .dw XT_HANDLER
-003d92 3881 .dw XT_STORE
-003d93 38f6 .dw XT_R_FROM
-003d94 38c4 .dw XT_SWAP
-003d95 38ff .dw XT_TO_R
-003d96 3a96 .dw XT_SP_STORE
-003d97 38d9 .dw XT_DROP
-003d98 38f6 .dw XT_R_FROM
-003d99 3820 .dw XT_EXIT
-
-
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-003d9a ff07 .dw $ff07
-003d9b 6445
-003d9c 6665
-003d9d 7265
-003d9e 0040 .db "Edefer@",0
-003d9f 3d81 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-003da0 3801 .dw DO_COLON
- PFA_EDEFERFETCH:
-003da1 3bcb .dw XT_FETCHI
-003da2 3b5f .dw XT_FETCHE
-003da3 3820 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-003da4 ff07 .dw $ff07
-003da5 6445
-003da6 6665
-003da7 7265
-003da8 0021 .db "Edefer!",0
-003da9 3d9a .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-003daa 3801 .dw DO_COLON
- PFA_EDEFERSTORE:
-003dab 3bcb .dw XT_FETCHI
-003dac 3b3b .dw XT_STOREE
-003dad 3820 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-003dae ff07 .dw $ff07
-003daf 6452
-003db0 6665
-003db1 7265
-003db2 0040 .db "Rdefer@",0
-003db3 3da4 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-003db4 3801 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-003db5 3bcb .dw XT_FETCHI
-003db6 3879 .dw XT_FETCH
-003db7 3820 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-003db8 ff07 .dw $ff07
-003db9 6452
-003dba 6665
-003dbb 7265
-003dbc 0021 .db "Rdefer!",0
-003dbd 3dae .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-003dbe 3801 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-003dbf 3bcb .dw XT_FETCHI
-003dc0 3881 .dw XT_STORE
-003dc1 3820 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-003dc2 ff07 .dw $ff07
-003dc3 6455
-003dc4 6665
-003dc5 7265
-003dc6 0040 .db "Udefer@",0
-003dc7 3db8 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-003dc8 3801 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-003dc9 3bcb .dw XT_FETCHI
-003dca 3b02 .dw XT_UP_FETCH
-003dcb 399d .dw XT_PLUS
-003dcc 3879 .dw XT_FETCH
-003dcd 3820 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-003dce ff07 .dw $ff07
-003dcf 6455
-003dd0 6665
-003dd1 7265
-003dd2 0021 .db "Udefer!",0
-003dd3 3dc2 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-003dd4 3801 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-003dd5 3bcb .dw XT_FETCHI
-003dd6 3b02 .dw XT_UP_FETCH
-003dd7 399d .dw XT_PLUS
-003dd8 3881 .dw XT_STORE
-003dd9 3820 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-003dda ff06 .dw $ff06
-003ddb 6564
-003ddc 6566
-003ddd 2172 .db "defer!"
-003dde 3dce .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-003ddf 3801 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-003de0 3fd0 .dw XT_TO_BODY
-003de1 38b1 .dw XT_DUP
-003de2 01d1 .dw XT_ICELLPLUS
-003de3 01d1 .dw XT_ICELLPLUS
-003de4 3bcb .dw XT_FETCHI
-003de5 382a .dw XT_EXECUTE
-003de6 3820 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-003de7 ff06 .dw $ff06
-003de8 6564
-003de9 6566
-003dea 4072 .db "defer@"
-003deb 3dda .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-003dec 3801 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-003ded 3fd0 .dw XT_TO_BODY
-003dee 38b1 .dw XT_DUP
-003def 01d1 .dw XT_ICELLPLUS
-003df0 3bcb .dw XT_FETCHI
-003df1 382a .dw XT_EXECUTE
-003df2 3820 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-003df3 ff07 .dw $ff07
-003df4 6428
-003df5 6665
-003df6 7265
-003df7 0029 .db "(defer)", 0
-003df8 3de7 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-003df9 3801 .dw DO_COLON
- PFA_DODEFER:
-003dfa 0739 .dw XT_DOCREATE
-003dfb 0899 .dw XT_REVEAL
-003dfc 075c .dw XT_COMPILE
-003dfd 3dff .dw PFA_DODEFER1
-003dfe 3820 .dw XT_EXIT
- PFA_DODEFER1:
-003dff 940e 08b2 call_ DO_DODOES
-003e01 38b1 .dw XT_DUP
-003e02 01d1 .dw XT_ICELLPLUS
-003e03 3bcb .dw XT_FETCHI
-003e04 382a .dw XT_EXECUTE
-003e05 382a .dw XT_EXECUTE
-003e06 3820 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-003e07 ff02 .dw $ff02
-003e08 2e75 .db "u."
-003e09 3df3 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-003e0a 3801 .dw DO_COLON
- PFA_UDOT:
- .endif
-003e0b 3954 .dw XT_ZERO
-003e0c 038d .dw XT_UDDOT
-003e0d 3820 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-003e0e ff03 .dw $ff03
-003e0f 2e75
-003e10 0072 .db "u.r",0
-003e11 3e07 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-003e12 3801 .dw DO_COLON
- PFA_UDOTR:
- .endif
-003e13 3954 .dw XT_ZERO
-003e14 38c4 .dw XT_SWAP
-003e15 0396 .dw XT_UDDOTR
-003e16 3820 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-003e17 ff05 .dw $ff05
-003e18 2f75
-003e19 6f6d
-003e1a 0064 .db "u/mod",0
-003e1b 3e0e .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-003e1c 3801 .dw DO_COLON
- PFA_USLASHMOD:
-003e1d 38ff .dw XT_TO_R
-003e1e 3954 .dw XT_ZERO
-003e1f 38f6 .dw XT_R_FROM
-003e20 39c2 .dw XT_UMSLASHMOD
-003e21 3820 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-003e22 ff06 .dw $ff06
-003e23 656e
-003e24 6167
-003e25 6574 .db "negate"
-003e26 3e17 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-003e27 3801 .dw DO_COLON
- PFA_NEGATE:
-003e28 39fd .dw XT_INVERT
-003e29 3a2f .dw XT_1PLUS
-003e2a 3820 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-003e2b ff01 .dw $ff01
-003e2c 002f .db "/",0
-003e2d 3e22 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-003e2e 3801 .dw DO_COLON
- PFA_SLASH:
- .endif
-003e2f 3c49 .dw XT_SLASHMOD
-003e30 38f0 .dw XT_NIP
-003e31 3820 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-003e32 ff03 .dw $ff03
-003e33 6f6d
-003e34 0064 .db "mod",0
-003e35 3e2b .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-003e36 3801 .dw DO_COLON
- PFA_MOD:
- .endif
-003e37 3c49 .dw XT_SLASHMOD
-003e38 38d9 .dw XT_DROP
-003e39 3820 .dw XT_EXIT
-
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-003e3a ff03 .dw $ff03
-003e3b 696d
-003e3c 006e .db "min",0
-003e3d 3e32 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-003e3e 3801 .dw DO_COLON
- PFA_MIN:
- .endif
-003e3f 3ec9 .dw XT_2DUP
-003e40 3978 .dw XT_GREATER
-003e41 3836 .dw XT_DOCONDBRANCH
-003e42 3e44 DEST(PFA_MIN1)
-003e43 38c4 .dw XT_SWAP
- PFA_MIN1:
-003e44 38d9 .dw XT_DROP
-003e45 3820 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-003e46 ff03 .dw $ff03
-003e47 616d
-003e48 0078 .db "max",0
-003e49 3e3a .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-003e4a 3801 .dw DO_COLON
- PFA_MAX:
-
- .endif
-003e4b 3ec9 .dw XT_2DUP
-003e4c 396e .dw XT_LESS
-003e4d 3836 .dw XT_DOCONDBRANCH
-003e4e 3e50 DEST(PFA_MAX1)
-003e4f 38c4 .dw XT_SWAP
- PFA_MAX1:
-003e50 38d9 .dw XT_DROP
-003e51 3820 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-003e52 ff06 .dw $ff06
-003e53 6977
-003e54 6874
-003e55 6e69 .db "within"
-003e56 3e46 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-003e57 3801 .dw DO_COLON
- PFA_WITHIN:
- .endif
-003e58 38cf .dw XT_OVER
-003e59 3993 .dw XT_MINUS
-003e5a 38ff .dw XT_TO_R
-003e5b 3993 .dw XT_MINUS
-003e5c 38f6 .dw XT_R_FROM
-003e5d 395c .dw XT_ULESS
-003e5e 3820 .dw XT_EXIT
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-003e5f ff0d .dw $ff0d
-003e60 6873
-003e61 776f
-003e62 772d
-003e63 726f
-003e64 6c64
-003e65 7369
-003e66 0074 .db "show-wordlist",0
-003e67 3e52 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-003e68 3801 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-003e69 383d .dw XT_DOLITERAL
-003e6a 3e6e .dw XT_SHOWWORD
-003e6b 38c4 .dw XT_SWAP
-003e6c 06da .dw XT_TRAVERSEWORDLIST
-003e6d 3820 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-003e6e 3801 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-003e6f 06f5 .dw XT_NAME2STRING
-003e70 0403 .dw XT_ITYPE
-003e71 3fae .dw XT_SPACE ; ( -- addr n)
-003e72 394b .dw XT_TRUE
-003e73 3820 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-003e74 ff05 .dw $ff05
-003e75 6f77
-003e76 6472
-003e77 0073 .db "words",0
-003e78 3e5f .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-003e79 3801 .dw DO_COLON
- PFA_WORDS:
- .endif
-003e7a 383d .dw XT_DOLITERAL
-003e7b 004c .dw CFG_ORDERLISTLEN+2
-003e7c 3b5f .dw XT_FETCHE
-003e7d 3e68 .dw XT_SHOWWORDLIST
-003e7e 3820 .dw XT_EXIT
-
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-003e7f 0002 .dw $0002
-003e80 222e .db ".",$22
-003e81 3e74 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-003e82 3801 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-003e83 3e8a .dw XT_SQUOTE
-003e84 075c .dw XT_COMPILE
-003e85 0403 .dw XT_ITYPE
-003e86 3820 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-003e87 0002 .dw $0002
-003e88 2273 .db "s",$22
-003e89 3e7f .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-003e8a 3801 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-003e8b 383d .dw XT_DOLITERAL
-003e8c 0022 .dw 34 ; 0x22
-003e8d 058e .dw XT_PARSE ; ( -- addr n)
-003e8e 3eb7 .dw XT_STATE
-003e8f 3879 .dw XT_FETCH
-003e90 3836 .dw XT_DOCONDBRANCH
-003e91 3e93 DEST(PFA_SQUOTE1)
-003e92 0788 .dw XT_SLITERAL
- PFA_SQUOTE1:
-003e93 3820 .dw XT_EXIT
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-003e94 ff04 .dw $ff04
-003e95 6966
-003e96 6c6c .db "fill"
-003e97 3e87 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-003e98 3801 .dw DO_COLON
- PFA_FILL:
-003e99 38e1 .dw XT_ROT
-003e9a 38e1 .dw XT_ROT
-003e9b 38b9
-003e9c 3836 .dw XT_QDUP,XT_DOCONDBRANCH
-003e9d 3ea5 DEST(PFA_FILL2)
-003e9e 3f99 .dw XT_BOUNDS
-003e9f 3a9b .dw XT_DODO
- PFA_FILL1:
-003ea0 38b1 .dw XT_DUP
-003ea1 3aac .dw XT_I
-003ea2 388d .dw XT_CSTORE ; ( -- c c-addr)
-003ea3 3ac9 .dw XT_DOLOOP
-003ea4 3ea0 .dw PFA_FILL1
- PFA_FILL2:
-003ea5 38d9 .dw XT_DROP
-003ea6 3820 .dw XT_EXIT
-
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-003ea7 ff05 .dw $ff05
-003ea8 5f66
-003ea9 7063
-003eaa 0075 .db "f_cpu",0
-003eab 3e94 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-003eac 3801 .dw DO_COLON
- PFA_F_CPU:
- .endif
-003ead 383d .dw XT_DOLITERAL
-003eae 2400 .dw (F_CPU % 65536)
-003eaf 383d .dw XT_DOLITERAL
-003eb0 00f4 .dw (F_CPU / 65536)
-003eb1 3820 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-003eb2 ff05 .dw $ff05
-003eb3 7473
-003eb4 7461
-003eb5 0065 .db "state",0
-003eb6 3ea7 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-003eb7 3848 .dw PFA_DOVARIABLE
- PFA_STATE:
-003eb8 01c0 .dw ram_state
-
- .dseg
-0001c0 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-003eb9 ff04 .dw $ff04
-003eba 6162
-003ebb 6573 .db "base"
-003ebc 3eb2 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-003ebd 3858 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-003ebe 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-003ebf ff05 .dw $ff05
-003ec0 6563
-003ec1 6c6c
-003ec2 0073 .db "cells",0
-003ec3 3eb9 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-003ec4 3a0c .dw PFA_2STAR
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-003ec5 ff04 .dw $ff04
-003ec6 6432
-003ec7 7075 .db "2dup"
-003ec8 3ebf .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-003ec9 3801 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-003eca 38cf .dw XT_OVER
-003ecb 38cf .dw XT_OVER
-003ecc 3820 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-003ecd ff05 .dw $ff05
-003ece 6432
-003ecf 6f72
-003ed0 0070 .db "2drop",0
-003ed1 3ec5 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-003ed2 3801 .dw DO_COLON
- PFA_2DROP:
- .endif
-003ed3 38d9 .dw XT_DROP
-003ed4 38d9 .dw XT_DROP
-003ed5 3820 .dw XT_EXIT
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-003ed6 ff04 .dw $ff04
-003ed7 7574
-003ed8 6b63 .db "tuck"
-003ed9 3ecd .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-003eda 3801 .dw DO_COLON
- PFA_TUCK:
- .endif
-003edb 38c4 .dw XT_SWAP
-003edc 38cf .dw XT_OVER
-003edd 3820 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-003ede ff03 .dw $ff03
-003edf 693e
-003ee0 006e .db ">in",0
-003ee1 3ed6 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-003ee2 3858 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-003ee3 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-003ee4 ff03 .dw $ff03
-003ee5 6170
-003ee6 0064 .db "pad",0
-003ee7 3ede .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-003ee8 3801 .dw DO_COLON
- PFA_PAD:
- .endif
-003ee9 3f23 .dw XT_HERE
-003eea 383d .dw XT_DOLITERAL
-003eeb 0028 .dw 40
-003eec 399d .dw XT_PLUS
-003eed 3820 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-003eee ff04 .dw $ff04
-003eef 6d65
-003ef0 7469 .db "emit"
-003ef1 3ee4 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-003ef2 3dff .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-003ef3 000e .dw USER_EMIT
-003ef4 3dc8 .dw XT_UDEFERFETCH
-003ef5 3dd4 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-003ef6 ff05 .dw $ff05
-003ef7 6d65
-003ef8 7469
-003ef9 003f .db "emit?",0
-003efa 3eee .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-003efb 3dff .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-003efc 0010 .dw USER_EMITQ
-003efd 3dc8 .dw XT_UDEFERFETCH
-003efe 3dd4 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-003eff ff03 .dw $ff03
-003f00 656b
-003f01 0079 .db "key",0
-003f02 3ef6 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-003f03 3dff .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-003f04 0012 .dw USER_KEY
-003f05 3dc8 .dw XT_UDEFERFETCH
-003f06 3dd4 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-003f07 ff04 .dw $ff04
-003f08 656b
-003f09 3f79 .db "key?"
-003f0a 3eff .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-003f0b 3dff .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-003f0c 0014 .dw USER_KEYQ
-003f0d 3dc8 .dw XT_UDEFERFETCH
-003f0e 3dd4 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-003f0f ff02 .dw $ff02
-003f10 7064 .db "dp"
-003f11 3f07 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-003f12 386f .dw PFA_DOVALUE1
- PFA_DP:
-003f13 0036 .dw CFG_DP
-003f14 3da0 .dw XT_EDEFERFETCH
-003f15 3daa .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-003f16 ff05 .dw $ff05
-003f17 6865
-003f18 7265
-003f19 0065 .db "ehere",0
-003f1a 3f0f .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-003f1b 386f .dw PFA_DOVALUE1
- PFA_EHERE:
-003f1c 003a .dw EE_EHERE
-003f1d 3da0 .dw XT_EDEFERFETCH
-003f1e 3daa .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-003f1f ff04 .dw $ff04
-003f20 6568
-003f21 6572 .db "here"
-003f22 3f16 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-003f23 386f .dw PFA_DOVALUE1
- PFA_HERE:
-003f24 0038 .dw EE_HERE
-003f25 3da0 .dw XT_EDEFERFETCH
-003f26 3daa .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-003f27 ff05 .dw $ff05
-003f28 6c61
-003f29 6f6c
-003f2a 0074 .db "allot",0
-003f2b 3f1f .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-003f2c 3801 .dw DO_COLON
- PFA_ALLOT:
-003f2d 3f23 .dw XT_HERE
-003f2e 399d .dw XT_PLUS
-003f2f 01bf .dw XT_DOTO
-003f30 3f24 .dw PFA_HERE
-003f31 3820 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-003f32 ff03 .dw $ff03
-003f33 6962
-003f34 006e .db "bin",0
-003f35 3f27 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-003f36 3801 .dw DO_COLON
- PFA_BIN:
- .endif
-003f37 3feb .dw XT_TWO
-003f38 3ebd .dw XT_BASE
-003f39 3881 .dw XT_STORE
-003f3a 3820 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-003f3b ff07 .dw $ff07
-003f3c 6564
-003f3d 6963
-003f3e 616d
-003f3f 006c .db "decimal",0
-003f40 3f32 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-003f41 3801 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-003f42 383d .dw XT_DOLITERAL
-003f43 000a .dw 10
-003f44 3ebd .dw XT_BASE
-003f45 3881 .dw XT_STORE
-003f46 3820 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-003f47 ff03 .dw $ff03
-003f48 6568
-003f49 0078 .db "hex",0
-003f4a 3f3b .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-003f4b 3801 .dw DO_COLON
- PFA_HEX:
- .endif
-003f4c 383d .dw XT_DOLITERAL
-003f4d 0010 .dw 16
-003f4e 3ebd .dw XT_BASE
-003f4f 3881 .dw XT_STORE
-003f50 3820 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-003f51 ff02 .dw $ff02
-003f52 6c62 .db "bl"
-003f53 3f47 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-003f54 3848 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-003f55 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-003f56 ff07 .dw $ff07
-003f57 7574
-003f58 6e72
-003f59 656b
-003f5a 0079 .db "turnkey",0
-003f5b 3f51 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-003f5c 3dff .dw PFA_DODEFER1
- PFA_TURNKEY:
-003f5d 0042 .dw CFG_TURNKEY
-003f5e 3da0 .dw XT_EDEFERFETCH
-003f5f 3daa .dw XT_EDEFERSTORE
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-003f60 ff07 .dw $ff07
-003f61 6f74
-003f62 7075
-003f63 6570
-003f64 0072 .db "toupper",0
-003f65 3f56 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-003f66 3801 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-003f67 38b1 .dw XT_DUP
-003f68 383d .dw XT_DOLITERAL
-003f69 0061 .dw 'a'
-003f6a 383d .dw XT_DOLITERAL
-003f6b 007b .dw 'z'+1
-003f6c 3e57 .dw XT_WITHIN
-003f6d 3836 .dw XT_DOCONDBRANCH
-003f6e 3f72 DEST(PFA_TOUPPER0)
-003f6f 383d .dw XT_DOLITERAL
-003f70 00df .dw 223 ; inverse of 0x20: 0xdf
-003f71 3a13 .dw XT_AND
- PFA_TOUPPER0:
-003f72 3820 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-003f73 ff07 .dw $ff07
-003f74 6f74
-003f75 6f6c
-003f76 6577
-003f77 0072 .db "tolower",0
-003f78 3f60 .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-003f79 3801 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-003f7a 38b1 .dw XT_DUP
-003f7b 383d .dw XT_DOLITERAL
-003f7c 0041 .dw 'A'
-003f7d 383d .dw XT_DOLITERAL
-003f7e 005b .dw 'Z'+1
-003f7f 3e57 .dw XT_WITHIN
-003f80 3836 .dw XT_DOCONDBRANCH
-003f81 3f85 DEST(PFA_TOLOWER0)
-003f82 383d .dw XT_DOLITERAL
-003f83 0020 .dw 32
-003f84 3a1c .dw XT_OR
- PFA_TOLOWER0:
-003f85 3820 .dw XT_EXIT
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-003f86 ff06 .dw $ff06
-003f87 733f
-003f88 6174
-003f89 6b63 .db "?stack"
-003f8a 3f73 .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-003f8b 3801 .dw DO_COLON
- PFA_QSTACK:
- .endif
-003f8c 05ed .dw XT_DEPTH
-003f8d 3921 .dw XT_ZEROLESS
-003f8e 3836 .dw XT_DOCONDBRANCH
-003f8f 3f93 DEST(PFA_QSTACK1)
-003f90 383d .dw XT_DOLITERAL
-003f91 fffc .dw -4
-003f92 3d86 .dw XT_THROW
- PFA_QSTACK1:
-003f93 3820 .dw XT_EXIT
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-003f94 ff06 .dw $ff06
-003f95 6f62
-003f96 6e75
-003f97 7364 .db "bounds"
-003f98 3f86 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-003f99 3801 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-003f9a 38cf .dw XT_OVER
-003f9b 399d .dw XT_PLUS
-003f9c 38c4 .dw XT_SWAP
-003f9d 3820 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-003f9e ff02 .dw 0xff02
-003f9f 7263 .db "cr"
-003fa0 3f94 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-003fa1 3801 .dw DO_COLON
- PFA_CR:
- .endif
-
-003fa2 383d .dw XT_DOLITERAL
-003fa3 000d .dw 13
-003fa4 3ef2 .dw XT_EMIT
-003fa5 383d .dw XT_DOLITERAL
-003fa6 000a .dw 10
-003fa7 3ef2 .dw XT_EMIT
-003fa8 3820 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-003fa9 ff05 .dw $ff05
-003faa 7073
-003fab 6361
-003fac 0065 .db "space",0
-003fad 3f9e .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-003fae 3801 .dw DO_COLON
- PFA_SPACE:
- .endif
-003faf 3f54 .dw XT_BL
-003fb0 3ef2 .dw XT_EMIT
-003fb1 3820 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-003fb2 ff06 .dw $ff06
-003fb3 7073
-003fb4 6361
-003fb5 7365 .db "spaces"
-003fb6 3fa9 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-003fb7 3801 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-003fb8 3954
-003fb9 3e4a .DW XT_ZERO, XT_MAX
-003fba 38b1
-003fbb 3836 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-003fbc 3fc1 DEST(SPCS2)
-003fbd 3fae
-003fbe 3a35
-003fbf 382f .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-003fc0 3fba DEST(SPCS1)
-003fc1 38d9
-003fc2 3820 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-003fc3 ff03 .dw $ff03
-003fc4 3e73
-003fc5 0064 .db "s>d",0
-003fc6 3fb2 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-003fc7 3801 .dw DO_COLON
- PFA_S2D:
- .endif
-003fc8 38b1 .dw XT_DUP
-003fc9 3921 .dw XT_ZEROLESS
-003fca 3820 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-003fcb ff05 .dw $ff05
-003fcc 623e
-003fcd 646f
-003fce 0079 .db ">body",0
-003fcf 3fc3 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-003fd0 3a30 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-003fd1 0008 .dw $0008
-003fd2 6c32
-003fd3 7469
-003fd4 7265
-003fd5 6c61 .db "2literal"
-003fd6 3fcb .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-003fd7 3801 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-003fd8 38c4 .dw XT_SWAP
-003fd9 077d .dw XT_LITERAL
-003fda 077d .dw XT_LITERAL
-003fdb 3820 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-003fdc ff01 .dw $ff01
-003fdd 003d .db "=",0
-003fde 3fd1 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-003fdf 3801 .dw DO_COLON
- PFA_EQUAL:
-003fe0 3993 .dw XT_MINUS
-003fe1 391a .dw XT_ZEROEQUAL
-003fe2 3820 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-003fe3 ff01 .dw $ff01
-003fe4 0031 .db "1",0
-003fe5 3fdc .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-003fe6 3848 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-003fe7 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-003fe8 ff01 .dw $ff01
-003fe9 0032 .db "2",0
-003fea 3fe3 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-003feb 3848 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-003fec 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-003fed ff02 .dw $ff02
-003fee 312d .db "-1"
-003fef 3fe8 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-003ff0 3848 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-003ff1 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000034 ff ff
- ; some configs
-000036 26 0b CFG_DP: .dw DPSTART ; Dictionary Pointer
-000038 c2 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00003a 8e 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00003c ce 09 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-00003e 5c 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000040 b0 08 CFG_LP0: .dw stackstart+1
-000042 78 0a CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000044 ff 02 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000046 48 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-000048 ed 3f CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00004a 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00004c 48 00 .dw CFG_FORTHWORDLIST ; get/set-order
-00004e .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00005c 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-00005e 70 06 .dw XT_REC_FIND
-000060 5c 06 .dw XT_REC_NUM
-000062 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-000066 7e 3b .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-000068 68 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00006a 00 00 .dw 0 ; USER_STATE
-00006c 00 00 .dw 0 ; USER_FOLLOWER
-00006e ff 08 .dw rstackstart ; USER_RP
-000070 af 08 .dw stackstart ; USER_SP0
-000072 af 08 .dw stackstart ; USER_SP
-
-000074 00 00 .dw 0 ; USER_HANDLER
-000076 0a 00 .dw 10 ; USER_BASE
-
-000078 a3 00 .dw XT_TX ; USER_EMIT
-00007a b1 00 .dw XT_TXQ ; USER_EMITQ
-00007c 78 00 .dw XT_RX ; USER_KEY
-00007e 93 00 .dw XT_RXQ ; USER_KEYQ
-000080 77 02 .dw XT_SOURCETIB ; USER_SOURCE
-000082 00 00 .dw 0 ; USER_G_IN
-000084 64 02 .dw XT_REFILLTIB ; USER_REFILL
-000086 c9 3c .dw XT_DEFAULT_PROMPTOK
-000088 e8 3c .dw XT_DEFAULT_PROMPTERROR
-00008a d8 3c .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-00008c 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega328P" register use summary:
-r0 : 25 r1 : 5 r2 : 10 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 89 r17: 61 r18: 61 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 212 r25: 145 r26: 28 r27: 17 r28: 7 r29: 4 r30: 90 r31: 49
-x : 4 y : 217 z : 50
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega328P" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 22 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 1
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 14 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 25 inc : 3 jmp : 13
-ld : 145 ldd : 4 ldi : 41 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 16 movw : 72 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 2 out : 22 pop : 49
-push : 43 rcall : 39 ret : 7 reti : 1 rjmp : 106 rol : 23
-ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3 sbis : 0
-sbiw : 16 sbr : 0 sbrc : 5 sbrs : 7 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 4 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 81 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 72 out of 113 (63.7%)
-
-"ATmega328P" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x007fe4 2082 11710 13792 32768 42.1%
-[.dseg] 0x000100 0x0001c2 0 194 194 2048 9.5%
-[.eseg] 0x000000 0x00008e 0 142 142 1024 13.9%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/eval-pollin/p328-16.map b/amforth-6.5/appl/eval-pollin/p328-16.map
deleted file mode 100644
index 4d9ad44..0000000
--- a/amforth-6.5/appl/eval-pollin/p328-16.map
+++ /dev/null
@@ -1,2054 +0,0 @@
-
-AVRASM ver. 2.1.52 p328-16.asm Sun Apr 30 20:10:15 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000095
-EQU SIGNATURE_002 0000000f
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK1 0000006c
-EQU PCMSK2 0000006d
-EQU PCMSK0 0000006b
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU WGM11 00000001
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU PSRSYNC 00000000
-EQU TSM 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ACME 00000006
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSR10 00000000
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SELFPRGEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU BODSE 00000005
-EQU BODS 00000006
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU EXTREF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU DWEN 00000006
-EQU RSTDISBL 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00003fff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00000800
-EQU RAMEND 000008ff
-EQU XRAMEND 00000000
-EQU E2END 000003ff
-EQU EEPROMEND 000003ff
-EQU EEADRBITS 0000000a
-EQU NRWW_START_ADDR 00003800
-EQU NRWW_STOP_ADDR 00003fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 000037ff
-EQU PAGESIZE 00000040
-EQU FIRSTBOOTSTART 00003f00
-EQU SECONDBOOTSTART 00003e00
-EQU THIRDBOOTSTART 00003c00
-EQU FOURTHBOOTSTART 00003800
-EQU SMALLBOOTSTART 00003f00
-EQU LARGEBOOTSTART 00003800
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU PCI0addr 00000006
-EQU PCI1addr 00000008
-EQU PCI2addr 0000000a
-EQU WDTaddr 0000000c
-EQU OC2Aaddr 0000000e
-EQU OC2Baddr 00000010
-EQU OVF2addr 00000012
-EQU ICP1addr 00000014
-EQU OC1Aaddr 00000016
-EQU OC1Baddr 00000018
-EQU OVF1addr 0000001a
-EQU OC0Aaddr 0000001c
-EQU OC0Baddr 0000001e
-EQU OVF0addr 00000020
-EQU SPIaddr 00000022
-EQU URXCaddr 00000024
-EQU UDREaddr 00000026
-EQU UTXCaddr 00000028
-EQU ADCCaddr 0000002a
-EQU ERDYaddr 0000002c
-EQU ACIaddr 0000002e
-EQU TWIaddr 00000030
-EQU SPMRaddr 00000032
-EQU INT_VECTORS_SIZE 00000034
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_USART0 00000000
-SET WANT_TWI 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_SPI 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_CPU 00000000
-SET WANT_EEPROM 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 00000129
-EQU INTVECTORS 0000001a
-EQU SPMEN 00000000
-CSEG mcu_info 00000033
-CSEG mcu_ramsize 00000033
-CSEG mcu_eepromsize 00000034
-CSEG mcu_maxdp 00000035
-CSEG mcu_numints 00000036
-CSEG mcu_name 00000037
-SET codestart 0000003d
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000008ff
-SET stackstart 000008af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000001e
-SET VE_HEAD 00003fed
-SET VE_ENVHEAD 000002ff
-SET AMFORTH_RO_SEG 00003801
-EQU F_CPU 00f42400
-EQU TIMER_INT 00000012
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 0000003d
-CSEG XT_TO_RXBUF 00000043
-CSEG PFA_rx_tobuf 00000044
-CSEG DO_NEXT 00003805
-CSEG VE_ISR_RX 00000054
-CSEG XT_ISR_RX 00000059
-CSEG DO_COLON 00003801
-CSEG usart_rx_isr 0000005a
-CSEG XT_DOLITERAL 0000383d
-CSEG XT_CFETCH 00003898
-CSEG XT_DUP 000038b1
-CSEG XT_EQUAL 00003fdf
-CSEG XT_DOCONDBRANCH 00003836
-CSEG usart_rx_isr1 00000064
-CSEG XT_COLD 00003d38
-CSEG XT_EXIT 00003820
-CSEG XT_USART_INIT_RX_BUFFER 00000066
-CSEG PFA_USART_INIT_RX_BUFFER 00000067
-CSEG XT_INTSTORE 00003ca5
-CSEG XT_ZERO 00003954
-CSEG XT_FILL 00003e98
-CSEG VE_RX_BUFFER 00000073
-CSEG XT_RX_BUFFER 00000078
-CSEG PFA_RX_BUFFER 00000079
-CSEG XT_RXQ_BUFFER 00000093
-CSEG XT_PLUS 0000399d
-CSEG XT_SWAP 000038c4
-CSEG XT_1PLUS 00003a2f
-CSEG XT_AND 00003a13
-CSEG XT_CSTORE 0000388d
-CSEG VE_RXQ_BUFFER 0000008d
-CSEG PFA_RXQ_BUFFER 00000094
-CSEG XT_PAUSE 00003d30
-CSEG XT_NOTEQUAL 00003913
-SET XT_RX 00000078
-SET XT_RXQ 00000093
-SET XT_USART_INIT_RX 00000066
-CSEG VE_TX_POLL 0000009d
-CSEG XT_TX_POLL 000000a3
-CSEG PFA_TX_POLL 000000a4
-CSEG XT_TXQ_POLL 000000b1
-CSEG VE_TXQ_POLL 000000ab
-CSEG PFA_TXQ_POLL 000000b2
-SET XT_TX 000000a3
-SET XT_TXQ 000000b1
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000ba
-CSEG XT_UBRR 000000be
-CSEG PFA_DOVALUE1 0000386f
-CSEG PFA_UBRR 000000bf
-ESEG EE_UBRRVAL 0000008c
-CSEG XT_EDEFERFETCH 00003da0
-CSEG XT_EDEFERSTORE 00003daa
-CSEG VE_USART 000000c2
-CSEG XT_USART 000000c7
-CSEG PFA_USART 000000c8
-CSEG XT_BYTESWAP 00003af9
-EQU OW_PORT 00000005
-EQU OW_BIT 00000004
-SET OW_DDR 00000004
-SET OW_PIN 00000003
-CSEG VE_OW_RESET 000000dd
-CSEG XT_OW_RESET 000000e3
-CSEG PFA_OW_RESET 000000e4
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_OW_SLOT 00000101
-CSEG XT_OW_SLOT 00000107
-CSEG PFA_OW_SLOT 00000108
-CSEG PFA_OW_SLOT0 00000115
-SET AMFORTH_NRWW_SIZE 00000ffc
-SET corepc 00000129
-CSEG PFA_COLD 00003d39
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 00000140
-CSEG XT_MPLUS 00000143
-CSEG PFA_MPLUS 00000144
-CSEG XT_S2D 00003fc7
-CSEG XT_DPLUS 00003c15
-CSEG VE_UDSTAR 00000147
-CSEG XT_UDSTAR 0000014b
-CSEG PFA_UDSTAR 0000014c
-CSEG XT_TO_R 000038ff
-CSEG XT_UMSTAR 000039e0
-CSEG XT_DROP 000038d9
-CSEG XT_R_FROM 000038f6
-CSEG XT_ROT 000038e1
-CSEG VE_UMAX 00000156
-CSEG XT_UMAX 0000015a
-CSEG PFA_UMAX 0000015b
-CSEG XT_2DUP 00003ec9
-CSEG XT_ULESS 0000395c
-CSEG UMAX1 00000160
-CSEG VE_UMIN 00000162
-CSEG XT_UMIN 00000166
-CSEG PFA_UMIN 00000167
-CSEG XT_UGREATER 00003967
-CSEG UMIN1 0000016c
-CSEG XT_IMMEDIATEQ 0000016e
-CSEG PFA_IMMEDIATEQ 0000016f
-CSEG XT_ZEROEQUAL 0000391a
-CSEG IMMEDIATEQ1 00000177
-CSEG XT_ONE 00003fe6
-CSEG XT_TRUE 0000394b
-CSEG VE_NAME2FLAGS 00000179
-CSEG XT_NAME2FLAGS 00000180
-CSEG PFA_NAME2FLAGS 00000181
-CSEG XT_FETCHI 00003bcb
-CSEG VE_DOT_VER 00000186
-CSEG XT_DOT_VER 0000018a
-CSEG PFA_DOT_VER 0000018b
-CSEG XT_ENV_FORTHNAME 000002da
-CSEG XT_ITYPE 00000403
-CSEG XT_SPACE 00003fae
-CSEG XT_BASE 00003ebd
-CSEG XT_FETCH 00003879
-CSEG XT_ENV_FORTHVERSION 000002e8
-CSEG XT_DECIMAL 00003f41
-CSEG XT_L_SHARP 00000321
-CSEG XT_SHARP 00000329
-CSEG XT_HOLD 00000312
-CSEG XT_SHARP_S 0000033f
-CSEG XT_SHARP_G 0000034a
-CSEG XT_TYPE 00000439
-CSEG XT_STORE 00003881
-CSEG XT_ENV_CPU 000002f0
-CSEG VE_NOOP 000001a1
-CSEG XT_NOOP 000001a5
-CSEG PFA_NOOP 000001a6
-CSEG VE_UNUSED 000001a7
-CSEG XT_UNUSED 000001ac
-CSEG PFA_UNUSED 000001ad
-CSEG XT_SP_FETCH 00003a8d
-CSEG XT_HERE 00003f23
-CSEG XT_MINUS 00003993
-CSEG VE_TO 000001b1
-CSEG XT_TO 000001b4
-CSEG PFA_TO 000001b5
-CSEG XT_TICK 00000448
-CSEG XT_TO_BODY 00003fd0
-CSEG XT_STATE 00003eb7
-CSEG PFA_TO1 000001c5
-CSEG XT_COMPILE 0000075c
-CSEG XT_DOTO 000001bf
-CSEG XT_COMMA 00000767
-CSEG PFA_DOTO 000001c0
-CSEG XT_ICELLPLUS 000001d1
-CSEG XT_EXECUTE 0000382a
-CSEG VE_ICELLPLUS 000001cb
-CSEG PFA_ICELLPLUS 000001d2
-CSEG VE_ICOMPARE 000001d4
-CSEG XT_ICOMPARE 000001da
-CSEG PFA_ICOMPARE 000001db
-CSEG XT_OVER 000038cf
-CSEG PFA_ICOMPARE_SAMELEN 000001e5
-CSEG XT_2DROP 00003ed2
-CSEG XT_QDOCHECK 00000826
-CSEG PFA_ICOMPARE_DONE 00000208
-CSEG XT_DODO 00003a9b
-CSEG PFA_ICOMPARE_LOOP 000001eb
-CSEG PFA_ICOMPARE_LASTCELL 000001f9
-CSEG PFA_ICOMPARE_NEXTLOOP 00000200
-CSEG XT_UNLOOP 00003ad4
-CSEG XT_CELLPLUS 00003c90
-CSEG XT_DOPLUSLOOP 00003aba
-CSEG VE_STAR 0000020b
-CSEG XT_STAR 0000020e
-CSEG PFA_STAR 0000020f
-CSEG XT_MSTAR 000039a6
-CSEG VE_J 00000212
-CSEG XT_J 00000215
-CSEG PFA_J 00000216
-CSEG XT_RP_FETCH 00003a76
-CSEG VE_DABS 00000222
-CSEG XT_DABS 00000226
-CSEG PFA_DABS 00000227
-CSEG XT_ZEROLESS 00003921
-CSEG PFA_DABS1 0000022c
-CSEG XT_DNEGATE 00000233
-CSEG VE_DNEGATE 0000022d
-CSEG PFA_DNEGATE 00000234
-CSEG XT_DINVERT 00003c3b
-CSEG VE_CMOVE 00000239
-CSEG XT_CMOVE 0000023e
-CSEG PFA_CMOVE 0000023f
-CSEG PFA_CMOVE1 0000024c
-CSEG PFA_CMOVE2 00000248
-CSEG VE_2SWAP 00000252
-CSEG XT_2SWAP 00000257
-CSEG PFA_2SWAP 00000258
-CSEG VE_REFILLTIB 0000025d
-CSEG XT_REFILLTIB 00000264
-CSEG PFA_REFILLTIB 00000265
-CSEG XT_TIB 00000280
-CSEG XT_ACCEPT 00000498
-CSEG XT_NUMBERTIB 00000286
-CSEG XT_TO_IN 00003ee2
-CSEG VE_SOURCETIB 00000270
-CSEG XT_SOURCETIB 00000277
-CSEG PFA_SOURCETIB 00000278
-CSEG VE_TIB 0000027c
-CSEG PFA_DOVARIABLE 00003848
-CSEG PFA_TIB 00000281
-DSEG ram_tib 0000012c
-CSEG VE_NUMBERTIB 00000282
-CSEG PFA_NUMBERTIB 00000287
-DSEG ram_sharptib 00000186
-CSEG VE_EE2RAM 00000288
-CSEG XT_EE2RAM 0000028d
-CSEG PFA_EE2RAM 0000028e
-CSEG PFA_EE2RAM_1 00000290
-CSEG XT_FETCHE 00003b5f
-CSEG XT_DOLOOP 00003ac9
-CSEG PFA_EE2RAM_2 0000029a
-CSEG VE_INIT_RAM 0000029c
-CSEG XT_INIT_RAM 000002a2
-CSEG PFA_INI_RAM 000002a3
-ESEG EE_INITUSER 0000006a
-CSEG XT_UP_FETCH 00003b02
-CSEG XT_2SLASH 00003a04
-CSEG VE_ENVIRONMENT 000002ab
-CSEG XT_ENVIRONMENT 000002b3
-CSEG PFA_ENVIRONMENT 000002b4
-ESEG CFG_ENVIRONMENT 00000044
-CSEG VE_ENVWORDLISTS 000002b5
-CSEG XT_ENVWORDLISTS 000002bc
-CSEG PFA_ENVWORDLISTS 000002bd
-CSEG VE_ENVSLASHPAD 000002c0
-CSEG XT_ENVSLASHPAD 000002c4
-CSEG PFA_ENVSLASHPAD 000002c5
-CSEG XT_PAD 00003ee8
-CSEG VE_ENVSLASHHOLD 000002c9
-CSEG XT_ENVSLASHHOLD 000002ce
-CSEG PFA_ENVSLASHHOLD 000002cf
-CSEG VE_ENV_FORTHNAME 000002d3
-CSEG PFA_EN_FORTHNAME 000002db
-CSEG XT_DOSLITERAL 000003d0
-CSEG VE_ENV_FORTHVERSION 000002e2
-CSEG PFA_EN_FORTHVERSION 000002e9
-CSEG VE_ENV_CPU 000002ec
-CSEG PFA_EN_CPU 000002f1
-CSEG XT_ICOUNT 0000042f
-CSEG VE_ENV_MCUINFO 000002f5
-CSEG XT_ENV_MCUINFO 000002fb
-CSEG PFA_EN_MCUINFO 000002fc
-CSEG VE_ENVUSERSIZE 000002ff
-CSEG XT_ENVUSERSIZE 00000304
-CSEG PFA_ENVUSERSIZE 00000305
-CSEG VE_HLD 00000308
-CSEG XT_HLD 0000030c
-CSEG PFA_HLD 0000030d
-DSEG ram_hld 00000188
-CSEG VE_HOLD 0000030e
-CSEG PFA_HOLD 00000313
-CSEG XT_1MINUS 00003a35
-CSEG VE_L_SHARP 0000031e
-CSEG PFA_L_SHARP 00000322
-CSEG VE_SHARP 00000326
-CSEG PFA_SHARP 0000032a
-CSEG XT_UDSLASHMOD 000003a6
-CSEG XT_LESS 0000396e
-CSEG PFA_SHARP1 00000337
-CSEG VE_SHARP_S 0000033c
-CSEG PFA_SHARP_S 00000340
-CSEG NUMS1 00000340
-CSEG XT_OR 00003a1c
-CSEG VE_SHARP_G 00000347
-CSEG PFA_SHARP_G 0000034b
-CSEG VE_SIGN 00000352
-CSEG XT_SIGN 00000356
-CSEG PFA_SIGN 00000357
-CSEG PFA_SIGN1 0000035d
-CSEG VE_DDOTR 0000035e
-CSEG XT_DDOTR 00000362
-CSEG PFA_DDOTR 00000363
-CSEG XT_TUCK 00003eda
-CSEG XT_SPACES 00003fb7
-CSEG VE_DOTR 00000371
-CSEG XT_DOTR 00000374
-CSEG PFA_DOTR 00000375
-CSEG VE_DDOT 0000037a
-CSEG XT_DDOT 0000037d
-CSEG PFA_DDOT 0000037e
-CSEG VE_DOT 00000382
-CSEG XT_DOT 00000385
-CSEG PFA_DOT 00000386
-CSEG VE_UDDOT 00000389
-CSEG XT_UDDOT 0000038d
-CSEG PFA_UDDOT 0000038e
-CSEG XT_UDDOTR 00000396
-CSEG VE_UDDOTR 00000392
-CSEG PFA_UDDOTR 00000397
-CSEG VE_UDSLASHMOD 000003a1
-CSEG PFA_UDSLASHMOD 000003a7
-CSEG XT_R_FETCH 00003908
-CSEG XT_UMSLASHMOD 000039c2
-CSEG VE_DIGITQ 000003b1
-CSEG XT_DIGITQ 000003b6
-CSEG PFA_DIGITQ 000003b7
-CSEG XT_TOUPPER 00003f66
-CSEG XT_GREATER 00003978
-CSEG PFA_DOSLITERAL 000003d1
-CSEG VE_SCOMMA 000003db
-CSEG XT_SCOMMA 000003de
-CSEG PFA_SCOMMA 000003df
-CSEG XT_DOSCOMMA 000003e2
-CSEG PFA_DOSCOMMA 000003e3
-CSEG XT_2STAR 00003a0b
-CSEG PFA_SCOMMA2 000003f5
-CSEG PFA_SCOMMA1 000003ef
-CSEG XT_GREATERZERO 00003928
-CSEG PFA_SCOMMA3 000003fc
-CSEG VE_ITYPE 000003fe
-CSEG PFA_ITYPE 00000404
-CSEG PFA_ITYPE2 00000417
-CSEG PFA_ITYPE1 0000040f
-CSEG XT_LOWEMIT 00000424
-CSEG XT_HIEMIT 00000420
-CSEG PFA_ITYPE3 0000041e
-CSEG PFA_HIEMIT 00000421
-CSEG PFA_LOWEMIT 00000425
-CSEG XT_EMIT 00003ef2
-CSEG VE_ICOUNT 0000042a
-CSEG PFA_ICOUNT 00000430
-CSEG VE_TYPE 00000435
-CSEG PFA_TYPE 0000043a
-CSEG XT_BOUNDS 00003f99
-CSEG PFA_TYPE2 00000444
-CSEG PFA_TYPE1 0000043f
-CSEG XT_I 00003aac
-CSEG VE_TICK 00000445
-CSEG PFA_TICK 00000449
-CSEG XT_PARSENAME 000005bb
-CSEG XT_FORTHRECOGNIZER 000005fe
-CSEG XT_RECOGNIZE 00000609
-CSEG XT_DT_NULL 00000696
-CSEG PFA_TICK1 0000045a
-CSEG XT_THROW 00003d86
-CSEG VE_CSKIP 0000045c
-CSEG XT_CSKIP 00000461
-CSEG PFA_CSKIP 00000462
-CSEG PFA_CSKIP1 00000463
-CSEG PFA_CSKIP2 00000470
-CSEG XT_SLASHSTRING 000005ac
-CSEG XT_DOBRANCH 0000382f
-CSEG VE_CSCAN 00000473
-CSEG XT_CSCAN 00000478
-CSEG PFA_CSCAN 00000479
-CSEG PFA_CSCAN1 0000047b
-CSEG PFA_CSCAN2 0000048d
-CSEG XT_NIP 000038f0
-CSEG VE_ACCEPT 00000493
-CSEG PFA_ACCEPT 00000499
-CSEG ACC1 0000049d
-CSEG XT_KEY 00003f03
-CSEG XT_CRLFQ 000004d9
-CSEG ACC5 000004cb
-CSEG ACC3 000004bb
-CSEG ACC6 000004b9
-CSEG XT_BS 000004d1
-CSEG ACC4 000004c9
-CSEG XT_BL 00003f54
-CSEG PFA_ACCEPT6 000004c2
-CSEG XT_CR 00003fa1
-CSEG VE_REFILL 000004e4
-CSEG XT_REFILL 000004e9
-CSEG PFA_DODEFER1 00003dff
-CSEG PFA_REFILL 000004ea
-CSEG XT_UDEFERFETCH 00003dc8
-CSEG XT_UDEFERSTORE 00003dd4
-CSEG VE_CHAR 000004ed
-CSEG XT_CHAR 000004f1
-CSEG PFA_CHAR 000004f2
-CSEG VE_NUMBER 000004f6
-CSEG XT_NUMBER 000004fb
-CSEG PFA_NUMBER 000004fc
-CSEG XT_QSIGN 0000053f
-CSEG XT_SET_BASE 00000552
-CSEG PFA_NUMBER0 00000512
-CSEG XT_2TO_R 00003b1e
-CSEG XT_2R_FROM 00003b2d
-CSEG XT_TO_NUMBER 00000570
-CSEG XT_QDUP 000038b9
-CSEG PFA_NUMBER1 00000534
-CSEG PFA_NUMBER2 0000052b
-CSEG PFA_NUMBER6 0000052c
-CSEG PFA_NUMBER3 00000528
-CSEG XT_TWO 00003feb
-CSEG PFA_NUMBER5 0000053a
-CSEG PFA_NUMBER4 00000539
-CSEG XT_NEGATE 00003e27
-CSEG PFA_QSIGN 00000540
-CSEG PFA_NUMBERSIGN_DONE 0000054b
-CSEG XT_BASES 0000054d
-CSEG PFA_DOCONSTANT 00003852
-CSEG PFA_SET_BASE 00000553
-CSEG XT_WITHIN 00003e57
-CSEG SET_BASE1 00000568
-CSEG SET_BASE2 00000569
-CSEG VE_TO_NUMBER 0000056a
-CSEG TONUM1 00000571
-CSEG TONUM3 00000588
-CSEG TONUM2 0000057c
-CSEG VE_PARSE 00000589
-CSEG XT_PARSE 0000058e
-CSEG PFA_PARSE 0000058f
-CSEG XT_SOURCE 000005a2
-CSEG XT_PLUSSTORE 00003a65
-CSEG VE_SOURCE 0000059d
-CSEG PFA_SOURCE 000005a3
-CSEG VE_SLASHSTRING 000005a6
-CSEG PFA_SLASHSTRING 000005ad
-CSEG VE_PARSENAME 000005b4
-CSEG PFA_PARSENAME 000005bc
-CSEG XT_SKIPSCANCHAR 000005bf
-CSEG PFA_SKIPSCANCHAR 000005c0
-CSEG VE_SP0 000005d1
-CSEG XT_SP0 000005d5
-CSEG PFA_SP0 000005d6
-CSEG VE_SP 000005d9
-CSEG XT_SP 000005dc
-CSEG PFA_DOUSER 00003858
-CSEG PFA_SP 000005dd
-CSEG VE_RP0 000005de
-CSEG XT_RP0 000005e2
-CSEG PFA_RP0 000005e3
-CSEG XT_DORP0 000005e6
-CSEG PFA_DORP0 000005e7
-CSEG VE_DEPTH 000005e8
-CSEG XT_DEPTH 000005ed
-CSEG PFA_DEPTH 000005ee
-CSEG VE_FORTHRECOGNIZER 000005f4
-CSEG PFA_FORTHRECOGNIZER 000005ff
-ESEG CFG_FORTHRECOGNIZER 0000003e
-CSEG VE_RECOGNIZE 00000602
-CSEG PFA_RECOGNIZE 0000060a
-CSEG XT_RECOGNIZE_A 00000614
-CSEG XT_MAPSTACK 000009a7
-CSEG PFA_RECOGNIZE1 00000613
-CSEG PFA_RECOGNIZE_A 00000615
-CSEG PFA_RECOGNIZE_A1 00000625
-CSEG VE_INTERPRET 00000629
-CSEG XT_INTERPRET 00000630
-CSEG PFA_INTERPRET 00000631
-CSEG PFA_INTERPRET2 00000641
-CSEG PFA_INTERPRET1 0000063c
-CSEG XT_QSTACK 00003f8b
-CSEG VE_DT_NUM 00000643
-CSEG XT_DT_NUM 00000648
-CSEG PFA_DT_NUM 00000649
-CSEG XT_LITERAL 0000077d
-CSEG VE_DT_DNUM 0000064c
-CSEG XT_DT_DNUM 00000652
-CSEG PFA_DT_DNUM 00000653
-CSEG XT_2LITERAL 00003fd7
-CSEG VE_REC_NUM 00000656
-CSEG XT_REC_NUM 0000065c
-CSEG PFA_REC_NUM 0000065d
-CSEG PFA_REC_NONUMBER 00000668
-CSEG PFA_REC_INTNUM2 00000666
-CSEG VE_REC_FIND 0000066a
-CSEG XT_REC_FIND 00000670
-CSEG PFA_REC_FIND 00000671
-CSEG XT_FINDXT 0000070b
-CSEG PFA_REC_WORD_FOUND 00000679
-CSEG XT_DT_XT 00000680
-CSEG VE_DT_XT 0000067b
-CSEG PFA_DT_XT 00000681
-CSEG XT_R_WORD_INTERPRET 00000684
-CSEG XT_R_WORD_COMPILE 00000688
-CSEG PFA_R_WORD_INTERPRET 00000685
-CSEG PFA_R_WORD_COMPILE 00000689
-CSEG PFA_R_WORD_COMPILE1 0000068e
-CSEG VE_DT_NULL 00000690
-CSEG PFA_DT_NULL 00000697
-CSEG XT_FAIL 0000069a
-CSEG PFA_FAIL 0000069b
-CSEG VE_SEARCH_WORDLIST 0000069e
-CSEG XT_SEARCH_WORDLIST 000006a8
-CSEG PFA_SEARCH_WORDLIST 000006a9
-CSEG XT_ISWORD 000006bd
-CSEG XT_TRAVERSEWORDLIST 000006da
-CSEG PFA_SEARCH_WORDLIST1 000006b7
-CSEG XT_NFA2CFA 00000701
-CSEG PFA_ISWORD 000006be
-CSEG XT_NAME2STRING 000006f5
-CSEG PFA_ISWORD3 000006cb
-CSEG VE_TRAVERSEWORDLIST 000006cf
-CSEG PFA_TRAVERSEWORDLIST 000006db
-CSEG PFA_TRAVERSEWORDLIST1 000006dc
-CSEG PFA_TRAVERSEWORDLIST2 000006eb
-CSEG XT_NFA2LFA 00000a16
-CSEG VE_NAME2STRING 000006ed
-CSEG PFA_NAME2STRING 000006f6
-CSEG VE_NFA2CFA 000006fb
-CSEG PFA_NFA2CFA 00000702
-CSEG VE_FINDXT 00000705
-CSEG PFA_FINDXT 0000070c
-CSEG XT_FINDXTA 00000717
-ESEG CFG_ORDERLISTLEN 0000004a
-CSEG PFA_FINDXT1 00000716
-CSEG PFA_FINDXTA 00000718
-CSEG PFA_FINDXTA1 00000724
-CSEG VE_NEWEST 00000725
-CSEG XT_NEWEST 0000072a
-CSEG PFA_NEWEST 0000072b
-DSEG ram_newest 0000018a
-CSEG VE_LATEST 0000072c
-CSEG XT_LATEST 00000731
-CSEG PFA_LATEST 00000732
-DSEG ram_latest 0000018e
-CSEG VE_DOCREATE 00000733
-CSEG XT_DOCREATE 00000739
-CSEG PFA_DOCREATE 0000073a
-CSEG XT_WLSCOPE 00000890
-CSEG XT_HEADER 00000875
-CSEG VE_BACKSLASH 00000744
-CSEG XT_BACKSLASH 00000747
-CSEG PFA_BACKSLASH 00000748
-CSEG VE_LPAREN 0000074d
-CSEG XT_LPAREN 00000750
-CSEG PFA_LPAREN 00000751
-CSEG VE_COMPILE 00000756
-CSEG PFA_COMPILE 0000075d
-CSEG VE_COMMA 00000764
-CSEG PFA_COMMA 00000768
-CSEG XT_DP 00003f12
-CSEG XT_STOREI 00003b73
-CSEG PFA_DP 00003f13
-CSEG VE_BRACKETTICK 0000076f
-CSEG XT_BRACKETTICK 00000773
-CSEG PFA_BRACKETTICK 00000774
-CSEG VE_LITERAL 00000777
-CSEG PFA_LITERAL 0000077e
-CSEG VE_SLITERAL 00000782
-CSEG XT_SLITERAL 00000788
-CSEG PFA_SLITERAL 00000789
-CSEG XT_GMARK 0000078d
-CSEG PFA_GMARK 0000078e
-CSEG XT_GRESOLVE 00000792
-CSEG PFA_GRESOLVE 00000793
-CSEG XT_LMARK 00000798
-CSEG PFA_LMARK 00000799
-CSEG XT_LRESOLVE 0000079b
-CSEG PFA_LRESOLVE 0000079c
-CSEG VE_AHEAD 0000079f
-CSEG XT_AHEAD 000007a4
-CSEG PFA_AHEAD 000007a5
-CSEG VE_IF 000007a9
-CSEG XT_IF 000007ac
-CSEG PFA_IF 000007ad
-CSEG VE_ELSE 000007b1
-CSEG XT_ELSE 000007b5
-CSEG PFA_ELSE 000007b6
-CSEG VE_THEN 000007bc
-CSEG XT_THEN 000007c0
-CSEG PFA_THEN 000007c1
-CSEG VE_BEGIN 000007c3
-CSEG XT_BEGIN 000007c8
-CSEG PFA_BEGIN 000007c9
-CSEG VE_WHILE 000007cb
-CSEG XT_WHILE 000007d0
-CSEG PFA_WHILE 000007d1
-CSEG VE_REPEAT 000007d4
-CSEG XT_REPEAT 000007d9
-CSEG PFA_REPEAT 000007da
-CSEG XT_AGAIN 000007ed
-CSEG VE_UNTIL 000007dd
-CSEG XT_UNTIL 000007e2
-CSEG PFA_UNTIL 000007e3
-CSEG VE_AGAIN 000007e8
-CSEG PFA_AGAIN 000007ee
-CSEG VE_DO 000007f2
-CSEG XT_DO 000007f5
-CSEG PFA_DO 000007f6
-CSEG XT_TO_L 00000850
-CSEG VE_LOOP 000007fc
-CSEG XT_LOOP 00000800
-CSEG PFA_LOOP 00000801
-CSEG XT_ENDLOOP 00000837
-CSEG VE_PLUSLOOP 00000805
-CSEG XT_PLUSLOOP 0000080a
-CSEG PFA_PLUSLOOP 0000080b
-CSEG VE_LEAVE 0000080f
-CSEG XT_LEAVE 00000814
-CSEG PFA_LEAVE 00000815
-CSEG VE_QDO 0000081a
-CSEG XT_QDO 0000081e
-CSEG PFA_QDO 0000081f
-CSEG PFA_QDOCHECK 00000827
-CSEG PFA_QDOCHECK1 0000082e
-CSEG XT_INVERT 000039fd
-CSEG VE_ENDLOOP 00000831
-CSEG PFA_ENDLOOP 00000838
-CSEG LOOP1 00000839
-CSEG XT_L_FROM 00000844
-CSEG LOOP2 00000840
-CSEG VE_L_FROM 00000841
-CSEG PFA_L_FROM 00000845
-CSEG XT_LP 00000863
-CSEG VE_TO_L 0000084d
-CSEG PFA_TO_L 00000851
-CSEG VE_LP0 00000858
-CSEG XT_LP0 0000085c
-CSEG PFA_LP0 0000085d
-ESEG CFG_LP0 00000040
-CSEG VE_LP 00000860
-CSEG PFA_LP 00000864
-DSEG ram_lp 00000190
-CSEG VE_CREATE 00000865
-CSEG XT_CREATE 0000086a
-CSEG PFA_CREATE 0000086b
-CSEG XT_REVEAL 00000899
-CSEG VE_HEADER 00000870
-CSEG PFA_HEADER 00000876
-CSEG PFA_HEADER1 00000887
-CSEG VE_WLSCOPE 0000088a
-CSEG PFA_WLSCOPE 00000891
-ESEG CFG_WLSCOPE 0000003c
-CSEG VE_REVEAL 00000894
-CSEG PFA_REVEAL 0000089a
-CSEG REVEAL1 000008a4
-CSEG XT_STOREE 00003b3b
-CSEG VE_DOES 000008a5
-CSEG XT_DOES 000008aa
-CSEG PFA_DOES 000008ab
-CSEG XT_DODOES 000008bd
-CSEG DO_DODOES 000008b2
-CSEG PFA_DODOES 000008be
-CSEG VE_COLON 000008c6
-CSEG XT_COLON 000008c9
-CSEG PFA_COLON 000008ca
-CSEG XT_COLONNONAME 000008d4
-CSEG VE_COLONNONAME 000008ce
-CSEG PFA_COLONNONAME 000008d5
-CSEG XT_RBRACKET 000008e9
-CSEG VE_SEMICOLON 000008dd
-CSEG XT_SEMICOLON 000008e0
-CSEG PFA_SEMICOLON 000008e1
-CSEG XT_LBRACKET 000008f1
-CSEG VE_RBRACKET 000008e6
-CSEG PFA_RBRACKET 000008ea
-CSEG VE_LBRACKET 000008ee
-CSEG PFA_LBRACKET 000008f2
-CSEG VE_VARIABLE 000008f6
-CSEG XT_VARIABLE 000008fc
-CSEG PFA_VARIABLE 000008fd
-CSEG XT_CONSTANT 00000908
-CSEG XT_ALLOT 00003f2c
-CSEG VE_CONSTANT 00000902
-CSEG PFA_CONSTANT 00000909
-CSEG VE_USER 0000090f
-CSEG XT_USER 00000913
-CSEG PFA_USER 00000914
-CSEG VE_RECURSE 0000091a
-CSEG XT_RECURSE 00000920
-CSEG PFA_RECURSE 00000921
-CSEG VE_IMMEDIATE 00000925
-CSEG XT_IMMEDIATE 0000092c
-CSEG PFA_IMMEDIATE 0000092d
-CSEG XT_GET_CURRENT 000009ce
-CSEG VE_BRACKETCHAR 00000937
-CSEG XT_BRACKETCHAR 0000093c
-CSEG PFA_BRACKETCHAR 0000093d
-CSEG VE_ABORTQUOTE 00000942
-CSEG XT_ABORTQUOTE 00000947
-CSEG PFA_ABORTQUOTE 00000948
-CSEG XT_SQUOTE 00003e8a
-CSEG XT_QABORT 00000959
-CSEG VE_ABORT 0000094c
-CSEG XT_ABORT 00000951
-CSEG PFA_ABORT 00000952
-CSEG VE_QABORT 00000954
-CSEG PFA_QABORT 0000095a
-CSEG QABO1 0000095f
-CSEG VE_GET_STACK 00000961
-CSEG XT_GET_STACK 00000968
-CSEG PFA_N_FETCH_E2 0000097f
-CSEG PFA_N_FETCH_E1 00000975
-CSEG XT_CELLS 00003ec4
-CSEG VE_SET_STACK 00000982
-CSEG XT_SET_STACK 00000989
-CSEG PFA_SET_STACK 0000098a
-CSEG PFA_SET_STACK0 00000991
-CSEG PFA_SET_STACK2 0000099e
-CSEG PFA_SET_STACK1 00000999
-CSEG VE_MAPSTACK 000009a0
-CSEG PFA_MAPSTACK 000009a8
-CSEG PFA_MAPSTACK3 000009c3
-CSEG PFA_MAPSTACK1 000009b2
-CSEG PFA_MAPSTACK2 000009bf
-CSEG VE_GET_CURRENT 000009c6
-CSEG PFA_GET_CURRENT 000009cf
-ESEG CFG_CURRENT 00000046
-CSEG VE_GET_ORDER 000009d3
-CSEG XT_GET_ORDER 000009da
-CSEG PFA_GET_ORDER 000009db
-CSEG VE_CFG_ORDER 000009df
-CSEG XT_CFG_ORDER 000009e6
-CSEG PFA_CFG_ORDER 000009e7
-CSEG VE_COMPARE 000009e8
-CSEG XT_COMPARE 000009ee
-CSEG PFA_COMPARE 000009ef
-CSEG PFA_COMPARE_LOOP 000009fb
-CSEG PFA_COMPARE_NOTEQUAL 00000a09
-CSEG PFA_COMPARE_ENDREACHED2 00000a04
-CSEG PFA_COMPARE_ENDREACHED 00000a05
-CSEG PFA_COMPARE_CHECKLASTCHAR 00000a09
-CSEG PFA_COMPARE_DONE 00000a0b
-CSEG VE_NFA2LFA 00000a10
-CSEG PFA_NFA2LFA 00000a17
-CSEG VE_DOTS 00000a1c
-CSEG XT_DOTS 00000a1f
-CSEG PFA_DOTS 00000a20
-CSEG XT_UDOT 00003e0a
-CSEG PFA_DOTS2 00000a2e
-CSEG PFA_DOTS1 00000a29
-CSEG XT_PICK 00003c84
-CSEG VE_SPIRW 00000a2f
-CSEG XT_SPIRW 00000a34
-CSEG PFA_SPIRW 00000a35
-CSEG do_spirw 00000a39
-CSEG do_spirw1 00000a3a
-CSEG VE_N_SPIR 00000a42
-CSEG XT_N_SPIR 00000a47
-CSEG PFA_N_SPIR 00000a48
-CSEG PFA_N_SPIR_LOOP 00000a4d
-CSEG PFA_N_SPIR_LOOP1 00000a4e
-CSEG VE_N_SPIW 00000a59
-CSEG XT_N_SPIW 00000a5e
-CSEG PFA_N_SPIW 00000a5f
-CSEG PFA_N_SPIW_LOOP 00000a64
-CSEG PFA_N_SPIW_LOOP1 00000a66
-CSEG VE_APPLTURNKEY 00000a70
-CSEG XT_APPLTURNKEY 00000a78
-CSEG PFA_APPLTURNKEY 00000a79
-CSEG XT_INTON 00003c97
-CSEG XT_F_CPU 00003eac
-CSEG VE_SET_CURRENT 00000a8a
-CSEG XT_SET_CURRENT 00000a92
-CSEG PFA_SET_CURRENT 00000a93
-CSEG VE_WORDLIST 00000a97
-CSEG XT_WORDLIST 00000a9d
-CSEG PFA_WORDLIST 00000a9e
-CSEG XT_EHERE 00003f1b
-CSEG PFA_EHERE 00003f1c
-CSEG VE_FORTHWORDLIST 00000aa7
-CSEG XT_FORTHWORDLIST 00000ab0
-CSEG PFA_FORTHWORDLIST 00000ab1
-ESEG CFG_FORTHWORDLIST 00000048
-CSEG VE_SET_ORDER 00000ab2
-CSEG XT_SET_ORDER 00000ab9
-CSEG PFA_SET_ORDER 00000aba
-CSEG VE_SET_RECOGNIZERS 00000abe
-CSEG XT_SET_RECOGNIZERS 00000ac8
-CSEG PFA_SET_RECOGNIZERS 00000ac9
-ESEG CFG_RECOGNIZERLISTLEN 0000005c
-CSEG VE_GET_RECOGNIZERS 00000acd
-CSEG XT_GET_RECOGNIZERS 00000ad7
-CSEG PFA_GET_RECOGNIZERS 00000ad8
-CSEG VE_CODE 00000adc
-CSEG XT_CODE 00000ae0
-CSEG PFA_CODE 00000ae1
-CSEG VE_ENDCODE 00000ae7
-CSEG XT_ENDCODE 00000aed
-CSEG PFA_ENDCODE 00000aee
-CSEG VE_MARKER 00000af3
-CSEG XT_MARKER 00000af9
-CSEG PFA_MARKER 00000afa
-ESEG EE_MARKER 00000068
-CSEG VE_POSTPONE 00000afd
-CSEG XT_POSTPONE 00000b03
-CSEG PFA_POSTPONE 00000b04
-CSEG VE_2R_FETCH 00000b12
-CSEG XT_2R_FETCH 00000b16
-CSEG PFA_2R_FETCH 00000b17
-SET DPSTART 00000b26
-CSEG DO_INTERRUPT 00003814
-CSEG DO_EXECUTE 0000380d
-CSEG XT_ISREXEC 00003cc0
-CSEG VE_EXIT 0000381c
-CSEG PFA_EXIT 00003821
-CSEG VE_EXECUTE 00003824
-CSEG PFA_EXECUTE 0000382b
-CSEG PFA_DOBRANCH 00003830
-CSEG PFA_DOCONDBRANCH 00003837
-CSEG PFA_DOLITERAL 0000383e
-CSEG XT_DOVARIABLE 00003847
-CSEG XT_DOCONSTANT 00003851
-CSEG XT_DOUSER 00003857
-CSEG VE_DOVALUE 00003863
-CSEG XT_DOVALUE 00003869
-CSEG PFA_DOVALUE 0000386a
-CSEG VE_FETCH 00003876
-CSEG PFA_FETCH 0000387a
-CSEG PFA_FETCHRAM 0000387a
-CSEG VE_STORE 0000387e
-CSEG PFA_STORE 00003882
-CSEG PFA_STORERAM 00003882
-CSEG VE_CSTORE 0000388a
-CSEG PFA_CSTORE 0000388e
-CSEG VE_CFETCH 00003895
-CSEG PFA_CFETCH 00003899
-CSEG VE_FETCHU 0000389d
-CSEG XT_FETCHU 000038a0
-CSEG PFA_FETCHU 000038a1
-CSEG VE_STOREU 000038a5
-CSEG XT_STOREU 000038a8
-CSEG PFA_STOREU 000038a9
-CSEG VE_DUP 000038ad
-CSEG PFA_DUP 000038b2
-CSEG VE_QDUP 000038b5
-CSEG PFA_QDUP 000038ba
-CSEG PFA_QDUP1 000038bf
-CSEG VE_SWAP 000038c0
-CSEG PFA_SWAP 000038c5
-CSEG VE_OVER 000038cb
-CSEG PFA_OVER 000038d0
-CSEG VE_DROP 000038d5
-CSEG PFA_DROP 000038da
-CSEG VE_ROT 000038dd
-CSEG PFA_ROT 000038e2
-CSEG VE_NIP 000038ec
-CSEG PFA_NIP 000038f1
-CSEG VE_R_FROM 000038f3
-CSEG PFA_R_FROM 000038f7
-CSEG VE_TO_R 000038fc
-CSEG PFA_TO_R 00003900
-CSEG VE_R_FETCH 00003905
-CSEG PFA_R_FETCH 00003909
-CSEG VE_NOTEQUAL 00003910
-CSEG PFA_NOTEQUAL 00003914
-CSEG VE_ZEROEQUAL 00003917
-CSEG PFA_ZEROEQUAL 0000391b
-CSEG PFA_ZERO1 00003957
-CSEG PFA_TRUE1 0000394e
-CSEG VE_ZEROLESS 0000391e
-CSEG PFA_ZEROLESS 00003922
-CSEG VE_GREATERZERO 00003925
-CSEG PFA_GREATERZERO 00003929
-CSEG VE_DGREATERZERO 0000392e
-CSEG XT_DGREATERZERO 00003932
-CSEG PFA_DGREATERZERO 00003933
-CSEG VE_DXT_ZEROLESS 0000393c
-CSEG XT_DXT_ZEROLESS 00003940
-CSEG PFA_DXT_ZEROLESS 00003941
-CSEG VE_TRUE 00003947
-CSEG PFA_TRUE 0000394c
-CSEG VE_ZERO 00003951
-CSEG PFA_ZERO 00003955
-CSEG VE_ULESS 00003959
-CSEG PFA_ULESS 0000395d
-CSEG VE_UGREATER 00003964
-CSEG PFA_UGREATER 00003968
-CSEG VE_LESS 0000396b
-CSEG PFA_LESS 0000396f
-CSEG PFA_LESSDONE 00003973
-CSEG VE_GREATER 00003975
-CSEG PFA_GREATER 00003979
-CSEG PFA_GREATERDONE 0000397d
-CSEG VE_LOG2 00003980
-CSEG XT_LOG2 00003984
-CSEG PFA_LOG2 00003985
-CSEG PFA_LOG2_1 00003988
-CSEG PFA_LOG2_2 0000398e
-CSEG VE_MINUS 00003990
-CSEG PFA_MINUS 00003994
-CSEG VE_PLUS 0000399a
-CSEG PFA_PLUS 0000399e
-CSEG VE_MSTAR 000039a3
-CSEG PFA_MSTAR 000039a7
-CSEG VE_UMSLASHMOD 000039bd
-CSEG PFA_UMSLASHMOD 000039c3
-CSEG PFA_UMSLASHMODmod 000039c8
-CSEG PFA_UMSLASHMODmod_loop 000039c9
-CSEG PFA_UMSLASHMODmod_loop_control 000039d6
-CSEG PFA_UMSLASHMODmod_subtract 000039d3
-CSEG PFA_UMSLASHMODmod_done 000039d8
-CSEG VE_UMSTAR 000039dc
-CSEG PFA_UMSTAR 000039e1
-CSEG VE_INVERT 000039f8
-CSEG PFA_INVERT 000039fe
-CSEG VE_2SLASH 00003a01
-CSEG PFA_2SLASH 00003a05
-CSEG VE_2STAR 00003a08
-CSEG PFA_2STAR 00003a0c
-CSEG VE_AND 00003a0f
-CSEG PFA_AND 00003a14
-CSEG VE_OR 00003a19
-CSEG PFA_OR 00003a1d
-CSEG VE_XOR 00003a22
-CSEG XT_XOR 00003a26
-CSEG PFA_XOR 00003a27
-CSEG VE_1PLUS 00003a2c
-CSEG PFA_1PLUS 00003a30
-CSEG VE_1MINUS 00003a32
-CSEG PFA_1MINUS 00003a36
-CSEG VE_QNEGATE 00003a38
-CSEG XT_QNEGATE 00003a3e
-CSEG PFA_QNEGATE 00003a3f
-CSEG QNEG1 00003a43
-CSEG VE_LSHIFT 00003a44
-CSEG XT_LSHIFT 00003a49
-CSEG PFA_LSHIFT 00003a4a
-CSEG PFA_LSHIFT1 00003a4d
-CSEG PFA_LSHIFT2 00003a52
-CSEG VE_RSHIFT 00003a53
-CSEG XT_RSHIFT 00003a58
-CSEG PFA_RSHIFT 00003a59
-CSEG PFA_RSHIFT1 00003a5c
-CSEG PFA_RSHIFT2 00003a61
-CSEG VE_PLUSSTORE 00003a62
-CSEG PFA_PLUSSTORE 00003a66
-CSEG VE_RP_FETCH 00003a72
-CSEG PFA_RP_FETCH 00003a77
-CSEG VE_RP_STORE 00003a7c
-CSEG XT_RP_STORE 00003a80
-CSEG PFA_RP_STORE 00003a81
-CSEG VE_SP_FETCH 00003a89
-CSEG PFA_SP_FETCH 00003a8e
-CSEG VE_SP_STORE 00003a92
-CSEG XT_SP_STORE 00003a96
-CSEG PFA_SP_STORE 00003a97
-CSEG PFA_DODO 00003a9c
-CSEG PFA_DODO1 00003a9e
-CSEG VE_I 00003aa9
-CSEG PFA_I 00003aad
-CSEG PFA_DOPLUSLOOP 00003abb
-CSEG PFA_DOPLUSLOOP_LEAVE 00003ac5
-CSEG PFA_DOPLUSLOOP_NEXT 00003ac2
-CSEG PFA_DOLOOP 00003aca
-CSEG VE_UNLOOP 00003acf
-CSEG PFA_UNLOOP 00003ad5
-CSEG VE_CMOVE_G 00003ada
-CSEG XT_CMOVE_G 00003adf
-CSEG PFA_CMOVE_G 00003ae0
-CSEG PFA_CMOVE_G1 00003af1
-CSEG PFA_CMOVE_G2 00003aed
-CSEG VE_BYTESWAP 00003af6
-CSEG PFA_BYTESWAP 00003afa
-CSEG VE_UP_FETCH 00003afe
-CSEG PFA_UP_FETCH 00003b03
-CSEG VE_UP_STORE 00003b07
-CSEG XT_UP_STORE 00003b0b
-CSEG PFA_UP_STORE 00003b0c
-CSEG VE_1MS 00003b10
-CSEG XT_1MS 00003b14
-CSEG PFA_1MS 00003b15
-CSEG VE_2TO_R 00003b1a
-CSEG PFA_2TO_R 00003b1f
-CSEG VE_2R_FROM 00003b29
-CSEG PFA_2R_FROM 00003b2e
-CSEG VE_STOREE 00003b38
-CSEG PFA_STOREE 00003b3c
-CSEG PFA_STOREE0 00003b3c
-CSEG PFA_FETCHE2 00003b6a
-CSEG PFA_STOREE3 00003b46
-CSEG PFA_STOREE1 00003b51
-CSEG PFA_STOREE4 00003b4d
-CSEG PFA_STOREE2 00003b53
-CSEG VE_FETCHE 00003b5c
-CSEG PFA_FETCHE 00003b60
-CSEG PFA_FETCHE1 00003b60
-CSEG VE_STOREI 00003b70
-CSEG PFA_STOREI 00003b74
-ESEG EE_STOREI 00000066
-CSEG VE_DO_STOREI_NRWW 00003b77
-CSEG XT_DO_STOREI 00003b7e
-CSEG PFA_DO_STOREI_NRWW 00003b7f
-CSEG DO_STOREI_atmega 00003b93
-CSEG pageload 00003ba4
-CSEG DO_STOREI_writepage 00003b9d
-CSEG dospm 00003bbd
-EQU pagemask ffffffc0
-CSEG pageload_loop 00003baa
-CSEG pageload_newdata 00003bb5
-CSEG pageload_cont 00003bb7
-CSEG pageload_done 00003bbc
-CSEG dospm_wait_ee 00003bbd
-CSEG dospm_wait_spm 00003bbf
-CSEG VE_FETCHI 00003bc8
-CSEG PFA_FETCHI 00003bcc
-CSEG VE_N_TO_R 00003bd2
-CSEG XT_N_TO_R 00003bd6
-CSEG PFA_N_TO_R 00003bd7
-CSEG PFA_N_TO_R1 00003bd9
-CSEG VE_N_R_FROM 00003be4
-CSEG XT_N_R_FROM 00003be8
-CSEG PFA_N_R_FROM 00003be9
-CSEG PFA_N_R_FROM1 00003bee
-CSEG VE_D2STAR 00003bf6
-CSEG XT_D2STAR 00003bfa
-CSEG PFA_D2STAR 00003bfb
-CSEG VE_D2SLASH 00003c04
-CSEG XT_D2SLASH 00003c08
-CSEG PFA_D2SLASH 00003c09
-CSEG VE_DPLUS 00003c12
-CSEG PFA_DPLUS 00003c16
-CSEG VE_DMINUS 00003c23
-CSEG XT_DMINUS 00003c26
-CSEG PFA_DMINUS 00003c27
-CSEG VE_DINVERT 00003c35
-CSEG PFA_DINVERT 00003c3c
-CSEG VE_SLASHMOD 00003c45
-CSEG XT_SLASHMOD 00003c49
-CSEG PFA_SLASHMOD 00003c4a
-CSEG PFA_SLASHMOD_1 00003c55
-CSEG PFA_SLASHMOD_2 00003c5b
-CSEG PFA_SLASHMOD_3 00003c5e
-CSEG PFA_SLASHMOD_5 00003c69
-CSEG PFA_SLASHMOD_4 00003c68
-CSEG PFA_SLASHMODmod_done 00003c74
-CSEG PFA_SLASHMOD_6 00003c72
-CSEG VE_ABS 00003c78
-CSEG XT_ABS 00003c7c
-CSEG PFA_ABS 00003c7d
-CSEG VE_PICK 00003c80
-CSEG PFA_PICK 00003c85
-CSEG VE_CELLPLUS 00003c8b
-CSEG PFA_CELLPLUS 00003c91
-CSEG VE_INTON 00003c93
-CSEG PFA_INTON 00003c98
-CSEG VE_INTOFF 00003c9a
-CSEG XT_INTOFF 00003c9e
-CSEG PFA_INTOFF 00003c9f
-CSEG VE_INTSTORE 00003ca1
-CSEG PFA_INTSTORE 00003ca6
-CSEG VE_INTFETCH 00003cab
-CSEG XT_INTFETCH 00003caf
-CSEG PFA_INTFETCH 00003cb0
-CSEG VE_INTTRAP 00003cb5
-CSEG XT_INTTRAP 00003cbb
-CSEG PFA_INTTRAP 00003cbc
-CSEG PFA_ISREXEC 00003cc1
-CSEG XT_ISREND 00003cc5
-CSEG PFA_ISREND 00003cc6
-CSEG PFA_ISREND1 00003cc8
-CSEG XT_DEFAULT_PROMPTOK 00003cc9
-CSEG PFA_DEFAULT_PROMPTOK 00003cca
-CSEG VE_PROMPTOK 00003cd0
-CSEG XT_PROMPTOK 00003cd4
-CSEG PFA_PROMPTOK 00003cd5
-CSEG XT_DEFAULT_PROMPTREADY 00003cd8
-CSEG PFA_DEFAULT_PROMPTREADY 00003cd9
-CSEG VE_PROMPTREADY 00003cdf
-CSEG XT_PROMPTREADY 00003ce4
-CSEG PFA_PROMPTREADY 00003ce5
-CSEG XT_DEFAULT_PROMPTERROR 00003ce8
-CSEG PFA_DEFAULT_PROMPTERROR 00003ce9
-CSEG VE_PROMPTERROR 00003cfa
-CSEG XT_PROMPTERROR 00003cff
-CSEG PFA_PROMPTERROR 00003d00
-CSEG VE_QUIT 00003d03
-CSEG XT_QUIT 00003d07
-CSEG PFA_QUIT 00003d08
-CSEG PFA_QUIT2 00003d10
-CSEG PFA_QUIT4 00003d16
-CSEG PFA_QUIT3 00003d28
-CSEG XT_CATCH 00003d70
-CSEG PFA_QUIT5 00003d26
-CSEG VE_PAUSE 00003d2b
-CSEG PFA_PAUSE 00003d31
-DSEG ram_pause 00000192
-CSEG XT_RDEFERFETCH 00003db4
-CSEG XT_RDEFERSTORE 00003dbe
-CSEG VE_COLD 00003d34
-CSEG clearloop 00003d40
-DSEG ram_user1 00000194
-CSEG PFA_WARM 00003d5a
-CSEG VE_WARM 00003d55
-CSEG XT_WARM 00003d59
-CSEG XT_DEFERSTORE 00003ddf
-CSEG XT_TURNKEY 00003f5c
-CSEG VE_HANDLER 00003d63
-CSEG XT_HANDLER 00003d69
-CSEG PFA_HANDLER 00003d6a
-CSEG VE_CATCH 00003d6b
-CSEG PFA_CATCH 00003d71
-CSEG VE_THROW 00003d81
-CSEG PFA_THROW 00003d87
-CSEG PFA_THROW1 00003d8d
-CSEG VE_EDEFERFETCH 00003d9a
-CSEG PFA_EDEFERFETCH 00003da1
-CSEG VE_EDEFERSTORE 00003da4
-CSEG PFA_EDEFERSTORE 00003dab
-CSEG VE_RDEFERFETCH 00003dae
-CSEG PFA_RDEFERFETCH 00003db5
-CSEG VE_RDEFERSTORE 00003db8
-CSEG PFA_RDEFERSTORE 00003dbf
-CSEG VE_UDEFERFETCH 00003dc2
-CSEG PFA_UDEFERFETCH 00003dc9
-CSEG VE_UDEFERSTORE 00003dce
-CSEG PFA_UDEFERSTORE 00003dd5
-CSEG VE_DEFERSTORE 00003dda
-CSEG PFA_DEFERSTORE 00003de0
-CSEG VE_DEFERFETCH 00003de7
-CSEG XT_DEFERFETCH 00003dec
-CSEG PFA_DEFERFETCH 00003ded
-CSEG VE_DODEFER 00003df3
-CSEG XT_DODEFER 00003df9
-CSEG PFA_DODEFER 00003dfa
-CSEG VE_UDOT 00003e07
-CSEG PFA_UDOT 00003e0b
-CSEG VE_UDOTR 00003e0e
-CSEG XT_UDOTR 00003e12
-CSEG PFA_UDOTR 00003e13
-CSEG VE_USLASHMOD 00003e17
-CSEG XT_USLASHMOD 00003e1c
-CSEG PFA_USLASHMOD 00003e1d
-CSEG VE_NEGATE 00003e22
-CSEG PFA_NEGATE 00003e28
-CSEG VE_SLASH 00003e2b
-CSEG XT_SLASH 00003e2e
-CSEG PFA_SLASH 00003e2f
-CSEG VE_MOD 00003e32
-CSEG XT_MOD 00003e36
-CSEG PFA_MOD 00003e37
-CSEG VE_MIN 00003e3a
-CSEG XT_MIN 00003e3e
-CSEG PFA_MIN 00003e3f
-CSEG PFA_MIN1 00003e44
-CSEG VE_MAX 00003e46
-CSEG XT_MAX 00003e4a
-CSEG PFA_MAX 00003e4b
-CSEG PFA_MAX1 00003e50
-CSEG VE_WITHIN 00003e52
-CSEG PFA_WITHIN 00003e58
-CSEG VE_SHOWWORDLIST 00003e5f
-CSEG XT_SHOWWORDLIST 00003e68
-CSEG PFA_SHOWWORDLIST 00003e69
-CSEG XT_SHOWWORD 00003e6e
-CSEG PFA_SHOWWORD 00003e6f
-CSEG VE_WORDS 00003e74
-CSEG XT_WORDS 00003e79
-CSEG PFA_WORDS 00003e7a
-CSEG VE_DOTSTRING 00003e7f
-CSEG XT_DOTSTRING 00003e82
-CSEG PFA_DOTSTRING 00003e83
-CSEG VE_SQUOTE 00003e87
-CSEG PFA_SQUOTE 00003e8b
-CSEG PFA_SQUOTE1 00003e93
-CSEG VE_FILL 00003e94
-CSEG PFA_FILL 00003e99
-CSEG PFA_FILL2 00003ea5
-CSEG PFA_FILL1 00003ea0
-CSEG VE_F_CPU 00003ea7
-CSEG PFA_F_CPU 00003ead
-CSEG VE_STATE 00003eb2
-CSEG PFA_STATE 00003eb8
-DSEG ram_state 000001c0
-CSEG VE_BASE 00003eb9
-CSEG PFA_BASE 00003ebe
-CSEG VE_CELLS 00003ebf
-CSEG VE_2DUP 00003ec5
-CSEG PFA_2DUP 00003eca
-CSEG VE_2DROP 00003ecd
-CSEG PFA_2DROP 00003ed3
-CSEG VE_TUCK 00003ed6
-CSEG PFA_TUCK 00003edb
-CSEG VE_TO_IN 00003ede
-CSEG PFA_TO_IN 00003ee3
-CSEG VE_PAD 00003ee4
-CSEG PFA_PAD 00003ee9
-CSEG VE_EMIT 00003eee
-CSEG PFA_EMIT 00003ef3
-CSEG VE_EMITQ 00003ef6
-CSEG XT_EMITQ 00003efb
-CSEG PFA_EMITQ 00003efc
-CSEG VE_KEY 00003eff
-CSEG PFA_KEY 00003f04
-CSEG VE_KEYQ 00003f07
-CSEG XT_KEYQ 00003f0b
-CSEG PFA_KEYQ 00003f0c
-CSEG VE_DP 00003f0f
-ESEG CFG_DP 00000036
-CSEG VE_EHERE 00003f16
-ESEG EE_EHERE 0000003a
-CSEG VE_HERE 00003f1f
-CSEG PFA_HERE 00003f24
-ESEG EE_HERE 00000038
-CSEG VE_ALLOT 00003f27
-CSEG PFA_ALLOT 00003f2d
-CSEG VE_BIN 00003f32
-CSEG XT_BIN 00003f36
-CSEG PFA_BIN 00003f37
-CSEG VE_DECIMAL 00003f3b
-CSEG PFA_DECIMAL 00003f42
-CSEG VE_HEX 00003f47
-CSEG XT_HEX 00003f4b
-CSEG PFA_HEX 00003f4c
-CSEG VE_BL 00003f51
-CSEG PFA_BL 00003f55
-CSEG VE_TURNKEY 00003f56
-CSEG PFA_TURNKEY 00003f5d
-ESEG CFG_TURNKEY 00000042
-CSEG VE_TOUPPER 00003f60
-CSEG PFA_TOUPPER 00003f67
-CSEG PFA_TOUPPER0 00003f72
-CSEG VE_TOLOWER 00003f73
-CSEG XT_TOLOWER 00003f79
-CSEG PFA_TOLOWER 00003f7a
-CSEG PFA_TOLOWER0 00003f85
-CSEG VE_QSTACK 00003f86
-CSEG PFA_QSTACK 00003f8c
-CSEG PFA_QSTACK1 00003f93
-CSEG VE_BOUNDS 00003f94
-CSEG PFA_BOUNDS 00003f9a
-CSEG VE_CR 00003f9e
-CSEG PFA_CR 00003fa2
-CSEG VE_SPACE 00003fa9
-CSEG PFA_SPACE 00003faf
-CSEG VE_SPACES 00003fb2
-CSEG PFA_SPACES 00003fb8
-CSEG SPCS1 00003fba
-CSEG SPCS2 00003fc1
-CSEG VE_S2D 00003fc3
-CSEG PFA_S2D 00003fc8
-CSEG VE_TO_BODY 00003fcb
-CSEG VE_2LITERAL 00003fd1
-CSEG PFA_2LITERAL 00003fd8
-CSEG VE_EQUAL 00003fdc
-CSEG PFA_EQUAL 00003fe0
-CSEG VE_ONE 00003fe3
-CSEG PFA_ONE 00003fe7
-CSEG VE_TWO 00003fe8
-CSEG PFA_TWO 00003fec
-CSEG VE_MINUSONE 00003fed
-CSEG XT_MINUSONE 00003ff0
-CSEG PFA_MINUSONE 00003ff1
-SET flashlast 00003ff2
-DSEG HERESTART 000001c2
-ESEG EHERESTART 0000008e
-ESEG CFG_ORDERLIST 0000004c
-ESEG CFG_RECOGNIZERLIST 0000005e
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/eval-pollin/p328-16.xml b/amforth-6.5/appl/eval-pollin/p328-16.xml
deleted file mode 100644
index 1d8cdb5..0000000
--- a/amforth-6.5/appl/eval-pollin/p328-16.xml
+++ /dev/null
@@ -1,36 +0,0 @@
-<project name="pollins-328-16" basedir="." default="Help">
- <target name="p328-16.asm">
- <copy tofile="p328-16.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="16000000"/>
- <filter token="USART" value="_0"/>
- </filterset>
- </copy>
- </target>
-
- <target name="p328-16.hex" depends="p328-16.asm" description="Hexfiles for p328-16">
- <avrasm2 projectname="p328-16" mcu="atmega328p"/>
- <delete file="p328-16.asm"/>
- </target>
-
- <target name="p328-16" depends="p328-16.hex" description="Atmega328 @ 16 MHz">
- <echo>Uploading Hexfiles for p328-16</echo>
- <avrdude
- type="stk200"
- mcu="atmega328p"
- flashfile="p328-16.hex"
- eepromfile="p328-16.eep.hex"
- />
- </target>
- <target name="p328-16.fuses" description="Set fuses for P16-8">
- <echo>Writing fuses</echo>
- <avrdude-3fuses
- type="${programmer}"
- mcu="${mcu}"
- efuse="0xff"
- hfuse="0xd9"
- lfuse="0xc6"
- />
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/p644-16.eep.hex b/amforth-6.5/appl/eval-pollin/p644-16.eep.hex
deleted file mode 100644
index f9365bf..0000000
--- a/amforth-6.5/appl/eval-pollin/p644-16.eep.hex
+++ /dev/null
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diff --git a/amforth-6.5/appl/eval-pollin/p644-16.hex b/amforth-6.5/appl/eval-pollin/p644-16.hex
deleted file mode 100644
index 3da58b1..0000000
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+++ /dev/null
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diff --git a/amforth-6.5/appl/eval-pollin/p644-16.lst b/amforth-6.5/appl/eval-pollin/p644-16.lst
deleted file mode 100644
index 2c8872a..0000000
--- a/amforth-6.5/appl/eval-pollin/p644-16.lst
+++ /dev/null
@@ -1,10444 +0,0 @@
-
-AVRASM ver. 2.1.52 p644-16.asm Sun Apr 30 20:10:15 2017
-
-p644-16.asm(5): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega644\device.asm'
-../../avr8/devices/atmega644\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m644def.inc'
-p644-16.asm(14): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-p644-16.asm(19): Including file '../../avr8\drivers/1wire.asm'
-p644-16.asm(21): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(9): Including file '../../avr8\dict/appl_8k.inc'
-../../avr8\dict/appl_8k.inc(1): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(3): Including file '../../common\words/dot-s.asm'
-dict_appl.inc(4): Including file '../../avr8\words/spirw.asm'
-dict_appl.inc(5): Including file '../../avr8\words/n-spi.asm'
-dict_appl.inc(6): Including file 'words/applturnkey.asm'
-dict_appl.inc(7): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(8): Including file '../../avr8\words/2r_fetch.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(102): Including file '../../avr8\dict/core_8k.inc'
-../../avr8\dict/core_8k.inc(2): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_8k.inc(3): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_8k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_8k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_8k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_8k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_8k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_8k.inc(10): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_8k.inc(11): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_8k.inc(13): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_8k.inc(14): Including file '../../common\words/words.asm'
-../../avr8\dict/core_8k.inc(15): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_8k.inc(17): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_8k.inc(18): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_8k.inc(19): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_8k.inc(21): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_8k.inc(23): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/core_8k.inc(24): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/core_8k.inc(25): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/core_8k.inc(26): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/core_8k.inc(27): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/core_8k.inc(28): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/core_8k.inc(29): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/core_8k.inc(30): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/core_8k.inc(31): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/core_8k.inc(33): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_8k.inc(34): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_8k.inc(35): Including file '../../common\words/base.asm'
-../../avr8\dict/core_8k.inc(37): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_8k.inc(38): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_8k.inc(40): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_8k.inc(41): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_8k.inc(43): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_8k.inc(45): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_8k.inc(46): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_8k.inc(47): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_8k.inc(48): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_8k.inc(49): Including file '../../common\words/key.asm'
-../../avr8\dict/core_8k.inc(50): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_8k.inc(52): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_8k.inc(53): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_8k.inc(54): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_8k.inc(55): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_8k.inc(57): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_8k.inc(58): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_8k.inc(59): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_8k.inc(60): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_8k.inc(62): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_8k.inc(64): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_8k.inc(65): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_8k.inc(66): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_8k.inc(67): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_8k.inc(68): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_8k.inc(69): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_8k.inc(70): Including file '../../common\words/min.asm'
-../../avr8\dict/core_8k.inc(71): Including file '../../common\words/max.asm'
-../../avr8\dict/core_8k.inc(72): Including file '../../common\words/within.asm'
-../../avr8\dict/core_8k.inc(74): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_8k.inc(75): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_8k.inc(77): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/core_8k.inc(78): Including file '../../common\words/hold.asm'
-../../avr8\dict/core_8k.inc(79): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/core_8k.inc(80): Including file '../../common\words/sharp.asm'
-../../avr8\dict/core_8k.inc(81): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/core_8k.inc(82): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/core_8k.inc(83): Including file '../../common\words/sign.asm'
-../../avr8\dict/core_8k.inc(84): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/core_8k.inc(85): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/core_8k.inc(86): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/core_8k.inc(87): Including file '../../common\words/dot.asm'
-../../avr8\dict/core_8k.inc(88): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/core_8k.inc(89): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/core_8k.inc(90): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/core_8k.inc(91): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/core_8k.inc(93): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/core_8k.inc(94): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/core_8k.inc(95): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/core_8k.inc(96): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/core_8k.inc(97): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_8k.inc(98): Including file '../../common\words/space.asm'
-../../avr8\dict/core_8k.inc(99): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_8k.inc(100): Including file '../../common\words/type.asm'
-../../avr8\dict/core_8k.inc(101): Including file '../../common\words/tick.asm'
-../../avr8\dict/core_8k.inc(103): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_8k.inc(104): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_8k.inc(105): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_8k.inc(107): Including file '../../common\words/cskip.asm'
-../../avr8\dict/core_8k.inc(108): Including file '../../common\words/cscan.asm'
-../../avr8\dict/core_8k.inc(109): Including file '../../common\words/accept.asm'
-../../avr8\dict/core_8k.inc(110): Including file '../../common\words/refill.asm'
-../../avr8\dict/core_8k.inc(111): Including file '../../common\words/char.asm'
-../../avr8\dict/core_8k.inc(112): Including file '../../common\words/number.asm'
-../../avr8\dict/core_8k.inc(113): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/core_8k.inc(114): Including file '../../common\words/set-base.asm'
-../../avr8\dict/core_8k.inc(115): Including file '../../common\words/to-number.asm'
-../../avr8\dict/core_8k.inc(116): Including file '../../common\words/parse.asm'
-../../avr8\dict/core_8k.inc(117): Including file '../../common\words/source.asm'
-../../avr8\dict/core_8k.inc(118): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/core_8k.inc(119): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/core_8k.inc(120): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/core_8k.inc(122): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_8k.inc(123): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_8k.inc(124): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_8k.inc(126): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_8k.inc(127): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_8k.inc(128): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_8k.inc(129): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_8k.inc(131): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/core_8k.inc(132): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/core_8k.inc(133): Including file '../../common\words/depth.asm'
-../../avr8\dict/core_8k.inc(134): Including file '../../common\words/interpret.asm'
-../../avr8\dict/core_8k.inc(135): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/core_8k.inc(136): Including file '../../common\words/recognize.asm'
-../../avr8\dict/core_8k.inc(137): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/core_8k.inc(138): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/core_8k.inc(139): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/core_8k.inc(141): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_8k.inc(142): Including file '../../common\words/ver.asm'
-../../avr8\dict/core_8k.inc(144): Including file '../../common\words/noop.asm'
-../../avr8\dict/core_8k.inc(145): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/core_8k.inc(147): Including file '../../common\words/to.asm'
-../../avr8\dict/core_8k.inc(148): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/core_8k.inc(150): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_8k.inc(151): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_8k.inc(152): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_8k.inc(153): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_8k.inc(154): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_8k.inc(155): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_8k.inc(156): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_8k.inc(157): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_8k.inc(158): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_8k.inc(160): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/core_8k.inc(161): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/core_8k.inc(162): Including file '../../common\words/name2string.asm'
-../../avr8\dict/core_8k.inc(163): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/core_8k.inc(164): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/core_8k.inc(166): Including file '../../common\words/star.asm'
-../../avr8\dict/core_8k.inc(167): Including file '../../avr8\words/j.asm'
-../../avr8\dict/core_8k.inc(169): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/core_8k.inc(170): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/core_8k.inc(171): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/core_8k.inc(172): Including file '../../common\words/2swap.asm'
-../../avr8\dict/core_8k.inc(174): Including file '../../common\words/tib.asm'
-../../avr8\dict/core_8k.inc(176): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/core_8k.inc(177): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/core_8k.inc(178): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_8k.inc(179): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_8k.inc(180): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ; file see ../template/template.asm. You may want to
- ; copy that file to this one and edit it afterwards.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
- .endmacro
- .macro writeflashcell
- lsl zl
- rol zh
- .endmacro
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_USART0 = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_WATCHDOG = 0
- .set WANT_JTAG = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_EEPROM = 0
- .set WANT_TWI = 0
- .set WANT_SPI = 0
- .set WANT_CPU = 0
- .equ intvecsize = 2 ; please verify; flash size: 65536 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d12a rcall isr ; External Interrupt Request 0
- .org 4
-000004 d128 rcall isr ; External Interrupt Request 1
- .org 6
-000006 d126 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d124 rcall isr ; Pin Change Interrupt Request 0
- .org 10
-00000a d122 rcall isr ; Pin Change Interrupt Request 1
- .org 12
-00000c d120 rcall isr ; Pin Change Interrupt Request 2
- .org 14
-00000e d11e rcall isr ; Pin Change Interrupt Request 3
- .org 16
-000010 d11c rcall isr ; Watchdog Time-out Interrupt
- .org 18
-000012 d11a rcall isr ; Timer/Counter2 Compare Match A
- .org 20
-000014 d118 rcall isr ; Timer/Counter2 Compare Match B
- .org 22
-000016 d116 rcall isr ; Timer/Counter2 Overflow
- .org 24
-000018 d114 rcall isr ; Timer/Counter1 Capture Event
- .org 26
-00001a d112 rcall isr ; Timer/Counter1 Compare Match A
- .org 28
-00001c d110 rcall isr ; Timer/Counter1 Compare Match B
- .org 30
-00001e d10e rcall isr ; Timer/Counter1 Overflow
- .org 32
-000020 d10c rcall isr ; Timer/Counter0 Compare Match A
- .org 34
-000022 d10a rcall isr ; Timer/Counter0 Compare Match B
- .org 36
-000024 d108 rcall isr ; Timer/Counter0 Overflow
- .org 38
-000026 d106 rcall isr ; SPI Serial Transfer Complete
- .org 40
-000028 d104 rcall isr ; USART0, Rx Complete
- .org 42
-00002a d102 rcall isr ; USART0 Data register Empty
- .org 44
-00002c d100 rcall isr ; USART0, Tx Complete
- .org 46
-00002e d0fe rcall isr ; Analog Comparator
- .org 48
-000030 d0fc rcall isr ; ADC Conversion Complete
- .org 50
-000032 d0fa rcall isr ; EEPROM Ready
- .org 52
-000034 d0f8 rcall isr ; 2-wire Serial Interface
- .org 54
-000036 d0f6 rcall isr ; Store Program Memory Read
- .equ INTVECTORS = 28
- .nooverlap
-
- ; compatability layer (maybe empty)
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000037 1000 .dw 4096
- mcu_eepromsize:
-000038 0800 .dw 2048
- mcu_maxdp:
-000039 e000 .dw 57344
- mcu_numints:
-00003a 001c .dw 28
- mcu_name:
-00003b 0009 .dw 9
-00003c 5441
-00003d 656d
-00003e 6167
-00003f 3436
-000040 0034 .db "ATmega644",0
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- .set AMFORTH_RO_SEG = NRWW_START_ADDR+1
-
- ; cpu clock in hertz
- .equ F_CPU = 16000000
- .set BAUD_MAXERROR = 30
- .equ TIMER_INT = OVF2addr
-
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .equ URXCaddr = URXC0addr
- .equ UDREaddr = UDRE0addr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-000041 ff07 .dw $ff07
-000042 723e
-000043 2d78
-000044 7562
-000045 0066 .db ">rx-buf",0
-000046 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000047 0048 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000048 2f08 mov temp0, tosl
-000049 9110 0110 lds temp1, usart_rx_in
-00004b e0e0 ldi zl, low(usart_rx_data)
-00004c e0f1 ldi zh, high(usart_rx_data)
-00004d 0fe1 add zl, temp1
-00004e 1df3 adc zh, zeroh
-00004f 8300 st Z, temp0
-000050 9513 inc temp1
-000051 701f andi temp1,usart_rx_mask
-000052 9310 0110 sts usart_rx_in, temp1
-000054 9189
-000055 9199 loadtos
-000056 940c 7005 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000058 ff06 .dw $ff06
-000059 7369
-00005a 2d72
-00005b 7872 .db "isr-rx"
-00005c 0041 .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-00005d 7001 .dw DO_COLON
- usart_rx_isr:
-00005e 703d .dw XT_DOLITERAL
-00005f 00c6 .dw usart_data
-000060 7098 .dw XT_CFETCH
-000061 70b1 .dw XT_DUP
-000062 703d .dw XT_DOLITERAL
-000063 0003 .dw 3
-000064 7d7f .dw XT_EQUAL
-000065 7036 .dw XT_DOCONDBRANCH
-000066 0068 .dw usart_rx_isr1
-000067 7a59 .dw XT_COLD
- usart_rx_isr1:
-000068 0047 .dw XT_TO_RXBUF
-000069 7020 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-00006a 7001 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-00006b 703d
-00006c 005d .dw XT_DOLITERAL, XT_ISR_RX
-00006d 703d
-00006e 0028 .dw XT_DOLITERAL, URXCaddr
-00006f 7487 .dw XT_INTSTORE
-
-000070 703d .dw XT_DOLITERAL
-000071 0100 .dw usart_rx_data
-000072 703d .dw XT_DOLITERAL
-000073 0016 .dw usart_rx_size + 6
-000074 7154 .dw XT_ZERO
-000075 74cf .dw XT_FILL
-000076 7020 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000077 ff06 .dw $ff06
-000078 7872
-000079 622d
-00007a 6675 .db "rx-buf"
-00007b 0058 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-00007c 7001 .dw DO_COLON
- PFA_RX_BUFFER:
-00007d 0097 .dw XT_RXQ_BUFFER
-00007e 7036 .dw XT_DOCONDBRANCH
-00007f 007d .dw PFA_RX_BUFFER
-000080 703d .dw XT_DOLITERAL
-000081 0111 .dw usart_rx_out
-000082 7098 .dw XT_CFETCH
-000083 70b1 .dw XT_DUP
-000084 703d .dw XT_DOLITERAL
-000085 0100 .dw usart_rx_data
-000086 719d .dw XT_PLUS
-000087 7098 .dw XT_CFETCH
-000088 70c4 .dw XT_SWAP
-000089 722f .dw XT_1PLUS
-00008a 703d .dw XT_DOLITERAL
-00008b 000f .dw usart_rx_mask
-00008c 7213 .dw XT_AND
-00008d 703d .dw XT_DOLITERAL
-00008e 0111 .dw usart_rx_out
-00008f 708d .dw XT_CSTORE
-000090 7020 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-000091 ff07 .dw $ff07
-000092 7872
-000093 2d3f
-000094 7562
-000095 0066 .db "rx?-buf",0
-000096 0077 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-000097 7001 .dw DO_COLON
- PFA_RXQ_BUFFER:
-000098 7a51 .dw XT_PAUSE
-000099 703d .dw XT_DOLITERAL
-00009a 0111 .dw usart_rx_out
-00009b 7098 .dw XT_CFETCH
-00009c 703d .dw XT_DOLITERAL
-00009d 0110 .dw usart_rx_in
-00009e 7098 .dw XT_CFETCH
-00009f 7113 .dw XT_NOTEQUAL
-0000a0 7020 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-0000a1 ff07 .dw $ff07
-0000a2 7874
-0000a3 702d
-0000a4 6c6f
-0000a5 006c .db "tx-poll",0
-0000a6 0091 .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000a7 7001 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000a8 00b5 .dw XT_TXQ_POLL
-0000a9 7036 .dw XT_DOCONDBRANCH
-0000aa 00a8 .dw PFA_TX_POLL
- ; send to usart
-0000ab 703d .dw XT_DOLITERAL
-0000ac 00c6 .dw USART_DATA
-0000ad 708d .dw XT_CSTORE
-0000ae 7020 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000af ff08 .dw $ff08
-0000b0 7874
-0000b1 2d3f
-0000b2 6f70
-0000b3 6c6c .db "tx?-poll"
-0000b4 00a1 .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000b5 7001 .dw DO_COLON
- PFA_TXQ_POLL:
-0000b6 7a51 .dw XT_PAUSE
-0000b7 703d .dw XT_DOLITERAL
-0000b8 00c0 .dw USART_A
-0000b9 7098 .dw XT_CFETCH
-0000ba 703d .dw XT_DOLITERAL
-0000bb 0020 .dw bm_USART_TXRD
-0000bc 7213 .dw XT_AND
-0000bd 7020 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000be ff04 .dw $ff04
-0000bf 6275
-0000c0 7272 .db "ubrr"
-0000c1 00af .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000c2 706f .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000c3 0090 .dw EE_UBRRVAL
-0000c4 7bb4 .dw XT_EDEFERFETCH
-0000c5 7bbe .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000c6 ff06 .dw $ff06
-0000c7 752b
-0000c8 6173
-0000c9 7472 .db "+usart"
-0000ca 00be .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000cb 7001 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000cc 703d .dw XT_DOLITERAL
-0000cd 0098 .dw USART_B_VALUE
-0000ce 703d .dw XT_DOLITERAL
-0000cf 00c1 .dw USART_B
-0000d0 708d .dw XT_CSTORE
-
-0000d1 703d .dw XT_DOLITERAL
-0000d2 0006 .dw USART_C_VALUE
-0000d3 703d .dw XT_DOLITERAL
-0000d4 00c2 .dw USART_C | bm_USARTC_en
-0000d5 708d .dw XT_CSTORE
-
-0000d6 00c2 .dw XT_UBRR
-0000d7 70b1 .dw XT_DUP
-0000d8 72f9 .dw XT_BYTESWAP
-0000d9 703d .dw XT_DOLITERAL
-0000da 00c5 .dw BAUDRATE_HIGH
-0000db 708d .dw XT_CSTORE
-0000dc 703d .dw XT_DOLITERAL
-0000dd 00c4 .dw BAUDRATE_LOW
-0000de 708d .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000df 006a .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000e0 7020 .dw XT_EXIT
-
- ; settings for 1wire interface
- .equ OW_PORT=PORTB
- .EQU OW_BIT=4
- .include "drivers/1wire.asm"
-
- ; B. J. Rodriguez (MSP 430)
- ; Matthias Trute (AVR Atmega)
- ; COPYRIGHT
- ; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
- ; adapted 430 assembly code to AVR
- ; wishlist:
- ; use a configurable pin at runtime, compatible with bitnames.frt
- ; no external pull up, no external power supply for devices
- ; ???
- ;
- ;.EQU OW_BIT=4
- ;.equ OW_PORT=PORTE
- .set OW_DDR=(OW_PORT-1)
- .set OW_PIN=(OW_DDR-1)
-
- ;****f* 1W.RESET
- ; NAME
- ; 1W.RESET
- ; SYNOPSIS
- ; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
- ; DESCRIPTION
- ; This configures the port pin used by the 1-wire interface, and then
- ; sends an "initialize" sequence to the 1-wire devices. If any device
- ; is present, it will be detected.
- ;
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" (drive output low) for >480 usec.
- ; b) Output "1" (let output float).
- ; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
- ; So, wait 75 usec and sample input.
- ; d) Leave output high (floating) for at least 480 usec.
- ;******
- ; ( -- f )
- ; Hardware
- ; Initialize 1-wire devices; return true if present
- VE_OW_RESET:
-0000e1 ff08 .dw $ff08
-0000e2 7731
-0000e3 722e
-0000e4 7365
-0000e5 7465 .db "1w.reset"
-0000e6 00c6 .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
- XT_OW_RESET:
-0000e7 00e8 .dw PFA_OW_RESET
- PFA_OW_RESET:
-0000e8 939a
-0000e9 938a savetos
- ; setup to output
-0000ea 9a24 sbi OW_DDR, OW_BIT
- ; Pull output low
-0000eb 982c cbi OW_PORT, OW_BIT
- ; Delay >480 usec
-0000ec e8e0
-0000ed e0f7
-0000ee 9731
-0000ef f7f1 DELAY 480
- ; Critical timing period, disable interrupts.
-0000f0 b71f in temp1, SREG
-0000f1 94f8 cli
- ; Pull output high
-0000f2 9a2c sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
-0000f3 9824 cbi OW_DDR, OW_BIT
-0000f4 e0e0
-0000f5 e0f1
-0000f6 9731
-0000f7 f7f1 DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
-0000f8 b183 in tosl, OW_PIN
-0000f9 ff84 sbrs tosl, OW_BIT
-0000fa ef9f ser tosh
- ; End critical timing period, enable interrupts
-0000fb bf1f out SREG, temp1
- ; release bus
-0000fc 9824 cbi OW_DDR, OW_BIT
-0000fd 982c cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
-0000fe e8e0
-0000ff e0f6
-000100 9731
-000101 f7f1 DELAY 416
- ; we now have the result flag in TOS
-000102 2f89 mov tosl, tosh
-000103 940c 7005 jmp_ DO_NEXT
-
- ;****f* 1W.SLOT
- ; NAME
- ; 1W.SLOT
- ; SYNOPSIS
- ; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
- ; DESCRIPTION
- ; The "touch byte" function is described in Dallas App Note 74.
- ; It outputs a byte to the 1-wire pin, LSB first, and reads back
- ; the state of the 1-wire pin after a suitable delay.
- ; To read a byte, output $FF and read the reply data.
- ; To write a byte, output that byte and discard the reply.
- ;
- ; This function performs one bit of the "touch" operation --
- ; one read/write "slot" in Dallas jargon. Perform this eight
- ; times in a row to get the "touch byte" function.
- ;
- ; PARAMETERS
- ; The input parameter is xxxxxxxxbbbbbbbo where
- ; 'xxxxxxxx' are don't cares,
- ; 'bbbbbbb' are bits to be shifted down, and
- ; 'o' is the bit to be output in the slot. This must be 1
- ; to create a read slot.
- ;
- ; The returned value is xxxxxxxxibbbbbbb where
- ; 'xxxxxxxx' are not known (the input shifted down 1 position),
- ; 'i' is the bit read during the slot. This has no meaning
- ; if it was a write slot.
- ; 'bbbbbbb' are the 7 input bits, shifted down one position.
- ;
- ; This peculiar parameter usage allows OWTOUCH to be written as
- ; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
- ;
- ; NOTES
- ; Interrupts are disabled during each bit.
-
- ; Timing, per DS18B20 data sheet:
- ; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
- ; b) Output data bit (0 or 1), open drain
- ; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
- ; d) After write-0 period from start of cycle, output "1" (>60 us)
- ; e) After recovery period, loop or return. (> 1 us)
- ; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
- ; * "Typical" values are per App Note 132 for a 300m cable length.
-
- ; --------- -------------------------------
- ; \ / /
- ; -------------------------------
- ; a b c d e
- ; | 6us | 19us | 35us | 2us |
- ;******
- ; ( c -- c' )
- ; Hardware
- ; Write and read one bit to/from 1-wire.
- VE_OW_SLOT:
-000105 ff07 .dw $ff07
-000106 7731
-000107 732e
-000108 6f6c
-000109 0074 .db "1w.slot",0
-00010a 00e1 .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
- XT_OW_SLOT:
-00010b 010c .dw PFA_OW_SLOT
- PFA_OW_SLOT:
- ; pull low
-00010c 982c cbi OW_PORT, OW_BIT
-00010d 9a24 sbi OW_DDR, OW_BIT
- ; disable interrupts
-00010e b71f in temp1, SREG
-00010f 94f8 cli
-000110 e1e8
-000111 e0f0
-000112 9731
-000113 f7f1 DELAY 6 ; DELAY A
- ; check bit
-000114 9488 clc
-000115 9587 ror tosl
-000116 f410 brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
-000117 9a2c sbi OW_PORT, OW_BIT
-000118 9824 cbi OW_DDR, OW_BIT
- PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
-000119 e2e4
-00011a e0f0
-00011b 9731
-00011c f7f1 DELAY 9 ; wait DELAY E to sample
-00011d b103 in temp0, OW_PIN
-00011e fd04 sbrc temp0, OW_BIT
-00011f 6880 ori tosl, $80
-
-000120 ecec
-000121 e0f0
-000122 9731
-000123 f7f1 DELAY 51 ; DELAY B
-000124 9a2c sbi OW_PORT, OW_BIT ; release bus
-000125 9824 cbi OW_DDR, OW_BIT
-000126 e0e8
-000127 e0f0
-000128 9731
-000129 f7f1 delay 2
- ; re-enable interrupts
-00012a bf1f out SREG, temp1
-00012b 940c 7005 jmp_ DO_NEXT
-
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c 7a5a jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-00012d 920a st -Y, r0
-00012e b60f in r0, SREG
-00012f 920a st -Y, r0
- .if (pclen==3)
- .endif
-000130 900f pop r0
-000131 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-000132 940a dec r0
- .if intvecsize == 1 ;
- .endif
-000133 2cb0 mov isrflag, r0
-000134 93ff push zh
-000135 93ef push zl
-000136 e1e2 ldi zl, low(intcnt)
-000137 e0f1 ldi zh, high(intcnt)
-000138 9406 lsr r0 ; we use byte addresses in the counter array, not words
-000139 0de0 add zl, r0
-00013a 1df3 adc zh, zeroh
-00013b 8000 ld r0, Z
-00013c 9403 inc r0
-00013d 8200 st Z, r0
-00013e 91ef pop zl
-00013f 91ff pop zh
-
-000140 9009 ld r0, Y+
-000141 be0f out SREG, r0
-000142 9009 ld r0, Y+
-000143 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000144 ff02 .dw $ff02
-000145 2b6d .db "m+"
-000146 0105 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-000147 7001 .dw DO_COLON
- PFA_MPLUS:
-000148 7d67 .dw XT_S2D
-000149 7415 .dw XT_DPLUS
-00014a 7020 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00014b ff03 .dw $ff03
-00014c 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-00014d 002a .db "ud*"
-00014e 0144 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-00014f 7001 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000150 70b1
-000151 70ff
-000152 71e0
-000153 70d9 .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000154 70c4
-000155 70f6
-000156 71e0
-000157 70e1
-000158 719d
-000159 7020 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00015a ff04 .dw $ff04
-00015b 6d75
-00015c 7861 .db "umax"
-00015d 014b .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-00015e 7001 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-00015f 7565
-000160 715c .DW XT_2DUP,XT_ULESS
-000161 7036 .dw XT_DOCONDBRANCH
-000162 0164 DEST(UMAX1)
-000163 70c4 .DW XT_SWAP
-000164 70d9 UMAX1: .DW XT_DROP
-000165 7020 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000166 ff04 .dw $ff04
-000167 6d75
-000168 6e69 .db "umin"
-000169 015a .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00016a 7001 .dw DO_COLON
- PFA_UMIN:
- .endif
-00016b 7565
-00016c 7167 .DW XT_2DUP,XT_UGREATER
-00016d 7036 .dw XT_DOCONDBRANCH
-00016e 0170 DEST(UMIN1)
-00016f 70c4 .DW XT_SWAP
-000170 70d9 UMIN1: .DW XT_DROP
-000171 7020 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000172 7001 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000173 703d .dw XT_DOLITERAL
-000174 8000 .dw $8000
-000175 7213 .dw XT_AND
-000176 711a .dw XT_ZEROEQUAL
-000177 7036 .dw XT_DOCONDBRANCH
-000178 017b DEST(IMMEDIATEQ1)
-000179 7d86 .dw XT_ONE
-00017a 7020 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00017b 714b .dw XT_TRUE
-00017c 7020 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-00017d ff0a .dw $ff0a
-00017e 616e
-00017f 656d
-000180 663e
-000181 616c
-000182 7367 .db "name>flags"
-000183 0166 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000184 7001 .dw DO_COLON
- PFA_NAME2FLAGS:
-000185 73cb .dw XT_FETCHI ; skip to link field
-000186 703d .dw XT_DOLITERAL
-000187 ff00 .dw $ff00
-000188 7213 .dw XT_AND
-000189 7020 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .include "dict/appl_8k.inc"
-
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-00018a ff06 .dw $ff06
-00018b 656e
-00018c 6577
-00018d 7473 .db "newest"
-00018e 017d .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-00018f 7048 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-000190 012e .dw ram_newest
-
- .dseg
-00012e ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-000191 ff06 .dw $ff06
-000192 616c
-000193 6574
-000194 7473 .db "latest"
-000195 018a .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000196 7048 .dw PFA_DOVARIABLE
- PFA_LATEST:
-000197 0132 .dw ram_latest
-
- .dseg
-000132 ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-000198 ff08 .dw $ff08
-000199 6328
-00019a 6572
-00019b 7461
-00019c 2965 .db "(create)"
-00019d 0191 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-00019e 7001 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-00019f 79b4
-0001a0 02f5 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-0001a1 70b1
-0001a2 018f
-0001a3 755e
-0001a4 7081 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-0001a5 02da
-0001a6 018f
-0001a7 7081 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-0001a8 7020 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-0001a9 0001 .dw $0001
-0001aa 005c .db $5c,0
-0001ab 0198 .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-0001ac 7001 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-0001ad 799b .dw XT_SOURCE
-0001ae 70f0 .dw XT_NIP
-0001af 757e .dw XT_TO_IN
-0001b0 7081 .dw XT_STORE
-0001b1 7020 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-0001b2 0001 .dw $0001
-0001b3 0028 .db "(" ,0
-0001b4 01a9 .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-0001b5 7001 .dw DO_COLON
- PFA_LPAREN:
- .endif
-0001b6 703d .dw XT_DOLITERAL
-0001b7 0029 .dw ')'
-0001b8 7987 .dw XT_PARSE
-0001b9 756e .dw XT_2DROP
-0001ba 7020 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-0001bb ff07 .dw $ff07
-0001bc 6f63
-0001bd 706d
-0001be 6c69
-0001bf 0065 .db "compile",0
-0001c0 01b2 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-0001c1 7001 .dw DO_COLON
- PFA_COMPILE:
- .endif
-0001c2 70f6 .dw XT_R_FROM
-0001c3 70b1 .dw XT_DUP
-0001c4 7bab .dw XT_ICELLPLUS
-0001c5 70ff .dw XT_TO_R
-0001c6 73cb .dw XT_FETCHI
-0001c7 01cc .dw XT_COMMA
-0001c8 7020 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-0001c9 ff01 .dw $ff01
-0001ca 002c .db ',',0 ; ,
-0001cb 01bb .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-0001cc 7001 .dw DO_COLON
- PFA_COMMA:
-0001cd 75ae .dw XT_DP
-0001ce 7373 .dw XT_STOREI
-0001cf 75ae .dw XT_DP
-0001d0 722f .dw XT_1PLUS
-0001d1 7b99 .dw XT_DOTO
-0001d2 75af .dw PFA_DP
-0001d3 7020 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-0001d4 0003 .dw $0003
-0001d5 275b
-0001d6 005d .db "[']",0
-0001d7 01c9 .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-0001d8 7001 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-0001d9 780a .dw XT_TICK
-0001da 01e2 .dw XT_LITERAL
-0001db 7020 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-0001dc 0007 .dw $0007
-0001dd 696c
-0001de 6574
-0001df 6172
-0001e0 006c .db "literal",0
-0001e1 01d4 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-0001e2 7001 .dw DO_COLON
- PFA_LITERAL:
- .endif
-0001e3 01c1 .DW XT_COMPILE
-0001e4 703d .DW XT_DOLITERAL
-0001e5 01cc .DW XT_COMMA
-0001e6 7020 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-0001e7 0008 .dw $0008
-0001e8 6c73
-0001e9 7469
-0001ea 7265
-0001eb 6c61 .db "sliteral"
-0001ec 01dc .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-0001ed 7001 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-0001ee 01c1 .dw XT_COMPILE
-0001ef 776d .dw XT_DOSLITERAL ; ( -- addr n)
-0001f0 777b .dw XT_SCOMMA
-0001f1 7020 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-0001f2 7001 .dw DO_COLON
- PFA_GMARK:
-0001f3 75ae .dw XT_DP
-0001f4 01c1 .dw XT_COMPILE
-0001f5 ffff .dw -1 ; ffff does not erase flash
-0001f6 7020 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-0001f7 7001 .dw DO_COLON
- PFA_GRESOLVE:
-0001f8 7b57 .dw XT_QSTACK
-0001f9 75ae .dw XT_DP
-0001fa 70c4 .dw XT_SWAP
-0001fb 7373 .dw XT_STOREI
-0001fc 7020 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-0001fd 7001 .dw DO_COLON
- PFA_LMARK:
-0001fe 75ae .dw XT_DP
-0001ff 7020 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-000200 7001 .dw DO_COLON
- PFA_LRESOLVE:
-000201 7b57 .dw XT_QSTACK
-000202 01cc .dw XT_COMMA
-000203 7020 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-000204 0005 .dw $0005
-000205 6861
-000206 6165
-000207 0064 .db "ahead",0
-000208 01e7 .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-000209 7001 .dw DO_COLON
- PFA_AHEAD:
- .endif
-00020a 01c1 .dw XT_COMPILE
-00020b 702f .dw XT_DOBRANCH
-00020c 01f2 .dw XT_GMARK
-00020d 7020 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-00020e 0002 .dw $0002
-00020f 6669 .db "if"
-000210 0204 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-000211 7001 .dw DO_COLON
- PFA_IF:
- .endif
-000212 01c1 .dw XT_COMPILE
-000213 7036 .dw XT_DOCONDBRANCH
-000214 01f2 .dw XT_GMARK
-000215 7020 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-000216 0004 .dw $0004
-000217 6c65
-000218 6573 .db "else"
-000219 020e .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-00021a 7001 .dw DO_COLON
- PFA_ELSE:
- .endif
-00021b 01c1 .dw XT_COMPILE
-00021c 702f .dw XT_DOBRANCH
-00021d 01f2 .dw XT_GMARK
-00021e 70c4 .dw XT_SWAP
-00021f 01f7 .dw XT_GRESOLVE
-000220 7020 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-000221 0004 .dw $0004
-000222 6874
-000223 6e65 .db "then"
-000224 0216 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-000225 7001 .dw DO_COLON
- PFA_THEN:
- .endif
-000226 01f7 .dw XT_GRESOLVE
-000227 7020 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-000228 0005 .dw $0005
-000229 6562
-00022a 6967
-00022b 006e .db "begin",0
-00022c 0221 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-00022d 7001 .dw DO_COLON
- PFA_BEGIN:
- .endif
-00022e 01fd .dw XT_LMARK
-00022f 7020 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-000230 0005 .dw $0005
-000231 6877
-000232 6c69
-000233 0065 .db "while",0
-000234 0228 .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-000235 7001 .dw DO_COLON
- PFA_WHILE:
- .endif
-000236 0211 .dw XT_IF
-000237 70c4 .dw XT_SWAP
-000238 7020 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-000239 0006 .dw $0006
-00023a 6572
-00023b 6570
-00023c 7461 .db "repeat"
-00023d 0230 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-00023e 7001 .dw DO_COLON
- PFA_REPEAT:
- .endif
-00023f 0252 .dw XT_AGAIN
-000240 0225 .dw XT_THEN
-000241 7020 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-000242 0005 .dw $0005
-000243 6e75
-000244 6974
-000245 006c .db "until",0
-000246 0239 .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-000247 7001 .dw DO_COLON
- PFA_UNTIL:
- .endif
-000248 703d .dw XT_DOLITERAL
-000249 7036 .dw XT_DOCONDBRANCH
-00024a 01cc .dw XT_COMMA
-
-00024b 0200 .dw XT_LRESOLVE
-00024c 7020 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-00024d 0005 .dw $0005
-00024e 6761
-00024f 6961
-000250 006e .db "again",0
-000251 0242 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-000252 7001 .dw DO_COLON
- PFA_AGAIN:
- .endif
-000253 01c1 .dw XT_COMPILE
-000254 702f .dw XT_DOBRANCH
-000255 0200 .dw XT_LRESOLVE
-000256 7020 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-000257 0002 .dw $0002
-000258 6f64 .db "do"
-000259 024d .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-00025a 7001 .dw DO_COLON
- PFA_DO:
-
- .endif
-00025b 01c1 .dw XT_COMPILE
-00025c 729b .dw XT_DODO
-00025d 01fd .dw XT_LMARK
-00025e 7154 .dw XT_ZERO
-00025f 02b5 .dw XT_TO_L
-000260 7020 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-000261 0004 .dw $0004
-000262 6f6c
-000263 706f .db "loop"
-000264 0257 .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000265 7001 .dw DO_COLON
- PFA_LOOP:
- .endif
-000266 01c1 .dw XT_COMPILE
-000267 72c9 .dw XT_DOLOOP
-000268 029c .dw XT_ENDLOOP
-000269 7020 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-00026a 0005 .dw $0005
-00026b 6c2b
-00026c 6f6f
-00026d 0070 .db "+loop",0
-00026e 0261 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-00026f 7001 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-000270 01c1 .dw XT_COMPILE
-000271 72ba .dw XT_DOPLUSLOOP
-000272 029c .dw XT_ENDLOOP
-000273 7020 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-000274 0005 .dw $0005
-000275 656c
-000276 7661
-000277 0065 .db "leave",0
-000278 026a .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-000279 7001 .dw DO_COLON
- PFA_LEAVE:
- .endif
-00027a 01c1
-00027b 72d4 .DW XT_COMPILE,XT_UNLOOP
-00027c 0209
-00027d 02b5
-00027e 7020 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-00027f 0003 .dw $0003
-000280 643f
-000281 006f .db "?do",0
-000282 0274 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000283 7001 .dw DO_COLON
- PFA_QDO:
- .endif
-000284 01c1 .dw XT_COMPILE
-000285 028b .dw XT_QDOCHECK
-000286 0211 .dw XT_IF
-000287 025a .dw XT_DO
-000288 70c4 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-000289 02b5 .dw XT_TO_L ; then follows at the end.
-00028a 7020 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00028b 7001 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00028c 7565 .dw XT_2DUP
-00028d 7d7f .dw XT_EQUAL
-00028e 70b1 .dw XT_DUP
-00028f 70ff .dw XT_TO_R
-000290 7036 .dw XT_DOCONDBRANCH
-000291 0293 DEST(PFA_QDOCHECK1)
-000292 756e .dw XT_2DROP
- PFA_QDOCHECK1:
-000293 70f6 .dw XT_R_FROM
-000294 71fd .dw XT_INVERT
-000295 7020 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000296 ff07 .dw $ff07
-000297 6e65
-000298 6c64
-000299 6f6f
-00029a 0070 .db "endloop",0
-00029b 027f .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-00029c 7001 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-00029d 0200 .DW XT_LRESOLVE
-00029e 02a9
-00029f 70b9
-0002a0 7036 LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-0002a1 02a5 DEST(LOOP2)
-0002a2 0225 .DW XT_THEN
-0002a3 702f .dw XT_DOBRANCH
-0002a4 029e DEST(LOOP1)
-0002a5 7020 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-0002a6 ff02 .dw $ff02
-0002a7 3e6c .db "l>"
-0002a8 0296 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-0002a9 7001 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-0002aa 02c8 .dw XT_LP
-0002ab 7079 .dw XT_FETCH
-0002ac 7079 .dw XT_FETCH
-0002ad 703d .dw XT_DOLITERAL
-0002ae fffe .dw -2
-0002af 02c8 .dw XT_LP
-0002b0 7265 .dw XT_PLUSSTORE
-0002b1 7020 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-0002b2 ff02 .dw $ff02
-0002b3 6c3e .db ">l"
-0002b4 02a6 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-0002b5 7001 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-0002b6 7d8b .dw XT_TWO
-0002b7 02c8 .dw XT_LP
-0002b8 7265 .dw XT_PLUSSTORE
-0002b9 02c8 .dw XT_LP
-0002ba 7079 .dw XT_FETCH
-0002bb 7081 .dw XT_STORE
-0002bc 7020 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-0002bd ff03 .dw $ff03
-0002be 706c
-0002bf 0030 .db "lp0",0
-0002c0 02b2 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-0002c1 706f .dw PFA_DOVALUE1
- PFA_LP0:
-0002c2 0044 .dw CFG_LP0
-0002c3 7bb4 .dw XT_EDEFERFETCH
-0002c4 7bbe .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-0002c5 ff02 .dw $ff02
-0002c6 706c .db "lp"
-0002c7 02bd .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-0002c8 7048 .dw PFA_DOVARIABLE
- PFA_LP:
-0002c9 0134 .dw ram_lp
-
- .dseg
-000134 ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-0002ca ff06 .dw $ff06
-0002cb 7263
-0002cc 6165
-0002cd 6574 .db "create"
-0002ce 02c5 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-0002cf 7001 .dw DO_COLON
- PFA_CREATE:
- .endif
-0002d0 019e .dw XT_DOCREATE
-0002d1 02fe .dw XT_REVEAL
-0002d2 01c1 .dw XT_COMPILE
-0002d3 7052 .dw PFA_DOCONSTANT
-0002d4 7020 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-0002d5 ff06 .dw $ff06
-0002d6 6568
-0002d7 6461
-0002d8 7265 .db "header"
-0002d9 02ca .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-0002da 7001 .dw DO_COLON
- PFA_HEADER:
-0002db 75ae .dw XT_DP ; the new Name Field
-0002dc 70ff .dw XT_TO_R
-0002dd 70ff .dw XT_TO_R ; ( R: NFA WID )
-0002de 70b1 .dw XT_DUP
-0002df 7128 .dw XT_GREATERZERO
-0002e0 7036 .dw XT_DOCONDBRANCH
-0002e1 02ec .dw PFA_HEADER1
-0002e2 70b1 .dw XT_DUP
-0002e3 703d .dw XT_DOLITERAL
-0002e4 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-0002e5 721c .dw XT_OR
-0002e6 777f .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-0002e7 70f6 .dw XT_R_FROM
-0002e8 735f .dw XT_FETCHE
-0002e9 01cc .dw XT_COMMA
-0002ea 70f6 .dw XT_R_FROM
-0002eb 7020 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-0002ec 703d .dw XT_DOLITERAL
-0002ed fff0 .dw -16
-0002ee 7841 .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-0002ef ff07 .dw $ff07
-0002f0 6c77
-0002f1 6373
-0002f2 706f
-0002f3 0065 .db "wlscope",0
-0002f4 02d5 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-0002f5 7c13 .dw PFA_DODEFER1
- PFA_WLSCOPE:
-0002f6 0040 .dw CFG_WLSCOPE
-0002f7 7bb4 .dw XT_EDEFERFETCH
-0002f8 7bbe .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-0002f9 ff06 .dw $ff06
-0002fa 6572
-0002fb 6576
-0002fc 6c61 .db "reveal"
-0002fd 02ef .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-0002fe 7001 .dw DO_COLON
- PFA_REVEAL:
- .endif
-0002ff 018f
-000300 755e
-000301 7079 .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-000302 70b9
-000303 7036 .DW XT_QDUP,XT_DOCONDBRANCH
-000304 0309 DEST(REVEAL1)
-000305 018f
-000306 7079
-000307 70c4
-000308 733b .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-000309 7020 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-00030a 0005 .dw $0005
-00030b 6f64
-00030c 7365
-00030d 003e .db "does>",0
-00030e 02f9 .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-00030f 7001 .dw DO_COLON
- PFA_DOES:
-000310 01c1 .dw XT_COMPILE
-000311 0322 .dw XT_DODOES
-000312 01c1 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-000313 940e .dw $940e ; the address of this compiled
-000314 01c1 .dw XT_COMPILE ; code will replace the XT of the
-000315 0317 .dw DO_DODOES ; word that CREATE created
-000316 7020 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-000317 939a
-000318 938a savetos
-000319 01cb movw tosl, wl
-00031a 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-00031b 917f pop wh
-00031c 916f pop wl
-
-00031d 93bf push XH
-00031e 93af push XL
-00031f 01db movw XL, wl
-000320 940c 7005 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-000322 7001 .dw DO_COLON
- PFA_DODOES:
-000323 70f6 .dw XT_R_FROM
-000324 018f .dw XT_NEWEST
-000325 755e .dw XT_CELLPLUS
-000326 7079 .dw XT_FETCH
-000327 735f .dw XT_FETCHE
-000328 7c7e .dw XT_NFA2CFA
-000329 7373 .dw XT_STOREI
-00032a 7020 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-00032b ff01 .dw $ff01
-00032c 003a .db ":",0
-00032d 030a .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-00032e 7001 .dw DO_COLON
- PFA_COLON:
- .endif
-00032f 019e .dw XT_DOCREATE
-000330 0339 .dw XT_COLONNONAME
-000331 70d9 .dw XT_DROP
-000332 7020 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-000333 ff07 .dw $ff07
-000334 6e3a
-000335 6e6f
-000336 6d61
-000337 0065 .db ":noname",0
-000338 032b .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-000339 7001 .dw DO_COLON
- PFA_COLONNONAME:
-00033a 75ae .dw XT_DP
-00033b 70b1 .dw XT_DUP
-00033c 0196 .dw XT_LATEST
-00033d 7081 .dw XT_STORE
-
-00033e 01c1 .dw XT_COMPILE
-00033f 7001 .dw DO_COLON
-
-000340 034e .dw XT_RBRACKET
-000341 7020 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-000342 0001 .dw $0001
-000343 003b .db $3b,0
-000344 0333 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-000345 7001 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-000346 01c1 .dw XT_COMPILE
-000347 7020 .dw XT_EXIT
-000348 0356 .dw XT_LBRACKET
-000349 02fe .dw XT_REVEAL
-00034a 7020 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-00034b ff01 .dw $ff01
-00034c 005d .db "]",0
-00034d 0342 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-00034e 7001 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-00034f 7d86 .dw XT_ONE
-000350 754b .dw XT_STATE
-000351 7081 .dw XT_STORE
-000352 7020 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-000353 0001 .dw $0001
-000354 005b .db "[",0
-000355 034b .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-000356 7001 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-000357 7154 .dw XT_ZERO
-000358 754b .dw XT_STATE
-000359 7081 .dw XT_STORE
-00035a 7020 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-00035b ff08 .dw $ff08
-00035c 6176
-00035d 6972
-00035e 6261
-00035f 656c .db "variable"
-000360 0353 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-000361 7001 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-000362 75bf .dw XT_HERE
-000363 036d .dw XT_CONSTANT
-000364 7d8b .dw XT_TWO
-000365 75c8 .dw XT_ALLOT
-000366 7020 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-000367 ff08 .dw $ff08
-000368 6f63
-000369 736e
-00036a 6174
-00036b 746e .db "constant"
-00036c 035b .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-00036d 7001 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-00036e 019e .dw XT_DOCREATE
-00036f 02fe .dw XT_REVEAL
-000370 01c1 .dw XT_COMPILE
-000371 7048 .dw PFA_DOVARIABLE
-000372 01cc .dw XT_COMMA
-000373 7020 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-000374 ff04 .dw $ff04
-000375 7375
-000376 7265 .db "user"
-000377 0367 .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-000378 7001 .dw DO_COLON
- PFA_USER:
-000379 019e .dw XT_DOCREATE
-00037a 02fe .dw XT_REVEAL
-
-00037b 01c1 .dw XT_COMPILE
-00037c 7058 .dw PFA_DOUSER
-00037d 01cc .dw XT_COMMA
-00037e 7020 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-00037f 0007 .dw $0007
-000380 6572
-000381 7563
-000382 7372
-000383 0065 .db "recurse",0
-000384 0374 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000385 7001 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000386 0196 .dw XT_LATEST
-000387 7079 .dw XT_FETCH
-000388 01cc .dw XT_COMMA
-000389 7020 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-00038a ff09 .dw $ff09
-00038b 6d69
-00038c 656d
-00038d 6964
-00038e 7461
-00038f 0065 .db "immediate",0
-000390 037f .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-000391 7001 .dw DO_COLON
- PFA_IMMEDIATE:
-000392 0433 .dw XT_GET_CURRENT
-000393 735f .dw XT_FETCHE
-000394 70b1 .dw XT_DUP
-000395 73cb .dw XT_FETCHI
-000396 703d .dw XT_DOLITERAL
-000397 7fff .dw $7fff
-000398 7213 .dw XT_AND
-000399 70c4 .dw XT_SWAP
-00039a 7373 .dw XT_STOREI
-00039b 7020 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-00039c 0006 .dw $0006
-00039d 635b
-00039e 6168
-00039f 5d72 .db "[char]"
-0003a0 038a .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-0003a1 7001 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-0003a2 01c1 .dw XT_COMPILE
-0003a3 703d .dw XT_DOLITERAL
-0003a4 78ea .dw XT_CHAR
-0003a5 01cc .dw XT_COMMA
-0003a6 7020 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-0003a7 0006 .dw $0006
-0003a8 6261
-0003a9 726f
-0003aa 2274 .db "abort",'"'
-0003ab 039c .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-0003ac 7001 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-0003ad 74c1 .dw XT_SQUOTE
-0003ae 01c1 .dw XT_COMPILE
-0003af 03be .dw XT_QABORT
-0003b0 7020 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-0003b1 ff05 .dw $ff05
-0003b2 6261
-0003b3 726f
-0003b4 0074 .db "abort",0
-0003b5 03a7 .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-0003b6 7001 .dw DO_COLON
- PFA_ABORT:
- .endif
-0003b7 714b .dw XT_TRUE
-0003b8 7841 .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-0003b9 ff06 .dw $ff06
-0003ba 613f
-0003bb 6f62
-0003bc 7472 .db "?abort"
-0003bd 03b1 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-0003be 7001 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-0003bf 70e1
-0003c0 7036 .DW XT_ROT,XT_DOCONDBRANCH
-0003c1 03c4 DEST(QABO1)
-0003c2 77a0
-0003c3 03b6 .DW XT_ITYPE,XT_ABORT
-0003c4 756e
-0003c5 7020 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-0003c6 ff09 .dw $ff09
-0003c7 6567
-0003c8 2d74
-0003c9 7473
-0003ca 6361
-0003cb 006b .db "get-stack",0
-0003cc 03b9 .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-0003cd 7001 .dw DO_COLON
- .endif
-0003ce 70b1 .dw XT_DUP
-0003cf 755e .dw XT_CELLPLUS
-0003d0 70c4 .dw XT_SWAP
-0003d1 735f .dw XT_FETCHE
-0003d2 70b1 .dw XT_DUP
-0003d3 70ff .dw XT_TO_R
-0003d4 7154 .dw XT_ZERO
-0003d5 70c4 .dw XT_SWAP ; go from bigger to smaller addresses
-0003d6 028b .dw XT_QDOCHECK
-0003d7 7036 .dw XT_DOCONDBRANCH
-0003d8 03e4 DEST(PFA_N_FETCH_E2)
-0003d9 729b .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-0003da 72ac .dw XT_I
-0003db 7235 .dw XT_1MINUS
-0003dc 7558 .dw XT_CELLS ; ( -- ee-addr i*2 )
-0003dd 70cf .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-0003de 719d .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-0003df 735f .dw XT_FETCHE ;( -- ee-addr item_i )
-0003e0 70c4 .dw XT_SWAP ;( -- item_i ee-addr )
-0003e1 714b .dw XT_TRUE ; shortcut for -1
-0003e2 72ba .dw XT_DOPLUSLOOP
-0003e3 03da DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-0003e4 756e .dw XT_2DROP
-0003e5 70f6 .dw XT_R_FROM
-0003e6 7020 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-0003e7 ff09 .dw $ff09
-0003e8 6573
-0003e9 2d74
-0003ea 7473
-0003eb 6361
-0003ec 006b .db "set-stack",0
-0003ed 03c6 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-0003ee 7001 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-0003ef 70cf .dw XT_OVER
-0003f0 7121 .dw XT_ZEROLESS
-0003f1 7036 .dw XT_DOCONDBRANCH
-0003f2 03f6 DEST(PFA_SET_STACK0)
-0003f3 703d .dw XT_DOLITERAL
-0003f4 fffc .dw -4
-0003f5 7841 .dw XT_THROW
- PFA_SET_STACK0:
-0003f6 7565 .dw XT_2DUP
-0003f7 733b .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-0003f8 70c4 .dw XT_SWAP
-0003f9 7154 .dw XT_ZERO
-0003fa 028b .dw XT_QDOCHECK
-0003fb 7036 .dw XT_DOCONDBRANCH
-0003fc 0403 DEST(PFA_SET_STACK2)
-0003fd 729b .dw XT_DODO
- PFA_SET_STACK1:
-0003fe 755e .dw XT_CELLPLUS ; ( -- i_x e-addr )
-0003ff 7576 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-000400 733b .dw XT_STOREE
-000401 72c9 .dw XT_DOLOOP
-000402 03fe DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-000403 70d9 .dw XT_DROP
-000404 7020 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-000405 ff09 .dw $ff09
-000406 616d
-000407 2d70
-000408 7473
-000409 6361
-00040a 006b .db "map-stack",0
-00040b 03e7 .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-00040c 7001 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-00040d 70b1 .dw XT_DUP
-00040e 755e .dw XT_CELLPLUS
-00040f 70c4 .dw XT_SWAP
-000410 735f .dw XT_FETCHE
-000411 7558 .dw XT_CELLS
-000412 7d5e .dw XT_BOUNDS
-000413 028b .dw XT_QDOCHECK
-000414 7036 .dw XT_DOCONDBRANCH
-000415 0428 DEST(PFA_MAPSTACK3)
-000416 729b .dw XT_DODO
- PFA_MAPSTACK1:
-000417 72ac .dw XT_I
-000418 735f .dw XT_FETCHE ; -- i*x XT id
-000419 70c4 .dw XT_SWAP
-00041a 70ff .dw XT_TO_R
-00041b 7108 .dw XT_R_FETCH
-00041c 702a .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-00041d 70b9 .dw XT_QDUP
-00041e 7036 .dw XT_DOCONDBRANCH
-00041f 0424 DEST(PFA_MAPSTACK2)
-000420 70f6 .dw XT_R_FROM
-000421 70d9 .dw XT_DROP
-000422 72d4 .dw XT_UNLOOP
-000423 7020 .dw XT_EXIT
- PFA_MAPSTACK2:
-000424 70f6 .dw XT_R_FROM
-000425 7d8b .dw XT_TWO
-000426 72ba .dw XT_DOPLUSLOOP
-000427 0417 DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-000428 70d9 .dw XT_DROP
-000429 7154 .dw XT_ZERO
-00042a 7020 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-00042b ff0b .dw $ff0b
-00042c 6567
-00042d 2d74
-00042e 7563
-00042f 7272
-000430 6e65
-000431 0074 .db "get-current",0
-000432 0405 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-000433 7001 .dw DO_COLON
- PFA_GET_CURRENT:
-000434 703d .dw XT_DOLITERAL
-000435 004a .dw CFG_CURRENT
-000436 735f .dw XT_FETCHE
-000437 7020 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-000438 ff09 .dw $ff09
-000439 6567
-00043a 2d74
-00043b 726f
-00043c 6564
-00043d 0072 .db "get-order",0
-00043e 042b .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-00043f 7001 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-000440 703d .dw XT_DOLITERAL
-000441 004e .dw CFG_ORDERLISTLEN
-000442 03cd .dw XT_GET_STACK
-000443 7020 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-000444 ff09 .dw $ff09
-000445 6663
-000446 2d67
-000447 726f
-000448 6564
-000449 0072 .db "cfg-order",0
-00044a 0438 .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-00044b 7048 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-00044c 004e .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-00044d ff07 .dw $ff07
-00044e 6f63
-00044f 706d
-000450 7261
-000451 0065 .db "compare",0
-000452 0444 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-000453 0454 .dw PFA_COMPARE
- PFA_COMPARE:
-000454 93bf push xh
-000455 93af push xl
-000456 018c movw temp0, tosl
-000457 9189
-000458 9199 loadtos
-000459 01dc movw xl, tosl
-00045a 9189
-00045b 9199 loadtos
-00045c 019c movw temp2, tosl
-00045d 9189
-00045e 9199 loadtos
-00045f 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-000460 90ed ld temp4, X+
-000461 90f1 ld temp5, Z+
-000462 14ef cp temp4, temp5
-000463 f451 brne PFA_COMPARE_NOTEQUAL
-000464 950a dec temp0
-000465 f019 breq PFA_COMPARE_ENDREACHED2
-000466 952a dec temp2
-000467 f7c1 brne PFA_COMPARE_LOOP
-000468 c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-000469 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-00046a 2b02 or temp0, temp2
-00046b f411 brne PFA_COMPARE_CHECKLASTCHAR
-00046c 2788 clr tosl
-00046d c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-00046e ef8f ser tosl
-00046f c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000470 2f98 mov tosh, tosl
-000471 91af pop xl
-000472 91bf pop xh
-000473 940c 7005 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000475 ff07 .dw $ff07
-000476 666e
-000477 3e61
-000478 666c
-000479 0061 .db "nfa>lfa",0
-00047a 044d .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-00047b 7001 .dw DO_COLON
- PFA_NFA2LFA:
-00047c 7c72 .dw XT_NAME2STRING
-00047d 722f .dw XT_1PLUS
-00047e 7204 .dw XT_2SLASH
-00047f 719d .dw XT_PLUS
-000480 7020 .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 4000
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; they may be moved to the core dictionary if needed
- .include "words/dot-s.asm"
-
- ; Tools
- ; stack dump
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTS:
-000481 ff02 .dw $ff02
-000482 732e .db ".s"
-000483 0475 .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
- XT_DOTS:
-000484 7001 .dw DO_COLON
- PFA_DOTS:
- .endif
-000485 7aa1 .dw XT_DEPTH
-000486 7448 .dw XT_UDOT
-000487 77e2 .dw XT_SPACE
-000488 7aa1 .dw XT_DEPTH
-000489 7154 .dw XT_ZERO
-00048a 028b .dw XT_QDOCHECK
-00048b 7036 .dw XT_DOCONDBRANCH
-00048c 0493 DEST(PFA_DOTS2)
-00048d 729b .dw XT_DODO
- PFA_DOTS1:
-00048e 72ac .dw XT_I
-00048f 74af .dw XT_PICK
-000490 7448 .dw XT_UDOT
-000491 72c9 .dw XT_DOLOOP
-000492 048e DEST(PFA_DOTS1)
- PFA_DOTS2:
-000493 7020 .dw XT_EXIT
- .include "words/spirw.asm"
-
- ; MCU
- ; SPI exchange of 1 byte
- VE_SPIRW:
-000494 ff06 .dw $ff06
-000495 2163
-000496 7340
-000497 6970 .db "c!@spi"
-000498 0481 .dw VE_HEAD
- .set VE_HEAD = VE_SPIRW
- XT_SPIRW:
-000499 049a .dw PFA_SPIRW
- PFA_SPIRW:
-00049a d003 rcall do_spirw
-00049b 2799 clr tosh
-00049c 940c 7005 jmp_ DO_NEXT
-
- do_spirw:
-00049e bd8e out_ SPDR, tosl
- do_spirw1:
-00049f b50d in_ temp0, SPSR
-0004a0 7f08 cbr temp0,7
-0004a1 bd0d out_ SPSR, temp0
-0004a2 b50d in_ temp0, SPSR
-0004a3 ff07 sbrs temp0, 7
-0004a4 cffa rjmp do_spirw1 ; wait until complete
-0004a5 b58e in_ tosl, SPDR
-0004a6 9508 ret
- .include "words/n-spi.asm"
-
- ; MCU
- ; read len bytes from SPI to addr
- VE_N_SPIR:
-0004a7 ff05 .dw $ff05
-0004a8 406e
-0004a9 7073
-0004aa 0069 .db "n@spi",0
-0004ab 0494 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIR
- XT_N_SPIR:
-0004ac 04ad .dw PFA_N_SPIR
- PFA_N_SPIR:
-0004ad 018c movw temp0, tosl
-0004ae 9189
-0004af 9199 loadtos
-0004b0 01fc movw zl, tosl
-0004b1 01c8 movw tosl, temp0
- PFA_N_SPIR_LOOP:
-0004b2 bc2e out_ SPDR, zerol
- PFA_N_SPIR_LOOP1:
-0004b3 b52d in_ temp2, SPSR
-0004b4 ff27 sbrs temp2, SPIF
-0004b5 cffd rjmp PFA_N_SPIR_LOOP1
-0004b6 b52e in_ temp2, SPDR
-0004b7 9321 st Z+, temp2
-0004b8 9701 sbiw tosl, 1
-0004b9 f7c1 brne PFA_N_SPIR_LOOP
-0004ba 9189
-0004bb 9199 loadtos
-0004bc 940c 7005 jmp_ DO_NEXT
-
- ; ( addr len -- )
- ; MCU
- ; write len bytes to SPI from addr
- VE_N_SPIW:
-0004be ff05 .dw $ff05
-0004bf 216e
-0004c0 7073
-0004c1 0069 .db "n!spi",0
-0004c2 04a7 .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIW
- XT_N_SPIW:
-0004c3 04c4 .dw PFA_N_SPIW
- PFA_N_SPIW:
-0004c4 018c movw temp0, tosl
-0004c5 9189
-0004c6 9199 loadtos
-0004c7 01fc movw zl, tosl
-0004c8 01c8 movw tosl, temp0
- PFA_N_SPIW_LOOP:
-0004c9 9121 ld temp2, Z+
-0004ca bd2e out_ SPDR, temp2
- PFA_N_SPIW_LOOP1:
-0004cb b52d in_ temp2, SPSR
-0004cc ff27 sbrs temp2, SPIF
-0004cd cffd rjmp PFA_N_SPIW_LOOP1
-0004ce b52e in_ temp2, SPDR ; ignore the data
-0004cf 9701 sbiw tosl, 1
-0004d0 f7c1 brne PFA_N_SPIW_LOOP
-0004d1 9189
-0004d2 9199 loadtos
-0004d3 940c 7005 jmp_ DO_NEXT
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-0004d5 ff0b .dw $ff0b
-0004d6 7061
-0004d7 6c70
-0004d8 7574
-0004d9 6e72
-0004da 656b
-0004db 0079 .db "applturnkey",0
-0004dc 04be .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-0004dd 7001 .dw DO_COLON
- PFA_APPLTURNKEY:
-0004de 00cb .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-0004df 7479 .dw XT_INTON
- .endif
-0004e0 7b64 .dw XT_DOT_VER
-0004e1 77e2 .dw XT_SPACE
-0004e2 7540 .dw XT_F_CPU
-0004e3 703d .dw XT_DOLITERAL
-0004e4 03e8 .dw 1000
-0004e5 71c2 .dw XT_UMSLASHMOD
-0004e6 70f0 .dw XT_NIP
-0004e7 75dd .dw XT_DECIMAL
-0004e8 7722 .dw XT_DOT
-0004e9 776d .dw XT_DOSLITERAL
-0004ea 0004 .dw 4
-0004eb 486b
-0004ec 207a .db "kHz "
-0004ed 77a0 .dw XT_ITYPE
-0004ee 7020 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-0004ef ff0b .dw $ff0b
-0004f0 6573
-0004f1 2d74
-0004f2 7563
-0004f3 7272
-0004f4 6e65
-0004f5 0074 .db "set-current",0
-0004f6 04d5 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-0004f7 7001 .dw DO_COLON
- PFA_SET_CURRENT:
-0004f8 703d .dw XT_DOLITERAL
-0004f9 004a .dw CFG_CURRENT
-0004fa 733b .dw XT_STOREE
-0004fb 7020 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-0004fc ff08 .dw $ff08
-0004fd 6f77
-0004fe 6472
-0004ff 696c
-000500 7473 .db "wordlist"
-000501 04ef .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000502 7001 .dw DO_COLON
- PFA_WORDLIST:
-000503 75b7 .dw XT_EHERE
-000504 7154 .dw XT_ZERO
-000505 70cf .dw XT_OVER
-000506 733b .dw XT_STOREE
-000507 70b1 .dw XT_DUP
-000508 755e .dw XT_CELLPLUS
-000509 7b99 .dw XT_DOTO
-00050a 75b8 .dw PFA_EHERE
-00050b 7020 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-00050c ff0e .dw $ff0e
-00050d 6f66
-00050e 7472
-00050f 2d68
-000510 6f77
-000511 6472
-000512 696c
-000513 7473 .db "forth-wordlist"
-000514 04fc .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-000515 7048 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-000516 004c .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-000517 ff09 .dw $ff09
-000518 6573
-000519 2d74
-00051a 726f
-00051b 6564
-00051c 0072 .db "set-order",0
-00051d 050c .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-00051e 7001 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-00051f 703d .dw XT_DOLITERAL
-000520 004e .dw CFG_ORDERLISTLEN
-000521 03ee .dw XT_SET_STACK
-000522 7020 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000523 ff0f .dw $ff0f
-000524 6573
-000525 2d74
-000526 6572
-000527 6f63
-000528 6e67
-000529 7a69
-00052a 7265
-00052b 0073 .db "set-recognizers",0
-00052c 0517 .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-00052d 7001 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-00052e 703d .dw XT_DOLITERAL
-00052f 0060 .dw CFG_RECOGNIZERLISTLEN
-000530 03ee .dw XT_SET_STACK
-000531 7020 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000532 ff0f .dw $ff0f
-000533 6567
-000534 2d74
-000535 6572
-000536 6f63
-000537 6e67
-000538 7a69
-000539 7265
-00053a 0073 .db "get-recognizers",0
-00053b 0523 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-00053c 7001 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-00053d 703d .dw XT_DOLITERAL
-00053e 0060 .dw CFG_RECOGNIZERLISTLEN
-00053f 03cd .dw XT_GET_STACK
-000540 7020 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000541 ff04 .dw $ff04
-000542 6f63
-000543 6564 .db "code"
-000544 0532 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-000545 7001 .dw DO_COLON
- PFA_CODE:
-000546 019e .dw XT_DOCREATE
-000547 02fe .dw XT_REVEAL
-000548 75ae .dw XT_DP
-000549 7bab .dw XT_ICELLPLUS
-00054a 01cc .dw XT_COMMA
-00054b 7020 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-00054c ff08 .dw $ff08
-00054d 6e65
-00054e 2d64
-00054f 6f63
-000550 6564 .db "end-code"
-000551 0541 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-000552 7001 .dw DO_COLON
- PFA_ENDCODE:
-000553 01c1 .dw XT_COMPILE
-000554 940c .dw $940c
-000555 01c1 .dw XT_COMPILE
-000556 7005 .dw DO_NEXT
-000557 7020 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-000558 ff08 .dw $ff08
-000559 6d28
-00055a 7261
-00055b 656b
-00055c 2972 .db "(marker)"
-00055d 054c .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-00055e 706f .dw PFA_DOVALUE1
- PFA_MARKER:
-00055f 006c .dw EE_MARKER
-000560 7bb4 .dw XT_EDEFERFETCH
-000561 7bbe .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-000562 0008 .dw $0008
-000563 6f70
-000564 7473
-000565 6f70
-000566 656e .db "postpone"
-000567 0558 .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-000568 7001 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-000569 79b4 .dw XT_PARSENAME
-00056a 7acc .dw XT_FORTHRECOGNIZER
-00056b 7ad7 .dw XT_RECOGNIZE
-00056c 70b1 .dw XT_DUP
-00056d 70ff .dw XT_TO_R
-00056e 7bab .dw XT_ICELLPLUS
-00056f 7bab .dw XT_ICELLPLUS
-000570 73cb .dw XT_FETCHI
-000571 702a .dw XT_EXECUTE
-000572 70f6 .dw XT_R_FROM
-000573 7bab .dw XT_ICELLPLUS
-000574 73cb .dw XT_FETCHI
-000575 01cc .dw XT_COMMA
-000576 7020 .dw XT_EXIT
- .endif
- .include "words/2r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_2R_FETCH:
-000577 ff03 .dw $ff03
-000578 7232
-000579 0040 .db "2r@",0
-00057a 0562 .dw VE_HEAD
- .set VE_HEAD = VE_2R_FETCH
- XT_2R_FETCH:
-00057b 057c .dw PFA_2R_FETCH
- PFA_2R_FETCH:
-00057c 939a
-00057d 938a savetos
-00057e 91ef pop zl
-00057f 91ff pop zh
-000580 918f pop tosl
-000581 919f pop tosh
-000582 939f push tosh
-000583 938f push tosl
-000584 93ff push zh
-000585 93ef push zl
-000586 939a
-000587 938a savetos
-000588 01cf movw tosl, zl
-000589 940c 7005 jmp_ DO_NEXT
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-007001 93bf push XH
-007002 93af push XL ; PUSH IP
-007003 01db movw XL, wl
-007004 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-007005 14b2 cp isrflag, zerol
-007006 f469 brne DO_INTERRUPT
- .endif
-007007 01fd movw zl, XL ; READ IP
-007008 0fee
-007009 1fff
-00700a 9165
-00700b 9175 readflashcell wl, wh
-00700c 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00700d 01fb movw zl, wl
-00700e 0fee
-00700f 1fff
-007010 9105
-007011 9115 readflashcell temp0,temp1
-007012 01f8 movw zl, temp0
-007013 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-007014 939a
-007015 938a savetos
-007016 2d8b mov tosl, isrflag
-007017 2799 clr tosh
-007018 24bb clr isrflag
-007019 ea62 ldi wl, LOW(XT_ISREXEC)
-00701a e774 ldi wh, HIGH(XT_ISREXEC)
-00701b cff1 rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00701c ff04 .dw $ff04
-00701d 7865
-00701e 7469 .db "exit"
-00701f 0577 .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-007020 7021 .dw PFA_EXIT
- PFA_EXIT:
-007021 91af pop XL
-007022 91bf pop XH
-007023 cfe1 jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-007024 ff07 .dw $ff07
-007025 7865
-007026 6365
-007027 7475
-007028 0065 .db "execute",0
-007029 701c .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-00702a 702b .dw PFA_EXECUTE
- PFA_EXECUTE:
-00702b 01bc movw wl, tosl
-00702c 9189
-00702d 9199 loadtos
-00702e cfde jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00702f 7030 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-007030 01fd movw zl, XL
-007031 0fee
-007032 1fff
-007033 91a5
-007034 91b5 readflashcell XL,XH
-007035 cfcf jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-007036 7037 .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-007037 2b98 or tosh, tosl
-007038 9189
-007039 9199 loadtos
-00703a f3a9 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00703b 9611 adiw XL, 1
-00703c cfc8 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00703d 703e .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00703e 939a
-00703f 938a savetos
-007040 01fd movw zl, xl
-007041 0fee
-007042 1fff
-007043 9185
-007044 9195 readflashcell tosl,tosh
-007045 9611 adiw xl, 1
-007046 cfbe jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-007047 7048 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-007048 939a
-007049 938a savetos
-00704a 01fb movw zl, wl
-00704b 9631 adiw zl,1
-00704c 0fee
-00704d 1fff
-00704e 9185
-00704f 9195 readflashcell tosl,tosh
-007050 cfb4 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-007051 7052 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-007052 939a
-007053 938a savetos
-007054 01cb movw tosl, wl
-007055 9601 adiw tosl, 1
-007056 cfae jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-007057 7058 .dw PFA_DOUSER
- PFA_DOUSER:
-007058 939a
-007059 938a savetos
-00705a 01fb movw zl, wl
-00705b 9631 adiw zl, 1
-00705c 0fee
-00705d 1fff
-00705e 9185
-00705f 9195 readflashcell tosl,tosh
-007060 0d84 add tosl, upl
-007061 1d95 adc tosh, uph
-007062 cfa2 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-007063 ff07 .dw $ff07
-007064 7628
-007065 6c61
-007066 6575
-007067 0029 .db "(value)", 0
-007068 7024 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-007069 7001 .dw DO_COLON
- PFA_DOVALUE:
-00706a 019e .dw XT_DOCREATE
-00706b 02fe .dw XT_REVEAL
-00706c 01c1 .dw XT_COMPILE
-00706d 706f .dw PFA_DOVALUE1
-00706e 7020 .dw XT_EXIT
- PFA_DOVALUE1:
-00706f 940e 0317 call_ DO_DODOES
-007071 70b1 .dw XT_DUP
-007072 7bab .dw XT_ICELLPLUS
-007073 73cb .dw XT_FETCHI
-007074 702a .dw XT_EXECUTE
-007075 7020 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-007076 ff01 .dw $ff01
-007077 0040 .db "@",0
-007078 7063 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-007079 707a .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-00707a 01fc movw zl, tosl
- ; low byte is read before the high byte
-00707b 9181 ld tosl, z+
-00707c 9191 ld tosh, z+
-00707d cf87 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00707e ff01 .dw $ff01
-00707f 0021 .db "!",0
-007080 7076 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-007081 7082 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-007082 01fc movw zl, tosl
-007083 9189
-007084 9199 loadtos
- ; the high byte is written before the low byte
-007085 8391 std Z+1, tosh
-007086 8380 std Z+0, tosl
-007087 9189
-007088 9199 loadtos
-007089 cf7b jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-00708a ff02 .dw $ff02
-00708b 2163 .db "c!"
-00708c 707e .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00708d 708e .dw PFA_CSTORE
- PFA_CSTORE:
-00708e 01fc movw zl, tosl
-00708f 9189
-007090 9199 loadtos
-007091 8380 st Z, tosl
-007092 9189
-007093 9199 loadtos
-007094 cf70 jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-007095 ff02 .dw $ff02
-007096 4063 .db "c@"
-007097 708a .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-007098 7099 .dw PFA_CFETCH
- PFA_CFETCH:
-007099 01fc movw zl, tosl
-00709a 2799 clr tosh
-00709b 8180 ld tosl, Z
-00709c cf68 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00709d ff02 .dw $ff02
-00709e 7540 .db "@u"
-00709f 7095 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-0070a0 7001 .dw DO_COLON
- PFA_FETCHU:
-0070a1 7302 .dw XT_UP_FETCH
-0070a2 719d .dw XT_PLUS
-0070a3 7079 .dw XT_FETCH
-0070a4 7020 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-0070a5 ff02 .dw $ff02
-0070a6 7521 .db "!u"
-0070a7 709d .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-0070a8 7001 .dw DO_COLON
- PFA_STOREU:
-0070a9 7302 .dw XT_UP_FETCH
-0070aa 719d .dw XT_PLUS
-0070ab 7081 .dw XT_STORE
-0070ac 7020 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-0070ad ff03 .dw $ff03
-0070ae 7564
-0070af 0070 .db "dup",0
-0070b0 70a5 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-0070b1 70b2 .dw PFA_DUP
- PFA_DUP:
-0070b2 939a
-0070b3 938a savetos
-0070b4 cf50 jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-0070b5 ff04 .dw $ff04
-0070b6 643f
-0070b7 7075 .db "?dup"
-0070b8 70ad .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-0070b9 70ba .dw PFA_QDUP
- PFA_QDUP:
-0070ba 2f08 mov temp0, tosl
-0070bb 2b09 or temp0, tosh
-0070bc f011 breq PFA_QDUP1
-0070bd 939a
-0070be 938a savetos
- PFA_QDUP1:
-0070bf cf45 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-0070c0 ff04 .dw $ff04
-0070c1 7773
-0070c2 7061 .db "swap"
-0070c3 70b5 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-0070c4 70c5 .dw PFA_SWAP
- PFA_SWAP:
-0070c5 018c movw temp0, tosl
-0070c6 9189
-0070c7 9199 loadtos
-0070c8 931a st -Y, temp1
-0070c9 930a st -Y, temp0
-0070ca cf3a jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-0070cb ff04 .dw $ff04
-0070cc 766f
-0070cd 7265 .db "over"
-0070ce 70c0 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-0070cf 70d0 .dw PFA_OVER
- PFA_OVER:
-0070d0 939a
-0070d1 938a savetos
-0070d2 818a ldd tosl, Y+2
-0070d3 819b ldd tosh, Y+3
-
-0070d4 cf30 jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-0070d5 ff04 .dw $ff04
-0070d6 7264
-0070d7 706f .db "drop"
-0070d8 70cb .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-0070d9 70da .dw PFA_DROP
- PFA_DROP:
-0070da 9189
-0070db 9199 loadtos
-0070dc cf28 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-0070dd ff03 .dw $ff03
-0070de 6f72
-0070df 0074 .db "rot",0
-0070e0 70d5 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-0070e1 70e2 .dw PFA_ROT
- PFA_ROT:
-0070e2 018c movw temp0, tosl
-0070e3 9129 ld temp2, Y+
-0070e4 9139 ld temp3, Y+
-0070e5 9189
-0070e6 9199 loadtos
-
-0070e7 933a st -Y, temp3
-0070e8 932a st -Y, temp2
-0070e9 931a st -Y, temp1
-0070ea 930a st -Y, temp0
-
-0070eb cf19 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-0070ec ff03 .dw $ff03
-0070ed 696e
-0070ee 0070 .db "nip",0
-0070ef 70dd .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-0070f0 70f1 .dw PFA_NIP
- PFA_NIP:
-0070f1 9622 adiw yl, 2
-0070f2 cf12 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-0070f3 ff02 .dw $ff02
-0070f4 3e72 .db "r>"
-0070f5 70ec .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-0070f6 70f7 .dw PFA_R_FROM
- PFA_R_FROM:
-0070f7 939a
-0070f8 938a savetos
-0070f9 918f pop tosl
-0070fa 919f pop tosh
-0070fb cf09 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-0070fc ff02 .dw $ff02
-0070fd 723e .db ">r"
-0070fe 70f3 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-0070ff 7100 .dw PFA_TO_R
- PFA_TO_R:
-007100 939f push tosh
-007101 938f push tosl
-007102 9189
-007103 9199 loadtos
-007104 cf00 jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-007105 ff02 .dw $ff02
-007106 4072 .db "r@"
-007107 70fc .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-007108 7109 .dw PFA_R_FETCH
- PFA_R_FETCH:
-007109 939a
-00710a 938a savetos
-00710b 918f pop tosl
-00710c 919f pop tosh
-00710d 939f push tosh
-00710e 938f push tosl
-00710f cef5 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-007110 ff02 .dw $ff02
-007111 3e3c .db "<>"
-007112 7105 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-007113 7001 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-007114 7d7f
-007115 711a
-007116 7020 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-007117 ff02 .dw $ff02
-007118 3d30 .db "0="
-007119 7110 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-00711a 711b .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00711b 2b98 or tosh, tosl
-00711c f5d1 brne PFA_ZERO1
-00711d c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00711e ff02 .dw $ff02
-00711f 3c30 .db "0<"
-007120 7117 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-007121 7122 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-007122 fd97 sbrc tosh,7
-007123 c02a rjmp PFA_TRUE1
-007124 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-007125 ff02 .dw $ff02
-007126 3e30 .db "0>"
-007127 711e .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-007128 7129 .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-007129 1582 cp tosl, zerol
-00712a 0593 cpc tosh, zeroh
-00712b f15c brlt PFA_ZERO1
-00712c f151 brbs 1, PFA_ZERO1
-00712d c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00712e ff03 .dw $ff03
-00712f 3064
-007130 003e .db "d0>",0
-007131 7125 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-007132 7133 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-007133 1582 cp tosl, zerol
-007134 0593 cpc tosh, zeroh
-007135 9189
-007136 9199 loadtos
-007137 0582 cpc tosl, zerol
-007138 0593 cpc tosh, zeroh
-007139 f0ec brlt PFA_ZERO1
-00713a f0e1 brbs 1, PFA_ZERO1
-00713b c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00713c ff03 .dw $ff03
-00713d 3064
-00713e 003c .db "d0<",0
-00713f 712e .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-007140 7141 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-007141 9622 adiw Y,2
-007142 fd97 sbrc tosh,7
-007143 940c 714e jmp PFA_TRUE1
-007145 940c 7157 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-007147 ff04 .dw $ff04
-007148 7274
-007149 6575 .db "true"
-00714a 713c .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00714b 714c .dw PFA_TRUE
- PFA_TRUE:
-00714c 939a
-00714d 938a savetos
- PFA_TRUE1:
-00714e ef8f ser tosl
-00714f ef9f ser tosh
-007150 ceb4 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-007151 ff01 .dw $ff01
-007152 0030 .db "0",0
-007153 7147 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-007154 7155 .dw PFA_ZERO
- PFA_ZERO:
-007155 939a
-007156 938a savetos
- PFA_ZERO1:
-007157 01c1 movw tosl, zerol
-007158 ceac jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-007159 ff02 .dw $ff02
-00715a 3c75 .db "u<"
-00715b 7151 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00715c 715d .dw PFA_ULESS
- PFA_ULESS:
-00715d 9129 ld temp2, Y+
-00715e 9139 ld temp3, Y+
-00715f 1782 cp tosl, temp2
-007160 0793 cpc tosh, temp3
-007161 f3a8 brlo PFA_ZERO1
-007162 f3a1 brbs 1, PFA_ZERO1
-007163 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-007164 ff02 .dw $ff02
-007165 3e75 .db "u>"
-007166 7159 .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-007167 7001 .dw DO_COLON
- PFA_UGREATER:
- .endif
-007168 70c4 .DW XT_SWAP
-007169 715c .dw XT_ULESS
-00716a 7020 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00716b ff01 .dw $ff01
-00716c 003c .db "<",0
-00716d 7164 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00716e 716f .dw PFA_LESS
- PFA_LESS:
-00716f 9129 ld temp2, Y+
-007170 9139 ld temp3, Y+
-007171 1728 cp temp2, tosl
-007172 0739 cpc temp3, tosh
- PFA_LESSDONE:
-007173 f71c brge PFA_ZERO1
-007174 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-007175 ff01 .dw $ff01
-007176 003e .db ">",0
-007177 716b .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-007178 7179 .dw PFA_GREATER
- PFA_GREATER:
-007179 9129 ld temp2, Y+
-00717a 9139 ld temp3, Y+
-00717b 1728 cp temp2, tosl
-00717c 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00717d f2cc brlt PFA_ZERO1
-00717e f2c1 brbs 1, PFA_ZERO1
-00717f cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-007180 ff04 .dw $ff04
-007181 6f6c
-007182 3267 .db "log2"
-007183 7175 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-007184 7185 .dw PFA_LOG2
- PFA_LOG2:
-007185 01fc movw zl, tosl
-007186 2799 clr tosh
-007187 e180 ldi tosl, 16
- PFA_LOG2_1:
-007188 958a dec tosl
-007189 f022 brmi PFA_LOG2_2 ; wrong data
-00718a 0fee lsl zl
-00718b 1fff rol zh
-00718c f7d8 brcc PFA_LOG2_1
-00718d ce77 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00718e 959a dec tosh
-00718f ce75 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-007190 ff01 .dw $ff01
-007191 002d .db "-",0
-007192 7180 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-007193 7194 .dw PFA_MINUS
- PFA_MINUS:
-007194 9109 ld temp0, Y+
-007195 9119 ld temp1, Y+
-007196 1b08 sub temp0, tosl
-007197 0b19 sbc temp1, tosh
-007198 01c8 movw tosl, temp0
-007199 ce6b jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-00719a ff01 .dw $ff01
-00719b 002b .db "+",0
-00719c 7190 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00719d 719e .dw PFA_PLUS
- PFA_PLUS:
-00719e 9109 ld temp0, Y+
-00719f 9119 ld temp1, Y+
-0071a0 0f80 add tosl, temp0
-0071a1 1f91 adc tosh, temp1
-0071a2 ce62 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-0071a3 ff02 .dw $ff02
-0071a4 2a6d .db "m*"
-0071a5 719a .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-0071a6 71a7 .dw PFA_MSTAR
- PFA_MSTAR:
-0071a7 018c movw temp0, tosl
-0071a8 9189
-0071a9 9199 loadtos
-0071aa 019c movw temp2, tosl
- ; high cell ah*bh
-0071ab 0231 muls temp3, temp1
-0071ac 0170 movw temp4, r0
- ; low cell al*bl
-0071ad 9f20 mul temp2, temp0
-0071ae 01c0 movw tosl, r0
- ; signed ah*bl
-0071af 0330 mulsu temp3, temp0
-0071b0 08f3 sbc temp5, zeroh
-0071b1 0d90 add tosh, r0
-0071b2 1ce1 adc temp4, r1
-0071b3 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-0071b4 0312 mulsu temp1, temp2
-0071b5 08f3 sbc temp5, zeroh
-0071b6 0d90 add tosh, r0
-0071b7 1ce1 adc temp4, r1
-0071b8 1cf3 adc temp5, zeroh
-
-0071b9 939a
-0071ba 938a savetos
-0071bb 01c7 movw tosl, temp4
-0071bc ce48 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-0071bd ff06 .dw $ff06
-0071be 6d75
-0071bf 6d2f
-0071c0 646f .db "um/mod"
-0071c1 71a3 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-0071c2 71c3 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-0071c3 017c movw temp4, tosl
-
-0071c4 9129 ld temp2, Y+
-0071c5 9139 ld temp3, Y+
-
-0071c6 9109 ld temp0, Y+
-0071c7 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-0071c8 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-0071c9 2755 clr temp7
-0071ca 0f00 lsl temp0
-0071cb 1f11 rol temp1
-0071cc 1f22 rol temp2
-0071cd 1f33 rol temp3
-0071ce 1f55 rol temp7
-
- ; try subtracting divisor
-0071cf 152e cp temp2, temp4
-0071d0 053f cpc temp3, temp5
-0071d1 0552 cpc temp7,zerol
-
-0071d2 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-0071d3 9503 inc temp0
-0071d4 192e sub temp2, temp4
-0071d5 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-0071d6 954a dec temp6
-0071d7 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-0071d8 933a st -Y,temp3
-0071d9 932a st -Y,temp2
-
- ; put quotient on stack
-0071da 01c8 movw tosl, temp0
-0071db ce29 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-0071dc ff03 .dw $ff03
-0071dd 6d75
-0071de 002a .db "um*",0
-0071df 71bd .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-0071e0 71e1 .dw PFA_UMSTAR
- PFA_UMSTAR:
-0071e1 018c movw temp0, tosl
-0071e2 9189
-0071e3 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-0071e4 9f80 mul tosl,temp0
-0071e5 01f0 movw zl, r0
-0071e6 2722 clr temp2
-0071e7 2733 clr temp3
- ; middle bytes
-0071e8 9f90 mul tosh, temp0
-0071e9 0df0 add zh, r0
-0071ea 1d21 adc temp2, r1
-0071eb 1d33 adc temp3, zeroh
-
-0071ec 9f81 mul tosl, temp1
-0071ed 0df0 add zh, r0
-0071ee 1d21 adc temp2, r1
-0071ef 1d33 adc temp3, zeroh
-
-0071f0 9f91 mul tosh, temp1
-0071f1 0d20 add temp2, r0
-0071f2 1d31 adc temp3, r1
-0071f3 01cf movw tosl, zl
-0071f4 939a
-0071f5 938a savetos
-0071f6 01c9 movw tosl, temp2
-0071f7 ce0d jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-0071f8 ff06 .dw $ff06
-0071f9 6e69
-0071fa 6576
-0071fb 7472 .db "invert"
-0071fc 71dc .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-0071fd 71fe .dw PFA_INVERT
- PFA_INVERT:
-0071fe 9580 com tosl
-0071ff 9590 com tosh
-007200 ce04 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-007201 ff02 .dw $ff02
-007202 2f32 .db "2/"
-007203 71f8 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-007204 7205 .dw PFA_2SLASH
- PFA_2SLASH:
-007205 9595 asr tosh
-007206 9587 ror tosl
-007207 cdfd jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-007208 ff02 .dw $ff02
-007209 2a32 .db "2*"
-00720a 7201 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-00720b 720c .dw PFA_2STAR
- PFA_2STAR:
-00720c 0f88 lsl tosl
-00720d 1f99 rol tosh
-00720e cdf6 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-00720f ff03 .dw $ff03
-007210 6e61
-007211 0064 .db "and",0
-007212 7208 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-007213 7214 .dw PFA_AND
- PFA_AND:
-007214 9109 ld temp0, Y+
-007215 9119 ld temp1, Y+
-007216 2380 and tosl, temp0
-007217 2391 and tosh, temp1
-007218 cdec jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-007219 ff02 .dw $ff02
-00721a 726f .db "or"
-00721b 720f .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-00721c 721d .dw PFA_OR
- PFA_OR:
-00721d 9109 ld temp0, Y+
-00721e 9119 ld temp1, Y+
-00721f 2b80 or tosl, temp0
-007220 2b91 or tosh, temp1
-007221 cde3 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-007222 ff03 .dw $ff03
-007223 6f78
-007224 0072 .db "xor",0
-007225 7219 .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-007226 7227 .dw PFA_XOR
- PFA_XOR:
-007227 9109 ld temp0, Y+
-007228 9119 ld temp1, Y+
-007229 2780 eor tosl, temp0
-00722a 2791 eor tosh, temp1
-00722b cdd9 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-00722c ff02 .dw $ff02
-00722d 2b31 .db "1+"
-00722e 7222 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-00722f 7230 .dw PFA_1PLUS
- PFA_1PLUS:
-007230 9601 adiw tosl,1
-007231 cdd3 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-007232 ff02 .dw $ff02
-007233 2d31 .db "1-"
-007234 722c .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-007235 7236 .dw PFA_1MINUS
- PFA_1MINUS:
-007236 9701 sbiw tosl, 1
-007237 cdcd jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-007238 ff07 .dw $ff07
-007239 6e3f
-00723a 6765
-00723b 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-00723c 0065 .db "?negate"
-00723d 7232 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-00723e 7001 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-00723f 7121
-007240 7036 .DW XT_ZEROLESS,XT_DOCONDBRANCH
-007241 7243 DEST(QNEG1)
-007242 763f .DW XT_NEGATE
-007243 7020 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-007244 ff06 .dw $ff06
-007245 736c
-007246 6968
-007247 7466 .db "lshift"
-007248 7238 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-007249 724a .dw PFA_LSHIFT
- PFA_LSHIFT:
-00724a 01fc movw zl, tosl
-00724b 9189
-00724c 9199 loadtos
- PFA_LSHIFT1:
-00724d 9731 sbiw zl, 1
-00724e f01a brmi PFA_LSHIFT2
-00724f 0f88 lsl tosl
-007250 1f99 rol tosh
-007251 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-007252 cdb2 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-007253 ff06 .dw $ff06
-007254 7372
-007255 6968
-007256 7466 .db "rshift"
-007257 7244 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-007258 7259 .dw PFA_RSHIFT
- PFA_RSHIFT:
-007259 01fc movw zl, tosl
-00725a 9189
-00725b 9199 loadtos
- PFA_RSHIFT1:
-00725c 9731 sbiw zl, 1
-00725d f01a brmi PFA_RSHIFT2
-00725e 9596 lsr tosh
-00725f 9587 ror tosl
-007260 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-007261 cda3 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-007262 ff02 .dw $ff02
-007263 212b .db "+!"
-007264 7253 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-007265 7266 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-007266 01fc movw zl, tosl
-007267 9189
-007268 9199 loadtos
-007269 8120 ldd temp2, Z+0
-00726a 8131 ldd temp3, Z+1
-00726b 0f82 add tosl, temp2
-00726c 1f93 adc tosh, temp3
-00726d 8380 std Z+0, tosl
-00726e 8391 std Z+1, tosh
-00726f 9189
-007270 9199 loadtos
-007271 cd93 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-007272 ff03 .dw $ff03
-007273 7072
-007274 0040 .db "rp@",0
-007275 7262 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-007276 7277 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-007277 939a
-007278 938a savetos
-007279 b78d in tosl, SPL
-00727a b79e in tosh, SPH
-00727b cd89 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-00727c ff03 .dw $ff03
-00727d 7072
-00727e 0021 .db "rp!",0
-00727f 7272 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-007280 7281 .dw PFA_RP_STORE
- PFA_RP_STORE:
-007281 b72f in temp2, SREG
-007282 94f8 cli
-007283 bf8d out SPL, tosl
-007284 bf9e out SPH, tosh
-007285 bf2f out SREG, temp2
-007286 9189
-007287 9199 loadtos
-007288 cd7c jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-007289 ff03 .dw $ff03
-00728a 7073
-00728b 0040 .db "sp@",0
-00728c 727c .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-00728d 728e .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-00728e 939a
-00728f 938a savetos
-007290 01ce movw tosl, yl
-007291 cd73 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-007292 ff03 .dw $ff03
-007293 7073
-007294 0021 .db "sp!",0
-007295 7289 .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-007296 7297 .dw PFA_SP_STORE
- PFA_SP_STORE:
-007297 01ec movw yl, tosl
-007298 9189
-007299 9199 loadtos
-00729a cd6a jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-00729b 729c .dw PFA_DODO
- PFA_DODO:
-00729c 9129 ld temp2, Y+
-00729d 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-00729e e8e0 ldi zl, $80
-00729f 0f3e add temp3, zl
-0072a0 1b82 sub tosl, temp2
-0072a1 0b93 sbc tosh, temp3
-
-0072a2 933f push temp3
-0072a3 932f push temp2 ; limit ( --> limit + $8000)
-0072a4 939f push tosh
-0072a5 938f push tosl ; start -> index ( --> index - (limit - $8000)
-0072a6 9189
-0072a7 9199 loadtos
-0072a8 cd5c jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-0072a9 ff01 .dw $FF01
-0072aa 0069 .db "i",0
-0072ab 7292 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-0072ac 72ad .dw PFA_I
- PFA_I:
-0072ad 939a
-0072ae 938a savetos
-0072af 918f pop tosl
-0072b0 919f pop tosh ; index
-0072b1 91ef pop zl
-0072b2 91ff pop zh ; limit
-0072b3 93ff push zh
-0072b4 93ef push zl
-0072b5 939f push tosh
-0072b6 938f push tosl
-0072b7 0f8e add tosl, zl
-0072b8 1f9f adc tosh, zh
-0072b9 cd4b jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-0072ba 72bb .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-0072bb 91ef pop zl
-0072bc 91ff pop zh
-0072bd 0fe8 add zl, tosl
-0072be 1ff9 adc zh, tosh
-0072bf 9189
-0072c0 9199 loadtos
-0072c1 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-0072c2 93ff push zh
-0072c3 93ef push zl
-0072c4 cd6b rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-0072c5 910f pop temp0
-0072c6 911f pop temp1 ; remove limit
-0072c7 9611 adiw xl, 1 ; skip branch-back address
-0072c8 cd3c jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-0072c9 72ca .dw PFA_DOLOOP
- PFA_DOLOOP:
-0072ca 91ef pop zl
-0072cb 91ff pop zh
-0072cc 9631 adiw zl,1
-0072cd f3bb brvs PFA_DOPLUSLOOP_LEAVE
-0072ce cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-0072cf ff06 .dw $ff06
-0072d0 6e75
-0072d1 6f6c
-0072d2 706f .db "unloop"
-0072d3 72a9 .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-0072d4 72d5 .dw PFA_UNLOOP
- PFA_UNLOOP:
-0072d5 911f pop temp1
-0072d6 910f pop temp0
-0072d7 911f pop temp1
-0072d8 910f pop temp0
-0072d9 cd2b jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-0072da ff06 .dw $ff06
-0072db 6d63
-0072dc 766f
-0072dd 3e65 .db "cmove>"
-0072de 72cf .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-0072df 72e0 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-0072e0 93bf push xh
-0072e1 93af push xl
-0072e2 91e9 ld zl, Y+
-0072e3 91f9 ld zh, Y+ ; addr-to
-0072e4 91a9 ld xl, Y+
-0072e5 91b9 ld xh, Y+ ; addr-from
-0072e6 2f09 mov temp0, tosh
-0072e7 2b08 or temp0, tosl
-0072e8 f041 brbs 1, PFA_CMOVE_G1
-0072e9 0fe8 add zl, tosl
-0072ea 1ff9 adc zh, tosh
-0072eb 0fa8 add xl, tosl
-0072ec 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-0072ed 911e ld temp1, -X
-0072ee 9312 st -Z, temp1
-0072ef 9701 sbiw tosl, 1
-0072f0 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-0072f1 91af pop xl
-0072f2 91bf pop xh
-0072f3 9189
-0072f4 9199 loadtos
-0072f5 cd0f jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-0072f6 ff02 .dw $ff02
-0072f7 3c3e .db "><"
-0072f8 72da .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-0072f9 72fa .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-0072fa 2f09 mov temp0, tosh
-0072fb 2f98 mov tosh, tosl
-0072fc 2f80 mov tosl, temp0
-0072fd cd07 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-0072fe ff03 .dw $ff03
-0072ff 7075
-007300 0040 .db "up@",0
-007301 72f6 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-007302 7303 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-007303 939a
-007304 938a savetos
-007305 01c2 movw tosl, upl
-007306 ccfe jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-007307 ff03 .dw $ff03
-007308 7075
-007309 0021 .db "up!",0
-00730a 72fe .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-00730b 730c .dw PFA_UP_STORE
- PFA_UP_STORE:
-00730c 012c movw upl, tosl
-00730d 9189
-00730e 9199 loadtos
-00730f ccf5 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-007310 ff03 .dw $ff03
-007311 6d31
-007312 0073 .db "1ms",0
-007313 7307 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-007314 7315 .dw PFA_1MS
- PFA_1MS:
-007315 eae0
-007316 e0ff
-007317 9731
-007318 f7f1 delay 1000
-007319 cceb jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-00731a ff03 .dw $ff03
-00731b 3e32
-00731c 0072 .db "2>r",0
-00731d 7310 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-00731e 731f .dw PFA_2TO_R
- PFA_2TO_R:
-00731f 01fc movw zl, tosl
-007320 9189
-007321 9199 loadtos
-007322 939f push tosh
-007323 938f push tosl
-007324 93ff push zh
-007325 93ef push zl
-007326 9189
-007327 9199 loadtos
-007328 ccdc jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-007329 ff03 .dw $ff03
-00732a 7232
-00732b 003e .db "2r>",0
-00732c 731a .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-00732d 732e .dw PFA_2R_FROM
- PFA_2R_FROM:
-00732e 939a
-00732f 938a savetos
-007330 91ef pop zl
-007331 91ff pop zh
-007332 918f pop tosl
-007333 919f pop tosh
-007334 939a
-007335 938a savetos
-007336 01cf movw tosl, zl
-007337 cccd jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-007338 ff02 .dw $ff02
-007339 6521 .db "!e"
-00733a 7329 .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-00733b 733c .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-00733c 01fc movw zl, tosl
-00733d 9189
-00733e 9199 loadtos
-00733f b72f in_ temp2, SREG
-007340 94f8 cli
-007341 d028 rcall PFA_FETCHE2
-007342 b500 in_ temp0, EEDR
-007343 1708 cp temp0,tosl
-007344 f009 breq PFA_STOREE3
-007345 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-007346 9631 adiw zl,1
-007347 d022 rcall PFA_FETCHE2
-007348 b500 in_ temp0, EEDR
-007349 1709 cp temp0,tosh
-00734a f011 breq PFA_STOREE4
-00734b 2f89 mov tosl, tosh
-00734c d004 rcall PFA_STOREE1
- PFA_STOREE4:
-00734d bf2f out_ SREG, temp2
-00734e 9189
-00734f 9199 loadtos
-007350 ccb4 jmp_ DO_NEXT
-
- PFA_STOREE1:
-007351 99f9 sbic EECR, EEPE
-007352 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-007353 b707 in_ temp0, SPMCSR
-007354 fd00 sbrc temp0,SPMEN
-007355 cffd rjmp PFA_STOREE2
-
-007356 bdf2 out_ EEARH,zh
-007357 bde1 out_ EEARL,zl
-007358 bd80 out_ EEDR, tosl
-007359 9afa sbi EECR,EEMPE
-00735a 9af9 sbi EECR,EEPE
-
-00735b 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-00735c ff02 .dw $ff02
-00735d 6540 .db "@e"
-00735e 7338 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-00735f 7360 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-007360 b72f in_ temp2, SREG
-007361 94f8 cli
-007362 01fc movw zl, tosl
-007363 d006 rcall PFA_FETCHE2
-007364 b580 in_ tosl, EEDR
-
-007365 9631 adiw zl,1
-
-007366 d003 rcall PFA_FETCHE2
-007367 b590 in_ tosh, EEDR
-007368 bf2f out_ SREG, temp2
-007369 cc9b jmp_ DO_NEXT
-
- PFA_FETCHE2:
-00736a 99f9 sbic EECR, EEPE
-00736b cffe rjmp PFA_FETCHE2
-
-00736c bdf2 out_ EEARH,zh
-00736d bde1 out_ EEARL,zl
-
-00736e 9af8 sbi EECR,EERE
-00736f 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-007370 ff02 .dw $ff02
-007371 6921 .db "!i"
-007372 735c .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-007373 7c13 .dw PFA_DODEFER1
- PFA_STOREI:
-007374 006a .dw EE_STOREI
-007375 7bb4 .dw XT_EDEFERFETCH
-007376 7bbe .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-007377 ff09 .dw $ff09
-007378 2128
-007379 2d69
-00737a 726e
-00737b 7777
-00737c 0029 .db "(!i-nrww)",0
-00737d 7370 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-00737e 737f .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-00737f b71f in temp1,SREG
-007380 931f push temp1
-007381 94f8 cli
-
-007382 019c movw temp2, tosl ; save the (word) address
-007383 9189
-007384 9199 loadtos ; get the new value for the flash cell
-007385 93af push xl
-007386 93bf push xh
-007387 93cf push yl
-007388 93df push yh
-007389 d009 rcall DO_STOREI_atmega
-00738a 91df pop yh
-00738b 91cf pop yl
-00738c 91bf pop xh
-00738d 91af pop xl
- ; finally clear the stack
-00738e 9189
-00738f 9199 loadtos
-007390 911f pop temp1
- ; restore status register (and interrupt enable flag)
-007391 bf1f out SREG,temp1
-
-007392 cc72 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-007393 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-007394 94e0 com temp4
-007395 94f0 com temp5
-007396 218e and tosl, temp4
-007397 219f and tosh, temp5
-007398 2b98 or tosh, tosl
-007399 f019 breq DO_STOREI_writepage
-00739a 01f9 movw zl, temp2
-00739b e002 ldi temp0,(1<<PGERS)
-00739c d020 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-00739d 01f9 movw zl, temp2
-00739e e004 ldi temp0,(1<<PGWRT)
-00739f d01d rcall dospm
-
- ; reenable RWW section
-0073a0 01f9 movw zl, temp2
-0073a1 e100 ldi temp0,(1<<RWWSRE)
-0073a2 d01a rcall dospm
-0073a3 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-0073a4 01f9 movw zl, temp2
- ; get the beginning of page
-0073a5 78e0 andi zl,low(pagemask)
-0073a6 7fff andi zh,high(pagemask)
-0073a7 01ef movw y, z
- ; loop counter (in words)
-0073a8 e8a0 ldi xl,low(pagesize)
-0073a9 e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-0073aa 01fe movw z, y
-0073ab 0fee
-0073ac 1fff
-0073ad 9145
-0073ae 9155 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-0073af 01fe movw z, y
-0073b0 17e2 cp zl, temp2
-0073b1 07f3 cpc zh, temp3
-0073b2 f011 breq pageload_newdata
-0073b3 010a movw r0, temp6
-0073b4 c002 rjmp pageload_cont
- pageload_newdata:
-0073b5 017a movw temp4, temp6
-0073b6 010c movw r0, tosl
- pageload_cont:
-0073b7 2700 clr temp0
-0073b8 d004 rcall dospm
-0073b9 9621 adiw y, 1
-0073ba 9711 sbiw x, 1
-0073bb f771 brne pageload_loop
-
- pageload_done:
-0073bc 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-0073bd 99f9 sbic EECR, EEPE
-0073be cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-0073bf b717 in_ temp1, SPMCSR
-0073c0 fd10 sbrc temp1, SPMEN
-0073c1 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-0073c2 0fee
-0073c3 1fff writeflashcell
- ; execute spm
-0073c4 6001 ori temp0, (1<<SPMEN)
-0073c5 bf07 out_ SPMCSR,temp0
-0073c6 95e8 spm
-0073c7 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-0073c8 ff02 .dw $ff02
-0073c9 6940 .db "@i"
-0073ca 7377 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-0073cb 73cc .dw PFA_FETCHI
- PFA_FETCHI:
-0073cc 01fc movw zl, tosl
-0073cd 0fee
-0073ce 1fff
-0073cf 9185
-0073d0 9195 readflashcell tosl,tosh
-0073d1 cc33 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .include "dict/core_8k.inc"
-
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-0073d2 ff03 .dw $ff03
-0073d3 3e6e
-0073d4 0072 .db "n>r",0
-0073d5 73c8 .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-0073d6 73d7 .dw PFA_N_TO_R
- PFA_N_TO_R:
-0073d7 01fc movw zl, tosl
-0073d8 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-0073d9 9189
-0073da 9199 loadtos
-0073db 939f push tosh
-0073dc 938f push tosl
-0073dd 950a dec temp0
-0073de f7d1 brne PFA_N_TO_R1
-0073df 93ef push zl
-0073e0 93ff push zh
-0073e1 9189
-0073e2 9199 loadtos
-0073e3 cc21 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-0073e4 ff03 .dw $ff03
-0073e5 726e
-0073e6 003e .db "nr>",0
-0073e7 73d2 .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-0073e8 73e9 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-0073e9 939a
-0073ea 938a savetos
-0073eb 91ff pop zh
-0073ec 91ef pop zl
-0073ed 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-0073ee 918f pop tosl
-0073ef 919f pop tosh
-0073f0 939a
-0073f1 938a savetos
-0073f2 950a dec temp0
-0073f3 f7d1 brne PFA_N_R_FROM1
-0073f4 01cf movw tosl, zl
-0073f5 cc0f jmp_ DO_NEXT
-
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-0073f6 ff03 .dw $ff03
-0073f7 3264
-0073f8 002a .db "d2*",0
-0073f9 73e4 .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-0073fa 73fb .dw PFA_D2STAR
- PFA_D2STAR:
-0073fb 9109 ld temp0, Y+
-0073fc 9119 ld temp1, Y+
-0073fd 0f00 lsl temp0
-0073fe 1f11 rol temp1
-0073ff 1f88 rol tosl
-007400 1f99 rol tosh
-007401 931a st -Y, temp1
-007402 930a st -Y, temp0
-007403 cc01 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-007404 ff03 .dw $ff03
-007405 3264
-007406 002f .db "d2/",0
-007407 73f6 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-007408 7409 .dw PFA_D2SLASH
- PFA_D2SLASH:
-007409 9109 ld temp0, Y+
-00740a 9119 ld temp1, Y+
-00740b 9595 asr tosh
-00740c 9587 ror tosl
-00740d 9517 ror temp1
-00740e 9507 ror temp0
-00740f 931a st -Y, temp1
-007410 930a st -Y, temp0
-007411 cbf3 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-007412 ff02 .dw $ff02
-007413 2b64 .db "d+"
-007414 7404 .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-007415 7416 .dw PFA_DPLUS
- PFA_DPLUS:
-007416 9129 ld temp2, Y+
-007417 9139 ld temp3, Y+
-
-007418 90e9 ld temp4, Y+
-007419 90f9 ld temp5, Y+
-00741a 9149 ld temp6, Y+
-00741b 9159 ld temp7, Y+
-
-00741c 0f24 add temp2, temp6
-00741d 1f35 adc temp3, temp7
-00741e 1d8e adc tosl, temp4
-00741f 1d9f adc tosh, temp5
-
-007420 933a st -Y, temp3
-007421 932a st -Y, temp2
-007422 cbe2 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-007423 ff02 .dw $ff02
-007424 2d64 .db "d-"
-007425 7412 .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-007426 7427 .dw PFA_DMINUS
- PFA_DMINUS:
-007427 9129 ld temp2, Y+
-007428 9139 ld temp3, Y+
-
-007429 90e9 ld temp4, Y+
-00742a 90f9 ld temp5, Y+
-00742b 9149 ld temp6, Y+
-00742c 9159 ld temp7, Y+
-
-00742d 1b42 sub temp6, temp2
-00742e 0b53 sbc temp7, temp3
-00742f 0ae8 sbc temp4, tosl
-007430 0af9 sbc temp5, tosh
-
-007431 935a st -Y, temp7
-007432 934a st -Y, temp6
-007433 01c7 movw tosl, temp4
-007434 cbd0 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-007435 ff07 .dw $ff07
-007436 6964
-007437 766e
-007438 7265
-007439 0074 .db "dinvert",0
-00743a 7423 .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-00743b 743c .dw PFA_DINVERT
- PFA_DINVERT:
-00743c 9109 ld temp0, Y+
-00743d 9119 ld temp1, Y+
-00743e 9580 com tosl
-00743f 9590 com tosh
-007440 9500 com temp0
-007441 9510 com temp1
-007442 931a st -Y, temp1
-007443 930a st -Y, temp0
-007444 cbc0 jmp_ DO_NEXT
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-007445 ff02 .dw $ff02
-007446 2e75 .db "u."
-007447 7435 .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-007448 7001 .dw DO_COLON
- PFA_UDOT:
- .endif
-007449 7154 .dw XT_ZERO
-00744a 772a .dw XT_UDDOT
-00744b 7020 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-00744c ff03 .dw $ff03
-00744d 2e75
-00744e 0072 .db "u.r",0
-00744f 7445 .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-007450 7001 .dw DO_COLON
- PFA_UDOTR:
- .endif
-007451 7154 .dw XT_ZERO
-007452 70c4 .dw XT_SWAP
-007453 7733 .dw XT_UDDOTR
-007454 7020 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-007455 ff0d .dw $ff0d
-007456 6873
-007457 776f
-007458 772d
-007459 726f
-00745a 6c64
-00745b 7369
-00745c 0074 .db "show-wordlist",0
-00745d 744c .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-00745e 7001 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-00745f 703d .dw XT_DOLITERAL
-007460 7464 .dw XT_SHOWWORD
-007461 70c4 .dw XT_SWAP
-007462 7c57 .dw XT_TRAVERSEWORDLIST
-007463 7020 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-007464 7001 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-007465 7c72 .dw XT_NAME2STRING
-007466 77a0 .dw XT_ITYPE
-007467 77e2 .dw XT_SPACE ; ( -- addr n)
-007468 714b .dw XT_TRUE
-007469 7020 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-00746a ff05 .dw $ff05
-00746b 6f77
-00746c 6472
-00746d 0073 .db "words",0
-00746e 7455 .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-00746f 7001 .dw DO_COLON
- PFA_WORDS:
- .endif
-007470 703d .dw XT_DOLITERAL
-007471 0050 .dw CFG_ORDERLISTLEN+2
-007472 735f .dw XT_FETCHE
-007473 745e .dw XT_SHOWWORDLIST
-007474 7020 .dw XT_EXIT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-007475 ff04 .dw $ff04
-007476 692b
-007477 746e .db "+int"
-007478 746a .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-007479 747a .dw PFA_INTON
- PFA_INTON:
-00747a 9478 sei
-00747b cb89 jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-00747c ff04 .dw $ff04
-00747d 692d
-00747e 746e .db "-int"
-00747f 7475 .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-007480 7481 .dw PFA_INTOFF
- PFA_INTOFF:
-007481 94f8 cli
-007482 cb82 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-007483 ff04 .dw $ff04
-007484 6e69
-007485 2174 .db "int!"
-007486 747c .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-007487 7001 .dw DO_COLON
- PFA_INTSTORE:
-007488 703d .dw XT_DOLITERAL
-007489 0000 .dw intvec
-00748a 719d .dw XT_PLUS
-00748b 733b .dw XT_STOREE
-00748c 7020 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-00748d ff04 .dw $ff04
-00748e 6e69
-00748f 4074 .db "int@"
-007490 7483 .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-007491 7001 .dw DO_COLON
- PFA_INTFETCH:
-007492 703d .dw XT_DOLITERAL
-007493 0000 .dw intvec
-007494 719d .dw XT_PLUS
-007495 735f .dw XT_FETCHE
-007496 7020 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-007497 ff08 .dw $ff08
-007498 6e69
-007499 2d74
-00749a 7274
-00749b 7061 .db "int-trap"
-00749c 748d .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-00749d 749e .dw PFA_INTTRAP
- PFA_INTTRAP:
-00749e 2eb8 mov isrflag, tosl
-00749f 9189
-0074a0 9199 loadtos
-0074a1 cb63 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-0074a2 7001 .dw DO_COLON
- PFA_ISREXEC:
-0074a3 7491 .dw XT_INTFETCH
-0074a4 702a .dw XT_EXECUTE
-0074a5 74a7 .dw XT_ISREND
-0074a6 7020 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-0074a7 74a8 .dw PFA_ISREND
- PFA_ISREND:
-0074a8 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-0074a9 cb5b jmp_ DO_NEXT
- PFA_ISREND1:
-0074aa 9518 reti
- .endif
-
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-0074ab ff04 .dw $ff04
-0074ac 6970
-0074ad 6b63 .db "pick"
-0074ae 7497 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-0074af 7001 .dw DO_COLON
- PFA_PICK:
- .endif
-0074b0 722f .dw XT_1PLUS
-0074b1 7558 .dw XT_CELLS
-0074b2 728d .dw XT_SP_FETCH
-0074b3 719d .dw XT_PLUS
-0074b4 7079 .dw XT_FETCH
-0074b5 7020 .dw XT_EXIT
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-0074b6 0002 .dw $0002
-0074b7 222e .db ".",$22
-0074b8 74ab .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-0074b9 7001 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-0074ba 74c1 .dw XT_SQUOTE
-0074bb 01c1 .dw XT_COMPILE
-0074bc 77a0 .dw XT_ITYPE
-0074bd 7020 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-0074be 0002 .dw $0002
-0074bf 2273 .db "s",$22
-0074c0 74b6 .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-0074c1 7001 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-0074c2 703d .dw XT_DOLITERAL
-0074c3 0022 .dw 34 ; 0x22
-0074c4 7987 .dw XT_PARSE ; ( -- addr n)
-0074c5 754b .dw XT_STATE
-0074c6 7079 .dw XT_FETCH
-0074c7 7036 .dw XT_DOCONDBRANCH
-0074c8 74ca DEST(PFA_SQUOTE1)
-0074c9 01ed .dw XT_SLITERAL
- PFA_SQUOTE1:
-0074ca 7020 .dw XT_EXIT
-
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-0074cb ff04 .dw $ff04
-0074cc 6966
-0074cd 6c6c .db "fill"
-0074ce 74be .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-0074cf 7001 .dw DO_COLON
- PFA_FILL:
-0074d0 70e1 .dw XT_ROT
-0074d1 70e1 .dw XT_ROT
-0074d2 70b9
-0074d3 7036 .dw XT_QDUP,XT_DOCONDBRANCH
-0074d4 74dc DEST(PFA_FILL2)
-0074d5 7d5e .dw XT_BOUNDS
-0074d6 729b .dw XT_DODO
- PFA_FILL1:
-0074d7 70b1 .dw XT_DUP
-0074d8 72ac .dw XT_I
-0074d9 708d .dw XT_CSTORE ; ( -- c c-addr)
-0074da 72c9 .dw XT_DOLOOP
-0074db 74d7 .dw PFA_FILL1
- PFA_FILL2:
-0074dc 70d9 .dw XT_DROP
-0074dd 7020 .dw XT_EXIT
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-0074de ff0b .dw $ff0b
-0074df 6e65
-0074e0 6976
-0074e1 6f72
-0074e2 6d6e
-0074e3 6e65
-0074e4 0074 .db "environment",0
-0074e5 74cb .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-0074e6 7048 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-0074e7 0048 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-0074e8 ff09 .dw $ff09
-0074e9 6f77
-0074ea 6472
-0074eb 696c
-0074ec 7473
-0074ed 0073 .db "wordlists",0
-0074ee 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-0074ef 7001 .dw DO_COLON
- PFA_ENVWORDLISTS:
-0074f0 703d .dw XT_DOLITERAL
-0074f1 0008 .dw NUMWORDLISTS
-0074f2 7020 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-0074f3 ff04 .dw $ff04
-0074f4 702f
-0074f5 6461 .db "/pad"
-0074f6 74e8 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-0074f7 7001 .dw DO_COLON
- PFA_ENVSLASHPAD:
-0074f8 728d .dw XT_SP_FETCH
-0074f9 7584 .dw XT_PAD
-0074fa 7193 .dw XT_MINUS
-0074fb 7020 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-0074fc ff05 .dw $ff05
-0074fd 682f
-0074fe 6c6f
-0074ff 0064 .db "/hold",0
-007500 74f3 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-007501 7001 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-007502 7584 .dw XT_PAD
-007503 75bf .dw XT_HERE
-007504 7193 .dw XT_MINUS
-007505 7020 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-007506 ff0a .dw $ff0a
-007507 6f66
-007508 7472
-007509 2d68
-00750a 616e
-00750b 656d .db "forth-name"
-00750c 74fc .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-00750d 7001 .dw DO_COLON
- PFA_EN_FORTHNAME:
-00750e 776d .dw XT_DOSLITERAL
-00750f 0007 .dw 7
- .endif
-007510 6d61
-007511 6f66
-007512 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-007513 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-007514 7020 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-007515 ff07 .dw $ff07
-007516 6576
-007517 7372
-007518 6f69
-007519 006e .db "version",0
-00751a 7506 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-00751b 7001 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-00751c 703d .dw XT_DOLITERAL
-00751d 0041 .dw 65
-00751e 7020 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-00751f ff03 .dw $ff03
-007520 7063
-007521 0075 .db "cpu",0
-007522 7515 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-007523 7001 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-007524 703d .dw XT_DOLITERAL
-007525 003b .dw mcu_name
-007526 77cc .dw XT_ICOUNT
-007527 7020 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-007528 ff08 .dw $ff08
-007529 636d
-00752a 2d75
-00752b 6e69
-00752c 6f66 .db "mcu-info"
-00752d 751f .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-00752e 7001 .dw DO_COLON
- PFA_EN_MCUINFO:
-00752f 703d .dw XT_DOLITERAL
-007530 0037 .dw mcu_info
-007531 7020 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-007532 ff05 .dw $ff05
-007533 752f
-007534 6573
-007535 0072 .db "/user",0
-007536 7528 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-007537 7001 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-007538 703d .dw XT_DOLITERAL
-007539 002c .dw SYSUSERSIZE + APPUSERSIZE
-00753a 7020 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-00753b ff05 .dw $ff05
-00753c 5f66
-00753d 7063
-00753e 0075 .db "f_cpu",0
-00753f 74de .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-007540 7001 .dw DO_COLON
- PFA_F_CPU:
- .endif
-007541 703d .dw XT_DOLITERAL
-007542 2400 .dw (F_CPU % 65536)
-007543 703d .dw XT_DOLITERAL
-007544 00f4 .dw (F_CPU / 65536)
-007545 7020 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-007546 ff05 .dw $ff05
-007547 7473
-007548 7461
-007549 0065 .db "state",0
-00754a 753b .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-00754b 7048 .dw PFA_DOVARIABLE
- PFA_STATE:
-00754c 0136 .dw ram_state
-
- .dseg
-000136 ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-00754d ff04 .dw $ff04
-00754e 6162
-00754f 6573 .db "base"
-007550 7546 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-007551 7058 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-007552 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-007553 ff05 .dw $ff05
-007554 6563
-007555 6c6c
-007556 0073 .db "cells",0
-007557 754d .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-007558 720c .dw PFA_2STAR
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-007559 ff05 .dw $ff05
-00755a 6563
-00755b 6c6c
-00755c 002b .db "cell+",0
-00755d 7553 .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-00755e 755f .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-00755f 9602 adiw tosl, CELLSIZE
-007560 caa4 jmp_ DO_NEXT
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-007561 ff04 .dw $ff04
-007562 6432
-007563 7075 .db "2dup"
-007564 7559 .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-007565 7001 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-007566 70cf .dw XT_OVER
-007567 70cf .dw XT_OVER
-007568 7020 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-007569 ff05 .dw $ff05
-00756a 6432
-00756b 6f72
-00756c 0070 .db "2drop",0
-00756d 7561 .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-00756e 7001 .dw DO_COLON
- PFA_2DROP:
- .endif
-00756f 70d9 .dw XT_DROP
-007570 70d9 .dw XT_DROP
-007571 7020 .dw XT_EXIT
-
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-007572 ff04 .dw $ff04
-007573 7574
-007574 6b63 .db "tuck"
-007575 7569 .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-007576 7001 .dw DO_COLON
- PFA_TUCK:
- .endif
-007577 70c4 .dw XT_SWAP
-007578 70cf .dw XT_OVER
-007579 7020 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-00757a ff03 .dw $ff03
-00757b 693e
-00757c 006e .db ">in",0
-00757d 7572 .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-00757e 7058 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-00757f 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-007580 ff03 .dw $ff03
-007581 6170
-007582 0064 .db "pad",0
-007583 757a .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-007584 7001 .dw DO_COLON
- PFA_PAD:
- .endif
-007585 75bf .dw XT_HERE
-007586 703d .dw XT_DOLITERAL
-007587 0028 .dw 40
-007588 719d .dw XT_PLUS
-007589 7020 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-00758a ff04 .dw $ff04
-00758b 6d65
-00758c 7469 .db "emit"
-00758d 7580 .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-00758e 7c13 .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-00758f 000e .dw USER_EMIT
-007590 7bdc .dw XT_UDEFERFETCH
-007591 7be8 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-007592 ff05 .dw $ff05
-007593 6d65
-007594 7469
-007595 003f .db "emit?",0
-007596 758a .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-007597 7c13 .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-007598 0010 .dw USER_EMITQ
-007599 7bdc .dw XT_UDEFERFETCH
-00759a 7be8 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-00759b ff03 .dw $ff03
-00759c 656b
-00759d 0079 .db "key",0
-00759e 7592 .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-00759f 7c13 .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-0075a0 0012 .dw USER_KEY
-0075a1 7bdc .dw XT_UDEFERFETCH
-0075a2 7be8 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-0075a3 ff04 .dw $ff04
-0075a4 656b
-0075a5 3f79 .db "key?"
-0075a6 759b .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-0075a7 7c13 .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-0075a8 0014 .dw USER_KEYQ
-0075a9 7bdc .dw XT_UDEFERFETCH
-0075aa 7be8 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-0075ab ff02 .dw $ff02
-0075ac 7064 .db "dp"
-0075ad 75a3 .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-0075ae 706f .dw PFA_DOVALUE1
- PFA_DP:
-0075af 003a .dw CFG_DP
-0075b0 7bb4 .dw XT_EDEFERFETCH
-0075b1 7bbe .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-0075b2 ff05 .dw $ff05
-0075b3 6865
-0075b4 7265
-0075b5 0065 .db "ehere",0
-0075b6 75ab .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-0075b7 706f .dw PFA_DOVALUE1
- PFA_EHERE:
-0075b8 003e .dw EE_EHERE
-0075b9 7bb4 .dw XT_EDEFERFETCH
-0075ba 7bbe .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-0075bb ff04 .dw $ff04
-0075bc 6568
-0075bd 6572 .db "here"
-0075be 75b2 .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-0075bf 706f .dw PFA_DOVALUE1
- PFA_HERE:
-0075c0 003c .dw EE_HERE
-0075c1 7bb4 .dw XT_EDEFERFETCH
-0075c2 7bbe .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-0075c3 ff05 .dw $ff05
-0075c4 6c61
-0075c5 6f6c
-0075c6 0074 .db "allot",0
-0075c7 75bb .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-0075c8 7001 .dw DO_COLON
- PFA_ALLOT:
-0075c9 75bf .dw XT_HERE
-0075ca 719d .dw XT_PLUS
-0075cb 7b99 .dw XT_DOTO
-0075cc 75c0 .dw PFA_HERE
-0075cd 7020 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-0075ce ff03 .dw $ff03
-0075cf 6962
-0075d0 006e .db "bin",0
-0075d1 75c3 .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-0075d2 7001 .dw DO_COLON
- PFA_BIN:
- .endif
-0075d3 7d8b .dw XT_TWO
-0075d4 7551 .dw XT_BASE
-0075d5 7081 .dw XT_STORE
-0075d6 7020 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-0075d7 ff07 .dw $ff07
-0075d8 6564
-0075d9 6963
-0075da 616d
-0075db 006c .db "decimal",0
-0075dc 75ce .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-0075dd 7001 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-0075de 703d .dw XT_DOLITERAL
-0075df 000a .dw 10
-0075e0 7551 .dw XT_BASE
-0075e1 7081 .dw XT_STORE
-0075e2 7020 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-0075e3 ff03 .dw $ff03
-0075e4 6568
-0075e5 0078 .db "hex",0
-0075e6 75d7 .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-0075e7 7001 .dw DO_COLON
- PFA_HEX:
- .endif
-0075e8 703d .dw XT_DOLITERAL
-0075e9 0010 .dw 16
-0075ea 7551 .dw XT_BASE
-0075eb 7081 .dw XT_STORE
-0075ec 7020 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-0075ed ff02 .dw $ff02
-0075ee 6c62 .db "bl"
-0075ef 75e3 .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-0075f0 7048 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-0075f1 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-0075f2 ff07 .dw $ff07
-0075f3 7574
-0075f4 6e72
-0075f5 656b
-0075f6 0079 .db "turnkey",0
-0075f7 75ed .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-0075f8 7c13 .dw PFA_DODEFER1
- PFA_TURNKEY:
-0075f9 0046 .dw CFG_TURNKEY
-0075fa 7bb4 .dw XT_EDEFERFETCH
-0075fb 7bbe .dw XT_EDEFERSTORE
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-0075fc ff04 .dw $ff04
-0075fd 6d2f
-0075fe 646f .db "/mod"
-0075ff 75f2 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-007600 7601 .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-007601 019c movw temp2, tosl
-
-007602 9109 ld temp0, Y+
-007603 9119 ld temp1, Y+
-
-007604 2f41 mov temp6,temp1 ;move dividend High to sign register
-007605 2743 eor temp6,temp3 ;xor divisor High with sign register
-007606 ff17 sbrs temp1,7 ;if MSB in dividend set
-007607 c004 rjmp PFA_SLASHMOD_1
-007608 9510 com temp1 ; change sign of dividend
-007609 9500 com temp0
-00760a 5f0f subi temp0,low(-1)
-00760b 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-00760c ff37 sbrs temp3,7 ;if MSB in divisor set
-00760d c004 rjmp PFA_SLASHMOD_2
-00760e 9530 com temp3 ; change sign of divisor
-00760f 9520 com temp2
-007610 5f2f subi temp2,low(-1)
-007611 4f3f sbci temp3,high(-1)
-007612 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-007613 18ff sub temp5,temp5;clear remainder High byte and carry
-007614 e151 ldi temp7,17 ;init loop counter
-
-007615 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-007616 1f11 rol temp1
-007617 955a dec temp7 ;decrement counter
-007618 f439 brne PFA_SLASHMOD_5 ;if done
-007619 ff47 sbrs temp6,7 ; if MSB in sign register set
-00761a c004 rjmp PFA_SLASHMOD_4
-00761b 9510 com temp1 ; change sign of result
-00761c 9500 com temp0
-00761d 5f0f subi temp0,low(-1)
-00761e 4f1f sbci temp1,high(-1)
-00761f c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-007620 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-007621 1cff rol temp5
-007622 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-007623 0af3 sbc temp5,temp3 ;
-007624 f420 brcc PFA_SLASHMOD_6 ;if result negative
-007625 0ee2 add temp4,temp2 ; restore remainder
-007626 1ef3 adc temp5,temp3
-007627 9488 clc ; clear carry to be shifted into result
-007628 cfec rjmp PFA_SLASHMOD_3 ;else
-007629 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-00762a cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-00762b 92fa st -Y,temp5
-00762c 92ea st -Y,temp4
-
- ; put quotient on stack
-00762d 01c8 movw tosl, temp0
-00762e c9d6 jmp_ DO_NEXT
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-00762f ff05 .dw $ff05
-007630 2f75
-007631 6f6d
-007632 0064 .db "u/mod",0
-007633 75fc .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-007634 7001 .dw DO_COLON
- PFA_USLASHMOD:
-007635 70ff .dw XT_TO_R
-007636 7154 .dw XT_ZERO
-007637 70f6 .dw XT_R_FROM
-007638 71c2 .dw XT_UMSLASHMOD
-007639 7020 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-00763a ff06 .dw $ff06
-00763b 656e
-00763c 6167
-00763d 6574 .db "negate"
-00763e 762f .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-00763f 7001 .dw DO_COLON
- PFA_NEGATE:
-007640 71fd .dw XT_INVERT
-007641 722f .dw XT_1PLUS
-007642 7020 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-007643 ff01 .dw $ff01
-007644 002f .db "/",0
-007645 763a .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-007646 7001 .dw DO_COLON
- PFA_SLASH:
- .endif
-007647 7600 .dw XT_SLASHMOD
-007648 70f0 .dw XT_NIP
-007649 7020 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-00764a ff03 .dw $ff03
-00764b 6f6d
-00764c 0064 .db "mod",0
-00764d 7643 .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-00764e 7001 .dw DO_COLON
- PFA_MOD:
- .endif
-00764f 7600 .dw XT_SLASHMOD
-007650 70d9 .dw XT_DROP
-007651 7020 .dw XT_EXIT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-007652 ff03 .dw $ff03
-007653 6261
-007654 0073 .db "abs",0
-007655 764a .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-007656 7001 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-007657 70b1
-007658 723e
-007659 7020 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-00765a ff03 .dw $ff03
-00765b 696d
-00765c 006e .db "min",0
-00765d 7652 .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-00765e 7001 .dw DO_COLON
- PFA_MIN:
- .endif
-00765f 7565 .dw XT_2DUP
-007660 7178 .dw XT_GREATER
-007661 7036 .dw XT_DOCONDBRANCH
-007662 7664 DEST(PFA_MIN1)
-007663 70c4 .dw XT_SWAP
- PFA_MIN1:
-007664 70d9 .dw XT_DROP
-007665 7020 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-007666 ff03 .dw $ff03
-007667 616d
-007668 0078 .db "max",0
-007669 765a .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-00766a 7001 .dw DO_COLON
- PFA_MAX:
-
- .endif
-00766b 7565 .dw XT_2DUP
-00766c 716e .dw XT_LESS
-00766d 7036 .dw XT_DOCONDBRANCH
-00766e 7670 DEST(PFA_MAX1)
-00766f 70c4 .dw XT_SWAP
- PFA_MAX1:
-007670 70d9 .dw XT_DROP
-007671 7020 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-007672 ff06 .dw $ff06
-007673 6977
-007674 6874
-007675 6e69 .db "within"
-007676 7666 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-007677 7001 .dw DO_COLON
- PFA_WITHIN:
- .endif
-007678 70cf .dw XT_OVER
-007679 7193 .dw XT_MINUS
-00767a 70ff .dw XT_TO_R
-00767b 7193 .dw XT_MINUS
-00767c 70f6 .dw XT_R_FROM
-00767d 715c .dw XT_ULESS
-00767e 7020 .dw XT_EXIT
-
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-00767f ff07 .dw $ff07
-007680 6f74
-007681 7075
-007682 6570
-007683 0072 .db "toupper",0
-007684 7672 .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-007685 7001 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-007686 70b1 .dw XT_DUP
-007687 703d .dw XT_DOLITERAL
-007688 0061 .dw 'a'
-007689 703d .dw XT_DOLITERAL
-00768a 007b .dw 'z'+1
-00768b 7677 .dw XT_WITHIN
-00768c 7036 .dw XT_DOCONDBRANCH
-00768d 7691 DEST(PFA_TOUPPER0)
-00768e 703d .dw XT_DOLITERAL
-00768f 00df .dw 223 ; inverse of 0x20: 0xdf
-007690 7213 .dw XT_AND
- PFA_TOUPPER0:
-007691 7020 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-007692 ff07 .dw $ff07
-007693 6f74
-007694 6f6c
-007695 6577
-007696 0072 .db "tolower",0
-007697 767f .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-007698 7001 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-007699 70b1 .dw XT_DUP
-00769a 703d .dw XT_DOLITERAL
-00769b 0041 .dw 'A'
-00769c 703d .dw XT_DOLITERAL
-00769d 005b .dw 'Z'+1
-00769e 7677 .dw XT_WITHIN
-00769f 7036 .dw XT_DOCONDBRANCH
-0076a0 76a4 DEST(PFA_TOLOWER0)
-0076a1 703d .dw XT_DOLITERAL
-0076a2 0020 .dw 32
-0076a3 721c .dw XT_OR
- PFA_TOLOWER0:
-0076a4 7020 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-0076a5 ff03 .dw $ff03
-0076a6 6c68
-0076a7 0064 .db "hld",0
-0076a8 7692 .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-0076a9 7048 .dw PFA_DOVARIABLE
- PFA_HLD:
-0076aa 0138 .dw ram_hld
-
- .dseg
-000138 ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-0076ab ff04 .dw $ff04
-0076ac 6f68
-0076ad 646c .db "hold"
-0076ae 76a5 .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-0076af 7001 .dw DO_COLON
- PFA_HOLD:
- .endif
-0076b0 76a9 .dw XT_HLD
-0076b1 70b1 .dw XT_DUP
-0076b2 7079 .dw XT_FETCH
-0076b3 7235 .dw XT_1MINUS
-0076b4 70b1 .dw XT_DUP
-0076b5 70ff .dw XT_TO_R
-0076b6 70c4 .dw XT_SWAP
-0076b7 7081 .dw XT_STORE
-0076b8 70f6 .dw XT_R_FROM
-0076b9 708d .dw XT_CSTORE
-0076ba 7020 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-0076bb ff02 .dw $ff02
-0076bc 233c .db "<#"
-0076bd 76ab .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-0076be 7001 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-0076bf 7584 .dw XT_PAD
-0076c0 76a9 .dw XT_HLD
-0076c1 7081 .dw XT_STORE
-0076c2 7020 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-0076c3 ff01 .dw $ff01
-0076c4 0023 .db "#",0
-0076c5 76bb .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-0076c6 7001 .dw DO_COLON
- PFA_SHARP:
- .endif
-0076c7 7551 .dw XT_BASE
-0076c8 7079 .dw XT_FETCH
-0076c9 7743 .dw XT_UDSLASHMOD
-0076ca 70e1 .dw XT_ROT
-0076cb 703d .dw XT_DOLITERAL
-0076cc 0009 .dw 9
-0076cd 70cf .dw XT_OVER
-0076ce 716e .dw XT_LESS
-0076cf 7036 .dw XT_DOCONDBRANCH
-0076d0 76d4 DEST(PFA_SHARP1)
-0076d1 703d .dw XT_DOLITERAL
-0076d2 0007 .dw 7
-0076d3 719d .dw XT_PLUS
- PFA_SHARP1:
-0076d4 703d .dw XT_DOLITERAL
-0076d5 0030 .dw 48 ; ASCII 0
-0076d6 719d .dw XT_PLUS
-0076d7 76af .dw XT_HOLD
-0076d8 7020 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-0076d9 ff02 .dw $ff02
-0076da 7323 .db "#s"
-0076db 76c3 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-0076dc 7001 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-0076dd 76c6 .dw XT_SHARP
-0076de 7565 .dw XT_2DUP
-0076df 721c .dw XT_OR
-0076e0 711a .dw XT_ZEROEQUAL
-0076e1 7036 .dw XT_DOCONDBRANCH
-0076e2 76dd DEST(NUMS1) ; PFA_SHARP_S
-0076e3 7020 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-0076e4 ff02 .dw $ff02
-0076e5 3e23 .db "#>"
-0076e6 76d9 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-0076e7 7001 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-0076e8 756e .dw XT_2DROP
-0076e9 76a9 .dw XT_HLD
-0076ea 7079 .dw XT_FETCH
-0076eb 7584 .dw XT_PAD
-0076ec 70cf .dw XT_OVER
-0076ed 7193 .dw XT_MINUS
-0076ee 7020 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-0076ef ff04 .dw $ff04
-0076f0 6973
-0076f1 6e67 .db "sign"
-0076f2 76e4 .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-0076f3 7001 .dw DO_COLON
- PFA_SIGN:
- .endif
-0076f4 7121 .dw XT_ZEROLESS
-0076f5 7036 .dw XT_DOCONDBRANCH
-0076f6 76fa DEST(PFA_SIGN1)
-0076f7 703d .dw XT_DOLITERAL
-0076f8 002d .dw 45 ; ascii -
-0076f9 76af .dw XT_HOLD
- PFA_SIGN1:
-0076fa 7020 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-0076fb ff03 .dw $ff03
-0076fc 2e64
-0076fd 0072 .db "d.r",0
-0076fe 76ef .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-0076ff 7001 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-007700 70ff .dw XT_TO_R
-007701 7576 .dw XT_TUCK
-007702 7cd4 .dw XT_DABS
-007703 76be .dw XT_L_SHARP
-007704 76dc .dw XT_SHARP_S
-007705 70e1 .dw XT_ROT
-007706 76f3 .dw XT_SIGN
-007707 76e7 .dw XT_SHARP_G
-007708 70f6 .dw XT_R_FROM
-007709 70cf .dw XT_OVER
-00770a 7193 .dw XT_MINUS
-00770b 77eb .dw XT_SPACES
-00770c 77fb .dw XT_TYPE
-00770d 7020 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-00770e ff02 .dw $ff02
-00770f 722e .db ".r"
-007710 76fb .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-007711 7001 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-007712 70ff .dw XT_TO_R
-007713 7d67 .dw XT_S2D
-007714 70f6 .dw XT_R_FROM
-007715 76ff .dw XT_DDOTR
-007716 7020 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-007717 ff02 .dw $ff02
-007718 2e64 .db "d."
-007719 770e .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-00771a 7001 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-00771b 7154 .dw XT_ZERO
-00771c 76ff .dw XT_DDOTR
-00771d 77e2 .dw XT_SPACE
-00771e 7020 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-00771f ff01 .dw $ff01
-007720 002e .db ".",0
-007721 7717 .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-007722 7001 .dw DO_COLON
- PFA_DOT:
- .endif
-007723 7d67 .dw XT_S2D
-007724 771a .dw XT_DDOT
-007725 7020 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-007726 ff03 .dw $ff03
-007727 6475
-007728 002e .db "ud.",0
-007729 771f .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-00772a 7001 .dw DO_COLON
- PFA_UDDOT:
- .endif
-00772b 7154 .dw XT_ZERO
-00772c 7733 .dw XT_UDDOTR
-00772d 77e2 .dw XT_SPACE
-00772e 7020 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-00772f ff04 .dw $ff04
-007730 6475
-007731 722e .db "ud.r"
-007732 7726 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-007733 7001 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-007734 70ff .dw XT_TO_R
-007735 76be .dw XT_L_SHARP
-007736 76dc .dw XT_SHARP_S
-007737 76e7 .dw XT_SHARP_G
-007738 70f6 .dw XT_R_FROM
-007739 70cf .dw XT_OVER
-00773a 7193 .dw XT_MINUS
-00773b 77eb .dw XT_SPACES
-00773c 77fb .dw XT_TYPE
-00773d 7020 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-00773e ff06 .dw $ff06
-00773f 6475
-007740 6d2f
-007741 646f .db "ud/mod"
-007742 772f .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-007743 7001 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-007744 70ff .dw XT_TO_R
-007745 7154 .dw XT_ZERO
-007746 7108 .dw XT_R_FETCH
-007747 71c2 .dw XT_UMSLASHMOD
-007748 70f6 .dw XT_R_FROM
-007749 70c4 .dw XT_SWAP
-00774a 70ff .dw XT_TO_R
-00774b 71c2 .dw XT_UMSLASHMOD
-00774c 70f6 .dw XT_R_FROM
-00774d 7020 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-00774e ff06 .dw $ff06
-00774f 6964
-007750 6967
-007751 3f74 .db "digit?"
-007752 773e .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-007753 7001 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-007754 7685 .dw XT_TOUPPER
-007755 70b1
-007756 703d
-007757 0039
-007758 7178
-007759 703d
-00775a 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-00775b 7213
-00775c 719d
-00775d 70b1
-00775e 703d
-00775f 0140
-007760 7178 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-007761 703d
-007762 0107
-007763 7213
-007764 7193
-007765 703d
-007766 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-007767 7193
-007768 70b1
-007769 7551
-00776a 7079
-00776b 715c .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-00776c 7020 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-00776d 7001 .dw DO_COLON
- PFA_DOSLITERAL:
-00776e 7108 .dw XT_R_FETCH ; ( -- addr )
-00776f 77cc .dw XT_ICOUNT
-007770 70f6 .dw XT_R_FROM
-007771 70cf .dw XT_OVER ; ( -- addr' n addr n)
-007772 722f .dw XT_1PLUS
-007773 7204 .dw XT_2SLASH ; ( -- addr' n addr k )
-007774 719d .dw XT_PLUS ; ( -- addr' n addr'' )
-007775 722f .dw XT_1PLUS
-007776 70ff .dw XT_TO_R ; ( -- )
-007777 7020 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-007778 ff02 .dw $ff02
-007779 2c73 .db "s",$2c
-00777a 774e .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-00777b 7001 .dw DO_COLON
- PFA_SCOMMA:
-00777c 70b1 .dw XT_DUP
-00777d 777f .dw XT_DOSCOMMA
-00777e 7020 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-00777f 7001 .dw DO_COLON
- PFA_DOSCOMMA:
-007780 01cc .dw XT_COMMA
-007781 70b1 .dw XT_DUP ; ( --addr len len)
-007782 7204 .dw XT_2SLASH ; ( -- addr len len/2
-007783 7576 .dw XT_TUCK ; ( -- addr len/2 len len/2
-007784 720b .dw XT_2STAR ; ( -- addr len/2 len len'
-007785 7193 .dw XT_MINUS ; ( -- addr len/2 rem
-007786 70ff .dw XT_TO_R
-007787 7154 .dw XT_ZERO
-007788 028b .dw XT_QDOCHECK
-007789 7036 .dw XT_DOCONDBRANCH
-00778a 7792 .dw PFA_SCOMMA2
-00778b 729b .dw XT_DODO
- PFA_SCOMMA1:
-00778c 70b1 .dw XT_DUP ; ( -- addr addr )
-00778d 7079 .dw XT_FETCH ; ( -- addr c1c2 )
-00778e 01cc .dw XT_COMMA ; ( -- addr )
-00778f 755e .dw XT_CELLPLUS ; ( -- addr+cell )
-007790 72c9 .dw XT_DOLOOP
-007791 778c .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-007792 70f6 .dw XT_R_FROM
-007793 7128 .dw XT_GREATERZERO
-007794 7036 .dw XT_DOCONDBRANCH
-007795 7799 .dw PFA_SCOMMA3
-007796 70b1 .dw XT_DUP ; well, tricky
-007797 7098 .dw XT_CFETCH
-007798 01cc .dw XT_COMMA
- PFA_SCOMMA3:
-007799 70d9 .dw XT_DROP ; ( -- )
-00779a 7020 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-00779b ff05 .dw $ff05
-00779c 7469
-00779d 7079
-00779e 0065 .db "itype",0
-00779f 7778 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-0077a0 7001 .dw DO_COLON
- PFA_ITYPE:
-0077a1 70b1 .dw XT_DUP ; ( --addr len len)
-0077a2 7204 .dw XT_2SLASH ; ( -- addr len len/2
-0077a3 7576 .dw XT_TUCK ; ( -- addr len/2 len len/2
-0077a4 720b .dw XT_2STAR ; ( -- addr len/2 len len'
-0077a5 7193 .dw XT_MINUS ; ( -- addr len/2 rem
-0077a6 70ff .dw XT_TO_R
-0077a7 7154 .dw XT_ZERO
-0077a8 028b .dw XT_QDOCHECK
-0077a9 7036 .dw XT_DOCONDBRANCH
-0077aa 77b4 .dw PFA_ITYPE2
-0077ab 729b .dw XT_DODO
- PFA_ITYPE1:
-0077ac 70b1 .dw XT_DUP ; ( -- addr addr )
-0077ad 73cb .dw XT_FETCHI ; ( -- addr c1c2 )
-0077ae 70b1 .dw XT_DUP
-0077af 77c1 .dw XT_LOWEMIT
-0077b0 77bd .dw XT_HIEMIT
-0077b1 722f .dw XT_1PLUS ; ( -- addr+cell )
-0077b2 72c9 .dw XT_DOLOOP
-0077b3 77ac .dw PFA_ITYPE1
- PFA_ITYPE2:
-0077b4 70f6 .dw XT_R_FROM
-0077b5 7128 .dw XT_GREATERZERO
-0077b6 7036 .dw XT_DOCONDBRANCH
-0077b7 77bb .dw PFA_ITYPE3
-0077b8 70b1 .dw XT_DUP ; make sure the drop below has always something to do
-0077b9 73cb .dw XT_FETCHI
-0077ba 77c1 .dw XT_LOWEMIT
- PFA_ITYPE3:
-0077bb 70d9 .dw XT_DROP
-0077bc 7020 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-0077bd 7001 .dw DO_COLON
- PFA_HIEMIT:
-0077be 72f9 .dw XT_BYTESWAP
-0077bf 77c1 .dw XT_LOWEMIT
-0077c0 7020 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-0077c1 7001 .dw DO_COLON
- PFA_LOWEMIT:
-0077c2 703d .dw XT_DOLITERAL
-0077c3 00ff .dw $00ff
-0077c4 7213 .dw XT_AND
-0077c5 758e .dw XT_EMIT
-0077c6 7020 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-0077c7 ff06 .dw $ff06
-0077c8 6369
-0077c9 756f
-0077ca 746e .db "icount"
-0077cb 779b .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-0077cc 7001 .dw DO_COLON
- PFA_ICOUNT:
-0077cd 70b1 .dw XT_DUP
-0077ce 722f .dw XT_1PLUS
-0077cf 70c4 .dw XT_SWAP
-0077d0 73cb .dw XT_FETCHI
-0077d1 7020 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-0077d2 ff02 .dw 0xff02
-0077d3 7263 .db "cr"
-0077d4 77c7 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-0077d5 7001 .dw DO_COLON
- PFA_CR:
- .endif
-
-0077d6 703d .dw XT_DOLITERAL
-0077d7 000d .dw 13
-0077d8 758e .dw XT_EMIT
-0077d9 703d .dw XT_DOLITERAL
-0077da 000a .dw 10
-0077db 758e .dw XT_EMIT
-0077dc 7020 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-0077dd ff05 .dw $ff05
-0077de 7073
-0077df 6361
-0077e0 0065 .db "space",0
-0077e1 77d2 .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-0077e2 7001 .dw DO_COLON
- PFA_SPACE:
- .endif
-0077e3 75f0 .dw XT_BL
-0077e4 758e .dw XT_EMIT
-0077e5 7020 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-0077e6 ff06 .dw $ff06
-0077e7 7073
-0077e8 6361
-0077e9 7365 .db "spaces"
-0077ea 77dd .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-0077eb 7001 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-0077ec 7154
-0077ed 766a .DW XT_ZERO, XT_MAX
-0077ee 70b1
-0077ef 7036 SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-0077f0 77f5 DEST(SPCS2)
-0077f1 77e2
-0077f2 7235
-0077f3 702f .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-0077f4 77ee DEST(SPCS1)
-0077f5 70d9
-0077f6 7020 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-0077f7 ff04 .dw $ff04
-0077f8 7974
-0077f9 6570 .db "type"
-0077fa 77e6 .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-0077fb 7001 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-0077fc 7d5e .dw XT_BOUNDS
-0077fd 028b .dw XT_QDOCHECK
-0077fe 7036 .dw XT_DOCONDBRANCH
-0077ff 7806 DEST(PFA_TYPE2)
-007800 729b .dw XT_DODO
- PFA_TYPE1:
-007801 72ac .dw XT_I
-007802 7098 .dw XT_CFETCH
-007803 758e .dw XT_EMIT
-007804 72c9 .dw XT_DOLOOP
-007805 7801 DEST(PFA_TYPE1)
- PFA_TYPE2:
-007806 7020 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-007807 ff01 .dw $ff01
-007808 0027 .db "'",0
-007809 77f7 .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00780a 7001 .dw DO_COLON
- PFA_TICK:
- .endif
-00780b 79b4 .dw XT_PARSENAME
-00780c 7acc .dw XT_FORTHRECOGNIZER
-00780d 7ad7 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-00780e 70b1 .dw XT_DUP
-00780f 7b4a .dw XT_DT_NULL
-007810 7d7f .dw XT_EQUAL
-007811 70c4 .dw XT_SWAP
-007812 73cb .dw XT_FETCHI
-007813 703d .dw XT_DOLITERAL
-007814 7b7f .dw XT_NOOP
-007815 7d7f .dw XT_EQUAL
-007816 721c .dw XT_OR
-007817 7036 .dw XT_DOCONDBRANCH
-007818 781c DEST(PFA_TICK1)
-007819 703d .dw XT_DOLITERAL
-00781a fff3 .dw -13
-00781b 7841 .dw XT_THROW
- PFA_TICK1:
-00781c 70d9 .dw XT_DROP
-00781d 7020 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-00781e ff07 .dw $ff07
-00781f 6168
-007820 646e
-007821 656c
-007822 0072 .db "handler",0
-007823 7807 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-007824 7058 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-007825 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-007826 ff05 .dw $ff05
-007827 6163
-007828 6374
-007829 0068 .db "catch",0
-00782a 781e .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-00782b 7001 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-00782c 728d .dw XT_SP_FETCH
-00782d 70ff .dw XT_TO_R
- ; handler @ >r
-00782e 7824 .dw XT_HANDLER
-00782f 7079 .dw XT_FETCH
-007830 70ff .dw XT_TO_R
- ; rp@ handler !
-007831 7276 .dw XT_RP_FETCH
-007832 7824 .dw XT_HANDLER
-007833 7081 .dw XT_STORE
-007834 702a .dw XT_EXECUTE
- ; r> handler !
-007835 70f6 .dw XT_R_FROM
-007836 7824 .dw XT_HANDLER
-007837 7081 .dw XT_STORE
-007838 70f6 .dw XT_R_FROM
-007839 70d9 .dw XT_DROP
-00783a 7154 .dw XT_ZERO
-00783b 7020 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-00783c ff05 .dw $ff05
-00783d 6874
-00783e 6f72
-00783f 0077 .db "throw",0
-007840 7826 .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-007841 7001 .dw DO_COLON
- PFA_THROW:
- .endif
-007842 70b1 .dw XT_DUP
-007843 711a .dw XT_ZEROEQUAL
-007844 7036 .dw XT_DOCONDBRANCH
-007845 7848 DEST(PFA_THROW1)
-007846 70d9 .dw XT_DROP
-007847 7020 .dw XT_EXIT
- PFA_THROW1:
-007848 7824 .dw XT_HANDLER
-007849 7079 .dw XT_FETCH
-00784a 7280 .dw XT_RP_STORE
-00784b 70f6 .dw XT_R_FROM
-00784c 7824 .dw XT_HANDLER
-00784d 7081 .dw XT_STORE
-00784e 70f6 .dw XT_R_FROM
-00784f 70c4 .dw XT_SWAP
-007850 70ff .dw XT_TO_R
-007851 7296 .dw XT_SP_STORE
-007852 70d9 .dw XT_DROP
-007853 70f6 .dw XT_R_FROM
-007854 7020 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-007855 ff05 .dw $ff05
-007856 7363
-007857 696b
-007858 0070 .db "cskip",0
-007859 783c .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-00785a 7001 .dw DO_COLON
- PFA_CSKIP:
- .endif
-00785b 70ff .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-00785c 70b1 .dw XT_DUP ; ( -- addr' n' n' )
-00785d 7036 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00785e 7869 DEST(PFA_CSKIP2)
-00785f 70cf .dw XT_OVER ; ( -- addr' n' addr' )
-007860 7098 .dw XT_CFETCH ; ( -- addr' n' c' )
-007861 7108 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-007862 7d7f .dw XT_EQUAL ; ( -- addr' n' f )
-007863 7036 .dw XT_DOCONDBRANCH ; ( -- addr' n')
-007864 7869 DEST(PFA_CSKIP2)
-007865 7d86 .dw XT_ONE
-007866 79a5 .dw XT_SLASHSTRING
-007867 702f .dw XT_DOBRANCH
-007868 785c DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-007869 70f6 .dw XT_R_FROM
-00786a 70d9 .dw XT_DROP ; ( -- addr2 n2)
-00786b 7020 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-00786c ff05 .dw $ff05
-00786d 7363
-00786e 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00786f 006e .db "cscan"
-007870 7855 .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-007871 7001 .dw DO_COLON
- PFA_CSCAN:
- .endif
-007872 70ff .dw XT_TO_R
-007873 70cf .dw XT_OVER
- PFA_CSCAN1:
-007874 70b1 .dw XT_DUP
-007875 7098 .dw XT_CFETCH
-007876 7108 .dw XT_R_FETCH
-007877 7d7f .dw XT_EQUAL
-007878 711a .dw XT_ZEROEQUAL
-007879 7036 .dw XT_DOCONDBRANCH
-00787a 7886 DEST(PFA_CSCAN2)
-00787b 70c4 .dw XT_SWAP
-00787c 7235 .dw XT_1MINUS
-00787d 70c4 .dw XT_SWAP
-00787e 70cf .dw XT_OVER
-00787f 7121 .dw XT_ZEROLESS ; not negative
-007880 711a .dw XT_ZEROEQUAL
-007881 7036 .dw XT_DOCONDBRANCH
-007882 7886 DEST(PFA_CSCAN2)
-007883 722f .dw XT_1PLUS
-007884 702f .dw XT_DOBRANCH
-007885 7874 DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-007886 70f0 .dw XT_NIP
-007887 70cf .dw XT_OVER
-007888 7193 .dw XT_MINUS
-007889 70f6 .dw XT_R_FROM
-00788a 70d9 .dw XT_DROP
-00788b 7020 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-00788c ff06 .dw $ff06
-00788d 6361
-00788e 6563
-00788f 7470 .db "accept"
-007890 786c .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-007891 7001 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-007892 70cf
-007893 719d
-007894 7235
-007895 70cf .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-007896 759f
-007897 70b1
-007898 78d2
-007899 711a
-00789a 7036 ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-00789b 78c4 DEST(ACC5)
-00789c 70b1
-00789d 703d
-00789e 0008
-00789f 7d7f
-0078a0 7036 .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-0078a1 78b4 DEST(ACC3)
-0078a2 70d9
-0078a3 70e1
-0078a4 7565
-0078a5 7178
-0078a6 70ff
-0078a7 70e1
-0078a8 70e1
-0078a9 70f6
-0078aa 7036 .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-0078ab 78b2 DEST(ACC6)
-0078ac 78ca
-0078ad 7235
-0078ae 70ff
-0078af 70cf
-0078b0 70f6
-0078b1 015e .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-0078b2 702f ACC6: .DW XT_DOBRANCH
-0078b3 78c2 DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-0078b4 70b1 .dw XT_DUP ; ( -- addr k k )
-0078b5 75f0 .dw XT_BL
-0078b6 716e .dw XT_LESS
-0078b7 7036 .dw XT_DOCONDBRANCH
-0078b8 78bb DEST(PFA_ACCEPT6)
-0078b9 70d9 .dw XT_DROP
-0078ba 75f0 .dw XT_BL
- PFA_ACCEPT6:
-0078bb 70b1
-0078bc 758e
-0078bd 70cf
-0078be 708d
-0078bf 722f
-0078c0 70cf
-0078c1 016a .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-0078c2 702f ACC4: .DW XT_DOBRANCH
-0078c3 7896 DEST(ACC1)
-0078c4 70d9
-0078c5 70f0
-0078c6 70c4
-0078c7 7193
-0078c8 77d5
-0078c9 7020 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-0078ca 7001 .dw DO_COLON
- .endif
-0078cb 703d .dw XT_DOLITERAL
-0078cc 0008 .dw 8
-0078cd 70b1 .dw XT_DUP
-0078ce 758e .dw XT_EMIT
-0078cf 77e2 .dw XT_SPACE
-0078d0 758e .dw XT_EMIT
-0078d1 7020 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-0078d2 7001 .dw DO_COLON
- .endif
-0078d3 70b1 .dw XT_DUP
-0078d4 703d .dw XT_DOLITERAL
-0078d5 000d .dw 13
-0078d6 7d7f .dw XT_EQUAL
-0078d7 70c4 .dw XT_SWAP
-0078d8 703d .dw XT_DOLITERAL
-0078d9 000a .dw 10
-0078da 7d7f .dw XT_EQUAL
-0078db 721c .dw XT_OR
-0078dc 7020 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-0078dd ff06 .dw $ff06
-0078de 6572
-0078df 6966
-0078e0 6c6c .db "refill"
-0078e1 788c .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-0078e2 7c13 .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-0078e3 001a .dw USER_REFILL
-0078e4 7bdc .dw XT_UDEFERFETCH
-0078e5 7be8 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-0078e6 ff04 .dw $ff04
-0078e7 6863
-0078e8 7261 .db "char"
-0078e9 78dd .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-0078ea 7001 .dw DO_COLON
- PFA_CHAR:
- .endif
-0078eb 79b4 .dw XT_PARSENAME
-0078ec 70d9 .dw XT_DROP
-0078ed 7098 .dw XT_CFETCH
-0078ee 7020 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-0078ef ff06 .dw $ff06
-0078f0 756e
-0078f1 626d
-0078f2 7265 .db "number"
-0078f3 78e6 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-0078f4 7001 .dw DO_COLON
- PFA_NUMBER:
- .endif
-0078f5 7551 .dw XT_BASE
-0078f6 7079 .dw XT_FETCH
-0078f7 70ff .dw XT_TO_R
-0078f8 7938 .dw XT_QSIGN
-0078f9 70ff .dw XT_TO_R
-0078fa 794b .dw XT_SET_BASE
-0078fb 7938 .dw XT_QSIGN
-0078fc 70f6 .dw XT_R_FROM
-0078fd 721c .dw XT_OR
-0078fe 70ff .dw XT_TO_R
- ; check whether something is left
-0078ff 70b1 .dw XT_DUP
-007900 711a .dw XT_ZEROEQUAL
-007901 7036 .dw XT_DOCONDBRANCH
-007902 790b DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-007903 756e .dw XT_2DROP
-007904 70f6 .dw XT_R_FROM
-007905 70d9 .dw XT_DROP
-007906 70f6 .dw XT_R_FROM
-007907 7551 .dw XT_BASE
-007908 7081 .dw XT_STORE
-007909 7154 .dw XT_ZERO
-00790a 7020 .dw XT_EXIT
- PFA_NUMBER0:
-00790b 731e .dw XT_2TO_R
-00790c 7154 .dw XT_ZERO ; starting value
-00790d 7154 .dw XT_ZERO
-00790e 732d .dw XT_2R_FROM
-00790f 7969 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-007910 70b9 .dw XT_QDUP
-007911 7036 .dw XT_DOCONDBRANCH
-007912 792d DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-007913 7d86 .dw XT_ONE
-007914 7d7f .dw XT_EQUAL
-007915 7036 .dw XT_DOCONDBRANCH
-007916 7924 DEST(PFA_NUMBER2)
- ; excatly one character is left
-007917 7098 .dw XT_CFETCH
-007918 703d .dw XT_DOLITERAL
-007919 002e .dw 46 ; .
-00791a 7d7f .dw XT_EQUAL
-00791b 7036 .dw XT_DOCONDBRANCH
-00791c 7925 DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-00791d 70f6 .dw XT_R_FROM
-00791e 7036 .dw XT_DOCONDBRANCH
-00791f 7921 DEST(PFA_NUMBER3)
-007920 7ce1 .dw XT_DNEGATE
- PFA_NUMBER3:
-007921 7d8b .dw XT_TWO
-007922 702f .dw XT_DOBRANCH
-007923 7933 DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-007924 70d9 .dw XT_DROP
- PFA_NUMBER6:
-007925 756e .dw XT_2DROP
-007926 70f6 .dw XT_R_FROM
-007927 70d9 .dw XT_DROP
-007928 70f6 .dw XT_R_FROM
-007929 7551 .dw XT_BASE
-00792a 7081 .dw XT_STORE
-00792b 7154 .dw XT_ZERO
-00792c 7020 .dw XT_EXIT
- PFA_NUMBER1:
-00792d 756e .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-00792e 70f6 .dw XT_R_FROM
-00792f 7036 .dw XT_DOCONDBRANCH
-007930 7932 DEST(PFA_NUMBER4)
-007931 763f .dw XT_NEGATE
- PFA_NUMBER4:
-007932 7d86 .dw XT_ONE
- PFA_NUMBER5:
-007933 70f6 .dw XT_R_FROM
-007934 7551 .dw XT_BASE
-007935 7081 .dw XT_STORE
-007936 714b .dw XT_TRUE
-007937 7020 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-007938 7001 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-007939 70cf .dw XT_OVER ; ( -- addr len addr )
-00793a 7098 .dw XT_CFETCH
-00793b 703d .dw XT_DOLITERAL
-00793c 002d .dw '-'
-00793d 7d7f .dw XT_EQUAL ; ( -- addr len flag )
-00793e 70b1 .dw XT_DUP
-00793f 70ff .dw XT_TO_R
-007940 7036 .dw XT_DOCONDBRANCH
-007941 7944 DEST(PFA_NUMBERSIGN_DONE)
-007942 7d86 .dw XT_ONE ; skip sign character
-007943 79a5 .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-007944 70f6 .dw XT_R_FROM
-007945 7020 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-007946 7052 .dw PFA_DOCONSTANT
- .endif
-007947 000a
-007948 0010
-007949 0002
-00794a 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-00794b 7001 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-00794c 70cf .dw XT_OVER
-00794d 7098 .dw XT_CFETCH
-00794e 703d .dw XT_DOLITERAL
-00794f 0023 .dw 35
-007950 7193 .dw XT_MINUS
-007951 70b1 .dw XT_DUP
-007952 7154 .dw XT_ZERO
-007953 703d .dw XT_DOLITERAL
-007954 0004 .dw 4
-007955 7677 .dw XT_WITHIN
-007956 7036 .dw XT_DOCONDBRANCH
-007957 7961 DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-007958 7946 .dw XT_BASES
-007959 719d .dw XT_PLUS
-00795a 73cb .dw XT_FETCHI
-00795b 7551 .dw XT_BASE
-00795c 7081 .dw XT_STORE
-00795d 7d86 .dw XT_ONE
-00795e 79a5 .dw XT_SLASHSTRING
-00795f 702f .dw XT_DOBRANCH
-007960 7962 DEST(SET_BASE2)
- SET_BASE1:
-007961 70d9 .dw XT_DROP
- SET_BASE2:
-007962 7020 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-007963 ff07 .dw $ff07
-007964 6e3e
-007965 6d75
-007966 6562
-007967 0072 .db ">number",0
-007968 78ef .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-007969 7001 .dw DO_COLON
-
- .endif
-
-00796a 70b1
-00796b 7036 TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-00796c 7981 DEST(TONUM3)
-00796d 70cf
-00796e 7098
-00796f 7753 .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-007970 711a
-007971 7036 .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-007972 7975 DEST(TONUM2)
-007973 70d9
-007974 7020 .DW XT_DROP,XT_EXIT
-007975 70ff
-007976 7d05
-007977 7551
-007978 7079
-007979 014f TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-00797a 70f6
-00797b 0147
-00797c 7d05 .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-00797d 7d86
-00797e 79a5
-00797f 702f .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-007980 796a DEST(TONUM1)
-007981 7020 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-007982 ff05 .dw $ff05
-007983 6170
-007984 7372
-007985 0065 .db "parse",0
-007986 7963 .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-007987 7001 .dw DO_COLON
- PFA_PARSE:
- .endif
-007988 70ff .dw XT_TO_R ; ( -- )
-007989 799b .dw XT_SOURCE ; ( -- addr len)
-00798a 757e .dw XT_TO_IN ; ( -- addr len >in)
-00798b 7079 .dw XT_FETCH
-00798c 79a5 .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-00798d 70f6 .dw XT_R_FROM ; ( -- addr' len' c)
-00798e 7871 .dw XT_CSCAN ; ( -- addr' len'')
-00798f 70b1 .dw XT_DUP ; ( -- addr' len'' len'')
-007990 722f .dw XT_1PLUS
-007991 757e .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-007992 7265 .dw XT_PLUSSTORE ; ( -- addr' len')
-007993 7d86 .dw XT_ONE
-007994 79a5 .dw XT_SLASHSTRING
-007995 7020 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-007996 ff06 .dw $FF06
-007997 6f73
-007998 7275
-007999 6563 .db "source"
-00799a 7982 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-00799b 7c13 .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-00799c 0016 .dw USER_SOURCE
-00799d 7bdc .dw XT_UDEFERFETCH
-00799e 7be8 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00799f ff07 .dw $ff07
-0079a0 732f
-0079a1 7274
-0079a2 6e69
-0079a3 0067 .db "/string",0
-0079a4 7996 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-0079a5 7001 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-0079a6 70e1 .dw XT_ROT
-0079a7 70cf .dw XT_OVER
-0079a8 719d .dw XT_PLUS
-0079a9 70e1 .dw XT_ROT
-0079aa 70e1 .dw XT_ROT
-0079ab 7193 .dw XT_MINUS
-0079ac 7020 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-0079ad ff0a .dw $FF0A
-0079ae 6170
-0079af 7372
-0079b0 2d65
-0079b1 616e
-0079b2 656d .db "parse-name"
-0079b3 799f .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-0079b4 7001 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-0079b5 75f0 .dw XT_BL
-0079b6 79b8 .dw XT_SKIPSCANCHAR
-0079b7 7020 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-0079b8 7001 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-0079b9 70ff .dw XT_TO_R
-0079ba 799b .dw XT_SOURCE
-0079bb 757e .dw XT_TO_IN
-0079bc 7079 .dw XT_FETCH
-0079bd 79a5 .dw XT_SLASHSTRING
-
-0079be 7108 .dw XT_R_FETCH
-0079bf 785a .dw XT_CSKIP
-0079c0 70f6 .dw XT_R_FROM
-0079c1 7871 .dw XT_CSCAN
-
- ; adjust >IN
-0079c2 7565 .dw XT_2DUP
-0079c3 719d .dw XT_PLUS
-0079c4 799b .dw XT_SOURCE
-0079c5 70d9 .dw XT_DROP
-0079c6 7193 .dw XT_MINUS
-0079c7 757e .dw XT_TO_IN
-0079c8 7081 .dw XT_STORE
-0079c9 7020 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-0079ca ff07 .dw $ff07
-0079cb 6966
-0079cc 646e
-0079cd 782d
-0079ce 0074 .db "find-xt",0
-0079cf 79ad .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-0079d0 7001 .dw DO_COLON
- PFA_FINDXT:
- .endif
-0079d1 703d .dw XT_DOLITERAL
-0079d2 79dc .dw XT_FINDXTA
-0079d3 703d .dw XT_DOLITERAL
-0079d4 004e .dw CFG_ORDERLISTLEN
-0079d5 040c .dw XT_MAPSTACK
-0079d6 711a .dw XT_ZEROEQUAL
-0079d7 7036 .dw XT_DOCONDBRANCH
-0079d8 79db DEST(PFA_FINDXT1)
-0079d9 756e .dw XT_2DROP
-0079da 7154 .dw XT_ZERO
- PFA_FINDXT1:
-0079db 7020 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-0079dc 7001 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-0079dd 70ff .dw XT_TO_R
-0079de 7565 .dw XT_2DUP
-0079df 70f6 .dw XT_R_FROM
-0079e0 7c25 .dw XT_SEARCH_WORDLIST
-0079e1 70b1 .dw XT_DUP
-0079e2 7036 .dw XT_DOCONDBRANCH
-0079e3 79e9 DEST(PFA_FINDXTA1)
-0079e4 70ff .dw XT_TO_R
-0079e5 70f0 .dw XT_NIP
-0079e6 70f0 .dw XT_NIP
-0079e7 70f6 .dw XT_R_FROM
-0079e8 714b .dw XT_TRUE
- PFA_FINDXTA1:
-0079e9 7020 .dw XT_EXIT
-
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-0079ea 7001 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-0079eb 776d .dw XT_DOSLITERAL
-0079ec 0003 .dw 3
-0079ed 6f20
-0079ee 006b .db " ok",0
- .endif
-0079ef 77a0 .dw XT_ITYPE
-0079f0 7020 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-0079f1 ff03 .dw $FF03
-0079f2 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-0079f3 006b .db ".ok"
-0079f4 79ca .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-0079f5 7c13 .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-0079f6 001c .dw USER_P_OK
-0079f7 7bdc .dw XT_UDEFERFETCH
-0079f8 7be8 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-0079f9 7001 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-0079fa 776d .dw XT_DOSLITERAL
-0079fb 0002 .dw 2
-0079fc 203e .db "> "
- .endif
-0079fd 77d5 .dw XT_CR
-0079fe 77a0 .dw XT_ITYPE
-0079ff 7020 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-007a00 ff06 .dw $FF06
-007a01 722e
-007a02 6165
-007a03 7964 .db ".ready"
-007a04 79f1 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-007a05 7c13 .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-007a06 0020 .dw USER_P_RDY
-007a07 7bdc .dw XT_UDEFERFETCH
-007a08 7be8 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-007a09 7001 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-007a0a 776d .dw XT_DOSLITERAL
-007a0b 0004 .dw 4
-007a0c 3f20
-007a0d 203f .db " ?? "
- .endif
-007a0e 77a0 .dw XT_ITYPE
-007a0f 7551 .dw XT_BASE
-007a10 7079 .dw XT_FETCH
-007a11 70ff .dw XT_TO_R
-007a12 75dd .dw XT_DECIMAL
-007a13 7722 .dw XT_DOT
-007a14 757e .dw XT_TO_IN
-007a15 7079 .dw XT_FETCH
-007a16 7722 .dw XT_DOT
-007a17 70f6 .dw XT_R_FROM
-007a18 7551 .dw XT_BASE
-007a19 7081 .dw XT_STORE
-007a1a 7020 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-007a1b ff06 .dw $FF06
-007a1c 652e
-007a1d 7272
-007a1e 726f .db ".error"
-007a1f 7a00 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-007a20 7c13 .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-007a21 001e .dw USER_P_ERR
-007a22 7bdc .dw XT_UDEFERFETCH
-007a23 7be8 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-007a24 ff04 .dw $ff04
-007a25 7571
-007a26 7469 .db "quit"
-007a27 7a1b .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-007a28 7001 .dw DO_COLON
- .endif
- PFA_QUIT:
-007a29 02c1
-007a2a 02c8
-007a2b 7081 .dw XT_LP0,XT_LP,XT_STORE
-007a2c 7a89 .dw XT_SP0
-007a2d 7296 .dw XT_SP_STORE
-007a2e 7a96 .dw XT_RP0
-007a2f 7280 .dw XT_RP_STORE
-007a30 0356 .dw XT_LBRACKET
-
- PFA_QUIT2:
-007a31 754b .dw XT_STATE
-007a32 7079 .dw XT_FETCH
-007a33 711a .dw XT_ZEROEQUAL
-007a34 7036 .dw XT_DOCONDBRANCH
-007a35 7a37 DEST(PFA_QUIT4)
-007a36 7a05 .dw XT_PROMPTREADY
- PFA_QUIT4:
-007a37 78e2 .dw XT_REFILL
-007a38 7036 .dw XT_DOCONDBRANCH
-007a39 7a49 DEST(PFA_QUIT3)
-007a3a 703d .dw XT_DOLITERAL
-007a3b 7aaf .dw XT_INTERPRET
-007a3c 782b .dw XT_CATCH
-007a3d 70b9 .dw XT_QDUP
-007a3e 7036 .dw XT_DOCONDBRANCH
-007a3f 7a49 DEST(PFA_QUIT3)
-007a40 70b1 .dw XT_DUP
-007a41 703d .dw XT_DOLITERAL
-007a42 fffe .dw -2
-007a43 716e .dw XT_LESS
-007a44 7036 .dw XT_DOCONDBRANCH
-007a45 7a47 DEST(PFA_QUIT5)
-007a46 7a20 .dw XT_PROMPTERROR
- PFA_QUIT5:
-007a47 702f .dw XT_DOBRANCH
-007a48 7a29 DEST(PFA_QUIT)
- PFA_QUIT3:
-007a49 79f5 .dw XT_PROMPTOK
-007a4a 702f .dw XT_DOBRANCH
-007a4b 7a31 DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-007a4c ff05 .dw $ff05
-007a4d 6170
-007a4e 7375
-007a4f 0065 .db "pause",0
-007a50 7a24 .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-007a51 7c13 .dw PFA_DODEFER1
- PFA_PAUSE:
-007a52 013a .dw ram_pause
-007a53 7bc8 .dw XT_RDEFERFETCH
-007a54 7bd2 .dw XT_RDEFERSTORE
-
- .dseg
-00013a ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-007a55 ff04 .dw $ff04
-007a56 6f63
-007a57 646c .db "cold"
-007a58 7a4c .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-007a59 7a5a .dw PFA_COLD
- PFA_COLD:
-007a5a b6a4 in_ mcu_boot, MCUSR
-007a5b 2422 clr zerol
-007a5c 2433 clr zeroh
-007a5d 24bb clr isrflag
-007a5e be24 out_ MCUSR, zerol
- ; clear RAM
-007a5f e0e0 ldi zl, low(ramstart)
-007a60 e0f1 ldi zh, high(ramstart)
- clearloop:
-007a61 9221 st Z+, zerol
-007a62 30e0 cpi zl, low(sram_size+ramstart)
-007a63 f7e9 brne clearloop
-007a64 31f1 cpi zh, high(sram_size+ramstart)
-007a65 f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-00013c ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-007a66 e3ec ldi zl, low(ram_user1)
-007a67 e0f1 ldi zh, high(ram_user1)
-007a68 012f movw upl, zl
- ; init return stack pointer
-007a69 ef0f ldi temp0,low(rstackstart)
-007a6a bf0d out_ SPL,temp0
-007a6b 8304 std Z+4, temp0
-007a6c e110 ldi temp1,high(rstackstart)
-007a6d bf1e out_ SPH,temp1
-007a6e 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-007a6f eacf ldi yl,low(stackstart)
-007a70 83c6 std Z+6, yl
-007a71 e1d0 ldi yh,high(stackstart)
-007a72 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-007a73 e7ac ldi XL, low(PFA_WARM)
-007a74 e7ba ldi XH, high(PFA_WARM)
- ; its a far jump...
-007a75 940c 7005 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-007a77 ff04 .dw $ff04
-007a78 6177
-007a79 6d72 .db "warm"
-007a7a 7a55 .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-007a7b 7001 .dw DO_COLON
- PFA_WARM:
- .endif
-007a7c 7d50 .dw XT_INIT_RAM
-007a7d 703d .dw XT_DOLITERAL
-007a7e 7b7f .dw XT_NOOP
-007a7f 703d .dw XT_DOLITERAL
-007a80 7a51 .dw XT_PAUSE
-007a81 7bf3 .dw XT_DEFERSTORE
-007a82 0356 .dw XT_LBRACKET
-007a83 75f8 .dw XT_TURNKEY
-007a84 7a28 .dw XT_QUIT ; never returns
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-007a85 ff03 .dw $ff03
-007a86 7073
-007a87 0030 .db "sp0",0
-007a88 7a77 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-007a89 706f .dw PFA_DOVALUE1
- PFA_SP0:
-007a8a 0006 .dw USER_SP0
-007a8b 7bdc .dw XT_UDEFERFETCH
-007a8c 7be8 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-007a8d ff02 .dw $ff02
-007a8e 7073 .db "sp"
-007a8f 7a85 .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-007a90 7058 .dw PFA_DOUSER
- PFA_SP:
-007a91 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-007a92 ff03 .dw $ff03
-007a93 7072
-007a94 0030 .db "rp0",0
-007a95 7a8d .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-007a96 7001 .dw DO_COLON
- PFA_RP0:
-007a97 7a9a .dw XT_DORP0
-007a98 7079 .dw XT_FETCH
-007a99 7020 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-007a9a 7058 .dw PFA_DOUSER
- PFA_DORP0:
-007a9b 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-007a9c ff05 .dw $ff05
-007a9d 6564
-007a9e 7470
-007a9f 0068 .db "depth",0
-007aa0 7a92 .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-007aa1 7001 .dw DO_COLON
- PFA_DEPTH:
- .endif
-007aa2 7a89 .dw XT_SP0
-007aa3 728d .dw XT_SP_FETCH
-007aa4 7193 .dw XT_MINUS
-007aa5 7204 .dw XT_2SLASH
-007aa6 7235 .dw XT_1MINUS
-007aa7 7020 .dw XT_EXIT
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-007aa8 ff09 .dw $ff09
-007aa9 6e69
-007aaa 6574
-007aab 7072
-007aac 6572
-007aad 0074 .db "interpret",0
-007aae 7a9c .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-007aaf 7001 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-007ab0 79b4 .dw XT_PARSENAME ; ( -- addr len )
-007ab1 70b1 .dw XT_DUP ; ( -- addr len flag)
-007ab2 7036 .dw XT_DOCONDBRANCH
-007ab3 7ac0 DEST(PFA_INTERPRET2)
-007ab4 7acc .dw XT_FORTHRECOGNIZER
-007ab5 7ad7 .dw XT_RECOGNIZE
-007ab6 754b .dw XT_STATE
-007ab7 7079 .dw XT_FETCH
-007ab8 7036 .dw XT_DOCONDBRANCH
-007ab9 7abb DEST(PFA_INTERPRET1)
-007aba 7bab .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-007abb 73cb .dw XT_FETCHI
-007abc 702a .dw XT_EXECUTE
-007abd 7b57 .dw XT_QSTACK
-007abe 702f .dw XT_DOBRANCH
-007abf 7ab0 DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-007ac0 756e .dw XT_2DROP
-007ac1 7020 .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-007ac2 ff10 .dw $ff10
-007ac3 6f66
-007ac4 7472
-007ac5 2d68
-007ac6 6572
-007ac7 6f63
-007ac8 6e67
-007ac9 7a69
-007aca 7265 .db "forth-recognizer"
-007acb 7aa8 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-007acc 706f .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-007acd 0042 .dw CFG_FORTHRECOGNIZER
-007ace 7bb4 .dw XT_EDEFERFETCH
-007acf 7bbe .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-007ad0 ff09 .dw $ff09
-007ad1 6572
-007ad2 6f63
-007ad3 6e67
-007ad4 7a69
-007ad5 0065 .db "recognize",0
-007ad6 7ac2 .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-007ad7 7001 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-007ad8 703d .dw XT_DOLITERAL
-007ad9 7ae2 .dw XT_RECOGNIZE_A
-007ada 70c4 .dw XT_SWAP
-007adb 040c .dw XT_MAPSTACK
-007adc 711a .dw XT_ZEROEQUAL
-007add 7036 .dw XT_DOCONDBRANCH
-007ade 7ae1 DEST(PFA_RECOGNIZE1)
-007adf 756e .dw XT_2DROP
-007ae0 7b4a .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-007ae1 7020 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-007ae2 7001 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-007ae3 70e1 .dw XT_ROT ; -- len xt addr
-007ae4 70e1 .dw XT_ROT ; -- xt addr len
-007ae5 7565 .dw XT_2DUP
-007ae6 731e .dw XT_2TO_R
-007ae7 70e1 .dw XT_ROT ; -- addr len xt
-007ae8 702a .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-007ae9 732d .dw XT_2R_FROM
-007aea 70e1 .dw XT_ROT
-007aeb 70b1 .dw XT_DUP
-007aec 7b4a .dw XT_DT_NULL
-007aed 7d7f .dw XT_EQUAL
-007aee 7036 .dw XT_DOCONDBRANCH
-007aef 7af3 DEST(PFA_RECOGNIZE_A1)
-007af0 70d9 .dw XT_DROP
-007af1 7154 .dw XT_ZERO
-007af2 7020 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-007af3 70f0 .dw XT_NIP
-007af4 70f0 .dw XT_NIP
-007af5 714b .dw XT_TRUE
-007af6 7020 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-007af7 ff06 .dw $ff06
-007af8 7464
-007af9 6e3a
-007afa 6d75 .db "dt:num"
-007afb 7ad0 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-007afc 7052 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-007afd 7b7f .dw XT_NOOP ; interpret
-007afe 01e2 .dw XT_LITERAL ; compile
-007aff 01e2 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-007b00 ff07 .dw $ff07
-007b01 7464
-007b02 643a
-007b03 756e
-007b04 006d .db "dt:dnum",0
-007b05 7af7 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-007b06 7052 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-007b07 7b7f .dw XT_NOOP ; interpret
-007b08 7d77 .dw XT_2LITERAL ; compile
-007b09 7d77 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-007b0a ff07 .dw $ff07
-007b0b 6572
-007b0c 3a63
-007b0d 756e
-007b0e 006d .db "rec:num",0
-007b0f 7b00 .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-007b10 7001 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-007b11 78f4 .dw XT_NUMBER
-007b12 7036 .dw XT_DOCONDBRANCH
-007b13 7b1c DEST(PFA_REC_NONUMBER)
-007b14 7d86 .dw XT_ONE
-007b15 7d7f .dw XT_EQUAL
-007b16 7036 .dw XT_DOCONDBRANCH
-007b17 7b1a DEST(PFA_REC_INTNUM2)
-007b18 7afc .dw XT_DT_NUM
-007b19 7020 .dw XT_EXIT
- PFA_REC_INTNUM2:
-007b1a 7b06 .dw XT_DT_DNUM
-007b1b 7020 .dw XT_EXIT
- PFA_REC_NONUMBER:
-007b1c 7b4a .dw XT_DT_NULL
-007b1d 7020 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-007b1e ff08 .dw $ff08
-007b1f 6572
-007b20 3a63
-007b21 6966
-007b22 646e .db "rec:find"
-007b23 7b0a .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-007b24 7001 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-007b25 79d0 .DW XT_FINDXT
-007b26 70b1 .dw XT_DUP
-007b27 711a .dw XT_ZEROEQUAL
-007b28 7036 .dw XT_DOCONDBRANCH
-007b29 7b2d DEST(PFA_REC_WORD_FOUND)
-007b2a 70d9 .dw XT_DROP
-007b2b 7b4a .dw XT_DT_NULL
-007b2c 7020 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-007b2d 7b34 .dw XT_DT_XT
-
-007b2e 7020 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-007b2f ff05 .dw $ff05
-007b30 7464
-007b31 783a
-007b32 0074 .db "dt:xt",0
-007b33 7b1e .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-007b34 7052 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-007b35 7b38 .dw XT_R_WORD_INTERPRET
-007b36 7b3c .dw XT_R_WORD_COMPILE
-007b37 7d77 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-007b38 7001 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-007b39 70d9 .dw XT_DROP ; the flags are in the way
-007b3a 702a .dw XT_EXECUTE
-007b3b 7020 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-007b3c 7001 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-007b3d 7121 .dw XT_ZEROLESS
-007b3e 7036 .dw XT_DOCONDBRANCH
-007b3f 7b42 DEST(PFA_R_WORD_COMPILE1)
-007b40 01cc .dw XT_COMMA
-007b41 7020 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-007b42 702a .dw XT_EXECUTE
-007b43 7020 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-007b44 ff07 .dw $ff07
-007b45 7464
-007b46 6e3a
-007b47 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-007b48 006c .db "dt:null"
-007b49 7b2f .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-007b4a 7052 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-007b4b 7b4e .dw XT_FAIL ; interpret
-007b4c 7b4e .dw XT_FAIL ; compile
-007b4d 7b4e .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-007b4e 7001 .dw DO_COLON
- PFA_FAIL:
- .endif
-007b4f 703d .dw XT_DOLITERAL
-007b50 fff3 .dw -13
-007b51 7841 .dw XT_THROW
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-007b52 ff06 .dw $ff06
-007b53 733f
-007b54 6174
-007b55 6b63 .db "?stack"
-007b56 7b44 .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-007b57 7001 .dw DO_COLON
- PFA_QSTACK:
- .endif
-007b58 7aa1 .dw XT_DEPTH
-007b59 7121 .dw XT_ZEROLESS
-007b5a 7036 .dw XT_DOCONDBRANCH
-007b5b 7b5f DEST(PFA_QSTACK1)
-007b5c 703d .dw XT_DOLITERAL
-007b5d fffc .dw -4
-007b5e 7841 .dw XT_THROW
- PFA_QSTACK1:
-007b5f 7020 .dw XT_EXIT
- .include "words/ver.asm"
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-007b60 ff03 .dw $ff03
-007b61 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-007b62 0072 .db "ver"
-007b63 7b52 .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-007b64 7001 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-007b65 750d .dw XT_ENV_FORTHNAME
-007b66 77a0 .dw XT_ITYPE
-007b67 77e2 .dw XT_SPACE
-007b68 7551 .dw XT_BASE
-007b69 7079 .dw XT_FETCH
-
-007b6a 751b .dw XT_ENV_FORTHVERSION
-007b6b 75dd .dw XT_DECIMAL
-007b6c 7d67 .dw XT_S2D
-007b6d 76be .dw XT_L_SHARP
-007b6e 76c6 .dw XT_SHARP
-007b6f 703d .dw XT_DOLITERAL
-007b70 002e .dw '.'
-007b71 76af .dw XT_HOLD
-007b72 76dc .dw XT_SHARP_S
-007b73 76e7 .dw XT_SHARP_G
-007b74 77fb .dw XT_TYPE
-007b75 7551 .dw XT_BASE
-007b76 7081 .dw XT_STORE
-007b77 77e2 .dw XT_SPACE
-007b78 7523 .dw XT_ENV_CPU
-007b79 77a0 .dw XT_ITYPE
-
-007b7a 7020 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-007b7b ff04 .dw $ff04
-007b7c 6f6e
-007b7d 706f .db "noop"
-007b7e 7b60 .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-007b7f 7001 .dw DO_COLON
- PFA_NOOP:
- .endif
-007b80 7020 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-007b81 ff06 .dw $ff06
-007b82 6e75
-007b83 7375
-007b84 6465 .db "unused"
-007b85 7b7b .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-007b86 7001 .dw DO_COLON
- PFA_UNUSED:
-007b87 728d .dw XT_SP_FETCH
-007b88 75bf .dw XT_HERE
-007b89 7193 .dw XT_MINUS
-007b8a 7020 .dw XT_EXIT
-
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-007b8b 0002 .dw $0002
-007b8c 6f74 .db "to"
-007b8d 7b81 .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-007b8e 7001 .dw DO_COLON
- PFA_TO:
- .endif
-007b8f 780a .dw XT_TICK
-007b90 7d70 .dw XT_TO_BODY
-007b91 754b .dw XT_STATE
-007b92 7079 .dw XT_FETCH
-007b93 7036 .dw XT_DOCONDBRANCH
-007b94 7b9f DEST(PFA_TO1)
-007b95 01c1 .dw XT_COMPILE
-007b96 7b99 .dw XT_DOTO
-007b97 01cc .dw XT_COMMA
-007b98 7020 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-007b99 7001 .dw DO_COLON
- PFA_DOTO:
- .endif
-007b9a 70f6 .dw XT_R_FROM
-007b9b 70b1 .dw XT_DUP
-007b9c 7bab .dw XT_ICELLPLUS
-007b9d 70ff .dw XT_TO_R
-007b9e 73cb .dw XT_FETCHI
- PFA_TO1:
-007b9f 70b1 .dw XT_DUP
-007ba0 7bab .dw XT_ICELLPLUS
-007ba1 7bab .dw XT_ICELLPLUS
-007ba2 73cb .dw XT_FETCHI
-007ba3 702a .dw XT_EXECUTE
-007ba4 7020 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-007ba5 ff07 .dw $FF07
-007ba6 2d69
-007ba7 6563
-007ba8 6c6c
-007ba9 002b .db "i-cell+",0
-007baa 7b8b .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-007bab 7001 .dw DO_COLON
- PFA_ICELLPLUS:
-007bac 722f .dw XT_1PLUS
-007bad 7020 .dw XT_EXIT
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-007bae ff07 .dw $ff07
-007baf 6445
-007bb0 6665
-007bb1 7265
-007bb2 0040 .db "Edefer@",0
-007bb3 7ba5 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-007bb4 7001 .dw DO_COLON
- PFA_EDEFERFETCH:
-007bb5 73cb .dw XT_FETCHI
-007bb6 735f .dw XT_FETCHE
-007bb7 7020 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-007bb8 ff07 .dw $ff07
-007bb9 6445
-007bba 6665
-007bbb 7265
-007bbc 0021 .db "Edefer!",0
-007bbd 7bae .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-007bbe 7001 .dw DO_COLON
- PFA_EDEFERSTORE:
-007bbf 73cb .dw XT_FETCHI
-007bc0 733b .dw XT_STOREE
-007bc1 7020 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-007bc2 ff07 .dw $ff07
-007bc3 6452
-007bc4 6665
-007bc5 7265
-007bc6 0040 .db "Rdefer@",0
-007bc7 7bb8 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-007bc8 7001 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-007bc9 73cb .dw XT_FETCHI
-007bca 7079 .dw XT_FETCH
-007bcb 7020 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-007bcc ff07 .dw $ff07
-007bcd 6452
-007bce 6665
-007bcf 7265
-007bd0 0021 .db "Rdefer!",0
-007bd1 7bc2 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-007bd2 7001 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-007bd3 73cb .dw XT_FETCHI
-007bd4 7081 .dw XT_STORE
-007bd5 7020 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-007bd6 ff07 .dw $ff07
-007bd7 6455
-007bd8 6665
-007bd9 7265
-007bda 0040 .db "Udefer@",0
-007bdb 7bcc .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-007bdc 7001 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-007bdd 73cb .dw XT_FETCHI
-007bde 7302 .dw XT_UP_FETCH
-007bdf 719d .dw XT_PLUS
-007be0 7079 .dw XT_FETCH
-007be1 7020 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-007be2 ff07 .dw $ff07
-007be3 6455
-007be4 6665
-007be5 7265
-007be6 0021 .db "Udefer!",0
-007be7 7bd6 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-007be8 7001 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-007be9 73cb .dw XT_FETCHI
-007bea 7302 .dw XT_UP_FETCH
-007beb 719d .dw XT_PLUS
-007bec 7081 .dw XT_STORE
-007bed 7020 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-007bee ff06 .dw $ff06
-007bef 6564
-007bf0 6566
-007bf1 2172 .db "defer!"
-007bf2 7be2 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-007bf3 7001 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-007bf4 7d70 .dw XT_TO_BODY
-007bf5 70b1 .dw XT_DUP
-007bf6 7bab .dw XT_ICELLPLUS
-007bf7 7bab .dw XT_ICELLPLUS
-007bf8 73cb .dw XT_FETCHI
-007bf9 702a .dw XT_EXECUTE
-007bfa 7020 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-007bfb ff06 .dw $ff06
-007bfc 6564
-007bfd 6566
-007bfe 4072 .db "defer@"
-007bff 7bee .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-007c00 7001 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-007c01 7d70 .dw XT_TO_BODY
-007c02 70b1 .dw XT_DUP
-007c03 7bab .dw XT_ICELLPLUS
-007c04 73cb .dw XT_FETCHI
-007c05 702a .dw XT_EXECUTE
-007c06 7020 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-007c07 ff07 .dw $ff07
-007c08 6428
-007c09 6665
-007c0a 7265
-007c0b 0029 .db "(defer)", 0
-007c0c 7bfb .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-007c0d 7001 .dw DO_COLON
- PFA_DODEFER:
-007c0e 019e .dw XT_DOCREATE
-007c0f 02fe .dw XT_REVEAL
-007c10 01c1 .dw XT_COMPILE
-007c11 7c13 .dw PFA_DODEFER1
-007c12 7020 .dw XT_EXIT
- PFA_DODEFER1:
-007c13 940e 0317 call_ DO_DODOES
-007c15 70b1 .dw XT_DUP
-007c16 7bab .dw XT_ICELLPLUS
-007c17 73cb .dw XT_FETCHI
-007c18 702a .dw XT_EXECUTE
-007c19 702a .dw XT_EXECUTE
-007c1a 7020 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-007c1b ff0f .dw $ff0f
-007c1c 6573
-007c1d 7261
-007c1e 6863
-007c1f 772d
-007c20 726f
-007c21 6c64
-007c22 7369
-007c23 0074 .db "search-wordlist",0
-007c24 7c07 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-007c25 7001 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-007c26 70ff .dw XT_TO_R
-007c27 7154 .dw XT_ZERO
-007c28 703d .dw XT_DOLITERAL
-007c29 7c3a .dw XT_ISWORD
-007c2a 70f6 .dw XT_R_FROM
-007c2b 7c57 .dw XT_TRAVERSEWORDLIST
-007c2c 70b1 .dw XT_DUP
-007c2d 711a .dw XT_ZEROEQUAL
-007c2e 7036 .dw XT_DOCONDBRANCH
-007c2f 7c34 DEST(PFA_SEARCH_WORDLIST1)
-007c30 756e .dw XT_2DROP
-007c31 70d9 .dw XT_DROP
-007c32 7154 .dw XT_ZERO
-007c33 7020 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-007c34 70b1 .dw XT_DUP
-007c35 7c7e .dw XT_NFA2CFA
- ; .. and get the header flag
-007c36 70c4 .dw XT_SWAP
-007c37 0184 .dw XT_NAME2FLAGS
-007c38 0172 .dw XT_IMMEDIATEQ
-007c39 7020 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-007c3a 7001 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-007c3b 70ff .dw XT_TO_R
-007c3c 70d9 .dw XT_DROP
-007c3d 7565 .dw XT_2DUP
-007c3e 7108 .dw XT_R_FETCH ; -- addr len addr len nt
-007c3f 7c72 .dw XT_NAME2STRING
-007c40 7c88 .dw XT_ICOMPARE ; (-- addr len f )
-007c41 7036 .dw XT_DOCONDBRANCH
-007c42 7c48 DEST(PFA_ISWORD3)
- ; not now
-007c43 70f6 .dw XT_R_FROM
-007c44 70d9 .dw XT_DROP
-007c45 7154 .dw XT_ZERO
-007c46 714b .dw XT_TRUE ; maybe next word
-007c47 7020 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-007c48 756e .dw XT_2DROP
-007c49 70f6 .dw XT_R_FROM
-007c4a 7154 .dw XT_ZERO ; finish traverse-wordlist
-007c4b 7020 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-007c4c ff11 .dw $ff11
-007c4d 7274
-007c4e 7661
-007c4f 7265
-007c50 6573
-007c51 772d
-007c52 726f
-007c53 6c64
-007c54 7369
-007c55 0074 .db "traverse-wordlist",0
-007c56 7c1b .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-007c57 7001 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-007c58 735f .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-007c59 70b1 .dw XT_DUP ; ( -- xt nt nt )
-007c5a 7036 .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-007c5b 7c68 DEST(PFA_TRAVERSEWORDLIST2)
-007c5c 7565 .dw XT_2DUP
-007c5d 731e .dw XT_2TO_R
-007c5e 70c4 .dw XT_SWAP
-007c5f 702a .dw XT_EXECUTE
-007c60 732d .dw XT_2R_FROM
-007c61 70e1 .dw XT_ROT
-007c62 7036 .dw XT_DOCONDBRANCH
-007c63 7c68 DEST(PFA_TRAVERSEWORDLIST2)
-007c64 047b .dw XT_NFA2LFA
-007c65 73cb .dw XT_FETCHI
-007c66 702f .dw XT_DOBRANCH ; ( -- addr )
-007c67 7c59 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-007c68 756e .dw XT_2DROP
-007c69 7020 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-007c6a ff0b .dw $ff0b
-007c6b 616e
-007c6c 656d
-007c6d 733e
-007c6e 7274
-007c6f 6e69
-007c70 0067 .db "name>string",0
-007c71 7c4c .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-007c72 7001 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-007c73 77cc .dw XT_ICOUNT ; ( -- addr n )
-007c74 703d .dw XT_DOLITERAL
-007c75 00ff .dw 255
-007c76 7213 .dw XT_AND ; mask immediate bit
-007c77 7020 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-007c78 ff07 .dw $ff07
-007c79 666e
-007c7a 3e61
-007c7b 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-007c7c 0061 .db "nfa>cfa"
-007c7d 7c6a .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-007c7e 7001 .dw DO_COLON
- PFA_NFA2CFA:
-007c7f 047b .dw XT_NFA2LFA ; skip to link field
-007c80 722f .dw XT_1PLUS ; next is the execution token
-007c81 7020 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-007c82 ff08 .dw $ff08
-007c83 6369
-007c84 6d6f
-007c85 6170
-007c86 6572 .db "icompare"
-007c87 7c78 .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-007c88 7001 .dw DO_COLON
- PFA_ICOMPARE:
-007c89 70ff .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-007c8a 70cf .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-007c8b 70f6 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-007c8c 7113 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-007c8d 7036 .dw XT_DOCONDBRANCH
-007c8e 7c93 .dw PFA_ICOMPARE_SAMELEN
-007c8f 756e .dw XT_2DROP
-007c90 70d9 .dw XT_DROP
-007c91 714b .dw XT_TRUE
-007c92 7020 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-007c93 70c4 .dw XT_SWAP ; ( -- r-addr f-addr len )
-007c94 7154 .dw XT_ZERO
-007c95 028b .dw XT_QDOCHECK
-007c96 7036 .dw XT_DOCONDBRANCH
-007c97 7cb6 .dw PFA_ICOMPARE_DONE
-007c98 729b .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-007c99 70cf .dw XT_OVER
-007c9a 7079 .dw XT_FETCH
- .if WANT_IGNORECASE == 1
- .endif
-007c9b 70cf .dw XT_OVER
-007c9c 73cb .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-007c9d 70b1 .dw XT_DUP
- ;.dw XT_BYTESWAP
-007c9e 703d .dw XT_DOLITERAL
-007c9f 0100 .dw $100
-007ca0 715c .dw XT_ULESS
-007ca1 7036 .dw XT_DOCONDBRANCH
-007ca2 7ca7 .dw PFA_ICOMPARE_LASTCELL
-007ca3 70c4 .dw XT_SWAP
-007ca4 703d .dw XT_DOLITERAL
-007ca5 00ff .dw $00FF
-007ca6 7213 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-007ca7 7113 .dw XT_NOTEQUAL
-007ca8 7036 .dw XT_DOCONDBRANCH
-007ca9 7cae .dw PFA_ICOMPARE_NEXTLOOP
-007caa 756e .dw XT_2DROP
-007cab 714b .dw XT_TRUE
-007cac 72d4 .dw XT_UNLOOP
-007cad 7020 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-007cae 722f .dw XT_1PLUS
-007caf 70c4 .dw XT_SWAP
-007cb0 755e .dw XT_CELLPLUS
-007cb1 70c4 .dw XT_SWAP
-007cb2 703d .dw XT_DOLITERAL
-007cb3 0002 .dw 2
-007cb4 72ba .dw XT_DOPLUSLOOP
-007cb5 7c99 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-007cb6 756e .dw XT_2DROP
-007cb7 7154 .dw XT_ZERO
-007cb8 7020 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- .endif
-
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-007cb9 ff01 .dw $ff01
-007cba 002a .db "*",0
-007cbb 7c82 .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-007cbc 7001 .dw DO_COLON
- PFA_STAR:
- .endif
-
-007cbd 71a6 .dw XT_MSTAR
-007cbe 70d9 .dw XT_DROP
-007cbf 7020 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-007cc0 ff01 .dw $FF01
-007cc1 006a .db "j",0
-007cc2 7cb9 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-007cc3 7001 .dw DO_COLON
- PFA_J:
-007cc4 7276 .dw XT_RP_FETCH
-007cc5 703d .dw XT_DOLITERAL
-007cc6 0007 .dw 7
-007cc7 719d .dw XT_PLUS
-007cc8 7079 .dw XT_FETCH
-007cc9 7276 .dw XT_RP_FETCH
-007cca 703d .dw XT_DOLITERAL
-007ccb 0009 .dw 9
-007ccc 719d .dw XT_PLUS
-007ccd 7079 .dw XT_FETCH
-007cce 719d .dw XT_PLUS
-007ccf 7020 .dw XT_EXIT
-
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-007cd0 ff04 .dw $ff04
-007cd1 6164
-007cd2 7362 .db "dabs"
-007cd3 7cc0 .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-007cd4 7001 .dw DO_COLON
- PFA_DABS:
-007cd5 70b1 .dw XT_DUP
-007cd6 7121 .dw XT_ZEROLESS
-007cd7 7036 .dw XT_DOCONDBRANCH
-007cd8 7cda .dw PFA_DABS1
-007cd9 7ce1 .dw XT_DNEGATE
- PFA_DABS1:
-007cda 7020 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-007cdb ff07 .dw $ff07
-007cdc 6e64
-007cdd 6765
-007cde 7461
-007cdf 0065 .db "dnegate",0
-007ce0 7cd0 .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-007ce1 7001 .dw DO_COLON
- PFA_DNEGATE:
-007ce2 743b .dw XT_DINVERT
-007ce3 7d86 .dw XT_ONE
-007ce4 7154 .dw XT_ZERO
-007ce5 7415 .dw XT_DPLUS
-007ce6 7020 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-007ce7 ff05 .dw $ff05
-007ce8 6d63
-007ce9 766f
-007cea 0065 .db "cmove",0
-007ceb 7cdb .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-007cec 7ced .dw PFA_CMOVE
- PFA_CMOVE:
-007ced 93bf push xh
-007cee 93af push xl
-007cef 91e9 ld zl, Y+
-007cf0 91f9 ld zh, Y+ ; addr-to
-007cf1 91a9 ld xl, Y+
-007cf2 91b9 ld xh, Y+ ; addr-from
-007cf3 2f09 mov temp0, tosh
-007cf4 2b08 or temp0, tosl
-007cf5 f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-007cf6 911d ld temp1, X+
-007cf7 9311 st Z+, temp1
-007cf8 9701 sbiw tosl, 1
-007cf9 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-007cfa 91af pop xl
-007cfb 91bf pop xh
-007cfc 9189
-007cfd 9199 loadtos
-007cfe 940c 7005 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-007d00 ff05 .dw $ff05
-007d01 7332
-007d02 6177
-007d03 0070 .db "2swap",0
-007d04 7ce7 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-007d05 7001 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-007d06 70e1 .dw XT_ROT
-007d07 70ff .dw XT_TO_R
-007d08 70e1 .dw XT_ROT
-007d09 70f6 .dw XT_R_FROM
-007d0a 7020 .dw XT_EXIT
-
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-007d0b ff0a .dw $ff0a
-007d0c 6572
-007d0d 6966
-007d0e 6c6c
-007d0f 742d
-007d10 6269 .db "refill-tib"
-007d11 7d00 .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-007d12 7001 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-007d13 7d2e .dw XT_TIB
-007d14 703d .dw XT_DOLITERAL
-007d15 005a .dw TIB_SIZE
-007d16 7891 .dw XT_ACCEPT
-007d17 7d34 .dw XT_NUMBERTIB
-007d18 7081 .dw XT_STORE
-007d19 7154 .dw XT_ZERO
-007d1a 757e .dw XT_TO_IN
-007d1b 7081 .dw XT_STORE
-007d1c 714b .dw XT_TRUE ; -1
-007d1d 7020 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-007d1e ff0a .dw $FF0A
-007d1f 6f73
-007d20 7275
-007d21 6563
-007d22 742d
-007d23 6269 .db "source-tib"
-007d24 7d0b .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-007d25 7001 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-007d26 7d2e .dw XT_TIB
-007d27 7d34 .dw XT_NUMBERTIB
-007d28 7079 .dw XT_FETCH
-007d29 7020 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-007d2a ff03 .dw $ff03
-007d2b 6974
-007d2c 0062 .db "tib",0
-007d2d 7d1e .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-007d2e 7048 .dw PFA_DOVARIABLE
- PFA_TIB:
-007d2f 0168 .dw ram_tib
- .dseg
-000168 ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-007d30 ff04 .dw $ff04
-007d31 7423
-007d32 6269 .db "#tib"
-007d33 7d2a .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-007d34 7048 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-007d35 01c2 .dw ram_sharptib
- .dseg
-0001c2 ram_sharptib: .byte 2
- .cseg
- .endif
-
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-007d36 ff06 .dw $ff06
-007d37 6565
-007d38 723e
-007d39 6d61 .db "ee>ram"
-007d3a 7d30 .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-007d3b 7001 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-007d3c 7154 .dw XT_ZERO
-007d3d 729b .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-007d3e 70cf .dw XT_OVER
-007d3f 735f .dw XT_FETCHE
-007d40 70cf .dw XT_OVER
-007d41 7081 .dw XT_STORE
-007d42 755e .dw XT_CELLPLUS
-007d43 70c4 .dw XT_SWAP
-007d44 755e .dw XT_CELLPLUS
-007d45 70c4 .dw XT_SWAP
-007d46 72c9 .dw XT_DOLOOP
-007d47 7d3e .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-007d48 756e .dw XT_2DROP
-007d49 7020 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-007d4a ff08 .dw $ff08
-007d4b 6e69
-007d4c 7469
-007d4d 722d
-007d4e 6d61 .db "init-ram"
-007d4f 7d36 .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-007d50 7001 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-007d51 703d .dw XT_DOLITERAL
-007d52 006e .dw EE_INITUSER
-007d53 7302 .dw XT_UP_FETCH
-007d54 703d .dw XT_DOLITERAL
-007d55 0022 .dw SYSUSERSIZE
-007d56 7204 .dw XT_2SLASH
-007d57 7d3b .dw XT_EE2RAM
-007d58 7020 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .endif
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-007d59 ff06 .dw $ff06
-007d5a 6f62
-007d5b 6e75
-007d5c 7364 .db "bounds"
-007d5d 7d4a .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-007d5e 7001 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-007d5f 70cf .dw XT_OVER
-007d60 719d .dw XT_PLUS
-007d61 70c4 .dw XT_SWAP
-007d62 7020 .dw XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-007d63 ff03 .dw $ff03
-007d64 3e73
-007d65 0064 .db "s>d",0
-007d66 7d59 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-007d67 7001 .dw DO_COLON
- PFA_S2D:
- .endif
-007d68 70b1 .dw XT_DUP
-007d69 7121 .dw XT_ZEROLESS
-007d6a 7020 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-007d6b ff05 .dw $ff05
-007d6c 623e
-007d6d 646f
-007d6e 0079 .db ">body",0
-007d6f 7d63 .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-007d70 7230 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>4000
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-007d71 0008 .dw $0008
-007d72 6c32
-007d73 7469
-007d74 7265
-007d75 6c61 .db "2literal"
-007d76 7d6b .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-007d77 7001 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-007d78 70c4 .dw XT_SWAP
-007d79 01e2 .dw XT_LITERAL
-007d7a 01e2 .dw XT_LITERAL
-007d7b 7020 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-007d7c ff01 .dw $ff01
-007d7d 003d .db "=",0
-007d7e 7d71 .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-007d7f 7001 .dw DO_COLON
- PFA_EQUAL:
-007d80 7193 .dw XT_MINUS
-007d81 711a .dw XT_ZEROEQUAL
-007d82 7020 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-007d83 ff01 .dw $ff01
-007d84 0031 .db "1",0
-007d85 7d7c .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-007d86 7048 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-007d87 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-007d88 ff01 .dw $ff01
-007d89 0032 .db "2",0
-007d8a 7d83 .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-007d8b 7048 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-007d8c 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-007d8d ff02 .dw $ff02
-007d8e 312d .db "-1"
-007d8f 7d88 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-007d90 7048 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-007d91 ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; do not delete it!
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000038 ff ff
- ; some configs
-00003a 8b 05 CFG_DP: .dw DPSTART ; Dictionary Pointer
-00003c c4 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00003e 92 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-000040 33 04 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-000042 60 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000044 b0 10 CFG_LP0: .dw stackstart+1
-000046 dd 04 CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000048 32 75 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-00004a 4c 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-00004c 8d 7d CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00004e 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-000050 4c 00 .dw CFG_FORTHWORDLIST ; get/set-order
-000052 .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-000060 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-000062 24 7b .dw XT_REC_FIND
-000064 10 7b .dw XT_REC_NUM
-000066 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-00006a 7e 73 .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-00006c 6c 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00006e 00 00 .dw 0 ; USER_STATE
-000070 00 00 .dw 0 ; USER_FOLLOWER
-000072 ff 10 .dw rstackstart ; USER_RP
-000074 af 10 .dw stackstart ; USER_SP0
-000076 af 10 .dw stackstart ; USER_SP
-
-000078 00 00 .dw 0 ; USER_HANDLER
-00007a 0a 00 .dw 10 ; USER_BASE
-
-00007c a7 00 .dw XT_TX ; USER_EMIT
-00007e b5 00 .dw XT_TXQ ; USER_EMITQ
-000080 7c 00 .dw XT_RX ; USER_KEY
-000082 97 00 .dw XT_RXQ ; USER_KEYQ
-000084 25 7d .dw XT_SOURCETIB ; USER_SOURCE
-000086 00 00 .dw 0 ; USER_G_IN
-000088 12 7d .dw XT_REFILLTIB ; USER_REFILL
-00008a ea 79 .dw XT_DEFAULT_PROMPTOK
-00008c 09 7a .dw XT_DEFAULT_PROMPTERROR
-00008e f9 79 .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-000090 19 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega644" register use summary:
-r0 : 25 r1 : 5 r2 : 10 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 89 r17: 61 r18: 61 r19: 37 r20: 13 r21: 11 r22: 11 r23: 3
-r24: 212 r25: 145 r26: 28 r27: 17 r28: 7 r29: 4 r30: 90 r31: 49
-x : 4 y : 217 z : 50
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega644" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 3 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 22 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 7 cbr : 1
-clc : 2 clh : 0 cli : 7 cln : 0 clr : 14 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 eor : 3 fmul : 0 fmuls : 0
-fmulsu: 0 icall : 0 ijmp : 1 in : 25 inc : 3 jmp : 14
-ld : 145 ldd : 4 ldi : 41 lds : 1 lpm : 16 lsl : 14
-lsr : 2 mov : 16 movw : 72 mul : 5 muls : 1 mulsu : 2
-neg : 0 nop : 0 or : 9 ori : 2 out : 22 pop : 49
-push : 43 rcall : 41 ret : 7 reti : 1 rjmp : 105 rol : 23
-ror : 6 sbc : 9 sbci : 3 sbi : 8 sbic : 3 sbis : 0
-sbiw : 16 sbr : 0 sbrc : 5 sbrs : 7 sec : 1 seh : 0
-sei : 1 sen : 0 ser : 4 ses : 0 set : 0 sev : 0
-sez : 0 sleep : 0 spm : 2 st : 81 std : 8 sts : 1
-sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-Instructions used: 72 out of 113 (63.7%)
-
-"ATmega644" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x00fb24 2088 14590 16678 65536 25.4%
-[.dseg] 0x000100 0x0001c4 0 196 196 4096 4.8%
-[.eseg] 0x000000 0x000092 0 146 146 2048 7.1%
-
-Assembly complete, 0 errors, 8 warnings
diff --git a/amforth-6.5/appl/eval-pollin/p644-16.map b/amforth-6.5/appl/eval-pollin/p644-16.map
deleted file mode 100644
index 414fea5..0000000
--- a/amforth-6.5/appl/eval-pollin/p644-16.map
+++ /dev/null
@@ -1,2133 +0,0 @@
-
-AVRASM ver. 2.1.52 p644-16.asm Sun Apr 30 20:10:15 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000096
-EQU SIGNATURE_002 00000009
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU PCMSK3 00000073
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK2 0000006d
-EQU PCMSK1 0000006c
-EQU PCMSK0 0000006b
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU OCDR 00000031
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU PORTA 00000002
-EQU DDRA 00000001
-EQU PINA 00000000
-EQU ACME 00000006
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSRSYNC 00000000
-EQU PSR10 00000000
-EQU TSM 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU JTD 00000007
-EQU JTRF 00000004
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU SIGRD 00000005
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC20 00000004
-EQU ISC21 00000005
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INT2 00000002
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU INTF2 00000002
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCIE3 00000003
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU PCIF3 00000003
-EQU PCINT24 00000000
-EQU PCINT25 00000001
-EQU PCINT26 00000002
-EQU PCINT27 00000003
-EQU PCINT28 00000004
-EQU PCINT29 00000005
-EQU PCINT30 00000006
-EQU PCINT31 00000007
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT15 00000007
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ADC6D 00000006
-EQU ADC7D 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU PWM10 00000000
-EQU WGM11 00000001
-EQU PWM11 00000001
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU CTC1 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEAR10 00000002
-EQU EEAR11 00000003
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 00007fff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00001000
-EQU RAMEND 000010ff
-EQU XRAMEND 00000000
-EQU E2END 000007ff
-EQU EEPROMEND 000007ff
-EQU EEADRBITS 0000000b
-EQU NRWW_START_ADDR 00007000
-EQU NRWW_STOP_ADDR 00007fff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 00006fff
-EQU PAGESIZE 00000080
-EQU FIRSTBOOTSTART 00007e00
-EQU SECONDBOOTSTART 00007c00
-EQU THIRDBOOTSTART 00007800
-EQU FOURTHBOOTSTART 00007000
-EQU SMALLBOOTSTART 00007e00
-EQU LARGEBOOTSTART 00007000
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU PCI0addr 00000008
-EQU PCI1addr 0000000a
-EQU PCI2addr 0000000c
-EQU PCI3addr 0000000e
-EQU WDTaddr 00000010
-EQU OC2Aaddr 00000012
-EQU OC2Baddr 00000014
-EQU OVF2addr 00000016
-EQU ICP1addr 00000018
-EQU OC1Aaddr 0000001a
-EQU OC1Baddr 0000001c
-EQU OVF1addr 0000001e
-EQU OC0Aaddr 00000020
-EQU OC0Baddr 00000022
-EQU OVF0addr 00000024
-EQU SPIaddr 00000026
-EQU URXC0addr 00000028
-EQU UDRE0addr 0000002a
-EQU UTXC0addr 0000002c
-EQU ACIaddr 0000002e
-EQU ADCCaddr 00000030
-EQU ERDYaddr 00000032
-EQU TWIaddr 00000034
-EQU SPMRaddr 00000036
-EQU INT_VECTORS_SIZE 00000038
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_USART0 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_JTAG 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_EEPROM 00000000
-SET WANT_TWI 00000000
-SET WANT_SPI 00000000
-SET WANT_CPU 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 0000012d
-EQU INTVECTORS 0000001c
-CSEG mcu_info 00000037
-CSEG mcu_ramsize 00000037
-CSEG mcu_eepromsize 00000038
-CSEG mcu_maxdp 00000039
-CSEG mcu_numints 0000003a
-CSEG mcu_name 0000003b
-SET codestart 00000041
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000000
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000010ff
-SET stackstart 000010af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000001e
-SET VE_HEAD 00007d8d
-SET VE_ENVHEAD 00007532
-SET AMFORTH_RO_SEG 00007001
-EQU F_CPU 00f42400
-EQU TIMER_INT 00000016
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU URXCaddr 00000028
-EQU UDREaddr 0000002a
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 00000041
-CSEG XT_TO_RXBUF 00000047
-CSEG PFA_rx_tobuf 00000048
-CSEG DO_NEXT 00007005
-CSEG VE_ISR_RX 00000058
-CSEG XT_ISR_RX 0000005d
-CSEG DO_COLON 00007001
-CSEG usart_rx_isr 0000005e
-CSEG XT_DOLITERAL 0000703d
-CSEG XT_CFETCH 00007098
-CSEG XT_DUP 000070b1
-CSEG XT_EQUAL 00007d7f
-CSEG XT_DOCONDBRANCH 00007036
-CSEG usart_rx_isr1 00000068
-CSEG XT_COLD 00007a59
-CSEG XT_EXIT 00007020
-CSEG XT_USART_INIT_RX_BUFFER 0000006a
-CSEG PFA_USART_INIT_RX_BUFFER 0000006b
-CSEG XT_INTSTORE 00007487
-CSEG XT_ZERO 00007154
-CSEG XT_FILL 000074cf
-CSEG VE_RX_BUFFER 00000077
-CSEG XT_RX_BUFFER 0000007c
-CSEG PFA_RX_BUFFER 0000007d
-CSEG XT_RXQ_BUFFER 00000097
-CSEG XT_PLUS 0000719d
-CSEG XT_SWAP 000070c4
-CSEG XT_1PLUS 0000722f
-CSEG XT_AND 00007213
-CSEG XT_CSTORE 0000708d
-CSEG VE_RXQ_BUFFER 00000091
-CSEG PFA_RXQ_BUFFER 00000098
-CSEG XT_PAUSE 00007a51
-CSEG XT_NOTEQUAL 00007113
-SET XT_RX 0000007c
-SET XT_RXQ 00000097
-SET XT_USART_INIT_RX 0000006a
-CSEG VE_TX_POLL 000000a1
-CSEG XT_TX_POLL 000000a7
-CSEG PFA_TX_POLL 000000a8
-CSEG XT_TXQ_POLL 000000b5
-CSEG VE_TXQ_POLL 000000af
-CSEG PFA_TXQ_POLL 000000b6
-SET XT_TX 000000a7
-SET XT_TXQ 000000b5
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000be
-CSEG XT_UBRR 000000c2
-CSEG PFA_DOVALUE1 0000706f
-CSEG PFA_UBRR 000000c3
-ESEG EE_UBRRVAL 00000090
-CSEG XT_EDEFERFETCH 00007bb4
-CSEG XT_EDEFERSTORE 00007bbe
-CSEG VE_USART 000000c6
-CSEG XT_USART 000000cb
-CSEG PFA_USART 000000cc
-CSEG XT_BYTESWAP 000072f9
-EQU OW_PORT 00000005
-EQU OW_BIT 00000004
-SET OW_DDR 00000004
-SET OW_PIN 00000003
-CSEG VE_OW_RESET 000000e1
-CSEG XT_OW_RESET 000000e7
-CSEG PFA_OW_RESET 000000e8
-SET cycles 00000000
-SET loop_cycles 00000fa0
-CSEG VE_OW_SLOT 00000105
-CSEG XT_OW_SLOT 0000010b
-CSEG PFA_OW_SLOT 0000010c
-CSEG PFA_OW_SLOT0 00000119
-SET AMFORTH_NRWW_SIZE 00001ffc
-SET corepc 0000012d
-CSEG PFA_COLD 00007a5a
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 00000144
-CSEG XT_MPLUS 00000147
-CSEG PFA_MPLUS 00000148
-CSEG XT_S2D 00007d67
-CSEG XT_DPLUS 00007415
-CSEG VE_UDSTAR 0000014b
-CSEG XT_UDSTAR 0000014f
-CSEG PFA_UDSTAR 00000150
-CSEG XT_TO_R 000070ff
-CSEG XT_UMSTAR 000071e0
-CSEG XT_DROP 000070d9
-CSEG XT_R_FROM 000070f6
-CSEG XT_ROT 000070e1
-CSEG VE_UMAX 0000015a
-CSEG XT_UMAX 0000015e
-CSEG PFA_UMAX 0000015f
-CSEG XT_2DUP 00007565
-CSEG XT_ULESS 0000715c
-CSEG UMAX1 00000164
-CSEG VE_UMIN 00000166
-CSEG XT_UMIN 0000016a
-CSEG PFA_UMIN 0000016b
-CSEG XT_UGREATER 00007167
-CSEG UMIN1 00000170
-CSEG XT_IMMEDIATEQ 00000172
-CSEG PFA_IMMEDIATEQ 00000173
-CSEG XT_ZEROEQUAL 0000711a
-CSEG IMMEDIATEQ1 0000017b
-CSEG XT_ONE 00007d86
-CSEG XT_TRUE 0000714b
-CSEG VE_NAME2FLAGS 0000017d
-CSEG XT_NAME2FLAGS 00000184
-CSEG PFA_NAME2FLAGS 00000185
-CSEG XT_FETCHI 000073cb
-CSEG VE_NEWEST 0000018a
-CSEG XT_NEWEST 0000018f
-CSEG PFA_DOVARIABLE 00007048
-CSEG PFA_NEWEST 00000190
-DSEG ram_newest 0000012e
-CSEG VE_LATEST 00000191
-CSEG XT_LATEST 00000196
-CSEG PFA_LATEST 00000197
-DSEG ram_latest 00000132
-CSEG VE_DOCREATE 00000198
-CSEG XT_DOCREATE 0000019e
-CSEG PFA_DOCREATE 0000019f
-CSEG XT_PARSENAME 000079b4
-CSEG XT_WLSCOPE 000002f5
-CSEG XT_CELLPLUS 0000755e
-CSEG XT_STORE 00007081
-CSEG XT_HEADER 000002da
-CSEG VE_BACKSLASH 000001a9
-CSEG XT_BACKSLASH 000001ac
-CSEG PFA_BACKSLASH 000001ad
-CSEG XT_SOURCE 0000799b
-CSEG XT_NIP 000070f0
-CSEG XT_TO_IN 0000757e
-CSEG VE_LPAREN 000001b2
-CSEG XT_LPAREN 000001b5
-CSEG PFA_LPAREN 000001b6
-CSEG XT_PARSE 00007987
-CSEG XT_2DROP 0000756e
-CSEG VE_COMPILE 000001bb
-CSEG XT_COMPILE 000001c1
-CSEG PFA_COMPILE 000001c2
-CSEG XT_ICELLPLUS 00007bab
-CSEG XT_COMMA 000001cc
-CSEG VE_COMMA 000001c9
-CSEG PFA_COMMA 000001cd
-CSEG XT_DP 000075ae
-CSEG XT_STOREI 00007373
-CSEG XT_DOTO 00007b99
-CSEG PFA_DP 000075af
-CSEG VE_BRACKETTICK 000001d4
-CSEG XT_BRACKETTICK 000001d8
-CSEG PFA_BRACKETTICK 000001d9
-CSEG XT_TICK 0000780a
-CSEG XT_LITERAL 000001e2
-CSEG VE_LITERAL 000001dc
-CSEG PFA_LITERAL 000001e3
-CSEG VE_SLITERAL 000001e7
-CSEG XT_SLITERAL 000001ed
-CSEG PFA_SLITERAL 000001ee
-CSEG XT_DOSLITERAL 0000776d
-CSEG XT_SCOMMA 0000777b
-CSEG XT_GMARK 000001f2
-CSEG PFA_GMARK 000001f3
-CSEG XT_GRESOLVE 000001f7
-CSEG PFA_GRESOLVE 000001f8
-CSEG XT_QSTACK 00007b57
-CSEG XT_LMARK 000001fd
-CSEG PFA_LMARK 000001fe
-CSEG XT_LRESOLVE 00000200
-CSEG PFA_LRESOLVE 00000201
-CSEG VE_AHEAD 00000204
-CSEG XT_AHEAD 00000209
-CSEG PFA_AHEAD 0000020a
-CSEG XT_DOBRANCH 0000702f
-CSEG VE_IF 0000020e
-CSEG XT_IF 00000211
-CSEG PFA_IF 00000212
-CSEG VE_ELSE 00000216
-CSEG XT_ELSE 0000021a
-CSEG PFA_ELSE 0000021b
-CSEG VE_THEN 00000221
-CSEG XT_THEN 00000225
-CSEG PFA_THEN 00000226
-CSEG VE_BEGIN 00000228
-CSEG XT_BEGIN 0000022d
-CSEG PFA_BEGIN 0000022e
-CSEG VE_WHILE 00000230
-CSEG XT_WHILE 00000235
-CSEG PFA_WHILE 00000236
-CSEG VE_REPEAT 00000239
-CSEG XT_REPEAT 0000023e
-CSEG PFA_REPEAT 0000023f
-CSEG XT_AGAIN 00000252
-CSEG VE_UNTIL 00000242
-CSEG XT_UNTIL 00000247
-CSEG PFA_UNTIL 00000248
-CSEG VE_AGAIN 0000024d
-CSEG PFA_AGAIN 00000253
-CSEG VE_DO 00000257
-CSEG XT_DO 0000025a
-CSEG PFA_DO 0000025b
-CSEG XT_DODO 0000729b
-CSEG XT_TO_L 000002b5
-CSEG VE_LOOP 00000261
-CSEG XT_LOOP 00000265
-CSEG PFA_LOOP 00000266
-CSEG XT_DOLOOP 000072c9
-CSEG XT_ENDLOOP 0000029c
-CSEG VE_PLUSLOOP 0000026a
-CSEG XT_PLUSLOOP 0000026f
-CSEG PFA_PLUSLOOP 00000270
-CSEG XT_DOPLUSLOOP 000072ba
-CSEG VE_LEAVE 00000274
-CSEG XT_LEAVE 00000279
-CSEG PFA_LEAVE 0000027a
-CSEG XT_UNLOOP 000072d4
-CSEG VE_QDO 0000027f
-CSEG XT_QDO 00000283
-CSEG PFA_QDO 00000284
-CSEG XT_QDOCHECK 0000028b
-CSEG PFA_QDOCHECK 0000028c
-CSEG PFA_QDOCHECK1 00000293
-CSEG XT_INVERT 000071fd
-CSEG VE_ENDLOOP 00000296
-CSEG PFA_ENDLOOP 0000029d
-CSEG LOOP1 0000029e
-CSEG XT_L_FROM 000002a9
-CSEG XT_QDUP 000070b9
-CSEG LOOP2 000002a5
-CSEG VE_L_FROM 000002a6
-CSEG PFA_L_FROM 000002aa
-CSEG XT_LP 000002c8
-CSEG XT_FETCH 00007079
-CSEG XT_PLUSSTORE 00007265
-CSEG VE_TO_L 000002b2
-CSEG PFA_TO_L 000002b6
-CSEG XT_TWO 00007d8b
-CSEG VE_LP0 000002bd
-CSEG XT_LP0 000002c1
-CSEG PFA_LP0 000002c2
-ESEG CFG_LP0 00000044
-CSEG VE_LP 000002c5
-CSEG PFA_LP 000002c9
-DSEG ram_lp 00000134
-CSEG VE_CREATE 000002ca
-CSEG XT_CREATE 000002cf
-CSEG PFA_CREATE 000002d0
-CSEG XT_REVEAL 000002fe
-CSEG PFA_DOCONSTANT 00007052
-CSEG VE_HEADER 000002d5
-CSEG PFA_HEADER 000002db
-CSEG XT_GREATERZERO 00007128
-CSEG PFA_HEADER1 000002ec
-CSEG XT_OR 0000721c
-CSEG XT_DOSCOMMA 0000777f
-CSEG XT_FETCHE 0000735f
-CSEG XT_THROW 00007841
-CSEG VE_WLSCOPE 000002ef
-CSEG PFA_DODEFER1 00007c13
-CSEG PFA_WLSCOPE 000002f6
-ESEG CFG_WLSCOPE 00000040
-CSEG VE_REVEAL 000002f9
-CSEG PFA_REVEAL 000002ff
-CSEG REVEAL1 00000309
-CSEG XT_STOREE 0000733b
-CSEG VE_DOES 0000030a
-CSEG XT_DOES 0000030f
-CSEG PFA_DOES 00000310
-CSEG XT_DODOES 00000322
-CSEG DO_DODOES 00000317
-CSEG PFA_DODOES 00000323
-CSEG XT_NFA2CFA 00007c7e
-CSEG VE_COLON 0000032b
-CSEG XT_COLON 0000032e
-CSEG PFA_COLON 0000032f
-CSEG XT_COLONNONAME 00000339
-CSEG VE_COLONNONAME 00000333
-CSEG PFA_COLONNONAME 0000033a
-CSEG XT_RBRACKET 0000034e
-CSEG VE_SEMICOLON 00000342
-CSEG XT_SEMICOLON 00000345
-CSEG PFA_SEMICOLON 00000346
-CSEG XT_LBRACKET 00000356
-CSEG VE_RBRACKET 0000034b
-CSEG PFA_RBRACKET 0000034f
-CSEG XT_STATE 0000754b
-CSEG VE_LBRACKET 00000353
-CSEG PFA_LBRACKET 00000357
-CSEG VE_VARIABLE 0000035b
-CSEG XT_VARIABLE 00000361
-CSEG PFA_VARIABLE 00000362
-CSEG XT_HERE 000075bf
-CSEG XT_CONSTANT 0000036d
-CSEG XT_ALLOT 000075c8
-CSEG VE_CONSTANT 00000367
-CSEG PFA_CONSTANT 0000036e
-CSEG VE_USER 00000374
-CSEG XT_USER 00000378
-CSEG PFA_USER 00000379
-CSEG PFA_DOUSER 00007058
-CSEG VE_RECURSE 0000037f
-CSEG XT_RECURSE 00000385
-CSEG PFA_RECURSE 00000386
-CSEG VE_IMMEDIATE 0000038a
-CSEG XT_IMMEDIATE 00000391
-CSEG PFA_IMMEDIATE 00000392
-CSEG XT_GET_CURRENT 00000433
-CSEG VE_BRACKETCHAR 0000039c
-CSEG XT_BRACKETCHAR 000003a1
-CSEG PFA_BRACKETCHAR 000003a2
-CSEG XT_CHAR 000078ea
-CSEG VE_ABORTQUOTE 000003a7
-CSEG XT_ABORTQUOTE 000003ac
-CSEG PFA_ABORTQUOTE 000003ad
-CSEG XT_SQUOTE 000074c1
-CSEG XT_QABORT 000003be
-CSEG VE_ABORT 000003b1
-CSEG XT_ABORT 000003b6
-CSEG PFA_ABORT 000003b7
-CSEG VE_QABORT 000003b9
-CSEG PFA_QABORT 000003bf
-CSEG QABO1 000003c4
-CSEG XT_ITYPE 000077a0
-CSEG VE_GET_STACK 000003c6
-CSEG XT_GET_STACK 000003cd
-CSEG PFA_N_FETCH_E2 000003e4
-CSEG PFA_N_FETCH_E1 000003da
-CSEG XT_I 000072ac
-CSEG XT_1MINUS 00007235
-CSEG XT_CELLS 00007558
-CSEG XT_OVER 000070cf
-CSEG VE_SET_STACK 000003e7
-CSEG XT_SET_STACK 000003ee
-CSEG PFA_SET_STACK 000003ef
-CSEG XT_ZEROLESS 00007121
-CSEG PFA_SET_STACK0 000003f6
-CSEG PFA_SET_STACK2 00000403
-CSEG PFA_SET_STACK1 000003fe
-CSEG XT_TUCK 00007576
-CSEG VE_MAPSTACK 00000405
-CSEG XT_MAPSTACK 0000040c
-CSEG PFA_MAPSTACK 0000040d
-CSEG XT_BOUNDS 00007d5e
-CSEG PFA_MAPSTACK3 00000428
-CSEG PFA_MAPSTACK1 00000417
-CSEG XT_R_FETCH 00007108
-CSEG XT_EXECUTE 0000702a
-CSEG PFA_MAPSTACK2 00000424
-CSEG VE_GET_CURRENT 0000042b
-CSEG PFA_GET_CURRENT 00000434
-ESEG CFG_CURRENT 0000004a
-CSEG VE_GET_ORDER 00000438
-CSEG XT_GET_ORDER 0000043f
-CSEG PFA_GET_ORDER 00000440
-ESEG CFG_ORDERLISTLEN 0000004e
-CSEG VE_CFG_ORDER 00000444
-CSEG XT_CFG_ORDER 0000044b
-CSEG PFA_CFG_ORDER 0000044c
-CSEG VE_COMPARE 0000044d
-CSEG XT_COMPARE 00000453
-CSEG PFA_COMPARE 00000454
-CSEG PFA_COMPARE_LOOP 00000460
-CSEG PFA_COMPARE_NOTEQUAL 0000046e
-CSEG PFA_COMPARE_ENDREACHED2 00000469
-CSEG PFA_COMPARE_ENDREACHED 0000046a
-CSEG PFA_COMPARE_CHECKLASTCHAR 0000046e
-CSEG PFA_COMPARE_DONE 00000470
-CSEG VE_NFA2LFA 00000475
-CSEG XT_NFA2LFA 0000047b
-CSEG PFA_NFA2LFA 0000047c
-CSEG XT_NAME2STRING 00007c72
-CSEG XT_2SLASH 00007204
-CSEG VE_DOTS 00000481
-CSEG XT_DOTS 00000484
-CSEG PFA_DOTS 00000485
-CSEG XT_DEPTH 00007aa1
-CSEG XT_UDOT 00007448
-CSEG XT_SPACE 000077e2
-CSEG PFA_DOTS2 00000493
-CSEG PFA_DOTS1 0000048e
-CSEG XT_PICK 000074af
-CSEG VE_SPIRW 00000494
-CSEG XT_SPIRW 00000499
-CSEG PFA_SPIRW 0000049a
-CSEG do_spirw 0000049e
-CSEG do_spirw1 0000049f
-CSEG VE_N_SPIR 000004a7
-CSEG XT_N_SPIR 000004ac
-CSEG PFA_N_SPIR 000004ad
-CSEG PFA_N_SPIR_LOOP 000004b2
-CSEG PFA_N_SPIR_LOOP1 000004b3
-CSEG VE_N_SPIW 000004be
-CSEG XT_N_SPIW 000004c3
-CSEG PFA_N_SPIW 000004c4
-CSEG PFA_N_SPIW_LOOP 000004c9
-CSEG PFA_N_SPIW_LOOP1 000004cb
-CSEG VE_APPLTURNKEY 000004d5
-CSEG XT_APPLTURNKEY 000004dd
-CSEG PFA_APPLTURNKEY 000004de
-CSEG XT_INTON 00007479
-CSEG XT_DOT_VER 00007b64
-CSEG XT_F_CPU 00007540
-CSEG XT_UMSLASHMOD 000071c2
-CSEG XT_DECIMAL 000075dd
-CSEG XT_DOT 00007722
-CSEG VE_SET_CURRENT 000004ef
-CSEG XT_SET_CURRENT 000004f7
-CSEG PFA_SET_CURRENT 000004f8
-CSEG VE_WORDLIST 000004fc
-CSEG XT_WORDLIST 00000502
-CSEG PFA_WORDLIST 00000503
-CSEG XT_EHERE 000075b7
-CSEG PFA_EHERE 000075b8
-CSEG VE_FORTHWORDLIST 0000050c
-CSEG XT_FORTHWORDLIST 00000515
-CSEG PFA_FORTHWORDLIST 00000516
-ESEG CFG_FORTHWORDLIST 0000004c
-CSEG VE_SET_ORDER 00000517
-CSEG XT_SET_ORDER 0000051e
-CSEG PFA_SET_ORDER 0000051f
-CSEG VE_SET_RECOGNIZERS 00000523
-CSEG XT_SET_RECOGNIZERS 0000052d
-CSEG PFA_SET_RECOGNIZERS 0000052e
-ESEG CFG_RECOGNIZERLISTLEN 00000060
-CSEG VE_GET_RECOGNIZERS 00000532
-CSEG XT_GET_RECOGNIZERS 0000053c
-CSEG PFA_GET_RECOGNIZERS 0000053d
-CSEG VE_CODE 00000541
-CSEG XT_CODE 00000545
-CSEG PFA_CODE 00000546
-CSEG VE_ENDCODE 0000054c
-CSEG XT_ENDCODE 00000552
-CSEG PFA_ENDCODE 00000553
-CSEG VE_MARKER 00000558
-CSEG XT_MARKER 0000055e
-CSEG PFA_MARKER 0000055f
-ESEG EE_MARKER 0000006c
-CSEG VE_POSTPONE 00000562
-CSEG XT_POSTPONE 00000568
-CSEG PFA_POSTPONE 00000569
-CSEG XT_FORTHRECOGNIZER 00007acc
-CSEG XT_RECOGNIZE 00007ad7
-CSEG VE_2R_FETCH 00000577
-CSEG XT_2R_FETCH 0000057b
-CSEG PFA_2R_FETCH 0000057c
-SET DPSTART 0000058b
-CSEG DO_INTERRUPT 00007014
-CSEG DO_EXECUTE 0000700d
-CSEG XT_ISREXEC 000074a2
-CSEG VE_EXIT 0000701c
-CSEG PFA_EXIT 00007021
-CSEG VE_EXECUTE 00007024
-CSEG PFA_EXECUTE 0000702b
-CSEG PFA_DOBRANCH 00007030
-CSEG PFA_DOCONDBRANCH 00007037
-CSEG PFA_DOLITERAL 0000703e
-CSEG XT_DOVARIABLE 00007047
-CSEG XT_DOCONSTANT 00007051
-CSEG XT_DOUSER 00007057
-CSEG VE_DOVALUE 00007063
-CSEG XT_DOVALUE 00007069
-CSEG PFA_DOVALUE 0000706a
-CSEG VE_FETCH 00007076
-CSEG PFA_FETCH 0000707a
-CSEG PFA_FETCHRAM 0000707a
-CSEG VE_STORE 0000707e
-CSEG PFA_STORE 00007082
-CSEG PFA_STORERAM 00007082
-CSEG VE_CSTORE 0000708a
-CSEG PFA_CSTORE 0000708e
-CSEG VE_CFETCH 00007095
-CSEG PFA_CFETCH 00007099
-CSEG VE_FETCHU 0000709d
-CSEG XT_FETCHU 000070a0
-CSEG PFA_FETCHU 000070a1
-CSEG XT_UP_FETCH 00007302
-CSEG VE_STOREU 000070a5
-CSEG XT_STOREU 000070a8
-CSEG PFA_STOREU 000070a9
-CSEG VE_DUP 000070ad
-CSEG PFA_DUP 000070b2
-CSEG VE_QDUP 000070b5
-CSEG PFA_QDUP 000070ba
-CSEG PFA_QDUP1 000070bf
-CSEG VE_SWAP 000070c0
-CSEG PFA_SWAP 000070c5
-CSEG VE_OVER 000070cb
-CSEG PFA_OVER 000070d0
-CSEG VE_DROP 000070d5
-CSEG PFA_DROP 000070da
-CSEG VE_ROT 000070dd
-CSEG PFA_ROT 000070e2
-CSEG VE_NIP 000070ec
-CSEG PFA_NIP 000070f1
-CSEG VE_R_FROM 000070f3
-CSEG PFA_R_FROM 000070f7
-CSEG VE_TO_R 000070fc
-CSEG PFA_TO_R 00007100
-CSEG VE_R_FETCH 00007105
-CSEG PFA_R_FETCH 00007109
-CSEG VE_NOTEQUAL 00007110
-CSEG PFA_NOTEQUAL 00007114
-CSEG VE_ZEROEQUAL 00007117
-CSEG PFA_ZEROEQUAL 0000711b
-CSEG PFA_ZERO1 00007157
-CSEG PFA_TRUE1 0000714e
-CSEG VE_ZEROLESS 0000711e
-CSEG PFA_ZEROLESS 00007122
-CSEG VE_GREATERZERO 00007125
-CSEG PFA_GREATERZERO 00007129
-CSEG VE_DGREATERZERO 0000712e
-CSEG XT_DGREATERZERO 00007132
-CSEG PFA_DGREATERZERO 00007133
-CSEG VE_DXT_ZEROLESS 0000713c
-CSEG XT_DXT_ZEROLESS 00007140
-CSEG PFA_DXT_ZEROLESS 00007141
-CSEG VE_TRUE 00007147
-CSEG PFA_TRUE 0000714c
-CSEG VE_ZERO 00007151
-CSEG PFA_ZERO 00007155
-CSEG VE_ULESS 00007159
-CSEG PFA_ULESS 0000715d
-CSEG VE_UGREATER 00007164
-CSEG PFA_UGREATER 00007168
-CSEG VE_LESS 0000716b
-CSEG XT_LESS 0000716e
-CSEG PFA_LESS 0000716f
-CSEG PFA_LESSDONE 00007173
-CSEG VE_GREATER 00007175
-CSEG XT_GREATER 00007178
-CSEG PFA_GREATER 00007179
-CSEG PFA_GREATERDONE 0000717d
-CSEG VE_LOG2 00007180
-CSEG XT_LOG2 00007184
-CSEG PFA_LOG2 00007185
-CSEG PFA_LOG2_1 00007188
-CSEG PFA_LOG2_2 0000718e
-CSEG VE_MINUS 00007190
-CSEG XT_MINUS 00007193
-CSEG PFA_MINUS 00007194
-CSEG VE_PLUS 0000719a
-CSEG PFA_PLUS 0000719e
-CSEG VE_MSTAR 000071a3
-CSEG XT_MSTAR 000071a6
-CSEG PFA_MSTAR 000071a7
-CSEG VE_UMSLASHMOD 000071bd
-CSEG PFA_UMSLASHMOD 000071c3
-CSEG PFA_UMSLASHMODmod 000071c8
-CSEG PFA_UMSLASHMODmod_loop 000071c9
-CSEG PFA_UMSLASHMODmod_loop_control 000071d6
-CSEG PFA_UMSLASHMODmod_subtract 000071d3
-CSEG PFA_UMSLASHMODmod_done 000071d8
-CSEG VE_UMSTAR 000071dc
-CSEG PFA_UMSTAR 000071e1
-CSEG VE_INVERT 000071f8
-CSEG PFA_INVERT 000071fe
-CSEG VE_2SLASH 00007201
-CSEG PFA_2SLASH 00007205
-CSEG VE_2STAR 00007208
-CSEG XT_2STAR 0000720b
-CSEG PFA_2STAR 0000720c
-CSEG VE_AND 0000720f
-CSEG PFA_AND 00007214
-CSEG VE_OR 00007219
-CSEG PFA_OR 0000721d
-CSEG VE_XOR 00007222
-CSEG XT_XOR 00007226
-CSEG PFA_XOR 00007227
-CSEG VE_1PLUS 0000722c
-CSEG PFA_1PLUS 00007230
-CSEG VE_1MINUS 00007232
-CSEG PFA_1MINUS 00007236
-CSEG VE_QNEGATE 00007238
-CSEG XT_QNEGATE 0000723e
-CSEG PFA_QNEGATE 0000723f
-CSEG QNEG1 00007243
-CSEG XT_NEGATE 0000763f
-CSEG VE_LSHIFT 00007244
-CSEG XT_LSHIFT 00007249
-CSEG PFA_LSHIFT 0000724a
-CSEG PFA_LSHIFT1 0000724d
-CSEG PFA_LSHIFT2 00007252
-CSEG VE_RSHIFT 00007253
-CSEG XT_RSHIFT 00007258
-CSEG PFA_RSHIFT 00007259
-CSEG PFA_RSHIFT1 0000725c
-CSEG PFA_RSHIFT2 00007261
-CSEG VE_PLUSSTORE 00007262
-CSEG PFA_PLUSSTORE 00007266
-CSEG VE_RP_FETCH 00007272
-CSEG XT_RP_FETCH 00007276
-CSEG PFA_RP_FETCH 00007277
-CSEG VE_RP_STORE 0000727c
-CSEG XT_RP_STORE 00007280
-CSEG PFA_RP_STORE 00007281
-CSEG VE_SP_FETCH 00007289
-CSEG XT_SP_FETCH 0000728d
-CSEG PFA_SP_FETCH 0000728e
-CSEG VE_SP_STORE 00007292
-CSEG XT_SP_STORE 00007296
-CSEG PFA_SP_STORE 00007297
-CSEG PFA_DODO 0000729c
-CSEG PFA_DODO1 0000729e
-CSEG VE_I 000072a9
-CSEG PFA_I 000072ad
-CSEG PFA_DOPLUSLOOP 000072bb
-CSEG PFA_DOPLUSLOOP_LEAVE 000072c5
-CSEG PFA_DOPLUSLOOP_NEXT 000072c2
-CSEG PFA_DOLOOP 000072ca
-CSEG VE_UNLOOP 000072cf
-CSEG PFA_UNLOOP 000072d5
-CSEG VE_CMOVE_G 000072da
-CSEG XT_CMOVE_G 000072df
-CSEG PFA_CMOVE_G 000072e0
-CSEG PFA_CMOVE_G1 000072f1
-CSEG PFA_CMOVE_G2 000072ed
-CSEG VE_BYTESWAP 000072f6
-CSEG PFA_BYTESWAP 000072fa
-CSEG VE_UP_FETCH 000072fe
-CSEG PFA_UP_FETCH 00007303
-CSEG VE_UP_STORE 00007307
-CSEG XT_UP_STORE 0000730b
-CSEG PFA_UP_STORE 0000730c
-CSEG VE_1MS 00007310
-CSEG XT_1MS 00007314
-CSEG PFA_1MS 00007315
-CSEG VE_2TO_R 0000731a
-CSEG XT_2TO_R 0000731e
-CSEG PFA_2TO_R 0000731f
-CSEG VE_2R_FROM 00007329
-CSEG XT_2R_FROM 0000732d
-CSEG PFA_2R_FROM 0000732e
-CSEG VE_STOREE 00007338
-CSEG PFA_STOREE 0000733c
-CSEG PFA_STOREE0 0000733c
-CSEG PFA_FETCHE2 0000736a
-CSEG PFA_STOREE3 00007346
-CSEG PFA_STOREE1 00007351
-CSEG PFA_STOREE4 0000734d
-CSEG PFA_STOREE2 00007353
-CSEG VE_FETCHE 0000735c
-CSEG PFA_FETCHE 00007360
-CSEG PFA_FETCHE1 00007360
-CSEG VE_STOREI 00007370
-CSEG PFA_STOREI 00007374
-ESEG EE_STOREI 0000006a
-CSEG VE_DO_STOREI_NRWW 00007377
-CSEG XT_DO_STOREI 0000737e
-CSEG PFA_DO_STOREI_NRWW 0000737f
-CSEG DO_STOREI_atmega 00007393
-CSEG pageload 000073a4
-CSEG DO_STOREI_writepage 0000739d
-CSEG dospm 000073bd
-EQU pagemask ffffff80
-CSEG pageload_loop 000073aa
-CSEG pageload_newdata 000073b5
-CSEG pageload_cont 000073b7
-CSEG pageload_done 000073bc
-CSEG dospm_wait_ee 000073bd
-CSEG dospm_wait_spm 000073bf
-CSEG VE_FETCHI 000073c8
-CSEG PFA_FETCHI 000073cc
-CSEG VE_N_TO_R 000073d2
-CSEG XT_N_TO_R 000073d6
-CSEG PFA_N_TO_R 000073d7
-CSEG PFA_N_TO_R1 000073d9
-CSEG VE_N_R_FROM 000073e4
-CSEG XT_N_R_FROM 000073e8
-CSEG PFA_N_R_FROM 000073e9
-CSEG PFA_N_R_FROM1 000073ee
-CSEG VE_D2STAR 000073f6
-CSEG XT_D2STAR 000073fa
-CSEG PFA_D2STAR 000073fb
-CSEG VE_D2SLASH 00007404
-CSEG XT_D2SLASH 00007408
-CSEG PFA_D2SLASH 00007409
-CSEG VE_DPLUS 00007412
-CSEG PFA_DPLUS 00007416
-CSEG VE_DMINUS 00007423
-CSEG XT_DMINUS 00007426
-CSEG PFA_DMINUS 00007427
-CSEG VE_DINVERT 00007435
-CSEG XT_DINVERT 0000743b
-CSEG PFA_DINVERT 0000743c
-CSEG VE_UDOT 00007445
-CSEG PFA_UDOT 00007449
-CSEG XT_UDDOT 0000772a
-CSEG VE_UDOTR 0000744c
-CSEG XT_UDOTR 00007450
-CSEG PFA_UDOTR 00007451
-CSEG XT_UDDOTR 00007733
-CSEG VE_SHOWWORDLIST 00007455
-CSEG XT_SHOWWORDLIST 0000745e
-CSEG PFA_SHOWWORDLIST 0000745f
-CSEG XT_SHOWWORD 00007464
-CSEG XT_TRAVERSEWORDLIST 00007c57
-CSEG PFA_SHOWWORD 00007465
-CSEG VE_WORDS 0000746a
-CSEG XT_WORDS 0000746f
-CSEG PFA_WORDS 00007470
-CSEG VE_INTON 00007475
-CSEG PFA_INTON 0000747a
-CSEG VE_INTOFF 0000747c
-CSEG XT_INTOFF 00007480
-CSEG PFA_INTOFF 00007481
-CSEG VE_INTSTORE 00007483
-CSEG PFA_INTSTORE 00007488
-CSEG VE_INTFETCH 0000748d
-CSEG XT_INTFETCH 00007491
-CSEG PFA_INTFETCH 00007492
-CSEG VE_INTTRAP 00007497
-CSEG XT_INTTRAP 0000749d
-CSEG PFA_INTTRAP 0000749e
-CSEG PFA_ISREXEC 000074a3
-CSEG XT_ISREND 000074a7
-CSEG PFA_ISREND 000074a8
-CSEG PFA_ISREND1 000074aa
-CSEG VE_PICK 000074ab
-CSEG PFA_PICK 000074b0
-CSEG VE_DOTSTRING 000074b6
-CSEG XT_DOTSTRING 000074b9
-CSEG PFA_DOTSTRING 000074ba
-CSEG VE_SQUOTE 000074be
-CSEG PFA_SQUOTE 000074c2
-CSEG PFA_SQUOTE1 000074ca
-CSEG VE_FILL 000074cb
-CSEG PFA_FILL 000074d0
-CSEG PFA_FILL2 000074dc
-CSEG PFA_FILL1 000074d7
-CSEG VE_ENVIRONMENT 000074de
-CSEG XT_ENVIRONMENT 000074e6
-CSEG PFA_ENVIRONMENT 000074e7
-ESEG CFG_ENVIRONMENT 00000048
-CSEG VE_ENVWORDLISTS 000074e8
-CSEG XT_ENVWORDLISTS 000074ef
-CSEG PFA_ENVWORDLISTS 000074f0
-CSEG VE_ENVSLASHPAD 000074f3
-CSEG XT_ENVSLASHPAD 000074f7
-CSEG PFA_ENVSLASHPAD 000074f8
-CSEG XT_PAD 00007584
-CSEG VE_ENVSLASHHOLD 000074fc
-CSEG XT_ENVSLASHHOLD 00007501
-CSEG PFA_ENVSLASHHOLD 00007502
-CSEG VE_ENV_FORTHNAME 00007506
-CSEG XT_ENV_FORTHNAME 0000750d
-CSEG PFA_EN_FORTHNAME 0000750e
-CSEG VE_ENV_FORTHVERSION 00007515
-CSEG XT_ENV_FORTHVERSION 0000751b
-CSEG PFA_EN_FORTHVERSION 0000751c
-CSEG VE_ENV_CPU 0000751f
-CSEG XT_ENV_CPU 00007523
-CSEG PFA_EN_CPU 00007524
-CSEG XT_ICOUNT 000077cc
-CSEG VE_ENV_MCUINFO 00007528
-CSEG XT_ENV_MCUINFO 0000752e
-CSEG PFA_EN_MCUINFO 0000752f
-CSEG VE_ENVUSERSIZE 00007532
-CSEG XT_ENVUSERSIZE 00007537
-CSEG PFA_ENVUSERSIZE 00007538
-CSEG VE_F_CPU 0000753b
-CSEG PFA_F_CPU 00007541
-CSEG VE_STATE 00007546
-CSEG PFA_STATE 0000754c
-DSEG ram_state 00000136
-CSEG VE_BASE 0000754d
-CSEG XT_BASE 00007551
-CSEG PFA_BASE 00007552
-CSEG VE_CELLS 00007553
-CSEG VE_CELLPLUS 00007559
-CSEG PFA_CELLPLUS 0000755f
-CSEG VE_2DUP 00007561
-CSEG PFA_2DUP 00007566
-CSEG VE_2DROP 00007569
-CSEG PFA_2DROP 0000756f
-CSEG VE_TUCK 00007572
-CSEG PFA_TUCK 00007577
-CSEG VE_TO_IN 0000757a
-CSEG PFA_TO_IN 0000757f
-CSEG VE_PAD 00007580
-CSEG PFA_PAD 00007585
-CSEG VE_EMIT 0000758a
-CSEG XT_EMIT 0000758e
-CSEG PFA_EMIT 0000758f
-CSEG XT_UDEFERFETCH 00007bdc
-CSEG XT_UDEFERSTORE 00007be8
-CSEG VE_EMITQ 00007592
-CSEG XT_EMITQ 00007597
-CSEG PFA_EMITQ 00007598
-CSEG VE_KEY 0000759b
-CSEG XT_KEY 0000759f
-CSEG PFA_KEY 000075a0
-CSEG VE_KEYQ 000075a3
-CSEG XT_KEYQ 000075a7
-CSEG PFA_KEYQ 000075a8
-CSEG VE_DP 000075ab
-ESEG CFG_DP 0000003a
-CSEG VE_EHERE 000075b2
-ESEG EE_EHERE 0000003e
-CSEG VE_HERE 000075bb
-CSEG PFA_HERE 000075c0
-ESEG EE_HERE 0000003c
-CSEG VE_ALLOT 000075c3
-CSEG PFA_ALLOT 000075c9
-CSEG VE_BIN 000075ce
-CSEG XT_BIN 000075d2
-CSEG PFA_BIN 000075d3
-CSEG VE_DECIMAL 000075d7
-CSEG PFA_DECIMAL 000075de
-CSEG VE_HEX 000075e3
-CSEG XT_HEX 000075e7
-CSEG PFA_HEX 000075e8
-CSEG VE_BL 000075ed
-CSEG XT_BL 000075f0
-CSEG PFA_BL 000075f1
-CSEG VE_TURNKEY 000075f2
-CSEG XT_TURNKEY 000075f8
-CSEG PFA_TURNKEY 000075f9
-ESEG CFG_TURNKEY 00000046
-CSEG VE_SLASHMOD 000075fc
-CSEG XT_SLASHMOD 00007600
-CSEG PFA_SLASHMOD 00007601
-CSEG PFA_SLASHMOD_1 0000760c
-CSEG PFA_SLASHMOD_2 00007612
-CSEG PFA_SLASHMOD_3 00007615
-CSEG PFA_SLASHMOD_5 00007620
-CSEG PFA_SLASHMOD_4 0000761f
-CSEG PFA_SLASHMODmod_done 0000762b
-CSEG PFA_SLASHMOD_6 00007629
-CSEG VE_USLASHMOD 0000762f
-CSEG XT_USLASHMOD 00007634
-CSEG PFA_USLASHMOD 00007635
-CSEG VE_NEGATE 0000763a
-CSEG PFA_NEGATE 00007640
-CSEG VE_SLASH 00007643
-CSEG XT_SLASH 00007646
-CSEG PFA_SLASH 00007647
-CSEG VE_MOD 0000764a
-CSEG XT_MOD 0000764e
-CSEG PFA_MOD 0000764f
-CSEG VE_ABS 00007652
-CSEG XT_ABS 00007656
-CSEG PFA_ABS 00007657
-CSEG VE_MIN 0000765a
-CSEG XT_MIN 0000765e
-CSEG PFA_MIN 0000765f
-CSEG PFA_MIN1 00007664
-CSEG VE_MAX 00007666
-CSEG XT_MAX 0000766a
-CSEG PFA_MAX 0000766b
-CSEG PFA_MAX1 00007670
-CSEG VE_WITHIN 00007672
-CSEG XT_WITHIN 00007677
-CSEG PFA_WITHIN 00007678
-CSEG VE_TOUPPER 0000767f
-CSEG XT_TOUPPER 00007685
-CSEG PFA_TOUPPER 00007686
-CSEG PFA_TOUPPER0 00007691
-CSEG VE_TOLOWER 00007692
-CSEG XT_TOLOWER 00007698
-CSEG PFA_TOLOWER 00007699
-CSEG PFA_TOLOWER0 000076a4
-CSEG VE_HLD 000076a5
-CSEG XT_HLD 000076a9
-CSEG PFA_HLD 000076aa
-DSEG ram_hld 00000138
-CSEG VE_HOLD 000076ab
-CSEG XT_HOLD 000076af
-CSEG PFA_HOLD 000076b0
-CSEG VE_L_SHARP 000076bb
-CSEG XT_L_SHARP 000076be
-CSEG PFA_L_SHARP 000076bf
-CSEG VE_SHARP 000076c3
-CSEG XT_SHARP 000076c6
-CSEG PFA_SHARP 000076c7
-CSEG XT_UDSLASHMOD 00007743
-CSEG PFA_SHARP1 000076d4
-CSEG VE_SHARP_S 000076d9
-CSEG XT_SHARP_S 000076dc
-CSEG PFA_SHARP_S 000076dd
-CSEG NUMS1 000076dd
-CSEG VE_SHARP_G 000076e4
-CSEG XT_SHARP_G 000076e7
-CSEG PFA_SHARP_G 000076e8
-CSEG VE_SIGN 000076ef
-CSEG XT_SIGN 000076f3
-CSEG PFA_SIGN 000076f4
-CSEG PFA_SIGN1 000076fa
-CSEG VE_DDOTR 000076fb
-CSEG XT_DDOTR 000076ff
-CSEG PFA_DDOTR 00007700
-CSEG XT_DABS 00007cd4
-CSEG XT_SPACES 000077eb
-CSEG XT_TYPE 000077fb
-CSEG VE_DOTR 0000770e
-CSEG XT_DOTR 00007711
-CSEG PFA_DOTR 00007712
-CSEG VE_DDOT 00007717
-CSEG XT_DDOT 0000771a
-CSEG PFA_DDOT 0000771b
-CSEG VE_DOT 0000771f
-CSEG PFA_DOT 00007723
-CSEG VE_UDDOT 00007726
-CSEG PFA_UDDOT 0000772b
-CSEG VE_UDDOTR 0000772f
-CSEG PFA_UDDOTR 00007734
-CSEG VE_UDSLASHMOD 0000773e
-CSEG PFA_UDSLASHMOD 00007744
-CSEG VE_DIGITQ 0000774e
-CSEG XT_DIGITQ 00007753
-CSEG PFA_DIGITQ 00007754
-CSEG PFA_DOSLITERAL 0000776e
-CSEG VE_SCOMMA 00007778
-CSEG PFA_SCOMMA 0000777c
-CSEG PFA_DOSCOMMA 00007780
-CSEG PFA_SCOMMA2 00007792
-CSEG PFA_SCOMMA1 0000778c
-CSEG PFA_SCOMMA3 00007799
-CSEG VE_ITYPE 0000779b
-CSEG PFA_ITYPE 000077a1
-CSEG PFA_ITYPE2 000077b4
-CSEG PFA_ITYPE1 000077ac
-CSEG XT_LOWEMIT 000077c1
-CSEG XT_HIEMIT 000077bd
-CSEG PFA_ITYPE3 000077bb
-CSEG PFA_HIEMIT 000077be
-CSEG PFA_LOWEMIT 000077c2
-CSEG VE_ICOUNT 000077c7
-CSEG PFA_ICOUNT 000077cd
-CSEG VE_CR 000077d2
-CSEG XT_CR 000077d5
-CSEG PFA_CR 000077d6
-CSEG VE_SPACE 000077dd
-CSEG PFA_SPACE 000077e3
-CSEG VE_SPACES 000077e6
-CSEG PFA_SPACES 000077ec
-CSEG SPCS1 000077ee
-CSEG SPCS2 000077f5
-CSEG VE_TYPE 000077f7
-CSEG PFA_TYPE 000077fc
-CSEG PFA_TYPE2 00007806
-CSEG PFA_TYPE1 00007801
-CSEG VE_TICK 00007807
-CSEG PFA_TICK 0000780b
-CSEG XT_DT_NULL 00007b4a
-CSEG XT_NOOP 00007b7f
-CSEG PFA_TICK1 0000781c
-CSEG VE_HANDLER 0000781e
-CSEG XT_HANDLER 00007824
-CSEG PFA_HANDLER 00007825
-CSEG VE_CATCH 00007826
-CSEG XT_CATCH 0000782b
-CSEG PFA_CATCH 0000782c
-CSEG VE_THROW 0000783c
-CSEG PFA_THROW 00007842
-CSEG PFA_THROW1 00007848
-CSEG VE_CSKIP 00007855
-CSEG XT_CSKIP 0000785a
-CSEG PFA_CSKIP 0000785b
-CSEG PFA_CSKIP1 0000785c
-CSEG PFA_CSKIP2 00007869
-CSEG XT_SLASHSTRING 000079a5
-CSEG VE_CSCAN 0000786c
-CSEG XT_CSCAN 00007871
-CSEG PFA_CSCAN 00007872
-CSEG PFA_CSCAN1 00007874
-CSEG PFA_CSCAN2 00007886
-CSEG VE_ACCEPT 0000788c
-CSEG XT_ACCEPT 00007891
-CSEG PFA_ACCEPT 00007892
-CSEG ACC1 00007896
-CSEG XT_CRLFQ 000078d2
-CSEG ACC5 000078c4
-CSEG ACC3 000078b4
-CSEG ACC6 000078b2
-CSEG XT_BS 000078ca
-CSEG ACC4 000078c2
-CSEG PFA_ACCEPT6 000078bb
-CSEG VE_REFILL 000078dd
-CSEG XT_REFILL 000078e2
-CSEG PFA_REFILL 000078e3
-CSEG VE_CHAR 000078e6
-CSEG PFA_CHAR 000078eb
-CSEG VE_NUMBER 000078ef
-CSEG XT_NUMBER 000078f4
-CSEG PFA_NUMBER 000078f5
-CSEG XT_QSIGN 00007938
-CSEG XT_SET_BASE 0000794b
-CSEG PFA_NUMBER0 0000790b
-CSEG XT_TO_NUMBER 00007969
-CSEG PFA_NUMBER1 0000792d
-CSEG PFA_NUMBER2 00007924
-CSEG PFA_NUMBER6 00007925
-CSEG PFA_NUMBER3 00007921
-CSEG XT_DNEGATE 00007ce1
-CSEG PFA_NUMBER5 00007933
-CSEG PFA_NUMBER4 00007932
-CSEG PFA_QSIGN 00007939
-CSEG PFA_NUMBERSIGN_DONE 00007944
-CSEG XT_BASES 00007946
-CSEG PFA_SET_BASE 0000794c
-CSEG SET_BASE1 00007961
-CSEG SET_BASE2 00007962
-CSEG VE_TO_NUMBER 00007963
-CSEG TONUM1 0000796a
-CSEG TONUM3 00007981
-CSEG TONUM2 00007975
-CSEG XT_2SWAP 00007d05
-CSEG VE_PARSE 00007982
-CSEG PFA_PARSE 00007988
-CSEG VE_SOURCE 00007996
-CSEG PFA_SOURCE 0000799c
-CSEG VE_SLASHSTRING 0000799f
-CSEG PFA_SLASHSTRING 000079a6
-CSEG VE_PARSENAME 000079ad
-CSEG PFA_PARSENAME 000079b5
-CSEG XT_SKIPSCANCHAR 000079b8
-CSEG PFA_SKIPSCANCHAR 000079b9
-CSEG VE_FINDXT 000079ca
-CSEG XT_FINDXT 000079d0
-CSEG PFA_FINDXT 000079d1
-CSEG XT_FINDXTA 000079dc
-CSEG PFA_FINDXT1 000079db
-CSEG PFA_FINDXTA 000079dd
-CSEG XT_SEARCH_WORDLIST 00007c25
-CSEG PFA_FINDXTA1 000079e9
-CSEG XT_DEFAULT_PROMPTOK 000079ea
-CSEG PFA_DEFAULT_PROMPTOK 000079eb
-CSEG VE_PROMPTOK 000079f1
-CSEG XT_PROMPTOK 000079f5
-CSEG PFA_PROMPTOK 000079f6
-CSEG XT_DEFAULT_PROMPTREADY 000079f9
-CSEG PFA_DEFAULT_PROMPTREADY 000079fa
-CSEG VE_PROMPTREADY 00007a00
-CSEG XT_PROMPTREADY 00007a05
-CSEG PFA_PROMPTREADY 00007a06
-CSEG XT_DEFAULT_PROMPTERROR 00007a09
-CSEG PFA_DEFAULT_PROMPTERROR 00007a0a
-CSEG VE_PROMPTERROR 00007a1b
-CSEG XT_PROMPTERROR 00007a20
-CSEG PFA_PROMPTERROR 00007a21
-CSEG VE_QUIT 00007a24
-CSEG XT_QUIT 00007a28
-CSEG PFA_QUIT 00007a29
-CSEG XT_SP0 00007a89
-CSEG XT_RP0 00007a96
-CSEG PFA_QUIT2 00007a31
-CSEG PFA_QUIT4 00007a37
-CSEG PFA_QUIT3 00007a49
-CSEG XT_INTERPRET 00007aaf
-CSEG PFA_QUIT5 00007a47
-CSEG VE_PAUSE 00007a4c
-CSEG PFA_PAUSE 00007a52
-DSEG ram_pause 0000013a
-CSEG XT_RDEFERFETCH 00007bc8
-CSEG XT_RDEFERSTORE 00007bd2
-CSEG VE_COLD 00007a55
-CSEG clearloop 00007a61
-DSEG ram_user1 0000013c
-CSEG PFA_WARM 00007a7c
-CSEG VE_WARM 00007a77
-CSEG XT_WARM 00007a7b
-CSEG XT_INIT_RAM 00007d50
-CSEG XT_DEFERSTORE 00007bf3
-CSEG VE_SP0 00007a85
-CSEG PFA_SP0 00007a8a
-CSEG VE_SP 00007a8d
-CSEG XT_SP 00007a90
-CSEG PFA_SP 00007a91
-CSEG VE_RP0 00007a92
-CSEG PFA_RP0 00007a97
-CSEG XT_DORP0 00007a9a
-CSEG PFA_DORP0 00007a9b
-CSEG VE_DEPTH 00007a9c
-CSEG PFA_DEPTH 00007aa2
-CSEG VE_INTERPRET 00007aa8
-CSEG PFA_INTERPRET 00007ab0
-CSEG PFA_INTERPRET2 00007ac0
-CSEG PFA_INTERPRET1 00007abb
-CSEG VE_FORTHRECOGNIZER 00007ac2
-CSEG PFA_FORTHRECOGNIZER 00007acd
-ESEG CFG_FORTHRECOGNIZER 00000042
-CSEG VE_RECOGNIZE 00007ad0
-CSEG PFA_RECOGNIZE 00007ad8
-CSEG XT_RECOGNIZE_A 00007ae2
-CSEG PFA_RECOGNIZE1 00007ae1
-CSEG PFA_RECOGNIZE_A 00007ae3
-CSEG PFA_RECOGNIZE_A1 00007af3
-CSEG VE_DT_NUM 00007af7
-CSEG XT_DT_NUM 00007afc
-CSEG PFA_DT_NUM 00007afd
-CSEG VE_DT_DNUM 00007b00
-CSEG XT_DT_DNUM 00007b06
-CSEG PFA_DT_DNUM 00007b07
-CSEG XT_2LITERAL 00007d77
-CSEG VE_REC_NUM 00007b0a
-CSEG XT_REC_NUM 00007b10
-CSEG PFA_REC_NUM 00007b11
-CSEG PFA_REC_NONUMBER 00007b1c
-CSEG PFA_REC_INTNUM2 00007b1a
-CSEG VE_REC_FIND 00007b1e
-CSEG XT_REC_FIND 00007b24
-CSEG PFA_REC_FIND 00007b25
-CSEG PFA_REC_WORD_FOUND 00007b2d
-CSEG XT_DT_XT 00007b34
-CSEG VE_DT_XT 00007b2f
-CSEG PFA_DT_XT 00007b35
-CSEG XT_R_WORD_INTERPRET 00007b38
-CSEG XT_R_WORD_COMPILE 00007b3c
-CSEG PFA_R_WORD_INTERPRET 00007b39
-CSEG PFA_R_WORD_COMPILE 00007b3d
-CSEG PFA_R_WORD_COMPILE1 00007b42
-CSEG VE_DT_NULL 00007b44
-CSEG PFA_DT_NULL 00007b4b
-CSEG XT_FAIL 00007b4e
-CSEG PFA_FAIL 00007b4f
-CSEG VE_QSTACK 00007b52
-CSEG PFA_QSTACK 00007b58
-CSEG PFA_QSTACK1 00007b5f
-CSEG VE_DOT_VER 00007b60
-CSEG PFA_DOT_VER 00007b65
-CSEG VE_NOOP 00007b7b
-CSEG PFA_NOOP 00007b80
-CSEG VE_UNUSED 00007b81
-CSEG XT_UNUSED 00007b86
-CSEG PFA_UNUSED 00007b87
-CSEG VE_TO 00007b8b
-CSEG XT_TO 00007b8e
-CSEG PFA_TO 00007b8f
-CSEG XT_TO_BODY 00007d70
-CSEG PFA_TO1 00007b9f
-CSEG PFA_DOTO 00007b9a
-CSEG VE_ICELLPLUS 00007ba5
-CSEG PFA_ICELLPLUS 00007bac
-CSEG VE_EDEFERFETCH 00007bae
-CSEG PFA_EDEFERFETCH 00007bb5
-CSEG VE_EDEFERSTORE 00007bb8
-CSEG PFA_EDEFERSTORE 00007bbf
-CSEG VE_RDEFERFETCH 00007bc2
-CSEG PFA_RDEFERFETCH 00007bc9
-CSEG VE_RDEFERSTORE 00007bcc
-CSEG PFA_RDEFERSTORE 00007bd3
-CSEG VE_UDEFERFETCH 00007bd6
-CSEG PFA_UDEFERFETCH 00007bdd
-CSEG VE_UDEFERSTORE 00007be2
-CSEG PFA_UDEFERSTORE 00007be9
-CSEG VE_DEFERSTORE 00007bee
-CSEG PFA_DEFERSTORE 00007bf4
-CSEG VE_DEFERFETCH 00007bfb
-CSEG XT_DEFERFETCH 00007c00
-CSEG PFA_DEFERFETCH 00007c01
-CSEG VE_DODEFER 00007c07
-CSEG XT_DODEFER 00007c0d
-CSEG PFA_DODEFER 00007c0e
-CSEG VE_SEARCH_WORDLIST 00007c1b
-CSEG PFA_SEARCH_WORDLIST 00007c26
-CSEG XT_ISWORD 00007c3a
-CSEG PFA_SEARCH_WORDLIST1 00007c34
-CSEG PFA_ISWORD 00007c3b
-CSEG XT_ICOMPARE 00007c88
-CSEG PFA_ISWORD3 00007c48
-CSEG VE_TRAVERSEWORDLIST 00007c4c
-CSEG PFA_TRAVERSEWORDLIST 00007c58
-CSEG PFA_TRAVERSEWORDLIST1 00007c59
-CSEG PFA_TRAVERSEWORDLIST2 00007c68
-CSEG VE_NAME2STRING 00007c6a
-CSEG PFA_NAME2STRING 00007c73
-CSEG VE_NFA2CFA 00007c78
-CSEG PFA_NFA2CFA 00007c7f
-CSEG VE_ICOMPARE 00007c82
-CSEG PFA_ICOMPARE 00007c89
-CSEG PFA_ICOMPARE_SAMELEN 00007c93
-CSEG PFA_ICOMPARE_DONE 00007cb6
-CSEG PFA_ICOMPARE_LOOP 00007c99
-CSEG PFA_ICOMPARE_LASTCELL 00007ca7
-CSEG PFA_ICOMPARE_NEXTLOOP 00007cae
-CSEG VE_STAR 00007cb9
-CSEG XT_STAR 00007cbc
-CSEG PFA_STAR 00007cbd
-CSEG VE_J 00007cc0
-CSEG XT_J 00007cc3
-CSEG PFA_J 00007cc4
-CSEG VE_DABS 00007cd0
-CSEG PFA_DABS 00007cd5
-CSEG PFA_DABS1 00007cda
-CSEG VE_DNEGATE 00007cdb
-CSEG PFA_DNEGATE 00007ce2
-CSEG VE_CMOVE 00007ce7
-CSEG XT_CMOVE 00007cec
-CSEG PFA_CMOVE 00007ced
-CSEG PFA_CMOVE1 00007cfa
-CSEG PFA_CMOVE2 00007cf6
-CSEG VE_2SWAP 00007d00
-CSEG PFA_2SWAP 00007d06
-CSEG VE_REFILLTIB 00007d0b
-CSEG XT_REFILLTIB 00007d12
-CSEG PFA_REFILLTIB 00007d13
-CSEG XT_TIB 00007d2e
-CSEG XT_NUMBERTIB 00007d34
-CSEG VE_SOURCETIB 00007d1e
-CSEG XT_SOURCETIB 00007d25
-CSEG PFA_SOURCETIB 00007d26
-CSEG VE_TIB 00007d2a
-CSEG PFA_TIB 00007d2f
-DSEG ram_tib 00000168
-CSEG VE_NUMBERTIB 00007d30
-CSEG PFA_NUMBERTIB 00007d35
-DSEG ram_sharptib 000001c2
-CSEG VE_EE2RAM 00007d36
-CSEG XT_EE2RAM 00007d3b
-CSEG PFA_EE2RAM 00007d3c
-CSEG PFA_EE2RAM_1 00007d3e
-CSEG PFA_EE2RAM_2 00007d48
-CSEG VE_INIT_RAM 00007d4a
-CSEG PFA_INI_RAM 00007d51
-ESEG EE_INITUSER 0000006e
-CSEG VE_BOUNDS 00007d59
-CSEG PFA_BOUNDS 00007d5f
-CSEG VE_S2D 00007d63
-CSEG PFA_S2D 00007d68
-CSEG VE_TO_BODY 00007d6b
-CSEG VE_2LITERAL 00007d71
-CSEG PFA_2LITERAL 00007d78
-CSEG VE_EQUAL 00007d7c
-CSEG PFA_EQUAL 00007d80
-CSEG VE_ONE 00007d83
-CSEG PFA_ONE 00007d87
-CSEG VE_TWO 00007d88
-CSEG PFA_TWO 00007d8c
-CSEG VE_MINUSONE 00007d8d
-CSEG XT_MINUSONE 00007d90
-CSEG PFA_MINUSONE 00007d91
-SET flashlast 00007d92
-DSEG HERESTART 000001c4
-ESEG EHERESTART 00000092
-ESEG CFG_ORDERLIST 00000050
-ESEG CFG_RECOGNIZERLIST 00000062
-EQU UBRR_VAL 00000019
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/eval-pollin/p644-16.xml b/amforth-6.5/appl/eval-pollin/p644-16.xml
deleted file mode 100644
index 2fc587c..0000000
--- a/amforth-6.5/appl/eval-pollin/p644-16.xml
+++ /dev/null
@@ -1,27 +0,0 @@
-<project name="pollins-644-16" basedir="." default="Help">
-
- <target name="p644-16.asm">
- <copy tofile="p644-16.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="16000000"/>
- <filter token="USART" value="_0"/>
- </filterset>
- </copy>
- </target>
-
- <target name="p644-16.hex" depends="p644-16.asm" description="Hexfiles for p644-16">
- <avrasm2 projectname="p644-16" mcu="atmega644"/>
- <delete file="p644-16.asm"/>
- </target>
-
- <target name="p644-16" depends="p644-16.hex" description="Atmega644 @ 16 MHz">
- <echo>Uploading Hexfiles for p644 - 16</echo>
- <avrdude
- type="mysmartusb"
- mcu="atmega644"
- flashfile="p644-16.hex"
- eepromfile="p644-16.eep.hex"
- />
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/p8-12.xml b/amforth-6.5/appl/eval-pollin/p8-12.xml
deleted file mode 100644
index aae5de9..0000000
--- a/amforth-6.5/appl/eval-pollin/p8-12.xml
+++ /dev/null
@@ -1,25 +0,0 @@
-<project name="pollins-8-12" basedir="." default="Help">
-
- <target name="p8-12.asm">
- <copy tofile="p8-12.asm" file="pollin.asm" overwrite="true">
- <filterset>
- <filter token="F_CPU" value="12000000"/>
- <filter token="USART" value=""/>
- </filterset>
- </copy>
- </target>
- <target name="p8-12.hex" description="Hexfiles for p8-12" depends="p8-12.asm">
- <avrasm2 projectname="p8-12" mcu="atmega88"/>
-
- </target>
-
- <target name="p8-12" depends="p8-12.hex" description="Atmega8 @ 12 MHz">
- <echo>Uploading Hexfiles for p8-12</echo>
- <avrdude
- type="stk200"
- mcu="atmega88"
- flashfile="p8-12.hex"
- eepromfile="p8-12.eep.hex"
- />
- </target>
-</project>
diff --git a/amforth-6.5/appl/eval-pollin/pollin.asm b/amforth-6.5/appl/eval-pollin/pollin.asm
deleted file mode 100644
index de3d0d2..0000000
--- a/amforth-6.5/appl/eval-pollin/pollin.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; for a description, what can be done in this
-; file see ../template/template.asm. You may want to
-; copy that file to this one and edit it afterwards.
-
-.include "preamble.inc"
-
-.set AMFORTH_RO_SEG = NRWW_START_ADDR+1
-
-; cpu clock in hertz
-.equ F_CPU = @F_CPU@
-.set BAUD_MAXERROR = 30
-.equ TIMER_INT = OVF2addr
-
-.include "drivers/usart@USART@.asm"
-
-; settings for 1wire interface
-.equ OW_PORT=PORTB
-.EQU OW_BIT=4
-.include "drivers/1wire.asm"
-
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/eval-pollin/words/applturnkey.asm b/amforth-6.5/appl/eval-pollin/words/applturnkey.asm
deleted file mode 100644
index 5e6b279..0000000
--- a/amforth-6.5/appl/eval-pollin/words/applturnkey.asm
+++ /dev/null
@@ -1,30 +0,0 @@
-; ( -- ) System
-; R( -- )
-; application specific turnkey action
-VE_APPLTURNKEY:
- .dw $ff0b
- .db "applturnkey",0
- .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
-XT_APPLTURNKEY:
- .dw DO_COLON
-PFA_APPLTURNKEY:
- .dw XT_USART
-
-.if WANT_INTERRUPTS == 1
- .dw XT_INTON
-.endif
- .dw XT_DOT_VER
- .dw XT_SPACE
- .dw XT_F_CPU
- .dw XT_DOLITERAL
- .dw 1000
- .dw XT_UMSLASHMOD
- .dw XT_NIP
- .dw XT_DECIMAL
- .dw XT_DOT
- .dw XT_DOSLITERAL
- .dw 4
- .db "kHz "
- .dw XT_ITYPE
- .dw XT_EXIT
diff --git a/amforth-6.5/appl/launchpad430/Makefile b/amforth-6.5/appl/launchpad430/Makefile
deleted file mode 100644
index f4aab37..0000000
--- a/amforth-6.5/appl/launchpad430/Makefile
+++ /dev/null
@@ -1,41 +0,0 @@
-
-all: lp-2553
-
-lp-2553.hex: lp-2553.asm ../../msp430/*
- naken_asm -I words \
- -I ../../msp430/devices/msp430g2553 \
- -I ../../msp430 \
- -I ../../common lp-2553.asm \
- -o lp-2553.hex -l
-
-lp-2553: lp-2553.hex
- mspdebug rf2500 "prog lp-2553.hex "
-
-# ###########################################
-
-lp-5529.hex: lp-5529.asm ../../msp430/*
- naken_asm -I words \
- -I ../../msp430/devices/msp430f5529 \
- -I ../../msp430 \
- -I ../../common lp-5529.asm \
- -o lp-5529.hex -l
-
-lp-5529: lp-5529.hex
- mspdebug tilib "prog lp-5529.hex "
-
-# ###########################################
-
-lp-5969.hex: lp-5969.asm ../../msp430/*
- naken_asm -I words \
- -I ../../msp430/devices/msp430fr5969 \
- -I ../../msp430 \
- -I ../../common lp-5969.asm \
- -o lp-5969.hex -l
-
-lp-5969: lp-5969.hex
- mspdebug tilib "prog lp-5969.hex "
-
-# ##############################################
-clean:
- rm *.lst *.hex
-
diff --git a/amforth-6.5/appl/launchpad430/blocks/1-ms.frt b/amforth-6.5/appl/launchpad430/blocks/1-ms.frt
deleted file mode 100644
index f0179ee..0000000
--- a/amforth-6.5/appl/launchpad430/blocks/1-ms.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-\ Launchpad 430 specific (G2553, 8MHz)
-: 1ms
- 41 0 do
- 11 0 do loop
- loop
-;
diff --git a/amforth-6.5/appl/launchpad430/build.xml b/amforth-6.5/appl/launchpad430/build.xml
deleted file mode 100644
index 6e0223e..0000000
--- a/amforth-6.5/appl/launchpad430/build.xml
+++ /dev/null
@@ -1,40 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="Launchpad 430" basedir="." default="Help">
- <import file="../msp-build.xml"/>
-
- <target name="lp-2553.hex" description="Hexfiles for TI launchpad430">
- <nakenasm projectname="lp-2553" mcu="msp430g2553"/>
- </target>
-
- <target name="lp-2553" depends="lp-2553.hex" description="Launchpad G2553">
- <echo>Uploading Hexfiles for TI LP 2553</echo>
- <mspdebug mcu="msp430g2553"
- projectname="lp-2553"
- programmer="rf2500"/>
- </target>
-
- <target name="lp-5529.hex" description="Hexfiles for TI LP F5529">
- <nakenasm projectname="lp-5529" mcu="msp430f5529"/>
- </target>
-
- <target name="lp-5529" depends="lp-5529.hex" description="Launchpad F5529">
- <echo>Uploading Hexfiles for TI LP 5529</echo>
- <mspdebug mcu="msp430f5529"
- projectname="lp-5529"
- programmer="tilib"/>
- </target>
-
-
- <target name="lp-5969.hex" description="Hexfiles for TI LP FR5969">
- <nakenasm projectname="lp-5969" mcu="msp430fr5969"/>
- </target>
-
- <target name="lp-5969" depends="lp-5969.hex" description="Launchpad FR5969">
- <echo>Uploading Hexfiles for TI LP 5969</echo>
- <mspdebug mcu="msp430fr5969"
- projectname="lp-5969"
- programmer="tilib"/>
- </target>
-
- <target name="compile" depends="lp-2553.hex,lp-5969.hex,lp-5529.hex"/>
-</project>
diff --git a/amforth-6.5/appl/launchpad430/dict_appl.inc b/amforth-6.5/appl/launchpad430/dict_appl.inc
deleted file mode 100644
index bb735cd..0000000
--- a/amforth-6.5/appl/launchpad430/dict_appl.inc
+++ /dev/null
@@ -1,66 +0,0 @@
-; These words not part of the essentials
-; but written in assembly language / notoation
-; for one of the following reason
-; * they use data available at compile time only (e.g. build-info)
-; * they are useful during core debugging (e.g. .S)
-; * they cannot be implemented in high level forth and
-; are not necessary for the core system (e.g. D+)
-;
-
-; various tools
-.include "words/dot-s.asm"
-;.include "words/dump.asm"
-; bleeding edge
-;.include "words/build-info.asm"
-
-.include "words/mcu-sr-fetch.asm"
-
-; additional environment queries
-;.include "words/env-usersize.asm"
-
-; next some words that may be useful in certain
-; applications only. Including them by default
-; would make the image too large to fit into 8kB
-; all other words are written in forth and have to
-; be uploaded as such.
-
-; location of some configuration stacks
-;.include "words/cfg-order.asm"
-;.include "words/cfg-recognizer.asm"
-
-;; generic tools
-;.include "words/n_to_r.asm"
-;.include "words/n_r_from.asm"
-;.include "words/get-stack.asm"
-;.include "words/set-stack.asm"
-
-;; wordlist management.
-;.include "words/infodp.asm"
-;.include "words/wordlist.asm"
-;.include "words/set-order.asm"
-;.include "words/get-order.asm"
-;.include "words/set-current.asm"
-;.include "words/forth-wordlist.asm"
-
-;; double cell arithmetics
-;.include "words/d-plus.asm"
-;.include "words/d-minus.asm"
-;.include "words/d-2slash.asm"
-;.include "words/d-2star.asm"
-
-;; some (external) assembly required
-;.include "words/code.asm"
-;.include "words/end-code.asm"
-
-;; compiler
-;.include "words/bracketcompile.asm"
-
-;; legacy words
-;.include "words/word.asm"
-;.include "words/count.asm"
-
-;; bit level operations
-;.include "words/bm-set.asm"
-;.include "words/bm-clear.asm"
-;.include "words/bm-test.asm"
-
diff --git a/amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.hex b/amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.hex
deleted file mode 100644
index 75d9e9f..0000000
--- a/amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.hex
+++ /dev/null
@@ -1,537 +0,0 @@
-:1002000000000000000000000000000000000000EE
-:1002100000000000000000000000000000000000DE
-:1002200000000000000000000000000000000000CE
-:1002300000000000000000000000000000000000BE
-:1002400000000000000000000000000000000000AE
-:10025000000000000000000000000000000000009E
-:0E026000000000000000000000000000000090
-:10028000000000000000000000000000000000006E
-:10029000000000000000000000000000000000005E
-:1002A000000000000000000000000000000000004E
-:1002B000000000000000000000000000000000003E
-:1002C000000000000000000000000000000000002E
-:1002D000000000000000000000000000000000001E
-:1002E000000000000000000000000000000000000E
-:1002F00000000000000000000000000000000000FE
-:1003000000000000000000000000000000000000ED
-:1003100000000000000000000000000000000000DD
-:1003200000000000000000000000000000000000CD
-:1003300000000000000000000000000000000000BD
-:1003400000000000000000000000000000000000AD
-:10035000000000000000000000000000000000009D
-:10036000000000000000000000000000000000008D
-:10037000000000000000000000000000000000007D
-:10038000000000000000000000000000000000006D
-:0603900000000000000067
-:10E000000B4D535034333047323535330000FF0762
-:10E01000666C6572617365001AE0364407560697B0
-:10E02000272C369000C00328369000E00628369052
-:10E0300000101E283690C0101B2C32C2B24000A522
-:10E040002C01B24002A52801B6430000B24000A551
-:10E050002801B24010A52C0132D2369000C005280C
-:10E06000369000E0022C3650C00136504000D73FB9
-:10E0700037443040DCE10FE0FF0221697EE03644A6
-:10E0800017B31E2026971C24379000C00328379012
-:10E0900000E00628379000100A283790C010072C9F
-:10E0A00032C2B24000A52C01B24040A528018746EB
-:10E0B0000000B24000A52801B24010A52C0132D2C8
-:10E0C00037443040DCE179E0FF0363216900D0E0B0
-:10E0D00036446697F527379000C00328379000E054
-:10E0E0000628379000100A283790C010072C32C23B
-:10E0F000B24000A52C01B24040A52801C74600004F
-:10E10000B24000A52801B24010A52C0132D2D83F60
-:10E11000C9E0FF04642D3E691AE136443A4407938E
-:10E12000202432C2B24000A52C01B24040A52801F3
-:10E1300017930B2416B309207B4A7C4A8C100BDC06
-:10E14000864B000026531783033CF64A0000165303
-:10E15000B24000A52801B24010A52C0132D217838D
-:10E16000E02337443040DCE113E1FF09666C616C69
-:10E1700069676E656400D8E13CE2000230E3B4E414
-:10E180003CE2FF01C8E47EE452E26BE1FF0453414C
-:10E190005645D8E13CE200023CE200103CE280003F
-:10E1A000E8ED18E018E152E28DE1FF08696E69744C
-:10E1B0002D72616DD8E13CE200103CE4B2E53EE630
-:10E1C0000800E8EB2AE606003CE200103CE2000210
-:10E1D0003CE280006EE752E2051205460F930220F2
-:10E1E00036453046248384470000074F0F433640AE
-:10E1F00028E9F73F1F4300132F4300133F4003005C
-:10E2000000132F4200133F40050000133F4006005B
-:10E2100000133F40070000133F4200133F40090036
-:10E2200000133F400A000013ABE1FF076578656308
-:10E230007574650036E20647374430463EE2248373
-:10E240008447000037453040DCE12BE2FF0465786D
-:10E25000697454E235413040DCE14DE2FF087661FB
-:10E26000726961626C65D8E104F07EE282FD18EBB0
-:10E2700052E25DE2FF08636F6E7374616E74D8E101
-:10E28000CEF464F5CCF68CE212F052E2248384479B
-:10E29000000027463040DCE1248384470000074625
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diff --git a/amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.lst b/amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.lst
deleted file mode 100644
index a384988..0000000
--- a/amforth-6.5/appl/launchpad430/lp-2553-with-interrupts.lst
+++ /dev/null
@@ -1,516 +0,0 @@
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 102 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0E000h
-.set WANT_INTERRUPTS = 1
-
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_a0.inc"
-.include "epilogue.asm"
-data sections:
-0200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..............
-0280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0390: 00 00 00 00 00 00 ......
-e000: 0b 4d 53 50 34 33 30 47 32 35 35 33 00 00 ff 07 .MSP430G2553....
-e010: 66 6c 65 72 61 73 65 00 1a e0 flerase...
-e076: 0f e0 ff 02 21 69 7e e0 ....!i..
-e0c6: 79 e0 ff 03 63 21 69 00 d0 e0 ....c!i...
-e110: c9 e0 ff 04 64 2d 3e 69 1a e1 ....d->i..
-e168: 13 e1 ff 09 66 6c 61 6c 69 67 6e 65 64 00 d8 e1 ....flaligned...
-e178: 3c e2 00 02 30 e3 b4 e4 3c e2 ff 01 c8 e4 7e e4 <...0...<.......
-e188: 52 e2 6b e1 ff 04 53 41 56 45 d8 e1 3c e2 00 02 R.k...SAVE..<...
-e198: 3c e2 00 10 3c e2 80 00 e8 ed 18 e0 18 e1 52 e2 <...<.........R.
-e1a8: 8d e1 ff 08 69 6e 69 74 2d 72 61 6d d8 e1 3c e2 ....init-ram..<.
-e1b8: 00 10 3c e4 b2 e5 3e e6 08 00 e8 eb 2a e6 06 00 ..<...>.....*...
-e1c8: 3c e2 00 10 3c e2 00 02 3c e2 80 00 6e e7 52 e2 <...<...<...n.R.
-e228: ab e1 ff 07 65 78 65 63 75 74 65 00 36 e2 ....execute.6.
-e23c: 3e e2 >.
-e24a: 2b e2 ff 04 65 78 69 74 54 e2 +...exitT.
-e25a: 4d e2 ff 08 76 61 72 69 61 62 6c 65 d8 e1 04 f0 M...variable....
-e26a: 7e e2 82 fd 18 eb 52 e2 5d e2 ff 08 63 6f 6e 73 ......R.]...cons
-e27a: 74 61 6e 74 d8 e1 ce f4 64 f5 cc f6 8c e2 12 f0 tant....d.......
-e28a: 52 e2 R.
-e2b8: 75 e2 ff 04 75 73 65 72 d8 e1 ce f4 cc f6 ce e2 u...user........
-e2c8: 12 f0 64 f5 52 e2 ..d.R.
-e2dc: bb e2 ff 03 64 75 70 00 e6 e2 ....dup...
-e2f0: df e2 ff 04 3f 64 75 70 fa e2 ....?dup..
-e302: f3 e2 ff 04 64 72 6f 70 0c e3 ....drop..
-e312: 05 e3 ff 04 73 77 61 70 1c e3 ....swap..
-e328: 15 e3 ff 04 6f 76 65 72 32 e3 ....over2.
-e340: 2b e3 ff 03 72 6f 74 00 4a e3 +...rot.J.
-e35c: 43 e3 ff 03 6e 69 70 00 66 e3 C...nip.f.
-e36c: 5f e3 ff 04 74 75 63 6b d8 e1 1a e3 30 e3 52 e2 _...tuck....0.R.
-e37c: 6f e3 ff 02 3e 72 84 e3 o...>r..
-e38c: 7f e3 ff 02 72 3e 94 e3 ....r>..
-e3a0: 8f e3 ff 02 72 40 a8 e3 ....r@..
-e3b4: a3 e3 ff 03 32 3e 72 00 be e3 ....2>r...
-e3ca: b7 e3 ff 03 32 72 3e 00 d4 e3 ....2r>...
-e3e6: cd e3 ff 03 73 70 40 00 f0 e3 ....sp@...
-e3fc: e9 e3 ff 03 73 70 21 00 06 e4 ....sp!...
-e40e: ff e3 ff 03 72 70 40 00 18 e4 ....rp@...
-e424: 11 e4 ff 03 72 70 21 00 2e e4 ....rp!...
-e436: 27 e4 ff 01 40 00 3e e4 '...@.>.
-e444: 39 e4 ff 01 21 00 4c e4 9...!.L.
-e456: 47 e4 ff 02 63 40 5e e4 G...c@^.
-e464: 59 e4 ff 02 63 21 6c e4 Y...c!l.
-e478: 67 e4 ff 01 2b 00 80 e4 g...+...
-e486: 7b e4 ff 02 2b 21 8e e4 ....+!..
-e498: 89 e4 ff 02 6d 2b a0 e4 ....m+..
-e4ae: 9b e4 ff 01 2d 00 b6 e4 ....-...
-e4c0: b1 e4 ff 03 61 6e 64 00 ca e4 ....and...
-e4d0: c3 e4 ff 02 6f 72 d8 e4 ....or..
-e4de: d3 e4 ff 03 78 6f 72 00 e8 e4 ....xor...
-e4ee: e1 e4 ff 06 69 6e 76 65 72 74 fa e4 ....invert..
-e500: f1 e4 ff 06 6e 65 67 61 74 65 0c e5 ....negate..
-e514: 03 e5 ff 02 31 2b 1c e5 ....1+..
-e522: 17 e5 ff 02 31 2d 2a e5 ....1-*.
-e530: 25 e5 ff 02 3e 3c 38 e5 %...><8.
-e53e: 33 e5 ff 02 32 2a 46 e5 3...2*F.
-e54c: 41 e5 ff 02 32 2f 54 e5 A...2/T.
-e55a: 4f e5 ff 06 6c 73 68 69 66 74 66 e5 O...lshiftf.
-e57a: 5d e5 ff 06 72 73 68 69 66 74 86 e5 ]...rshift..
-e59c: 7d e5 ff 02 30 3d a4 e5 ....0=..
-e5ac: 9f e5 ff 02 30 3c b4 e5 ....0<..
-e5be: af e5 ff 01 3d 00 c6 e5 ....=...
-e5d2: c1 e5 ff 02 3c 3e d8 e1 c4 e5 a2 e5 52 e2 d5 e5 ....<>......R...
-e5e2: ff 01 3c 00 e8 e5 ..<...
-e5f4: e3 e5 ff 01 3e 00 d8 e1 1a e3 e6 e5 52 e2 f7 e5 ....>.......R...
-e604: ff 02 75 3c 0a e6 ..u<..
-e612: 05 e6 ff 02 75 3e d8 e1 1a e3 08 e6 52 e2 15 e6 ....u>......R...
-e622: ff 06 62 72 61 6e 63 68 2c e6 ..branch,.
-e632: 23 e6 ff 07 3f 62 72 61 6e 63 68 00 40 e6 #...?branch.@.
-e64c: 4e e6 N.
-e668: 6a e6 j.
-e67c: 7e e6 ..
-e692: 35 e6 ff 01 69 00 9a e6 5...i...
-e6a8: 95 e6 ff 01 6a 00 b0 e6 ....j...
-e6c0: ab e6 ff 06 75 6e 6c 6f 6f 70 cc e6 ....unloop..
-e6d4: c3 e6 ff 03 75 6d 2a 00 de e6 ....um*...
-e706: d7 e6 ff 06 75 6d 2f 6d 6f 64 12 e7 ....um/mod..
-e742: 09 e7 ff 04 66 69 6c 6c 4c e7 ....fillL.
-e764: 45 e7 ff 05 63 6d 6f 76 65 00 70 e7 E...cmove.p.
-e788: 67 e7 ff 06 63 6d 6f 76 65 3e 94 e7 g...cmove>..
-e7b2: 8b e7 ff 05 63 73 6b 69 70 00 d8 e1 82 e3 e4 e2 ....cskip.......
-e7c2: 3e e6 16 00 30 e3 5c e4 a6 e3 c4 e5 3e e6 0a 00 >...0.\.....>...
-e7d2: 78 fd 72 f0 2a e6 e8 ff 92 e3 0a e3 52 e2 b5 e7 x.r.*.......R...
-e7e2: ff 05 63 73 63 61 6e 00 d8 e1 82 e3 30 e3 e4 e2 ..cscan.....0...
-e7f2: 5c e4 a6 e3 c4 e5 a2 e5 3e e6 18 00 1a e3 28 e5 \.......>.....(.
-e802: 1a e3 30 e3 b2 e5 a2 e5 3e e6 08 00 1a e5 2a e6 ..0.....>.....*.
-e812: de ff 64 e3 30 e3 b4 e4 92 e3 0a e3 52 e2 e3 e7 ..d.0.......R...
-e822: ff 02 73 3d 28 e8 ..s=(.
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-f9a8: 6c 64 ac f9 ld..
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-fef2: 6b 65 79 3f a8 fd 14 00 98 fe b0 fe f1 fe ff 02 ke.?............
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-ff12: 3e e6 0e 00 4c e6 98 e6 ee ef 90 ef 68 e6 f8 ff >...L.......h...
-ff22: 52 e2 01 ff ff 03 73 72 40 00 2e ff R.....sr@...
-ff3a: 27 ff ff 02 74 78 d8 e1 d6 fe 3e e6 fc ff 3c e2 '...tx....>...<.
-ff4a: 67 00 6a e4 52 e2 3d ff ff 03 74 78 3f 00 d8 e1 g.j.R.=...tx?...
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-ff6a: c4 e5 52 e2 53 ff ff 02 72 78 d8 e1 f6 fe 3e e6 ..R.S...rx....>.
-ff7a: fc ff 3c e2 66 00 5c e4 52 e2 71 ff ff 03 72 78 ..<.f.\.R.q...rx
-ff8a: 3f 00 d8 e1 fc f9 3c e2 01 00 e4 e2 3c e2 03 00 ?.....<.....<...
-ff9a: 5c e4 c8 e4 c4 e5 52 e2 87 ff ff 06 2b 75 73 61 \.....R.....+usa
-ffaa: 72 74 ae ff rt..
-fffe: ac f9 ..
-
-
-Program Info:
-Include Paths: .
- ../../msp430/devices/msp430g2553
- ../../msp430
- ../../common
- ../..
- /home/mt/share/naken_asm/include
- Instructions: 483
- Code Bytes: 1390
- Data Bytes: 7013
- Low Address: 0200 (512)
- High Address: ffff (65535)
-
diff --git a/amforth-6.5/appl/launchpad430/lp-2553.asm b/amforth-6.5/appl/launchpad430/lp-2553.asm
deleted file mode 100644
index 3a96c8d..0000000
--- a/amforth-6.5/appl/launchpad430/lp-2553.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 102 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0E000h
-.set WANT_INTERRUPTS = 0
-
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_a0.inc"
-.include "epilogue.asm"
diff --git a/amforth-6.5/appl/launchpad430/lp-2553.hex b/amforth-6.5/appl/launchpad430/lp-2553.hex
deleted file mode 100644
index be55d2a..0000000
--- a/amforth-6.5/appl/launchpad430/lp-2553.hex
+++ /dev/null
@@ -1,524 +0,0 @@
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diff --git a/amforth-6.5/appl/launchpad430/lp-2553.lst b/amforth-6.5/appl/launchpad430/lp-2553.lst
deleted file mode 100644
index 8a50ae0..0000000
--- a/amforth-6.5/appl/launchpad430/lp-2553.lst
+++ /dev/null
@@ -1,508 +0,0 @@
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 102 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0E000h
-.set WANT_INTERRUPTS = 0
-
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_a0.inc"
-.include "epilogue.asm"
-data sections:
-0200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0250: 00 00 00 00 00 00 00 00 00 00 ..........
-0280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-02f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0390: 00 00 00 00 00 00 ......
-e000: 0b 4d 53 50 34 33 30 47 32 35 35 33 00 00 ff 07 .MSP430G2553....
-e010: 66 6c 65 72 61 73 65 00 1a e0 flerase...
-e076: 0f e0 ff 02 21 69 7e e0 ....!i..
-e0c6: 79 e0 ff 03 63 21 69 00 d0 e0 ....c!i...
-e110: c9 e0 ff 04 64 2d 3e 69 1a e1 ....d->i..
-e168: 13 e1 ff 09 66 6c 61 6c 69 67 6e 65 64 00 d8 e1 ....flaligned...
-e178: f4 e1 00 02 e8 e2 6c e4 f4 e1 ff 01 80 e4 36 e4 ......l.......6.
-e188: 0a e2 6b e1 ff 04 53 41 56 45 d8 e1 f4 e1 00 02 ..k...SAVE......
-e198: f4 e1 00 10 f4 e1 80 00 24 ed 18 e0 18 e1 0a e2 ........$.......
-e1a8: 8d e1 ff 08 69 6e 69 74 2d 72 61 6d d8 e1 f4 e1 ....init-ram....
-e1b8: 00 10 f4 e3 6a e5 f6 e5 08 00 38 eb e2 e5 06 00 ....j.....8.....
-e1c8: f4 e1 00 10 f4 e1 00 02 f4 e1 80 00 26 e7 0a e2 ............&...
-e1e0: ab e1 ff 07 65 78 65 63 75 74 65 00 ee e1 ....execute...
-e1f4: f6 e1 ..
-e202: e3 e1 ff 04 65 78 69 74 0c e2 ....exit..
-e212: 05 e2 ff 08 76 61 72 69 61 62 6c 65 d8 e1 40 ef ....variable..@.
-e222: 36 e2 be fc 68 ea 0a e2 15 e2 ff 08 63 6f 6e 73 6...h.......cons
-e232: 74 61 6e 74 d8 e1 0a f4 a0 f4 08 f6 44 e2 4e ef tant........D.N.
-e242: 0a e2 ..
-e270: 2d e2 ff 04 75 73 65 72 d8 e1 0a f4 08 f6 86 e2 -...user........
-e280: 4e ef a0 f4 0a e2 N.....
-e294: 73 e2 ff 03 64 75 70 00 9e e2 s...dup...
-e2a8: 97 e2 ff 04 3f 64 75 70 b2 e2 ....?dup..
-e2ba: ab e2 ff 04 64 72 6f 70 c4 e2 ....drop..
-e2ca: bd e2 ff 04 73 77 61 70 d4 e2 ....swap..
-e2e0: cd e2 ff 04 6f 76 65 72 ea e2 ....over..
-e2f8: e3 e2 ff 03 72 6f 74 00 02 e3 ....rot...
-e314: fb e2 ff 03 6e 69 70 00 1e e3 ....nip...
-e324: 17 e3 ff 04 74 75 63 6b d8 e1 d2 e2 e8 e2 0a e2 ....tuck........
-e334: 27 e3 ff 02 3e 72 3c e3 '...>r<.
-e344: 37 e3 ff 02 72 3e 4c e3 7...r>L.
-e358: 47 e3 ff 02 72 40 60 e3 G...r@`.
-e36c: 5b e3 ff 03 32 3e 72 00 76 e3 [...2>r.v.
-e382: 6f e3 ff 03 32 72 3e 00 8c e3 o...2r>...
-e39e: 85 e3 ff 03 73 70 40 00 a8 e3 ....sp@...
-e3b4: a1 e3 ff 03 73 70 21 00 be e3 ....sp!...
-e3c6: b7 e3 ff 03 72 70 40 00 d0 e3 ....rp@...
-e3dc: c9 e3 ff 03 72 70 21 00 e6 e3 ....rp!...
-e3ee: df e3 ff 01 40 00 f6 e3 ....@...
-e3fc: f1 e3 ff 01 21 00 04 e4 ....!...
-e40e: ff e3 ff 02 63 40 16 e4 ....c@..
-e41c: 11 e4 ff 02 63 21 24 e4 ....c!$.
-e430: 1f e4 ff 01 2b 00 38 e4 ....+.8.
-e43e: 33 e4 ff 02 2b 21 46 e4 3...+!F.
-e450: 41 e4 ff 02 6d 2b 58 e4 A...m+X.
-e466: 53 e4 ff 01 2d 00 6e e4 S...-.n.
-e478: 69 e4 ff 03 61 6e 64 00 82 e4 i...and...
-e488: 7b e4 ff 02 6f 72 90 e4 ....or..
-e496: 8b e4 ff 03 78 6f 72 00 a0 e4 ....xor...
-e4a6: 99 e4 ff 06 69 6e 76 65 72 74 b2 e4 ....invert..
-e4b8: a9 e4 ff 06 6e 65 67 61 74 65 c4 e4 ....negate..
-e4cc: bb e4 ff 02 31 2b d4 e4 ....1+..
-e4da: cf e4 ff 02 31 2d e2 e4 ....1-..
-e4e8: dd e4 ff 02 3e 3c f0 e4 ....><..
-e4f6: eb e4 ff 02 32 2a fe e4 ....2*..
-e504: f9 e4 ff 02 32 2f 0c e5 ....2/..
-e512: 07 e5 ff 06 6c 73 68 69 66 74 1e e5 ....lshift..
-e532: 15 e5 ff 06 72 73 68 69 66 74 3e e5 ....rshift>.
-e554: 35 e5 ff 02 30 3d 5c e5 5...0=\.
-e564: 57 e5 ff 02 30 3c 6c e5 W...0<l.
-e576: 67 e5 ff 01 3d 00 7e e5 g...=...
-e58a: 79 e5 ff 02 3c 3e d8 e1 7c e5 5a e5 0a e2 8d e5 ....<>....Z.....
-e59a: ff 01 3c 00 a0 e5 ..<...
-e5ac: 9b e5 ff 01 3e 00 d8 e1 d2 e2 9e e5 0a e2 af e5 ....>...........
-e5bc: ff 02 75 3c c2 e5 ..u<..
-e5ca: bd e5 ff 02 75 3e d8 e1 d2 e2 c0 e5 0a e2 cd e5 ....u>..........
-e5da: ff 06 62 72 61 6e 63 68 e4 e5 ..branch..
-e5ea: db e5 ff 07 3f 62 72 61 6e 63 68 00 f8 e5 ....?branch...
-e604: 06 e6 ..
-e620: 22 e6 ".
-e634: 36 e6 6.
-e64a: ed e5 ff 01 69 00 52 e6 ....i.R.
-e660: 4d e6 ff 01 6a 00 68 e6 M...j.h.
-e678: 63 e6 ff 06 75 6e 6c 6f 6f 70 84 e6 c...unloop..
-e68c: 7b e6 ff 03 75 6d 2a 00 96 e6 ....um*...
-e6be: 8f e6 ff 06 75 6d 2f 6d 6f 64 ca e6 ....um/mod..
-e6fa: c1 e6 ff 04 66 69 6c 6c 04 e7 ....fill..
-e71c: fd e6 ff 05 63 6d 6f 76 65 00 28 e7 ....cmove.(.
-e740: 1f e7 ff 06 63 6d 6f 76 65 3e 4c e7 ....cmove>L.
-e76a: 43 e7 ff 05 63 73 6b 69 70 00 d8 e1 3a e3 9c e2 C...cskip...:...
-e77a: f6 e5 16 00 e8 e2 14 e4 5e e3 7c e5 f6 e5 0a 00 ........^.......
-e78a: b4 fc ae ef e2 e5 e8 ff 4a e3 c2 e2 0a e2 6d e7 ........J.....m.
-e79a: ff 05 63 73 63 61 6e 00 d8 e1 3a e3 e8 e2 9c e2 ..cscan...:.....
-e7aa: 14 e4 5e e3 7c e5 5a e5 f6 e5 18 00 d2 e2 e0 e4 ..^...Z.........
-e7ba: d2 e2 e8 e2 6a e5 5a e5 f6 e5 08 00 d2 e4 e2 e5 ....j.Z.........
-e7ca: de ff 1c e3 e8 e2 6c e4 4a e3 c2 e2 0a e2 9b e7 ......l.J.......
-e7da: ff 02 73 3d e0 e7 ..s=..
-e800: db e7 ff 05 61 6c 69 67 6e 00 d8 e1 76 ef b4 fc ....align...v...
-e810: 80 e4 88 ef 0a e2 03 e8 ff 07 61 6c 69 67 6e 65 ..........aligne
-e820: 64 00 d8 e1 9c e2 b4 fc 80 e4 36 e4 0a e2 19 e8 d.........6.....
-e830: ff 05 63 65 6c 6c 2b 00 3a e8 ..cell+.:.
-e840: 31 e8 ff 05 63 65 6c 6c 73 00 fe e4 43 e8 ff 05 1...cells...C...
-e850: 3e 62 6f 64 79 00 3a e8 4f e8 ff 03 75 70 40 00 >bod..:.O...up@.
-e860: 62 e8 b.
-e86e: 5b e8 ff 03 75 70 21 00 78 e8 [...up!.x.
-e880: 71 e8 ff 02 63 72 d8 e1 f4 e1 0d 00 00 fe f4 e1 q...cr..........
-e890: 0a 00 00 fe 0a e2 83 e8 ff 05 73 70 61 63 65 00 ..........space.
-e8a0: d8 e1 04 eb 00 fe 0a e2 99 e8 ff 06 73 70 61 63 ............spac
-e8b0: 65 73 d8 e1 aa fc e2 ec 9c e2 f6 e5 0a 00 a0 e8 es..............
-e8c0: e0 e4 e2 e5 f4 ff c2 e2 0a e2 ab e8 ff 04 75 6d ..............um
-e8d0: 69 6e d8 e1 24 ed d0 e5 f6 e5 04 00 d2 e2 c2 e2 in..$...........
-e8e0: 0a e2 cd e8 ff 04 75 6d 61 78 d8 e1 24 ed c0 e5 ......umax..$...
-e8f0: f6 e5 04 00 d2 e2 c2 e2 0a e2 e5 e8 ff 06 61 63 ..............ac
-e900: 63 65 70 74 d8 e1 e8 e2 36 e4 e0 e4 e8 e2 22 fe cept....6.....".
-e910: 9c e2 86 e9 5a e5 f6 e5 52 00 9c e2 f4 e1 08 00 ....Z...R.......
-e920: 7c e5 f6 e5 26 00 c2 e2 00 e3 24 ed b2 e5 3a e3 ....&.....$...:.
-e930: 00 e3 00 e3 4a e3 f6 e5 0e 00 76 e9 e0 e4 3a e3 ....J.....v...:.
-e940: e8 e2 4a e3 ea e8 e2 e5 1e 00 9c e2 04 eb 9e e5 ..J.............
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-f6f0: 64 6f d8 e1 08 f6 04 e6 f6 f5 aa fc c4 f6 0a e2 do..............
-f700: ef f6 fe 03 3f 64 6f 00 d8 e1 08 f6 18 f7 32 f6 ....?do.......2.
-f710: f2 f6 d2 e2 c4 f6 0a e2 d8 e1 24 ed 7c e5 9c e2 ..........$.....
-f720: 3a e3 f6 e5 04 00 14 ed 4a e3 b0 e4 0a e2 03 f7 :.......J.......
-f730: ff 07 65 6e 64 6c 6f 6f 70 00 d8 e1 ea f5 da f6 ..endloop.......
-f740: b0 e2 f6 e5 08 00 44 f6 e2 e5 f4 ff 0a e2 31 f7 ......D.......1.
-f750: fe 04 6c 6f 6f 70 d8 e1 08 f6 20 e6 3a f7 0a e2 ..loop.... .:...
-f760: 51 f7 fe 05 2b 6c 6f 6f 70 00 d8 e1 08 f6 34 e6 Q...+loop.....4.
-f770: 3a f7 0a e2 63 f7 fe 05 6c 65 61 76 65 00 d8 e1 :...c...leave...
-f780: 08 f6 82 e6 22 f6 c4 f6 0a e2 77 f7 ff 06 77 69 ....".....w...wi
-f790: 74 68 69 6e d8 e1 e8 e2 6c e4 3a e3 6c e4 4a e3 thin....l.:.l.J.
-f7a0: c0 e5 0a e2 8d f7 ff 05 64 65 70 74 68 00 d8 e1 ........depth...
-f7b0: a4 ea a6 e3 6c e4 0a e5 e0 e4 0a e2 a7 f7 ff 05 ....l...........
-f7c0: 77 6f 72 64 73 00 d8 e1 f4 e1 0c 02 f4 e3 3c f8 words.........<.
-f7d0: 0a e2 bf f7 ff 11 74 72 61 76 65 72 73 65 2d 77 ......traverse-w
-f7e0: 6f 72 64 6c 69 73 74 00 d8 e1 f4 e3 9c e2 f6 e5 ordlist.........
-f7f0: 1a 00 24 ed 74 e3 d2 e2 ec e1 8a e3 00 e3 f6 e5 ..$.t...........
-f800: 0a 00 f2 ef dc ed e2 e5 e4 ff 14 ed 0a e2 d5 f7 ................
-f810: ff 0b 6e 61 6d 65 3e 73 74 72 69 6e 67 00 d8 e1 ..name>string...
-f820: 4c ed f4 e1 ff 00 80 e4 0a e2 11 f8 ff 0d 73 68 L.............sh
-f830: 6f 77 2d 77 6f 72 64 6c 69 73 74 00 d8 e1 f4 e1 ow-wordlist.....
-f840: 48 f8 d2 e2 e8 f7 0a e2 d8 e1 1e f8 62 ed a0 e8 H...........b...
-f850: c8 fc 0a e2 2d f8 ff 03 75 2e 72 00 d8 e1 aa fc ....-...u.r.....
-f860: d2 e2 80 f8 0a e2 57 f8 ff 03 75 64 2e 00 d8 e1 ......W...ud....
-f870: aa fc 80 f8 a0 e8 0a e2 69 f8 ff 04 75 64 2e 72 ........i...ud.r
-f880: d8 e1 3a e3 4c ee 88 ee 9e ee 4a e3 e8 e2 6c e4 ..:.L.....J...l.
-f890: b2 e8 a4 e9 0a e2 7b f8 ff 02 2e 72 d8 e1 3a e3 ...........r..:.
-f8a0: 92 eb 4a e3 c0 f8 0a e2 99 f8 ff 02 64 2e d8 e1 ..J.........d...
-f8b0: aa fc c0 f8 a0 e8 0a e2 ab f8 ff 03 64 2e 72 00 ............d.r.
-f8c0: d8 e1 3a e3 2c e3 fe eb 4c ee 88 ee 00 e3 b6 ee ..:.,...L.......
-f8d0: 9e ee 4a e3 e8 e2 6c e4 b2 e8 a4 e9 0a e2 bb f8 ..J...l.........
-f8e0: ff 04 63 6f 6c 64 e8 f8 ..cold..
-f92e: e1 f8 ff 05 70 61 75 73 65 00 e4 fc 80 02 ac fd ....pause.......
-f93e: c0 fd 31 f9 ff 04 77 61 72 6d d8 e1 b4 e1 f4 e1 ..1...warm......
-f94e: 9c fd f4 e1 38 f9 84 fd 7c f4 26 fd da f2 43 f9 ....8.....&...C.
-f95e: ff 0b 61 70 70 6c 74 75 72 6e 6b 65 79 00 d8 e1 ..applturnke....
-f96e: e8 fe 06 fa a0 e8 3e fa f4 e1 e8 03 c8 e6 1c e3 ......>.........
-f97e: ee ee da ee 70 ed 03 6b 48 7a 62 ed 0a e2 5f f9 ....p..kH.b..._.
-f98e: ff 0b 65 6e 76 69 72 6f 6e 6d 65 6e 74 00 44 e2 ..environment.D.
-f99e: 28 02 00 00 ff 08 6d 63 75 2d 69 6e 66 6f d8 e1 (.....mcu-info..
-f9ae: f4 e1 b4 f9 0a e2 00 02 00 00 ff df 01 00 a3 f9 ................
-f9be: ff 03 63 70 75 00 d8 e1 f4 e1 00 e0 4c ed 0a e2 ..cpu.......L...
-f9ce: bf f9 ff 0a 66 6f 72 74 68 2d 6e 61 6d 65 d8 e1 ....forth-name..
-f9de: 70 ed 07 61 6d 66 6f 72 74 68 0a e2 d1 f9 ff 07 p..amforth......
-f9ee: 76 65 72 73 69 6f 6e 00 d8 e1 f4 e1 41 00 0a e2 version.....A...
-f9fe: 8f f9 ff 03 76 65 72 00 d8 e1 dc f9 62 ed a0 e8 ....ver.....b...
-fa0e: ea e9 f4 e3 f6 f9 ee ee 92 eb 4c ee 5c ee f4 e1 ..........L.\...
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-fa2e: c4 f9 62 ed 0a e2 01 fa ff 05 66 5f 63 70 75 00 ..b.......f_cpu.
-fa3e: d8 e1 f4 e1 00 12 f4 e1 7a 00 0a e2 37 fa ff 06 ............7...
-fa4e: 3f 73 74 61 63 6b d8 e1 ae f7 6a e5 f6 e5 08 00 ?stack....j.....
-fa5e: f4 e1 fc ff a8 f5 0a e2 4d fa fe 01 5c 00 d8 e1 ........M...\...
-fa6e: 9a ef 1c e3 de e9 02 e4 0a e2 69 fa ff 0a 70 61 ..........i...pa
-fa7e: 72 73 65 2d 6e 61 6d 65 d8 e1 04 eb 8e fa 0a e2 rse-name........
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-fa9e: 4a e3 a2 e7 24 ed 36 e4 9a ef c2 e2 6c e4 de e9 J...$.6.....l...
-faae: 02 e4 0a e2 7b fa ff 09 6d 61 70 2d 73 74 61 63 ........map-stac
-fabe: 6b 00 d8 e1 9c e2 38 e8 d2 e2 f4 e3 4a e8 18 ef k.....8.....J...
-face: 18 f7 f6 e5 26 00 04 e6 50 e6 f4 e3 d2 e2 3a e3 ....&...P.....:.
-fade: 5e e3 ec e1 b0 e2 f6 e5 0a 00 4a e3 c2 e2 82 e6 ^.........J.....
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-fafe: b5 fa ff 09 72 65 63 6f 67 6e 69 7a 65 00 d8 e1 ....recogni.e...
-fb0e: f4 e1 22 fb d2 e2 c0 fa 5a e5 f6 e5 06 00 14 ed ..".....Z.......
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-fb2e: ec e1 8a e3 00 e3 9c e2 58 fb 7c e5 f6 e5 08 00 ........X.......
-fb3e: c2 e2 aa fc 0a e2 1c e3 1c e3 c8 fc 0a e2 01 fb ................
-fb4e: ff 07 64 74 3a 6e 75 6c 6c 00 50 e2 60 fb 60 fb ..dt:null.P.`.`.
-fb5e: 60 fb d8 e1 f4 e1 f3 ff a8 f5 4f fb ff 08 72 65 `.........O...re
-fb6e: 63 3a 66 69 6e 64 d8 e1 4e f0 9c e2 5a e5 f6 e5 c:find..N...Z...
-fb7e: 08 00 c2 e2 58 fb 0a e2 94 fb 0a e2 6b fb ff 06 ....X.......k...
-fb8e: 64 74 3a 78 74 00 50 e2 9c fb a4 fb cc ed d8 e1 dt:xt.P.........
-fb9e: c2 e2 ec e1 0a e2 d8 e1 6a e5 f6 e5 06 00 4e ef ........j.....N.
-fbae: 0a e2 ec e1 0a e2 8d fb ff 06 64 74 3a 6e 75 6d ..........dt:num
-fbbe: 50 e2 9c fd 8e f0 8e f0 b7 fb ff 07 64 74 3a 64 P...........dt:d
-fbce: 6e 75 6d 00 50 e2 9c fd cc ed cc ed c9 fb ff 07 num.P...........
-fbde: 72 65 63 3a 6e 75 6d 00 d8 e1 76 f1 f6 e5 12 00 rec:num...v.....
-fbee: b4 fc 7c e5 f6 e5 06 00 be fb 0a e2 d2 fb 0a e2 ................
-fbfe: 58 fb 0a e2 dd fb fe 02 73 2c d8 e1 9c e2 3a e3 X.......s,....:.
-fc0e: 60 ef 76 ef 5e e3 18 e1 4a e3 88 ef 0a e8 0a e2 `.v.^...J.......
-fc1e: 05 fc ff 07 63 6f 6d 70 61 72 65 00 d8 e1 00 e3 ....compare.....
-fc2e: e8 e2 90 e5 f6 e5 0a 00 c2 e2 14 ed c8 fc 0a e2 ................
-fc3e: de e7 0a e2 21 fc ff 0f 73 65 61 72 63 68 2d 77 ....!...search-w
-fc4e: 6f 72 64 6c 69 73 74 00 d8 e1 3a e3 aa fc f4 e1 ordlist...:.....
-fc5e: 80 fc 4a e3 e8 f7 9c e2 5a e5 f6 e5 0a 00 14 ed ..J.....Z.......
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-fc7e: 0a e2 d8 e1 3a e3 c2 e2 24 ed 5e e3 1e f8 2a fc ....:...$.^...*.
-fc8e: f6 e5 0c 00 4a e3 c2 e2 aa fc c8 fc 0a e2 14 ed ....J...........
-fc9e: 4a e3 aa fc 0a e2 45 fc ff 01 30 00 44 e2 00 00 J.....E...0.D...
-fcae: a7 fc ff 01 31 00 44 e2 01 00 b1 fc ff 01 32 00 ....1.D.......2.
-fcbe: 44 e2 02 00 bb fc ff 02 2d 31 44 e2 ff ff c5 fc D.......-1D.....
-fcce: ff 07 28 64 65 66 65 72 29 00 d8 e1 0a f4 a0 f4 ..(defer).......
-fcde: 08 f6 e4 fc 0a e2 30 40 5c e2 9c e2 3e f5 dc ed ......0@\...>...
-fcee: ec e1 ec e1 0a e2 cf fc ff 07 28 76 61 6c 75 65 ..........(value
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-fd1e: 74 75 72 6e 6b 65 79 00 e4 fc 1c 02 ac fd c0 fd turnke..........
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-fd3e: f6 e5 16 00 08 f6 4a fd 4e ef 0a e2 d8 e1 4a e3 ......J.N.....J.
-fd4e: 9c e2 3e f5 3a e3 dc ed 9c e2 3e f5 3e f5 dc ed ..>.:.....>.>...
-fd5e: ec e1 0a e2 31 fd ff 06 64 65 66 65 72 40 d8 e1 ....1...defer@..
-fd6e: 56 e8 9c e2 3e f5 dc ed ec e1 0a e2 65 fd ff 06 V...>.......e...
-fd7e: 64 65 66 65 72 21 d8 e1 56 e8 9c e2 3e f5 3e f5 defer!..V...>.>.
-fd8e: dc ed ec e1 0a e2 7d fd ff 04 6e 6f 6f 70 d8 e1 ..........noop..
-fd9e: 0a e2 97 fd ff 07 52 64 65 66 65 72 40 00 d8 e1 ......Rdefer@...
-fdae: dc ed f4 e3 0a e2 a3 fd ff 07 52 64 65 66 65 72 ..........Rdefer
-fdbe: 21 00 d8 e1 dc ed 02 e4 0a e2 b7 fd ff 07 55 64 !.............Ud
-fdce: 65 66 65 72 40 00 d8 e1 dc ed 60 e8 36 e4 f4 e3 efer@.....`.6...
-fdde: 0a e2 cb fd ff 07 55 64 65 66 65 72 21 00 d8 e1 ......Udefer!...
-fdee: dc ed 60 e8 36 e4 02 e4 0a e2 e3 fd ff 04 65 6d ..`.6.........em
-fdfe: 69 74 e4 fc 0e 00 d4 fd ec fd fb fd ff 05 65 6d it............em
-fe0e: 69 74 3f 00 e4 fc 10 00 d4 fd ec fd 0b fe ff 03 it?.............
-fe1e: 6b 65 79 00 e4 fc 12 00 d4 fd ec fd 1d fe ff 04 ke..............
-fe2e: 6b 65 79 3f e4 fc 14 00 d4 fd ec fd 2d fe ff 02 ke.?........-...
-fe3e: 2e 73 d8 e1 ae f7 cc ee a0 e8 ae f7 aa fc 18 f7 .s..............
-fe4e: f6 e5 0e 00 04 e6 50 e6 2a ef cc ee 20 e6 f8 ff ......P.*... ...
-fe5e: 0a e2 3d fe ff 03 73 72 40 00 6a fe ..=...sr@.j.
-fe76: 63 fe ff 02 74 78 d8 e1 12 fe f6 e5 fc ff f4 e1 c...tx..........
-fe86: 67 00 22 e4 0a e2 79 fe ff 03 74 78 3f 00 d8 e1 g.".......tx?...
-fe96: 38 f9 f4 e1 02 00 9c e2 f4 e1 03 00 14 e4 80 e4 8...............
-fea6: 7c e5 0a e2 8f fe ff 02 72 78 d8 e1 32 fe f6 e5 ........rx..2...
-feb6: fc ff f4 e1 66 00 14 e4 0a e2 ad fe ff 03 72 78 ....f.........rx
-fec6: 3f 00 d8 e1 38 f9 f4 e1 01 00 9c e2 f4 e1 03 00 ?...8...........
-fed6: 14 e4 80 e4 7c e5 0a e2 c3 fe ff 06 2b 75 73 61 ............+usa
-fee6: 72 74 ea fe rt..
-fffe: e8 f8 ..
-
-
-Program Info:
-Include Paths: .
- ../../msp430/devices/msp430g2553
- ../../msp430
- ../../common
- ../..
- /home/mt/share/naken_asm/include
- Instructions: 510
- Code Bytes: 1276
- Data Bytes: 6911
- Low Address: 0200 (512)
- High Address: ffff (65535)
-
diff --git a/amforth-6.5/appl/launchpad430/lp-5529.asm b/amforth-6.5/appl/launchpad430/lp-5529.asm
deleted file mode 100644
index 9f32bee..0000000
--- a/amforth-6.5/appl/launchpad430/lp-5529.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 92 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0e000h
-
-.set WANT_INTERRUPTS = 0
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_a1.inc"
-.include "epilogue.asm"
diff --git a/amforth-6.5/appl/launchpad430/lp-5529.hex b/amforth-6.5/appl/launchpad430/lp-5529.hex
deleted file mode 100644
index 708f37a..0000000
--- a/amforth-6.5/appl/launchpad430/lp-5529.hex
+++ /dev/null
@@ -1,522 +0,0 @@
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diff --git a/amforth-6.5/appl/launchpad430/lp-5529.lst b/amforth-6.5/appl/launchpad430/lp-5529.lst
deleted file mode 100644
index 68c2001..0000000
--- a/amforth-6.5/appl/launchpad430/lp-5529.lst
+++ /dev/null
@@ -1,508 +0,0 @@
-
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 92 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0e000h
-
-.set WANT_INTERRUPTS = 0
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_a1.inc"
-.include "epilogue.asm"
-data sections:
-2400: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2410: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2450: 00 00 00 00 00 00 00 00 00 00 ..........
-2480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2490: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-24a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-24b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-24c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-24d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-24e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-24f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2510: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2530: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2570: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-2580: 00 00 00 00 00 00 00 00 00 00 00 00 ............
-e000: 0b 4d 53 50 34 33 30 46 35 35 32 39 00 00 ff 07 .MSP430F5529....
-e010: 66 6c 65 72 61 73 65 00 1a e0 flerase...
-e076: 0f e0 ff 02 21 69 7e e0 ....!i..
-e0c6: 79 e0 ff 03 63 21 69 00 d0 e0 ....c!i...
-e110: c9 e0 ff 04 64 2d 3e 69 1a e1 ....d->i..
-e168: 13 e1 ff 09 66 6c 61 6c 69 67 6e 65 64 00 d8 e1 ....flaligned...
-e178: f4 e1 00 02 e8 e2 6c e4 f4 e1 ff 01 80 e4 36 e4 ......l.......6.
-e188: 0a e2 6b e1 ff 04 53 41 56 45 d8 e1 f4 e1 00 24 ..k...SAVE.....$
-e198: f4 e1 00 18 f4 e1 80 00 18 ed 18 e0 18 e1 0a e2 ................
-e1a8: 8d e1 ff 08 69 6e 69 74 2d 72 61 6d d8 e1 f4 e1 ....init-ram....
-e1b8: 00 18 f4 e3 6a e5 f6 e5 08 00 2c eb e2 e5 06 00 ....j.....,.....
-e1c8: f4 e1 00 18 f4 e1 00 24 f4 e1 80 00 1a e7 0a e2 .......$........
-e1e0: ab e1 ff 07 65 78 65 63 75 74 65 00 ee e1 ....execute...
-e1f4: f6 e1 ..
-e202: e3 e1 ff 04 65 78 69 74 0c e2 ....exit..
-e212: 05 e2 ff 08 76 61 72 69 61 62 6c 65 d8 e1 34 ef ....variable..4.
-e222: 36 e2 c2 fc 5c ea 0a e2 15 e2 ff 08 63 6f 6e 73 6...\.......cons
-e232: 74 61 6e 74 d8 e1 fe f3 94 f4 fc f5 44 e2 42 ef tant........D.B.
-e242: 0a e2 ..
-e270: 2d e2 ff 04 75 73 65 72 d8 e1 fe f3 fc f5 86 e2 -...user........
-e280: 42 ef 94 f4 0a e2 B.....
-e294: 73 e2 ff 03 64 75 70 00 9e e2 s...dup...
-e2a8: 97 e2 ff 04 3f 64 75 70 b2 e2 ....?dup..
-e2ba: ab e2 ff 04 64 72 6f 70 c4 e2 ....drop..
-e2ca: bd e2 ff 04 73 77 61 70 d4 e2 ....swap..
-e2e0: cd e2 ff 04 6f 76 65 72 ea e2 ....over..
-e2f8: e3 e2 ff 03 72 6f 74 00 02 e3 ....rot...
-e314: fb e2 ff 03 6e 69 70 00 1e e3 ....nip...
-e324: 17 e3 ff 04 74 75 63 6b d8 e1 d2 e2 e8 e2 0a e2 ....tuck........
-e334: 27 e3 ff 02 3e 72 3c e3 '...>r<.
-e344: 37 e3 ff 02 72 3e 4c e3 7...r>L.
-e358: 47 e3 ff 02 72 40 60 e3 G...r@`.
-e36c: 5b e3 ff 03 32 3e 72 00 76 e3 [...2>r.v.
-e382: 6f e3 ff 03 32 72 3e 00 8c e3 o...2r>...
-e39e: 85 e3 ff 03 73 70 40 00 a8 e3 ....sp@...
-e3b4: a1 e3 ff 03 73 70 21 00 be e3 ....sp!...
-e3c6: b7 e3 ff 03 72 70 40 00 d0 e3 ....rp@...
-e3dc: c9 e3 ff 03 72 70 21 00 e6 e3 ....rp!...
-e3ee: df e3 ff 01 40 00 f6 e3 ....@...
-e3fc: f1 e3 ff 01 21 00 04 e4 ....!...
-e40e: ff e3 ff 02 63 40 16 e4 ....c@..
-e41c: 11 e4 ff 02 63 21 24 e4 ....c!$.
-e430: 1f e4 ff 01 2b 00 38 e4 ....+.8.
-e43e: 33 e4 ff 02 2b 21 46 e4 3...+!F.
-e450: 41 e4 ff 02 6d 2b 58 e4 A...m+X.
-e466: 53 e4 ff 01 2d 00 6e e4 S...-.n.
-e478: 69 e4 ff 03 61 6e 64 00 82 e4 i...and...
-e488: 7b e4 ff 02 6f 72 90 e4 ....or..
-e496: 8b e4 ff 03 78 6f 72 00 a0 e4 ....xor...
-e4a6: 99 e4 ff 06 69 6e 76 65 72 74 b2 e4 ....invert..
-e4b8: a9 e4 ff 06 6e 65 67 61 74 65 c4 e4 ....negate..
-e4cc: bb e4 ff 02 31 2b d4 e4 ....1+..
-e4da: cf e4 ff 02 31 2d e2 e4 ....1-..
-e4e8: dd e4 ff 02 3e 3c f0 e4 ....><..
-e4f6: eb e4 ff 02 32 2a fe e4 ....2*..
-e504: f9 e4 ff 02 32 2f 0c e5 ....2/..
-e512: 07 e5 ff 06 6c 73 68 69 66 74 1e e5 ....lshift..
-e532: 15 e5 ff 06 72 73 68 69 66 74 3e e5 ....rshift>.
-e554: 35 e5 ff 02 30 3d 5c e5 5...0=\.
-e564: 57 e5 ff 02 30 3c 6c e5 W...0<l.
-e576: 67 e5 ff 01 3d 00 7e e5 g...=...
-e58a: 79 e5 ff 02 3c 3e d8 e1 7c e5 5a e5 0a e2 8d e5 ....<>....Z.....
-e59a: ff 01 3c 00 a0 e5 ..<...
-e5ac: 9b e5 ff 01 3e 00 d8 e1 d2 e2 9e e5 0a e2 af e5 ....>...........
-e5bc: ff 02 75 3c c2 e5 ..u<..
-e5ca: bd e5 ff 02 75 3e d8 e1 d2 e2 c0 e5 0a e2 cd e5 ....u>..........
-e5da: ff 06 62 72 61 6e 63 68 e4 e5 ..branch..
-e5ea: db e5 ff 07 3f 62 72 61 6e 63 68 00 f8 e5 ....?branch...
-e604: 06 e6 ..
-e620: 22 e6 ".
-e634: 36 e6 6.
-e64a: ed e5 ff 01 69 00 52 e6 ....i.R.
-e660: 4d e6 ff 01 6a 00 68 e6 M...j.h.
-e678: 63 e6 ff 06 75 6e 6c 6f 6f 70 84 e6 c...unloop..
-e68c: 7b e6 ff 03 75 6d 2a 00 96 e6 ....um*...
-e6b2: 8f e6 ff 06 75 6d 2f 6d 6f 64 be e6 ....um/mod..
-e6ee: b5 e6 ff 04 66 69 6c 6c f8 e6 ....fill..
-e710: f1 e6 ff 05 63 6d 6f 76 65 00 1c e7 ....cmove...
-e734: 13 e7 ff 06 63 6d 6f 76 65 3e 40 e7 ....cmove>@.
-e75e: 37 e7 ff 05 63 73 6b 69 70 00 d8 e1 3a e3 9c e2 7...cskip...:...
-e76e: f6 e5 16 00 e8 e2 14 e4 5e e3 7c e5 f6 e5 0a 00 ........^.......
-e77e: b8 fc a2 ef e2 e5 e8 ff 4a e3 c2 e2 0a e2 61 e7 ........J.....a.
-e78e: ff 05 63 73 63 61 6e 00 d8 e1 3a e3 e8 e2 9c e2 ..cscan...:.....
-e79e: 14 e4 5e e3 7c e5 5a e5 f6 e5 18 00 d2 e2 e0 e4 ..^...Z.........
-e7ae: d2 e2 e8 e2 6a e5 5a e5 f6 e5 08 00 d2 e4 e2 e5 ....j.Z.........
-e7be: de ff 1c e3 e8 e2 6c e4 4a e3 c2 e2 0a e2 8f e7 ......l.J.......
-e7ce: ff 02 73 3d d4 e7 ..s=..
-e7f4: cf e7 ff 05 61 6c 69 67 6e 00 d8 e1 6a ef b8 fc ....align...j...
-e804: 80 e4 7c ef 0a e2 f7 e7 ff 07 61 6c 69 67 6e 65 ..........aligne
-e814: 64 00 d8 e1 9c e2 b8 fc 80 e4 36 e4 0a e2 0d e8 d.........6.....
-e824: ff 05 63 65 6c 6c 2b 00 2e e8 ..cell+...
-e834: 25 e8 ff 05 63 65 6c 6c 73 00 fe e4 37 e8 ff 05 %...cells...7...
-e844: 3e 62 6f 64 79 00 2e e8 43 e8 ff 03 75 70 40 00 >bod....C...up@.
-e854: 56 e8 V.
-e862: 4f e8 ff 03 75 70 21 00 6c e8 O...up!.l.
-e874: 65 e8 ff 02 63 72 d8 e1 f4 e1 0d 00 04 fe f4 e1 e...cr..........
-e884: 0a 00 04 fe 0a e2 77 e8 ff 05 73 70 61 63 65 00 ......w...space.
-e894: d8 e1 f8 ea 04 fe 0a e2 8d e8 ff 06 73 70 61 63 ............spac
-e8a4: 65 73 d8 e1 ae fc d6 ec 9c e2 f6 e5 0a 00 94 e8 es..............
-e8b4: e0 e4 e2 e5 f4 ff c2 e2 0a e2 9f e8 ff 04 75 6d ..............um
-e8c4: 69 6e d8 e1 18 ed d0 e5 f6 e5 04 00 d2 e2 c2 e2 in..............
-e8d4: 0a e2 c1 e8 ff 04 75 6d 61 78 d8 e1 18 ed c0 e5 ......umax......
-e8e4: f6 e5 04 00 d2 e2 c2 e2 0a e2 d9 e8 ff 06 61 63 ..............ac
-e8f4: 63 65 70 74 d8 e1 e8 e2 36 e4 e0 e4 e8 e2 26 fe cept....6.....&.
-e904: 9c e2 7a e9 5a e5 f6 e5 52 00 9c e2 f4 e1 08 00 ....Z...R.......
-e914: 7c e5 f6 e5 26 00 c2 e2 00 e3 18 ed b2 e5 3a e3 ....&.........:.
-e924: 00 e3 00 e3 4a e3 f6 e5 0e 00 6a e9 e0 e4 3a e3 ....J.....j...:.
-e934: e8 e2 4a e3 de e8 e2 e5 1e 00 9c e2 f8 ea 9e e5 ..J.............
-e944: f6 e5 06 00 c2 e2 f8 ea 9c e2 04 fe e8 e2 22 e4 ..............".
-e954: d2 e4 e8 e2 c6 e8 e2 e5 a6 ff c2 e2 1c e3 d2 e2 ................
-e964: 6c e4 7a e8 0a e2 d8 e1 f4 e1 08 00 9c e2 04 fe l...............
-e974: 94 e8 04 fe 0a e2 d8 e1 9c e2 f4 e1 0d 00 7c e5 ................
-e984: d2 e2 f4 e1 0a 00 7c e5 8e e4 0a e2 f1 e8 ff 04 ................
-e994: 74 79 70 65 d8 e1 0c ef 0c f7 f6 e5 0e 00 04 e6 t.pe............
-e9a4: 50 e6 14 e4 04 fe 20 e6 f8 ff 0a e2 93 e9 ff 06 P..... .........
-e9b4: 61 3e 69 6e 66 6f d8 e1 f4 e1 00 18 f4 e1 00 24 a>info.........$
-e9c4: 6c e4 36 e4 0a e2 b3 e9 ff 03 3e 69 6e 00 86 e2 l.6.......>in...
-e9d4: 18 00 cd e9 ff 04 62 61 73 65 86 e2 0c 00 d9 e9 ......base......
-e9e4: ff 05 73 74 61 74 65 00 44 e2 82 24 e5 e9 ff 02 ..state.D..$....
-e9f4: 64 70 44 e2 1e 24 f3 e9 ff 0b 67 65 74 2d 63 75 dpD..$....get-cu
-ea04: 72 72 65 6e 74 00 d8 e1 f4 e1 24 24 f4 e3 0a e2 rrent.....$$....
-ea14: fd e9 ff 03 68 6c 64 00 44 e2 84 24 17 ea ff 02 ....hld.D..$....
-ea24: 6c 70 44 e2 86 24 23 ea ff 03 69 64 70 00 44 e2 lpD..$#...idp.D.
-ea34: 20 24 2d ea ff 06 6e 65 77 65 73 74 44 e2 88 24 $-...newestD..$
-ea44: 39 ea ff 06 6c 61 74 65 73 74 44 e2 8c 24 47 ea 9...latestD..$G.
-ea54: ff 05 61 6c 6c 6f 74 00 d8 e1 f6 e9 44 e4 0a e2 ..allot.....D...
-ea64: 55 ea ff 03 70 61 64 00 d8 e1 34 ef f4 e1 28 00 U...pad...4...(.
-ea74: 36 e4 0a e2 67 ea ff 03 6c 70 30 00 44 e2 ec 24 6...g...lp0.D..$
-ea84: 7b ea ff 03 72 70 30 00 44 e2 8c 25 87 ea ff 03 ....rp0.D..%....
-ea94: 73 70 30 00 44 e2 3c 25 93 ea ff 0a 72 65 66 69 sp0.D.<%....refi
-eaa4: 6c 6c 2d 74 69 62 d8 e1 e2 ea f4 e1 5c 00 f8 e8 ll-tib......\...
-eab4: ee ea 02 e4 ae fc d2 e9 02 e4 cc fc 0a e2 9f ea ................
-eac4: ff 0a 73 6f 75 72 63 65 2d 74 69 62 d8 e1 e2 ea ..source-tib....
-ead4: ee ea f4 e3 0a e2 c5 ea ff 03 74 69 62 00 44 e2 ..........tib.D.
-eae4: 90 24 dd ea ff 04 23 74 69 62 44 e2 8e 24 e9 ea .$....#tibD..$..
-eaf4: ff 02 62 6c 44 e2 20 00 f5 ea ff 07 74 6f 75 70 ..blD. .....toup
-eb04: 70 65 72 00 d8 e1 9c e2 f4 e1 61 00 f4 e1 7b 00 per.......a.....
-eb14: 88 f7 f6 e5 08 00 f4 e1 df 00 80 e4 0a e2 ff ea ................
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-f8c4: 92 ee 4a e3 e8 e2 6c e4 a6 e8 98 e9 0a e2 af f8 ..J...l.........
-f8d4: ff 04 63 6f 6c 64 dc f8 ..cold..
-f932: d5 f8 ff 05 70 61 75 73 65 00 e8 fc 80 24 b0 fd ....pause....$..
-f942: c4 fd 35 f9 ff 04 77 61 72 6d d8 e1 b4 e1 f4 e1 ..5...warm......
-f952: a0 fd f4 e1 3c f9 88 fd 70 f4 2a fd ce f2 47 f9 ....<...p.*...G.
-f962: ff 0b 61 70 70 6c 74 75 72 6e 6b 65 79 00 d8 e1 ..applturnke....
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-f992: ff 0b 65 6e 76 69 72 6f 6e 6d 65 6e 74 00 44 e2 ..environment.D.
-f9a2: 28 24 00 00 ff 08 6d 63 75 2d 69 6e 66 6f d8 e1 ($....mcu-info..
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-f9c2: ff 03 63 70 75 00 d8 e1 f4 e1 00 e0 40 ed 0a e2 ..cpu.......@...
-f9d2: c3 f9 ff 0a 66 6f 72 74 68 2d 6e 61 6d 65 d8 e1 ....forth-name..
-f9e2: 64 ed 07 61 6d 66 6f 72 74 68 0a e2 d5 f9 ff 07 d..amforth......
-f9f2: 76 65 72 73 69 6f 6e 00 d8 e1 f4 e1 41 00 0a e2 version.....A...
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-fa42: d8 e1 f4 e1 00 12 f4 e1 7a 00 0a e2 3b fa ff 06 ............;...
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-fba2: c2 e2 ec e1 0a e2 d8 e1 6a e5 f6 e5 06 00 42 ef ........j.....B.
-fbb2: 0a e2 ec e1 0a e2 91 fb ff 06 64 74 3a 6e 75 6d ..........dt:num
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-fbd2: 6e 75 6d 00 50 e2 a0 fd c0 ed c0 ed cd fb ff 07 num.P...........
-fbe2: 72 65 63 3a 6e 75 6d 00 d8 e1 6a f1 f6 e5 12 00 rec:num...j.....
-fbf2: b8 fc 7c e5 f6 e5 06 00 c2 fb 0a e2 d6 fb 0a e2 ................
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-fc22: 09 fc ff 07 63 6f 6d 70 61 72 65 00 d8 e1 00 e3 ....compare.....
-fc32: e8 e2 90 e5 f6 e5 0a 00 c2 e2 08 ed cc fc 0a e2 ................
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-fc52: 6f 72 64 6c 69 73 74 00 d8 e1 3a e3 ae fc f4 e1 ordlist...:.....
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-fd82: 64 65 66 65 72 21 d8 e1 4a e8 9c e2 32 f5 32 f5 defer!..J...2.2.
-fd92: d0 ed ec e1 0a e2 81 fd ff 04 6e 6f 6f 70 d8 e1 ..........noop..
-fda2: 0a e2 9b fd ff 07 52 64 65 66 65 72 40 00 d8 e1 ......Rdefer@...
-fdb2: d0 ed f4 e3 0a e2 a7 fd ff 07 52 64 65 66 65 72 ..........Rdefer
-fdc2: 21 00 d8 e1 d0 ed 02 e4 0a e2 bb fd ff 07 55 64 !.............Ud
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-fde2: 0a e2 cf fd ff 07 55 64 65 66 65 72 21 00 d8 e1 ......Udefer!...
-fdf2: d0 ed 54 e8 36 e4 02 e4 0a e2 e7 fd ff 04 65 6d ..T.6.........em
-fe02: 69 74 e8 fc 0e 00 d8 fd f0 fd ff fd ff 05 65 6d it............em
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-fe22: 6b 65 79 00 e8 fc 12 00 d8 fd f0 fd 21 fe ff 04 ke..........!...
-fe32: 6b 65 79 3f e8 fc 14 00 d8 fd f0 fd 31 fe ff 02 ke.?........1...
-fe42: 2e 73 d8 e1 a2 f7 c0 ee 94 e8 a2 f7 ae fc 0c f7 .s..............
-fe52: f6 e5 0e 00 04 e6 50 e6 1e ef c0 ee 20 e6 f8 ff ......P..... ...
-fe62: 0a e2 41 fe ff 03 73 72 40 00 6e fe ..A...sr@.n.
-fe7a: 67 fe ff 02 74 78 d8 e1 16 fe f6 e5 fc ff f4 e1 g...tx..........
-fe8a: 0e 06 22 e4 0a e2 7d fe ff 03 74 78 3f 00 d8 e1 ..".......tx?...
-fe9a: 3c f9 f4 e1 02 00 9c e2 f4 e1 1d 06 14 e4 80 e4 <...............
-feaa: 7c e5 0a e2 93 fe ff 02 72 78 d8 e1 36 fe f6 e5 ........rx..6...
-feba: fc ff f4 e1 0c 06 14 e4 0a e2 b1 fe ff 03 72 78 ..............rx
-feca: 3f 00 d8 e1 3c f9 f4 e1 01 00 9c e2 f4 e1 1d 06 ?...<...........
-feda: 14 e4 80 e4 7c e5 0a e2 c7 fe ff 06 2b 75 73 61 ............+usa
-feea: 72 74 ee fe rt..
-fffe: dc f8 ..
-
-
-Program Info:
-Include Paths: .
- ../../msp430/devices/msp430f5529
- ../../msp430
- ../../common
- ../..
- /home/mt/share/naken_asm/include
- Instructions: 503
- Code Bytes: 1264
- Data Bytes: 6901
- Low Address: 2400 (9216)
- High Address: ffff (65535)
-
diff --git a/amforth-6.5/appl/launchpad430/lp-5969.asm b/amforth-6.5/appl/launchpad430/lp-5969.asm
deleted file mode 100644
index 891e936..0000000
--- a/amforth-6.5/appl/launchpad430/lp-5969.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 92 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0e000h
-
-.set WANT_INTERRUPTS = 0
-
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_f-a0.inc"
-.include "epilogue.asm"
diff --git a/amforth-6.5/appl/launchpad430/lp-5969.hex b/amforth-6.5/appl/launchpad430/lp-5969.hex
deleted file mode 100644
index 92152a3..0000000
--- a/amforth-6.5/appl/launchpad430/lp-5969.hex
+++ /dev/null
@@ -1,510 +0,0 @@
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diff --git a/amforth-6.5/appl/launchpad430/lp-5969.lst b/amforth-6.5/appl/launchpad430/lp-5969.lst
deleted file mode 100644
index abf7282..0000000
--- a/amforth-6.5/appl/launchpad430/lp-5969.lst
+++ /dev/null
@@ -1,508 +0,0 @@
-
-
-.include "preamble.inc"
-APPUSERSIZE equ 10 ; bytes, see uinit.asm
-RSTACK_SIZE equ 40 ; cells
-PSTACK_SIZE equ 40 ; cells
-; following only required for terminal tasks
-TIB_SIZE equ 92 ; bytes (must be even)
-
-F_CPU EQU 8000000
-AMFORTH_START equ 0e000h
-
-.set WANT_INTERRUPTS = 0
-
-; now include all and everything
-
-.include "amforth.asm"
-.include "drivers/usart_f-a0.inc"
-.include "epilogue.asm"
-data sections:
-1c00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1c10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1c20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1c30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1c40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1c50: 00 00 00 00 00 00 00 00 00 00 ..........
-1c80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1c90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1ca0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1cb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1cc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1cd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1ce0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1cf0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-1d80: 00 00 00 00 00 00 00 00 00 00 00 00 ............
-e000: 0c 4d 53 50 34 33 30 46 52 35 39 36 39 00 00 00 .MSP430FR5969...
-e010: ff 02 21 69 16 e0 ..!i..
-e030: 11 e0 ff 03 63 21 69 00 3a e0 ....c!i.:.
-e052: 33 e0 ff 04 64 2d 3e 69 5c e0 3...d->i\.
-e0a2: 55 e0 ff 09 66 6c 61 6c 69 67 6e 65 64 00 0e e1 U...flaligned...
-e0b2: 2a e1 00 02 1e e2 a2 e3 2a e1 ff 01 b6 e3 6c e3 *.......*.....l.
-e0c2: 40 e1 a5 e0 ff 04 53 41 56 45 0e e1 2a e1 00 1c @.....SAVE..*...
-e0d2: 2a e1 00 18 2a e1 80 00 5a e0 40 e1 c7 e0 ff 08 *...*...Z.@.....
-e0e2: 69 6e 69 74 2d 72 61 6d 0e e1 2a e1 00 18 2a e3 init-ram..*...*.
-e0f2: a0 e4 2c e5 08 00 62 ea 18 e5 06 00 2a e1 00 18 ..,...b.....*...
-e102: 2a e1 00 1c 2a e1 80 00 50 e6 40 e1 *...*...P.@.
-e116: e1 e0 ff 07 65 78 65 63 75 74 65 00 24 e1 ....execute.$.
-e12a: 2c e1 ,.
-e138: 19 e1 ff 04 65 78 69 74 42 e1 ....exitB.
-e148: 3b e1 ff 08 76 61 72 69 61 62 6c 65 0e e1 6a ee ;...variable..j.
-e158: 6c e1 ee fb 92 e9 40 e1 4b e1 ff 08 63 6f 6e 73 l.....@.K...cons
-e168: 74 61 6e 74 0e e1 34 f3 ca f3 32 f5 7a e1 78 ee tant..4...2...x.
-e178: 40 e1 @.
-e1a6: 63 e1 ff 04 75 73 65 72 0e e1 34 f3 32 f5 bc e1 c...user..4.2...
-e1b6: 78 ee ca f3 40 e1 x...@.
-e1ca: a9 e1 ff 03 64 75 70 00 d4 e1 ....dup...
-e1de: cd e1 ff 04 3f 64 75 70 e8 e1 ....?dup..
-e1f0: e1 e1 ff 04 64 72 6f 70 fa e1 ....drop..
-e200: f3 e1 ff 04 73 77 61 70 0a e2 ....swap..
-e216: 03 e2 ff 04 6f 76 65 72 20 e2 ....over .
-e22e: 19 e2 ff 03 72 6f 74 00 38 e2 ....rot.8.
-e24a: 31 e2 ff 03 6e 69 70 00 54 e2 1...nip.T.
-e25a: 4d e2 ff 04 74 75 63 6b 0e e1 08 e2 1e e2 40 e1 M...tuck......@.
-e26a: 5d e2 ff 02 3e 72 72 e2 ]...>rr.
-e27a: 6d e2 ff 02 72 3e 82 e2 m...r>..
-e28e: 7d e2 ff 02 72 40 96 e2 ....r@..
-e2a2: 91 e2 ff 03 32 3e 72 00 ac e2 ....2>r...
-e2b8: a5 e2 ff 03 32 72 3e 00 c2 e2 ....2r>...
-e2d4: bb e2 ff 03 73 70 40 00 de e2 ....sp@...
-e2ea: d7 e2 ff 03 73 70 21 00 f4 e2 ....sp!...
-e2fc: ed e2 ff 03 72 70 40 00 06 e3 ....rp@...
-e312: ff e2 ff 03 72 70 21 00 1c e3 ....rp!...
-e324: 15 e3 ff 01 40 00 2c e3 ....@.,.
-e332: 27 e3 ff 01 21 00 3a e3 '...!.:.
-e344: 35 e3 ff 02 63 40 4c e3 5...c@L.
-e352: 47 e3 ff 02 63 21 5a e3 G...c!Z.
-e366: 55 e3 ff 01 2b 00 6e e3 U...+.n.
-e374: 69 e3 ff 02 2b 21 7c e3 i...+!..
-e386: 77 e3 ff 02 6d 2b 8e e3 w...m+..
-e39c: 89 e3 ff 01 2d 00 a4 e3 ....-...
-e3ae: 9f e3 ff 03 61 6e 64 00 b8 e3 ....and...
-e3be: b1 e3 ff 02 6f 72 c6 e3 ....or..
-e3cc: c1 e3 ff 03 78 6f 72 00 d6 e3 ....xor...
-e3dc: cf e3 ff 06 69 6e 76 65 72 74 e8 e3 ....invert..
-e3ee: df e3 ff 06 6e 65 67 61 74 65 fa e3 ....negate..
-e402: f1 e3 ff 02 31 2b 0a e4 ....1+..
-e410: 05 e4 ff 02 31 2d 18 e4 ....1-..
-e41e: 13 e4 ff 02 3e 3c 26 e4 ....><&.
-e42c: 21 e4 ff 02 32 2a 34 e4 !...2*4.
-e43a: 2f e4 ff 02 32 2f 42 e4 /...2/B.
-e448: 3d e4 ff 06 6c 73 68 69 66 74 54 e4 =...lshiftT.
-e468: 4b e4 ff 06 72 73 68 69 66 74 74 e4 K...rshiftt.
-e48a: 6b e4 ff 02 30 3d 92 e4 k...0=..
-e49a: 8d e4 ff 02 30 3c a2 e4 ....0<..
-e4ac: 9d e4 ff 01 3d 00 b4 e4 ....=...
-e4c0: af e4 ff 02 3c 3e 0e e1 b2 e4 90 e4 40 e1 c3 e4 ....<>......@...
-e4d0: ff 01 3c 00 d6 e4 ..<...
-e4e2: d1 e4 ff 01 3e 00 0e e1 08 e2 d4 e4 40 e1 e5 e4 ....>.......@...
-e4f2: ff 02 75 3c f8 e4 ..u<..
-e500: f3 e4 ff 02 75 3e 0e e1 08 e2 f6 e4 40 e1 03 e5 ....u>......@...
-e510: ff 06 62 72 61 6e 63 68 1a e5 ..branch..
-e520: 11 e5 ff 07 3f 62 72 61 6e 63 68 00 2e e5 ....?branch...
-e53a: 3c e5 <.
-e556: 58 e5 X.
-e56a: 6c e5 l.
-e580: 23 e5 ff 01 69 00 88 e5 #...i...
-e596: 83 e5 ff 01 6a 00 9e e5 ....j...
-e5ae: 99 e5 ff 06 75 6e 6c 6f 6f 70 ba e5 ....unloop..
-e5c2: b1 e5 ff 03 75 6d 2a 00 cc e5 ....um*...
-e5e8: c5 e5 ff 06 75 6d 2f 6d 6f 64 f4 e5 ....um/mod..
-e624: eb e5 ff 04 66 69 6c 6c 2e e6 ....fill..
-e646: 27 e6 ff 05 63 6d 6f 76 65 00 52 e6 '...cmove.R.
-e66a: 49 e6 ff 06 63 6d 6f 76 65 3e 76 e6 I...cmove>v.
-e694: 6d e6 ff 05 63 73 6b 69 70 00 0e e1 70 e2 d2 e1 m...cskip...p...
-e6a4: 2c e5 16 00 1e e2 4a e3 94 e2 b2 e4 2c e5 0a 00 ,.....J.....,...
-e6b4: e4 fb d8 ee 18 e5 e8 ff 80 e2 f8 e1 40 e1 97 e6 ............@...
-e6c4: ff 05 63 73 63 61 6e 00 0e e1 70 e2 1e e2 d2 e1 ..cscan...p.....
-e6d4: 4a e3 94 e2 b2 e4 90 e4 2c e5 18 00 08 e2 16 e4 J.......,.......
-e6e4: 08 e2 1e e2 a0 e4 90 e4 2c e5 08 00 08 e4 18 e5 ........,.......
-e6f4: de ff 52 e2 1e e2 a2 e3 80 e2 f8 e1 40 e1 c5 e6 ..R.........@...
-e704: ff 02 73 3d 0a e7 ..s=..
-e72a: 05 e7 ff 05 61 6c 69 67 6e 00 0e e1 a0 ee e4 fb ....align.......
-e73a: b6 e3 b2 ee 40 e1 2d e7 ff 07 61 6c 69 67 6e 65 ....@.-...aligne
-e74a: 64 00 0e e1 d2 e1 e4 fb b6 e3 6c e3 40 e1 43 e7 d.........l.@.C.
-e75a: ff 05 63 65 6c 6c 2b 00 64 e7 ..cell+.d.
-e76a: 5b e7 ff 05 63 65 6c 6c 73 00 34 e4 6d e7 ff 05 [...cells.4.m...
-e77a: 3e 62 6f 64 79 00 64 e7 79 e7 ff 03 75 70 40 00 >bod..d.....up@.
-e78a: 8c e7 ..
-e798: 85 e7 ff 03 75 70 21 00 a2 e7 ....up!...
-e7aa: 9b e7 ff 02 63 72 0e e1 2a e1 0d 00 30 fd 2a e1 ....cr..*...0.*.
-e7ba: 0a 00 30 fd 40 e1 ad e7 ff 05 73 70 61 63 65 00 ..0.@.....space.
-e7ca: 0e e1 2e ea 30 fd 40 e1 c3 e7 ff 06 73 70 61 63 ....0.@.....spac
-e7da: 65 73 0e e1 da fb 0c ec d2 e1 2c e5 0a 00 ca e7 es........,.....
-e7ea: 16 e4 18 e5 f4 ff f8 e1 40 e1 d5 e7 ff 04 75 6d ........@.....um
-e7fa: 69 6e 0e e1 4e ec 06 e5 2c e5 04 00 08 e2 f8 e1 in..N...,.......
-e80a: 40 e1 f7 e7 ff 04 75 6d 61 78 0e e1 4e ec f6 e4 @.....umax..N...
-e81a: 2c e5 04 00 08 e2 f8 e1 40 e1 0f e8 ff 06 61 63 ,.......@.....ac
-e82a: 63 65 70 74 0e e1 1e e2 6c e3 16 e4 1e e2 52 fd cept....l.....R.
-e83a: d2 e1 b0 e8 90 e4 2c e5 52 00 d2 e1 2a e1 08 00 ......,.R...*...
-e84a: b2 e4 2c e5 26 00 f8 e1 36 e2 4e ec e8 e4 70 e2 ..,.&...6.N...p.
-e85a: 36 e2 36 e2 80 e2 2c e5 0e 00 a0 e8 16 e4 70 e2 6.6...,.......p.
-e86a: 1e e2 80 e2 14 e8 18 e5 1e 00 d2 e1 2e ea d4 e4 ................
-e87a: 2c e5 06 00 f8 e1 2e ea d2 e1 30 fd 1e e2 58 e3 ,.........0...X.
-e88a: 08 e4 1e e2 fc e7 18 e5 a6 ff f8 e1 52 e2 08 e2 ............R...
-e89a: a2 e3 b0 e7 40 e1 0e e1 2a e1 08 00 d2 e1 30 fd ....@...*.....0.
-e8aa: ca e7 30 fd 40 e1 0e e1 d2 e1 2a e1 0d 00 b2 e4 ..0.@.....*.....
-e8ba: 08 e2 2a e1 0a 00 b2 e4 c4 e3 40 e1 27 e8 ff 04 ..*.......@.'...
-e8ca: 74 79 70 65 0e e1 42 ee 42 f6 2c e5 0e 00 3a e5 t.pe..B.B.,...:.
-e8da: 86 e5 4a e3 30 fd 56 e5 f8 ff 40 e1 c9 e8 ff 06 ..J.0.V...@.....
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-e90a: 18 00 03 e9 ff 04 62 61 73 65 bc e1 0c 00 0f e9 ......base......
-e91a: ff 05 73 74 61 74 65 00 7a e1 82 1c 1b e9 ff 02 ..state.........
-e92a: 64 70 7a e1 1e 1c 29 e9 ff 0b 67 65 74 2d 63 75 dp....)...get-cu
-e93a: 72 72 65 6e 74 00 0e e1 2a e1 24 1c 2a e3 40 e1 rrent...*.$.*.@.
-e94a: 33 e9 ff 03 68 6c 64 00 7a e1 84 1c 4d e9 ff 02 3...hld.....M...
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-e98a: ff 05 61 6c 6c 6f 74 00 0e e1 2c e9 7a e3 40 e1 ..allot...,...@.
-e99a: 8b e9 ff 03 70 61 64 00 0e e1 6a ee 2a e1 28 00 ....pad...j.*.(.
-e9aa: 6c e3 40 e1 9d e9 ff 03 6c 70 30 00 7a e1 ec 1c l.@.....lp0.....
-e9ba: b1 e9 ff 03 72 70 30 00 7a e1 8c 1d bd e9 ff 03 ....rp0.........
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-e9fa: ff 0a 73 6f 75 72 63 65 2d 74 69 62 0e e1 18 ea ..source-tib....
-ea0a: 24 ea 2a e3 40 e1 fb e9 ff 03 74 69 62 00 7a e1 $.*.@.....tib...
-ea1a: 90 1c 13 ea ff 04 23 74 69 62 7a e1 8e 1c 1f ea ......#tib......
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-ea3a: 70 65 72 00 0e e1 d2 e1 2a e1 61 00 2a e1 7b 00 per.....*.a.*...
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-ea5a: ff 05 75 69 6e 69 74 00 86 e1 02 00 a4 fa 16 fb ..uinit.........
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-ea7a: 00 00 00 00 00 00 9c f8 8c 1d 00 44 5a 1c 26 1c ...........DZ.&.
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-eaea: 40 e1 df ea ff 07 64 6e 65 67 61 74 65 00 0e e1 @.....dnegate...
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-eb0a: ff 08 3f 64 6e 65 67 61 74 65 0e e1 a0 e4 2c e5 ..?dnegate....,.
-eb1a: 04 00 f8 ea 40 e1 0b eb ff 04 64 61 62 73 0e e1 ....@.....dabs..
-eb2a: d2 e1 14 eb 40 e1 23 eb ff 02 6d 2a 0e e1 4e ec ....@.#...m*..N.
-eb3a: d4 e3 70 e2 08 e2 e4 ea 08 e2 e4 ea ca e5 80 e2 ..p.............
-eb4a: 14 eb 40 e1 33 eb ff 06 73 6d 2f 72 65 6d 0e e1 ..@.3...sm/rem..
-eb5a: 4e ec d4 e3 70 e2 1e e2 70 e2 e4 ea 70 e2 28 eb N...p...p...p.(.
-eb6a: 80 e2 f2 e5 08 e2 80 e2 d0 ea 08 e2 80 e2 d0 ea ................
-eb7a: 40 e1 51 eb ff 06 66 6d 2f 6d 6f 64 0e e1 d2 e1 @.Q...fm/mod....
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-ec4a: 32 64 75 70 0e e1 1e e2 1e e2 40 e1 49 ec ff 05 2dup......@.I...
-ec5a: 32 73 77 61 70 00 0e e1 36 e2 70 e2 36 e2 80 e2 2swap...6.p.6...
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-ec7a: 08 e4 08 e2 4a e3 40 e1 6f ec ff 05 69 74 79 70 ....J.@.o...it.p
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-ecaa: 95 ec fe 02 73 22 0e e1 2a e1 22 00 f2 ee 22 e9 ....s"..*."...".
-ecba: 2a e3 2c e5 04 00 e0 ec 40 e1 ad ec fe 02 2e 22 *.,.....@......"
-ecca: 0e e1 b0 ec 32 f5 8c ec 40 e1 c7 ec fe 08 73 6c ....2...@.....sl
-ecda: 69 74 65 72 61 6c 0e e1 32 f5 9a ec 38 fb 40 e1 iteral..2...8.@.
-ecea: d7 ec fe 08 32 6c 69 74 65 72 61 6c 0e e1 08 e2 ....2literal....
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-ed1a: 6f 64 0e e1 70 e2 da fb 94 e2 f2 e5 80 e2 08 e2 od..p...........
-ed2a: 70 e2 f2 e5 80 e2 40 e1 15 ed ff 03 75 64 2a 00 p.....@.....ud*.
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-ed4a: 36 e2 6c e3 40 e1 35 ed ff 04 68 6f 6c 64 0e e1 6.l.@.5...hold..
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-fafe: 6e 75 6d 00 86 e1 cc fc f6 ec f6 ec f9 fa ff 07 num.............
-fb0e: 72 65 63 3a 6e 75 6d 00 0e e1 a0 f0 2c e5 12 00 rec:num.....,...
-fb1e: e4 fb b2 e4 2c e5 06 00 ee fa 40 e1 02 fb 40 e1 ....,.....@...@.
-fb2e: 88 fa 40 e1 0d fb fe 02 73 2c 0e e1 d2 e1 70 e2 ..@.....s,....p.
-fb3e: 8a ee a0 ee 94 e2 5a e0 80 e2 b2 ee 34 e7 40 e1 ......Z.....4.@.
-fb4e: 35 fb ff 07 63 6f 6d 70 61 72 65 00 0e e1 36 e2 5...compare...6.
-fb5e: 1e e2 c6 e4 2c e5 0a 00 f8 e1 3e ec f8 fb 40 e1 ....,.....>...@.
-fb6e: 08 e7 40 e1 51 fb ff 0f 73 65 61 72 63 68 2d 77 ..@.Q...search-w
-fb7e: 6f 72 64 6c 69 73 74 00 0e e1 70 e2 da fb 2a e1 ordlist...p...*.
-fb8e: b0 fb 80 e2 12 f7 d2 e1 90 e4 2c e5 0a 00 3e ec ..........,...>.
-fb9e: f8 e1 da fb 40 e1 d2 e1 32 ef 08 e2 50 ef 58 ef ....@...2...P.X.
-fbae: 40 e1 0e e1 70 e2 f8 e1 4e ec 94 e2 48 f7 5a fb @...p...N...H.Z.
-fbbe: 2c e5 0c 00 80 e2 f8 e1 da fb f8 fb 40 e1 3e ec ,...........@.>.
-fbce: 80 e2 da fb 40 e1 75 fb ff 01 30 00 7a e1 00 00 ....@.u...0.....
-fbde: d7 fb ff 01 31 00 7a e1 01 00 e1 fb ff 01 32 00 ....1.........2.
-fbee: 7a e1 02 00 eb fb ff 02 2d 31 7a e1 ff ff f5 fb ........-1......
-fbfe: ff 07 28 64 65 66 65 72 29 00 0e e1 34 f3 ca f3 ..(defer)...4...
-fc0e: 32 f5 14 fc 40 e1 30 40 92 e1 d2 e1 68 f4 06 ed 2...@.0@....h...
-fc1e: 22 e1 22 e1 40 e1 ff fb ff 07 28 76 61 6c 75 65 ".".@.....(value
-fc2e: 29 00 0e e1 34 f3 ca f3 32 f5 3c fc 40 e1 30 40 )...4...2.<.@.0@
-fc3e: 92 e1 d2 e1 68 f4 06 ed 22 e1 40 e1 27 fc ff 07 ....h...".@.'...
-fc4e: 74 75 72 6e 6b 65 79 00 14 fc 1c 1c dc fc f0 fc turnke..........
-fc5e: 4d fc fe 02 74 6f 0e e1 90 f2 80 e7 22 e9 2a e3 M...to......".*.
-fc6e: 2c e5 16 00 32 f5 7a fc 78 ee 40 e1 0e e1 80 e2 ,...2...x.@.....
-fc7e: d2 e1 68 f4 70 e2 06 ed d2 e1 68 f4 68 f4 06 ed ..h.p.....h.h...
-fc8e: 22 e1 40 e1 61 fc ff 06 64 65 66 65 72 40 0e e1 ".@.a...defer@..
-fc9e: 80 e7 d2 e1 68 f4 06 ed 22 e1 40 e1 95 fc ff 06 ....h...".@.....
-fcae: 64 65 66 65 72 21 0e e1 80 e7 d2 e1 68 f4 68 f4 defer!......h.h.
-fcbe: 06 ed 22 e1 40 e1 ad fc ff 04 6e 6f 6f 70 0e e1 ..".@.....noop..
-fcce: 40 e1 c7 fc ff 07 52 64 65 66 65 72 40 00 0e e1 @.....Rdefer@...
-fcde: 06 ed 2a e3 40 e1 d3 fc ff 07 52 64 65 66 65 72 ..*.@.....Rdefer
-fcee: 21 00 0e e1 06 ed 38 e3 40 e1 e7 fc ff 07 55 64 !.....8.@.....Ud
-fcfe: 65 66 65 72 40 00 0e e1 06 ed 8a e7 6c e3 2a e3 efer@.......l.*.
-fd0e: 40 e1 fb fc ff 07 55 64 65 66 65 72 21 00 0e e1 @.....Udefer!...
-fd1e: 06 ed 8a e7 6c e3 38 e3 40 e1 13 fd ff 04 65 6d ....l.8.@.....em
-fd2e: 69 74 14 fc 0e 00 04 fd 1c fd 2b fd ff 05 65 6d it........+...em
-fd3e: 69 74 3f 00 14 fc 10 00 04 fd 1c fd 3b fd ff 03 it?.........;...
-fd4e: 6b 65 79 00 14 fc 12 00 04 fd 1c fd 4d fd ff 04 ke..........M...
-fd5e: 6b 65 79 3f 14 fc 14 00 04 fd 1c fd 5d fd ff 02 ke.?........]...
-fd6e: 2e 73 0e e1 d8 f6 f6 ed ca e7 d8 f6 da fb 42 f6 .s............B.
-fd7e: 2c e5 0e 00 3a e5 86 e5 54 ee f6 ed 56 e5 f8 ff ,...:...T...V...
-fd8e: 40 e1 6d fd ff 03 73 72 40 00 9a fd @.m...sr@...
-fda6: 93 fd ff 02 74 78 0e e1 42 fd 2c e5 fc ff 2a e1 ....tx..B.,...*.
-fdb6: ce 05 58 e3 40 e1 a9 fd ff 03 74 78 3f 00 0e e1 ..X.@.....tx?...
-fdc6: 68 f8 2a e1 02 00 d2 e1 2a e1 dc 05 4a e3 b6 e3 h.*.....*...J...
-fdd6: b2 e4 40 e1 bf fd ff 02 72 78 0e e1 62 fd 2c e5 ..@.....rx..b.,.
-fde6: fc ff 2a e1 cc 05 4a e3 40 e1 dd fd ff 03 72 78 ..*...J.@.....rx
-fdf6: 3f 00 0e e1 68 f8 2a e1 01 00 d2 e1 2a e1 dc 05 ?...h.*.....*...
-fe06: 4a e3 b6 e3 b2 e4 40 e1 f3 fd ff 06 2b 75 73 61 J.....@.....+usa
-fe16: 72 74 1a fe rt..
-fffe: 12 f8 ..
-
-
-Program Info:
-Include Paths: .
- ../../msp430/devices/msp430fr5969
- ../../msp430
- ../../common
- ../..
- /home/mt/share/naken_asm/include
- Instructions: 441
- Code Bytes: 1076
- Data Bytes: 6885
- Low Address: 1c00 (7168)
- High Address: ffff (65535)
-
diff --git a/amforth-6.5/appl/launchpad430/readme.txt b/amforth-6.5/appl/launchpad430/readme.txt
deleted file mode 100644
index e848652..0000000
--- a/amforth-6.5/appl/launchpad430/readme.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Some notes on the amforth on the TI Stellaris Launchpad 430
-
- - not very structured so far -
-
-It is a merge of camelforth 0.5a by Brad Rodriguez. His code
-is highly modified and restructured. This is possible since
-both forth's are very close to each other. The naken_asm
-from Michael Kohn is used to create the hex file (any recent
-version should do). The avrdude pendant is the mspdebug
-utility from the default repositories. For some devices the
-tilib plugin from TI is necessary. More Details and how
-to handle the devices are in the documentation (Cookbook).
-
-The primary goal is to explore the possibilities, the atmega
-code base leads whenever it makes sense. A remote vision is to
-have a single code base for all higer level code and the tools.
-
-The MSP430 G2553 runs at 8MHz. The serial terminal
-uses 9600/8N1 without flow control.
-
-The MSP430 F5529 and the FR5969 run at 8MHz, the terminal
-uses 115200 8N1 without flow control.
-
-The major difference to the AVR8 world is that the MSP430
-requires an explicit SAVE command to keep the dictionary
-intact during reboots.
-
-Todo (major only)
-- identify library and example code that works
- on both systems without modification. create
- portability libraries (csetb+cclrb vs portpin:)
diff --git a/amforth-6.5/appl/launchpad430/words/applturnkey.asm b/amforth-6.5/appl/launchpad430/words/applturnkey.asm
deleted file mode 100644
index 807741f..0000000
--- a/amforth-6.5/appl/launchpad430/words/applturnkey.asm
+++ /dev/null
@@ -1,37 +0,0 @@
-; ( -- ) System
-; R( -- )
-; application specific turnkey action
-
-.if cpu_msp430==1
- HEADER(XT_APPLTURNKEY,11,"applturnkey",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_APPLTURNKEY:
- .dw $ff0b
- .db "applturnkey",0
- .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
-XT_APPLTURNKEY:
- .dw DO_COLON
-PFA_APPLTURNKEY:
-.if WANT_INTERRUPTS==1
- .dw XT_INTON
-.endif
-.endif
- .dw XT_USART
- .dw XT_DOT_VER
- .dw XT_SPACE
- .dw XT_F_CPU
- .dw XT_DOLITERAL
- .dw 1000
- .dw XT_UMSLASHMOD
- .dw XT_NIP
- .dw XT_DECIMAL
- .dw XT_DOT
- .dw XT_DOSLITERAL
- .db 3
- .db "kHz"
- .align 16
- .dw XT_ITYPE
- .dw XT_EXIT
diff --git a/amforth-6.5/appl/launchpad430/words/dump.asm b/amforth-6.5/appl/launchpad430/words/dump.asm
deleted file mode 100644
index 6cc9095..0000000
--- a/amforth-6.5/appl/launchpad430/words/dump.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-;X DUMP adr n -- dump memory
-; OVER + SWAP DO
-; CR I 4 U.R SPACE SPACE
-; I $10 + I DO I C@ 3 U.R LOOP SPACE SPACE
-; I $10 + I DO I C@ $7F AND $7E MIN BL MAX EMIT LOOP
-; 10 +LOOP ;
- HEADER(DUMP,4,"dump",DOCOLON)
- DW XT_OVER,XT_PLUS,XT_SWAP,XT_DODO
-LDUMP1: DW XT_CR,XT_I,XT_DOLITERAL,4,XT_UDOTR,XT_SPACE,XT_SPACE
- DW XT_I,XT_DOLITERAL,10h,XT_PLUS,XT_I,XT_DODO
-LDUMP2: DW XT_I,XT_CFETCH,XT_DOLITERAL,3,XT_UDOTR,XT_DOLOOP
- DEST(LDUMP2)
- DW XT_SPACE,XT_SPACE
- DW XT_I,XT_DOLITERAL,10h,XT_PLUS,XT_I,XT_DODO
-LDUMP3: DW XT_I,XT_CFETCH,XT_DOLITERAL,7Fh,XT_AND,XT_DOLITERAL,7Eh,XT_MIN,XT_BL,XT_MAX,XT_EMIT,XT_DOLOOP
- DEST(LDUMP3)
- DW XT_DOLITERAL,10h,XT_DOPLUSLOOP
- DEST(LDUMP1)
- DW XT_EXIT
diff --git a/amforth-6.5/appl/msp-build.xml b/amforth-6.5/appl/msp-build.xml
deleted file mode 100644
index 29a77c3..0000000
--- a/amforth-6.5/appl/msp-build.xml
+++ /dev/null
@@ -1,40 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="Amforth for MSP 430 Tools" basedir="." default="Help">
- <import file="common-build.xml"/>
- <macrodef name="mspdebug">
- <attribute name="binary" default="mspdebug" />
- <attribute name="projectname" default="undefined"/>
- <attribute name="mcu" default="undefined"/>
- <attribute name="amforth.core" default="../.."/>
- <attribute name="programmer" default=""/>
- <sequential>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="@{programmer} 'erase all'"/>
- </exec>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="@{programmer} 'prog @{projectname}.hex'"/>
- </exec>
- </sequential>
- </macrodef>
-
- <macrodef name="nakenasm">
- <attribute name="binary" default="naken_asm" />
- <attribute name="projectname" default="undefined"/>
- <attribute name="mcu" default="undefined"/>
- <attribute name="amforth.core" default="../.."/>
- <sequential>
- <echo>Producing Hexfiles for @{mcu}</echo>
- <exec executable="@{binary}" spawn="false" failonerror="true">
- <arg line="-I @{amforth.core}/msp430/devices/@{mcu}"/>
- <arg line="-I @{amforth.core}/msp430"/>
- <arg line="-I @{amforth.core}/common"/>
- <arg line="-I @{amforth.core}"/>
- <arg line="-l"/>
- <arg line="-o @{projectname}.hex"/>
- <arg line="@{projectname}.asm"/>
- </exec>
- </sequential>
- </macrodef>
-
-
-</project>
diff --git a/amforth-6.5/appl/programmer.properties b/amforth-6.5/appl/programmer.properties
deleted file mode 100644
index accb97a..0000000
--- a/amforth-6.5/appl/programmer.properties
+++ /dev/null
@@ -1,19 +0,0 @@
-# Definitions of available programmers
-avr.programmer.dragonport=usb
-avr.programmer.dragon=dragon_jtag
-
-avr.programmer.mysmartusbport=/dev/ttyUSB2
-avr.programmer.mysmartusb=avr911
-
-avr.programmer.stk200port=/dev/parport0
-avr.programmer.stk200=stk200
-
-avr.programmer.avrisp2port=usb
-# avr.programmer.avrisp2=avrisp2
-avr.programmer.avrisp2=avrispmkII
-
-avr.programmer.jtag1=jtag1
-avr.programmer.jtag1port=/dev/ttyUSB2
-
-avr.programmer.avr109port=/dev/ttyUSB1
-avr.programmer.avr109=avr109
diff --git a/amforth-6.5/appl/template/build.xml b/amforth-6.5/appl/template/build.xml
deleted file mode 100644
index b4a5d70..0000000
--- a/amforth-6.5/appl/template/build.xml
+++ /dev/null
@@ -1,21 +0,0 @@
-<!-- make multiple targets with antelope -->
-<project name="Template Project" basedir="." default="Help">
- <import file="../avr-build.xml"/>
-
- <target name="template.hex" depends="build-info" description="Hexfiles for Template">
- <avrasm2 projectname="template" mcu="atmega1284p"/>
- </target>
-
- <target name="template" depends="template.hex" description="Template @ Template mHz">
- <echo>Uploading Hexfiles for Template</echo>
- <avrdude
- type="dragon"
- mcu="m1284p"
- flashfile="template.hex"
- eepromfile="template.eep.hex"
- />
- </target>
- <target name="compile" depends="template.hex">
- </target>
-
-</project>
diff --git a/amforth-6.5/appl/template/dict_appl.inc b/amforth-6.5/appl/template/dict_appl.inc
deleted file mode 100644
index 6a023ee..0000000
--- a/amforth-6.5/appl/template/dict_appl.inc
+++ /dev/null
@@ -1,32 +0,0 @@
-
-; This file contains definitions which are either
-; optional or application specific. They are placed
-; in the RWW flash section.
-
-; The file dict/compiler2.inc contains a number of
-; non-essential words with compiler functionality.
-; It is recoomended but not strictly necessairy
-; to include it. It is already included by default
-; on atmegas with 8k boot loader sections, but it is
-; safe to include this file twice.
-
-.include "dict/compiler2.inc"
-
-; turnkey is always needed and application specific
-.include "words/applturnkey.asm"
-
-; the command .s has many flavors. the one in the
-; core directory prints the TOS on the *left* hand side.
-; lib/tools/dot-s.frt has a .s for the opposite.
-.include "words/dot-s.asm"
-
-; print the date and time the amforth hex files are created
-; comment the next line if not needed. Depends on a make/ant
-; rule to create the actual include file from a template.
-.include "words/build-info.asm"
-
-; now add words which are either not included by default but
-; part of amforth (e.g. words for counted strings) or add
-; your own ones (from the words directory in this one)
-.include "words/place.asm"
-.include "words/word.asm"
diff --git a/amforth-6.5/appl/template/dict_appl_core.inc b/amforth-6.5/appl/template/dict_appl_core.inc
deleted file mode 100644
index 1d12fdc..0000000
--- a/amforth-6.5/appl/template/dict_appl_core.inc
+++ /dev/null
@@ -1,5 +0,0 @@
-; This file contains additional words that are placed
-; in the NRWW flash section. There is a default file
-; called dict/nrww.inc which contains all essential
-; words which is included automatically. There is usually
-; not much space left.
diff --git a/amforth-6.5/appl/template/makefile b/amforth-6.5/appl/template/makefile
deleted file mode 100644
index 22ba346..0000000
--- a/amforth-6.5/appl/template/makefile
+++ /dev/null
@@ -1,78 +0,0 @@
-# simple makefile for building the
-# template project.
-
-SHELL=/bin/bash
-
-# --- edit these values ------------------------------------
-# Name of your application (useful, if you rename template.asm)
-TARGET=template
-
-# versions before 2.1 may produce some warnings
-# but should produce a running system. You should
-# _always_ use the trunk.
-
-#AMFORTH=../../releases/3.6
-AMFORTH=../..
-
-# the MCU should be identical to the device
-MCU=atmega328p
-# set the fuses according to your MCU
-LFUSE=0xnn
-HFUSE=0xnn
-# some MCU have this one, see write-fuses target below
-EFUSE=0xnn
-
-# serial port
-CONSOLE=/dev/ttyUSB0
-
-# directories
-DIR_ATMEL=../../avr8/Atmel
-
-# programms / flags
-USB=-c avr911 -P /dev/ttyUSB3
-PP=-c stk200 -P /dev/parport0
-JTAG=-c jtag2 -P /dev/ttyUSB2
-BURNER=$(USB)
-AVRDUDE=avrdude
-AVRDUDE_FLAGS=-q $(BURNER) -p $(MCU)
-
-#AVRASM=wine $(DIR_ATMEL)/avrasm2.exe -I $(DIR_ATMEL)/Appnotes2
-AVRASM=avra -I $(DIR_ATMEL)/Appnotes2
-
-# ----------------------------------------------------------
-
-INCLUDE=-I $(AMFORTH)/avr8/devices/$(MCU) -I $(AMFORTH)/avr8 -I $(AMFORTH)/common
-
-default: $(TARGET).hex
-
-erase:
- $(AVRDUDE) $(AVRDUDE_FLAGS) -e
-
-install: $(TARGET).hex
- $(AVRDUDE) $(AVRDUDE_FLAGS) -e -U flash:w:$(TARGET).hex:i -U eeprom:w:$(TARGET).eep.hex:i
-
-$(TARGET).hex: $(TARGET).asm words/*.asm $(AMFORTH)/common/words/*.asm $(AMFORTH)/avr8/words/*.asm $(AMFORTH)/avr8/devices/$(MCU)/*.asm
- ( TSTAMP=$$(date +"%Y-%m-%dT%H:%M:%S"); \
- TSTAMPLEN=$${#TSTAMP}; \
- echo "($$TSTAMPLEN) $$TSTAMP"; \
- sed -e "s/@TSTAMPLEN@/$$TSTAMPLEN/g" -e "s/@TSTAMP@/$$TSTAMP/g" $(AMFORTH)/common/words/build-info.tmpl > words/build-info.asm )
- $(AVRASM) $(INCLUDE) -fI -e $(TARGET).eep.hex -l $(TARGET).lst $(TARGET).asm
-
-$(TARGET).back:
- $(AVRDUDE) $(AVRDUDE_FLAGS) -U flash:r:$(TARGET).hex:i -U eeprom:r:$(TARGET).eep.hex:i
-
-clean:
- rm -f $(TARGET).hex
- rm -f $(TARGET).eep.hex
- rm -f $(TARGET).lst
- rm -f $(TARGET).map
- rm -f $(TARGET).cof
- rm -f $(TARGET).obj
-
-read-fuse:
- $(AVRDUDE) $(AVRDUDE_FLAGS) -U hfuse:r:-:h -U lfuse:r:-:h -U lock:r:-:h
- # $(AVRDUDE) $(AVRDUDE_FLAGS) -U hfuse:r:-:h -U lfuse:r:-:h -U efuse:r:-:h -U lock:r:-:h
-
-write-fuse:
- $(AVRDUDE) $(AVRDUDE_FLAGS) -U hfuse:w:$(HFUSE):m -U lfuse:w:$(LFUSE):m
-# $(AVRDUDE) $(AVRDUDE_FLAGS) -U efuse:w:$(EFUSE):m -U hfuse:w:$(HFUSE):m -U lfuse:w:$(LFUSE):m
diff --git a/amforth-6.5/appl/template/template.asm b/amforth-6.5/appl/template/template.asm
deleted file mode 100644
index 53de860..0000000
--- a/amforth-6.5/appl/template/template.asm
+++ /dev/null
@@ -1,124 +0,0 @@
-; This is a template for an amforth project.
-;
-; The order of the entries (esp the include order) must not be
-; changed since it is very important that the settings are in the
-; right order
-;
-; note: .set is like a variable, .equ is like a constant
-;
-; first is include the preamble. It contains macro definitions,
-; default settings and mcu specific stuff like register names.
-; The files included with it depend on the -I order of the
-; assembler.
-
-.include "preamble.inc"
-
-; The amforth code is split into two segments, one starting
-; at address 0 (the RWW area) and one starting in
-; the NRWW region. The latter part cannot be changed
-; at runtime so it contains most of the core system
-; that would never be changed. If unsure what it
-; means, leave it as it is. This address may be
-; adjusted to give room for other code fragments (e.g.
-; bootloaders). The amforth code will start here and may
-; occupy all space until flash-end.
-
-; If you want leave out the first 512 bytes of the NRWW section
-; for e.g. a bootloader change the line to
-; .equ AMFORTH_RO_SEG = NRWW_START_ADDR+512/2
-; note the /2 since the flash is 16bit per address
-; default is the whole NRWW section
-; .equ AMFORTH_RO_SEG = NRWW_START_ADDR
-
-.set AMFORTH_RO_SEG = NRWW_START_ADDR
-
-; amforth needs two essential parameters: CPU clock
-; and command terminal line.
-; cpu clock in hertz, 1MHz is factory default
-.equ F_CPU = 20000000
-
-; terminal settings
-; check http://amforth.sourceforge.net/TG/recipes/Usart.html
-; for further information
-
-; serial line settings. The defaults are set in avr8/preamble.inc.
-; You should not change that file but use your own settings *here*
-; since it may get changed in future versions of amforth.
-;.set BAUD=38400
-;.set BAUD_MAXERROR=10
-;.set WANT_ISR_RX = 1 ; interrupt driven receive
-;.set WANT_ISR_TX = 0 ; send slowly but with less code space
-
-; define which usart to use.
-.include "drivers/usart_0.asm"
-
-
-; now define your own options, if the settings from
-; the files included above are not ok. Use the .set
-; instruction, not the .equ. e.g.:
-;
-; .set WANT_XY = 1
-;
-; there are many options available. There are two
-; places where they are defined initially: core/macros.asm
-; and core/devices/<mcutype>/device.asm. Setting the value
-; to 1 enables the feature, setting to 0 disables it.
-; Most options are disabled by default. You should never
-; change the files mentioned above, setting the options here
-; is absolutly sufficient.
-
-; the dictionary search treats lowercase and uppercase
-; letters the same. Set to 0 if you do not want it
-.set WANT_IGNORECASE = 1
-
-
-; default settings as specified in core/macros.asm. Uncomment and
-; change them if necessary.
-
-; Size of the Terminal Input Buffer. This is the command line buffer.
-; .set TIBSIZE = $64 ; bytes; ANS94 needs at least 80 characters per line
-
-; The total USER size is the sum of the system internal USER area plus
-; the size specified here.
-; .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
-; addresses of various data segments.
-;.set rstackstart = RAMEND ; start address of return stack, grows downward
-;.set stackstart = RAMEND - 80 ; start address of data stack, grows downward
-; change only if you know what to you do
-
-; Total number of entries in the search order.
-; The standard requires 8 wordlists in the search oder, amforth uses
-; already one for itself. So you'll have 7 slots available.
-;.set NUMWORDLISTS = 8
-
-; Total number of recognizers.
-; There are 2 recognizers already in the core system. That makes
-; 2 for you.
-;.set NUMRECOGNIZERS = 4
-
-
-; DRIVER SECTION
-;
-; settings for 1wire interface, uncomment to use it
-;.equ OW_PORT=PORTB
-;.equ OW_BIT=4
-;.include "drivers/1wire.asm"
-
-; Interrupts.
-; globally enable (or disable) the interrupt support. It is
-; enabled by default and some other settings (usart receive)
-; depend on it. disabling it makes the inner interpreter
-; slightly faster and frees some code space.
-; .set WANT_INTERRUPTS = 1
-
-; reserve a RAM region to count each interrupt individually.
-; each interrupt of the given controller type gets a byte
-; that is incremented for each interrupt. Needs a lot of
-; RAM but may be useful for debugging interrupts or get rid
-; of random effects. disabled by default.
-; .set WANT_INTERRUPT_COUNTERS = 0
-
-
-; include the whole source tree.
-.include "amforth.asm"
diff --git a/amforth-6.5/appl/template/template.eep.hex b/amforth-6.5/appl/template/template.eep.hex
deleted file mode 100644
index 5d80eb7..0000000
--- a/amforth-6.5/appl/template/template.eep.hex
+++ /dev/null
@@ -1,7 +0,0 @@
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-:0800980004FA23FA13FA0C002C
-:00000001FF
diff --git a/amforth-6.5/appl/template/template.hex b/amforth-6.5/appl/template/template.hex
deleted file mode 100644
index e5a66ec..0000000
--- a/amforth-6.5/appl/template/template.hex
+++ /dev/null
@@ -1,632 +0,0 @@
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-:10FA3000BF93AF93E991F991A991B991092F082B3F
-:10FA400021F01D9111930197E1F7AF91BF91899139
-:10FA500099910C9404F005FF32737761700012FDE8
-:10FA600000F0F2F010F1F2F007F125F00AFF7265F4
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-:10FA80005A00ABF85FFD92F065F198F592F05CF1E9
-:10FA900025F00AFF736F757263652D74696236FD18
-:10FAA00000F059FD5FFD8AF025F003FF74696200E4
-:10FAB00049FD53F06F0104FF2374696255FD53F053
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-:10FAD000ACF2E0F070F3E0F092F078F5D5F078F564
-:10FAE000D5F0DAF269FD88F525F008FF696E6974D2
-:10FAF0002D72616D61FD00F045F07C0013F345F05F
-:10FB0000220015F266FD25F006FF626F756E6473C4
-:10FB100075FD00F0E0F0AEF1D5F025F003FF733E87
-:10FB2000640084FD00F0C2F032F125F005FF3E6272
-:10FB30006F6479008EFD41F20800326C6974657261
-:10FB4000616C96FD00F0D5F0A501A50125F001FF3F
-:10FB50003D009CFD00F0A4F12BF125F001FF3100E8
-:10FB6000A7FD53F0010001FF3200AEFD53F002008B
-:0AFB700002FF2D31B3FD53F0FFFF3B
-:00000001FF
diff --git a/amforth-6.5/appl/template/template.lst b/amforth-6.5/appl/template/template.lst
deleted file mode 100644
index 01fc431..0000000
--- a/amforth-6.5/appl/template/template.lst
+++ /dev/null
@@ -1,10414 +0,0 @@
-
-AVRASM ver. 2.1.52 template.asm Sun Apr 30 20:10:14 2017
-
-template.asm(14): Including file '../../avr8\preamble.inc'
-../../avr8\preamble.inc(2): Including file '../../avr8\macros.asm'
-../../avr8\macros.asm(6): Including file '../../avr8\user.inc'
-../../avr8\preamble.inc(6): Including file '../../avr8/devices/atmega1284p\device.asm'
-../../avr8/devices/atmega1284p\device.asm(5): Including file '../../avr8/Atmel/Appnotes2\m1284Pdef.inc'
-template.asm(53): Including file '../../avr8\drivers/usart_0.asm'
-../../avr8\drivers/usart_0.asm(32): Including file '../../avr8\drivers/usart_common.asm'
-../../avr8\drivers/usart_common.asm(11): Including file '../../avr8\drivers/usart-rx-buffer.asm'
-../../avr8\drivers/usart_common.asm(24): Including file '../../avr8\words/usart-tx-poll.asm'
-../../avr8\drivers/usart_common.asm(29): Including file '../../avr8\words/ubrr.asm'
-../../avr8\drivers/usart_common.asm(30): Including file '../../avr8\words/usart.asm'
-template.asm(124): Including file '../../avr8\amforth.asm'
-../../avr8\amforth.asm(12): Including file '../../avr8\drivers/generic-isr.asm'
-../../avr8\amforth.asm(14): Including file '../../avr8\dict/rww.inc'
-../../avr8\dict/rww.inc(1): Including file '../../avr8\words/mplus.asm'
-../../avr8\dict/rww.inc(2): Including file '../../common\words/ud-star.asm'
-../../avr8\dict/rww.inc(3): Including file '../../common\words/umax.asm'
-../../avr8\dict/rww.inc(4): Including file '../../common\words/umin.asm'
-../../avr8\dict/rww.inc(5): Including file '../../avr8\words/immediate-q.asm'
-../../avr8\dict/rww.inc(6): Including file '../../avr8\words/name2flags.asm'
-../../avr8\dict/rww.inc(9): Including file '../../avr8\dict/appl_8k.inc'
-../../avr8\dict/appl_8k.inc(1): Including file '../../avr8\dict/compiler1.inc'
-../../avr8\dict/compiler1.inc(2): Including file '../../avr8\words/newest.asm'
-../../avr8\dict/compiler1.inc(3): Including file '../../avr8\words/latest.asm'
-../../avr8\dict/compiler1.inc(4): Including file '../../common\words/do-create.asm'
-../../avr8\dict/compiler1.inc(5): Including file '../../common\words/backslash.asm'
-../../avr8\dict/compiler1.inc(6): Including file '../../common\words/l-paren.asm'
-../../avr8\dict/compiler1.inc(8): Including file '../../common\words/compile.asm'
-../../avr8\dict/compiler1.inc(9): Including file '../../avr8\words/comma.asm'
-../../avr8\dict/compiler1.inc(10): Including file '../../common\words/brackettick.asm'
-../../avr8\dict/compiler1.inc(13): Including file '../../common\words/literal.asm'
-../../avr8\dict/compiler1.inc(14): Including file '../../common\words/sliteral.asm'
-../../avr8\dict/compiler1.inc(15): Including file '../../avr8\words/g-mark.asm'
-../../avr8\dict/compiler1.inc(16): Including file '../../avr8\words/g-resolve.asm'
-../../avr8\dict/compiler1.inc(17): Including file '../../avr8\words/l_mark.asm'
-../../avr8\dict/compiler1.inc(18): Including file '../../avr8\words/l_resolve.asm'
-../../avr8\dict/compiler1.inc(20): Including file '../../common\words/ahead.asm'
-../../avr8\dict/compiler1.inc(21): Including file '../../common\words/if.asm'
-../../avr8\dict/compiler1.inc(22): Including file '../../common\words/else.asm'
-../../avr8\dict/compiler1.inc(23): Including file '../../common\words/then.asm'
-../../avr8\dict/compiler1.inc(24): Including file '../../common\words/begin.asm'
-../../avr8\dict/compiler1.inc(25): Including file '../../common\words/while.asm'
-../../avr8\dict/compiler1.inc(26): Including file '../../common\words/repeat.asm'
-../../avr8\dict/compiler1.inc(27): Including file '../../common\words/until.asm'
-../../avr8\dict/compiler1.inc(28): Including file '../../common\words/again.asm'
-../../avr8\dict/compiler1.inc(29): Including file '../../common\words/do.asm'
-../../avr8\dict/compiler1.inc(30): Including file '../../common\words/loop.asm'
-../../avr8\dict/compiler1.inc(31): Including file '../../common\words/plusloop.asm'
-../../avr8\dict/compiler1.inc(32): Including file '../../common\words/leave.asm'
-../../avr8\dict/compiler1.inc(33): Including file '../../common\words/qdo.asm'
-../../avr8\dict/compiler1.inc(34): Including file '../../common\words/endloop.asm'
-../../avr8\dict/compiler1.inc(36): Including file '../../common\words/l-from.asm'
-../../avr8\dict/compiler1.inc(37): Including file '../../common\words/to-l.asm'
-../../avr8\dict/compiler1.inc(38): Including file '../../avr8\words/lp0.asm'
-../../avr8\dict/compiler1.inc(39): Including file '../../avr8\words/lp.asm'
-../../avr8\dict/compiler1.inc(41): Including file '../../common\words/create.asm'
-../../avr8\dict/compiler1.inc(42): Including file '../../avr8\words/header.asm'
-../../avr8\dict/compiler1.inc(43): Including file '../../avr8\words/wlscope.asm'
-../../avr8\dict/compiler1.inc(44): Including file '../../common\words/reveal.asm'
-../../avr8\dict/compiler1.inc(45): Including file '../../avr8\words/does.asm'
-../../avr8\dict/compiler1.inc(46): Including file '../../common\words/colon.asm'
-../../avr8\dict/compiler1.inc(47): Including file '../../avr8\words/colon-noname.asm'
-../../avr8\dict/compiler1.inc(48): Including file '../../common\words/semicolon.asm'
-../../avr8\dict/compiler1.inc(49): Including file '../../common\words/right-bracket.asm'
-../../avr8\dict/compiler1.inc(50): Including file '../../common\words/left-bracket.asm'
-../../avr8\dict/compiler1.inc(51): Including file '../../common\words/variable.asm'
-../../avr8\dict/compiler1.inc(52): Including file '../../common\words/constant.asm'
-../../avr8\dict/compiler1.inc(53): Including file '../../avr8\words/user.asm'
-../../avr8\dict/compiler1.inc(55): Including file '../../common\words/recurse.asm'
-../../avr8\dict/compiler1.inc(56): Including file '../../avr8\words/immediate.asm'
-../../avr8\dict/compiler1.inc(58): Including file '../../common\words/bracketchar.asm'
-../../avr8\dict/compiler1.inc(59): Including file '../../common\words/abort-string.asm'
-../../avr8\dict/compiler1.inc(60): Including file '../../common\words/abort.asm'
-../../avr8\dict/compiler1.inc(61): Including file '../../common\words/q-abort.asm'
-../../avr8\dict/compiler1.inc(63): Including file '../../common\words/get-stack.asm'
-../../avr8\dict/compiler1.inc(64): Including file '../../common\words/set-stack.asm'
-../../avr8\dict/compiler1.inc(65): Including file '../../common\words/map-stack.asm'
-../../avr8\dict/compiler1.inc(66): Including file '../../avr8\words/get-current.asm'
-../../avr8\dict/compiler1.inc(67): Including file '../../common\words/get-order.asm'
-../../avr8\dict/compiler1.inc(68): Including file '../../common\words/cfg-order.asm'
-../../avr8\dict/compiler1.inc(69): Including file '../../avr8\words/compare.asm'
-../../avr8\dict/compiler1.inc(70): Including file '../../avr8\words/nfa2lfa.asm'
-../../avr8\amforth.asm(15): Including file 'dict_appl.inc'
-dict_appl.inc(13): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/compiler2.inc(8): Including file '../../avr8\words/set-current.asm'
-../../avr8\dict/compiler2.inc(9): Including file '../../avr8\words/wordlist.asm'
-../../avr8\dict/compiler2.inc(11): Including file '../../avr8\words/forth-wordlist.asm'
-../../avr8\dict/compiler2.inc(12): Including file '../../common\words/set-order.asm'
-../../avr8\dict/compiler2.inc(13): Including file '../../common\words/set-recognizer.asm'
-../../avr8\dict/compiler2.inc(14): Including file '../../common\words/get-recognizer.asm'
-../../avr8\dict/compiler2.inc(15): Including file '../../avr8\words/code.asm'
-../../avr8\dict/compiler2.inc(16): Including file '../../avr8\words/end-code.asm'
-../../avr8\dict/compiler2.inc(17): Including file '../../avr8\words/marker.asm'
-../../avr8\dict/compiler2.inc(18): Including file '../../common\words/postpone.asm'
-dict_appl.inc(16): Including file 'words/applturnkey.asm'
-dict_appl.inc(21): Including file '../../common\words/dot-s.asm'
-dict_appl.inc(26): Including file 'words/build-info.asm'
-dict_appl.inc(31): Including file '../../common\words/place.asm'
-dict_appl.inc(32): Including file '../../common\words/word.asm'
-../../avr8\amforth.asm(23): Including file '../../avr8\amforth-interpreter.asm'
-../../avr8\amforth.asm(24): Including file '../../avr8\dict/nrww.inc'
-../../avr8\dict/nrww.inc(4): Including file '../../avr8\words/exit.asm'
-../../avr8\dict/nrww.inc(5): Including file '../../avr8\words/execute.asm'
-../../avr8\dict/nrww.inc(6): Including file '../../avr8\words/dobranch.asm'
-../../avr8\dict/nrww.inc(7): Including file '../../avr8\words/docondbranch.asm'
-../../avr8\dict/nrww.inc(10): Including file '../../avr8\words/doliteral.asm'
-../../avr8\dict/nrww.inc(11): Including file '../../avr8\words/dovariable.asm'
-../../avr8\dict/nrww.inc(12): Including file '../../avr8\words/doconstant.asm'
-../../avr8\dict/nrww.inc(13): Including file '../../avr8\words/douser.asm'
-../../avr8\dict/nrww.inc(14): Including file '../../avr8\words/do-value.asm'
-../../avr8\dict/nrww.inc(15): Including file '../../avr8\words/fetch.asm'
-../../avr8\dict/nrww.inc(16): Including file '../../avr8\words/store.asm'
-../../avr8\dict/nrww.inc(17): Including file '../../avr8\words/cstore.asm'
-../../avr8\dict/nrww.inc(18): Including file '../../avr8\words/cfetch.asm'
-../../avr8\dict/nrww.inc(19): Including file '../../avr8\words/fetch-u.asm'
-../../avr8\dict/nrww.inc(20): Including file '../../avr8\words/store-u.asm'
-../../avr8\dict/nrww.inc(23): Including file '../../avr8\words/dup.asm'
-../../avr8\dict/nrww.inc(24): Including file '../../avr8\words/qdup.asm'
-../../avr8\dict/nrww.inc(25): Including file '../../avr8\words/swap.asm'
-../../avr8\dict/nrww.inc(26): Including file '../../avr8\words/over.asm'
-../../avr8\dict/nrww.inc(27): Including file '../../avr8\words/drop.asm'
-../../avr8\dict/nrww.inc(28): Including file '../../avr8\words/rot.asm'
-../../avr8\dict/nrww.inc(29): Including file '../../avr8\words/nip.asm'
-../../avr8\dict/nrww.inc(31): Including file '../../avr8\words/r_from.asm'
-../../avr8\dict/nrww.inc(32): Including file '../../avr8\words/to_r.asm'
-../../avr8\dict/nrww.inc(33): Including file '../../avr8\words/r_fetch.asm'
-../../avr8\dict/nrww.inc(36): Including file '../../common\words/not-equal.asm'
-../../avr8\dict/nrww.inc(37): Including file '../../avr8\words/equalzero.asm'
-../../avr8\dict/nrww.inc(38): Including file '../../avr8\words/lesszero.asm'
-../../avr8\dict/nrww.inc(39): Including file '../../avr8\words/greaterzero.asm'
-../../avr8\dict/nrww.inc(40): Including file '../../avr8\words/d-greaterzero.asm'
-../../avr8\dict/nrww.inc(41): Including file '../../avr8\words/d-lesszero.asm'
-../../avr8\dict/nrww.inc(43): Including file '../../avr8\words/true.asm'
-../../avr8\dict/nrww.inc(44): Including file '../../avr8\words/zero.asm'
-../../avr8\dict/nrww.inc(45): Including file '../../avr8\words/uless.asm'
-../../avr8\dict/nrww.inc(46): Including file '../../common\words/u-greater.asm'
-../../avr8\dict/nrww.inc(47): Including file '../../avr8\words/less.asm'
-../../avr8\dict/nrww.inc(48): Including file '../../avr8\words/greater.asm'
-../../avr8\dict/nrww.inc(50): Including file '../../avr8\words/log2.asm'
-../../avr8\dict/nrww.inc(51): Including file '../../avr8\words/minus.asm'
-../../avr8\dict/nrww.inc(52): Including file '../../avr8\words/plus.asm'
-../../avr8\dict/nrww.inc(53): Including file '../../avr8\words/mstar.asm'
-../../avr8\dict/nrww.inc(54): Including file '../../avr8\words/umslashmod.asm'
-../../avr8\dict/nrww.inc(55): Including file '../../avr8\words/umstar.asm'
-../../avr8\dict/nrww.inc(57): Including file '../../avr8\words/invert.asm'
-../../avr8\dict/nrww.inc(58): Including file '../../avr8\words/2slash.asm'
-../../avr8\dict/nrww.inc(59): Including file '../../avr8\words/2star.asm'
-../../avr8\dict/nrww.inc(60): Including file '../../avr8\words/and.asm'
-../../avr8\dict/nrww.inc(61): Including file '../../avr8\words/or.asm'
-../../avr8\dict/nrww.inc(62): Including file '../../avr8\words/xor.asm'
-../../avr8\dict/nrww.inc(64): Including file '../../avr8\words/1plus.asm'
-../../avr8\dict/nrww.inc(65): Including file '../../avr8\words/1minus.asm'
-../../avr8\dict/nrww.inc(66): Including file '../../common\words/q-negate.asm'
-../../avr8\dict/nrww.inc(67): Including file '../../avr8\words/lshift.asm'
-../../avr8\dict/nrww.inc(68): Including file '../../avr8\words/rshift.asm'
-../../avr8\dict/nrww.inc(69): Including file '../../avr8\words/plusstore.asm'
-../../avr8\dict/nrww.inc(71): Including file '../../avr8\words/rpfetch.asm'
-../../avr8\dict/nrww.inc(72): Including file '../../avr8\words/rpstore.asm'
-../../avr8\dict/nrww.inc(73): Including file '../../avr8\words/spfetch.asm'
-../../avr8\dict/nrww.inc(74): Including file '../../avr8\words/spstore.asm'
-../../avr8\dict/nrww.inc(76): Including file '../../avr8\words/dodo.asm'
-../../avr8\dict/nrww.inc(77): Including file '../../avr8\words/i.asm'
-../../avr8\dict/nrww.inc(78): Including file '../../avr8\words/doplusloop.asm'
-../../avr8\dict/nrww.inc(79): Including file '../../avr8\words/doloop.asm'
-../../avr8\dict/nrww.inc(80): Including file '../../avr8\words/unloop.asm'
-../../avr8\dict/nrww.inc(84): Including file '../../avr8\words/cmove_g.asm'
-../../avr8\dict/nrww.inc(85): Including file '../../avr8\words/byteswap.asm'
-../../avr8\dict/nrww.inc(86): Including file '../../avr8\words/up.asm'
-../../avr8\dict/nrww.inc(87): Including file '../../avr8\words/1ms.asm'
-../../avr8\dict/nrww.inc(88): Including file '../../avr8\words/2to_r.asm'
-../../avr8\dict/nrww.inc(89): Including file '../../avr8\words/2r_from.asm'
-../../avr8\dict/nrww.inc(91): Including file '../../avr8\words/store-e.asm'
-../../avr8\dict/nrww.inc(92): Including file '../../avr8\words/fetch-e.asm'
-../../avr8\dict/nrww.inc(93): Including file '../../avr8\words/store-i.asm'
-../../avr8\dict/nrww.inc(97): Including file '../../avr8\words/store-i_nrww.asm'
-../../avr8\dict/nrww.inc(99): Including file '../../avr8\words/fetch-i.asm'
-../../avr8\dict/nrww.inc(102): Including file '../../avr8\dict/core_8k.inc'
-../../avr8\dict/core_8k.inc(2): Including file '../../avr8\words/n_to_r.asm'
-../../avr8\dict/core_8k.inc(3): Including file '../../avr8\words/n_r_from.asm'
-../../avr8\dict/core_8k.inc(5): Including file '../../avr8\words/d-2star.asm'
-../../avr8\dict/core_8k.inc(6): Including file '../../avr8\words/d-2slash.asm'
-../../avr8\dict/core_8k.inc(7): Including file '../../avr8\words/d-plus.asm'
-../../avr8\dict/core_8k.inc(8): Including file '../../avr8\words/d-minus.asm'
-../../avr8\dict/core_8k.inc(9): Including file '../../avr8\words/d-invert.asm'
-../../avr8\dict/core_8k.inc(10): Including file '../../common\words/u-dot.asm'
-../../avr8\dict/core_8k.inc(11): Including file '../../common\words/u-dot-r.asm'
-../../avr8\dict/core_8k.inc(13): Including file '../../common\words/show-wordlist.asm'
-../../avr8\dict/core_8k.inc(14): Including file '../../common\words/words.asm'
-../../avr8\dict/core_8k.inc(15): Including file '../../avr8\dict/interrupt.inc'
-../../avr8\dict/interrupt.inc(8): Including file '../../avr8\words/int-on.asm'
-../../avr8\dict/interrupt.inc(9): Including file '../../avr8\words/int-off.asm'
-../../avr8\dict/interrupt.inc(10): Including file '../../avr8\words/int-store.asm'
-../../avr8\dict/interrupt.inc(11): Including file '../../avr8\words/int-fetch.asm'
-../../avr8\dict/interrupt.inc(12): Including file '../../avr8\words/int-trap.asm'
-../../avr8\dict/interrupt.inc(14): Including file '../../avr8\words/isr-exec.asm'
-../../avr8\dict/interrupt.inc(15): Including file '../../avr8\words/isr-end.asm'
-../../avr8\dict/core_8k.inc(17): Including file '../../common\words/pick.asm'
-../../avr8\dict/core_8k.inc(18): Including file '../../common\words/dot-quote.asm'
-../../avr8\dict/core_8k.inc(19): Including file '../../common\words/squote.asm'
-../../avr8\dict/core_8k.inc(21): Including file '../../avr8\words/fill.asm'
-../../avr8\dict/core_8k.inc(23): Including file '../../avr8\words/environment.asm'
-../../avr8\dict/core_8k.inc(24): Including file '../../avr8\words/env-wordlists.asm'
-../../avr8\dict/core_8k.inc(25): Including file '../../avr8\words/env-slashpad.asm'
-../../avr8\dict/core_8k.inc(26): Including file '../../common\words/env-slashhold.asm'
-../../avr8\dict/core_8k.inc(27): Including file '../../common\words/env-forthname.asm'
-../../avr8\dict/core_8k.inc(28): Including file '../../common\words/env-forthversion.asm'
-../../avr8\dict/core_8k.inc(29): Including file '../../common\words/env-cpu.asm'
-../../avr8\dict/core_8k.inc(30): Including file '../../avr8\words/env-mcuinfo.asm'
-../../avr8\dict/core_8k.inc(31): Including file '../../common\words/env-usersize.asm'
-../../avr8\dict/core_8k.inc(33): Including file '../../common\words/f_cpu.asm'
-../../avr8\dict/core_8k.inc(34): Including file '../../avr8\words/state.asm'
-../../avr8\dict/core_8k.inc(35): Including file '../../common\words/base.asm'
-../../avr8\dict/core_8k.inc(37): Including file '../../avr8\words/cells.asm'
-../../avr8\dict/core_8k.inc(38): Including file '../../avr8\words/cellplus.asm'
-../../avr8\dict/core_8k.inc(40): Including file '../../common\words/2dup.asm'
-../../avr8\dict/core_8k.inc(41): Including file '../../common\words/2drop.asm'
-../../avr8\dict/core_8k.inc(43): Including file '../../common\words/tuck.asm'
-../../avr8\dict/core_8k.inc(45): Including file '../../common\words/to-in.asm'
-../../avr8\dict/core_8k.inc(46): Including file '../../common\words/pad.asm'
-../../avr8\dict/core_8k.inc(47): Including file '../../common\words/emit.asm'
-../../avr8\dict/core_8k.inc(48): Including file '../../common\words/emitq.asm'
-../../avr8\dict/core_8k.inc(49): Including file '../../common\words/key.asm'
-../../avr8\dict/core_8k.inc(50): Including file '../../common\words/keyq.asm'
-../../avr8\dict/core_8k.inc(52): Including file '../../avr8\words/dp.asm'
-../../avr8\dict/core_8k.inc(53): Including file '../../avr8\words/ehere.asm'
-../../avr8\dict/core_8k.inc(54): Including file '../../avr8\words/here.asm'
-../../avr8\dict/core_8k.inc(55): Including file '../../avr8\words/allot.asm'
-../../avr8\dict/core_8k.inc(57): Including file '../../common\words/bin.asm'
-../../avr8\dict/core_8k.inc(58): Including file '../../common\words/decimal.asm'
-../../avr8\dict/core_8k.inc(59): Including file '../../common\words/hex.asm'
-../../avr8\dict/core_8k.inc(60): Including file '../../common\words/bl.asm'
-../../avr8\dict/core_8k.inc(62): Including file '../../avr8\words/turnkey.asm'
-../../avr8\dict/core_8k.inc(64): Including file '../../avr8\words/slashmod.asm'
-../../avr8\dict/core_8k.inc(65): Including file '../../avr8\words/uslashmod.asm'
-../../avr8\dict/core_8k.inc(66): Including file '../../avr8\words/negate.asm'
-../../avr8\dict/core_8k.inc(67): Including file '../../common\words/slash.asm'
-../../avr8\dict/core_8k.inc(68): Including file '../../common\words/mod.asm'
-../../avr8\dict/core_8k.inc(69): Including file '../../common\words/abs.asm'
-../../avr8\dict/core_8k.inc(70): Including file '../../common\words/min.asm'
-../../avr8\dict/core_8k.inc(71): Including file '../../common\words/max.asm'
-../../avr8\dict/core_8k.inc(72): Including file '../../common\words/within.asm'
-../../avr8\dict/core_8k.inc(74): Including file '../../common\words/to-upper.asm'
-../../avr8\dict/core_8k.inc(75): Including file '../../common\words/to-lower.asm'
-../../avr8\dict/core_8k.inc(77): Including file '../../avr8\words/hld.asm'
-../../avr8\dict/core_8k.inc(78): Including file '../../common\words/hold.asm'
-../../avr8\dict/core_8k.inc(79): Including file '../../common\words/less-sharp.asm'
-../../avr8\dict/core_8k.inc(80): Including file '../../common\words/sharp.asm'
-../../avr8\dict/core_8k.inc(81): Including file '../../common\words/sharp-s.asm'
-../../avr8\dict/core_8k.inc(82): Including file '../../common\words/sharp-greater.asm'
-../../avr8\dict/core_8k.inc(83): Including file '../../common\words/sign.asm'
-../../avr8\dict/core_8k.inc(84): Including file '../../common\words/d-dot-r.asm'
-../../avr8\dict/core_8k.inc(85): Including file '../../common\words/dot-r.asm'
-../../avr8\dict/core_8k.inc(86): Including file '../../common\words/d-dot.asm'
-../../avr8\dict/core_8k.inc(87): Including file '../../common\words/dot.asm'
-../../avr8\dict/core_8k.inc(88): Including file '../../common\words/ud-dot.asm'
-../../avr8\dict/core_8k.inc(89): Including file '../../common\words/ud-dot-r.asm'
-../../avr8\dict/core_8k.inc(90): Including file '../../common\words/ud-slash-mod.asm'
-../../avr8\dict/core_8k.inc(91): Including file '../../common\words/digit-q.asm'
-../../avr8\dict/core_8k.inc(93): Including file '../../avr8\words/do-sliteral.asm'
-../../avr8\dict/core_8k.inc(94): Including file '../../avr8\words/scomma.asm'
-../../avr8\dict/core_8k.inc(95): Including file '../../avr8\words/itype.asm'
-../../avr8\dict/core_8k.inc(96): Including file '../../avr8\words/icount.asm'
-../../avr8\dict/core_8k.inc(97): Including file '../../common\words/cr.asm'
-../../avr8\dict/core_8k.inc(98): Including file '../../common\words/space.asm'
-../../avr8\dict/core_8k.inc(99): Including file '../../common\words/spaces.asm'
-../../avr8\dict/core_8k.inc(100): Including file '../../common\words/type.asm'
-../../avr8\dict/core_8k.inc(101): Including file '../../common\words/tick.asm'
-../../avr8\dict/core_8k.inc(103): Including file '../../common\words/handler.asm'
-../../avr8\dict/core_8k.inc(104): Including file '../../common\words/catch.asm'
-../../avr8\dict/core_8k.inc(105): Including file '../../common\words/throw.asm'
-../../avr8\dict/core_8k.inc(107): Including file '../../common\words/cskip.asm'
-../../avr8\dict/core_8k.inc(108): Including file '../../common\words/cscan.asm'
-../../avr8\dict/core_8k.inc(109): Including file '../../common\words/accept.asm'
-../../avr8\dict/core_8k.inc(110): Including file '../../common\words/refill.asm'
-../../avr8\dict/core_8k.inc(111): Including file '../../common\words/char.asm'
-../../avr8\dict/core_8k.inc(112): Including file '../../common\words/number.asm'
-../../avr8\dict/core_8k.inc(113): Including file '../../common\words/q-sign.asm'
-../../avr8\dict/core_8k.inc(114): Including file '../../common\words/set-base.asm'
-../../avr8\dict/core_8k.inc(115): Including file '../../common\words/to-number.asm'
-../../avr8\dict/core_8k.inc(116): Including file '../../common\words/parse.asm'
-../../avr8\dict/core_8k.inc(117): Including file '../../common\words/source.asm'
-../../avr8\dict/core_8k.inc(118): Including file '../../common\words/slash-string.asm'
-../../avr8\dict/core_8k.inc(119): Including file '../../common\words/parse-name.asm'
-../../avr8\dict/core_8k.inc(120): Including file '../../common\words/find-xt.asm'
-../../avr8\dict/core_8k.inc(122): Including file '../../common\words/prompt-ok.asm'
-../../avr8\dict/core_8k.inc(123): Including file '../../common\words/prompt-ready.asm'
-../../avr8\dict/core_8k.inc(124): Including file '../../common\words/prompt-error.asm'
-../../avr8\dict/core_8k.inc(126): Including file '../../common\words/quit.asm'
-../../avr8\dict/core_8k.inc(127): Including file '../../avr8\words/pause.asm'
-../../avr8\dict/core_8k.inc(128): Including file '../../avr8\words/cold.asm'
-../../avr8\dict/core_8k.inc(129): Including file '../../common\words/warm.asm'
-../../avr8\dict/core_8k.inc(131): Including file '../../avr8\words/sp0.asm'
-../../avr8\dict/core_8k.inc(132): Including file '../../avr8\words/rp0.asm'
-../../avr8\dict/core_8k.inc(133): Including file '../../common\words/depth.asm'
-../../avr8\dict/core_8k.inc(134): Including file '../../common\words/interpret.asm'
-../../avr8\dict/core_8k.inc(135): Including file '../../avr8\words/forth-recognizer.asm'
-../../avr8\dict/core_8k.inc(136): Including file '../../common\words/recognize.asm'
-../../avr8\dict/core_8k.inc(137): Including file '../../common\words/rec-intnum.asm'
-../../avr8\dict/core_8k.inc(138): Including file '../../common\words/rec-find.asm'
-../../avr8\dict/core_8k.inc(139): Including file '../../common\words/dt-null.asm'
-../../avr8\dict/core_8k.inc(141): Including file '../../common\words/q-stack.asm'
-../../avr8\dict/core_8k.inc(142): Including file '../../common\words/ver.asm'
-../../avr8\dict/core_8k.inc(144): Including file '../../common\words/noop.asm'
-../../avr8\dict/core_8k.inc(145): Including file '../../avr8\words/unused.asm'
-../../avr8\dict/core_8k.inc(147): Including file '../../common\words/to.asm'
-../../avr8\dict/core_8k.inc(148): Including file '../../avr8\words/i-cellplus.asm'
-../../avr8\dict/core_8k.inc(150): Including file '../../avr8\words/edefer-fetch.asm'
-../../avr8\dict/core_8k.inc(151): Including file '../../avr8\words/edefer-store.asm'
-../../avr8\dict/core_8k.inc(152): Including file '../../common\words/rdefer-fetch.asm'
-../../avr8\dict/core_8k.inc(153): Including file '../../common\words/rdefer-store.asm'
-../../avr8\dict/core_8k.inc(154): Including file '../../common\words/udefer-fetch.asm'
-../../avr8\dict/core_8k.inc(155): Including file '../../common\words/udefer-store.asm'
-../../avr8\dict/core_8k.inc(156): Including file '../../common\words/defer-store.asm'
-../../avr8\dict/core_8k.inc(157): Including file '../../common\words/defer-fetch.asm'
-../../avr8\dict/core_8k.inc(158): Including file '../../avr8\words/do-defer.asm'
-../../avr8\dict/core_8k.inc(160): Including file '../../common\words/search-wordlist.asm'
-../../avr8\dict/core_8k.inc(161): Including file '../../common\words/traverse-wordlist.asm'
-../../avr8\dict/core_8k.inc(162): Including file '../../common\words/name2string.asm'
-../../avr8\dict/core_8k.inc(163): Including file '../../avr8\words/nfa2cfa.asm'
-../../avr8\dict/core_8k.inc(164): Including file '../../avr8\words/icompare.asm'
-../../avr8\dict/core_8k.inc(166): Including file '../../common\words/star.asm'
-../../avr8\dict/core_8k.inc(167): Including file '../../avr8\words/j.asm'
-../../avr8\dict/core_8k.inc(169): Including file '../../avr8\words/dabs.asm'
-../../avr8\dict/core_8k.inc(170): Including file '../../avr8\words/dnegate.asm'
-../../avr8\dict/core_8k.inc(171): Including file '../../avr8\words/cmove.asm'
-../../avr8\dict/core_8k.inc(172): Including file '../../common\words/2swap.asm'
-../../avr8\dict/core_8k.inc(174): Including file '../../common\words/tib.asm'
-../../avr8\dict/core_8k.inc(176): Including file '../../avr8\words/init-ram.asm'
-../../avr8\dict/core_8k.inc(177): Including file '../../avr8\dict/compiler2.inc'
-../../avr8\dict/core_8k.inc(178): Including file '../../common\words/bounds.asm'
-../../avr8\dict/core_8k.inc(179): Including file '../../common\words/s-to-d.asm'
-../../avr8\dict/core_8k.inc(180): Including file '../../avr8\words/to-body.asm'
-../../avr8\dict/nrww.inc(112): Including file '../../common\words/2literal.asm'
-../../avr8\dict/nrww.inc(113): Including file '../../avr8\words/equal.asm'
-../../avr8\dict/nrww.inc(114): Including file '../../common\words/num-constants.asm'
-../../avr8\amforth.asm(25): Including file 'dict_appl_core.inc'
-../../avr8\amforth.asm(36): Including file '../../avr8\amforth-eeprom.inc'
-
-
- ;
- ; The order of the entries (esp the include order) must not be
- ; changed since it is very important that the settings are in the
- ; right order
- ;
- ; note: .set is like a variable, .equ is like a constant
- ;
- ; first is include the preamble. It contains macro definitions,
- ; default settings and mcu specific stuff like register names.
- ; The files included with it depend on the -I order of the
- ; assembler.
-
- .include "preamble.inc"
-
- .include "macros.asm"
-
- .set DICT_COMPILER2 = 0 ;
- .set cpu_msp430 = 0
- .set cpu_avr8 = 1
-
- .include "user.inc"
-
- ;
-
- ; used by the multitasker
- .set USER_STATE = 0
- .set USER_FOLLOWER = 2
-
- ; stackpointer, used by mulitasker
- .set USER_RP = 4
- .set USER_SP0 = 6
- .set USER_SP = 8
-
- ; excpection handling
- .set USER_HANDLER = 10
-
- ; numeric IO
- .set USER_BASE = 12
-
- ; character IO
- .set USER_EMIT = 14
- .set USER_EMITQ = 16
- .set USER_KEY = 18
- .set USER_KEYQ = 20
-
- .set USER_SOURCE = 22
- .set USER_TO_IN = 24
- .set USER_REFILL = 26
-
- .set USER_P_OK = 28
- .set USER_P_ERR = 30
- .set USER_P_RDY = 32
-
- .set SYSUSERSIZE = 34
- ;
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
- ; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
- .macro loadtos
- ld tosl, Y+
- ld tosh, Y+
- .endmacro
-
- .macro savetos
- st -Y, tosh
- st -Y, tosl
- .endmacro
-
- .macro in_
- .if (@1 < $40)
- in @0,@1
- .else
- lds @0,@1
- .endif
- .endmacro
-
- .macro out_
- .if (@0 < $40)
- out @0,@1
- .else
- sts @0,@1
- .endif
- .endmacro
-
- .macro sbi_
- .if (@0 < $40)
- sbi @0,@1
- .else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
- .endif
- .endmacro
-
- .macro cbi_
- .if (@0 < $40)
- cbi @0,@1
- .else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
- .endif
- .endmacro
-
- .macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
- .endmacro
- .macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
- .endmacro
-
- ; F_CPU
- ; µsec 16000000 14745600 8000000 1000000
- ; 1 16 14,74 8 1
- ; 10 160 147,45 80 10
- ; 100 1600 1474,56 800 100
- ; 1000 16000 14745,6 8000 1000
- ;
- ; cycles = µsec * f_cpu / 1e6
- ; n_loops=cycles/5
- ;
- ; cycles already used will be subtracted from the delay
- ; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
- ; the maximum delay at 20MHz (50ns/clock) is 38350ns
- ; waitcount register must specify an immediate register
- ;
- ; busy waits a specfied amount of microseconds
- .macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
- .endmacro
-
- ; portability macros, they come from the msp430 branches
-
- .macro DEST
- .dw @0
- .endm
-
- ; controller specific file selected via include
- ; directory definition when calling the assembler (-I)
- .include "device.asm"
-
- ; generated automatically, do not edit
-
- .list
-
- .equ ramstart = 256
- .equ CELLSIZE = 2
- .macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
- .endmacro
- .macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- .endmacro
- .set WANT_ANALOG_COMPARATOR = 0
- .set WANT_USART0 = 0
- .set WANT_PORTA = 0
- .set WANT_PORTB = 0
- .set WANT_PORTC = 0
- .set WANT_PORTD = 0
- .set WANT_TIMER_COUNTER_0 = 0
- .set WANT_TIMER_COUNTER_1 = 0
- .set WANT_TIMER_COUNTER_2 = 0
- .set WANT_TIMER_COUNTER_3 = 0
- .set WANT_BOOT_LOAD = 0
- .set WANT_EXTERNAL_INTERRUPT = 0
- .set WANT_AD_CONVERTER = 0
- .set WANT_JTAG = 0
- .set WANT_EEPROM = 0
- .set WANT_TWI = 0
- .set WANT_USART1 = 0
- .set WANT_SPI = 0
- .set WANT_WATCHDOG = 0
- .set WANT_CPU = 0
- .equ intvecsize = 2 ; please verify; flash size: 131072 bytes
- .equ pclen = 2 ; please verify
- .overlap
- .org 2
-000002 d0ed rcall isr ; External Interrupt Request 0
- .org 4
-000004 d0eb rcall isr ; External Interrupt Request 1
- .org 6
-000006 d0e9 rcall isr ; External Interrupt Request 2
- .org 8
-000008 d0e7 rcall isr ; Pin Change Interrupt Request 0
- .org 10
-00000a d0e5 rcall isr ; Pin Change Interrupt Request 1
- .org 12
-00000c d0e3 rcall isr ; Pin Change Interrupt Request 2
- .org 14
-00000e d0e1 rcall isr ; Pin Change Interrupt Request 3
- .org 16
-000010 d0df rcall isr ; Watchdog Time-out Interrupt
- .org 18
-000012 d0dd rcall isr ; Timer/Counter2 Compare Match A
- .org 20
-000014 d0db rcall isr ; Timer/Counter2 Compare Match B
- .org 22
-000016 d0d9 rcall isr ; Timer/Counter2 Overflow
- .org 24
-000018 d0d7 rcall isr ; Timer/Counter1 Capture Event
- .org 26
-00001a d0d5 rcall isr ; Timer/Counter1 Compare Match A
- .org 28
-00001c d0d3 rcall isr ; Timer/Counter1 Compare Match B
- .org 30
-00001e d0d1 rcall isr ; Timer/Counter1 Overflow
- .org 32
-000020 d0cf rcall isr ; Timer/Counter0 Compare Match A
- .org 34
-000022 d0cd rcall isr ; Timer/Counter0 Compare Match B
- .org 36
-000024 d0cb rcall isr ; Timer/Counter0 Overflow
- .org 38
-000026 d0c9 rcall isr ; SPI Serial Transfer Complete
- .org 40
-000028 d0c7 rcall isr ; USART0, Rx Complete
- .org 42
-00002a d0c5 rcall isr ; USART0 Data register Empty
- .org 44
-00002c d0c3 rcall isr ; USART0, Tx Complete
- .org 46
-00002e d0c1 rcall isr ; Analog Comparator
- .org 48
-000030 d0bf rcall isr ; ADC Conversion Complete
- .org 50
-000032 d0bd rcall isr ; EEPROM Ready
- .org 52
-000034 d0bb rcall isr ; 2-wire Serial Interface
- .org 54
-000036 d0b9 rcall isr ; Store Program Memory Read
- .org 56
-000038 d0b7 rcall isr ; USART1 RX complete
- .org 58
-00003a d0b5 rcall isr ; USART1 Data Register Empty
- .org 60
-00003c d0b3 rcall isr ; USART1 TX complete
- .org 62
-00003e d0b1 rcall isr ; Timer/Counter3 Capture Event
- .org 64
-000040 d0af rcall isr ; Timer/Counter3 Compare Match A
- .org 66
-000042 d0ad rcall isr ; Timer/Counter3 Compare Match B
- .org 68
-000044 d0ab rcall isr ; Timer/Counter3 Overflow
- .equ INTVECTORS = 35
- .nooverlap
-
- ; compatability layer (maybe empty)
-
- ; controller data area, environment query mcu-info
- mcu_info:
- mcu_ramsize:
-000045 4000 .dw 16384
- mcu_eepromsize:
-000046 1000 .dw 4096
- mcu_maxdp:
-000047 ffff .dw 65535
- mcu_numints:
-000048 0023 .dw 35
- mcu_name:
-000049 000b .dw 11
-00004a 5441
-00004b 656d
-00004c 6167
-00004d 3231
-00004e 3438
-00004f 0050 .db "ATmega1284P",0
- .set codestart=pc
-
- ; some defaults, change them in your application master file
- ; see template.asm for an example
-
- ; enabling Interrupts, disabling them affects
- ; other settings as well.
- .set WANT_INTERRUPTS = 1
-
- ; count the number of interrupts individually.
- ; requires a lot of RAM (one byte per interrupt)
- ; disabled by default.
- .set WANT_INTERRUPT_COUNTERS = 0
-
- ; receiving is asynchronously, so an interrupt queue is useful.
- .set WANT_ISR_RX = 1
-
- ; case insensitve dictionary lookup.
- .set WANT_IGNORECASE = 0
-
- ; map all memories to one address space. Details in the
- ; technical guide
- .set WANT_UNIFIED = 0
-
- ; terminal input buffer
- .set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
- ; USER variables *in addition* to system ones
- .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments
- .set rstackstart = RAMEND ; start address of return stack, grows downward
- .set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
- .set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
- .set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
- ; 10 per mille (1 per cent) is ok.
- .set BAUD = 38400
- .set BAUD_MAXERROR = 10
-
- ; Dictionary setup
- .set VE_HEAD = $0000
- .set VE_ENVHEAD = $0000
-
- ; The amforth code is split into two segments, one starting
- ; at address 0 (the RWW area) and one starting in
- ; the NRWW region. The latter part cannot be changed
- ; at runtime so it contains most of the core system
- ; that would never be changed. If unsure what it
- ; means, leave it as it is. This address may be
- ; adjusted to give room for other code fragments (e.g.
- ; bootloaders). The amforth code will start here and may
- ; occupy all space until flash-end.
-
- ; If you want leave out the first 512 bytes of the NRWW section
- ; for e.g. a bootloader change the line to
- ; .equ AMFORTH_RO_SEG = NRWW_START_ADDR+512/2
- ; note the /2 since the flash is 16bit per address
- ; default is the whole NRWW section
- ; .equ AMFORTH_RO_SEG = NRWW_START_ADDR
-
- .set AMFORTH_RO_SEG = NRWW_START_ADDR
-
- ; amforth needs two essential parameters: CPU clock
- ; and command terminal line.
- ; cpu clock in hertz, 1MHz is factory default
- .equ F_CPU = 8000000
-
- ; terminal settings
- ; check http://amforth.sourceforge.net/TG/recipes/Usart.html
- ; for further information
-
- ; serial line settings. The defaults are set in avr8/preamble.inc.
- ; You should not change that file but use your own settings *here*
- ; since it may get changed in future versions of amforth.
- ;.set BAUD=38400
- ;.set BAUD_MAXERROR=10
- ;.set WANT_ISR_RX = 1 ; interrupt driven receive
- ;.set WANT_ISR_TX = 0 ; send slowly but with less code space
-
- ; define which usart to use.
- .include "drivers/usart_0.asm"
-
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .equ URXCaddr = URXC0addr
- .equ UDREaddr = UDRE0addr
- .endif
-
- .equ bm_USART_RXRD = 1 << RXC0
- .equ bm_USART_TXRD = 1 << UDRE0
- .equ bm_ENABLE_TX = 1 << TXEN0
- .equ bm_ENABLE_RX = 1 << RXEN0
- .equ bm_ENABLE_INT_RX = 1<<RXCIE0
- .equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
- .equ bm_USARTC_en = 0
- .equ bm_ASYNC = 0 << 6
- .equ bm_SYNC = 1 << 6
- .equ bm_NO_PARITY = 0 << 4
- .equ bm_EVEN_PARITY = 2 << 4
- .equ bm_ODD_PARITY = 3 << 4
- .equ bm_1STOPBIT = 0 << 3
- .equ bm_2STOPBIT = 1 << 3
- .equ bm_5BIT = 0 << 1
- .equ bm_6BIT = 1 << 1
- .equ bm_7BIT = 2 << 1
- .equ bm_8BIT = 3 << 1
-
- .include "drivers/usart_common.asm"
-
- .set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
- .if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .endif
- .endif
-
- .if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-
-
- ; sizes have to be powers of 2!
- .equ usart_rx_size = $10
- .equ usart_rx_mask = usart_rx_size - 1
- .dseg
-000100 usart_rx_data: .byte usart_rx_size
-000110 usart_rx_in: .byte 1
-000111 usart_rx_out: .byte 1
- .cseg
-
- VE_TO_RXBUF:
-000050 ff07 .dw $ff07
-000051 723e
-000052 2d78
-000053 7562
-000054 0066 .db ">rx-buf",0
-000055 0000 .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
- XT_TO_RXBUF:
-000056 0057 .dw PFA_rx_tobuf
- PFA_rx_tobuf:
-000057 2f08 mov temp0, tosl
-000058 9110 0110 lds temp1, usart_rx_in
-00005a e0e0 ldi zl, low(usart_rx_data)
-00005b e0f1 ldi zh, high(usart_rx_data)
-00005c 0fe1 add zl, temp1
-00005d 1df3 adc zh, zeroh
-00005e 8300 st Z, temp0
-00005f 9513 inc temp1
-000060 701f andi temp1,usart_rx_mask
-000061 9310 0110 sts usart_rx_in, temp1
-000063 9189
-000064 9199 loadtos
-000065 940c f004 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ; setup with
- ; ' isr-rx URXCaddr int!
- VE_ISR_RX:
-000067 ff06 .dw $ff06
-000068 7369
-000069 2d72
-00006a 7872 .db "isr-rx"
-00006b 0050 .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
- XT_ISR_RX:
-00006c f000 .dw DO_COLON
- usart_rx_isr:
-00006d f045 .dw XT_DOLITERAL
-00006e 00c6 .dw usart_data
-00006f f0a9 .dw XT_CFETCH
-000070 f0c2 .dw XT_DUP
-000071 f045 .dw XT_DOLITERAL
-000072 0003 .dw 3
-000073 fdaa .dw XT_EQUAL
-000074 f03e .dw XT_DOCONDBRANCH
-000075 0077 .dw usart_rx_isr1
-000076 fa73 .dw XT_COLD
- usart_rx_isr1:
-000077 0056 .dw XT_TO_RXBUF
-000078 f025 .dw XT_EXIT
-
- ; ( -- ) Hardware Access
- ; R( --)
- ; initialize usart
- ;VE_USART_INIT_RXBUFFER:
- ; .dw $ff0x
- ; .db "+usart-buffer"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_USART_INIT_RXBUFFER
- XT_USART_INIT_RX_BUFFER:
-000079 f000 .dw DO_COLON
- PFA_USART_INIT_RX_BUFFER: ; ( -- )
-00007a f045
-00007b 006c .dw XT_DOLITERAL, XT_ISR_RX
-00007c f045
-00007d 0028 .dw XT_DOLITERAL, URXCaddr
-00007e f4a1 .dw XT_INTSTORE
-
-00007f f045 .dw XT_DOLITERAL
-000080 0100 .dw usart_rx_data
-000081 f045 .dw XT_DOLITERAL
-000082 0016 .dw usart_rx_size + 6
-000083 f165 .dw XT_ZERO
-000084 f4e9 .dw XT_FILL
-000085 f025 .dw XT_EXIT
-
- ; ( -- c)
- ; MCU
- ; get 1 character from input queue, wait if needed using interrupt driver
- VE_RX_BUFFER:
-000086 ff06 .dw $ff06
-000087 7872
-000088 622d
-000089 6675 .db "rx-buf"
-00008a 0067 .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
- XT_RX_BUFFER:
-00008b f000 .dw DO_COLON
- PFA_RX_BUFFER:
-00008c 00a6 .dw XT_RXQ_BUFFER
-00008d f03e .dw XT_DOCONDBRANCH
-00008e 008c .dw PFA_RX_BUFFER
-00008f f045 .dw XT_DOLITERAL
-000090 0111 .dw usart_rx_out
-000091 f0a9 .dw XT_CFETCH
-000092 f0c2 .dw XT_DUP
-000093 f045 .dw XT_DOLITERAL
-000094 0100 .dw usart_rx_data
-000095 f1ae .dw XT_PLUS
-000096 f0a9 .dw XT_CFETCH
-000097 f0d5 .dw XT_SWAP
-000098 f240 .dw XT_1PLUS
-000099 f045 .dw XT_DOLITERAL
-00009a 000f .dw usart_rx_mask
-00009b f224 .dw XT_AND
-00009c f045 .dw XT_DOLITERAL
-00009d 0111 .dw usart_rx_out
-00009e f09e .dw XT_CSTORE
-00009f f025 .dw XT_EXIT
-
- ; ( -- f)
- ; MCU
- ; check if unread characters are in the input queue
- VE_RXQ_BUFFER:
-0000a0 ff07 .dw $ff07
-0000a1 7872
-0000a2 2d3f
-0000a3 7562
-0000a4 0066 .db "rx?-buf",0
-0000a5 0086 .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
- XT_RXQ_BUFFER:
-0000a6 f000 .dw DO_COLON
- PFA_RXQ_BUFFER:
-0000a7 fa6b .dw XT_PAUSE
-0000a8 f045 .dw XT_DOLITERAL
-0000a9 0111 .dw usart_rx_out
-0000aa f0a9 .dw XT_CFETCH
-0000ab f045 .dw XT_DOLITERAL
-0000ac 0110 .dw usart_rx_in
-0000ad f0a9 .dw XT_CFETCH
-0000ae f124 .dw XT_NOTEQUAL
-0000af f025 .dw XT_EXIT
- ; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
- .else
- .endif
-
- .include "words/usart-tx-poll.asm"
-
- ; MCU
- ; check availability and send one character to the terminal using register poll
- VE_TX_POLL:
-0000b0 ff07 .dw $ff07
-0000b1 7874
-0000b2 702d
-0000b3 6c6f
-0000b4 006c .db "tx-poll",0
-0000b5 00a0 .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
- XT_TX_POLL:
-0000b6 f000 .dw DO_COLON
- PFA_TX_POLL:
- ; wait for data ready
-0000b7 00c4 .dw XT_TXQ_POLL
-0000b8 f03e .dw XT_DOCONDBRANCH
-0000b9 00b7 .dw PFA_TX_POLL
- ; send to usart
-0000ba f045 .dw XT_DOLITERAL
-0000bb 00c6 .dw USART_DATA
-0000bc f09e .dw XT_CSTORE
-0000bd f025 .dw XT_EXIT
-
- ; ( -- f) MCU
- ; MCU
- ; check if a character can be send using register poll
- VE_TXQ_POLL:
-0000be ff08 .dw $ff08
-0000bf 7874
-0000c0 2d3f
-0000c1 6f70
-0000c2 6c6c .db "tx?-poll"
-0000c3 00b0 .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
- XT_TXQ_POLL:
-0000c4 f000 .dw DO_COLON
- PFA_TXQ_POLL:
-0000c5 fa6b .dw XT_PAUSE
-0000c6 f045 .dw XT_DOLITERAL
-0000c7 00c0 .dw USART_A
-0000c8 f0a9 .dw XT_CFETCH
-0000c9 f045 .dw XT_DOLITERAL
-0000ca 0020 .dw bm_USART_TXRD
-0000cb f224 .dw XT_AND
-0000cc f025 .dw XT_EXIT
- .set XT_TX = XT_TX_POLL
- .set XT_TXQ = XT_TXQ_POLL
- .set XT_USART_INIT_TX = 0
-
- .include "words/ubrr.asm"
-
- ; MCU
- ; returns usart UBRR settings
- VE_UBRR:
-0000cd ff04 .dw $ff04
-0000ce 6275
-0000cf 7272 .db "ubrr"
-0000d0 00be .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
- XT_UBRR:
-0000d1 f080 .dw PFA_DOVALUE1
- PFA_UBRR: ; ( -- )
-0000d2 009e .dw EE_UBRRVAL
-0000d3 fbce .dw XT_EDEFERFETCH
-0000d4 fbd8 .dw XT_EDEFERSTORE
- .include "words/usart.asm"
-
- ; MCU
- ; initialize usart
- VE_USART:
-0000d5 ff06 .dw $ff06
-0000d6 752b
-0000d7 6173
-0000d8 7472 .db "+usart"
-0000d9 00cd .dw VE_HEAD
- .set VE_HEAD = VE_USART
- XT_USART:
-0000da f000 .dw DO_COLON
- PFA_USART: ; ( -- )
-
-0000db f045 .dw XT_DOLITERAL
-0000dc 0098 .dw USART_B_VALUE
-0000dd f045 .dw XT_DOLITERAL
-0000de 00c1 .dw USART_B
-0000df f09e .dw XT_CSTORE
-
-0000e0 f045 .dw XT_DOLITERAL
-0000e1 0006 .dw USART_C_VALUE
-0000e2 f045 .dw XT_DOLITERAL
-0000e3 00c2 .dw USART_C | bm_USARTC_en
-0000e4 f09e .dw XT_CSTORE
-
-0000e5 00d1 .dw XT_UBRR
-0000e6 f0c2 .dw XT_DUP
-0000e7 f30a .dw XT_BYTESWAP
-0000e8 f045 .dw XT_DOLITERAL
-0000e9 00c5 .dw BAUDRATE_HIGH
-0000ea f09e .dw XT_CSTORE
-0000eb f045 .dw XT_DOLITERAL
-0000ec 00c4 .dw BAUDRATE_LOW
-0000ed f09e .dw XT_CSTORE
- .if XT_USART_INIT_RX!=0
-0000ee 0079 .dw XT_USART_INIT_RX
- .endif
- .if XT_USART_INIT_TX!=0
- .endif
-
-0000ef f025 .dw XT_EXIT
-
-
- ; now define your own options, if the settings from
- ; the files included above are not ok. Use the .set
- ; instruction, not the .equ. e.g.:
- ;
- ; .set WANT_XY = 1
- ;
- ; there are many options available. There are two
- ; places where they are defined initially: core/macros.asm
- ; and core/devices/<mcutype>/device.asm. Setting the value
- ; to 1 enables the feature, setting to 0 disables it.
- ; Most options are disabled by default. You should never
- ; change the files mentioned above, setting the options here
- ; is absolutly sufficient.
-
- ; the dictionary search treats lowercase and uppercase
- ; letters the same. Set to 0 if you do not want it
- .set WANT_IGNORECASE = 1
-
-
- ; default settings as specified in core/macros.asm. Uncomment and
- ; change them if necessary.
-
- ; Size of the Terminal Input Buffer. This is the command line buffer.
- ; .set TIBSIZE = $64 ; bytes; ANS94 needs at least 80 characters per line
-
- ; The total USER size is the sum of the system internal USER area plus
- ; the size specified here.
- ; .set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
- ; addresses of various data segments.
- ;.set rstackstart = RAMEND ; start address of return stack, grows downward
- ;.set stackstart = RAMEND - 80 ; start address of data stack, grows downward
- ; change only if you know what to you do
-
- ; Total number of entries in the search order.
- ; The standard requires 8 wordlists in the search oder, amforth uses
- ; already one for itself. So you'll have 7 slots available.
- ;.set NUMWORDLISTS = 8
-
- ; Total number of recognizers.
- ; There are 2 recognizers already in the core system. That makes
- ; 2 for you.
- ;.set NUMRECOGNIZERS = 4
-
-
- ; DRIVER SECTION
- ;
- ; settings for 1wire interface, uncomment to use it
- ;.equ OW_PORT=PORTB
- ;.equ OW_BIT=4
- ;.include "drivers/1wire.asm"
-
- ; Interrupts.
- ; globally enable (or disable) the interrupt support. It is
- ; enabled by default and some other settings (usart receive)
- ; depend on it. disabling it makes the inner interpreter
- ; slightly faster and frees some code space.
- ; .set WANT_INTERRUPTS = 1
-
- ; reserve a RAM region to count each interrupt individually.
- ; each interrupt of the given controller type gets a byte
- ; that is incremented for each interrupt. Needs a lot of
- ; RAM but may be useful for debugging interrupts or get rid
- ; of random effects. disabled by default.
- ; .set WANT_INTERRUPT_COUNTERS = 0
-
-
- ; include the whole source tree.
- .include "amforth.asm"
-
- ;;;;
- ;;;; GPL V2 (only)
-
- .set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
- .set corepc = pc
- .org $0000
-000000 940c fa74 jmp_ PFA_COLD
-
- .org corepc
- .include "drivers/generic-isr.asm"
-
- .eseg
-000000 intvec: .byte INTVECTORS * CELLSIZE
- .dseg
-000112 intcnt: .byte INTVECTORS
- .cseg
-
- ; interrupt routine gets called (again) by rcall! This gives the
- ; address of the int-vector on the stack.
- isr:
-0000f0 920a st -Y, r0
-0000f1 b60f in r0, SREG
-0000f2 920a st -Y, r0
- .if (pclen==3)
- .endif
-0000f3 900f pop r0
-0000f4 900f pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
-0000f5 940a dec r0
- .if intvecsize == 1 ;
- .endif
-0000f6 2cb0 mov isrflag, r0
-0000f7 93ff push zh
-0000f8 93ef push zl
-0000f9 e1e2 ldi zl, low(intcnt)
-0000fa e0f1 ldi zh, high(intcnt)
-0000fb 9406 lsr r0 ; we use byte addresses in the counter array, not words
-0000fc 0de0 add zl, r0
-0000fd 1df3 adc zh, zeroh
-0000fe 8000 ld r0, Z
-0000ff 9403 inc r0
-000100 8200 st Z, r0
-000101 91ef pop zl
-000102 91ff pop zh
-
-000103 9009 ld r0, Y+
-000104 be0f out SREG, r0
-000105 9009 ld r0, Y+
-000106 9508 ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
- ; lower part of the dictionary
- .include "dict/rww.inc"
-
-
- ; Arithmetics
- ; add a number to a double cell
- VE_MPLUS:
-000107 ff02 .dw $ff02
-000108 2b6d .db "m+"
-000109 00d5 .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
- XT_MPLUS:
-00010a f000 .dw DO_COLON
- PFA_MPLUS:
-00010b fd92 .dw XT_S2D
-00010c f42f .dw XT_DPLUS
-00010d f025 .dw XT_EXIT
- .include "words/ud-star.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSTAR:
-00010e ff03 .dw $ff03
-00010f 6475
-../../common\words/ud-star.asm(9): warning: .cseg .db misalignment - padding zero byte
-000110 002a .db "ud*"
-000111 0107 .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
- XT_UDSTAR:
-000112 f000 .dw DO_COLON
- PFA_UDSTAR:
-
- .endif
- ;Z UD* ud1 d2 -- ud3 32*16->32 multiply
- ; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
-000113 f0c2
-000114 f110
-000115 f1f1
-000116 f0ea .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
-000117 f0d5
-000118 f107
-000119 f1f1
-00011a f0f2
-00011b f1ae
-00011c f025 .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
- .include "words/umax.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMAX:
-00011d ff04 .dw $ff04
-00011e 6d75
-00011f 7861 .db "umax"
-000120 010e .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
- XT_UMAX:
-000121 f000 .dw DO_COLON
- PFA_UMAX:
- .endif
-
-000122 f57f
-000123 f16d .DW XT_2DUP,XT_ULESS
-000124 f03e .dw XT_DOCONDBRANCH
-000125 0127 DEST(UMAX1)
-000126 f0d5 .DW XT_SWAP
-000127 f0ea UMAX1: .DW XT_DROP
-000128 f025 .dw XT_EXIT
- .include "words/umin.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UMIN:
-000129 ff04 .dw $ff04
-00012a 6d75
-00012b 6e69 .db "umin"
-00012c 011d .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
- XT_UMIN:
-00012d f000 .dw DO_COLON
- PFA_UMIN:
- .endif
-00012e f57f
-00012f f178 .DW XT_2DUP,XT_UGREATER
-000130 f03e .dw XT_DOCONDBRANCH
-000131 0133 DEST(UMIN1)
-000132 f0d5 .DW XT_SWAP
-000133 f0ea UMIN1: .DW XT_DROP
-000134 f025 .dw XT_EXIT
- .include "words/immediate-q.asm"
-
- ; Tools
- ; return +1 if immediate, -1 otherwise, flag from name>flags
- ;VE_IMMEDIATEQ:
- ; .dw $ff06
- ; .db "immediate?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_IMMEDIATEQ
- XT_IMMEDIATEQ:
-000135 f000 .dw DO_COLON
- PFA_IMMEDIATEQ:
-000136 f045 .dw XT_DOLITERAL
-000137 8000 .dw $8000
-000138 f224 .dw XT_AND
-000139 f12b .dw XT_ZEROEQUAL
-00013a f03e .dw XT_DOCONDBRANCH
-00013b 013e DEST(IMMEDIATEQ1)
-00013c fdb1 .dw XT_ONE
-00013d f025 .dw XT_EXIT
- IMMEDIATEQ1:
- ; not immediate
-00013e f15c .dw XT_TRUE
-00013f f025 .dw XT_EXIT
- .include "words/name2flags.asm"
-
- ; Tools
- ; get the flags from a name token
- VE_NAME2FLAGS:
-000140 ff0a .dw $ff0a
-000141 616e
-000142 656d
-000143 663e
-000144 616c
-000145 7367 .db "name>flags"
-000146 0129 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
- XT_NAME2FLAGS:
-000147 f000 .dw DO_COLON
- PFA_NAME2FLAGS:
-000148 f3e2 .dw XT_FETCHI ; skip to link field
-000149 f045 .dw XT_DOLITERAL
-00014a ff00 .dw $ff00
-00014b f224 .dw XT_AND
-00014c f025 .dw XT_EXIT
-
- .if AMFORTH_NRWW_SIZE > 8000
- .include "dict/appl_8k.inc"
-
-
- .include "words/newest.asm"
-
- ; System Variable
- ; system state
- VE_NEWEST:
-00014d ff06 .dw $ff06
-00014e 656e
-00014f 6577
-000150 7473 .db "newest"
-000151 0140 .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
- XT_NEWEST:
-000152 f053 .dw PFA_DOVARIABLE
- PFA_NEWEST:
-000153 0135 .dw ram_newest
-
- .dseg
-000135 ram_newest: .byte 4
- .include "words/latest.asm"
-
- ; System Variable
- ; system state
- VE_LATEST:
-000154 ff06 .dw $ff06
-000155 616c
-000156 6574
-000157 7473 .db "latest"
-000158 014d .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
- XT_LATEST:
-000159 f053 .dw PFA_DOVARIABLE
- PFA_LATEST:
-00015a 0139 .dw ram_latest
-
- .dseg
-000139 ram_latest: .byte 2
- .include "words/do-create.asm"
-
- ; Compiler
- ; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOCREATE:
-00015b ff08 .dw $ff08
-00015c 6328
-00015d 6572
-00015e 7461
-00015f 2965 .db "(create)"
-000160 0154 .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
- XT_DOCREATE:
-000161 f000 .dw DO_COLON
- PFA_DOCREATE:
- .endif
-000162 f9ce
-000163 02b8 .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
-000164 f0c2
-000165 0152
-000166 f578
-000167 f092 .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
-000168 029d
-000169 0152
-00016a f092 .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
-00016b f025 .DW XT_EXIT
- .include "words/backslash.asm"
-
- ; Compiler
- ; everything up to the end of the current line is a comment
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BACKSLASH:
-00016c 0001 .dw $0001
-00016d 005c .db $5c,0
-00016e 015b .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
- XT_BACKSLASH:
-00016f f000 .dw DO_COLON
- PFA_BACKSLASH:
- .endif
-000170 f9b5 .dw XT_SOURCE
-000171 f101 .dw XT_NIP
-000172 f598 .dw XT_TO_IN
-000173 f092 .dw XT_STORE
-000174 f025 .dw XT_EXIT
- .include "words/l-paren.asm"
-
- ; Compiler
- ; skip everything up to the closing bracket on the same line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LPAREN:
-000175 0001 .dw $0001
-000176 0028 .db "(" ,0
-000177 016c .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
- XT_LPAREN:
-000178 f000 .dw DO_COLON
- PFA_LPAREN:
- .endif
-000179 f045 .dw XT_DOLITERAL
-00017a 0029 .dw ')'
-00017b f9a1 .dw XT_PARSE
-00017c f588 .dw XT_2DROP
-00017d f025 .dw XT_EXIT
-
- .include "words/compile.asm"
-
- ; Dictionary
- ; read the following cell from the dictionary and append it to the current dictionary position.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COMPILE:
-00017e ff07 .dw $ff07
-00017f 6f63
-000180 706d
-000181 6c69
-000182 0065 .db "compile",0
-000183 0175 .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
- XT_COMPILE:
-000184 f000 .dw DO_COLON
- PFA_COMPILE:
- .endif
-000185 f107 .dw XT_R_FROM
-000186 f0c2 .dw XT_DUP
-000187 fbc5 .dw XT_ICELLPLUS
-000188 f110 .dw XT_TO_R
-000189 f3e2 .dw XT_FETCHI
-00018a 018f .dw XT_COMMA
-00018b f025 .dw XT_EXIT
- .include "words/comma.asm"
-
- ; Dictionary
- ; compile 16 bit into flash at DP
- VE_COMMA:
-00018c ff01 .dw $ff01
-00018d 002c .db ',',0 ; ,
-00018e 017e .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
- XT_COMMA:
-00018f f000 .dw DO_COLON
- PFA_COMMA:
-000190 f5c8 .dw XT_DP
-000191 f384 .dw XT_STOREI
-000192 f5c8 .dw XT_DP
-000193 f240 .dw XT_1PLUS
-000194 fbb3 .dw XT_DOTO
-000195 f5c9 .dw PFA_DP
-000196 f025 .dw XT_EXIT
- .include "words/brackettick.asm"
-
- ; Compiler
- ; what ' does in the interpreter mode, do in colon definitions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETTICK:
-000197 0003 .dw $0003
-000198 275b
-000199 005d .db "[']",0
-00019a 018c .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
- XT_BRACKETTICK:
-00019b f000 .dw DO_COLON
- PFA_BRACKETTICK:
- .endif
-00019c f824 .dw XT_TICK
-00019d 01a5 .dw XT_LITERAL
-00019e f025 .dw XT_EXIT
-
-
- .include "words/literal.asm"
-
- ; Compiler
- ; compile a literal in colon defintions
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LITERAL:
-00019f 0007 .dw $0007
-0001a0 696c
-0001a1 6574
-0001a2 6172
-0001a3 006c .db "literal",0
-0001a4 0197 .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
- XT_LITERAL:
-0001a5 f000 .dw DO_COLON
- PFA_LITERAL:
- .endif
-0001a6 0184 .DW XT_COMPILE
-0001a7 f045 .DW XT_DOLITERAL
-0001a8 018f .DW XT_COMMA
-0001a9 f025 .DW XT_EXIT
- .include "words/sliteral.asm"
-
- ; String
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLITERAL:
-0001aa 0008 .dw $0008
-0001ab 6c73
-0001ac 7469
-0001ad 7265
-0001ae 6c61 .db "sliteral"
-0001af 019f .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
- XT_SLITERAL:
-0001b0 f000 .dw DO_COLON
- PFA_SLITERAL:
- .endif
-0001b1 0184 .dw XT_COMPILE
-0001b2 f787 .dw XT_DOSLITERAL ; ( -- addr n)
-0001b3 f795 .dw XT_SCOMMA
-0001b4 f025 .dw XT_EXIT
- .include "words/g-mark.asm"
-
- ; Compiler
- ; places current dictionary position for backward resolves
- ;VE_GMARK:
- ; .dw $ff05
- ; .db ">mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GMARK
- XT_GMARK:
-0001b5 f000 .dw DO_COLON
- PFA_GMARK:
-0001b6 f5c8 .dw XT_DP
-0001b7 0184 .dw XT_COMPILE
-0001b8 ffff .dw -1 ; ffff does not erase flash
-0001b9 f025 .dw XT_EXIT
- .include "words/g-resolve.asm"
-
- ; Compiler
- ; resolve backward jumps
- ;VE_GRESOLVE:
- ; .dw $ff08
- ; .db ">resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_GRESOLVE
- XT_GRESOLVE:
-0001ba f000 .dw DO_COLON
- PFA_GRESOLVE:
-0001bb fb71 .dw XT_QSTACK
-0001bc f5c8 .dw XT_DP
-0001bd f0d5 .dw XT_SWAP
-0001be f384 .dw XT_STOREI
-0001bf f025 .dw XT_EXIT
- .include "words/l_mark.asm"
-
- ; Compiler
- ; place destination for backward branch
- ;VE_LMARK:
- ; .dw $ff05
- ; .db "<mark"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LMARK
- XT_LMARK:
-0001c0 f000 .dw DO_COLON
- PFA_LMARK:
-0001c1 f5c8 .dw XT_DP
-0001c2 f025 .dw XT_EXIT
- .include "words/l_resolve.asm"
-
- ; Compiler
- ; resolve backward branch
- ;VE_LRESOLVE:
- ; .dw $ff08
- ; .db "<resolve"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LRESOLVE
- XT_LRESOLVE:
-0001c3 f000 .dw DO_COLON
- PFA_LRESOLVE:
-0001c4 fb71 .dw XT_QSTACK
-0001c5 018f .dw XT_COMMA
-0001c6 f025 .dw XT_EXIT
-
- .include "words/ahead.asm"
-
- ; Compiler
- ; do a unconditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AHEAD:
-0001c7 0005 .dw $0005
-0001c8 6861
-0001c9 6165
-0001ca 0064 .db "ahead",0
-0001cb 01aa .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
- XT_AHEAD:
-0001cc f000 .dw DO_COLON
- PFA_AHEAD:
- .endif
-0001cd 0184 .dw XT_COMPILE
-0001ce f034 .dw XT_DOBRANCH
-0001cf 01b5 .dw XT_GMARK
-0001d0 f025 .dw XT_EXIT
- .include "words/if.asm"
-
- ; Compiler
- ; start conditional branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_IF:
-0001d1 0002 .dw $0002
-0001d2 6669 .db "if"
-0001d3 01c7 .dw VE_HEAD
- .set VE_HEAD = VE_IF
- XT_IF:
-0001d4 f000 .dw DO_COLON
- PFA_IF:
- .endif
-0001d5 0184 .dw XT_COMPILE
-0001d6 f03e .dw XT_DOCONDBRANCH
-0001d7 01b5 .dw XT_GMARK
-0001d8 f025 .dw XT_EXIT
- .include "words/else.asm"
-
- ; Compiler
- ; resolve the forward reference and place a new unresolved forward reference
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ELSE:
-0001d9 0004 .dw $0004
-0001da 6c65
-0001db 6573 .db "else"
-0001dc 01d1 .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
- XT_ELSE:
-0001dd f000 .dw DO_COLON
- PFA_ELSE:
- .endif
-0001de 0184 .dw XT_COMPILE
-0001df f034 .dw XT_DOBRANCH
-0001e0 01b5 .dw XT_GMARK
-0001e1 f0d5 .dw XT_SWAP
-0001e2 01ba .dw XT_GRESOLVE
-0001e3 f025 .dw XT_EXIT
- .include "words/then.asm"
-
- ; Compiler
- ; finish if
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THEN:
-0001e4 0004 .dw $0004
-0001e5 6874
-0001e6 6e65 .db "then"
-0001e7 01d9 .dw VE_HEAD
- .set VE_HEAD = VE_THEN
- XT_THEN:
-0001e8 f000 .dw DO_COLON
- PFA_THEN:
- .endif
-0001e9 01ba .dw XT_GRESOLVE
-0001ea f025 .dw XT_EXIT
- .include "words/begin.asm"
-
- ; Compiler
- ; put the next location for a transfer of control onto the control flow stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BEGIN:
-0001eb 0005 .dw $0005
-0001ec 6562
-0001ed 6967
-0001ee 006e .db "begin",0
-0001ef 01e4 .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
- XT_BEGIN:
-0001f0 f000 .dw DO_COLON
- PFA_BEGIN:
- .endif
-0001f1 01c0 .dw XT_LMARK
-0001f2 f025 .dw XT_EXIT
- .include "words/while.asm"
-
- ; Compiler
- ; at runtime skip until repeat if non-true
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WHILE:
-0001f3 0005 .dw $0005
-0001f4 6877
-0001f5 6c69
-0001f6 0065 .db "while",0
-0001f7 01eb .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
- XT_WHILE:
-0001f8 f000 .dw DO_COLON
- PFA_WHILE:
- .endif
-0001f9 01d4 .dw XT_IF
-0001fa f0d5 .dw XT_SWAP
-0001fb f025 .dw XT_EXIT
- .include "words/repeat.asm"
-
- ; Compiler
- ; continue execution at dest, resolve orig
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REPEAT:
-0001fc 0006 .dw $0006
-0001fd 6572
-0001fe 6570
-0001ff 7461 .db "repeat"
-000200 01f3 .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
- XT_REPEAT:
-000201 f000 .dw DO_COLON
- PFA_REPEAT:
- .endif
-000202 0215 .dw XT_AGAIN
-000203 01e8 .dw XT_THEN
-000204 f025 .dw XT_EXIT
- .include "words/until.asm"
-
- ; Compiler
- ; finish begin with conditional branch, leaves the loop if true flag at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UNTIL:
-000205 0005 .dw $0005
-000206 6e75
-000207 6974
-000208 006c .db "until",0
-000209 01fc .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
- XT_UNTIL:
-00020a f000 .dw DO_COLON
- PFA_UNTIL:
- .endif
-00020b f045 .dw XT_DOLITERAL
-00020c f03e .dw XT_DOCONDBRANCH
-00020d 018f .dw XT_COMMA
-
-00020e 01c3 .dw XT_LRESOLVE
-00020f f025 .dw XT_EXIT
- .include "words/again.asm"
-
- ; Compiler
- ; compile a jump back to dest
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_AGAIN:
-000210 0005 .dw $0005
-000211 6761
-000212 6961
-000213 006e .db "again",0
-000214 0205 .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
- XT_AGAIN:
-000215 f000 .dw DO_COLON
- PFA_AGAIN:
- .endif
-000216 0184 .dw XT_COMPILE
-000217 f034 .dw XT_DOBRANCH
-000218 01c3 .dw XT_LRESOLVE
-000219 f025 .dw XT_EXIT
- .include "words/do.asm"
-
- ; Compiler
- ; start do .. [+]loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DO:
-00021a 0002 .dw $0002
-00021b 6f64 .db "do"
-00021c 0210 .dw VE_HEAD
- .set VE_HEAD = VE_DO
- XT_DO:
-00021d f000 .dw DO_COLON
- PFA_DO:
-
- .endif
-00021e 0184 .dw XT_COMPILE
-00021f f2ac .dw XT_DODO
-000220 01c0 .dw XT_LMARK
-000221 f165 .dw XT_ZERO
-000222 0278 .dw XT_TO_L
-000223 f025 .dw XT_EXIT
- .include "words/loop.asm"
-
- ; Compiler
- ; compile (loop) and resolve the backward branch
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LOOP:
-000224 0004 .dw $0004
-000225 6f6c
-000226 706f .db "loop"
-000227 021a .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
- XT_LOOP:
-000228 f000 .dw DO_COLON
- PFA_LOOP:
- .endif
-000229 0184 .dw XT_COMPILE
-00022a f2da .dw XT_DOLOOP
-00022b 025f .dw XT_ENDLOOP
-00022c f025 .dw XT_EXIT
- .include "words/plusloop.asm"
-
- ; Compiler
- ; compile (+loop) and resolve branches
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLUSLOOP:
-00022d 0005 .dw $0005
-00022e 6c2b
-00022f 6f6f
-000230 0070 .db "+loop",0
-000231 0224 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
- XT_PLUSLOOP:
-000232 f000 .dw DO_COLON
- PFA_PLUSLOOP:
- .endif
-000233 0184 .dw XT_COMPILE
-000234 f2cb .dw XT_DOPLUSLOOP
-000235 025f .dw XT_ENDLOOP
-000236 f025 .dw XT_EXIT
- .include "words/leave.asm"
-
- ; Compiler
- ; immediatly leave the current DO..LOOP
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LEAVE:
-000237 0005 .dw $0005
-000238 656c
-000239 7661
-00023a 0065 .db "leave",0
-00023b 022d .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
- XT_LEAVE:
-00023c f000 .dw DO_COLON
- PFA_LEAVE:
- .endif
-00023d 0184
-00023e f2e5 .DW XT_COMPILE,XT_UNLOOP
-00023f 01cc
-000240 0278
-000241 f025 .DW XT_AHEAD,XT_TO_L,XT_EXIT
- .include "words/qdo.asm"
-
- ; Compiler
- ; start a ?do .. [+]loop control structure
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_QDO:
-000242 0003 .dw $0003
-000243 643f
-000244 006f .db "?do",0
-000245 0237 .dw VE_HEAD
- .set VE_HEAD = VE_QDO
- XT_QDO:
-000246 f000 .dw DO_COLON
- PFA_QDO:
- .endif
-000247 0184 .dw XT_COMPILE
-000248 024e .dw XT_QDOCHECK
-000249 01d4 .dw XT_IF
-00024a 021d .dw XT_DO
-00024b f0d5 .dw XT_SWAP ; DO sets a 0 marker on the leave stack
-00024c 0278 .dw XT_TO_L ; then follows at the end.
-00024d f025 .dw XT_EXIT
-
- ; there is no special runtime for ?do, the do runtime
- ; gets wrapped with the sequence
- ; ... ?do-check if do ..... loop then
- ; with
- ; : ?do-check ( n1 n2 -- n1 n2 true | false )
- ; 2dup = dup >r if 2drop then r> invert ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QDOCHECK:
-00024e f000 .dw DO_COLON
- PFA_QDOCHECK:
- .endif
-00024f f57f .dw XT_2DUP
-000250 fdaa .dw XT_EQUAL
-000251 f0c2 .dw XT_DUP
-000252 f110 .dw XT_TO_R
-000253 f03e .dw XT_DOCONDBRANCH
-000254 0256 DEST(PFA_QDOCHECK1)
-000255 f588 .dw XT_2DROP
- PFA_QDOCHECK1:
-000256 f107 .dw XT_R_FROM
-000257 f20e .dw XT_INVERT
-000258 f025 .dw XT_EXIT
- .include "words/endloop.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENDLOOP:
-000259 ff07 .dw $ff07
-00025a 6e65
-00025b 6c64
-00025c 6f6f
-00025d 0070 .db "endloop",0
-00025e 0242 .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
- XT_ENDLOOP:
-00025f f000 .dw DO_COLON
- PFA_ENDLOOP:
- .endif
- ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
- ; <resolve backward loop
- ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
- ; resolve LEAVEs
- ; This is a common factor of LOOP and +LOOP.
-
-000260 01c3 .DW XT_LRESOLVE
-000261 026c
-000262 f0ca
-000263 f03e LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
-000264 0268 DEST(LOOP2)
-000265 01e8 .DW XT_THEN
-000266 f034 .dw XT_DOBRANCH
-000267 0261 DEST(LOOP1)
-000268 f025 LOOP2: .DW XT_EXIT
- ; leave address stack
- .include "words/l-from.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_FROM:
-000269 ff02 .dw $ff02
-00026a 3e6c .db "l>"
-00026b 0259 .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
- XT_L_FROM:
-00026c f000 .dw DO_COLON
- PFA_L_FROM:
-
- .endif
- ;Z L> -- x L: x -- move from leave stack
- ; LP @ @ -2 LP +! ;
-
-00026d 028b .dw XT_LP
-00026e f08a .dw XT_FETCH
-00026f f08a .dw XT_FETCH
-000270 f045 .dw XT_DOLITERAL
-000271 fffe .dw -2
-000272 028b .dw XT_LP
-000273 f276 .dw XT_PLUSSTORE
-000274 f025 .dw XT_EXIT
- .include "words/to-l.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_L:
-000275 ff02 .dw $ff02
-000276 6c3e .db ">l"
-000277 0269 .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
- XT_TO_L:
-000278 f000 .dw DO_COLON
- PFA_TO_L:
- .endif
- ;Z >L x -- L: -- x move to leave stack
- ; CELL LP +! LP @ ! ; (L stack grows up)
-
-000279 fdb6 .dw XT_TWO
-00027a 028b .dw XT_LP
-00027b f276 .dw XT_PLUSSTORE
-00027c 028b .dw XT_LP
-00027d f08a .dw XT_FETCH
-00027e f092 .dw XT_STORE
-00027f f025 .dw XT_EXIT
- .include "words/lp0.asm"
-
- ; Stack
- ; start address of leave stack
- VE_LP0:
-000280 ff03 .dw $ff03
-000281 706c
-000282 0030 .db "lp0",0
-000283 0275 .dw VE_HEAD
- .set VE_HEAD = VE_LP0
- XT_LP0:
-000284 f080 .dw PFA_DOVALUE1
- PFA_LP0:
-000285 0052 .dw CFG_LP0
-000286 fbce .dw XT_EDEFERFETCH
-000287 fbd8 .dw XT_EDEFERSTORE
- .include "words/lp.asm"
-
- ; System Variable
- ; leave stack pointer
- VE_LP:
-000288 ff02 .dw $ff02
-000289 706c .db "lp"
-00028a 0280 .dw VE_HEAD
- .set VE_HEAD = VE_LP
- XT_LP:
-00028b f053 .dw PFA_DOVARIABLE
- PFA_LP:
-00028c 013b .dw ram_lp
-
- .dseg
-00013b ram_lp: .byte 2
- .cseg
-
-
- .include "words/create.asm"
-
- ; Dictionary
- ; create a dictionary header. XT is (constant), with the address of the data field of name
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CREATE:
-00028d ff06 .dw $ff06
-00028e 7263
-00028f 6165
-000290 6574 .db "create"
-000291 0288 .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
- XT_CREATE:
-000292 f000 .dw DO_COLON
- PFA_CREATE:
- .endif
-000293 0161 .dw XT_DOCREATE
-000294 02c1 .dw XT_REVEAL
-000295 0184 .dw XT_COMPILE
-000296 f060 .dw PFA_DOCONSTANT
-000297 f025 .dw XT_EXIT
- .include "words/header.asm"
-
- ; Compiler
- ; creates the vocabulary header without XT and data field (PF) in the wordlist wid
- VE_HEADER:
-000298 ff06 .dw $ff06
-000299 6568
-00029a 6461
-00029b 7265 .db "header"
-00029c 028d .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
- XT_HEADER:
-00029d f000 .dw DO_COLON
- PFA_HEADER:
-00029e f5c8 .dw XT_DP ; the new Name Field
-00029f f110 .dw XT_TO_R
-0002a0 f110 .dw XT_TO_R ; ( R: NFA WID )
-0002a1 f0c2 .dw XT_DUP
-0002a2 f139 .dw XT_GREATERZERO
-0002a3 f03e .dw XT_DOCONDBRANCH
-0002a4 02af .dw PFA_HEADER1
-0002a5 f0c2 .dw XT_DUP
-0002a6 f045 .dw XT_DOLITERAL
-0002a7 ff00 .dw $ff00 ; all flags are off (e.g. immediate)
-0002a8 f22d .dw XT_OR
-0002a9 f799 .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
-0002aa f107 .dw XT_R_FROM
-0002ab f370 .dw XT_FETCHE
-0002ac 018f .dw XT_COMMA
-0002ad f107 .dw XT_R_FROM
-0002ae f025 .dw XT_EXIT
-
- PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
-0002af f045 .dw XT_DOLITERAL
-0002b0 fff0 .dw -16
-0002b1 f85b .dw XT_THROW
-
- .include "words/wlscope.asm"
-
- ; Compiler
- ; dynamically place a word in a wordlist. The word name may be changed.
- VE_WLSCOPE:
-0002b2 ff07 .dw $ff07
-0002b3 6c77
-0002b4 6373
-0002b5 706f
-0002b6 0065 .db "wlscope",0
-0002b7 0298 .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
- XT_WLSCOPE:
-0002b8 fc2d .dw PFA_DODEFER1
- PFA_WLSCOPE:
-0002b9 004e .dw CFG_WLSCOPE
-0002ba fbce .dw XT_EDEFERFETCH
-0002bb fbd8 .dw XT_EDEFERSTORE
-
- ; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
- ; which enables the AmForth application to choose the wordlist ( wid ) for the
- ; new voc entry based on the input ( addr len ) string. The name of the new voc
- ; entry ( addr' len' ) may be different from the input string. Note that all
- ; created voc entry types pass through the wlscope mechanism. The default
- ; wlscope action passes the input string to the output without modification and
- ; uses get-current to select the wid.
- .include "words/reveal.asm"
-
- ; Dictionary
- ; makes an entry in a wordlist visible, if not already done.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REVEAL:
-0002bc ff06 .dw $ff06
-0002bd 6572
-0002be 6576
-0002bf 6c61 .db "reveal"
-0002c0 02b2 .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
- XT_REVEAL:
-0002c1 f000 .dw DO_COLON
- PFA_REVEAL:
- .endif
-0002c2 0152
-0002c3 f578
-0002c4 f08a .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
-0002c5 f0ca
-0002c6 f03e .DW XT_QDUP,XT_DOCONDBRANCH
-0002c7 02cc DEST(REVEAL1)
-0002c8 0152
-0002c9 f08a
-0002ca f0d5
-0002cb f34c .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
- ; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
- REVEAL1:
-0002cc f025 .DW XT_EXIT
- .include "words/does.asm"
-
- ; Compiler
- ; organize the XT replacement to call other colon code
- VE_DOES:
-0002cd 0005 .dw $0005
-0002ce 6f64
-0002cf 7365
-0002d0 003e .db "does>",0
-0002d1 02bc .dw VE_HEAD
- .set VE_HEAD = VE_DOES
- XT_DOES:
-0002d2 f000 .dw DO_COLON
- PFA_DOES:
-0002d3 0184 .dw XT_COMPILE
-0002d4 02e5 .dw XT_DODOES
-0002d5 0184 .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
-0002d6 940e .dw $940e ; the address of this compiled
-0002d7 0184 .dw XT_COMPILE ; code will replace the XT of the
-0002d8 02da .dw DO_DODOES ; word that CREATE created
-0002d9 f025 .dw XT_EXIT ;
-
- DO_DODOES: ; ( -- PFA )
-0002da 939a
-0002db 938a savetos
-0002dc 01cb movw tosl, wl
-0002dd 9601 adiw tosl, 1
- ; the following takes the address from a real uC-call
- .if (pclen==3)
- .endif
-0002de 917f pop wh
-0002df 916f pop wl
-
-0002e0 93bf push XH
-0002e1 93af push XL
-0002e2 01db movw XL, wl
-0002e3 940c f004 jmp_ DO_NEXT
-
- ; ( -- )
- ; System
- ; replace the XT written by CREATE to call the code that follows does>
- ;VE_DODOES:
- ; .dw $ff07
- ; .db "(does>)"
- ; .set VE_HEAD = VE_DODOES
- XT_DODOES:
-0002e5 f000 .dw DO_COLON
- PFA_DODOES:
-0002e6 f107 .dw XT_R_FROM
-0002e7 0152 .dw XT_NEWEST
-0002e8 f578 .dw XT_CELLPLUS
-0002e9 f08a .dw XT_FETCH
-0002ea f370 .dw XT_FETCHE
-0002eb fc98 .dw XT_NFA2CFA
-0002ec f384 .dw XT_STOREI
-0002ed f025 .dw XT_EXIT
- .include "words/colon.asm"
-
- ; Compiler
- ; create a named entry in the dictionary, XT is DO_COLON
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_COLON:
-0002ee ff01 .dw $ff01
-0002ef 003a .db ":",0
-0002f0 02cd .dw VE_HEAD
- .set VE_HEAD = VE_COLON
- XT_COLON:
-0002f1 f000 .dw DO_COLON
- PFA_COLON:
- .endif
-0002f2 0161 .dw XT_DOCREATE
-0002f3 02fc .dw XT_COLONNONAME
-0002f4 f0ea .dw XT_DROP
-0002f5 f025 .dw XT_EXIT
- .include "words/colon-noname.asm"
-
- ; Compiler
- ; create an unnamed entry in the dictionary, XT is DO_COLON
- VE_COLONNONAME:
-0002f6 ff07 .dw $ff07
-0002f7 6e3a
-0002f8 6e6f
-0002f9 6d61
-0002fa 0065 .db ":noname",0
-0002fb 02ee .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
- XT_COLONNONAME:
-0002fc f000 .dw DO_COLON
- PFA_COLONNONAME:
-0002fd f5c8 .dw XT_DP
-0002fe f0c2 .dw XT_DUP
-0002ff 0159 .dw XT_LATEST
-000300 f092 .dw XT_STORE
-
-000301 0184 .dw XT_COMPILE
-000302 f000 .dw DO_COLON
-
-000303 0311 .dw XT_RBRACKET
-000304 f025 .dw XT_EXIT
- .include "words/semicolon.asm"
-
- ; Compiler
- ; finish colon defintion, compiles (exit) and returns to interpret state
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SEMICOLON:
-000305 0001 .dw $0001
-000306 003b .db $3b,0
-000307 02f6 .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
- XT_SEMICOLON:
-000308 f000 .dw DO_COLON
- PFA_SEMICOLON:
- .endif
-000309 0184 .dw XT_COMPILE
-00030a f025 .dw XT_EXIT
-00030b 0319 .dw XT_LBRACKET
-00030c 02c1 .dw XT_REVEAL
-00030d f025 .dw XT_EXIT
- .include "words/right-bracket.asm"
-
- ; Compiler
- ; enter compiler mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RBRACKET:
-00030e ff01 .dw $ff01
-00030f 005d .db "]",0
-000310 0305 .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
- XT_RBRACKET:
-000311 f000 .dw DO_COLON
- PFA_RBRACKET:
- .endif
-000312 fdb1 .dw XT_ONE
-000313 f565 .dw XT_STATE
-000314 f092 .dw XT_STORE
-000315 f025 .dw XT_EXIT
- .include "words/left-bracket.asm"
-
- ; Compiler
- ; enter interpreter mode
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_LBRACKET:
-000316 0001 .dw $0001
-000317 005b .db "[",0
-000318 030e .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
- XT_LBRACKET:
-000319 f000 .dw DO_COLON
- PFA_LBRACKET:
- .endif
-00031a f165 .dw XT_ZERO
-00031b f565 .dw XT_STATE
-00031c f092 .dw XT_STORE
-00031d f025 .dw XT_EXIT
- .include "words/variable.asm"
-
- ; Compiler
- ; create a dictionary entry for a variable and allocate 1 cell RAM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_VARIABLE:
-00031e ff08 .dw $ff08
-00031f 6176
-000320 6972
-000321 6261
-000322 656c .db "variable"
-000323 0316 .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
- XT_VARIABLE:
-000324 f000 .dw DO_COLON
- PFA_VARIABLE:
- .endif
-000325 f5d9 .dw XT_HERE
-000326 0330 .dw XT_CONSTANT
-000327 fdb6 .dw XT_TWO
-000328 f5e2 .dw XT_ALLOT
-000329 f025 .dw XT_EXIT
- .include "words/constant.asm"
-
- ; Compiler
- ; create a constant in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_CONSTANT:
-00032a ff08 .dw $ff08
-00032b 6f63
-00032c 736e
-00032d 6174
-00032e 746e .db "constant"
-00032f 031e .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
- XT_CONSTANT:
-000330 f000 .dw DO_COLON
- PFA_CONSTANT:
- .endif
-000331 0161 .dw XT_DOCREATE
-000332 02c1 .dw XT_REVEAL
-000333 0184 .dw XT_COMPILE
-000334 f053 .dw PFA_DOVARIABLE
-000335 018f .dw XT_COMMA
-000336 f025 .dw XT_EXIT
- .include "words/user.asm"
-
- ; Compiler
- ; create a dictionary entry for a user variable at offset n
- VE_USER:
-000337 ff04 .dw $ff04
-000338 7375
-000339 7265 .db "user"
-00033a 032a .dw VE_HEAD
- .set VE_HEAD = VE_USER
- XT_USER:
-00033b f000 .dw DO_COLON
- PFA_USER:
-00033c 0161 .dw XT_DOCREATE
-00033d 02c1 .dw XT_REVEAL
-
-00033e 0184 .dw XT_COMPILE
-00033f f066 .dw PFA_DOUSER
-000340 018f .dw XT_COMMA
-000341 f025 .dw XT_EXIT
-
- .include "words/recurse.asm"
-
- ; Compiler
- ; compile the XT of the word currently being defined into the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECURSE:
-000342 0007 .dw $0007
-000343 6572
-000344 7563
-000345 7372
-000346 0065 .db "recurse",0
-000347 0337 .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
- XT_RECURSE:
-000348 f000 .dw DO_COLON
- PFA_RECURSE:
- .endif
-000349 0159 .dw XT_LATEST
-00034a f08a .dw XT_FETCH
-00034b 018f .dw XT_COMMA
-00034c f025 .dw XT_EXIT
- .include "words/immediate.asm"
-
- ; Compiler
- ; set immediate flag for the most recent word definition
- VE_IMMEDIATE:
-00034d ff09 .dw $ff09
-00034e 6d69
-00034f 656d
-000350 6964
-000351 7461
-000352 0065 .db "immediate",0
-000353 0342 .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
- XT_IMMEDIATE:
-000354 f000 .dw DO_COLON
- PFA_IMMEDIATE:
-000355 03f6 .dw XT_GET_CURRENT
-000356 f370 .dw XT_FETCHE
-000357 f0c2 .dw XT_DUP
-000358 f3e2 .dw XT_FETCHI
-000359 f045 .dw XT_DOLITERAL
-00035a 7fff .dw $7fff
-00035b f224 .dw XT_AND
-00035c f0d5 .dw XT_SWAP
-00035d f384 .dw XT_STOREI
-00035e f025 .dw XT_EXIT
-
- .include "words/bracketchar.asm"
-
- ; Tools
- ; skip leading space delimites, place the first character of the word on the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BRACKETCHAR:
-00035f 0006 .dw $0006
-000360 635b
-000361 6168
-000362 5d72 .db "[char]"
-000363 034d .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
- XT_BRACKETCHAR:
-000364 f000 .dw DO_COLON
- PFA_BRACKETCHAR:
- .endif
-000365 0184 .dw XT_COMPILE
-000366 f045 .dw XT_DOLITERAL
-000367 f904 .dw XT_CHAR
-000368 018f .dw XT_COMMA
-000369 f025 .dw XT_EXIT
- .include "words/abort-string.asm"
-
- ;C i*x x1 -- R: j*x -- x1<>0
- ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORTQUOTE:
-00036a 0006 .dw $0006
-00036b 6261
-00036c 726f
-00036d 2274 .db "abort",'"'
-00036e 035f .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
- XT_ABORTQUOTE:
-00036f f000 .dw DO_COLON
- PFA_ABORTQUOTE:
- .endif
-000370 f4db .dw XT_SQUOTE
-000371 0184 .dw XT_COMPILE
-000372 0381 .dw XT_QABORT
-000373 f025 .DW XT_EXIT
- .include "words/abort.asm"
-
- ; Exceptions
- ; send an exception -1
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABORT:
-000374 ff05 .dw $ff05
-000375 6261
-000376 726f
-000377 0074 .db "abort",0
-000378 036a .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
- XT_ABORT:
-000379 f000 .dw DO_COLON
- PFA_ABORT:
- .endif
-00037a f15c .dw XT_TRUE
-00037b f85b .dw XT_THROW
- .include "words/q-abort.asm"
-
- ; ROT IF ITYPE ABORT THEN 2DROP ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QABORT:
-00037c ff06 .dw $ff06
-00037d 613f
-00037e 6f62
-00037f 7472 .db "?abort"
-000380 0374 .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
- XT_QABORT:
-000381 f000 .dw DO_COLON
- PFA_QABORT:
-
- .endif
-000382 f0f2
-000383 f03e .DW XT_ROT,XT_DOCONDBRANCH
-000384 0387 DEST(QABO1)
-000385 f7ba
-000386 0379 .DW XT_ITYPE,XT_ABORT
-000387 f588
-000388 f025 QABO1: .DW XT_2DROP,XT_EXIT
-
- .include "words/get-stack.asm"
-
- ; Tools
- ; Get a stack from EEPROM
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_STACK:
-000389 ff09 .dw $ff09
-00038a 6567
-00038b 2d74
-00038c 7473
-00038d 6361
-00038e 006b .db "get-stack",0
-00038f 037c .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
- XT_GET_STACK:
-000390 f000 .dw DO_COLON
- .endif
-000391 f0c2 .dw XT_DUP
-000392 f578 .dw XT_CELLPLUS
-000393 f0d5 .dw XT_SWAP
-000394 f370 .dw XT_FETCHE
-000395 f0c2 .dw XT_DUP
-000396 f110 .dw XT_TO_R
-000397 f165 .dw XT_ZERO
-000398 f0d5 .dw XT_SWAP ; go from bigger to smaller addresses
-000399 024e .dw XT_QDOCHECK
-00039a f03e .dw XT_DOCONDBRANCH
-00039b 03a7 DEST(PFA_N_FETCH_E2)
-00039c f2ac .dw XT_DODO
- PFA_N_FETCH_E1:
- ; ( ee-addr )
-00039d f2bd .dw XT_I
-00039e f246 .dw XT_1MINUS
-00039f f572 .dw XT_CELLS ; ( -- ee-addr i*2 )
-0003a0 f0e0 .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
-0003a1 f1ae .dw XT_PLUS ; ( -- ee-addr ee-addr+i
-0003a2 f370 .dw XT_FETCHE ;( -- ee-addr item_i )
-0003a3 f0d5 .dw XT_SWAP ;( -- item_i ee-addr )
-0003a4 f15c .dw XT_TRUE ; shortcut for -1
-0003a5 f2cb .dw XT_DOPLUSLOOP
-0003a6 039d DEST(PFA_N_FETCH_E1)
- PFA_N_FETCH_E2:
-0003a7 f588 .dw XT_2DROP
-0003a8 f107 .dw XT_R_FROM
-0003a9 f025 .dw XT_EXIT
-
- .include "words/set-stack.asm"
-
- ; Tools
- ; Write a stack to EEPROM
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_STACK:
-0003aa ff09 .dw $ff09
-0003ab 6573
-0003ac 2d74
-0003ad 7473
-0003ae 6361
-0003af 006b .db "set-stack",0
-0003b0 0389 .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
- XT_SET_STACK:
-0003b1 f000 .dw DO_COLON
- PFA_SET_STACK:
- .endif
-0003b2 f0e0 .dw XT_OVER
-0003b3 f132 .dw XT_ZEROLESS
-0003b4 f03e .dw XT_DOCONDBRANCH
-0003b5 03b9 DEST(PFA_SET_STACK0)
-0003b6 f045 .dw XT_DOLITERAL
-0003b7 fffc .dw -4
-0003b8 f85b .dw XT_THROW
- PFA_SET_STACK0:
-0003b9 f57f .dw XT_2DUP
-0003ba f34c .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
-0003bb f0d5 .dw XT_SWAP
-0003bc f165 .dw XT_ZERO
-0003bd 024e .dw XT_QDOCHECK
-0003be f03e .dw XT_DOCONDBRANCH
-0003bf 03c6 DEST(PFA_SET_STACK2)
-0003c0 f2ac .dw XT_DODO
- PFA_SET_STACK1:
-0003c1 f578 .dw XT_CELLPLUS ; ( -- i_x e-addr )
-0003c2 f590 .dw XT_TUCK ; ( -- e-addr i_x e-addr
-0003c3 f34c .dw XT_STOREE
-0003c4 f2da .dw XT_DOLOOP
-0003c5 03c1 DEST(PFA_SET_STACK1)
- PFA_SET_STACK2:
-0003c6 f0ea .dw XT_DROP
-0003c7 f025 .dw XT_EXIT
-
- .include "words/map-stack.asm"
-
- ; Tools
- ; Iterate over a stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAPSTACK:
-0003c8 ff09 .dw $ff09
-0003c9 616d
-0003ca 2d70
-0003cb 7473
-0003cc 6361
-0003cd 006b .db "map-stack",0
-0003ce 03aa .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
- XT_MAPSTACK:
-0003cf f000 .dw DO_COLON
- PFA_MAPSTACK:
- .endif
-0003d0 f0c2 .dw XT_DUP
-0003d1 f578 .dw XT_CELLPLUS
-0003d2 f0d5 .dw XT_SWAP
-0003d3 f370 .dw XT_FETCHE
-0003d4 f572 .dw XT_CELLS
-0003d5 fd89 .dw XT_BOUNDS
-0003d6 024e .dw XT_QDOCHECK
-0003d7 f03e .dw XT_DOCONDBRANCH
-0003d8 03eb DEST(PFA_MAPSTACK3)
-0003d9 f2ac .dw XT_DODO
- PFA_MAPSTACK1:
-0003da f2bd .dw XT_I
-0003db f370 .dw XT_FETCHE ; -- i*x XT id
-0003dc f0d5 .dw XT_SWAP
-0003dd f110 .dw XT_TO_R
-0003de f119 .dw XT_R_FETCH
-0003df f02f .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
-0003e0 f0ca .dw XT_QDUP
-0003e1 f03e .dw XT_DOCONDBRANCH
-0003e2 03e7 DEST(PFA_MAPSTACK2)
-0003e3 f107 .dw XT_R_FROM
-0003e4 f0ea .dw XT_DROP
-0003e5 f2e5 .dw XT_UNLOOP
-0003e6 f025 .dw XT_EXIT
- PFA_MAPSTACK2:
-0003e7 f107 .dw XT_R_FROM
-0003e8 fdb6 .dw XT_TWO
-0003e9 f2cb .dw XT_DOPLUSLOOP
-0003ea 03da DEST(PFA_MAPSTACK1)
- PFA_MAPSTACK3:
-0003eb f0ea .dw XT_DROP
-0003ec f165 .dw XT_ZERO
-0003ed f025 .dw XT_EXIT
-
- ;
- ; : map-stack ( i*x XT e-addr -- j*y )
- ; dup cell+ swap @e cells bounds ?do
- ; ( -- i*x XT )
- ; i @e swap >r r@ execute
- ; ?dup if r> drop unloop exit then
- ; r>
- ; 2 +loop drop 0
- ; ;
- .include "words/get-current.asm"
-
- ; Search Order
- ; get the wid of the current compilation word list
- VE_GET_CURRENT:
-0003ee ff0b .dw $ff0b
-0003ef 6567
-0003f0 2d74
-0003f1 7563
-0003f2 7272
-0003f3 6e65
-0003f4 0074 .db "get-current",0
-0003f5 03c8 .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
- XT_GET_CURRENT:
-0003f6 f000 .dw DO_COLON
- PFA_GET_CURRENT:
-0003f7 f045 .dw XT_DOLITERAL
-0003f8 0058 .dw CFG_CURRENT
-0003f9 f370 .dw XT_FETCHE
-0003fa f025 .dw XT_EXIT
- .include "words/get-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_ORDER:
-0003fb ff09 .dw $ff09
-0003fc 6567
-0003fd 2d74
-0003fe 726f
-0003ff 6564
-000400 0072 .db "get-order",0
-000401 03ee .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
- XT_GET_ORDER:
-000402 f000 .dw DO_COLON
- PFA_GET_ORDER:
- .endif
-000403 f045 .dw XT_DOLITERAL
-000404 005c .dw CFG_ORDERLISTLEN
-000405 0390 .dw XT_GET_STACK
-000406 f025 .dw XT_EXIT
- .include "words/cfg-order.asm"
-
- ; Search Order
- ; Get the current search order word list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CFG_ORDER:
-000407 ff09 .dw $ff09
-000408 6663
-000409 2d67
-00040a 726f
-00040b 6564
-00040c 0072 .db "cfg-order",0
-00040d 03fb .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
- XT_CFG_ORDER:
-00040e f053 .dw PFA_DOVARIABLE
- PFA_CFG_ORDER:
- .endif
-00040f 005c .dw CFG_ORDERLISTLEN
- .include "words/compare.asm"
-
- ; String
- ; compares two strings in RAM
- VE_COMPARE:
-000410 ff07 .dw $ff07
-000411 6f63
-000412 706d
-000413 7261
-000414 0065 .db "compare",0
-000415 0407 .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
- XT_COMPARE:
-000416 0417 .dw PFA_COMPARE
- PFA_COMPARE:
-000417 93bf push xh
-000418 93af push xl
-000419 018c movw temp0, tosl
-00041a 9189
-00041b 9199 loadtos
-00041c 01dc movw xl, tosl
-00041d 9189
-00041e 9199 loadtos
-00041f 019c movw temp2, tosl
-000420 9189
-000421 9199 loadtos
-000422 01fc movw zl, tosl
- PFA_COMPARE_LOOP:
-000423 90ed ld temp4, X+
-000424 90f1 ld temp5, Z+
-000425 14ef cp temp4, temp5
-000426 f451 brne PFA_COMPARE_NOTEQUAL
-000427 950a dec temp0
-000428 f019 breq PFA_COMPARE_ENDREACHED2
-000429 952a dec temp2
-00042a f7c1 brne PFA_COMPARE_LOOP
-00042b c001 rjmp PFA_COMPARE_ENDREACHED
- PFA_COMPARE_ENDREACHED2:
-00042c 952a dec temp2
- PFA_COMPARE_ENDREACHED:
-00042d 2b02 or temp0, temp2
-00042e f411 brne PFA_COMPARE_CHECKLASTCHAR
-00042f 2788 clr tosl
-000430 c002 rjmp PFA_COMPARE_DONE
- PFA_COMPARE_CHECKLASTCHAR:
- PFA_COMPARE_NOTEQUAL:
-000431 ef8f ser tosl
-000432 c000 rjmp PFA_COMPARE_DONE
-
- PFA_COMPARE_DONE:
-000433 2f98 mov tosh, tosl
-000434 91af pop xl
-000435 91bf pop xh
-000436 940c f004 jmp_ DO_NEXT
- .include "words/nfa2lfa.asm"
-
- ; System
- ; get the link field address from the name field address
- VE_NFA2LFA:
-000438 ff07 .dw $ff07
-000439 666e
-00043a 3e61
-00043b 666c
-00043c 0061 .db "nfa>lfa",0
-00043d 0410 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
- XT_NFA2LFA:
-00043e f000 .dw DO_COLON
- PFA_NFA2LFA:
-00043f fc8c .dw XT_NAME2STRING
-000440 f240 .dw XT_1PLUS
-000441 f215 .dw XT_2SLASH
-000442 f1ae .dw XT_PLUS
-000443 f025 .dw XT_EXIT
- .elif AMFORTH_NRWW_SIZE > 4000
- .elif AMFORTH_NRWW_SIZE > 2000
- .else
- .endif
- .include "dict_appl.inc"
-
- ; This file contains definitions which are either
- ; optional or application specific. They are placed
- ; in the RWW flash section.
-
- ; The file dict/compiler2.inc contains a number of
- ; non-essential words with compiler functionality.
- ; It is recoomended but not strictly necessairy
- ; to include it. It is already included by default
- ; on atmegas with 8k boot loader sections, but it is
- ; safe to include this file twice.
-
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .set DICT_COMPILER2 = 1
-
- .include "words/set-current.asm"
-
- ; Search Order
- ; set current word list to the given word list wid
- VE_SET_CURRENT:
-000444 ff0b .dw $ff0b
-000445 6573
-000446 2d74
-000447 7563
-000448 7272
-000449 6e65
-00044a 0074 .db "set-current",0
-00044b 0438 .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
- XT_SET_CURRENT:
-00044c f000 .dw DO_COLON
- PFA_SET_CURRENT:
-00044d f045 .dw XT_DOLITERAL
-00044e 0058 .dw CFG_CURRENT
-00044f f34c .dw XT_STOREE
-000450 f025 .dw XT_EXIT
- .include "words/wordlist.asm"
-
- ; Search Order
- ; create a new, empty wordlist
- VE_WORDLIST:
-000451 ff08 .dw $ff08
-000452 6f77
-000453 6472
-000454 696c
-000455 7473 .db "wordlist"
-000456 0444 .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
- XT_WORDLIST:
-000457 f000 .dw DO_COLON
- PFA_WORDLIST:
-000458 f5d1 .dw XT_EHERE
-000459 f165 .dw XT_ZERO
-00045a f0e0 .dw XT_OVER
-00045b f34c .dw XT_STOREE
-00045c f0c2 .dw XT_DUP
-00045d f578 .dw XT_CELLPLUS
-00045e fbb3 .dw XT_DOTO
-00045f f5d2 .dw PFA_EHERE
-000460 f025 .dw XT_EXIT
-
- .include "words/forth-wordlist.asm"
-
- ; Search Order
- ; get the system default word list
- VE_FORTHWORDLIST:
-000461 ff0e .dw $ff0e
-000462 6f66
-000463 7472
-000464 2d68
-000465 6f77
-000466 6472
-000467 696c
-000468 7473 .db "forth-wordlist"
-000469 0451 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
- XT_FORTHWORDLIST:
-00046a f053 .dw PFA_DOVARIABLE
- PFA_FORTHWORDLIST:
-00046b 005a .dw CFG_FORTHWORDLIST
- .include "words/set-order.asm"
-
- ; Search Order
- ; replace the search order list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_ORDER:
-00046c ff09 .dw $ff09
-00046d 6573
-00046e 2d74
-00046f 726f
-000470 6564
-000471 0072 .db "set-order",0
-000472 0461 .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
- XT_SET_ORDER:
-000473 f000 .dw DO_COLON
- PFA_SET_ORDER:
- .endif
-000474 f045 .dw XT_DOLITERAL
-000475 005c .dw CFG_ORDERLISTLEN
-000476 03b1 .dw XT_SET_STACK
-000477 f025 .dw XT_EXIT
-
- .include "words/set-recognizer.asm"
-
- ; Interpreter
- ; replace the recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SET_RECOGNIZERS:
-000478 ff0f .dw $ff0f
-000479 6573
-00047a 2d74
-00047b 6572
-00047c 6f63
-00047d 6e67
-00047e 7a69
-00047f 7265
-000480 0073 .db "set-recognizers",0
-000481 046c .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
- XT_SET_RECOGNIZERS:
-000482 f000 .dw DO_COLON
- PFA_SET_RECOGNIZERS:
- .endif
-000483 f045 .dw XT_DOLITERAL
-000484 006e .dw CFG_RECOGNIZERLISTLEN
-000485 03b1 .dw XT_SET_STACK
-000486 f025 .dw XT_EXIT
-
- .include "words/get-recognizer.asm"
-
- ; Interpreter
- ; Get the current recognizer list
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_GET_RECOGNIZERS:
-000487 ff0f .dw $ff0f
-000488 6567
-000489 2d74
-00048a 6572
-00048b 6f63
-00048c 6e67
-00048d 7a69
-00048e 7265
-00048f 0073 .db "get-recognizers",0
-000490 0478 .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
- XT_GET_RECOGNIZERS:
-000491 f000 .dw DO_COLON
- PFA_GET_RECOGNIZERS:
- .endif
-000492 f045 .dw XT_DOLITERAL
-000493 006e .dw CFG_RECOGNIZERLISTLEN
-000494 0390 .dw XT_GET_STACK
-000495 f025 .dw XT_EXIT
- .include "words/code.asm"
-
- ; Compiler
- ; create named entry in the dictionary, XT is the data field
- VE_CODE:
-000496 ff04 .dw $ff04
-000497 6f63
-000498 6564 .db "code"
-000499 0487 .dw VE_HEAD
- .set VE_HEAD = VE_CODE
- XT_CODE:
-00049a f000 .dw DO_COLON
- PFA_CODE:
-00049b 0161 .dw XT_DOCREATE
-00049c 02c1 .dw XT_REVEAL
-00049d f5c8 .dw XT_DP
-00049e fbc5 .dw XT_ICELLPLUS
-00049f 018f .dw XT_COMMA
-0004a0 f025 .dw XT_EXIT
- .include "words/end-code.asm"
-
- ; Compiler
- ; finish a code definition
- VE_ENDCODE:
-0004a1 ff08 .dw $ff08
-0004a2 6e65
-0004a3 2d64
-0004a4 6f63
-0004a5 6564 .db "end-code"
-0004a6 0496 .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
- XT_ENDCODE:
-0004a7 f000 .dw DO_COLON
- PFA_ENDCODE:
-0004a8 0184 .dw XT_COMPILE
-0004a9 940c .dw $940c
-0004aa 0184 .dw XT_COMPILE
-0004ab f004 .dw DO_NEXT
-0004ac f025 .dw XT_EXIT
- .include "words/marker.asm"
-
- ; System Value
- ; The eeprom address until which MARKER saves and restores the eeprom data.
- VE_MARKER:
-0004ad ff08 .dw $ff08
-0004ae 6d28
-0004af 7261
-0004b0 656b
-0004b1 2972 .db "(marker)"
-0004b2 04a1 .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
- XT_MARKER:
-0004b3 f080 .dw PFA_DOVALUE1
- PFA_MARKER:
-0004b4 007a .dw EE_MARKER
-0004b5 fbce .dw XT_EDEFERFETCH
-0004b6 fbd8 .dw XT_EDEFERSTORE
- .include "words/postpone.asm"
-
- ; Compiler
- ; Append the compilation semantics of "name" to the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_POSTPONE:
-0004b7 0008 .dw $0008
-0004b8 6f70
-0004b9 7473
-0004ba 6f70
-0004bb 656e .db "postpone"
-0004bc 04ad .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
- XT_POSTPONE:
-0004bd f000 .dw DO_COLON
- PFA_POSTPONE:
- .endif
-0004be f9ce .dw XT_PARSENAME
-0004bf fae6 .dw XT_FORTHRECOGNIZER
-0004c0 faf1 .dw XT_RECOGNIZE
-0004c1 f0c2 .dw XT_DUP
-0004c2 f110 .dw XT_TO_R
-0004c3 fbc5 .dw XT_ICELLPLUS
-0004c4 fbc5 .dw XT_ICELLPLUS
-0004c5 f3e2 .dw XT_FETCHI
-0004c6 f02f .dw XT_EXECUTE
-0004c7 f107 .dw XT_R_FROM
-0004c8 fbc5 .dw XT_ICELLPLUS
-0004c9 f3e2 .dw XT_FETCHI
-0004ca 018f .dw XT_COMMA
-0004cb f025 .dw XT_EXIT
- .endif
-
- ; turnkey is always needed and application specific
- .include "words/applturnkey.asm"
-
- ; R( -- )
- ; application specific turnkey action
- VE_APPLTURNKEY:
-0004cc ff0b .dw $ff0b
-0004cd 7061
-0004ce 6c70
-0004cf 7574
-0004d0 6e72
-0004d1 656b
-0004d2 0079 .db "applturnkey",0
-0004d3 04b7 .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
- XT_APPLTURNKEY:
-0004d4 f000 .dw DO_COLON
- PFA_APPLTURNKEY:
-0004d5 00da .dw XT_USART
-
- .if WANT_INTERRUPTS == 1
-0004d6 f493 .dw XT_INTON
- .endif
-0004d7 fb7e .dw XT_DOT_VER
-0004d8 f025 .dw XT_EXIT
-
- ; the command .s has many flavors. the one in the
- ; core directory prints the TOS on the *left* hand side.
- ; lib/tools/dot-s.frt has a .s for the opposite.
- .include "words/dot-s.asm"
-
- ; Tools
- ; stack dump
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTS:
-0004d9 ff02 .dw $ff02
-0004da 732e .db ".s"
-0004db 04cc .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
- XT_DOTS:
-0004dc f000 .dw DO_COLON
- PFA_DOTS:
- .endif
-0004dd fabb .dw XT_DEPTH
-0004de f462 .dw XT_UDOT
-0004df f7fc .dw XT_SPACE
-0004e0 fabb .dw XT_DEPTH
-0004e1 f165 .dw XT_ZERO
-0004e2 024e .dw XT_QDOCHECK
-0004e3 f03e .dw XT_DOCONDBRANCH
-0004e4 04eb DEST(PFA_DOTS2)
-0004e5 f2ac .dw XT_DODO
- PFA_DOTS1:
-0004e6 f2bd .dw XT_I
-0004e7 f4c9 .dw XT_PICK
-0004e8 f462 .dw XT_UDOT
-0004e9 f2da .dw XT_DOLOOP
-0004ea 04e6 DEST(PFA_DOTS1)
- PFA_DOTS2:
-0004eb f025 .dw XT_EXIT
-
- ; print the date and time the amforth hex files are created
- ; comment the next line if not needed. Depends on a make/ant
- ; rule to create the actual include file from a template.
- .include "words/build-info.asm"
-
- ; R( -- )
- ; Build Info as flash string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BUILDINFO:
-0004ec ff0a .dw $ff0a
-0004ed 7562
-0004ee 6c69
-0004ef 2d64
-0004f0 6e69
-0004f1 6f66 .db "build-info"
-0004f2 04d9 .dw VE_HEAD
- .set VE_HEAD = VE_BUILDINFO
- XT_BUILDINFO:
-0004f3 f000 .dw DO_COLON
- PFA_BUILDINFO:
-0004f4 f787 .dw XT_DOSLITERAL
-0004f5 0015 .dw 21
-0004f6 7041
-0004f7 2072
-0004f8 3033
-0004f9 202c
-0004fa 3032
-0004fb 3731
-0004fc 3220
-0004fd 3a30
-0004fe 3031
-0004ff 313a
-words/build-info.asm(24): warning: .cseg .db misalignment - padding zero byte
-000500 0034 .db "Apr 30, 2017 20:10:14"
- .endif
-000501 f025 .dw XT_EXIT
-
- ; now add words which are either not included by default but
- ; part of amforth (e.g. words for counted strings) or add
- ; your own ones (from the words directory in this one)
- .include "words/place.asm"
-
- ; String
- ; copy string as counted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PLACE:
-000502 ff05 .dw $ff05
-000503 6c70
-000504 6361
-000505 0065 .db "place",0
-000506 04ec .dw VE_HEAD
- .set VE_HEAD = VE_PLACE
- XT_PLACE:
-000507 f000 .dw DO_COLON
- PFA_PLACE:
- .endif
-000508 f57f .dw XT_2DUP ; ( -- addr1 len1 addr2 len1 addr2)
-000509 f09e .dw XT_CSTORE ; ( -- addr1 len1 addr2)
-00050a f240 .dw XT_1PLUS ; ( -- addr1 len1 addr2')
-00050b f0d5 .dw XT_SWAP ; ( -- addr1 addr2' len1)
-00050c fd17 .dw XT_CMOVE ; ( --- )
-00050d f025 .dw XT_EXIT
- .include "words/word.asm"
-
- ; Tools
- ; skip leading delimiter character and parse SOURCE until the next delimiter. copy the word to HERE
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WORD:
-00050e ff04 .dw $ff04
-00050f 6f77
-000510 6472 .db "word"
-000511 0502 .dw VE_HEAD
- .set VE_HEAD = VE_WORD
- XT_WORD:
-000512 f000 .dw DO_COLON
- PFA_WORD:
- .endif
-000513 f9d2 .dw XT_SKIPSCANCHAR ; factor for both parse/word
- ; move to HERE
-000514 f5d9 .dw XT_HERE
-000515 0507 .dw XT_PLACE
- ; leave result
-000516 f5d9 .dw XT_HERE
-000517 f025 .dw XT_EXIT
-
- .set DPSTART = pc
- .if(pc>AMFORTH_RO_SEG)
- .endif
-
- .org AMFORTH_RO_SEG
- .include "amforth-interpreter.asm"
-
-
- DO_COLON:
-00f000 93bf push XH
-00f001 93af push XL ; PUSH IP
-00f002 01db movw XL, wl
-00f003 9611 adiw xl, 1
- DO_NEXT:
- .if WANT_INTERRUPTS == 1
-00f004 14b2 cp isrflag, zerol
-00f005 f499 brne DO_INTERRUPT
- .endif
-00f006 01fd movw zl, XL ; READ IP
-00f007 2755
-00f008 0fee
-00f009 1fff
-00f00a 1f55
-00f00b bf5b
-00f00c 9167
-00f00d 9177 readflashcell wl, wh
-00f00e 9611 adiw XL, 1 ; INC IP
-
- DO_EXECUTE:
-00f00f 01fb movw zl, wl
-00f010 2755
-00f011 0fee
-00f012 1fff
-00f013 1f55
-00f014 bf5b
-00f015 9107
-00f016 9117 readflashcell temp0,temp1
-00f017 01f8 movw zl, temp0
-00f018 9409 ijmp
-
- .if WANT_INTERRUPTS == 1
- DO_INTERRUPT:
- ; here we deal with interrupts the forth way
-00f019 939a
-00f01a 938a savetos
-00f01b 2d8b mov tosl, isrflag
-00f01c 2799 clr tosh
-00f01d 24bb clr isrflag
-00f01e eb6c ldi wl, LOW(XT_ISREXEC)
-00f01f ef74 ldi wh, HIGH(XT_ISREXEC)
-00f020 cfee rjmp DO_EXECUTE
- .include "dict/nrww.inc"
-
- ; section together with the forth inner interpreter
-
- .include "words/exit.asm"
-
- ; Compiler
- ; end of current colon word
- VE_EXIT:
-00f021 ff04 .dw $ff04
-00f022 7865
-00f023 7469 .db "exit"
-00f024 050e .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
- XT_EXIT:
-00f025 f026 .dw PFA_EXIT
- PFA_EXIT:
-00f026 91af pop XL
-00f027 91bf pop XH
-00f028 cfdb jmp_ DO_NEXT
- .include "words/execute.asm"
-
- ; System
- ; execute XT
- VE_EXECUTE:
-00f029 ff07 .dw $ff07
-00f02a 7865
-00f02b 6365
-00f02c 7475
-00f02d 0065 .db "execute",0
-00f02e f021 .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
- XT_EXECUTE:
-00f02f f030 .dw PFA_EXECUTE
- PFA_EXECUTE:
-00f030 01bc movw wl, tosl
-00f031 9189
-00f032 9199 loadtos
-00f033 cfdb jmp_ DO_EXECUTE
- .include "words/dobranch.asm"
-
- ; System
- ; runtime of branch
- ;VE_DOBRANCH:
- ; .dw $ff08
- ; .db "(branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOBRANCH
- XT_DOBRANCH:
-00f034 f035 .dw PFA_DOBRANCH
- PFA_DOBRANCH:
-00f035 01fd movw zl, XL
-00f036 2755
-00f037 0fee
-00f038 1fff
-00f039 1f55
-00f03a bf5b
-00f03b 91a7
-00f03c 91b7 readflashcell XL,XH
-00f03d cfc6 jmp_ DO_NEXT
- .include "words/docondbranch.asm"
-
- ; System
- ; runtime of ?branch
- ;VE_DOCONDBRANCH:
- ; .dw $ff09
- ; .db "(?branch)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONDBRANCH
- XT_DOCONDBRANCH:
-00f03e f03f .dw PFA_DOCONDBRANCH
- PFA_DOCONDBRANCH:
-00f03f 2b98 or tosh, tosl
-00f040 9189
-00f041 9199 loadtos
-00f042 f391 brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
-00f043 9611 adiw XL, 1
-00f044 cfbf jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/doliteral.asm"
-
- ; System
- ; runtime of literal
- ;VE_DOLITERAL:
- ; .dw $ff09
- ; .db "(literal)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLITERAL
- XT_DOLITERAL:
-00f045 f046 .dw PFA_DOLITERAL
- PFA_DOLITERAL:
-00f046 939a
-00f047 938a savetos
-00f048 01fd movw zl, xl
-00f049 2755
-00f04a 0fee
-00f04b 1fff
-00f04c 1f55
-00f04d bf5b
-00f04e 9187
-00f04f 9197 readflashcell tosl,tosh
-00f050 9611 adiw xl, 1
-00f051 cfb2 jmp_ DO_NEXT
-
- .include "words/dovariable.asm"
-
- ; System
- ; puts content of parameter field (1 cell) to TOS
- ;VE_DOVARIABLE:
- ; .dw $ff0a
- ; .db "(variable)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOVARIABLE
- XT_DOVARIABLE:
-00f052 f053 .dw PFA_DOVARIABLE
- PFA_DOVARIABLE:
-00f053 939a
-00f054 938a savetos
-00f055 01fb movw zl, wl
-00f056 9631 adiw zl,1
-00f057 2755
-00f058 0fee
-00f059 1fff
-00f05a 1f55
-00f05b bf5b
-00f05c 9187
-00f05d 9197 readflashcell tosl,tosh
-00f05e cfa5 jmp_ DO_NEXT
- .include "words/doconstant.asm"
-
- ; System
- ; place data field address on TOS
- ;VE_DOCONSTANT:
- ; .dw $ff0a
- ; .db "(constant)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOCONSTANT
- XT_DOCONSTANT:
-00f05f f060 .dw PFA_DOCONSTANT
- PFA_DOCONSTANT:
-00f060 939a
-00f061 938a savetos
-00f062 01cb movw tosl, wl
-00f063 9601 adiw tosl, 1
-00f064 cf9f jmp_ DO_NEXT
- .include "words/douser.asm"
-
- ; System
- ; runtime part of user
- ;VE_DOUSER:
- ; .dw $ff06
- ; .db "(user)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOUSER
- XT_DOUSER:
-00f065 f066 .dw PFA_DOUSER
- PFA_DOUSER:
-00f066 939a
-00f067 938a savetos
-00f068 01fb movw zl, wl
-00f069 9631 adiw zl, 1
-00f06a 2755
-00f06b 0fee
-00f06c 1fff
-00f06d 1f55
-00f06e bf5b
-00f06f 9187
-00f070 9197 readflashcell tosl,tosh
-00f071 0d84 add tosl, upl
-00f072 1d95 adc tosh, uph
-00f073 cf90 jmp_ DO_NEXT
- .include "words/do-value.asm"
-
- ; System
- ; runtime of value
- VE_DOVALUE:
-00f074 ff07 .dw $ff07
-00f075 7628
-00f076 6c61
-00f077 6575
-00f078 0029 .db "(value)", 0
-00f079 f029 .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
- XT_DOVALUE:
-00f07a f000 .dw DO_COLON
- PFA_DOVALUE:
-00f07b 0161 .dw XT_DOCREATE
-00f07c 02c1 .dw XT_REVEAL
-00f07d 0184 .dw XT_COMPILE
-00f07e f080 .dw PFA_DOVALUE1
-00f07f f025 .dw XT_EXIT
- PFA_DOVALUE1:
-00f080 940e 02da call_ DO_DODOES
-00f082 f0c2 .dw XT_DUP
-00f083 fbc5 .dw XT_ICELLPLUS
-00f084 f3e2 .dw XT_FETCHI
-00f085 f02f .dw XT_EXECUTE
-00f086 f025 .dw XT_EXIT
-
- ; : (value) <builds does> dup icell+ @i execute ;
- .include "words/fetch.asm"
-
- ; Memory
- ; read 1 cell from RAM address
- VE_FETCH:
-00f087 ff01 .dw $ff01
-00f088 0040 .db "@",0
-00f089 f074 .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
- XT_FETCH:
-00f08a f08b .dw PFA_FETCH
- PFA_FETCH:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHRAM:
-00f08b 01fc movw zl, tosl
- ; low byte is read before the high byte
-00f08c 9181 ld tosl, z+
-00f08d 9191 ld tosh, z+
-00f08e cf75 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store.asm"
-
- ; Memory
- ; write n to RAM memory at addr, low byte first
- VE_STORE:
-00f08f ff01 .dw $ff01
-00f090 0021 .db "!",0
-00f091 f087 .dw VE_HEAD
- .set VE_HEAD = VE_STORE
- XT_STORE:
-00f092 f093 .dw PFA_STORE
- PFA_STORE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STORERAM:
-00f093 01fc movw zl, tosl
-00f094 9189
-00f095 9199 loadtos
- ; the high byte is written before the low byte
-00f096 8391 std Z+1, tosh
-00f097 8380 std Z+0, tosl
-00f098 9189
-00f099 9199 loadtos
-00f09a cf69 jmp_ DO_NEXT
- .if WANT_UNIFIED == 1
- .endif
- .include "words/cstore.asm"
-
- ; Memory
- ; store a single byte to RAM address
- VE_CSTORE:
-00f09b ff02 .dw $ff02
-00f09c 2163 .db "c!"
-00f09d f08f .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
- XT_CSTORE:
-00f09e f09f .dw PFA_CSTORE
- PFA_CSTORE:
-00f09f 01fc movw zl, tosl
-00f0a0 9189
-00f0a1 9199 loadtos
-00f0a2 8380 st Z, tosl
-00f0a3 9189
-00f0a4 9199 loadtos
-00f0a5 cf5e jmp_ DO_NEXT
- .include "words/cfetch.asm"
-
- ; Memory
- ; fetch a single byte from memory mapped locations
- VE_CFETCH:
-00f0a6 ff02 .dw $ff02
-00f0a7 4063 .db "c@"
-00f0a8 f09b .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
- XT_CFETCH:
-00f0a9 f0aa .dw PFA_CFETCH
- PFA_CFETCH:
-00f0aa 01fc movw zl, tosl
-00f0ab 2799 clr tosh
-00f0ac 8180 ld tosl, Z
-00f0ad cf56 jmp_ DO_NEXT
- .include "words/fetch-u.asm"
-
- ; Memory
- ; read 1 cell from USER area
- VE_FETCHU:
-00f0ae ff02 .dw $ff02
-00f0af 7540 .db "@u"
-00f0b0 f0a6 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
- XT_FETCHU:
-00f0b1 f000 .dw DO_COLON
- PFA_FETCHU:
-00f0b2 f313 .dw XT_UP_FETCH
-00f0b3 f1ae .dw XT_PLUS
-00f0b4 f08a .dw XT_FETCH
-00f0b5 f025 .dw XT_EXIT
- .include "words/store-u.asm"
-
- ; Memory
- ; write n to USER area at offset
- VE_STOREU:
-00f0b6 ff02 .dw $ff02
-00f0b7 7521 .db "!u"
-00f0b8 f0ae .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
- XT_STOREU:
-00f0b9 f000 .dw DO_COLON
- PFA_STOREU:
-00f0ba f313 .dw XT_UP_FETCH
-00f0bb f1ae .dw XT_PLUS
-00f0bc f092 .dw XT_STORE
-00f0bd f025 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/dup.asm"
-
- ; Stack
- ; duplicate TOS
- VE_DUP:
-00f0be ff03 .dw $ff03
-00f0bf 7564
-00f0c0 0070 .db "dup",0
-00f0c1 f0b6 .dw VE_HEAD
- .set VE_HEAD = VE_DUP
- XT_DUP:
-00f0c2 f0c3 .dw PFA_DUP
- PFA_DUP:
-00f0c3 939a
-00f0c4 938a savetos
-00f0c5 cf3e jmp_ DO_NEXT
- .include "words/qdup.asm"
-
- ; Stack
- ; duplicate TOS if non-zero
- VE_QDUP:
-00f0c6 ff04 .dw $ff04
-00f0c7 643f
-00f0c8 7075 .db "?dup"
-00f0c9 f0be .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
- XT_QDUP:
-00f0ca f0cb .dw PFA_QDUP
- PFA_QDUP:
-00f0cb 2f08 mov temp0, tosl
-00f0cc 2b09 or temp0, tosh
-00f0cd f011 breq PFA_QDUP1
-00f0ce 939a
-00f0cf 938a savetos
- PFA_QDUP1:
-00f0d0 cf33 jmp_ DO_NEXT
- .include "words/swap.asm"
-
- ; Stack
- ; swaps the two top level stack cells
- VE_SWAP:
-00f0d1 ff04 .dw $ff04
-00f0d2 7773
-00f0d3 7061 .db "swap"
-00f0d4 f0c6 .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
- XT_SWAP:
-00f0d5 f0d6 .dw PFA_SWAP
- PFA_SWAP:
-00f0d6 018c movw temp0, tosl
-00f0d7 9189
-00f0d8 9199 loadtos
-00f0d9 931a st -Y, temp1
-00f0da 930a st -Y, temp0
-00f0db cf28 jmp_ DO_NEXT
- .include "words/over.asm"
-
- ; Stack
- ; Place a copy of x1 on top of the stack
- VE_OVER:
-00f0dc ff04 .dw $ff04
-00f0dd 766f
-00f0de 7265 .db "over"
-00f0df f0d1 .dw VE_HEAD
- .set VE_HEAD = VE_OVER
- XT_OVER:
-00f0e0 f0e1 .dw PFA_OVER
- PFA_OVER:
-00f0e1 939a
-00f0e2 938a savetos
-00f0e3 818a ldd tosl, Y+2
-00f0e4 819b ldd tosh, Y+3
-
-00f0e5 cf1e jmp_ DO_NEXT
- .include "words/drop.asm"
-
- ; Stack
- ; drop TOS
- VE_DROP:
-00f0e6 ff04 .dw $ff04
-00f0e7 7264
-00f0e8 706f .db "drop"
-00f0e9 f0dc .dw VE_HEAD
- .set VE_HEAD = VE_DROP
- XT_DROP:
-00f0ea f0eb .dw PFA_DROP
- PFA_DROP:
-00f0eb 9189
-00f0ec 9199 loadtos
-00f0ed cf16 jmp_ DO_NEXT
- .include "words/rot.asm"
-
- ; Stack
- ; rotate the three top level cells
- VE_ROT:
-00f0ee ff03 .dw $ff03
-00f0ef 6f72
-00f0f0 0074 .db "rot",0
-00f0f1 f0e6 .dw VE_HEAD
- .set VE_HEAD = VE_ROT
- XT_ROT:
-00f0f2 f0f3 .dw PFA_ROT
- PFA_ROT:
-00f0f3 018c movw temp0, tosl
-00f0f4 9129 ld temp2, Y+
-00f0f5 9139 ld temp3, Y+
-00f0f6 9189
-00f0f7 9199 loadtos
-
-00f0f8 933a st -Y, temp3
-00f0f9 932a st -Y, temp2
-00f0fa 931a st -Y, temp1
-00f0fb 930a st -Y, temp0
-
-00f0fc cf07 jmp_ DO_NEXT
- .include "words/nip.asm"
-
- ; Stack
- ; Remove Second of Stack
- VE_NIP:
-00f0fd ff03 .dw $ff03
-00f0fe 696e
-00f0ff 0070 .db "nip",0
-00f100 f0ee .dw VE_HEAD
- .set VE_HEAD = VE_NIP
- XT_NIP:
-00f101 f102 .dw PFA_NIP
- PFA_NIP:
-00f102 9622 adiw yl, 2
-00f103 cf00 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/r_from.asm"
-
- ; Stack
- ; move TOR to TOS
- VE_R_FROM:
-00f104 ff02 .dw $ff02
-00f105 3e72 .db "r>"
-00f106 f0fd .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
- XT_R_FROM:
-00f107 f108 .dw PFA_R_FROM
- PFA_R_FROM:
-00f108 939a
-00f109 938a savetos
-00f10a 918f pop tosl
-00f10b 919f pop tosh
-00f10c cef7 jmp_ DO_NEXT
- .include "words/to_r.asm"
-
- ; Stack
- ; move TOS to TOR
- VE_TO_R:
-00f10d ff02 .dw $ff02
-00f10e 723e .db ">r"
-00f10f f104 .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
- XT_TO_R:
-00f110 f111 .dw PFA_TO_R
- PFA_TO_R:
-00f111 939f push tosh
-00f112 938f push tosl
-00f113 9189
-00f114 9199 loadtos
-00f115 ceee jmp_ DO_NEXT
- .include "words/r_fetch.asm"
-
- ; Stack
- ; fetch content of TOR
- VE_R_FETCH:
-00f116 ff02 .dw $ff02
-00f117 4072 .db "r@"
-00f118 f10d .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
- XT_R_FETCH:
-00f119 f11a .dw PFA_R_FETCH
- PFA_R_FETCH:
-00f11a 939a
-00f11b 938a savetos
-00f11c 918f pop tosl
-00f11d 919f pop tosh
-00f11e 939f push tosh
-00f11f 938f push tosl
-00f120 cee3 jmp_ DO_NEXT
-
-
- .include "words/not-equal.asm"
-
- ; Compare
- ; true if n1 is not equal to n2
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOTEQUAL:
-00f121 ff02 .dw $ff02
-00f122 3e3c .db "<>"
-00f123 f116 .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
- XT_NOTEQUAL:
-00f124 f000 .dw DO_COLON
- PFA_NOTEQUAL:
- .endif
-
-00f125 fdaa
-00f126 f12b
-00f127 f025 .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
- .include "words/equalzero.asm"
-
- ; Compare
- ; compare with 0 (zero)
- VE_ZEROEQUAL:
-00f128 ff02 .dw $ff02
-00f129 3d30 .db "0="
-00f12a f121 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
- XT_ZEROEQUAL:
-00f12b f12c .dw PFA_ZEROEQUAL
- PFA_ZEROEQUAL:
-00f12c 2b98 or tosh, tosl
-00f12d f5d1 brne PFA_ZERO1
-00f12e c030 rjmp PFA_TRUE1
- .include "words/lesszero.asm"
-
- ; Compare
- ; compare with zero
- VE_ZEROLESS:
-00f12f ff02 .dw $ff02
-00f130 3c30 .db "0<"
-00f131 f128 .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
- XT_ZEROLESS:
-00f132 f133 .dw PFA_ZEROLESS
- PFA_ZEROLESS:
-00f133 fd97 sbrc tosh,7
-00f134 c02a rjmp PFA_TRUE1
-00f135 c032 rjmp PFA_ZERO1
- .include "words/greaterzero.asm"
-
- ; Compare
- ; true if n1 is greater than 0
- VE_GREATERZERO:
-00f136 ff02 .dw $ff02
-00f137 3e30 .db "0>"
-00f138 f12f .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
- XT_GREATERZERO:
-00f139 f13a .dw PFA_GREATERZERO
- PFA_GREATERZERO:
-00f13a 1582 cp tosl, zerol
-00f13b 0593 cpc tosh, zeroh
-00f13c f15c brlt PFA_ZERO1
-00f13d f151 brbs 1, PFA_ZERO1
-00f13e c020 rjmp PFA_TRUE1
- .include "words/d-greaterzero.asm"
-
- ; Compare
- ; compares if a double double cell number is greater 0
- VE_DGREATERZERO:
-00f13f ff03 .dw $ff03
-00f140 3064
-00f141 003e .db "d0>",0
-00f142 f136 .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
- XT_DGREATERZERO:
-00f143 f144 .dw PFA_DGREATERZERO
- PFA_DGREATERZERO:
-00f144 1582 cp tosl, zerol
-00f145 0593 cpc tosh, zeroh
-00f146 9189
-00f147 9199 loadtos
-00f148 0582 cpc tosl, zerol
-00f149 0593 cpc tosh, zeroh
-00f14a f0ec brlt PFA_ZERO1
-00f14b f0e1 brbs 1, PFA_ZERO1
-00f14c c012 rjmp PFA_TRUE1
- .include "words/d-lesszero.asm"
-
- ; Compare
- ; compares if a double double cell number is less than 0
- VE_DXT_ZEROLESS:
-00f14d ff03 .dw $ff03
-00f14e 3064
-00f14f 003c .db "d0<",0
-00f150 f13f .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
- XT_DXT_ZEROLESS:
-00f151 f152 .dw PFA_DXT_ZEROLESS
- PFA_DXT_ZEROLESS:
-00f152 9622 adiw Y,2
-00f153 fd97 sbrc tosh,7
-00f154 940c f15f jmp PFA_TRUE1
-00f156 940c f168 jmp PFA_ZERO1
-
- .include "words/true.asm"
-
- ; Arithmetics
- ; leaves the value -1 (true) on TOS
- VE_TRUE:
-00f158 ff04 .dw $ff04
-00f159 7274
-00f15a 6575 .db "true"
-00f15b f14d .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
- XT_TRUE:
-00f15c f15d .dw PFA_TRUE
- PFA_TRUE:
-00f15d 939a
-00f15e 938a savetos
- PFA_TRUE1:
-00f15f ef8f ser tosl
-00f160 ef9f ser tosh
-00f161 cea2 jmp_ DO_NEXT
- .include "words/zero.asm"
-
- ; Arithmetics
- ; place a value 0 on TOS
- VE_ZERO:
-00f162 ff01 .dw $ff01
-00f163 0030 .db "0",0
-00f164 f158 .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
- XT_ZERO:
-00f165 f166 .dw PFA_ZERO
- PFA_ZERO:
-00f166 939a
-00f167 938a savetos
- PFA_ZERO1:
-00f168 01c1 movw tosl, zerol
-00f169 ce9a jmp_ DO_NEXT
- .include "words/uless.asm"
-
- ; Compare
- ; true if u1 < u2 (unsigned)
- VE_ULESS:
-00f16a ff02 .dw $ff02
-00f16b 3c75 .db "u<"
-00f16c f162 .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
- XT_ULESS:
-00f16d f16e .dw PFA_ULESS
- PFA_ULESS:
-00f16e 9129 ld temp2, Y+
-00f16f 9139 ld temp3, Y+
-00f170 1782 cp tosl, temp2
-00f171 0793 cpc tosh, temp3
-00f172 f3a8 brlo PFA_ZERO1
-00f173 f3a1 brbs 1, PFA_ZERO1
-00f174 cfea jmp_ PFA_TRUE1
- .include "words/u-greater.asm"
-
- ; Compare
- ; true if u1 > u2 (unsigned)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UGREATER:
-00f175 ff02 .dw $ff02
-00f176 3e75 .db "u>"
-00f177 f16a .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
- XT_UGREATER:
-00f178 f000 .dw DO_COLON
- PFA_UGREATER:
- .endif
-00f179 f0d5 .DW XT_SWAP
-00f17a f16d .dw XT_ULESS
-00f17b f025 .dw XT_EXIT
- .include "words/less.asm"
-
- ; Compare
- ; true if n1 is less than n2
- VE_LESS:
-00f17c ff01 .dw $ff01
-00f17d 003c .db "<",0
-00f17e f175 .dw VE_HEAD
- .set VE_HEAD = VE_LESS
- XT_LESS:
-00f17f f180 .dw PFA_LESS
- PFA_LESS:
-00f180 9129 ld temp2, Y+
-00f181 9139 ld temp3, Y+
-00f182 1728 cp temp2, tosl
-00f183 0739 cpc temp3, tosh
- PFA_LESSDONE:
-00f184 f71c brge PFA_ZERO1
-00f185 cfd9 rjmp PFA_TRUE1
- .include "words/greater.asm"
-
- ; Compare
- ; flag is true if n1 is greater than n2
- VE_GREATER:
-00f186 ff01 .dw $ff01
-00f187 003e .db ">",0
-00f188 f17c .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
- XT_GREATER:
-00f189 f18a .dw PFA_GREATER
- PFA_GREATER:
-00f18a 9129 ld temp2, Y+
-00f18b 9139 ld temp3, Y+
-00f18c 1728 cp temp2, tosl
-00f18d 0739 cpc temp3, tosh
- PFA_GREATERDONE:
-00f18e f2cc brlt PFA_ZERO1
-00f18f f2c1 brbs 1, PFA_ZERO1
-00f190 cfce rjmp PFA_TRUE1
-
- .include "words/log2.asm"
-
- ; Arithmetics
- ; logarithm to base 2 or highest set bitnumber
- VE_LOG2:
-00f191 ff04 .dw $ff04
-00f192 6f6c
-00f193 3267 .db "log2"
-00f194 f186 .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
- XT_LOG2:
-00f195 f196 .dw PFA_LOG2
- PFA_LOG2:
-00f196 01fc movw zl, tosl
-00f197 2799 clr tosh
-00f198 e180 ldi tosl, 16
- PFA_LOG2_1:
-00f199 958a dec tosl
-00f19a f022 brmi PFA_LOG2_2 ; wrong data
-00f19b 0fee lsl zl
-00f19c 1fff rol zh
-00f19d f7d8 brcc PFA_LOG2_1
-00f19e ce65 jmp_ DO_NEXT
-
- PFA_LOG2_2:
-00f19f 959a dec tosh
-00f1a0 ce63 jmp_ DO_NEXT
- .include "words/minus.asm"
-
- ; Arithmetics
- ; subtract n2 from n1
- VE_MINUS:
-00f1a1 ff01 .dw $ff01
-00f1a2 002d .db "-",0
-00f1a3 f191 .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
- XT_MINUS:
-00f1a4 f1a5 .dw PFA_MINUS
- PFA_MINUS:
-00f1a5 9109 ld temp0, Y+
-00f1a6 9119 ld temp1, Y+
-00f1a7 1b08 sub temp0, tosl
-00f1a8 0b19 sbc temp1, tosh
-00f1a9 01c8 movw tosl, temp0
-00f1aa ce59 jmp_ DO_NEXT
- .include "words/plus.asm"
-
- ; Arithmetics
- ; add n1 and n2
- VE_PLUS:
-00f1ab ff01 .dw $ff01
-00f1ac 002b .db "+",0
-00f1ad f1a1 .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
- XT_PLUS:
-00f1ae f1af .dw PFA_PLUS
- PFA_PLUS:
-00f1af 9109 ld temp0, Y+
-00f1b0 9119 ld temp1, Y+
-00f1b1 0f80 add tosl, temp0
-00f1b2 1f91 adc tosh, temp1
-00f1b3 ce50 jmp_ DO_NEXT
- .include "words/mstar.asm"
-
- ; Arithmetics
- ; multiply 2 cells to a double cell
- VE_MSTAR:
-00f1b4 ff02 .dw $ff02
-00f1b5 2a6d .db "m*"
-00f1b6 f1ab .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
- XT_MSTAR:
-00f1b7 f1b8 .dw PFA_MSTAR
- PFA_MSTAR:
-00f1b8 018c movw temp0, tosl
-00f1b9 9189
-00f1ba 9199 loadtos
-00f1bb 019c movw temp2, tosl
- ; high cell ah*bh
-00f1bc 0231 muls temp3, temp1
-00f1bd 0170 movw temp4, r0
- ; low cell al*bl
-00f1be 9f20 mul temp2, temp0
-00f1bf 01c0 movw tosl, r0
- ; signed ah*bl
-00f1c0 0330 mulsu temp3, temp0
-00f1c1 08f3 sbc temp5, zeroh
-00f1c2 0d90 add tosh, r0
-00f1c3 1ce1 adc temp4, r1
-00f1c4 1cf3 adc temp5, zeroh
-
- ; signed al*bh
-00f1c5 0312 mulsu temp1, temp2
-00f1c6 08f3 sbc temp5, zeroh
-00f1c7 0d90 add tosh, r0
-00f1c8 1ce1 adc temp4, r1
-00f1c9 1cf3 adc temp5, zeroh
-
-00f1ca 939a
-00f1cb 938a savetos
-00f1cc 01c7 movw tosl, temp4
-00f1cd ce36 jmp_ DO_NEXT
- .include "words/umslashmod.asm"
-
- ; Arithmetics
- ; unsigned division ud / u2 with remainder
- VE_UMSLASHMOD:
-00f1ce ff06 .dw $ff06
-00f1cf 6d75
-00f1d0 6d2f
-00f1d1 646f .db "um/mod"
-00f1d2 f1b4 .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
- XT_UMSLASHMOD:
-00f1d3 f1d4 .dw PFA_UMSLASHMOD
- PFA_UMSLASHMOD:
-00f1d4 017c movw temp4, tosl
-
-00f1d5 9129 ld temp2, Y+
-00f1d6 9139 ld temp3, Y+
-
-00f1d7 9109 ld temp0, Y+
-00f1d8 9119 ld temp1, Y+
-
- ;; unsigned 32/16 -> 16r16 divide
-
- PFA_UMSLASHMODmod:
-
- ; set loop counter
-00f1d9 e140 ldi temp6,$10
-
- PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
-00f1da 2755 clr temp7
-00f1db 0f00 lsl temp0
-00f1dc 1f11 rol temp1
-00f1dd 1f22 rol temp2
-00f1de 1f33 rol temp3
-00f1df 1f55 rol temp7
-
- ; try subtracting divisor
-00f1e0 152e cp temp2, temp4
-00f1e1 053f cpc temp3, temp5
-00f1e2 0552 cpc temp7,zerol
-
-00f1e3 f018 brcs PFA_UMSLASHMODmod_loop_control
-
- PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
-00f1e4 9503 inc temp0
-00f1e5 192e sub temp2, temp4
-00f1e6 093f sbc temp3, temp5
-
- PFA_UMSLASHMODmod_loop_control:
-00f1e7 954a dec temp6
-00f1e8 f789 brne PFA_UMSLASHMODmod_loop
-
- PFA_UMSLASHMODmod_done:
- ; put remainder on stack
-00f1e9 933a st -Y,temp3
-00f1ea 932a st -Y,temp2
-
- ; put quotient on stack
-00f1eb 01c8 movw tosl, temp0
-00f1ec ce17 jmp_ DO_NEXT
- .include "words/umstar.asm"
-
- ; Arithmetics
- ; multiply 2 unsigned cells to a double cell
- VE_UMSTAR:
-00f1ed ff03 .dw $ff03
-00f1ee 6d75
-00f1ef 002a .db "um*",0
-00f1f0 f1ce .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
- XT_UMSTAR:
-00f1f1 f1f2 .dw PFA_UMSTAR
- PFA_UMSTAR:
-00f1f2 018c movw temp0, tosl
-00f1f3 9189
-00f1f4 9199 loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
-00f1f5 9f80 mul tosl,temp0
-00f1f6 01f0 movw zl, r0
-00f1f7 2722 clr temp2
-00f1f8 2733 clr temp3
- ; middle bytes
-00f1f9 9f90 mul tosh, temp0
-00f1fa 0df0 add zh, r0
-00f1fb 1d21 adc temp2, r1
-00f1fc 1d33 adc temp3, zeroh
-
-00f1fd 9f81 mul tosl, temp1
-00f1fe 0df0 add zh, r0
-00f1ff 1d21 adc temp2, r1
-00f200 1d33 adc temp3, zeroh
-
-00f201 9f91 mul tosh, temp1
-00f202 0d20 add temp2, r0
-00f203 1d31 adc temp3, r1
-00f204 01cf movw tosl, zl
-00f205 939a
-00f206 938a savetos
-00f207 01c9 movw tosl, temp2
-00f208 cdfb jmp_ DO_NEXT
-
- .include "words/invert.asm"
-
- ; Arithmetics
- ; 1-complement of TOS
- VE_INVERT:
-00f209 ff06 .dw $ff06
-00f20a 6e69
-00f20b 6576
-00f20c 7472 .db "invert"
-00f20d f1ed .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
- XT_INVERT:
-00f20e f20f .dw PFA_INVERT
- PFA_INVERT:
-00f20f 9580 com tosl
-00f210 9590 com tosh
-00f211 cdf2 jmp_ DO_NEXT
- .include "words/2slash.asm"
-
- ; Arithmetics
- ; arithmetic shift right
- VE_2SLASH:
-00f212 ff02 .dw $ff02
-00f213 2f32 .db "2/"
-00f214 f209 .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
- XT_2SLASH:
-00f215 f216 .dw PFA_2SLASH
- PFA_2SLASH:
-00f216 9595 asr tosh
-00f217 9587 ror tosl
-00f218 cdeb jmp_ DO_NEXT
- .include "words/2star.asm"
-
- ; Arithmetics
- ; arithmetic shift left, filling with zero
- VE_2STAR:
-00f219 ff02 .dw $ff02
-00f21a 2a32 .db "2*"
-00f21b f212 .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
- XT_2STAR:
-00f21c f21d .dw PFA_2STAR
- PFA_2STAR:
-00f21d 0f88 lsl tosl
-00f21e 1f99 rol tosh
-00f21f cde4 jmp_ DO_NEXT
- .include "words/and.asm"
-
- ; Logic
- ; bitwise and
- VE_AND:
-00f220 ff03 .dw $ff03
-00f221 6e61
-00f222 0064 .db "and",0
-00f223 f219 .dw VE_HEAD
- .set VE_HEAD = VE_AND
- XT_AND:
-00f224 f225 .dw PFA_AND
- PFA_AND:
-00f225 9109 ld temp0, Y+
-00f226 9119 ld temp1, Y+
-00f227 2380 and tosl, temp0
-00f228 2391 and tosh, temp1
-00f229 cdda jmp_ DO_NEXT
- .include "words/or.asm"
-
- ; Logic
- ; logical or
- VE_OR:
-00f22a ff02 .dw $ff02
-00f22b 726f .db "or"
-00f22c f220 .dw VE_HEAD
- .set VE_HEAD = VE_OR
- XT_OR:
-00f22d f22e .dw PFA_OR
- PFA_OR:
-00f22e 9109 ld temp0, Y+
-00f22f 9119 ld temp1, Y+
-00f230 2b80 or tosl, temp0
-00f231 2b91 or tosh, temp1
-00f232 cdd1 jmp_ DO_NEXT
-
- .include "words/xor.asm"
-
- ; Logic
- ; exclusive or
- VE_XOR:
-00f233 ff03 .dw $ff03
-00f234 6f78
-00f235 0072 .db "xor",0
-00f236 f22a .dw VE_HEAD
- .set VE_HEAD = VE_XOR
- XT_XOR:
-00f237 f238 .dw PFA_XOR
- PFA_XOR:
-00f238 9109 ld temp0, Y+
-00f239 9119 ld temp1, Y+
-00f23a 2780 eor tosl, temp0
-00f23b 2791 eor tosh, temp1
-00f23c cdc7 jmp_ DO_NEXT
-
- .include "words/1plus.asm"
-
- ; Arithmetics
- ; optimized increment
- VE_1PLUS:
-00f23d ff02 .dw $ff02
-00f23e 2b31 .db "1+"
-00f23f f233 .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
- XT_1PLUS:
-00f240 f241 .dw PFA_1PLUS
- PFA_1PLUS:
-00f241 9601 adiw tosl,1
-00f242 cdc1 jmp_ DO_NEXT
- .include "words/1minus.asm"
-
- ; Arithmetics
- ; optimized decrement
- VE_1MINUS:
-00f243 ff02 .dw $ff02
-00f244 2d31 .db "1-"
-00f245 f23d .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
- XT_1MINUS:
-00f246 f247 .dw PFA_1MINUS
- PFA_1MINUS:
-00f247 9701 sbiw tosl, 1
-00f248 cdbb jmp_ DO_NEXT
- .include "words/q-negate.asm"
-
- ; 0< IF NEGATE THEN ; ...a common factor
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QNEGATE:
-00f249 ff07 .dw $ff07
-00f24a 6e3f
-00f24b 6765
-00f24c 7461
-../../common\words/q-negate.asm(11): warning: .cseg .db misalignment - padding zero byte
-00f24d 0065 .db "?negate"
-00f24e f243 .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
- XT_QNEGATE:
-00f24f f000 .dw DO_COLON
- PFA_QNEGATE:
-
- .endif
-00f250 f132
-00f251 f03e .DW XT_ZEROLESS,XT_DOCONDBRANCH
-00f252 f254 DEST(QNEG1)
-00f253 f659 .DW XT_NEGATE
-00f254 f025 QNEG1: .DW XT_EXIT
- .include "words/lshift.asm"
-
- ; Arithmetics
- ; logically shift n1 left n2 times
- VE_LSHIFT:
-00f255 ff06 .dw $ff06
-00f256 736c
-00f257 6968
-00f258 7466 .db "lshift"
-00f259 f249 .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
- XT_LSHIFT:
-00f25a f25b .dw PFA_LSHIFT
- PFA_LSHIFT:
-00f25b 01fc movw zl, tosl
-00f25c 9189
-00f25d 9199 loadtos
- PFA_LSHIFT1:
-00f25e 9731 sbiw zl, 1
-00f25f f01a brmi PFA_LSHIFT2
-00f260 0f88 lsl tosl
-00f261 1f99 rol tosh
-00f262 cffb rjmp PFA_LSHIFT1
- PFA_LSHIFT2:
-00f263 cda0 jmp_ DO_NEXT
-
- .include "words/rshift.asm"
-
- ; Arithmetics
- ; shift n1 n2-times logically right
- VE_RSHIFT:
-00f264 ff06 .dw $ff06
-00f265 7372
-00f266 6968
-00f267 7466 .db "rshift"
-00f268 f255 .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
- XT_RSHIFT:
-00f269 f26a .dw PFA_RSHIFT
- PFA_RSHIFT:
-00f26a 01fc movw zl, tosl
-00f26b 9189
-00f26c 9199 loadtos
- PFA_RSHIFT1:
-00f26d 9731 sbiw zl, 1
-00f26e f01a brmi PFA_RSHIFT2
-00f26f 9596 lsr tosh
-00f270 9587 ror tosl
-00f271 cffb rjmp PFA_RSHIFT1
- PFA_RSHIFT2:
-00f272 cd91 jmp_ DO_NEXT
-
- .include "words/plusstore.asm"
-
- ; Arithmetics
- ; add n to content of RAM address a-addr
- VE_PLUSSTORE:
-00f273 ff02 .dw $ff02
-00f274 212b .db "+!"
-00f275 f264 .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
- XT_PLUSSTORE:
-00f276 f277 .dw PFA_PLUSSTORE
- PFA_PLUSSTORE:
-00f277 01fc movw zl, tosl
-00f278 9189
-00f279 9199 loadtos
-00f27a 8120 ldd temp2, Z+0
-00f27b 8131 ldd temp3, Z+1
-00f27c 0f82 add tosl, temp2
-00f27d 1f93 adc tosh, temp3
-00f27e 8380 std Z+0, tosl
-00f27f 8391 std Z+1, tosh
-00f280 9189
-00f281 9199 loadtos
-00f282 cd81 jmp_ DO_NEXT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/rpfetch.asm"
-
- ; Stack
- ; current return stack pointer address
- VE_RP_FETCH:
-00f283 ff03 .dw $ff03
-00f284 7072
-00f285 0040 .db "rp@",0
-00f286 f273 .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
- XT_RP_FETCH:
-00f287 f288 .dw PFA_RP_FETCH
- PFA_RP_FETCH:
-00f288 939a
-00f289 938a savetos
-00f28a b78d in tosl, SPL
-00f28b b79e in tosh, SPH
-00f28c cd77 jmp_ DO_NEXT
- .include "words/rpstore.asm"
-
- ; Stack
- ; set return stack pointer
- VE_RP_STORE:
-00f28d ff03 .dw $ff03
-00f28e 7072
-00f28f 0021 .db "rp!",0
-00f290 f283 .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
- XT_RP_STORE:
-00f291 f292 .dw PFA_RP_STORE
- PFA_RP_STORE:
-00f292 b72f in temp2, SREG
-00f293 94f8 cli
-00f294 bf8d out SPL, tosl
-00f295 bf9e out SPH, tosh
-00f296 bf2f out SREG, temp2
-00f297 9189
-00f298 9199 loadtos
-00f299 cd6a jmp_ DO_NEXT
- .include "words/spfetch.asm"
-
- ; Stack
- ; current data stack pointer
- VE_SP_FETCH:
-00f29a ff03 .dw $ff03
-00f29b 7073
-00f29c 0040 .db "sp@",0
-00f29d f28d .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
- XT_SP_FETCH:
-00f29e f29f .dw PFA_SP_FETCH
- PFA_SP_FETCH:
-00f29f 939a
-00f2a0 938a savetos
-00f2a1 01ce movw tosl, yl
-00f2a2 cd61 jmp_ DO_NEXT
- .include "words/spstore.asm"
-
- ; Stack
- ; set data stack pointer to addr
- VE_SP_STORE:
-00f2a3 ff03 .dw $ff03
-00f2a4 7073
-00f2a5 0021 .db "sp!",0
-00f2a6 f29a .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
- XT_SP_STORE:
-00f2a7 f2a8 .dw PFA_SP_STORE
- PFA_SP_STORE:
-00f2a8 01ec movw yl, tosl
-00f2a9 9189
-00f2aa 9199 loadtos
-00f2ab cd58 jmp_ DO_NEXT
-
- .include "words/dodo.asm"
-
- ; System
- ; runtime of do
- ;VE_DODO:
- ; .dw $ff04
- ; .db "(do)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DODO
- XT_DODO:
-00f2ac f2ad .dw PFA_DODO
- PFA_DODO:
-00f2ad 9129 ld temp2, Y+
-00f2ae 9139 ld temp3, Y+ ; limit
- PFA_DODO1:
-00f2af e8e0 ldi zl, $80
-00f2b0 0f3e add temp3, zl
-00f2b1 1b82 sub tosl, temp2
-00f2b2 0b93 sbc tosh, temp3
-
-00f2b3 933f push temp3
-00f2b4 932f push temp2 ; limit ( --> limit + $8000)
-00f2b5 939f push tosh
-00f2b6 938f push tosl ; start -> index ( --> index - (limit - $8000)
-00f2b7 9189
-00f2b8 9199 loadtos
-00f2b9 cd4a jmp_ DO_NEXT
- .include "words/i.asm"
-
- ; Compiler
- ; current loop counter
- VE_I:
-00f2ba ff01 .dw $FF01
-00f2bb 0069 .db "i",0
-00f2bc f2a3 .dw VE_HEAD
- .set VE_HEAD = VE_I
- XT_I:
-00f2bd f2be .dw PFA_I
- PFA_I:
-00f2be 939a
-00f2bf 938a savetos
-00f2c0 918f pop tosl
-00f2c1 919f pop tosh ; index
-00f2c2 91ef pop zl
-00f2c3 91ff pop zh ; limit
-00f2c4 93ff push zh
-00f2c5 93ef push zl
-00f2c6 939f push tosh
-00f2c7 938f push tosl
-00f2c8 0f8e add tosl, zl
-00f2c9 1f9f adc tosh, zh
-00f2ca cd39 jmp_ DO_NEXT
- .include "words/doplusloop.asm"
-
- ; System
- ; runtime of +loop
- ;VE_DOPLUSLOOP:
- ; .dw $ff07
- ; .db "(+loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOPLUSLOOP
- XT_DOPLUSLOOP:
-00f2cb f2cc .dw PFA_DOPLUSLOOP
- PFA_DOPLUSLOOP:
-00f2cc 91ef pop zl
-00f2cd 91ff pop zh
-00f2ce 0fe8 add zl, tosl
-00f2cf 1ff9 adc zh, tosh
-00f2d0 9189
-00f2d1 9199 loadtos
-00f2d2 f01b brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
- PFA_DOPLUSLOOP_NEXT:
- ; next iteration
-00f2d3 93ff push zh
-00f2d4 93ef push zl
-00f2d5 cd5f rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
- PFA_DOPLUSLOOP_LEAVE:
-00f2d6 910f pop temp0
-00f2d7 911f pop temp1 ; remove limit
-00f2d8 9611 adiw xl, 1 ; skip branch-back address
-00f2d9 cd2a jmp_ DO_NEXT
- .include "words/doloop.asm"
-
- ; System
- ; runtime of loop
- ;VE_DOLOOP:
- ; .dw $ff06
- ; .db "(loop)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOLOOP
- XT_DOLOOP:
-00f2da f2db .dw PFA_DOLOOP
- PFA_DOLOOP:
-00f2db 91ef pop zl
-00f2dc 91ff pop zh
-00f2dd 9631 adiw zl,1
-00f2de f3bb brvs PFA_DOPLUSLOOP_LEAVE
-00f2df cff3 jmp_ PFA_DOPLUSLOOP_NEXT
- .include "words/unloop.asm"
-
- ; Compiler
- ; remove loop-sys, exit the loop and continue execution after it
- VE_UNLOOP:
-00f2e0 ff06 .dw $ff06
-00f2e1 6e75
-00f2e2 6f6c
-00f2e3 706f .db "unloop"
-00f2e4 f2ba .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
- XT_UNLOOP:
-00f2e5 f2e6 .dw PFA_UNLOOP
- PFA_UNLOOP:
-00f2e6 911f pop temp1
-00f2e7 910f pop temp0
-00f2e8 911f pop temp1
-00f2e9 910f pop temp0
-00f2ea cd19 jmp_ DO_NEXT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
- .include "words/cmove_g.asm"
-
- ; Memory
- ; copy data in RAM from higher to lower addresses.
- VE_CMOVE_G:
-00f2eb ff06 .dw $ff06
-00f2ec 6d63
-00f2ed 766f
-00f2ee 3e65 .db "cmove>"
-00f2ef f2e0 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
- XT_CMOVE_G:
-00f2f0 f2f1 .dw PFA_CMOVE_G
- PFA_CMOVE_G:
-00f2f1 93bf push xh
-00f2f2 93af push xl
-00f2f3 91e9 ld zl, Y+
-00f2f4 91f9 ld zh, Y+ ; addr-to
-00f2f5 91a9 ld xl, Y+
-00f2f6 91b9 ld xh, Y+ ; addr-from
-00f2f7 2f09 mov temp0, tosh
-00f2f8 2b08 or temp0, tosl
-00f2f9 f041 brbs 1, PFA_CMOVE_G1
-00f2fa 0fe8 add zl, tosl
-00f2fb 1ff9 adc zh, tosh
-00f2fc 0fa8 add xl, tosl
-00f2fd 1fb9 adc xh, tosh
- PFA_CMOVE_G2:
-00f2fe 911e ld temp1, -X
-00f2ff 9312 st -Z, temp1
-00f300 9701 sbiw tosl, 1
-00f301 f7e1 brbc 1, PFA_CMOVE_G2
- PFA_CMOVE_G1:
-00f302 91af pop xl
-00f303 91bf pop xh
-00f304 9189
-00f305 9199 loadtos
-00f306 ccfd jmp_ DO_NEXT
- .include "words/byteswap.asm"
-
- ; Arithmetics
- ; exchange the bytes of the TOS
- VE_BYTESWAP:
-00f307 ff02 .dw $ff02
-00f308 3c3e .db "><"
-00f309 f2eb .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
- XT_BYTESWAP:
-00f30a f30b .dw PFA_BYTESWAP
- PFA_BYTESWAP:
-00f30b 2f09 mov temp0, tosh
-00f30c 2f98 mov tosh, tosl
-00f30d 2f80 mov tosl, temp0
-00f30e ccf5 jmp_ DO_NEXT
- .include "words/up.asm"
-
- ; System Variable
- ; get user area pointer
- VE_UP_FETCH:
-00f30f ff03 .dw $ff03
-00f310 7075
-00f311 0040 .db "up@",0
-00f312 f307 .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
- XT_UP_FETCH:
-00f313 f314 .dw PFA_UP_FETCH
- PFA_UP_FETCH:
-00f314 939a
-00f315 938a savetos
-00f316 01c2 movw tosl, upl
-00f317 ccec jmp_ DO_NEXT
-
- ; ( addr -- )
- ; System Variable
- ; set user area pointer
- VE_UP_STORE:
-00f318 ff03 .dw $ff03
-00f319 7075
-00f31a 0021 .db "up!",0
-00f31b f30f .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
- XT_UP_STORE:
-00f31c f31d .dw PFA_UP_STORE
- PFA_UP_STORE:
-00f31d 012c movw upl, tosl
-00f31e 9189
-00f31f 9199 loadtos
-00f320 cce3 jmp_ DO_NEXT
- .include "words/1ms.asm"
-
- ; Time
- ; busy waits (almost) exactly 1 millisecond
- VE_1MS:
-00f321 ff03 .dw $ff03
-00f322 6d31
-00f323 0073 .db "1ms",0
-00f324 f318 .dw VE_HEAD
- .set VE_HEAD = VE_1MS
- XT_1MS:
-00f325 f326 .dw PFA_1MS
- PFA_1MS:
-00f326 ede0
-00f327 e0f7
-00f328 9731
-00f329 f7f1 delay 1000
-00f32a ccd9 jmp_ DO_NEXT
- .include "words/2to_r.asm"
-
- ; Stack
- ; move DTOS to TOR
- VE_2TO_R:
-00f32b ff03 .dw $ff03
-00f32c 3e32
-00f32d 0072 .db "2>r",0
-00f32e f321 .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
- XT_2TO_R:
-00f32f f330 .dw PFA_2TO_R
- PFA_2TO_R:
-00f330 01fc movw zl, tosl
-00f331 9189
-00f332 9199 loadtos
-00f333 939f push tosh
-00f334 938f push tosl
-00f335 93ff push zh
-00f336 93ef push zl
-00f337 9189
-00f338 9199 loadtos
-00f339 ccca jmp_ DO_NEXT
- .include "words/2r_from.asm"
-
- ; Stack
- ; move DTOR to TOS
- VE_2R_FROM:
-00f33a ff03 .dw $ff03
-00f33b 7232
-00f33c 003e .db "2r>",0
-00f33d f32b .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
- XT_2R_FROM:
-00f33e f33f .dw PFA_2R_FROM
- PFA_2R_FROM:
-00f33f 939a
-00f340 938a savetos
-00f341 91ef pop zl
-00f342 91ff pop zh
-00f343 918f pop tosl
-00f344 919f pop tosh
-00f345 939a
-00f346 938a savetos
-00f347 01cf movw tosl, zl
-00f348 ccbb jmp_ DO_NEXT
-
- .include "words/store-e.asm"
-
- ; Memory
- ; write n (2bytes) to eeprom address
- VE_STOREE:
-00f349 ff02 .dw $ff02
-00f34a 6521 .db "!e"
-00f34b f33a .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
- XT_STOREE:
-00f34c f34d .dw PFA_STOREE
- PFA_STOREE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_STOREE0:
-00f34d 01fc movw zl, tosl
-00f34e 9189
-00f34f 9199 loadtos
-00f350 b72f in_ temp2, SREG
-00f351 94f8 cli
-00f352 d028 rcall PFA_FETCHE2
-00f353 b500 in_ temp0, EEDR
-00f354 1708 cp temp0,tosl
-00f355 f009 breq PFA_STOREE3
-00f356 d00b rcall PFA_STOREE1
- PFA_STOREE3:
-00f357 9631 adiw zl,1
-00f358 d022 rcall PFA_FETCHE2
-00f359 b500 in_ temp0, EEDR
-00f35a 1709 cp temp0,tosh
-00f35b f011 breq PFA_STOREE4
-00f35c 2f89 mov tosl, tosh
-00f35d d004 rcall PFA_STOREE1
- PFA_STOREE4:
-00f35e bf2f out_ SREG, temp2
-00f35f 9189
-00f360 9199 loadtos
-00f361 cca2 jmp_ DO_NEXT
-
- PFA_STOREE1:
-00f362 99f9 sbic EECR, EEPE
-00f363 cffe rjmp PFA_STOREE1
-
- PFA_STOREE2: ; estore_wait_low_spm:
-00f364 b707 in_ temp0, SPMCSR
-00f365 fd00 sbrc temp0,SPMEN
-00f366 cffd rjmp PFA_STOREE2
-
-00f367 bdf2 out_ EEARH,zh
-00f368 bde1 out_ EEARL,zl
-00f369 bd80 out_ EEDR, tosl
-00f36a 9afa sbi EECR,EEMPE
-00f36b 9af9 sbi EECR,EEPE
-
-00f36c 9508 ret
- .if WANT_UNIFIED == 1
- .endif
- .include "words/fetch-e.asm"
-
- ; Memory
- ; read 1 cell from eeprom
- VE_FETCHE:
-00f36d ff02 .dw $ff02
-00f36e 6540 .db "@e"
-00f36f f349 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
- XT_FETCHE:
-00f370 f371 .dw PFA_FETCHE
- PFA_FETCHE:
- .if WANT_UNIFIED == 1
- .endif
- PFA_FETCHE1:
-00f371 b72f in_ temp2, SREG
-00f372 94f8 cli
-00f373 01fc movw zl, tosl
-00f374 d006 rcall PFA_FETCHE2
-00f375 b580 in_ tosl, EEDR
-
-00f376 9631 adiw zl,1
-
-00f377 d003 rcall PFA_FETCHE2
-00f378 b590 in_ tosh, EEDR
-00f379 bf2f out_ SREG, temp2
-00f37a cc89 jmp_ DO_NEXT
-
- PFA_FETCHE2:
-00f37b 99f9 sbic EECR, EEPE
-00f37c cffe rjmp PFA_FETCHE2
-
-00f37d bdf2 out_ EEARH,zh
-00f37e bde1 out_ EEARL,zl
-
-00f37f 9af8 sbi EECR,EERE
-00f380 9508 ret
-
- .if WANT_UNIFIED == 1
- .endif
- .include "words/store-i.asm"
-
- ; System Value
- ; Deferred action to write a single 16bit cell to flash
- VE_STOREI:
-00f381 ff02 .dw $ff02
-00f382 6921 .db "!i"
-00f383 f36d .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
- XT_STOREI:
-00f384 fc2d .dw PFA_DODEFER1
- PFA_STOREI:
-00f385 0078 .dw EE_STOREI
-00f386 fbce .dw XT_EDEFERFETCH
-00f387 fbd8 .dw XT_EDEFERSTORE
- .if FLASHEND > $10000
- .else
- .include "words/store-i_nrww.asm"
-
- ; Memory
- ; writes n to flash memory using assembly code (code to be placed in boot loader section)
- VE_DO_STOREI_NRWW:
-00f388 ff09 .dw $ff09
-00f389 2128
-00f38a 2d69
-00f38b 726e
-00f38c 7777
-00f38d 0029 .db "(!i-nrww)",0
-00f38e f381 .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
- XT_DO_STOREI:
-00f38f f390 .dw PFA_DO_STOREI_NRWW
- PFA_DO_STOREI_NRWW:
- ; store status register
-00f390 b71f in temp1,SREG
-00f391 931f push temp1
-00f392 94f8 cli
-
-00f393 019c movw temp2, tosl ; save the (word) address
-00f394 9189
-00f395 9199 loadtos ; get the new value for the flash cell
-00f396 93af push xl
-00f397 93bf push xh
-00f398 93cf push yl
-00f399 93df push yh
-00f39a d009 rcall DO_STOREI_atmega
-00f39b 91df pop yh
-00f39c 91cf pop yl
-00f39d 91bf pop xh
-00f39e 91af pop xl
- ; finally clear the stack
-00f39f 9189
-00f3a0 9199 loadtos
-00f3a1 911f pop temp1
- ; restore status register (and interrupt enable flag)
-00f3a2 bf1f out SREG,temp1
-
-00f3a3 cc60 jmp_ DO_NEXT
-
- ;
- DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
-00f3a4 d010 rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
-00f3a5 94e0 com temp4
-00f3a6 94f0 com temp5
-00f3a7 218e and tosl, temp4
-00f3a8 219f and tosh, temp5
-00f3a9 2b98 or tosh, tosl
-00f3aa f019 breq DO_STOREI_writepage
-00f3ab 01f9 movw zl, temp2
-00f3ac e002 ldi temp0,(1<<PGERS)
-00f3ad d023 rcall dospm
-
- DO_STOREI_writepage:
- ; write page
-00f3ae 01f9 movw zl, temp2
-00f3af e004 ldi temp0,(1<<PGWRT)
-00f3b0 d020 rcall dospm
-
- ; reenable RWW section
-00f3b1 01f9 movw zl, temp2
-00f3b2 e100 ldi temp0,(1<<RWWSRE)
-00f3b3 d01d rcall dospm
-00f3b4 9508 ret
-
- ; load the desired page
- .equ pagemask = ~ ( PAGESIZE - 1 )
- pageload:
-00f3b5 01f9 movw zl, temp2
- ; get the beginning of page
-00f3b6 78e0 andi zl,low(pagemask)
-00f3b7 7fff andi zh,high(pagemask)
-00f3b8 01ef movw y, z
- ; loop counter (in words)
-00f3b9 e8a0 ldi xl,low(pagesize)
-00f3ba e0b0 ldi xh,high(pagesize)
- pageload_loop:
- ; we need the current flash value anyways
-00f3bb 01fe movw z, y
-00f3bc 2755
-00f3bd 0fee
-00f3be 1fff
-00f3bf 1f55
-00f3c0 bf5b
-00f3c1 9147
-00f3c2 9157 readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
-00f3c3 01fe movw z, y
-00f3c4 17e2 cp zl, temp2
-00f3c5 07f3 cpc zh, temp3
-00f3c6 f011 breq pageload_newdata
-00f3c7 010a movw r0, temp6
-00f3c8 c002 rjmp pageload_cont
- pageload_newdata:
-00f3c9 017a movw temp4, temp6
-00f3ca 010c movw r0, tosl
- pageload_cont:
-00f3cb 2700 clr temp0
-00f3cc d004 rcall dospm
-00f3cd 9621 adiw y, 1
-00f3ce 9711 sbiw x, 1
-00f3cf f759 brne pageload_loop
-
- pageload_done:
-00f3d0 9508 ret
-
-
- ;; dospm
- ;;
- ;; execute spm instruction
- ;; temp0 holds the value for SPMCR
-
- dospm:
- dospm_wait_ee:
-00f3d1 99f9 sbic EECR, EEPE
-00f3d2 cffe rjmp dospm_wait_ee
- dospm_wait_spm:
-00f3d3 b717 in_ temp1, SPMCSR
-00f3d4 fd10 sbrc temp1, SPMEN
-00f3d5 cffd rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
-00f3d6 2755
-00f3d7 0fee
-00f3d8 1fff
-00f3d9 1f55
-00f3da bf5b writeflashcell
- ; execute spm
-00f3db 6001 ori temp0, (1<<SPMEN)
-00f3dc bf07 out_ SPMCSR,temp0
-00f3dd 95e8 spm
-00f3de 9508 ret
- .endif
- .include "words/fetch-i.asm"
-
- ; Memory
- ; read 1 cell from flash
- VE_FETCHI:
-00f3df ff02 .dw $ff02
-00f3e0 6940 .db "@i"
-00f3e1 f388 .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
- XT_FETCHI:
-00f3e2 f3e3 .dw PFA_FETCHI
- PFA_FETCHI:
-00f3e3 01fc movw zl, tosl
-00f3e4 2755
-00f3e5 0fee
-00f3e6 1fff
-00f3e7 1f55
-00f3e8 bf5b
-00f3e9 9187
-00f3ea 9197 readflashcell tosl,tosh
-00f3eb cc18 jmp_ DO_NEXT
-
- .if AMFORTH_NRWW_SIZE>8000
- .include "dict/core_8k.inc"
-
- .include "words/n_to_r.asm"
-
- ; Stack
- ; move n items from data stack to return stack
- VE_N_TO_R:
-00f3ec ff03 .dw $ff03
-00f3ed 3e6e
-00f3ee 0072 .db "n>r",0
-00f3ef f3df .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
- XT_N_TO_R:
-00f3f0 f3f1 .dw PFA_N_TO_R
- PFA_N_TO_R:
-00f3f1 01fc movw zl, tosl
-00f3f2 2f08 mov temp0, tosl
- PFA_N_TO_R1:
-00f3f3 9189
-00f3f4 9199 loadtos
-00f3f5 939f push tosh
-00f3f6 938f push tosl
-00f3f7 950a dec temp0
-00f3f8 f7d1 brne PFA_N_TO_R1
-00f3f9 93ef push zl
-00f3fa 93ff push zh
-00f3fb 9189
-00f3fc 9199 loadtos
-00f3fd cc06 jmp_ DO_NEXT
- .include "words/n_r_from.asm"
-
- ; Stack
- ; move n items from return stack to data stack
- VE_N_R_FROM:
-00f3fe ff03 .dw $ff03
-00f3ff 726e
-00f400 003e .db "nr>",0
-00f401 f3ec .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
- XT_N_R_FROM:
-00f402 f403 .dw PFA_N_R_FROM
- PFA_N_R_FROM:
-00f403 939a
-00f404 938a savetos
-00f405 91ff pop zh
-00f406 91ef pop zl
-00f407 2f0e mov temp0, zl
- PFA_N_R_FROM1:
-00f408 918f pop tosl
-00f409 919f pop tosh
-00f40a 939a
-00f40b 938a savetos
-00f40c 950a dec temp0
-00f40d f7d1 brne PFA_N_R_FROM1
-00f40e 01cf movw tosl, zl
-00f40f cbf4 jmp_ DO_NEXT
-
- .include "words/d-2star.asm"
-
- ; Arithmetics
- ; shift a double cell left
- VE_D2STAR:
-00f410 ff03 .dw $ff03
-00f411 3264
-00f412 002a .db "d2*",0
-00f413 f3fe .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
- XT_D2STAR:
-00f414 f415 .dw PFA_D2STAR
- PFA_D2STAR:
-00f415 9109 ld temp0, Y+
-00f416 9119 ld temp1, Y+
-00f417 0f00 lsl temp0
-00f418 1f11 rol temp1
-00f419 1f88 rol tosl
-00f41a 1f99 rol tosh
-00f41b 931a st -Y, temp1
-00f41c 930a st -Y, temp0
-00f41d cbe6 jmp_ DO_NEXT
- .include "words/d-2slash.asm"
-
- ; Arithmetics
- ; shift a double cell value right
- VE_D2SLASH:
-00f41e ff03 .dw $ff03
-00f41f 3264
-00f420 002f .db "d2/",0
-00f421 f410 .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
- XT_D2SLASH:
-00f422 f423 .dw PFA_D2SLASH
- PFA_D2SLASH:
-00f423 9109 ld temp0, Y+
-00f424 9119 ld temp1, Y+
-00f425 9595 asr tosh
-00f426 9587 ror tosl
-00f427 9517 ror temp1
-00f428 9507 ror temp0
-00f429 931a st -Y, temp1
-00f42a 930a st -Y, temp0
-00f42b cbd8 jmp_ DO_NEXT
- .include "words/d-plus.asm"
-
- ; Arithmetics
- ; add 2 double cell values
- VE_DPLUS:
-00f42c ff02 .dw $ff02
-00f42d 2b64 .db "d+"
-00f42e f41e .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
- XT_DPLUS:
-00f42f f430 .dw PFA_DPLUS
- PFA_DPLUS:
-00f430 9129 ld temp2, Y+
-00f431 9139 ld temp3, Y+
-
-00f432 90e9 ld temp4, Y+
-00f433 90f9 ld temp5, Y+
-00f434 9149 ld temp6, Y+
-00f435 9159 ld temp7, Y+
-
-00f436 0f24 add temp2, temp6
-00f437 1f35 adc temp3, temp7
-00f438 1d8e adc tosl, temp4
-00f439 1d9f adc tosh, temp5
-
-00f43a 933a st -Y, temp3
-00f43b 932a st -Y, temp2
-00f43c cbc7 jmp_ DO_NEXT
- .include "words/d-minus.asm"
-
- ; Arithmetics
- ; subtract d2 from d1
- VE_DMINUS:
-00f43d ff02 .dw $ff02
-00f43e 2d64 .db "d-"
-00f43f f42c .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
- XT_DMINUS:
-00f440 f441 .dw PFA_DMINUS
- PFA_DMINUS:
-00f441 9129 ld temp2, Y+
-00f442 9139 ld temp3, Y+
-
-00f443 90e9 ld temp4, Y+
-00f444 90f9 ld temp5, Y+
-00f445 9149 ld temp6, Y+
-00f446 9159 ld temp7, Y+
-
-00f447 1b42 sub temp6, temp2
-00f448 0b53 sbc temp7, temp3
-00f449 0ae8 sbc temp4, tosl
-00f44a 0af9 sbc temp5, tosh
-
-00f44b 935a st -Y, temp7
-00f44c 934a st -Y, temp6
-00f44d 01c7 movw tosl, temp4
-00f44e cbb5 jmp_ DO_NEXT
- .include "words/d-invert.asm"
-
- ; Arithmetics
- ; invert all bits in the double cell value
- VE_DINVERT:
-00f44f ff07 .dw $ff07
-00f450 6964
-00f451 766e
-00f452 7265
-00f453 0074 .db "dinvert",0
-00f454 f43d .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
- XT_DINVERT:
-00f455 f456 .dw PFA_DINVERT
- PFA_DINVERT:
-00f456 9109 ld temp0, Y+
-00f457 9119 ld temp1, Y+
-00f458 9580 com tosl
-00f459 9590 com tosh
-00f45a 9500 com temp0
-00f45b 9510 com temp1
-00f45c 931a st -Y, temp1
-00f45d 930a st -Y, temp0
-00f45e cba5 jmp_ DO_NEXT
- .include "words/u-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDOT:
-00f45f ff02 .dw $ff02
-00f460 2e75 .db "u."
-00f461 f44f .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
- XT_UDOT:
-00f462 f000 .dw DO_COLON
- PFA_UDOT:
- .endif
-00f463 f165 .dw XT_ZERO
-00f464 f744 .dw XT_UDDOT
-00f465 f025 .dw XT_EXIT
- ; : u. ( us -- ) 0 ud. ;
- .include "words/u-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with single cells numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDOTR:
-00f466 ff03 .dw $ff03
-00f467 2e75
-00f468 0072 .db "u.r",0
-00f469 f45f .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
- XT_UDOTR:
-00f46a f000 .dw DO_COLON
- PFA_UDOTR:
- .endif
-00f46b f165 .dw XT_ZERO
-00f46c f0d5 .dw XT_SWAP
-00f46d f74d .dw XT_UDDOTR
-00f46e f025 .dw XT_EXIT
- ; : u.r ( s n -- ) 0 swap ud.r ;
-
- .include "words/show-wordlist.asm"
-
- ; Tools
- ; prints the name of the words in a wordlist
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHOWWORDLIST:
-00f46f ff0d .dw $ff0d
-00f470 6873
-00f471 776f
-00f472 772d
-00f473 726f
-00f474 6c64
-00f475 7369
-00f476 0074 .db "show-wordlist",0
-00f477 f466 .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
- XT_SHOWWORDLIST:
-00f478 f000 .dw DO_COLON
- PFA_SHOWWORDLIST:
- .endif
-00f479 f045 .dw XT_DOLITERAL
-00f47a f47e .dw XT_SHOWWORD
-00f47b f0d5 .dw XT_SWAP
-00f47c fc71 .dw XT_TRAVERSEWORDLIST
-00f47d f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SHOWWORD:
-00f47e f000 .dw DO_COLON
- PFA_SHOWWORD:
- .endif
-00f47f fc8c .dw XT_NAME2STRING
-00f480 f7ba .dw XT_ITYPE
-00f481 f7fc .dw XT_SPACE ; ( -- addr n)
-00f482 f15c .dw XT_TRUE
-00f483 f025 .dw XT_EXIT
- .include "words/words.asm"
-
- ; Tools
- ; prints a list of all (visible) words in the dictionary
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_WORDS:
-00f484 ff05 .dw $ff05
-00f485 6f77
-00f486 6472
-00f487 0073 .db "words",0
-00f488 f46f .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
- XT_WORDS:
-00f489 f000 .dw DO_COLON
- PFA_WORDS:
- .endif
-00f48a f045 .dw XT_DOLITERAL
-00f48b 005e .dw CFG_ORDERLISTLEN+2
-00f48c f370 .dw XT_FETCHE
-00f48d f478 .dw XT_SHOWWORDLIST
-00f48e f025 .dw XT_EXIT
- .include "dict/interrupt.inc"
-
- .if WANT_INTERRUPTS == 1
-
- .if WANT_INTERRUPT_COUNTERS == 1
- .endif
-
- .include "words/int-on.asm"
-
- ; Interrupt
- ; turns on all interrupts
- VE_INTON:
-00f48f ff04 .dw $ff04
-00f490 692b
-00f491 746e .db "+int"
-00f492 f484 .dw VE_HEAD
- .set VE_HEAD = VE_INTON
- XT_INTON:
-00f493 f494 .dw PFA_INTON
- PFA_INTON:
-00f494 9478 sei
-00f495 cb6e jmp_ DO_NEXT
- .include "words/int-off.asm"
-
- ; Interrupt
- ; turns off all interrupts
- VE_INTOFF:
-00f496 ff04 .dw $ff04
-00f497 692d
-00f498 746e .db "-int"
-00f499 f48f .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
- XT_INTOFF:
-00f49a f49b .dw PFA_INTOFF
- PFA_INTOFF:
-00f49b 94f8 cli
-00f49c cb67 jmp_ DO_NEXT
- .include "words/int-store.asm"
-
- ; Interrupt
- ; stores XT as interrupt vector i
- VE_INTSTORE:
-00f49d ff04 .dw $ff04
-00f49e 6e69
-00f49f 2174 .db "int!"
-00f4a0 f496 .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
- XT_INTSTORE:
-00f4a1 f000 .dw DO_COLON
- PFA_INTSTORE:
-00f4a2 f045 .dw XT_DOLITERAL
-00f4a3 0000 .dw intvec
-00f4a4 f1ae .dw XT_PLUS
-00f4a5 f34c .dw XT_STOREE
-00f4a6 f025 .dw XT_EXIT
- .include "words/int-fetch.asm"
-
- ; Interrupt
- ; fetches XT from interrupt vector i
- VE_INTFETCH:
-00f4a7 ff04 .dw $ff04
-00f4a8 6e69
-00f4a9 4074 .db "int@"
-00f4aa f49d .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
- XT_INTFETCH:
-00f4ab f000 .dw DO_COLON
- PFA_INTFETCH:
-00f4ac f045 .dw XT_DOLITERAL
-00f4ad 0000 .dw intvec
-00f4ae f1ae .dw XT_PLUS
-00f4af f370 .dw XT_FETCHE
-00f4b0 f025 .dw XT_EXIT
- .include "words/int-trap.asm"
-
- ; Interrupt
- ; trigger an interrupt
- VE_INTTRAP:
-00f4b1 ff08 .dw $ff08
-00f4b2 6e69
-00f4b3 2d74
-00f4b4 7274
-00f4b5 7061 .db "int-trap"
-00f4b6 f4a7 .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
- XT_INTTRAP:
-00f4b7 f4b8 .dw PFA_INTTRAP
- PFA_INTTRAP:
-00f4b8 2eb8 mov isrflag, tosl
-00f4b9 9189
-00f4ba 9199 loadtos
-00f4bb cb48 jmp_ DO_NEXT
-
- .include "words/isr-exec.asm"
-
- ; Interrupt
- ; executes an interrupt service routine
- ;VE_ISREXEC:
- ; .dw $ff08
- ; .db "isr-exec"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREXEC
- XT_ISREXEC:
-00f4bc f000 .dw DO_COLON
- PFA_ISREXEC:
-00f4bd f4ab .dw XT_INTFETCH
-00f4be f02f .dw XT_EXECUTE
-00f4bf f4c1 .dw XT_ISREND
-00f4c0 f025 .dw XT_EXIT
- .include "words/isr-end.asm"
-
- ; Interrupt
- ; re-enables interrupts in an ISR
- ;VE_ISREND:
- ; .dw $ff07
- ; .db "isr-end",0
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ISREND
- XT_ISREND:
-00f4c1 f4c2 .dw PFA_ISREND
- PFA_ISREND:
-00f4c2 d001 rcall PFA_ISREND1 ; clear the interrupt flag for the controller
-00f4c3 cb40 jmp_ DO_NEXT
- PFA_ISREND1:
-00f4c4 9518 reti
- .endif
-
- .include "words/pick.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PICK:
-00f4c5 ff04 .dw $ff04
-00f4c6 6970
-00f4c7 6b63 .db "pick"
-00f4c8 f4b1 .dw VE_HEAD
- .set VE_HEAD = VE_PICK
- XT_PICK:
-00f4c9 f000 .dw DO_COLON
- PFA_PICK:
- .endif
-00f4ca f240 .dw XT_1PLUS
-00f4cb f572 .dw XT_CELLS
-00f4cc f29e .dw XT_SP_FETCH
-00f4cd f1ae .dw XT_PLUS
-00f4ce f08a .dw XT_FETCH
-00f4cf f025 .dw XT_EXIT
- .include "words/dot-quote.asm"
-
- ; Compiler
- ; compiles string into dictionary to be printed at runtime
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOTSTRING:
-00f4d0 0002 .dw $0002
-00f4d1 222e .db ".",$22
-00f4d2 f4c5 .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
- XT_DOTSTRING:
-00f4d3 f000 .dw DO_COLON
- PFA_DOTSTRING:
- .endif
-00f4d4 f4db .dw XT_SQUOTE
-00f4d5 0184 .dw XT_COMPILE
-00f4d6 f7ba .dw XT_ITYPE
-00f4d7 f025 .dw XT_EXIT
- .include "words/squote.asm"
-
- ; Compiler
- ; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SQUOTE:
-00f4d8 0002 .dw $0002
-00f4d9 2273 .db "s",$22
-00f4da f4d0 .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
- XT_SQUOTE:
-00f4db f000 .dw DO_COLON
- PFA_SQUOTE:
- .endif
-00f4dc f045 .dw XT_DOLITERAL
-00f4dd 0022 .dw 34 ; 0x22
-00f4de f9a1 .dw XT_PARSE ; ( -- addr n)
-00f4df f565 .dw XT_STATE
-00f4e0 f08a .dw XT_FETCH
-00f4e1 f03e .dw XT_DOCONDBRANCH
-00f4e2 f4e4 DEST(PFA_SQUOTE1)
-00f4e3 01b0 .dw XT_SLITERAL
- PFA_SQUOTE1:
-00f4e4 f025 .dw XT_EXIT
-
- .include "words/fill.asm"
-
- ; Memory
- ; fill u bytes memory beginning at a-addr with character c
- VE_FILL:
-00f4e5 ff04 .dw $ff04
-00f4e6 6966
-00f4e7 6c6c .db "fill"
-00f4e8 f4d8 .dw VE_HEAD
- .set VE_HEAD = VE_FILL
- XT_FILL:
-00f4e9 f000 .dw DO_COLON
- PFA_FILL:
-00f4ea f0f2 .dw XT_ROT
-00f4eb f0f2 .dw XT_ROT
-00f4ec f0ca
-00f4ed f03e .dw XT_QDUP,XT_DOCONDBRANCH
-00f4ee f4f6 DEST(PFA_FILL2)
-00f4ef fd89 .dw XT_BOUNDS
-00f4f0 f2ac .dw XT_DODO
- PFA_FILL1:
-00f4f1 f0c2 .dw XT_DUP
-00f4f2 f2bd .dw XT_I
-00f4f3 f09e .dw XT_CSTORE ; ( -- c c-addr)
-00f4f4 f2da .dw XT_DOLOOP
-00f4f5 f4f1 .dw PFA_FILL1
- PFA_FILL2:
-00f4f6 f0ea .dw XT_DROP
-00f4f7 f025 .dw XT_EXIT
-
- .include "words/environment.asm"
-
- ; System Value
- ; word list identifier of the environmental search list
- VE_ENVIRONMENT:
-00f4f8 ff0b .dw $ff0b
-00f4f9 6e65
-00f4fa 6976
-00f4fb 6f72
-00f4fc 6d6e
-00f4fd 6e65
-00f4fe 0074 .db "environment",0
-00f4ff f4e5 .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
- XT_ENVIRONMENT:
-00f500 f053 .dw PFA_DOVARIABLE
- PFA_ENVIRONMENT:
-00f501 0056 .dw CFG_ENVIRONMENT
- .include "words/env-wordlists.asm"
-
- ; Environment
- ; maximum number of wordlists in the dictionary search order
- VE_ENVWORDLISTS:
-00f502 ff09 .dw $ff09
-00f503 6f77
-00f504 6472
-00f505 696c
-00f506 7473
-00f507 0073 .db "wordlists",0
-00f508 0000 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
- XT_ENVWORDLISTS:
-00f509 f000 .dw DO_COLON
- PFA_ENVWORDLISTS:
-00f50a f045 .dw XT_DOLITERAL
-00f50b 0008 .dw NUMWORDLISTS
-00f50c f025 .dw XT_EXIT
- .include "words/env-slashpad.asm"
-
- ; Environment
- ; Size of the PAD buffer in bytes
- VE_ENVSLASHPAD:
-00f50d ff04 .dw $ff04
-00f50e 702f
-00f50f 6461 .db "/pad"
-00f510 f502 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
- XT_ENVSLASHPAD:
-00f511 f000 .dw DO_COLON
- PFA_ENVSLASHPAD:
-00f512 f29e .dw XT_SP_FETCH
-00f513 f59e .dw XT_PAD
-00f514 f1a4 .dw XT_MINUS
-00f515 f025 .dw XT_EXIT
- .include "words/env-slashhold.asm"
-
- ; Environment
- ; size of the pictured numeric output buffer in bytes
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENVSLASHHOLD:
-00f516 ff05 .dw $ff05
-00f517 682f
-00f518 6c6f
-00f519 0064 .db "/hold",0
-00f51a f50d .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
- XT_ENVSLASHHOLD:
-00f51b f000 .dw DO_COLON
- PFA_ENVSLASHHOLD:
- .endif
-00f51c f59e .dw XT_PAD
-00f51d f5d9 .dw XT_HERE
-00f51e f1a4 .dw XT_MINUS
-00f51f f025 .dw XT_EXIT
- .include "words/env-forthname.asm"
-
- ; Environment
- ; flash address of the amforth name string
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHNAME:
-00f520 ff0a .dw $ff0a
-00f521 6f66
-00f522 7472
-00f523 2d68
-00f524 616e
-00f525 656d .db "forth-name"
-00f526 f516 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
- XT_ENV_FORTHNAME:
-00f527 f000 .dw DO_COLON
- PFA_EN_FORTHNAME:
-00f528 f787 .dw XT_DOSLITERAL
-00f529 0007 .dw 7
- .endif
-00f52a 6d61
-00f52b 6f66
-00f52c 7472
-../../common\words/env-forthname.asm(22): warning: .cseg .db misalignment - padding zero byte
-00f52d 0068 .db "amforth"
- .if cpu_msp430==1
- .endif
-00f52e f025 .dw XT_EXIT
- .include "words/env-forthversion.asm"
-
- ; Environment
- ; version number of amforth
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_FORTHVERSION:
-00f52f ff07 .dw $ff07
-00f530 6576
-00f531 7372
-00f532 6f69
-00f533 006e .db "version",0
-00f534 f520 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
- XT_ENV_FORTHVERSION:
-00f535 f000 .dw DO_COLON
- PFA_EN_FORTHVERSION:
- .endif
-00f536 f045 .dw XT_DOLITERAL
-00f537 0041 .dw 65
-00f538 f025 .dw XT_EXIT
- .include "words/env-cpu.asm"
-
- ; Environment
- ; flash address of the CPU identification string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ENV_CPU:
-00f539 ff03 .dw $ff03
-00f53a 7063
-00f53b 0075 .db "cpu",0
-00f53c f52f .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
- XT_ENV_CPU:
-00f53d f000 .dw DO_COLON
- PFA_EN_CPU:
- .endif
-00f53e f045 .dw XT_DOLITERAL
-00f53f 0049 .dw mcu_name
-00f540 f7e6 .dw XT_ICOUNT
-00f541 f025 .dw XT_EXIT
- .include "words/env-mcuinfo.asm"
-
- ; Environment
- ; flash address of some CPU specific parameters
- VE_ENV_MCUINFO:
-00f542 ff08 .dw $ff08
-00f543 636d
-00f544 2d75
-00f545 6e69
-00f546 6f66 .db "mcu-info"
-00f547 f539 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
- XT_ENV_MCUINFO:
-00f548 f000 .dw DO_COLON
- PFA_EN_MCUINFO:
-00f549 f045 .dw XT_DOLITERAL
-00f54a 0045 .dw mcu_info
-00f54b f025 .dw XT_EXIT
- .include "words/env-usersize.asm"
-
- ; Environment
- ; size of the USER area in bytes
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_ENVUSERSIZE:
-00f54c ff05 .dw $ff05
-00f54d 752f
-00f54e 6573
-00f54f 0072 .db "/user",0
-00f550 f542 .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
- XT_ENVUSERSIZE:
-00f551 f000 .dw DO_COLON
- PFA_ENVUSERSIZE:
- .endif
-00f552 f045 .dw XT_DOLITERAL
-00f553 002c .dw SYSUSERSIZE + APPUSERSIZE
-00f554 f025 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/f_cpu.asm"
-
- ; System
- ; put the cpu frequency in Hz on stack
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_F_CPU:
-00f555 ff05 .dw $ff05
-00f556 5f66
-00f557 7063
-00f558 0075 .db "f_cpu",0
-00f559 f4f8 .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
- XT_F_CPU:
-00f55a f000 .dw DO_COLON
- PFA_F_CPU:
- .endif
-00f55b f045 .dw XT_DOLITERAL
-00f55c 1200 .dw (F_CPU % 65536)
-00f55d f045 .dw XT_DOLITERAL
-00f55e 007a .dw (F_CPU / 65536)
-00f55f f025 .dw XT_EXIT
- .include "words/state.asm"
-
- ; System Variable
- ; system state
- VE_STATE:
-00f560 ff05 .dw $ff05
-00f561 7473
-00f562 7461
-00f563 0065 .db "state",0
-00f564 f555 .dw VE_HEAD
- .set VE_HEAD = VE_STATE
- XT_STATE:
-00f565 f053 .dw PFA_DOVARIABLE
- PFA_STATE:
-00f566 013d .dw ram_state
-
- .dseg
-00013d ram_state: .byte 2
- .include "words/base.asm"
-
- ; Numeric IO
- ; location of the cell containing the number conversion radix
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BASE:
-00f567 ff04 .dw $ff04
-00f568 6162
-00f569 6573 .db "base"
-00f56a f560 .dw VE_HEAD
- .set VE_HEAD = VE_BASE
- XT_BASE:
-00f56b f066 .dw PFA_DOUSER
- PFA_BASE:
- .endif
-00f56c 000c .dw USER_BASE
-
- .include "words/cells.asm"
-
- ; Arithmetics
- ; n2 is the size in address units of n1 cells
- VE_CELLS:
-00f56d ff05 .dw $ff05
-00f56e 6563
-00f56f 6c6c
-00f570 0073 .db "cells",0
-00f571 f567 .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
- XT_CELLS:
-00f572 f21d .dw PFA_2STAR
- .include "words/cellplus.asm"
-
- ; Arithmetics
- ; add the size of an address-unit to a-addr1
- VE_CELLPLUS:
-00f573 ff05 .dw $ff05
-00f574 6563
-00f575 6c6c
-00f576 002b .db "cell+",0
-00f577 f56d .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
- XT_CELLPLUS:
-00f578 f579 .dw PFA_CELLPLUS
- PFA_CELLPLUS:
-00f579 9602 adiw tosl, CELLSIZE
-00f57a ca89 jmp_ DO_NEXT
-
- .include "words/2dup.asm"
-
- ; Stack
- ; Duplicate the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DUP:
-00f57b ff04 .dw $ff04
-00f57c 6432
-00f57d 7075 .db "2dup"
-00f57e f573 .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
- XT_2DUP:
-00f57f f000 .dw DO_COLON
- PFA_2DUP:
- .endif
-
-00f580 f0e0 .dw XT_OVER
-00f581 f0e0 .dw XT_OVER
-00f582 f025 .dw XT_EXIT
- .include "words/2drop.asm"
-
- ; Stack
- ; Remove the 2 top elements
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2DROP:
-00f583 ff05 .dw $ff05
-00f584 6432
-00f585 6f72
-00f586 0070 .db "2drop",0
-00f587 f57b .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
- XT_2DROP:
-00f588 f000 .dw DO_COLON
- PFA_2DROP:
- .endif
-00f589 f0ea .dw XT_DROP
-00f58a f0ea .dw XT_DROP
-00f58b f025 .dw XT_EXIT
-
- .include "words/tuck.asm"
-
- ; Stack
- ; Copy the first (top) stack item below the second stack item.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TUCK:
-00f58c ff04 .dw $ff04
-00f58d 7574
-00f58e 6b63 .db "tuck"
-00f58f f583 .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
- XT_TUCK:
-00f590 f000 .dw DO_COLON
- PFA_TUCK:
- .endif
-00f591 f0d5 .dw XT_SWAP
-00f592 f0e0 .dw XT_OVER
-00f593 f025 .dw XT_EXIT
-
- .include "words/to-in.asm"
-
- ; System Variable
- ; pointer to current read position in input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_IN:
-00f594 ff03 .dw $ff03
-00f595 693e
-00f596 006e .db ">in",0
-00f597 f58c .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
- XT_TO_IN:
-00f598 f066 .dw PFA_DOUSER
- PFA_TO_IN:
- .endif
-00f599 0018 .dw USER_TO_IN
- .include "words/pad.asm"
-
- ; System Variable
- ; Address of the temporary scratch buffer.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PAD:
-00f59a ff03 .dw $ff03
-00f59b 6170
-00f59c 0064 .db "pad",0
-00f59d f594 .dw VE_HEAD
- .set VE_HEAD = VE_PAD
- XT_PAD:
-00f59e f000 .dw DO_COLON
- PFA_PAD:
- .endif
-00f59f f5d9 .dw XT_HERE
-00f5a0 f045 .dw XT_DOLITERAL
-00f5a1 0028 .dw 40
-00f5a2 f1ae .dw XT_PLUS
-00f5a3 f025 .dw XT_EXIT
- .include "words/emit.asm"
-
- ; Character IO
- ; fetch the emit vector and execute it. should emit a character from TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMIT:
-00f5a4 ff04 .dw $ff04
-00f5a5 6d65
-00f5a6 7469 .db "emit"
-00f5a7 f59a .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
- XT_EMIT:
-00f5a8 fc2d .dw PFA_DODEFER1
- PFA_EMIT:
- .endif
-00f5a9 000e .dw USER_EMIT
-00f5aa fbf6 .dw XT_UDEFERFETCH
-00f5ab fc02 .dw XT_UDEFERSTORE
- .include "words/emitq.asm"
-
- ; Character IO
- ; fetch emit? vector and execute it. should return the ready-to-send condition
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_EMITQ:
-00f5ac ff05 .dw $ff05
-00f5ad 6d65
-00f5ae 7469
-00f5af 003f .db "emit?",0
-00f5b0 f5a4 .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
- XT_EMITQ:
-00f5b1 fc2d .dw PFA_DODEFER1
- PFA_EMITQ:
- .endif
-00f5b2 0010 .dw USER_EMITQ
-00f5b3 fbf6 .dw XT_UDEFERFETCH
-00f5b4 fc02 .dw XT_UDEFERSTORE
- .include "words/key.asm"
-
- ; Character IO
- ; fetch key vector and execute it, should leave a single character on TOS
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEY:
-00f5b5 ff03 .dw $ff03
-00f5b6 656b
-00f5b7 0079 .db "key",0
-00f5b8 f5ac .dw VE_HEAD
- .set VE_HEAD = VE_KEY
- XT_KEY:
-00f5b9 fc2d .dw PFA_DODEFER1
- PFA_KEY:
- .endif
-00f5ba 0012 .dw USER_KEY
-00f5bb fbf6 .dw XT_UDEFERFETCH
-00f5bc fc02 .dw XT_UDEFERSTORE
- .include "words/keyq.asm"
-
- ; Character IO
- ; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_KEYQ:
-00f5bd ff04 .dw $ff04
-00f5be 656b
-00f5bf 3f79 .db "key?"
-00f5c0 f5b5 .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
- XT_KEYQ:
-00f5c1 fc2d .dw PFA_DODEFER1
- PFA_KEYQ:
- .endif
-00f5c2 0014 .dw USER_KEYQ
-00f5c3 fbf6 .dw XT_UDEFERFETCH
-00f5c4 fc02 .dw XT_UDEFERSTORE
-
- .include "words/dp.asm"
-
- ; System Value
- ; address of the next free dictionary cell
- VE_DP:
-00f5c5 ff02 .dw $ff02
-00f5c6 7064 .db "dp"
-00f5c7 f5bd .dw VE_HEAD
- .set VE_HEAD = VE_DP
- XT_DP:
-00f5c8 f080 .dw PFA_DOVALUE1
- PFA_DP:
-00f5c9 0048 .dw CFG_DP
-00f5ca fbce .dw XT_EDEFERFETCH
-00f5cb fbd8 .dw XT_EDEFERSTORE
- .include "words/ehere.asm"
-
- ; System Value
- ; address of the next free address in eeprom
- VE_EHERE:
-00f5cc ff05 .dw $ff05
-00f5cd 6865
-00f5ce 7265
-00f5cf 0065 .db "ehere",0
-00f5d0 f5c5 .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
- XT_EHERE:
-00f5d1 f080 .dw PFA_DOVALUE1
- PFA_EHERE:
-00f5d2 004c .dw EE_EHERE
-00f5d3 fbce .dw XT_EDEFERFETCH
-00f5d4 fbd8 .dw XT_EDEFERSTORE
- .include "words/here.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_HERE:
-00f5d5 ff04 .dw $ff04
-00f5d6 6568
-00f5d7 6572 .db "here"
-00f5d8 f5cc .dw VE_HEAD
- .set VE_HEAD = VE_HERE
- XT_HERE:
-00f5d9 f080 .dw PFA_DOVALUE1
- PFA_HERE:
-00f5da 004a .dw EE_HERE
-00f5db fbce .dw XT_EDEFERFETCH
-00f5dc fbd8 .dw XT_EDEFERSTORE
- .include "words/allot.asm"
-
- ; System
- ; allocate or release memory in RAM
- VE_ALLOT:
-00f5dd ff05 .dw $ff05
-00f5de 6c61
-00f5df 6f6c
-00f5e0 0074 .db "allot",0
-00f5e1 f5d5 .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
- XT_ALLOT:
-00f5e2 f000 .dw DO_COLON
- PFA_ALLOT:
-00f5e3 f5d9 .dw XT_HERE
-00f5e4 f1ae .dw XT_PLUS
-00f5e5 fbb3 .dw XT_DOTO
-00f5e6 f5da .dw PFA_HERE
-00f5e7 f025 .dw XT_EXIT
-
- .include "words/bin.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BIN:
-00f5e8 ff03 .dw $ff03
-00f5e9 6962
-00f5ea 006e .db "bin",0
-00f5eb f5dd .dw VE_HEAD
- .set VE_HEAD = VE_BIN
- XT_BIN:
-00f5ec f000 .dw DO_COLON
- PFA_BIN:
- .endif
-00f5ed fdb6 .dw XT_TWO
-00f5ee f56b .dw XT_BASE
-00f5ef f092 .dw XT_STORE
-00f5f0 f025 .dw XT_EXIT
- .include "words/decimal.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DECIMAL:
-00f5f1 ff07 .dw $ff07
-00f5f2 6564
-00f5f3 6963
-00f5f4 616d
-00f5f5 006c .db "decimal",0
-00f5f6 f5e8 .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
- XT_DECIMAL:
-00f5f7 f000 .dw DO_COLON
- PFA_DECIMAL:
- .endif
-00f5f8 f045 .dw XT_DOLITERAL
-00f5f9 000a .dw 10
-00f5fa f56b .dw XT_BASE
-00f5fb f092 .dw XT_STORE
-00f5fc f025 .dw XT_EXIT
- .include "words/hex.asm"
-
- ; Numeric IO
- ; set base for numeric conversion to 10
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HEX:
-00f5fd ff03 .dw $ff03
-00f5fe 6568
-00f5ff 0078 .db "hex",0
-00f600 f5f1 .dw VE_HEAD
- .set VE_HEAD = VE_HEX
- XT_HEX:
-00f601 f000 .dw DO_COLON
- PFA_HEX:
- .endif
-00f602 f045 .dw XT_DOLITERAL
-00f603 0010 .dw 16
-00f604 f56b .dw XT_BASE
-00f605 f092 .dw XT_STORE
-00f606 f025 .dw XT_EXIT
- .include "words/bl.asm"
-
- ; Character IO
- ; put ascii code of the blank to the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BL:
-00f607 ff02 .dw $ff02
-00f608 6c62 .db "bl"
-00f609 f5fd .dw VE_HEAD
- .set VE_HEAD = VE_BL
- XT_BL:
-00f60a f053 .dw PFA_DOVARIABLE
- PFA_BL:
- .endif
-00f60b 0020 .dw 32
-
- .include "words/turnkey.asm"
-
- ; System Value
- ; Deferred action during startup/reset
- VE_TURNKEY:
-00f60c ff07 .dw $ff07
-00f60d 7574
-00f60e 6e72
-00f60f 656b
-00f610 0079 .db "turnkey",0
-00f611 f607 .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
- XT_TURNKEY:
-00f612 fc2d .dw PFA_DODEFER1
- PFA_TURNKEY:
-00f613 0054 .dw CFG_TURNKEY
-00f614 fbce .dw XT_EDEFERFETCH
-00f615 fbd8 .dw XT_EDEFERSTORE
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/slashmod.asm"
-
- ; Arithmetics
- ; signed division n1/n2 with remainder and quotient
- VE_SLASHMOD:
-00f616 ff04 .dw $ff04
-00f617 6d2f
-00f618 646f .db "/mod"
-00f619 f60c .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
- XT_SLASHMOD:
-00f61a f61b .dw PFA_SLASHMOD
- PFA_SLASHMOD:
-00f61b 019c movw temp2, tosl
-
-00f61c 9109 ld temp0, Y+
-00f61d 9119 ld temp1, Y+
-
-00f61e 2f41 mov temp6,temp1 ;move dividend High to sign register
-00f61f 2743 eor temp6,temp3 ;xor divisor High with sign register
-00f620 ff17 sbrs temp1,7 ;if MSB in dividend set
-00f621 c004 rjmp PFA_SLASHMOD_1
-00f622 9510 com temp1 ; change sign of dividend
-00f623 9500 com temp0
-00f624 5f0f subi temp0,low(-1)
-00f625 4f1f sbci temp1,high(-1)
- PFA_SLASHMOD_1:
-00f626 ff37 sbrs temp3,7 ;if MSB in divisor set
-00f627 c004 rjmp PFA_SLASHMOD_2
-00f628 9530 com temp3 ; change sign of divisor
-00f629 9520 com temp2
-00f62a 5f2f subi temp2,low(-1)
-00f62b 4f3f sbci temp3,high(-1)
-00f62c 24ee PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
-00f62d 18ff sub temp5,temp5;clear remainder High byte and carry
-00f62e e151 ldi temp7,17 ;init loop counter
-
-00f62f 1f00 PFA_SLASHMOD_3: rol temp0 ;shift left dividend
-00f630 1f11 rol temp1
-00f631 955a dec temp7 ;decrement counter
-00f632 f439 brne PFA_SLASHMOD_5 ;if done
-00f633 ff47 sbrs temp6,7 ; if MSB in sign register set
-00f634 c004 rjmp PFA_SLASHMOD_4
-00f635 9510 com temp1 ; change sign of result
-00f636 9500 com temp0
-00f637 5f0f subi temp0,low(-1)
-00f638 4f1f sbci temp1,high(-1)
-00f639 c00b PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-00f63a 1cee PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
-00f63b 1cff rol temp5
-00f63c 1ae2 sub temp4,temp2 ;remainder = remainder - divisor
-00f63d 0af3 sbc temp5,temp3 ;
-00f63e f420 brcc PFA_SLASHMOD_6 ;if result negative
-00f63f 0ee2 add temp4,temp2 ; restore remainder
-00f640 1ef3 adc temp5,temp3
-00f641 9488 clc ; clear carry to be shifted into result
-00f642 cfec rjmp PFA_SLASHMOD_3 ;else
-00f643 9408 PFA_SLASHMOD_6: sec ; set carry to be shifted into result
-00f644 cfea rjmp PFA_SLASHMOD_3
-
- PFA_SLASHMODmod_done:
- ; put remainder on stack
-00f645 92fa st -Y,temp5
-00f646 92ea st -Y,temp4
-
- ; put quotient on stack
-00f647 01c8 movw tosl, temp0
-00f648 c9bb jmp_ DO_NEXT
- .include "words/uslashmod.asm"
-
- ; Arithmetics
- ; unsigned division with remainder
- VE_USLASHMOD:
-00f649 ff05 .dw $ff05
-00f64a 2f75
-00f64b 6f6d
-00f64c 0064 .db "u/mod",0
-00f64d f616 .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
- XT_USLASHMOD:
-00f64e f000 .dw DO_COLON
- PFA_USLASHMOD:
-00f64f f110 .dw XT_TO_R
-00f650 f165 .dw XT_ZERO
-00f651 f107 .dw XT_R_FROM
-00f652 f1d3 .dw XT_UMSLASHMOD
-00f653 f025 .dw XT_EXIT
- .include "words/negate.asm"
-
- ; Logic
- ; 2-complement
- VE_NEGATE:
-00f654 ff06 .dw $ff06
-00f655 656e
-00f656 6167
-00f657 6574 .db "negate"
-00f658 f649 .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
- XT_NEGATE:
-00f659 f000 .dw DO_COLON
- PFA_NEGATE:
-00f65a f20e .dw XT_INVERT
-00f65b f240 .dw XT_1PLUS
-00f65c f025 .dw XT_EXIT
- .include "words/slash.asm"
-
- ; Arithmetics
- ; divide n1 by n2. giving the quotient
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SLASH:
-00f65d ff01 .dw $ff01
-00f65e 002f .db "/",0
-00f65f f654 .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
- XT_SLASH:
-00f660 f000 .dw DO_COLON
- PFA_SLASH:
- .endif
-00f661 f61a .dw XT_SLASHMOD
-00f662 f101 .dw XT_NIP
-00f663 f025 .dw XT_EXIT
-
- .include "words/mod.asm"
-
- ; Arithmetics
- ; divide n1 by n2 giving the remainder n3
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MOD:
-00f664 ff03 .dw $ff03
-00f665 6f6d
-00f666 0064 .db "mod",0
-00f667 f65d .dw VE_HEAD
- .set VE_HEAD = VE_MOD
- XT_MOD:
-00f668 f000 .dw DO_COLON
- PFA_MOD:
- .endif
-00f669 f61a .dw XT_SLASHMOD
-00f66a f0ea .dw XT_DROP
-00f66b f025 .dw XT_EXIT
- .include "words/abs.asm"
-
- ; DUP ?NEGATE ;
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ABS:
-00f66c ff03 .dw $ff03
-00f66d 6261
-00f66e 0073 .db "abs",0
-00f66f f664 .dw VE_HEAD
- .set VE_HEAD = VE_ABS
- XT_ABS:
-00f670 f000 .dw DO_COLON
- PFA_ABS:
-
- .endif
-
-00f671 f0c2
-00f672 f24f
-00f673 f025 .DW XT_DUP,XT_QNEGATE,XT_EXIT
- .include "words/min.asm"
-
- ; Compare
- ; compare two values leave the smaller one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_MIN:
-00f674 ff03 .dw $ff03
-00f675 696d
-00f676 006e .db "min",0
-00f677 f66c .dw VE_HEAD
- .set VE_HEAD = VE_MIN
- XT_MIN:
-00f678 f000 .dw DO_COLON
- PFA_MIN:
- .endif
-00f679 f57f .dw XT_2DUP
-00f67a f189 .dw XT_GREATER
-00f67b f03e .dw XT_DOCONDBRANCH
-00f67c f67e DEST(PFA_MIN1)
-00f67d f0d5 .dw XT_SWAP
- PFA_MIN1:
-00f67e f0ea .dw XT_DROP
-00f67f f025 .dw XT_EXIT
- .include "words/max.asm"
-
- ; Compare
- ; compare two values, leave the bigger one
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MAX:
-00f680 ff03 .dw $ff03
-00f681 616d
-00f682 0078 .db "max",0
-00f683 f674 .dw VE_HEAD
- .set VE_HEAD = VE_MAX
- XT_MAX:
-00f684 f000 .dw DO_COLON
- PFA_MAX:
-
- .endif
-00f685 f57f .dw XT_2DUP
-00f686 f17f .dw XT_LESS
-00f687 f03e .dw XT_DOCONDBRANCH
-00f688 f68a DEST(PFA_MAX1)
-00f689 f0d5 .dw XT_SWAP
- PFA_MAX1:
-00f68a f0ea .dw XT_DROP
-00f68b f025 .dw XT_EXIT
- .include "words/within.asm"
-
- ; Compare
- ; check if n is within min..max
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WITHIN:
-00f68c ff06 .dw $ff06
-00f68d 6977
-00f68e 6874
-00f68f 6e69 .db "within"
-00f690 f680 .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
- XT_WITHIN:
-00f691 f000 .dw DO_COLON
- PFA_WITHIN:
- .endif
-00f692 f0e0 .dw XT_OVER
-00f693 f1a4 .dw XT_MINUS
-00f694 f110 .dw XT_TO_R
-00f695 f1a4 .dw XT_MINUS
-00f696 f107 .dw XT_R_FROM
-00f697 f16d .dw XT_ULESS
-00f698 f025 .dw XT_EXIT
-
- .include "words/to-upper.asm"
-
- ; String
- ; if c is a lowercase letter convert it to uppercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TOUPPER:
-00f699 ff07 .dw $ff07
-00f69a 6f74
-00f69b 7075
-00f69c 6570
-00f69d 0072 .db "toupper",0
-00f69e f68c .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
- XT_TOUPPER:
-00f69f f000 .dw DO_COLON
- PFA_TOUPPER:
- .endif
-00f6a0 f0c2 .dw XT_DUP
-00f6a1 f045 .dw XT_DOLITERAL
-00f6a2 0061 .dw 'a'
-00f6a3 f045 .dw XT_DOLITERAL
-00f6a4 007b .dw 'z'+1
-00f6a5 f691 .dw XT_WITHIN
-00f6a6 f03e .dw XT_DOCONDBRANCH
-00f6a7 f6ab DEST(PFA_TOUPPER0)
-00f6a8 f045 .dw XT_DOLITERAL
-00f6a9 00df .dw 223 ; inverse of 0x20: 0xdf
-00f6aa f224 .dw XT_AND
- PFA_TOUPPER0:
-00f6ab f025 .dw XT_EXIT
- .include "words/to-lower.asm"
-
- ; String
- ; if C is an uppercase letter convert it to lowercase
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_TOLOWER:
-00f6ac ff07 .dw $ff07
-00f6ad 6f74
-00f6ae 6f6c
-00f6af 6577
-00f6b0 0072 .db "tolower",0
-00f6b1 f699 .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
- XT_TOLOWER:
-00f6b2 f000 .dw DO_COLON
- PFA_TOLOWER:
- .endif
-00f6b3 f0c2 .dw XT_DUP
-00f6b4 f045 .dw XT_DOLITERAL
-00f6b5 0041 .dw 'A'
-00f6b6 f045 .dw XT_DOLITERAL
-00f6b7 005b .dw 'Z'+1
-00f6b8 f691 .dw XT_WITHIN
-00f6b9 f03e .dw XT_DOCONDBRANCH
-00f6ba f6be DEST(PFA_TOLOWER0)
-00f6bb f045 .dw XT_DOLITERAL
-00f6bc 0020 .dw 32
-00f6bd f22d .dw XT_OR
- PFA_TOLOWER0:
-00f6be f025 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;
- .include "words/hld.asm"
-
- ; Numeric IO
- ; pointer to current write position in the Pictured Numeric Output buffer
- VE_HLD:
-00f6bf ff03 .dw $ff03
-00f6c0 6c68
-00f6c1 0064 .db "hld",0
-00f6c2 f6ac .dw VE_HEAD
- .set VE_HEAD = VE_HLD
- XT_HLD:
-00f6c3 f053 .dw PFA_DOVARIABLE
- PFA_HLD:
-00f6c4 013f .dw ram_hld
-
- .dseg
-00013f ram_hld: .byte 2
- .cseg
- .include "words/hold.asm"
-
- ; Numeric IO
- ; prepend character to pictured numeric output buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HOLD:
-00f6c5 ff04 .dw $ff04
-00f6c6 6f68
-00f6c7 646c .db "hold"
-00f6c8 f6bf .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
- XT_HOLD:
-00f6c9 f000 .dw DO_COLON
- PFA_HOLD:
- .endif
-00f6ca f6c3 .dw XT_HLD
-00f6cb f0c2 .dw XT_DUP
-00f6cc f08a .dw XT_FETCH
-00f6cd f246 .dw XT_1MINUS
-00f6ce f0c2 .dw XT_DUP
-00f6cf f110 .dw XT_TO_R
-00f6d0 f0d5 .dw XT_SWAP
-00f6d1 f092 .dw XT_STORE
-00f6d2 f107 .dw XT_R_FROM
-00f6d3 f09e .dw XT_CSTORE
-00f6d4 f025 .dw XT_EXIT
- .include "words/less-sharp.asm" ; <#
-
- ; Numeric IO
- ; initialize the pictured numeric output conversion process
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_L_SHARP:
-00f6d5 ff02 .dw $ff02
-00f6d6 233c .db "<#"
-00f6d7 f6c5 .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
- XT_L_SHARP:
-00f6d8 f000 .dw DO_COLON
- PFA_L_SHARP:
- .endif
-00f6d9 f59e .dw XT_PAD
-00f6da f6c3 .dw XT_HLD
-00f6db f092 .dw XT_STORE
-00f6dc f025 .dw XT_EXIT
- .include "words/sharp.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert one digit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_SHARP:
-00f6dd ff01 .dw $ff01
-00f6de 0023 .db "#",0
-00f6df f6d5 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
- XT_SHARP:
-00f6e0 f000 .dw DO_COLON
- PFA_SHARP:
- .endif
-00f6e1 f56b .dw XT_BASE
-00f6e2 f08a .dw XT_FETCH
-00f6e3 f75d .dw XT_UDSLASHMOD
-00f6e4 f0f2 .dw XT_ROT
-00f6e5 f045 .dw XT_DOLITERAL
-00f6e6 0009 .dw 9
-00f6e7 f0e0 .dw XT_OVER
-00f6e8 f17f .dw XT_LESS
-00f6e9 f03e .dw XT_DOCONDBRANCH
-00f6ea f6ee DEST(PFA_SHARP1)
-00f6eb f045 .dw XT_DOLITERAL
-00f6ec 0007 .dw 7
-00f6ed f1ae .dw XT_PLUS
- PFA_SHARP1:
-00f6ee f045 .dw XT_DOLITERAL
-00f6ef 0030 .dw 48 ; ASCII 0
-00f6f0 f1ae .dw XT_PLUS
-00f6f1 f6c9 .dw XT_HOLD
-00f6f2 f025 .dw XT_EXIT
- ; : # ( ud1 -- ud2 )
- ; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
- .include "words/sharp-s.asm"
-
- ; Numeric IO
- ; pictured numeric output: convert all digits until 0 (zero) is reached
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_S:
-00f6f3 ff02 .dw $ff02
-00f6f4 7323 .db "#s"
-00f6f5 f6dd .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
- XT_SHARP_S:
-00f6f6 f000 .dw DO_COLON
- PFA_SHARP_S:
- .endif
- NUMS1:
-00f6f7 f6e0 .dw XT_SHARP
-00f6f8 f57f .dw XT_2DUP
-00f6f9 f22d .dw XT_OR
-00f6fa f12b .dw XT_ZEROEQUAL
-00f6fb f03e .dw XT_DOCONDBRANCH
-00f6fc f6f7 DEST(NUMS1) ; PFA_SHARP_S
-00f6fd f025 .dw XT_EXIT
- .include "words/sharp-greater.asm" ; #>
-
- ; Numeric IO
- ; Pictured Numeric Output: convert PNO buffer into an string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SHARP_G:
-00f6fe ff02 .dw $ff02
-00f6ff 3e23 .db "#>"
-00f700 f6f3 .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
- XT_SHARP_G:
-00f701 f000 .dw DO_COLON
- PFA_SHARP_G:
- .endif
-00f702 f588 .dw XT_2DROP
-00f703 f6c3 .dw XT_HLD
-00f704 f08a .dw XT_FETCH
-00f705 f59e .dw XT_PAD
-00f706 f0e0 .dw XT_OVER
-00f707 f1a4 .dw XT_MINUS
-00f708 f025 .dw XT_EXIT
- .include "words/sign.asm"
-
- ; Numeric IO
- ; place a - in HLD if n is negative
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SIGN:
-00f709 ff04 .dw $ff04
-00f70a 6973
-00f70b 6e67 .db "sign"
-00f70c f6fe .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
- XT_SIGN:
-00f70d f000 .dw DO_COLON
- PFA_SIGN:
- .endif
-00f70e f132 .dw XT_ZEROLESS
-00f70f f03e .dw XT_DOCONDBRANCH
-00f710 f714 DEST(PFA_SIGN1)
-00f711 f045 .dw XT_DOLITERAL
-00f712 002d .dw 45 ; ascii -
-00f713 f6c9 .dw XT_HOLD
- PFA_SIGN1:
-00f714 f025 .dw XT_EXIT
- .include "words/d-dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOTR:
-00f715 ff03 .dw $ff03
-00f716 2e64
-00f717 0072 .db "d.r",0
-00f718 f709 .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
- XT_DDOTR:
-00f719 f000 .dw DO_COLON
- PFA_DDOTR:
-
- .endif
-00f71a f110 .dw XT_TO_R
-00f71b f590 .dw XT_TUCK
-00f71c fcff .dw XT_DABS
-00f71d f6d8 .dw XT_L_SHARP
-00f71e f6f6 .dw XT_SHARP_S
-00f71f f0f2 .dw XT_ROT
-00f720 f70d .dw XT_SIGN
-00f721 f701 .dw XT_SHARP_G
-00f722 f107 .dw XT_R_FROM
-00f723 f0e0 .dw XT_OVER
-00f724 f1a4 .dw XT_MINUS
-00f725 f805 .dw XT_SPACES
-00f726 f815 .dw XT_TYPE
-00f727 f025 .dw XT_EXIT
- ; : d.r ( d n -- )
- ; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
- .include "words/dot-r.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOTR:
-00f728 ff02 .dw $ff02
-00f729 722e .db ".r"
-00f72a f715 .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
- XT_DOTR:
-00f72b f000 .dw DO_COLON
- PFA_DOTR:
-
- .endif
-00f72c f110 .dw XT_TO_R
-00f72d fd92 .dw XT_S2D
-00f72e f107 .dw XT_R_FROM
-00f72f f719 .dw XT_DDOTR
-00f730 f025 .dw XT_EXIT
- ; : .r ( s n -- ) >r s>d r> d.r ;
- .include "words/d-dot.asm"
-
- ; Numeric IO
- ; singed PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DDOT:
-00f731 ff02 .dw $ff02
-00f732 2e64 .db "d."
-00f733 f728 .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
- XT_DDOT:
-00f734 f000 .dw DO_COLON
- PFA_DDOT:
-
- .endif
-00f735 f165 .dw XT_ZERO
-00f736 f719 .dw XT_DDOTR
-00f737 f7fc .dw XT_SPACE
-00f738 f025 .dw XT_EXIT
- ; : d. ( d -- ) 0 d.r space ;
- .include "words/dot.asm"
-
- ; Numeric IO
- ; singed PNO with single cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_DOT:
-00f739 ff01 .dw $ff01
-00f73a 002e .db ".",0
-00f73b f731 .dw VE_HEAD
- .set VE_HEAD = VE_DOT
- XT_DOT:
-00f73c f000 .dw DO_COLON
- PFA_DOT:
- .endif
-00f73d fd92 .dw XT_S2D
-00f73e f734 .dw XT_DDOT
-00f73f f025 .dw XT_EXIT
- ; : . ( s -- ) s>d d. ;
- .include "words/ud-dot.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDDOT:
-00f740 ff03 .dw $ff03
-00f741 6475
-00f742 002e .db "ud.",0
-00f743 f739 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
- XT_UDDOT:
-00f744 f000 .dw DO_COLON
- PFA_UDDOT:
- .endif
-00f745 f165 .dw XT_ZERO
-00f746 f74d .dw XT_UDDOTR
-00f747 f7fc .dw XT_SPACE
-00f748 f025 .dw XT_EXIT
- .include "words/ud-dot-r.asm"
-
- ; Numeric IO
- ; unsigned PNO with double cell numbers, right aligned in width w
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
-
- VE_UDDOTR:
-00f749 ff04 .dw $ff04
-00f74a 6475
-00f74b 722e .db "ud.r"
-00f74c f740 .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
- XT_UDDOTR:
-00f74d f000 .dw DO_COLON
- PFA_UDDOTR:
- .endif
-00f74e f110 .dw XT_TO_R
-00f74f f6d8 .dw XT_L_SHARP
-00f750 f6f6 .dw XT_SHARP_S
-00f751 f701 .dw XT_SHARP_G
-00f752 f107 .dw XT_R_FROM
-00f753 f0e0 .dw XT_OVER
-00f754 f1a4 .dw XT_MINUS
-00f755 f805 .dw XT_SPACES
-00f756 f815 .dw XT_TYPE
-00f757 f025 .dw XT_EXIT
- .include "words/ud-slash-mod.asm"
-
- ; Arithmetics
- ; unsigned double cell division with remainder
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDSLASHMOD:
-00f758 ff06 .dw $ff06
-00f759 6475
-00f75a 6d2f
-00f75b 646f .db "ud/mod"
-00f75c f749 .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
- XT_UDSLASHMOD:
-00f75d f000 .dw DO_COLON
- PFA_UDSLASHMOD:
- .endif
-00f75e f110 .dw XT_TO_R
-00f75f f165 .dw XT_ZERO
-00f760 f119 .dw XT_R_FETCH
-00f761 f1d3 .dw XT_UMSLASHMOD
-00f762 f107 .dw XT_R_FROM
-00f763 f0d5 .dw XT_SWAP
-00f764 f110 .dw XT_TO_R
-00f765 f1d3 .dw XT_UMSLASHMOD
-00f766 f107 .dw XT_R_FROM
-00f767 f025 .dw XT_EXIT
- .include "words/digit-q.asm"
-
- ; Numeric IO
- ; tries to convert a character to a number, set flag accordingly
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DIGITQ:
-00f768 ff06 .dw $ff06
-00f769 6964
-00f76a 6967
-00f76b 3f74 .db "digit?"
-00f76c f758 .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
- XT_DIGITQ:
-00f76d f000 .dw DO_COLON
- PFA_DIGITQ:
- .endif
-00f76e f69f .dw XT_TOUPPER
-00f76f f0c2
-00f770 f045
-00f771 0039
-00f772 f189
-00f773 f045
-00f774 0100 .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
-00f775 f224
-00f776 f1ae
-00f777 f0c2
-00f778 f045
-00f779 0140
-00f77a f189 .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
-00f77b f045
-00f77c 0107
-00f77d f224
-00f77e f1a4
-00f77f f045
-00f780 0030 .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
-00f781 f1a4
-00f782 f0c2
-00f783 f56b
-00f784 f08a
-00f785 f16d .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
-00f786 f025 .DW XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/do-sliteral.asm"
-
- ; String
- ; runtime portion of sliteral
- ;VE_DOSLITERAL:
- ; .dw $ff0a
- ; .db "(sliteral)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSLITERAL
- XT_DOSLITERAL:
-00f787 f000 .dw DO_COLON
- PFA_DOSLITERAL:
-00f788 f119 .dw XT_R_FETCH ; ( -- addr )
-00f789 f7e6 .dw XT_ICOUNT
-00f78a f107 .dw XT_R_FROM
-00f78b f0e0 .dw XT_OVER ; ( -- addr' n addr n)
-00f78c f240 .dw XT_1PLUS
-00f78d f215 .dw XT_2SLASH ; ( -- addr' n addr k )
-00f78e f1ae .dw XT_PLUS ; ( -- addr' n addr'' )
-00f78f f240 .dw XT_1PLUS
-00f790 f110 .dw XT_TO_R ; ( -- )
-00f791 f025 .dw XT_EXIT
- .include "words/scomma.asm"
-
- ; Compiler
- ; compiles a string from RAM to Flash
- VE_SCOMMA:
-00f792 ff02 .dw $ff02
-00f793 2c73 .db "s",$2c
-00f794 f768 .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
- XT_SCOMMA:
-00f795 f000 .dw DO_COLON
- PFA_SCOMMA:
-00f796 f0c2 .dw XT_DUP
-00f797 f799 .dw XT_DOSCOMMA
-00f798 f025 .dw XT_EXIT
-
- ; ( addr len len' -- )
- ; Compiler
- ; compiles a string from RAM to Flash
- ;VE_DOSCOMMA:
- ; .dw $ff04
- ; .db "(s",$2c,")"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOSCOMMA
- XT_DOSCOMMA:
-00f799 f000 .dw DO_COLON
- PFA_DOSCOMMA:
-00f79a 018f .dw XT_COMMA
-00f79b f0c2 .dw XT_DUP ; ( --addr len len)
-00f79c f215 .dw XT_2SLASH ; ( -- addr len len/2
-00f79d f590 .dw XT_TUCK ; ( -- addr len/2 len len/2
-00f79e f21c .dw XT_2STAR ; ( -- addr len/2 len len'
-00f79f f1a4 .dw XT_MINUS ; ( -- addr len/2 rem
-00f7a0 f110 .dw XT_TO_R
-00f7a1 f165 .dw XT_ZERO
-00f7a2 024e .dw XT_QDOCHECK
-00f7a3 f03e .dw XT_DOCONDBRANCH
-00f7a4 f7ac .dw PFA_SCOMMA2
-00f7a5 f2ac .dw XT_DODO
- PFA_SCOMMA1:
-00f7a6 f0c2 .dw XT_DUP ; ( -- addr addr )
-00f7a7 f08a .dw XT_FETCH ; ( -- addr c1c2 )
-00f7a8 018f .dw XT_COMMA ; ( -- addr )
-00f7a9 f578 .dw XT_CELLPLUS ; ( -- addr+cell )
-00f7aa f2da .dw XT_DOLOOP
-00f7ab f7a6 .dw PFA_SCOMMA1
- PFA_SCOMMA2:
-00f7ac f107 .dw XT_R_FROM
-00f7ad f139 .dw XT_GREATERZERO
-00f7ae f03e .dw XT_DOCONDBRANCH
-00f7af f7b3 .dw PFA_SCOMMA3
-00f7b0 f0c2 .dw XT_DUP ; well, tricky
-00f7b1 f0a9 .dw XT_CFETCH
-00f7b2 018f .dw XT_COMMA
- PFA_SCOMMA3:
-00f7b3 f0ea .dw XT_DROP ; ( -- )
-00f7b4 f025 .dw XT_EXIT
- .include "words/itype.asm"
-
- ; Tools
- ; reads string from flash and prints it
- VE_ITYPE:
-00f7b5 ff05 .dw $ff05
-00f7b6 7469
-00f7b7 7079
-00f7b8 0065 .db "itype",0
-00f7b9 f792 .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
- XT_ITYPE:
-00f7ba f000 .dw DO_COLON
- PFA_ITYPE:
-00f7bb f0c2 .dw XT_DUP ; ( --addr len len)
-00f7bc f215 .dw XT_2SLASH ; ( -- addr len len/2
-00f7bd f590 .dw XT_TUCK ; ( -- addr len/2 len len/2
-00f7be f21c .dw XT_2STAR ; ( -- addr len/2 len len'
-00f7bf f1a4 .dw XT_MINUS ; ( -- addr len/2 rem
-00f7c0 f110 .dw XT_TO_R
-00f7c1 f165 .dw XT_ZERO
-00f7c2 024e .dw XT_QDOCHECK
-00f7c3 f03e .dw XT_DOCONDBRANCH
-00f7c4 f7ce .dw PFA_ITYPE2
-00f7c5 f2ac .dw XT_DODO
- PFA_ITYPE1:
-00f7c6 f0c2 .dw XT_DUP ; ( -- addr addr )
-00f7c7 f3e2 .dw XT_FETCHI ; ( -- addr c1c2 )
-00f7c8 f0c2 .dw XT_DUP
-00f7c9 f7db .dw XT_LOWEMIT
-00f7ca f7d7 .dw XT_HIEMIT
-00f7cb f240 .dw XT_1PLUS ; ( -- addr+cell )
-00f7cc f2da .dw XT_DOLOOP
-00f7cd f7c6 .dw PFA_ITYPE1
- PFA_ITYPE2:
-00f7ce f107 .dw XT_R_FROM
-00f7cf f139 .dw XT_GREATERZERO
-00f7d0 f03e .dw XT_DOCONDBRANCH
-00f7d1 f7d5 .dw PFA_ITYPE3
-00f7d2 f0c2 .dw XT_DUP ; make sure the drop below has always something to do
-00f7d3 f3e2 .dw XT_FETCHI
-00f7d4 f7db .dw XT_LOWEMIT
- PFA_ITYPE3:
-00f7d5 f0ea .dw XT_DROP
-00f7d6 f025 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_HIEMIT:
- ; .dw $ff06
- ; .db "hiemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_HIEMIT
- XT_HIEMIT:
-00f7d7 f000 .dw DO_COLON
- PFA_HIEMIT:
-00f7d8 f30a .dw XT_BYTESWAP
-00f7d9 f7db .dw XT_LOWEMIT
-00f7da f025 .dw XT_EXIT
-
- ; ( w -- )
- ; R( -- )
- ; content of cell fetched on stack.
- ;VE_LOWEMIT:
- ; .dw $ff07
- ; .db "lowemit"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_LOWEMIT
- XT_LOWEMIT:
-00f7db f000 .dw DO_COLON
- PFA_LOWEMIT:
-00f7dc f045 .dw XT_DOLITERAL
-00f7dd 00ff .dw $00ff
-00f7de f224 .dw XT_AND
-00f7df f5a8 .dw XT_EMIT
-00f7e0 f025 .dw XT_EXIT
- .include "words/icount.asm"
-
- ; Tools
- ; get count information out of a counted string in flash
- VE_ICOUNT:
-00f7e1 ff06 .dw $ff06
-00f7e2 6369
-00f7e3 756f
-00f7e4 746e .db "icount"
-00f7e5 f7b5 .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
- XT_ICOUNT:
-00f7e6 f000 .dw DO_COLON
- PFA_ICOUNT:
-00f7e7 f0c2 .dw XT_DUP
-00f7e8 f240 .dw XT_1PLUS
-00f7e9 f0d5 .dw XT_SWAP
-00f7ea f3e2 .dw XT_FETCHI
-00f7eb f025 .dw XT_EXIT
- .include "words/cr.asm"
-
- ; Character IO
- ; cause subsequent output appear at the beginning of the next line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CR:
-00f7ec ff02 .dw 0xff02
-00f7ed 7263 .db "cr"
-00f7ee f7e1 .dw VE_HEAD
- .set VE_HEAD = VE_CR
- XT_CR:
-00f7ef f000 .dw DO_COLON
- PFA_CR:
- .endif
-
-00f7f0 f045 .dw XT_DOLITERAL
-00f7f1 000d .dw 13
-00f7f2 f5a8 .dw XT_EMIT
-00f7f3 f045 .dw XT_DOLITERAL
-00f7f4 000a .dw 10
-00f7f5 f5a8 .dw XT_EMIT
-00f7f6 f025 .dw XT_EXIT
- .include "words/space.asm"
-
- ; Character IO
- ; emits a space (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACE:
-00f7f7 ff05 .dw $ff05
-00f7f8 7073
-00f7f9 6361
-00f7fa 0065 .db "space",0
-00f7fb f7ec .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
- XT_SPACE:
-00f7fc f000 .dw DO_COLON
- PFA_SPACE:
- .endif
-00f7fd f60a .dw XT_BL
-00f7fe f5a8 .dw XT_EMIT
-00f7ff f025 .dw XT_EXIT
- .include "words/spaces.asm"
-
- ; Character IO
- ; emits n space(s) (bl)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SPACES:
-00f800 ff06 .dw $ff06
-00f801 7073
-00f802 6361
-00f803 7365 .db "spaces"
-00f804 f7f7 .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
- XT_SPACES:
-00f805 f000 .dw DO_COLON
- PFA_SPACES:
-
- .endif
- ;C SPACES n -- output n spaces
- ; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
-00f806 f165
-00f807 f684 .DW XT_ZERO, XT_MAX
-00f808 f0c2
-00f809 f03e SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
-00f80a f80f DEST(SPCS2)
-00f80b f7fc
-00f80c f246
-00f80d f034 .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
-00f80e f808 DEST(SPCS1)
-00f80f f0ea
-00f810 f025 SPCS2: .DW XT_DROP,XT_EXIT
- .include "words/type.asm"
-
- ; Character IO
- ; print a RAM based string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TYPE:
-00f811 ff04 .dw $ff04
-00f812 7974
-00f813 6570 .db "type"
-00f814 f800 .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
- XT_TYPE:
-00f815 f000 .dw DO_COLON
- PFA_TYPE:
-
- .endif
-00f816 fd89 .dw XT_BOUNDS
-00f817 024e .dw XT_QDOCHECK
-00f818 f03e .dw XT_DOCONDBRANCH
-00f819 f820 DEST(PFA_TYPE2)
-00f81a f2ac .dw XT_DODO
- PFA_TYPE1:
-00f81b f2bd .dw XT_I
-00f81c f0a9 .dw XT_CFETCH
-00f81d f5a8 .dw XT_EMIT
-00f81e f2da .dw XT_DOLOOP
-00f81f f81b DEST(PFA_TYPE1)
- PFA_TYPE2:
-00f820 f025 .dw XT_EXIT
- .include "words/tick.asm"
-
- ; Dictionary
- ; search dictionary for name, return XT or throw an exception -13
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TICK:
-00f821 ff01 .dw $ff01
-00f822 0027 .db "'",0
-00f823 f811 .dw VE_HEAD
- .set VE_HEAD = VE_TICK
- XT_TICK:
-00f824 f000 .dw DO_COLON
- PFA_TICK:
- .endif
-00f825 f9ce .dw XT_PARSENAME
-00f826 fae6 .dw XT_FORTHRECOGNIZER
-00f827 faf1 .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
-00f828 f0c2 .dw XT_DUP
-00f829 fb64 .dw XT_DT_NULL
-00f82a fdaa .dw XT_EQUAL
-00f82b f0d5 .dw XT_SWAP
-00f82c f3e2 .dw XT_FETCHI
-00f82d f045 .dw XT_DOLITERAL
-00f82e fb99 .dw XT_NOOP
-00f82f fdaa .dw XT_EQUAL
-00f830 f22d .dw XT_OR
-00f831 f03e .dw XT_DOCONDBRANCH
-00f832 f836 DEST(PFA_TICK1)
-00f833 f045 .dw XT_DOLITERAL
-00f834 fff3 .dw -13
-00f835 f85b .dw XT_THROW
- PFA_TICK1:
-00f836 f0ea .dw XT_DROP
-00f837 f025 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/handler.asm"
-
- ; Exceptions
- ; USER variable used by catch/throw
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_HANDLER:
-00f838 ff07 .dw $ff07
-00f839 6168
-00f83a 646e
-00f83b 656c
-00f83c 0072 .db "handler",0
-00f83d f821 .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
- XT_HANDLER:
-00f83e f066 .dw PFA_DOUSER
- PFA_HANDLER:
- .endif
-00f83f 000a .dw USER_HANDLER
- .include "words/catch.asm"
-
- ; Exceptions
- ; execute XT and check for exceptions.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CATCH:
-00f840 ff05 .dw $ff05
-00f841 6163
-00f842 6374
-00f843 0068 .db "catch",0
-00f844 f838 .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
- XT_CATCH:
-00f845 f000 .dw DO_COLON
- PFA_CATCH:
- .endif
-
- ; sp@ >r
-00f846 f29e .dw XT_SP_FETCH
-00f847 f110 .dw XT_TO_R
- ; handler @ >r
-00f848 f83e .dw XT_HANDLER
-00f849 f08a .dw XT_FETCH
-00f84a f110 .dw XT_TO_R
- ; rp@ handler !
-00f84b f287 .dw XT_RP_FETCH
-00f84c f83e .dw XT_HANDLER
-00f84d f092 .dw XT_STORE
-00f84e f02f .dw XT_EXECUTE
- ; r> handler !
-00f84f f107 .dw XT_R_FROM
-00f850 f83e .dw XT_HANDLER
-00f851 f092 .dw XT_STORE
-00f852 f107 .dw XT_R_FROM
-00f853 f0ea .dw XT_DROP
-00f854 f165 .dw XT_ZERO
-00f855 f025 .dw XT_EXIT
- .include "words/throw.asm"
-
- ; Exceptions
- ; throw an exception
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_THROW:
-00f856 ff05 .dw $ff05
-00f857 6874
-00f858 6f72
-00f859 0077 .db "throw",0
-00f85a f840 .dw VE_HEAD
- .set VE_HEAD = VE_THROW
- XT_THROW:
-00f85b f000 .dw DO_COLON
- PFA_THROW:
- .endif
-00f85c f0c2 .dw XT_DUP
-00f85d f12b .dw XT_ZEROEQUAL
-00f85e f03e .dw XT_DOCONDBRANCH
-00f85f f862 DEST(PFA_THROW1)
-00f860 f0ea .dw XT_DROP
-00f861 f025 .dw XT_EXIT
- PFA_THROW1:
-00f862 f83e .dw XT_HANDLER
-00f863 f08a .dw XT_FETCH
-00f864 f291 .dw XT_RP_STORE
-00f865 f107 .dw XT_R_FROM
-00f866 f83e .dw XT_HANDLER
-00f867 f092 .dw XT_STORE
-00f868 f107 .dw XT_R_FROM
-00f869 f0d5 .dw XT_SWAP
-00f86a f110 .dw XT_TO_R
-00f86b f2a7 .dw XT_SP_STORE
-00f86c f0ea .dw XT_DROP
-00f86d f107 .dw XT_R_FROM
-00f86e f025 .dw XT_EXIT
-
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/cskip.asm"
-
- ; String
- ; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSKIP:
-00f86f ff05 .dw $ff05
-00f870 7363
-00f871 696b
-00f872 0070 .db "cskip",0
-00f873 f856 .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
- XT_CSKIP:
-00f874 f000 .dw DO_COLON
- PFA_CSKIP:
- .endif
-00f875 f110 .dw XT_TO_R ; ( -- addr1 n1 )
- PFA_CSKIP1:
-00f876 f0c2 .dw XT_DUP ; ( -- addr' n' n' )
-00f877 f03e .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00f878 f883 DEST(PFA_CSKIP2)
-00f879 f0e0 .dw XT_OVER ; ( -- addr' n' addr' )
-00f87a f0a9 .dw XT_CFETCH ; ( -- addr' n' c' )
-00f87b f119 .dw XT_R_FETCH ; ( -- addr' n' c' c )
-00f87c fdaa .dw XT_EQUAL ; ( -- addr' n' f )
-00f87d f03e .dw XT_DOCONDBRANCH ; ( -- addr' n')
-00f87e f883 DEST(PFA_CSKIP2)
-00f87f fdb1 .dw XT_ONE
-00f880 f9bf .dw XT_SLASHSTRING
-00f881 f034 .dw XT_DOBRANCH
-00f882 f876 DEST(PFA_CSKIP1)
- PFA_CSKIP2:
-00f883 f107 .dw XT_R_FROM
-00f884 f0ea .dw XT_DROP ; ( -- addr2 n2)
-00f885 f025 .dw XT_EXIT
- .include "words/cscan.asm"
-
- ; String
- ; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CSCAN:
-00f886 ff05 .dw $ff05
-00f887 7363
-00f888 6163
-../../common\words/cscan.asm(12): warning: .cseg .db misalignment - padding zero byte
-00f889 006e .db "cscan"
-00f88a f86f .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
- XT_CSCAN:
-00f88b f000 .dw DO_COLON
- PFA_CSCAN:
- .endif
-00f88c f110 .dw XT_TO_R
-00f88d f0e0 .dw XT_OVER
- PFA_CSCAN1:
-00f88e f0c2 .dw XT_DUP
-00f88f f0a9 .dw XT_CFETCH
-00f890 f119 .dw XT_R_FETCH
-00f891 fdaa .dw XT_EQUAL
-00f892 f12b .dw XT_ZEROEQUAL
-00f893 f03e .dw XT_DOCONDBRANCH
-00f894 f8a0 DEST(PFA_CSCAN2)
-00f895 f0d5 .dw XT_SWAP
-00f896 f246 .dw XT_1MINUS
-00f897 f0d5 .dw XT_SWAP
-00f898 f0e0 .dw XT_OVER
-00f899 f132 .dw XT_ZEROLESS ; not negative
-00f89a f12b .dw XT_ZEROEQUAL
-00f89b f03e .dw XT_DOCONDBRANCH
-00f89c f8a0 DEST(PFA_CSCAN2)
-00f89d f240 .dw XT_1PLUS
-00f89e f034 .dw XT_DOBRANCH
-00f89f f88e DEST(PFA_CSCAN1)
- PFA_CSCAN2:
-00f8a0 f101 .dw XT_NIP
-00f8a1 f0e0 .dw XT_OVER
-00f8a2 f1a4 .dw XT_MINUS
-00f8a3 f107 .dw XT_R_FROM
-00f8a4 f0ea .dw XT_DROP
-00f8a5 f025 .dw XT_EXIT
-
- ; : my-cscan ( addr len c -- addr len' )
- ; >r over ( -- addr len addr )
- ; begin
- ; dup c@ r@ <> while
- ; swap 1- swap over 0 >= while
- ; 1+
- ; repeat then
- ; nip over - r> drop
- ; ;
- .include "words/accept.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ACCEPT:
-00f8a6 ff06 .dw $ff06
-00f8a7 6361
-00f8a8 6563
-00f8a9 7470 .db "accept"
-00f8aa f886 .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
- XT_ACCEPT:
-00f8ab f000 .dw DO_COLON
- PFA_ACCEPT:
-
- .endif
-00f8ac f0e0
-00f8ad f1ae
-00f8ae f246
-00f8af f0e0 .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-00f8b0 f5b9
-00f8b1 f0c2
-00f8b2 f8ec
-00f8b3 f12b
-00f8b4 f03e ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
-00f8b5 f8de DEST(ACC5)
-00f8b6 f0c2
-00f8b7 f045
-00f8b8 0008
-00f8b9 fdaa
-00f8ba f03e .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
-00f8bb f8ce DEST(ACC3)
-00f8bc f0ea
-00f8bd f0f2
-00f8be f57f
-00f8bf f189
-00f8c0 f110
-00f8c1 f0f2
-00f8c2 f0f2
-00f8c3 f107
-00f8c4 f03e .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
-00f8c5 f8cc DEST(ACC6)
-00f8c6 f8e4
-00f8c7 f246
-00f8c8 f110
-00f8c9 f0e0
-00f8ca f107
-00f8cb 0121 .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-00f8cc f034 ACC6: .DW XT_DOBRANCH
-00f8cd f8dc DEST(ACC4)
-
-
- ACC3: ; check for remaining control characters, replace them with blank
-00f8ce f0c2 .dw XT_DUP ; ( -- addr k k )
-00f8cf f60a .dw XT_BL
-00f8d0 f17f .dw XT_LESS
-00f8d1 f03e .dw XT_DOCONDBRANCH
-00f8d2 f8d5 DEST(PFA_ACCEPT6)
-00f8d3 f0ea .dw XT_DROP
-00f8d4 f60a .dw XT_BL
- PFA_ACCEPT6:
-00f8d5 f0c2
-00f8d6 f5a8
-00f8d7 f0e0
-00f8d8 f09e
-00f8d9 f240
-00f8da f0e0
-00f8db 012d .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-00f8dc f034 ACC4: .DW XT_DOBRANCH
-00f8dd f8b0 DEST(ACC1)
-00f8de f0ea
-00f8df f101
-00f8e0 f0d5
-00f8e1 f1a4
-00f8e2 f7ef
-00f8e3 f025 ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
- ; ( -- )
- ; System
- ; send a backspace character to overwrite the current char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- ;VE_BS:
- ; .dw $ff02
- ; .db "bs"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_BS
- XT_BS:
-00f8e4 f000 .dw DO_COLON
- .endif
-00f8e5 f045 .dw XT_DOLITERAL
-00f8e6 0008 .dw 8
-00f8e7 f0c2 .dw XT_DUP
-00f8e8 f5a8 .dw XT_EMIT
-00f8e9 f7fc .dw XT_SPACE
-00f8ea f5a8 .dw XT_EMIT
-00f8eb f025 .dw XT_EXIT
-
-
- ; ( c -- f )
- ; System
- ; is the character a line end character?
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_CRLFQ:
- ; .dw $ff02
- ; .db "crlf?"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_CRLFQ
- XT_CRLFQ:
-00f8ec f000 .dw DO_COLON
- .endif
-00f8ed f0c2 .dw XT_DUP
-00f8ee f045 .dw XT_DOLITERAL
-00f8ef 000d .dw 13
-00f8f0 fdaa .dw XT_EQUAL
-00f8f1 f0d5 .dw XT_SWAP
-00f8f2 f045 .dw XT_DOLITERAL
-00f8f3 000a .dw 10
-00f8f4 fdaa .dw XT_EQUAL
-00f8f5 f22d .dw XT_OR
-00f8f6 f025 .dw XT_EXIT
- .include "words/refill.asm"
-
- ; System
- ; refills the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILL:
-00f8f7 ff06 .dw $ff06
-00f8f8 6572
-00f8f9 6966
-00f8fa 6c6c .db "refill"
-00f8fb f8a6 .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
- XT_REFILL:
-00f8fc fc2d .dw PFA_DODEFER1
- PFA_REFILL:
- .endif
-00f8fd 001a .dw USER_REFILL
-00f8fe fbf6 .dw XT_UDEFERFETCH
-00f8ff fc02 .dw XT_UDEFERSTORE
- .include "words/char.asm"
-
- ; Tools
- ; copy the first character of the next word onto the stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_CHAR:
-00f900 ff04 .dw $ff04
-00f901 6863
-00f902 7261 .db "char"
-00f903 f8f7 .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
- XT_CHAR:
-00f904 f000 .dw DO_COLON
- PFA_CHAR:
- .endif
-00f905 f9ce .dw XT_PARSENAME
-00f906 f0ea .dw XT_DROP
-00f907 f0a9 .dw XT_CFETCH
-00f908 f025 .dw XT_EXIT
- .include "words/number.asm"
-
- ; Numeric IO
- ; convert a string at addr to a number
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBER:
-00f909 ff06 .dw $ff06
-00f90a 756e
-00f90b 626d
-00f90c 7265 .db "number"
-00f90d f900 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
- XT_NUMBER:
-00f90e f000 .dw DO_COLON
- PFA_NUMBER:
- .endif
-00f90f f56b .dw XT_BASE
-00f910 f08a .dw XT_FETCH
-00f911 f110 .dw XT_TO_R
-00f912 f952 .dw XT_QSIGN
-00f913 f110 .dw XT_TO_R
-00f914 f965 .dw XT_SET_BASE
-00f915 f952 .dw XT_QSIGN
-00f916 f107 .dw XT_R_FROM
-00f917 f22d .dw XT_OR
-00f918 f110 .dw XT_TO_R
- ; check whether something is left
-00f919 f0c2 .dw XT_DUP
-00f91a f12b .dw XT_ZEROEQUAL
-00f91b f03e .dw XT_DOCONDBRANCH
-00f91c f925 DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
-00f91d f588 .dw XT_2DROP
-00f91e f107 .dw XT_R_FROM
-00f91f f0ea .dw XT_DROP
-00f920 f107 .dw XT_R_FROM
-00f921 f56b .dw XT_BASE
-00f922 f092 .dw XT_STORE
-00f923 f165 .dw XT_ZERO
-00f924 f025 .dw XT_EXIT
- PFA_NUMBER0:
-00f925 f32f .dw XT_2TO_R
-00f926 f165 .dw XT_ZERO ; starting value
-00f927 f165 .dw XT_ZERO
-00f928 f33e .dw XT_2R_FROM
-00f929 f983 .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
-00f92a f0ca .dw XT_QDUP
-00f92b f03e .dw XT_DOCONDBRANCH
-00f92c f947 DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
-00f92d fdb1 .dw XT_ONE
-00f92e fdaa .dw XT_EQUAL
-00f92f f03e .dw XT_DOCONDBRANCH
-00f930 f93e DEST(PFA_NUMBER2)
- ; excatly one character is left
-00f931 f0a9 .dw XT_CFETCH
-00f932 f045 .dw XT_DOLITERAL
-00f933 002e .dw 46 ; .
-00f934 fdaa .dw XT_EQUAL
-00f935 f03e .dw XT_DOCONDBRANCH
-00f936 f93f DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
-00f937 f107 .dw XT_R_FROM
-00f938 f03e .dw XT_DOCONDBRANCH
-00f939 f93b DEST(PFA_NUMBER3)
-00f93a fd0c .dw XT_DNEGATE
- PFA_NUMBER3:
-00f93b fdb6 .dw XT_TWO
-00f93c f034 .dw XT_DOBRANCH
-00f93d f94d DEST(PFA_NUMBER5)
- PFA_NUMBER2:
-00f93e f0ea .dw XT_DROP
- PFA_NUMBER6:
-00f93f f588 .dw XT_2DROP
-00f940 f107 .dw XT_R_FROM
-00f941 f0ea .dw XT_DROP
-00f942 f107 .dw XT_R_FROM
-00f943 f56b .dw XT_BASE
-00f944 f092 .dw XT_STORE
-00f945 f165 .dw XT_ZERO
-00f946 f025 .dw XT_EXIT
- PFA_NUMBER1:
-00f947 f588 .dw XT_2DROP ; remove the address
- ; incorporate sign into number
-00f948 f107 .dw XT_R_FROM
-00f949 f03e .dw XT_DOCONDBRANCH
-00f94a f94c DEST(PFA_NUMBER4)
-00f94b f659 .dw XT_NEGATE
- PFA_NUMBER4:
-00f94c fdb1 .dw XT_ONE
- PFA_NUMBER5:
-00f94d f107 .dw XT_R_FROM
-00f94e f56b .dw XT_BASE
-00f94f f092 .dw XT_STORE
-00f950 f15c .dw XT_TRUE
-00f951 f025 .dw XT_EXIT
- .include "words/q-sign.asm"
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_QSIGN:
-00f952 f000 .dw DO_COLON
- PFA_QSIGN: ; ( c -- )
- .endif
-00f953 f0e0 .dw XT_OVER ; ( -- addr len addr )
-00f954 f0a9 .dw XT_CFETCH
-00f955 f045 .dw XT_DOLITERAL
-00f956 002d .dw '-'
-00f957 fdaa .dw XT_EQUAL ; ( -- addr len flag )
-00f958 f0c2 .dw XT_DUP
-00f959 f110 .dw XT_TO_R
-00f95a f03e .dw XT_DOCONDBRANCH
-00f95b f95e DEST(PFA_NUMBERSIGN_DONE)
-00f95c fdb1 .dw XT_ONE ; skip sign character
-00f95d f9bf .dw XT_SLASHSTRING
- PFA_NUMBERSIGN_DONE:
-00f95e f107 .dw XT_R_FROM
-00f95f f025 .dw XT_EXIT
- .include "words/set-base.asm"
-
- ; Numeric IO
- ; skip a numeric prefix character
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_BASES:
-00f960 f060 .dw PFA_DOCONSTANT
- .endif
-00f961 000a
-00f962 0010
-00f963 0002
-00f964 000a .dw 10,16,2,10 ; last one could a 8 instead.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_SET_BASE:
-00f965 f000 .dw DO_COLON
- PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
- .endif
-00f966 f0e0 .dw XT_OVER
-00f967 f0a9 .dw XT_CFETCH
-00f968 f045 .dw XT_DOLITERAL
-00f969 0023 .dw 35
-00f96a f1a4 .dw XT_MINUS
-00f96b f0c2 .dw XT_DUP
-00f96c f165 .dw XT_ZERO
-00f96d f045 .dw XT_DOLITERAL
-00f96e 0004 .dw 4
-00f96f f691 .dw XT_WITHIN
-00f970 f03e .dw XT_DOCONDBRANCH
-00f971 f97b DEST(SET_BASE1)
- .if cpu_msp430==1
- .endif
-00f972 f960 .dw XT_BASES
-00f973 f1ae .dw XT_PLUS
-00f974 f3e2 .dw XT_FETCHI
-00f975 f56b .dw XT_BASE
-00f976 f092 .dw XT_STORE
-00f977 fdb1 .dw XT_ONE
-00f978 f9bf .dw XT_SLASHSTRING
-00f979 f034 .dw XT_DOBRANCH
-00f97a f97c DEST(SET_BASE2)
- SET_BASE1:
-00f97b f0ea .dw XT_DROP
- SET_BASE2:
-00f97c f025 .dw XT_EXIT
-
- ; create bases 10 , 16 , 2 , 8 ,
- ; : set-base 35 - dup 0 4 within if
- ; bases + @i base ! 1 /string
- ; else
- ; drop
- ; then ;
- .include "words/to-number.asm"
-
- ; Numeric IO
- ; convert a string to a number c-addr2/u2 is the unconverted string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO_NUMBER:
-00f97d ff07 .dw $ff07
-00f97e 6e3e
-00f97f 6d75
-00f980 6562
-00f981 0072 .db ">number",0
-00f982 f909 .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
- XT_TO_NUMBER:
-00f983 f000 .dw DO_COLON
-
- .endif
-
-00f984 f0c2
-00f985 f03e TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
-00f986 f99b DEST(TONUM3)
-00f987 f0e0
-00f988 f0a9
-00f989 f76d .DW XT_OVER,XT_CFETCH,XT_DIGITQ
-00f98a f12b
-00f98b f03e .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
-00f98c f98f DEST(TONUM2)
-00f98d f0ea
-00f98e f025 .DW XT_DROP,XT_EXIT
-00f98f f110
-00f990 fd30
-00f991 f56b
-00f992 f08a
-00f993 0112 TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
-00f994 f107
-00f995 010a
-00f996 fd30 .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
-00f997 fdb1
-00f998 f9bf
-00f999 f034 .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
-00f99a f984 DEST(TONUM1)
-00f99b f025 TONUM3: .DW XT_EXIT
-
- ;C >NUMBER ud adr u -- ud' adr' u'
- ;C convert string to number
- ; BEGIN
- ; DUP WHILE
- ; OVER C@ DIGIT?
- ; 0= IF DROP EXIT THEN
- ; >R 2SWAP BASE @ UD*
- ; R> M+ 2SWAP
- ; 1 /STRING
- ; REPEAT ;
- .include "words/parse.asm"
-
- ; String
- ; in input buffer parse ccc delimited string by the delimiter char.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PARSE:
-00f99c ff05 .dw $ff05
-00f99d 6170
-00f99e 7372
-00f99f 0065 .db "parse",0
-00f9a0 f97d .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
- XT_PARSE:
-00f9a1 f000 .dw DO_COLON
- PFA_PARSE:
- .endif
-00f9a2 f110 .dw XT_TO_R ; ( -- )
-00f9a3 f9b5 .dw XT_SOURCE ; ( -- addr len)
-00f9a4 f598 .dw XT_TO_IN ; ( -- addr len >in)
-00f9a5 f08a .dw XT_FETCH
-00f9a6 f9bf .dw XT_SLASHSTRING ; ( -- addr' len' )
-
-00f9a7 f107 .dw XT_R_FROM ; ( -- addr' len' c)
-00f9a8 f88b .dw XT_CSCAN ; ( -- addr' len'')
-00f9a9 f0c2 .dw XT_DUP ; ( -- addr' len'' len'')
-00f9aa f240 .dw XT_1PLUS
-00f9ab f598 .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
-00f9ac f276 .dw XT_PLUSSTORE ; ( -- addr' len')
-00f9ad fdb1 .dw XT_ONE
-00f9ae f9bf .dw XT_SLASHSTRING
-00f9af f025 .dw XT_EXIT
- .include "words/source.asm"
-
- ; System
- ; address and current length of the input buffer
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCE:
-00f9b0 ff06 .dw $FF06
-00f9b1 6f73
-00f9b2 7275
-00f9b3 6563 .db "source"
-00f9b4 f99c .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
- XT_SOURCE:
-00f9b5 fc2d .dw PFA_DODEFER1
- PFA_SOURCE:
- .endif
-00f9b6 0016 .dw USER_SOURCE
-00f9b7 fbf6 .dw XT_UDEFERFETCH
-00f9b8 fc02 .dw XT_UDEFERSTORE
-
-
- .include "words/slash-string.asm"
-
- ; String
- ; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SLASHSTRING:
-00f9b9 ff07 .dw $ff07
-00f9ba 732f
-00f9bb 7274
-00f9bc 6e69
-00f9bd 0067 .db "/string",0
-00f9be f9b0 .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
- XT_SLASHSTRING:
-00f9bf f000 .dw DO_COLON
- PFA_SLASHSTRING:
- .endif
-00f9c0 f0f2 .dw XT_ROT
-00f9c1 f0e0 .dw XT_OVER
-00f9c2 f1ae .dw XT_PLUS
-00f9c3 f0f2 .dw XT_ROT
-00f9c4 f0f2 .dw XT_ROT
-00f9c5 f1a4 .dw XT_MINUS
-00f9c6 f025 .dw XT_EXIT
-
- .include "words/parse-name.asm"
-
- ; String
- ; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_PARSENAME:
-00f9c7 ff0a .dw $FF0A
-00f9c8 6170
-00f9c9 7372
-00f9ca 2d65
-00f9cb 616e
-00f9cc 656d .db "parse-name"
-00f9cd f9b9 .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
- XT_PARSENAME:
-00f9ce f000 .dw DO_COLON
- PFA_PARSENAME:
- .endif
-00f9cf f60a .dw XT_BL
-00f9d0 f9d2 .dw XT_SKIPSCANCHAR
-00f9d1 f025 .dw XT_EXIT
-
- ; ( c -- addr2 len2 )
- ; String
- ; skips char and scan what's left in source for char
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_SKIPSCANCHAR:
- ; .dw $FF0A
- ; .db "skipscanchar"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_SKIPSCANCHAR
- XT_SKIPSCANCHAR:
-00f9d2 f000 .dw DO_COLON
- PFA_SKIPSCANCHAR:
- .endif
-00f9d3 f110 .dw XT_TO_R
-00f9d4 f9b5 .dw XT_SOURCE
-00f9d5 f598 .dw XT_TO_IN
-00f9d6 f08a .dw XT_FETCH
-00f9d7 f9bf .dw XT_SLASHSTRING
-
-00f9d8 f119 .dw XT_R_FETCH
-00f9d9 f874 .dw XT_CSKIP
-00f9da f107 .dw XT_R_FROM
-00f9db f88b .dw XT_CSCAN
-
- ; adjust >IN
-00f9dc f57f .dw XT_2DUP
-00f9dd f1ae .dw XT_PLUS
-00f9de f9b5 .dw XT_SOURCE
-00f9df f0ea .dw XT_DROP
-00f9e0 f1a4 .dw XT_MINUS
-00f9e1 f598 .dw XT_TO_IN
-00f9e2 f092 .dw XT_STORE
-00f9e3 f025 .dw XT_EXIT
- .include "words/find-xt.asm"
-
- ; Tools
- ; search wordlists for an entry with the xt from c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_FINDXT:
-00f9e4 ff07 .dw $ff07
-00f9e5 6966
-00f9e6 646e
-00f9e7 782d
-00f9e8 0074 .db "find-xt",0
-00f9e9 f9c7 .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
- XT_FINDXT:
-00f9ea f000 .dw DO_COLON
- PFA_FINDXT:
- .endif
-00f9eb f045 .dw XT_DOLITERAL
-00f9ec f9f6 .dw XT_FINDXTA
-00f9ed f045 .dw XT_DOLITERAL
-00f9ee 005c .dw CFG_ORDERLISTLEN
-00f9ef 03cf .dw XT_MAPSTACK
-00f9f0 f12b .dw XT_ZEROEQUAL
-00f9f1 f03e .dw XT_DOCONDBRANCH
-00f9f2 f9f5 DEST(PFA_FINDXT1)
-00f9f3 f588 .dw XT_2DROP
-00f9f4 f165 .dw XT_ZERO
- PFA_FINDXT1:
-00f9f5 f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_FINDXTA:
-00f9f6 f000 .dw DO_COLON
- PFA_FINDXTA:
- .endif
-00f9f7 f110 .dw XT_TO_R
-00f9f8 f57f .dw XT_2DUP
-00f9f9 f107 .dw XT_R_FROM
-00f9fa fc3f .dw XT_SEARCH_WORDLIST
-00f9fb f0c2 .dw XT_DUP
-00f9fc f03e .dw XT_DOCONDBRANCH
-00f9fd fa03 DEST(PFA_FINDXTA1)
-00f9fe f110 .dw XT_TO_R
-00f9ff f101 .dw XT_NIP
-00fa00 f101 .dw XT_NIP
-00fa01 f107 .dw XT_R_FROM
-00fa02 f15c .dw XT_TRUE
- PFA_FINDXTA1:
-00fa03 f025 .dw XT_EXIT
-
- .include "words/prompt-ok.asm"
-
- ; System
- ; send the READY prompt to the command line
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTOK:
- ; .dw $ff02
- ; .db "ok"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTOK
- XT_DEFAULT_PROMPTOK:
-00fa04 f000 .dw DO_COLON
- PFA_DEFAULT_PROMPTOK:
-00fa05 f787 .dw XT_DOSLITERAL
-00fa06 0003 .dw 3
-00fa07 6f20
-00fa08 006b .db " ok",0
- .endif
-00fa09 f7ba .dw XT_ITYPE
-00fa0a f025 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTOK:
-00fa0b ff03 .dw $FF03
-00fa0c 6f2e
-../../common\words/prompt-ok.asm(43): warning: .cseg .db misalignment - padding zero byte
-00fa0d 006b .db ".ok"
-00fa0e f9e4 .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
- XT_PROMPTOK:
-00fa0f fc2d .dw PFA_DODEFER1
- PFA_PROMPTOK:
- .endif
-00fa10 001c .dw USER_P_OK
-00fa11 fbf6 .dw XT_UDEFERFETCH
-00fa12 fc02 .dw XT_UDEFERSTORE
- .include "words/prompt-ready.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTRDY:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTRDY
- XT_DEFAULT_PROMPTREADY:
-00fa13 f000 .dw DO_COLON
- PFA_DEFAULT_PROMPTREADY:
-00fa14 f787 .dw XT_DOSLITERAL
-00fa15 0002 .dw 2
-00fa16 203e .db "> "
- .endif
-00fa17 f7ef .dw XT_CR
-00fa18 f7ba .dw XT_ITYPE
-00fa19 f025 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTREADY:
-00fa1a ff06 .dw $FF06
-00fa1b 722e
-00fa1c 6165
-00fa1d 7964 .db ".ready"
-00fa1e fa0b .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
- XT_PROMPTREADY:
-00fa1f fc2d .dw PFA_DODEFER1
- PFA_PROMPTREADY:
- .endif
-00fa20 0020 .dw USER_P_RDY
-00fa21 fbf6 .dw XT_UDEFERFETCH
-00fa22 fc02 .dw XT_UDEFERSTORE
- .include "words/prompt-error.asm"
-
- ; System
- ; process the error prompt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ;VE_PROMPTERROR:
- ; .dw $ff04
- ; .db "p_er"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_PROMPTERROR
- XT_DEFAULT_PROMPTERROR:
-00fa23 f000 .dw DO_COLON
- PFA_DEFAULT_PROMPTERROR:
-00fa24 f787 .dw XT_DOSLITERAL
-00fa25 0004 .dw 4
-00fa26 3f20
-00fa27 203f .db " ?? "
- .endif
-00fa28 f7ba .dw XT_ITYPE
-00fa29 f56b .dw XT_BASE
-00fa2a f08a .dw XT_FETCH
-00fa2b f110 .dw XT_TO_R
-00fa2c f5f7 .dw XT_DECIMAL
-00fa2d f73c .dw XT_DOT
-00fa2e f598 .dw XT_TO_IN
-00fa2f f08a .dw XT_FETCH
-00fa30 f73c .dw XT_DOT
-00fa31 f107 .dw XT_R_FROM
-00fa32 f56b .dw XT_BASE
-00fa33 f092 .dw XT_STORE
-00fa34 f025 .dw XT_EXIT
-
- ; ------------------------
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_PROMPTERROR:
-00fa35 ff06 .dw $FF06
-00fa36 652e
-00fa37 7272
-00fa38 726f .db ".error"
-00fa39 fa1a .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
- XT_PROMPTERROR:
-00fa3a fc2d .dw PFA_DODEFER1
- PFA_PROMPTERROR:
- .endif
-00fa3b 001e .dw USER_P_ERR
-00fa3c fbf6 .dw XT_UDEFERFETCH
-00fa3d fc02 .dw XT_UDEFERSTORE
-
- .include "words/quit.asm"
-
- ; System
- ; main loop of amforth. accept - interpret in an endless loop
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QUIT:
-00fa3e ff04 .dw $ff04
-00fa3f 7571
-00fa40 7469 .db "quit"
-00fa41 fa35 .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
- XT_QUIT:
-00fa42 f000 .dw DO_COLON
- .endif
- PFA_QUIT:
-00fa43 0284
-00fa44 028b
-00fa45 f092 .dw XT_LP0,XT_LP,XT_STORE
-00fa46 faa3 .dw XT_SP0
-00fa47 f2a7 .dw XT_SP_STORE
-00fa48 fab0 .dw XT_RP0
-00fa49 f291 .dw XT_RP_STORE
-00fa4a 0319 .dw XT_LBRACKET
-
- PFA_QUIT2:
-00fa4b f565 .dw XT_STATE
-00fa4c f08a .dw XT_FETCH
-00fa4d f12b .dw XT_ZEROEQUAL
-00fa4e f03e .dw XT_DOCONDBRANCH
-00fa4f fa51 DEST(PFA_QUIT4)
-00fa50 fa1f .dw XT_PROMPTREADY
- PFA_QUIT4:
-00fa51 f8fc .dw XT_REFILL
-00fa52 f03e .dw XT_DOCONDBRANCH
-00fa53 fa63 DEST(PFA_QUIT3)
-00fa54 f045 .dw XT_DOLITERAL
-00fa55 fac9 .dw XT_INTERPRET
-00fa56 f845 .dw XT_CATCH
-00fa57 f0ca .dw XT_QDUP
-00fa58 f03e .dw XT_DOCONDBRANCH
-00fa59 fa63 DEST(PFA_QUIT3)
-00fa5a f0c2 .dw XT_DUP
-00fa5b f045 .dw XT_DOLITERAL
-00fa5c fffe .dw -2
-00fa5d f17f .dw XT_LESS
-00fa5e f03e .dw XT_DOCONDBRANCH
-00fa5f fa61 DEST(PFA_QUIT5)
-00fa60 fa3a .dw XT_PROMPTERROR
- PFA_QUIT5:
-00fa61 f034 .dw XT_DOBRANCH
-00fa62 fa43 DEST(PFA_QUIT)
- PFA_QUIT3:
-00fa63 fa0f .dw XT_PROMPTOK
-00fa64 f034 .dw XT_DOBRANCH
-00fa65 fa4b DEST(PFA_QUIT2)
- ; .dw XT_EXIT ; never reached
-
- .include "words/pause.asm"
-
- ; Multitasking
- ; Fetch pause vector and execute it. may make a context/task switch
- VE_PAUSE:
-00fa66 ff05 .dw $ff05
-00fa67 6170
-00fa68 7375
-00fa69 0065 .db "pause",0
-00fa6a fa3e .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
- XT_PAUSE:
-00fa6b fc2d .dw PFA_DODEFER1
- PFA_PAUSE:
-00fa6c 0141 .dw ram_pause
-00fa6d fbe2 .dw XT_RDEFERFETCH
-00fa6e fbec .dw XT_RDEFERSTORE
-
- .dseg
-000141 ram_pause: .byte 2
- .cseg
- .include "words/cold.asm"
-
- ; System
- ; start up amforth.
- VE_COLD:
-00fa6f ff04 .dw $ff04
-00fa70 6f63
-00fa71 646c .db "cold"
-00fa72 fa66 .dw VE_HEAD
- .set VE_HEAD = VE_COLD
- XT_COLD:
-00fa73 fa74 .dw PFA_COLD
- PFA_COLD:
-00fa74 b6a4 in_ mcu_boot, MCUSR
-00fa75 2422 clr zerol
-00fa76 2433 clr zeroh
-00fa77 24bb clr isrflag
-00fa78 be24 out_ MCUSR, zerol
- ; clear RAM
-00fa79 e0e0 ldi zl, low(ramstart)
-00fa7a e0f1 ldi zh, high(ramstart)
- clearloop:
-00fa7b 9221 st Z+, zerol
-00fa7c 30e0 cpi zl, low(sram_size+ramstart)
-00fa7d f7e9 brne clearloop
-00fa7e 34f1 cpi zh, high(sram_size+ramstart)
-00fa7f f7d9 brne clearloop
- ; init first user data area
- ; allocate space for User Area
- .dseg
-000143 ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
- .cseg
-00fa80 e4e3 ldi zl, low(ram_user1)
-00fa81 e0f1 ldi zh, high(ram_user1)
-00fa82 012f movw upl, zl
- ; init return stack pointer
-00fa83 ef0f ldi temp0,low(rstackstart)
-00fa84 bf0d out_ SPL,temp0
-00fa85 8304 std Z+4, temp0
-00fa86 e410 ldi temp1,high(rstackstart)
-00fa87 bf1e out_ SPH,temp1
-00fa88 8315 std Z+5, temp1
-
- ; init parameter stack pointer
-00fa89 eacf ldi yl,low(stackstart)
-00fa8a 83c6 std Z+6, yl
-00fa8b e4d0 ldi yh,high(stackstart)
-00fa8c 83d7 std Z+7, yh
-
- ; load Forth IP with starting word
-00fa8d e9a6 ldi XL, low(PFA_WARM)
-00fa8e efba ldi XH, high(PFA_WARM)
- ; its a far jump...
-00fa8f 940c f004 jmp_ DO_NEXT
- .include "words/warm.asm"
-
- ; System
- ; initialize amforth further. executes turnkey operation and go to quit
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_WARM:
-00fa91 ff04 .dw $ff04
-00fa92 6177
-00fa93 6d72 .db "warm"
-00fa94 fa6f .dw VE_HEAD
- .set VE_HEAD = VE_WARM
- XT_WARM:
-00fa95 f000 .dw DO_COLON
- PFA_WARM:
- .endif
-00fa96 fd7b .dw XT_INIT_RAM
-00fa97 f045 .dw XT_DOLITERAL
-00fa98 fb99 .dw XT_NOOP
-00fa99 f045 .dw XT_DOLITERAL
-00fa9a fa6b .dw XT_PAUSE
-00fa9b fc0d .dw XT_DEFERSTORE
-00fa9c 0319 .dw XT_LBRACKET
-00fa9d f612 .dw XT_TURNKEY
-00fa9e fa42 .dw XT_QUIT ; never returns
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/sp0.asm"
-
- ; Stack
- ; start address of the data stack
- VE_SP0:
-00fa9f ff03 .dw $ff03
-00faa0 7073
-00faa1 0030 .db "sp0",0
-00faa2 fa91 .dw VE_HEAD
- .set VE_HEAD = VE_SP0
- XT_SP0:
-00faa3 f080 .dw PFA_DOVALUE1
- PFA_SP0:
-00faa4 0006 .dw USER_SP0
-00faa5 fbf6 .dw XT_UDEFERFETCH
-00faa6 fc02 .dw XT_UDEFERSTORE
-
- ; ( -- addr)
- ; Stack
- ; address of user variable to store top-of-stack for inactive tasks
- VE_SP:
-00faa7 ff02 .dw $ff02
-00faa8 7073 .db "sp"
-00faa9 fa9f .dw VE_HEAD
- .set VE_HEAD = VE_SP
- XT_SP:
-00faaa f066 .dw PFA_DOUSER
- PFA_SP:
-00faab 0008 .dw USER_SP
- .include "words/rp0.asm"
-
- ; Stack
- ; start address of return stack
- VE_RP0:
-00faac ff03 .dw $ff03
-00faad 7072
-00faae 0030 .db "rp0",0
-00faaf faa7 .dw VE_HEAD
- .set VE_HEAD = VE_RP0
- XT_RP0:
-00fab0 f000 .dw DO_COLON
- PFA_RP0:
-00fab1 fab4 .dw XT_DORP0
-00fab2 f08a .dw XT_FETCH
-00fab3 f025 .dw XT_EXIT
-
- ; ( -- addr)
- ; Stack
- ; user variable of the address of the initial return stack
- ;VE_DORP0:
- ; .dw $ff05
- ; .db "(rp0)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DORP0
- XT_DORP0:
-00fab4 f066 .dw PFA_DOUSER
- PFA_DORP0:
-00fab5 0004 .dw USER_RP
- .include "words/depth.asm"
-
- ; Stack
- ; number of single-cell values contained in the data stack before n was placed on the stack.
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEPTH:
-00fab6 ff05 .dw $ff05
-00fab7 6564
-00fab8 7470
-00fab9 0068 .db "depth",0
-00faba faac .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
- XT_DEPTH:
-00fabb f000 .dw DO_COLON
- PFA_DEPTH:
- .endif
-00fabc faa3 .dw XT_SP0
-00fabd f29e .dw XT_SP_FETCH
-00fabe f1a4 .dw XT_MINUS
-00fabf f215 .dw XT_2SLASH
-00fac0 f246 .dw XT_1MINUS
-00fac1 f025 .dw XT_EXIT
- .include "words/interpret.asm"
-
- ; System
- ; Interpret SOURCE word by word.
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_INTERPRET:
-00fac2 ff09 .dw $ff09
-00fac3 6e69
-00fac4 6574
-00fac5 7072
-00fac6 6572
-00fac7 0074 .db "interpret",0
-00fac8 fab6 .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
- XT_INTERPRET:
-00fac9 f000 .dw DO_COLON
- .endif
- PFA_INTERPRET:
-00faca f9ce .dw XT_PARSENAME ; ( -- addr len )
-00facb f0c2 .dw XT_DUP ; ( -- addr len flag)
-00facc f03e .dw XT_DOCONDBRANCH
-00facd fada DEST(PFA_INTERPRET2)
-00face fae6 .dw XT_FORTHRECOGNIZER
-00facf faf1 .dw XT_RECOGNIZE
-00fad0 f565 .dw XT_STATE
-00fad1 f08a .dw XT_FETCH
-00fad2 f03e .dw XT_DOCONDBRANCH
-00fad3 fad5 DEST(PFA_INTERPRET1)
-00fad4 fbc5 .dw XT_ICELLPLUS ; we need the compile action
- PFA_INTERPRET1:
-00fad5 f3e2 .dw XT_FETCHI
-00fad6 f02f .dw XT_EXECUTE
-00fad7 fb71 .dw XT_QSTACK
-00fad8 f034 .dw XT_DOBRANCH
-00fad9 faca DEST(PFA_INTERPRET)
- PFA_INTERPRET2:
-00fada f588 .dw XT_2DROP
-00fadb f025 .dw XT_EXIT
- .include "words/forth-recognizer.asm"
-
- ; System Value
- ; address of the next free data space (RAM) cell
- VE_FORTHRECOGNIZER:
-00fadc ff10 .dw $ff10
-00fadd 6f66
-00fade 7472
-00fadf 2d68
-00fae0 6572
-00fae1 6f63
-00fae2 6e67
-00fae3 7a69
-00fae4 7265 .db "forth-recognizer"
-00fae5 fac2 .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
- XT_FORTHRECOGNIZER:
-00fae6 f080 .dw PFA_DOVALUE1
- PFA_FORTHRECOGNIZER:
-00fae7 0050 .dw CFG_FORTHRECOGNIZER
-00fae8 fbce .dw XT_EDEFERFETCH
-00fae9 fbd8 .dw XT_EDEFERSTORE
- .include "words/recognize.asm"
-
- ; System
- ; walk the recognizer stack
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RECOGNIZE:
-00faea ff09 .dw $ff09
-00faeb 6572
-00faec 6f63
-00faed 6e67
-00faee 7a69
-00faef 0065 .db "recognize",0
-00faf0 fadc .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
- XT_RECOGNIZE:
-00faf1 f000 .dw DO_COLON
- PFA_RECOGNIZE:
- .endif
-00faf2 f045 .dw XT_DOLITERAL
-00faf3 fafc .dw XT_RECOGNIZE_A
-00faf4 f0d5 .dw XT_SWAP
-00faf5 03cf .dw XT_MAPSTACK
-00faf6 f12b .dw XT_ZEROEQUAL
-00faf7 f03e .dw XT_DOCONDBRANCH
-00faf8 fafb DEST(PFA_RECOGNIZE1)
-00faf9 f588 .dw XT_2DROP
-00fafa fb64 .dw XT_DT_NULL
- PFA_RECOGNIZE1:
-00fafb f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- ; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
- XT_RECOGNIZE_A:
-00fafc f000 .dw DO_COLON
- PFA_RECOGNIZE_A:
- .endif
-00fafd f0f2 .dw XT_ROT ; -- len xt addr
-00fafe f0f2 .dw XT_ROT ; -- xt addr len
-00faff f57f .dw XT_2DUP
-00fb00 f32f .dw XT_2TO_R
-00fb01 f0f2 .dw XT_ROT ; -- addr len xt
-00fb02 f02f .dw XT_EXECUTE ; -- i*x dt:* | dt:null
-00fb03 f33e .dw XT_2R_FROM
-00fb04 f0f2 .dw XT_ROT
-00fb05 f0c2 .dw XT_DUP
-00fb06 fb64 .dw XT_DT_NULL
-00fb07 fdaa .dw XT_EQUAL
-00fb08 f03e .dw XT_DOCONDBRANCH
-00fb09 fb0d DEST(PFA_RECOGNIZE_A1)
-00fb0a f0ea .dw XT_DROP
-00fb0b f165 .dw XT_ZERO
-00fb0c f025 .dw XT_EXIT
- PFA_RECOGNIZE_A1:
-00fb0d f101 .dw XT_NIP
-00fb0e f101 .dw XT_NIP
-00fb0f f15c .dw XT_TRUE
-00fb10 f025 .dw XT_EXIT
-
- ; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
- ; [: ( addr len -- addr len 0 | i*x dt:* -1 )
- ; rot rot 2dup 2>r rot execute 2r> rot
- ; dup dt:null = ( -- addr len dt:* f )
- ; if drop 0 else nip nip -1 then
- ; ;]
- ; map-stack ( -- i*x addr len dt:* f )
- ; 0= if \ a recognizer did the job, remove addr/len
- ; 2drop dt:null
- ; then ;
- ;
- .include "words/rec-intnum.asm"
-
- ; Interpreter
- ; Method table for single cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NUM:
-00fb11 ff06 .dw $ff06
-00fb12 7464
-00fb13 6e3a
-00fb14 6d75 .db "dt:num"
-00fb15 faea .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
- XT_DT_NUM:
-00fb16 f060 .dw PFA_DOCONSTANT
- PFA_DT_NUM:
- .endif
-00fb17 fb99 .dw XT_NOOP ; interpret
-00fb18 01a5 .dw XT_LITERAL ; compile
-00fb19 01a5 .dw XT_LITERAL ; postpone
-
- ; ( -- addr )
- ; Interpreter
- ; Method table for double cell integers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_DNUM:
-00fb1a ff07 .dw $ff07
-00fb1b 7464
-00fb1c 643a
-00fb1d 756e
-00fb1e 006d .db "dt:dnum",0
-00fb1f fb11 .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
- XT_DT_DNUM:
-00fb20 f060 .dw PFA_DOCONSTANT
- PFA_DT_DNUM:
- .endif
-00fb21 fb99 .dw XT_NOOP ; interpret
-00fb22 fda2 .dw XT_2LITERAL ; compile
-00fb23 fda2 .dw XT_2LITERAL ; postpone
-
- ; ( addr len -- f )
- ; Interpreter
- ; recognizer for integer numbers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- VE_REC_NUM:
-00fb24 ff07 .dw $ff07
-00fb25 6572
-00fb26 3a63
-00fb27 756e
-00fb28 006d .db "rec:num",0
-00fb29 fb1a .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
- XT_REC_NUM:
-00fb2a f000 .dw DO_COLON
- PFA_REC_NUM:
- .endif
- ; try converting to a number
-00fb2b f90e .dw XT_NUMBER
-00fb2c f03e .dw XT_DOCONDBRANCH
-00fb2d fb36 DEST(PFA_REC_NONUMBER)
-00fb2e fdb1 .dw XT_ONE
-00fb2f fdaa .dw XT_EQUAL
-00fb30 f03e .dw XT_DOCONDBRANCH
-00fb31 fb34 DEST(PFA_REC_INTNUM2)
-00fb32 fb16 .dw XT_DT_NUM
-00fb33 f025 .dw XT_EXIT
- PFA_REC_INTNUM2:
-00fb34 fb20 .dw XT_DT_DNUM
-00fb35 f025 .dw XT_EXIT
- PFA_REC_NONUMBER:
-00fb36 fb64 .dw XT_DT_NULL
-00fb37 f025 .dw XT_EXIT
- .include "words/rec-find.asm"
-
- ; Interpreter
- ; search for a word
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- VE_REC_FIND:
-00fb38 ff08 .dw $ff08
-00fb39 6572
-00fb3a 3a63
-00fb3b 6966
-00fb3c 646e .db "rec:find"
-00fb3d fb24 .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
- XT_REC_FIND:
-00fb3e f000 .dw DO_COLON
- PFA_REC_FIND:
- .endif
-00fb3f f9ea .DW XT_FINDXT
-00fb40 f0c2 .dw XT_DUP
-00fb41 f12b .dw XT_ZEROEQUAL
-00fb42 f03e .dw XT_DOCONDBRANCH
-00fb43 fb47 DEST(PFA_REC_WORD_FOUND)
-00fb44 f0ea .dw XT_DROP
-00fb45 fb64 .dw XT_DT_NULL
-00fb46 f025 .dw XT_EXIT
- PFA_REC_WORD_FOUND:
-00fb47 fb4e .dw XT_DT_XT
-
-00fb48 f025 .dw XT_EXIT
-
- ; ( -- addr )
- ; Interpreter
- ; actions to handle execution tokens and their flags
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_XT:
-00fb49 ff05 .dw $ff05
-00fb4a 7464
-00fb4b 783a
-00fb4c 0074 .db "dt:xt",0
-00fb4d fb38 .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
- XT_DT_XT:
-00fb4e f060 .dw PFA_DOCONSTANT
- PFA_DT_XT:
- .endif
-00fb4f fb52 .dw XT_R_WORD_INTERPRET
-00fb50 fb56 .dw XT_R_WORD_COMPILE
-00fb51 fda2 .dw XT_2LITERAL
-
- ; ( XT flags -- )
- ; Interpreter
- ; interpret method for WORD recognizer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_R_WORD_INTERPRET:
-00fb52 f000 .dw DO_COLON
- PFA_R_WORD_INTERPRET:
- .endif
-00fb53 f0ea .dw XT_DROP ; the flags are in the way
-00fb54 f02f .dw XT_EXECUTE
-00fb55 f025 .dw XT_EXIT
-
- ; ( XT flags -- )
- ; Interpreter
- ; Compile method for WORD recognizer
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- XT_R_WORD_COMPILE:
-00fb56 f000 .dw DO_COLON
- PFA_R_WORD_COMPILE:
- .endif
-00fb57 f132 .dw XT_ZEROLESS
-00fb58 f03e .dw XT_DOCONDBRANCH
-00fb59 fb5c DEST(PFA_R_WORD_COMPILE1)
-00fb5a 018f .dw XT_COMMA
-00fb5b f025 .dw XT_EXIT
- PFA_R_WORD_COMPILE1:
-00fb5c f02f .dw XT_EXECUTE
-00fb5d f025 .dw XT_EXIT
- .include "words/dt-null.asm"
-
- ; Interpreter
- ; there is no parser for this recognizer, this is the default and failsafe part
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DT_NULL:
-00fb5e ff07 .dw $ff07
-00fb5f 7464
-00fb60 6e3a
-00fb61 6c75
-../../common\words/dt-null.asm(12): warning: .cseg .db misalignment - padding zero byte
-00fb62 006c .db "dt:null"
-00fb63 fb49 .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
- XT_DT_NULL:
-00fb64 f060 .dw PFA_DOCONSTANT
- PFA_DT_NULL:
- .endif
-00fb65 fb68 .dw XT_FAIL ; interpret
-00fb66 fb68 .dw XT_FAIL ; compile
-00fb67 fb68 .dw XT_FAIL ; postpone
-
- ; ( addr len -- )
- ; Interpreter
- ; default failure action: throw exception -13.
- .if cpu_msp430==1
- .endif
- .if cpu_avr8==1
- ;VE_FAIL:
- ; .dw $ff04
- ; .db "fail"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_FAIL
- XT_FAIL:
-00fb68 f000 .dw DO_COLON
- PFA_FAIL:
- .endif
-00fb69 f045 .dw XT_DOLITERAL
-00fb6a fff3 .dw -13
-00fb6b f85b .dw XT_THROW
-
- .include "words/q-stack.asm"
-
- ; Tools
- ; check data stack depth and exit to quit if underrun
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_QSTACK:
-00fb6c ff06 .dw $ff06
-00fb6d 733f
-00fb6e 6174
-00fb6f 6b63 .db "?stack"
-00fb70 fb5e .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
- XT_QSTACK:
-00fb71 f000 .dw DO_COLON
- PFA_QSTACK:
- .endif
-00fb72 fabb .dw XT_DEPTH
-00fb73 f132 .dw XT_ZEROLESS
-00fb74 f03e .dw XT_DOCONDBRANCH
-00fb75 fb79 DEST(PFA_QSTACK1)
-00fb76 f045 .dw XT_DOLITERAL
-00fb77 fffc .dw -4
-00fb78 f85b .dw XT_THROW
- PFA_QSTACK1:
-00fb79 f025 .dw XT_EXIT
- .include "words/ver.asm"
-
- ; Tools
- ; print the version string
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DOT_VER:
-00fb7a ff03 .dw $ff03
-00fb7b 6576
-../../common\words/ver.asm(12): warning: .cseg .db misalignment - padding zero byte
-00fb7c 0072 .db "ver"
-00fb7d fb6c .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
- XT_DOT_VER:
-00fb7e f000 .dw DO_COLON
- PFA_DOT_VER:
- .endif
-00fb7f f527 .dw XT_ENV_FORTHNAME
-00fb80 f7ba .dw XT_ITYPE
-00fb81 f7fc .dw XT_SPACE
-00fb82 f56b .dw XT_BASE
-00fb83 f08a .dw XT_FETCH
-
-00fb84 f535 .dw XT_ENV_FORTHVERSION
-00fb85 f5f7 .dw XT_DECIMAL
-00fb86 fd92 .dw XT_S2D
-00fb87 f6d8 .dw XT_L_SHARP
-00fb88 f6e0 .dw XT_SHARP
-00fb89 f045 .dw XT_DOLITERAL
-00fb8a 002e .dw '.'
-00fb8b f6c9 .dw XT_HOLD
-00fb8c f6f6 .dw XT_SHARP_S
-00fb8d f701 .dw XT_SHARP_G
-00fb8e f815 .dw XT_TYPE
-00fb8f f56b .dw XT_BASE
-00fb90 f092 .dw XT_STORE
-00fb91 f7fc .dw XT_SPACE
-00fb92 f53d .dw XT_ENV_CPU
-00fb93 f7ba .dw XT_ITYPE
-
-00fb94 f025 .dw XT_EXIT
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/noop.asm"
-
- ; Tools
- ; do nothing
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NOOP:
-00fb95 ff04 .dw $ff04
-00fb96 6f6e
-00fb97 706f .db "noop"
-00fb98 fb7a .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
- XT_NOOP:
-00fb99 f000 .dw DO_COLON
- PFA_NOOP:
- .endif
-00fb9a f025 .DW XT_EXIT
- .include "words/unused.asm"
-
- ; Tools
- ; Amount of available RAM (incl. PAD)
- VE_UNUSED:
-00fb9b ff06 .dw $ff06
-00fb9c 6e75
-00fb9d 7375
-00fb9e 6465 .db "unused"
-00fb9f fb95 .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
- XT_UNUSED:
-00fba0 f000 .dw DO_COLON
- PFA_UNUSED:
-00fba1 f29e .dw XT_SP_FETCH
-00fba2 f5d9 .dw XT_HERE
-00fba3 f1a4 .dw XT_MINUS
-00fba4 f025 .dw XT_EXIT
-
- .include "words/to.asm"
-
- ; Tools
- ; store the TOS to the named value (eeprom cell)
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TO:
-00fba5 0002 .dw $0002
-00fba6 6f74 .db "to"
-00fba7 fb9b .dw VE_HEAD
- .set VE_HEAD = VE_TO
- XT_TO:
-00fba8 f000 .dw DO_COLON
- PFA_TO:
- .endif
-00fba9 f824 .dw XT_TICK
-00fbaa fd9b .dw XT_TO_BODY
-00fbab f565 .dw XT_STATE
-00fbac f08a .dw XT_FETCH
-00fbad f03e .dw XT_DOCONDBRANCH
-00fbae fbb9 DEST(PFA_TO1)
-00fbaf 0184 .dw XT_COMPILE
-00fbb0 fbb3 .dw XT_DOTO
-00fbb1 018f .dw XT_COMMA
-00fbb2 f025 .dw XT_EXIT
-
- ; ( n -- ) (R: IP -- IP+1)
- ; Tools
- ; runtime portion of to
- ;VE_DOTO:
- ; .dw $ff04
- ; .db "(to)"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_DOTO
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
-
- XT_DOTO:
-00fbb3 f000 .dw DO_COLON
- PFA_DOTO:
- .endif
-00fbb4 f107 .dw XT_R_FROM
-00fbb5 f0c2 .dw XT_DUP
-00fbb6 fbc5 .dw XT_ICELLPLUS
-00fbb7 f110 .dw XT_TO_R
-00fbb8 f3e2 .dw XT_FETCHI
- PFA_TO1:
-00fbb9 f0c2 .dw XT_DUP
-00fbba fbc5 .dw XT_ICELLPLUS
-00fbbb fbc5 .dw XT_ICELLPLUS
-00fbbc f3e2 .dw XT_FETCHI
-00fbbd f02f .dw XT_EXECUTE
-00fbbe f025 .dw XT_EXIT
- .include "words/i-cellplus.asm"
-
- ; Compiler
- ; skip to the next cell in flash
- VE_ICELLPLUS:
-00fbbf ff07 .dw $FF07
-00fbc0 2d69
-00fbc1 6563
-00fbc2 6c6c
-00fbc3 002b .db "i-cell+",0
-00fbc4 fba5 .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
- XT_ICELLPLUS:
-00fbc5 f000 .dw DO_COLON
- PFA_ICELLPLUS:
-00fbc6 f240 .dw XT_1PLUS
-00fbc7 f025 .dw XT_EXIT
-
- .include "words/edefer-fetch.asm"
-
- ; System
- ; does the real defer@ for eeprom defers
- VE_EDEFERFETCH:
-00fbc8 ff07 .dw $ff07
-00fbc9 6445
-00fbca 6665
-00fbcb 7265
-00fbcc 0040 .db "Edefer@",0
-00fbcd fbbf .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
- XT_EDEFERFETCH:
-00fbce f000 .dw DO_COLON
- PFA_EDEFERFETCH:
-00fbcf f3e2 .dw XT_FETCHI
-00fbd0 f370 .dw XT_FETCHE
-00fbd1 f025 .dw XT_EXIT
- .include "words/edefer-store.asm"
-
- ; System
- ; does the real defer! for eeprom defers
- VE_EDEFERSTORE:
-00fbd2 ff07 .dw $ff07
-00fbd3 6445
-00fbd4 6665
-00fbd5 7265
-00fbd6 0021 .db "Edefer!",0
-00fbd7 fbc8 .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
- XT_EDEFERSTORE:
-00fbd8 f000 .dw DO_COLON
- PFA_EDEFERSTORE:
-00fbd9 f3e2 .dw XT_FETCHI
-00fbda f34c .dw XT_STOREE
-00fbdb f025 .dw XT_EXIT
- .include "words/rdefer-fetch.asm"
-
- ; System
- ; The defer@ for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERFETCH:
-00fbdc ff07 .dw $ff07
-00fbdd 6452
-00fbde 6665
-00fbdf 7265
-00fbe0 0040 .db "Rdefer@",0
-00fbe1 fbd2 .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
- XT_RDEFERFETCH:
-00fbe2 f000 .dw DO_COLON
- PFA_RDEFERFETCH:
- .endif
-00fbe3 f3e2 .dw XT_FETCHI
-00fbe4 f08a .dw XT_FETCH
-00fbe5 f025 .dw XT_EXIT
- .include "words/rdefer-store.asm"
-
- ; System
- ; The defer! for ram defers
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_RDEFERSTORE:
-00fbe6 ff07 .dw $ff07
-00fbe7 6452
-00fbe8 6665
-00fbe9 7265
-00fbea 0021 .db "Rdefer!",0
-00fbeb fbdc .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
- XT_RDEFERSTORE:
-00fbec f000 .dw DO_COLON
- PFA_RDEFERSTORE:
- .endif
-00fbed f3e2 .dw XT_FETCHI
-00fbee f092 .dw XT_STORE
-00fbef f025 .dw XT_EXIT
-
- .include "words/udefer-fetch.asm"
-
- ; System
- ; does the real defer@ for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERFETCH:
-00fbf0 ff07 .dw $ff07
-00fbf1 6455
-00fbf2 6665
-00fbf3 7265
-00fbf4 0040 .db "Udefer@",0
-00fbf5 fbe6 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
- XT_UDEFERFETCH:
-00fbf6 f000 .dw DO_COLON
- PFA_UDEFERFETCH:
- .endif
-00fbf7 f3e2 .dw XT_FETCHI
-00fbf8 f313 .dw XT_UP_FETCH
-00fbf9 f1ae .dw XT_PLUS
-00fbfa f08a .dw XT_FETCH
-00fbfb f025 .dw XT_EXIT
- .include "words/udefer-store.asm"
-
- ; System
- ; does the real defer! for user based defers
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_UDEFERSTORE:
-00fbfc ff07 .dw $ff07
-00fbfd 6455
-00fbfe 6665
-00fbff 7265
-00fc00 0021 .db "Udefer!",0
-00fc01 fbf0 .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
- XT_UDEFERSTORE:
-00fc02 f000 .dw DO_COLON
- PFA_UDEFERSTORE:
- .endif
-
-00fc03 f3e2 .dw XT_FETCHI
-00fc04 f313 .dw XT_UP_FETCH
-00fc05 f1ae .dw XT_PLUS
-00fc06 f092 .dw XT_STORE
-00fc07 f025 .dw XT_EXIT
-
- .include "words/defer-store.asm"
-
- ; System
- ; stores xt1 as the xt to be executed when xt2 is called
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERSTORE:
-00fc08 ff06 .dw $ff06
-00fc09 6564
-00fc0a 6566
-00fc0b 2172 .db "defer!"
-00fc0c fbfc .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
- XT_DEFERSTORE:
-00fc0d f000 .dw DO_COLON
- PFA_DEFERSTORE:
- .endif
-00fc0e fd9b .dw XT_TO_BODY
-00fc0f f0c2 .dw XT_DUP
-00fc10 fbc5 .dw XT_ICELLPLUS
-00fc11 fbc5 .dw XT_ICELLPLUS
-00fc12 f3e2 .dw XT_FETCHI
-00fc13 f02f .dw XT_EXECUTE
-00fc14 f025 .dw XT_EXIT
-
- .include "words/defer-fetch.asm"
-
- ; System
- ; returns the XT associated with the given XT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_DEFERFETCH:
-00fc15 ff06 .dw $ff06
-00fc16 6564
-00fc17 6566
-00fc18 4072 .db "defer@"
-00fc19 fc08 .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
- XT_DEFERFETCH:
-00fc1a f000 .dw DO_COLON
- PFA_DEFERFETCH:
- .endif
-00fc1b fd9b .dw XT_TO_BODY
-00fc1c f0c2 .dw XT_DUP
-00fc1d fbc5 .dw XT_ICELLPLUS
-00fc1e f3e2 .dw XT_FETCHI
-00fc1f f02f .dw XT_EXECUTE
-00fc20 f025 .dw XT_EXIT
- .include "words/do-defer.asm"
-
- ; System
- ; runtime of defer
- VE_DODEFER:
-00fc21 ff07 .dw $ff07
-00fc22 6428
-00fc23 6665
-00fc24 7265
-00fc25 0029 .db "(defer)", 0
-00fc26 fc15 .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
- XT_DODEFER:
-00fc27 f000 .dw DO_COLON
- PFA_DODEFER:
-00fc28 0161 .dw XT_DOCREATE
-00fc29 02c1 .dw XT_REVEAL
-00fc2a 0184 .dw XT_COMPILE
-00fc2b fc2d .dw PFA_DODEFER1
-00fc2c f025 .dw XT_EXIT
- PFA_DODEFER1:
-00fc2d 940e 02da call_ DO_DODOES
-00fc2f f0c2 .dw XT_DUP
-00fc30 fbc5 .dw XT_ICELLPLUS
-00fc31 f3e2 .dw XT_FETCHI
-00fc32 f02f .dw XT_EXECUTE
-00fc33 f02f .dw XT_EXECUTE
-00fc34 f025 .dw XT_EXIT
-
- ; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
-
- .include "words/search-wordlist.asm"
-
- ; Search Order
- ; searches the word list wid for the word at c-addr/len
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SEARCH_WORDLIST:
-00fc35 ff0f .dw $ff0f
-00fc36 6573
-00fc37 7261
-00fc38 6863
-00fc39 772d
-00fc3a 726f
-00fc3b 6c64
-00fc3c 7369
-00fc3d 0074 .db "search-wordlist",0
-00fc3e fc21 .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
- XT_SEARCH_WORDLIST:
-00fc3f f000 .dw DO_COLON
- PFA_SEARCH_WORDLIST:
- .endif
-00fc40 f110 .dw XT_TO_R
-00fc41 f165 .dw XT_ZERO
-00fc42 f045 .dw XT_DOLITERAL
-00fc43 fc54 .dw XT_ISWORD
-00fc44 f107 .dw XT_R_FROM
-00fc45 fc71 .dw XT_TRAVERSEWORDLIST
-00fc46 f0c2 .dw XT_DUP
-00fc47 f12b .dw XT_ZEROEQUAL
-00fc48 f03e .dw XT_DOCONDBRANCH
-00fc49 fc4e DEST(PFA_SEARCH_WORDLIST1)
-00fc4a f588 .dw XT_2DROP
-00fc4b f0ea .dw XT_DROP
-00fc4c f165 .dw XT_ZERO
-00fc4d f025 .dw XT_EXIT
- PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
-00fc4e f0c2 .dw XT_DUP
-00fc4f fc98 .dw XT_NFA2CFA
- ; .. and get the header flag
-00fc50 f0d5 .dw XT_SWAP
-00fc51 0147 .dw XT_NAME2FLAGS
-00fc52 0135 .dw XT_IMMEDIATEQ
-00fc53 f025 .dw XT_EXIT
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- XT_ISWORD:
-00fc54 f000 .dw DO_COLON
- PFA_ISWORD:
- .endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
-00fc55 f110 .dw XT_TO_R
-00fc56 f0ea .dw XT_DROP
-00fc57 f57f .dw XT_2DUP
-00fc58 f119 .dw XT_R_FETCH ; -- addr len addr len nt
-00fc59 fc8c .dw XT_NAME2STRING
-00fc5a fca2 .dw XT_ICOMPARE ; (-- addr len f )
-00fc5b f03e .dw XT_DOCONDBRANCH
-00fc5c fc62 DEST(PFA_ISWORD3)
- ; not now
-00fc5d f107 .dw XT_R_FROM
-00fc5e f0ea .dw XT_DROP
-00fc5f f165 .dw XT_ZERO
-00fc60 f15c .dw XT_TRUE ; maybe next word
-00fc61 f025 .dw XT_EXIT
- PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
-00fc62 f588 .dw XT_2DROP
-00fc63 f107 .dw XT_R_FROM
-00fc64 f165 .dw XT_ZERO ; finish traverse-wordlist
-00fc65 f025 .dw XT_EXIT
- .include "words/traverse-wordlist.asm"
-
- ; Tools Ext (2012)
- ; call the xt for every member of the wordlist wid until xt returns false
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TRAVERSEWORDLIST:
-00fc66 ff11 .dw $ff11
-00fc67 7274
-00fc68 7661
-00fc69 7265
-00fc6a 6573
-00fc6b 772d
-00fc6c 726f
-00fc6d 6c64
-00fc6e 7369
-00fc6f 0074 .db "traverse-wordlist",0
-00fc70 fc35 .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
- XT_TRAVERSEWORDLIST:
-00fc71 f000 .dw DO_COLON
- PFA_TRAVERSEWORDLIST:
-
- .endif
-00fc72 f370 .dw XT_FETCHE
- PFA_TRAVERSEWORDLIST1:
-00fc73 f0c2 .dw XT_DUP ; ( -- xt nt nt )
-00fc74 f03e .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
-00fc75 fc82 DEST(PFA_TRAVERSEWORDLIST2)
-00fc76 f57f .dw XT_2DUP
-00fc77 f32f .dw XT_2TO_R
-00fc78 f0d5 .dw XT_SWAP
-00fc79 f02f .dw XT_EXECUTE
-00fc7a f33e .dw XT_2R_FROM
-00fc7b f0f2 .dw XT_ROT
-00fc7c f03e .dw XT_DOCONDBRANCH
-00fc7d fc82 DEST(PFA_TRAVERSEWORDLIST2)
-00fc7e 043e .dw XT_NFA2LFA
-00fc7f f3e2 .dw XT_FETCHI
-00fc80 f034 .dw XT_DOBRANCH ; ( -- addr )
-00fc81 fc73 DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
- PFA_TRAVERSEWORDLIST2:
-00fc82 f588 .dw XT_2DROP
-00fc83 f025 .dw XT_EXIT
-
- ; : traverse-wordlist ( i*x xt wid -- i*x' )
- ; begin @ dup
- ; while
- ; 2dup 2>r
- ; swap execute ( i*x nt -- i*x' f )
- ; 2r> rot
- ; while
- ; nfa>lfa @i
- ; repeat then 2drop ;
- .include "words/name2string.asm"
-
- ; Tools Ext (2012)
- ; get a (flash) string from a name token nt
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NAME2STRING:
-00fc84 ff0b .dw $ff0b
-00fc85 616e
-00fc86 656d
-00fc87 733e
-00fc88 7274
-00fc89 6e69
-00fc8a 0067 .db "name>string",0
-00fc8b fc66 .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
- XT_NAME2STRING:
-00fc8c f000 .dw DO_COLON
- PFA_NAME2STRING:
-
- .endif
-00fc8d f7e6 .dw XT_ICOUNT ; ( -- addr n )
-00fc8e f045 .dw XT_DOLITERAL
-00fc8f 00ff .dw 255
-00fc90 f224 .dw XT_AND ; mask immediate bit
-00fc91 f025 .dw XT_EXIT
- .include "words/nfa2cfa.asm"
-
- ; Tools
- ; get the XT from a name token
- VE_NFA2CFA:
-00fc92 ff07 .dw $ff07
-00fc93 666e
-00fc94 3e61
-00fc95 6663
-../../avr8\words/nfa2cfa.asm(6): warning: .cseg .db misalignment - padding zero byte
-00fc96 0061 .db "nfa>cfa"
-00fc97 fc84 .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
- XT_NFA2CFA:
-00fc98 f000 .dw DO_COLON
- PFA_NFA2CFA:
-00fc99 043e .dw XT_NFA2LFA ; skip to link field
-00fc9a f240 .dw XT_1PLUS ; next is the execution token
-00fc9b f025 .dw XT_EXIT
- .include "words/icompare.asm"
-
- ; Tools
- ; compares string in RAM with string in flash. f is zero if equal like COMPARE
- VE_ICOMPARE:
-00fc9c ff08 .dw $ff08
-00fc9d 6369
-00fc9e 6d6f
-00fc9f 6170
-00fca0 6572 .db "icompare"
-00fca1 fc92 .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
- XT_ICOMPARE:
-00fca2 f000 .dw DO_COLON
- PFA_ICOMPARE:
-00fca3 f110 .dw XT_TO_R ; ( -- r-addr r-len f-addr)
-00fca4 f0e0 .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
-00fca5 f107 .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
-00fca6 f124 .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
-00fca7 f03e .dw XT_DOCONDBRANCH
-00fca8 fcad .dw PFA_ICOMPARE_SAMELEN
-00fca9 f588 .dw XT_2DROP
-00fcaa f0ea .dw XT_DROP
-00fcab f15c .dw XT_TRUE
-00fcac f025 .dw XT_EXIT
- PFA_ICOMPARE_SAMELEN:
-00fcad f0d5 .dw XT_SWAP ; ( -- r-addr f-addr len )
-00fcae f165 .dw XT_ZERO
-00fcaf 024e .dw XT_QDOCHECK
-00fcb0 f03e .dw XT_DOCONDBRANCH
-00fcb1 fcd2 .dw PFA_ICOMPARE_DONE
-00fcb2 f2ac .dw XT_DODO
- PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
-00fcb3 f0e0 .dw XT_OVER
-00fcb4 f08a .dw XT_FETCH
- .if WANT_IGNORECASE == 1
-00fcb5 fcd5 .dw XT_ICOMPARE_LC
- .endif
-00fcb6 f0e0 .dw XT_OVER
-00fcb7 f3e2 .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
- .if WANT_IGNORECASE == 1
-00fcb8 fcd5 .dw XT_ICOMPARE_LC
- .endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
-00fcb9 f0c2 .dw XT_DUP
- ;.dw XT_BYTESWAP
-00fcba f045 .dw XT_DOLITERAL
-00fcbb 0100 .dw $100
-00fcbc f16d .dw XT_ULESS
-00fcbd f03e .dw XT_DOCONDBRANCH
-00fcbe fcc3 .dw PFA_ICOMPARE_LASTCELL
-00fcbf f0d5 .dw XT_SWAP
-00fcc0 f045 .dw XT_DOLITERAL
-00fcc1 00ff .dw $00FF
-00fcc2 f224 .dw XT_AND ; the final swap can be omitted
- PFA_ICOMPARE_LASTCELL:
-00fcc3 f124 .dw XT_NOTEQUAL
-00fcc4 f03e .dw XT_DOCONDBRANCH
-00fcc5 fcca .dw PFA_ICOMPARE_NEXTLOOP
-00fcc6 f588 .dw XT_2DROP
-00fcc7 f15c .dw XT_TRUE
-00fcc8 f2e5 .dw XT_UNLOOP
-00fcc9 f025 .dw XT_EXIT
- PFA_ICOMPARE_NEXTLOOP:
-00fcca f240 .dw XT_1PLUS
-00fccb f0d5 .dw XT_SWAP
-00fccc f578 .dw XT_CELLPLUS
-00fccd f0d5 .dw XT_SWAP
-00fcce f045 .dw XT_DOLITERAL
-00fccf 0002 .dw 2
-00fcd0 f2cb .dw XT_DOPLUSLOOP
-00fcd1 fcb3 .dw PFA_ICOMPARE_LOOP
- PFA_ICOMPARE_DONE:
-00fcd2 f588 .dw XT_2DROP
-00fcd3 f165 .dw XT_ZERO
-00fcd4 f025 .dw XT_EXIT
-
- .if WANT_IGNORECASE == 1
- ; ( cc1 cc2 -- f)
- ; Tools
- ; compares two packed characters
- ;VE_ICOMPARELC:
- ; .dw $ff08
- ; .db "icompare-lower"
- ; .dw VE_HEAD
- ; .set VE_HEAD = VE_ICOMPARELC
- XT_ICOMPARE_LC:
-00fcd5 f000 .dw DO_COLON
- PFA_ICOMPARE_LC:
-00fcd6 f0c2 .dw XT_DUP
-00fcd7 f045 .dw XT_DOLITERAL
-00fcd8 00ff .dw $00ff
-00fcd9 f224 .dw XT_AND
-00fcda f6b2 .dw XT_TOLOWER
-00fcdb f0d5 .dw XT_SWAP
-00fcdc f30a .dw XT_BYTESWAP
-00fcdd f045 .dw XT_DOLITERAL
-00fcde 00ff .dw $00ff
-00fcdf f224 .dw XT_AND
-00fce0 f6b2 .dw XT_TOLOWER
-00fce1 f30a .dw XT_BYTESWAP
-00fce2 f22d .dw XT_OR
-00fce3 f025 .dw XT_EXIT
- .endif
-
- .include "words/star.asm"
-
- ; Arithmetics
- ; multiply routine
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_STAR:
-00fce4 ff01 .dw $ff01
-00fce5 002a .db "*",0
-00fce6 fc9c .dw VE_HEAD
- .set VE_HEAD = VE_STAR
- XT_STAR:
-00fce7 f000 .dw DO_COLON
- PFA_STAR:
- .endif
-
-00fce8 f1b7 .dw XT_MSTAR
-00fce9 f0ea .dw XT_DROP
-00fcea f025 .dw XT_EXIT
- .include "words/j.asm"
-
- ; Compiler
- ; loop counter of outer loop
- VE_J:
-00fceb ff01 .dw $FF01
-00fcec 006a .db "j",0
-00fced fce4 .dw VE_HEAD
- .set VE_HEAD = VE_J
- XT_J:
-00fcee f000 .dw DO_COLON
- PFA_J:
-00fcef f287 .dw XT_RP_FETCH
-00fcf0 f045 .dw XT_DOLITERAL
-00fcf1 0007 .dw 7
-00fcf2 f1ae .dw XT_PLUS
-00fcf3 f08a .dw XT_FETCH
-00fcf4 f287 .dw XT_RP_FETCH
-00fcf5 f045 .dw XT_DOLITERAL
-00fcf6 0009 .dw 9
-00fcf7 f1ae .dw XT_PLUS
-00fcf8 f08a .dw XT_FETCH
-00fcf9 f1ae .dw XT_PLUS
-00fcfa f025 .dw XT_EXIT
-
- .include "words/dabs.asm"
-
- ; Arithmetics
- ; double cell absolute value
- VE_DABS:
-00fcfb ff04 .dw $ff04
-00fcfc 6164
-00fcfd 7362 .db "dabs"
-00fcfe fceb .dw VE_HEAD
- .set VE_HEAD = VE_DABS
- XT_DABS:
-00fcff f000 .dw DO_COLON
- PFA_DABS:
-00fd00 f0c2 .dw XT_DUP
-00fd01 f132 .dw XT_ZEROLESS
-00fd02 f03e .dw XT_DOCONDBRANCH
-00fd03 fd05 .dw PFA_DABS1
-00fd04 fd0c .dw XT_DNEGATE
- PFA_DABS1:
-00fd05 f025 .dw XT_EXIT
- ; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
- .include "words/dnegate.asm"
-
- ; Arithmetics
- ; double cell negation
- VE_DNEGATE:
-00fd06 ff07 .dw $ff07
-00fd07 6e64
-00fd08 6765
-00fd09 7461
-00fd0a 0065 .db "dnegate",0
-00fd0b fcfb .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
- XT_DNEGATE:
-00fd0c f000 .dw DO_COLON
- PFA_DNEGATE:
-00fd0d f455 .dw XT_DINVERT
-00fd0e fdb1 .dw XT_ONE
-00fd0f f165 .dw XT_ZERO
-00fd10 f42f .dw XT_DPLUS
-00fd11 f025 .dw XT_EXIT
- ; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
- .include "words/cmove.asm"
-
- ; Memory
- ; copy data in RAM, from lower to higher addresses
- VE_CMOVE:
-00fd12 ff05 .dw $ff05
-00fd13 6d63
-00fd14 766f
-00fd15 0065 .db "cmove",0
-00fd16 fd06 .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
- XT_CMOVE:
-00fd17 fd18 .dw PFA_CMOVE
- PFA_CMOVE:
-00fd18 93bf push xh
-00fd19 93af push xl
-00fd1a 91e9 ld zl, Y+
-00fd1b 91f9 ld zh, Y+ ; addr-to
-00fd1c 91a9 ld xl, Y+
-00fd1d 91b9 ld xh, Y+ ; addr-from
-00fd1e 2f09 mov temp0, tosh
-00fd1f 2b08 or temp0, tosl
-00fd20 f021 brbs 1, PFA_CMOVE1
- PFA_CMOVE2:
-00fd21 911d ld temp1, X+
-00fd22 9311 st Z+, temp1
-00fd23 9701 sbiw tosl, 1
-00fd24 f7e1 brbc 1, PFA_CMOVE2
- PFA_CMOVE1:
-00fd25 91af pop xl
-00fd26 91bf pop xh
-00fd27 9189
-00fd28 9199 loadtos
-00fd29 940c f004 jmp_ DO_NEXT
- .include "words/2swap.asm"
-
- ; Stack
- ; Exchange the two top cell pairs
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2SWAP:
-00fd2b ff05 .dw $ff05
-00fd2c 7332
-00fd2d 6177
-00fd2e 0070 .db "2swap",0
-00fd2f fd12 .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
- XT_2SWAP:
-00fd30 f000 .dw DO_COLON
- PFA_2SWAP:
-
- .endif
-00fd31 f0f2 .dw XT_ROT
-00fd32 f110 .dw XT_TO_R
-00fd33 f0f2 .dw XT_ROT
-00fd34 f107 .dw XT_R_FROM
-00fd35 f025 .dw XT_EXIT
-
- .include "words/tib.asm"
-
- ; System
- ; refills the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_REFILLTIB:
-00fd36 ff0a .dw $ff0a
-00fd37 6572
-00fd38 6966
-00fd39 6c6c
-00fd3a 742d
-00fd3b 6269 .db "refill-tib"
-00fd3c fd2b .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
- XT_REFILLTIB:
-00fd3d f000 .dw DO_COLON
- PFA_REFILLTIB:
- .endif
-00fd3e fd59 .dw XT_TIB
-00fd3f f045 .dw XT_DOLITERAL
-00fd40 005a .dw TIB_SIZE
-00fd41 f8ab .dw XT_ACCEPT
-00fd42 fd5f .dw XT_NUMBERTIB
-00fd43 f092 .dw XT_STORE
-00fd44 f165 .dw XT_ZERO
-00fd45 f598 .dw XT_TO_IN
-00fd46 f092 .dw XT_STORE
-00fd47 f15c .dw XT_TRUE ; -1
-00fd48 f025 .dw XT_EXIT
-
- ; ( -- addr n )
- ; System
- ; address and current length of the input buffer
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_SOURCETIB:
-00fd49 ff0a .dw $FF0A
-00fd4a 6f73
-00fd4b 7275
-00fd4c 6563
-00fd4d 742d
-00fd4e 6269 .db "source-tib"
-00fd4f fd36 .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
- XT_SOURCETIB:
-00fd50 f000 .dw DO_COLON
- PFA_SOURCETIB:
- .endif
-00fd51 fd59 .dw XT_TIB
-00fd52 fd5f .dw XT_NUMBERTIB
-00fd53 f08a .dw XT_FETCH
-00fd54 f025 .dw XT_EXIT
-
- ; ( -- addr )
- ; System Variable
- ; terminal input buffer address
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TIB:
-00fd55 ff03 .dw $ff03
-00fd56 6974
-00fd57 0062 .db "tib",0
-00fd58 fd49 .dw VE_HEAD
- .set VE_HEAD = VE_TIB
- XT_TIB:
-00fd59 f053 .dw PFA_DOVARIABLE
- PFA_TIB:
-00fd5a 016f .dw ram_tib
- .dseg
-00016f ram_tib: .byte TIB_SIZE
- .cseg
- .endif
-
- ; ( -- addr )
- ; System Variable
- ; variable holding the number of characters in TIB
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_NUMBERTIB:
-00fd5b ff04 .dw $ff04
-00fd5c 7423
-00fd5d 6269 .db "#tib"
-00fd5e fd55 .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
- XT_NUMBERTIB:
-00fd5f f053 .dw PFA_DOVARIABLE
- PFA_NUMBERTIB:
-00fd60 01c9 .dw ram_sharptib
- .dseg
-0001c9 ram_sharptib: .byte 2
- .cseg
- .endif
-
- .include "words/init-ram.asm"
-
- ; Tools
- ; copy len cells from eeprom to ram
- VE_EE2RAM:
-00fd61 ff06 .dw $ff06
-00fd62 6565
-00fd63 723e
-00fd64 6d61 .db "ee>ram"
-00fd65 fd5b .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
- XT_EE2RAM:
-00fd66 f000 .dw DO_COLON
- PFA_EE2RAM: ; ( -- )
-00fd67 f165 .dw XT_ZERO
-00fd68 f2ac .dw XT_DODO
- PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
-00fd69 f0e0 .dw XT_OVER
-00fd6a f370 .dw XT_FETCHE
-00fd6b f0e0 .dw XT_OVER
-00fd6c f092 .dw XT_STORE
-00fd6d f578 .dw XT_CELLPLUS
-00fd6e f0d5 .dw XT_SWAP
-00fd6f f578 .dw XT_CELLPLUS
-00fd70 f0d5 .dw XT_SWAP
-00fd71 f2da .dw XT_DOLOOP
-00fd72 fd69 .dw PFA_EE2RAM_1
- PFA_EE2RAM_2:
-00fd73 f588 .dw XT_2DROP
-00fd74 f025 .dw XT_EXIT
-
- ; ( -- )
- ; Tools
- ; setup the default user area from eeprom
- VE_INIT_RAM:
-00fd75 ff08 .dw $ff08
-00fd76 6e69
-00fd77 7469
-00fd78 722d
-00fd79 6d61 .db "init-ram"
-00fd7a fd61 .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
- XT_INIT_RAM:
-00fd7b f000 .dw DO_COLON
- PFA_INI_RAM: ; ( -- )
-00fd7c f045 .dw XT_DOLITERAL
-00fd7d 007c .dw EE_INITUSER
-00fd7e f313 .dw XT_UP_FETCH
-00fd7f f045 .dw XT_DOLITERAL
-00fd80 0022 .dw SYSUSERSIZE
-00fd81 f215 .dw XT_2SLASH
-00fd82 fd66 .dw XT_EE2RAM
-00fd83 f025 .dw XT_EXIT
- .include "dict/compiler2.inc"
-
- ; included almost independently from each other
- ; on a include-per-use basis
- ;
- .if DICT_COMPILER2 == 0
- .endif
- .include "words/bounds.asm"
-
- ; Tools
- ; convert a string to an address range
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_BOUNDS:
-00fd84 ff06 .dw $ff06
-00fd85 6f62
-00fd86 6e75
-00fd87 7364 .db "bounds"
-00fd88 fd75 .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
- XT_BOUNDS:
-00fd89 f000 .dw DO_COLON
- PFA_BOUNDS:
- .endif
-00fd8a f0e0 .dw XT_OVER
-00fd8b f1ae .dw XT_PLUS
-00fd8c f0d5 .dw XT_SWAP
-00fd8d f025 .dw XT_EXIT
- .include "words/s-to-d.asm"
-
- ; Conversion
- ; extend (signed) single cell value to double cell
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_S2D:
-00fd8e ff03 .dw $ff03
-00fd8f 3e73
-00fd90 0064 .db "s>d",0
-00fd91 fd84 .dw VE_HEAD
- .set VE_HEAD = VE_S2D
- XT_S2D:
-00fd92 f000 .dw DO_COLON
- PFA_S2D:
- .endif
-00fd93 f0c2 .dw XT_DUP
-00fd94 f132 .dw XT_ZEROLESS
-00fd95 f025 .dw XT_EXIT
- .include "words/to-body.asm"
-
- ; Core
- ; get body from XT
- VE_TO_BODY:
-00fd96 ff05 .dw $ff05
-00fd97 623e
-00fd98 646f
-00fd99 0079 .db ">body",0
-00fd9a fd8e .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
- XT_TO_BODY:
-00fd9b f241 .dw PFA_1PLUS
- .elif AMFORTH_NRWW_SIZE>4000
- .elif AMFORTH_NRWW_SIZE>2000
- .else
- .endif
- ; now colon words
- ;;;;;;;;;;;;;;;;;;;;;;;;
- .include "words/2literal.asm"
-
- ; Compiler
- ; compile a cell pair literal in colon definitions
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_2LITERAL:
-00fd9c 0008 .dw $0008
-00fd9d 6c32
-00fd9e 7469
-00fd9f 7265
-00fda0 6c61 .db "2literal"
-00fda1 fd96 .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
- XT_2LITERAL:
-00fda2 f000 .dw DO_COLON
- PFA_2LITERAL:
- .endif
-00fda3 f0d5 .dw XT_SWAP
-00fda4 01a5 .dw XT_LITERAL
-00fda5 01a5 .dw XT_LITERAL
-00fda6 f025 .dw XT_EXIT
- .include "words/equal.asm"
-
- ; Compare
- ; compares two values for equality
- VE_EQUAL:
-00fda7 ff01 .dw $ff01
-00fda8 003d .db "=",0
-00fda9 fd9c .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
- XT_EQUAL:
-00fdaa f000 .dw DO_COLON
- PFA_EQUAL:
-00fdab f1a4 .dw XT_MINUS
-00fdac f12b .dw XT_ZEROEQUAL
-00fdad f025 .dw XT_EXIT
- .include "words/num-constants.asm"
-
- .endif
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_ONE:
-00fdae ff01 .dw $ff01
-00fdaf 0031 .db "1",0
-00fdb0 fda7 .dw VE_HEAD
- .set VE_HEAD = VE_ONE
- XT_ONE:
-00fdb1 f053 .dw PFA_DOVARIABLE
- PFA_ONE:
- .endif
-00fdb2 0001 .DW 1
-
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_TWO:
-00fdb3 ff01 .dw $ff01
-00fdb4 0032 .db "2",0
-00fdb5 fdae .dw VE_HEAD
- .set VE_HEAD = VE_TWO
- XT_TWO:
-00fdb6 f053 .dw PFA_DOVARIABLE
- PFA_TWO:
- .endif
-00fdb7 0002 .DW 2
- .if cpu_msp430==1
- .endif
-
- .if cpu_avr8==1
- VE_MINUSONE:
-00fdb8 ff02 .dw $ff02
-00fdb9 312d .db "-1"
-00fdba fdb3 .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
- XT_MINUSONE:
-00fdbb f053 .dw PFA_DOVARIABLE
- PFA_MINUSONE:
- .endif
-00fdbc ffff .DW -1
- .include "dict_appl_core.inc"
-
- ; in the NRWW flash section. There is a default file
- ; called dict/nrww.inc which contains all essential
- ; words which is included automatically. There is usually
- ; not much space left.
-
- .set flashlast = pc
- .if (pc>FLASHEND)
- .endif
-
- .dseg
- ; define a label for the 1st free ram address
- HERESTART:
- .eseg
- .include "amforth-eeprom.inc"
-000046 ff ff
- ; some configs
-000048 18 05 CFG_DP: .dw DPSTART ; Dictionary Pointer
-00004a cb 01 EE_HERE: .dw HERESTART ; Memory Allocation
-00004c a0 00 EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-00004e f6 03 CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-000050 6e 00 CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
- ; LEAVE stack is between data stack and return stack.
-000052 b0 40 CFG_LP0: .dw stackstart+1
-000054 d4 04 CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-000056 4c f5 CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-000058 5a 00 CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-00005a b8 fd CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
- CFG_ORDERLISTLEN:
-00005c 01 00 .dw 1
- CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
-00005e 5a 00 .dw CFG_FORTHWORDLIST ; get/set-order
-000060 .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
- CFG_RECOGNIZERLISTLEN:
-00006e 02 00 .dw 2
- CFG_RECOGNIZERLIST:
-000070 3e fb .dw XT_REC_FIND
-000072 2a fb .dw XT_REC_NUM
-000074 .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
- EE_STOREI:
-000078 8f f3 .dw XT_DO_STOREI ; Store a cell into flash
-
- ; MARKER saves everything up to here. Nothing beyond gets saved
- EE_MARKER:
-00007a 7a 00 .dw EE_MARKER
-
- ; default user area
- EE_INITUSER:
-00007c 00 00 .dw 0 ; USER_STATE
-00007e 00 00 .dw 0 ; USER_FOLLOWER
-000080 ff 40 .dw rstackstart ; USER_RP
-000082 af 40 .dw stackstart ; USER_SP0
-000084 af 40 .dw stackstart ; USER_SP
-
-000086 00 00 .dw 0 ; USER_HANDLER
-000088 0a 00 .dw 10 ; USER_BASE
-
-00008a b6 00 .dw XT_TX ; USER_EMIT
-00008c c4 00 .dw XT_TXQ ; USER_EMITQ
-00008e 8b 00 .dw XT_RX ; USER_KEY
-000090 a6 00 .dw XT_RXQ ; USER_KEYQ
-000092 50 fd .dw XT_SOURCETIB ; USER_SOURCE
-000094 00 00 .dw 0 ; USER_G_IN
-000096 3d fd .dw XT_REFILLTIB ; USER_REFILL
-000098 04 fa .dw XT_DEFAULT_PROMPTOK
-00009a 23 fa .dw XT_DEFAULT_PROMPTERROR
-00009c 13 fa .dw XT_DEFAULT_PROMPTREADY
-
- ; calculate baud rate error
- .equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
- .equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
- .equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
- .if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .endif
- EE_UBRRVAL:
-00009e 0c 00 .dw UBRR_VAL ; BAUDRATE
- ; 1st free address in EEPROM.
- EHERESTART:
- .cseg
-
-
-RESOURCE USE INFORMATION
-------------------------
-
-Notice:
-The register and instruction counts are symbol table hit counts,
-and hence implicitly used resources are not counted, eg, the
-'lpm' instruction without operands implicitly uses r0 and z,
-none of which are counted.
-
-x,y,z are separate entities in the symbol table and are
-counted separately from r26..r31 here.
-
-.dseg memory usage only counts static data declared with .byte
-
-"ATmega1284P" register use summary:
-r0 : 25 r1 : 5 r2 : 9 r3 : 12 r4 : 4 r5 : 1 r6 : 0 r7 : 0
-r8 : 0 r9 : 0 r10: 1 r11: 6 r12: 0 r13: 0 r14: 22 r15: 20
-r16: 78 r17: 57 r18: 52 r19: 37 r20: 13 r21: 38 r22: 11 r23: 3
-r24: 187 r25: 133 r26: 28 r27: 17 r28: 7 r29: 4 r30: 78 r31: 40
-x : 4 y : 203 z : 41
-Registers used: 29 out of 35 (82.9%)
-
-"ATmega1284P" instruction use summary:
-.lds : 0 .sts : 0 adc : 22 add : 17 adiw : 17 and : 4
-andi : 3 asr : 2 bclr : 0 bld : 0 brbc : 2 brbs : 7
-brcc : 2 brcs : 1 break : 0 breq : 6 brge : 1 brhc : 0
-brhs : 0 brid : 0 brie : 0 brlo : 1 brlt : 3 brmi : 3
-brne : 13 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
-brvs : 2 bset : 0 bst : 0 call : 2 cbi : 0 cbr : 0
-clc : 1 clh : 0 cli : 5 cln : 0 clr : 22 cls : 0
-clt : 0 clv : 0 clz : 0 com : 14 cp : 11 cpc : 10
-cpi : 2 cpse : 0 dec : 10 elpm : 16 eor : 3 fmul : 0
-fmuls : 0 fmulsu: 0 icall : 0 ijmp : 1 in : 14 inc : 3
-jmp : 8 ld : 136 ldd : 4 ldi : 27 lds : 1 lpm : 0
-lsl : 14 lsr : 2 mov : 15 movw : 65 mul : 5 muls : 1
-mulsu : 2 neg : 0 nop : 0 or : 9 ori : 1 out : 25
-pop : 45 push : 39 rcall : 47 ret : 6 reti : 1 rjmp : 102
-rol : 32 ror : 5 sbc : 9 sbci : 3 sbi : 3 sbic : 3
-sbis : 0 sbiw : 7 sbr : 0 sbrc : 4 sbrs : 3 sec : 1
-seh : 0 sei : 1 sen : 0 ser : 3 ses : 0 set : 0
-sev : 0 sez : 0 sleep : 0 spm : 2 st : 74 std : 8
-sts : 1 sub : 6 subi : 3 swap : 0 tst : 0 wdr : 0
-
-Instructions used: 70 out of 114 (61.4%)
-
-"ATmega1284P" memory use summary [bytes]:
-Segment Begin End Code Data Used Size Use%
----------------------------------------------------------------
-[.cseg] 0x000000 0x01fb7a 1908 14702 16610 131072 12.7%
-[.dseg] 0x000100 0x0001cb 0 203 203 16384 1.2%
-[.eseg] 0x000000 0x0000a0 0 160 160 4096 3.9%
-
-Assembly complete, 0 errors, 9 warnings
diff --git a/amforth-6.5/appl/template/template.map b/amforth-6.5/appl/template/template.map
deleted file mode 100644
index 77bcf21..0000000
--- a/amforth-6.5/appl/template/template.map
+++ /dev/null
@@ -1,2234 +0,0 @@
-
-AVRASM ver. 2.1.52 template.asm Sun Apr 30 20:10:14 2017
-
-
-SET DICT_COMPILER2 00000001
-SET cpu_msp430 00000000
-SET cpu_avr8 00000001
-SET USER_STATE 00000000
-SET USER_FOLLOWER 00000002
-SET USER_RP 00000004
-SET USER_SP0 00000006
-SET USER_SP 00000008
-SET USER_HANDLER 0000000a
-SET USER_BASE 0000000c
-SET USER_EMIT 0000000e
-SET USER_EMITQ 00000010
-SET USER_KEY 00000012
-SET USER_KEYQ 00000014
-SET USER_SOURCE 00000016
-SET USER_TO_IN 00000018
-SET USER_REFILL 0000001a
-SET USER_P_OK 0000001c
-SET USER_P_ERR 0000001e
-SET USER_P_RDY 00000020
-SET SYSUSERSIZE 00000022
-DEF zerol r2
-DEF zeroh r3
-DEF upl r4
-DEF uph r5
-DEF al r6
-DEF ah r7
-DEF bl r8
-DEF bh r9
-DEF mcu_boot r10
-DEF isrflag r11
-DEF temp4 r14
-DEF temp5 r15
-DEF temp0 r16
-DEF temp1 r17
-DEF temp2 r18
-DEF temp3 r19
-DEF temp6 r20
-DEF temp7 r21
-DEF tosl r24
-DEF tosh r25
-DEF wl r22
-DEF wh r23
-EQU SIGNATURE_000 0000001e
-EQU SIGNATURE_001 00000097
-EQU SIGNATURE_002 00000005
-EQU UDR1 000000ce
-EQU UBRR1L 000000cc
-EQU UBRR1H 000000cd
-EQU UCSR1C 000000ca
-EQU UCSR1B 000000c9
-EQU UCSR1A 000000c8
-EQU UDR0 000000c6
-EQU UBRR0L 000000c4
-EQU UBRR0H 000000c5
-EQU UCSR0C 000000c2
-EQU UCSR0B 000000c1
-EQU UCSR0A 000000c0
-EQU TWAMR 000000bd
-EQU TWCR 000000bc
-EQU TWDR 000000bb
-EQU TWAR 000000ba
-EQU TWSR 000000b9
-EQU TWBR 000000b8
-EQU ASSR 000000b6
-EQU OCR2B 000000b4
-EQU OCR2A 000000b3
-EQU TCNT2 000000b2
-EQU TCCR2B 000000b1
-EQU TCCR2A 000000b0
-EQU OCR3BL 0000009a
-EQU OCR3BH 0000009b
-EQU OCR3AL 00000098
-EQU OCR3AH 00000099
-EQU ICR3L 00000096
-EQU ICR3H 00000097
-EQU TCNT3L 00000094
-EQU TCNT3H 00000095
-EQU TCCR3C 00000092
-EQU TCCR3B 00000091
-EQU TCCR3A 00000090
-EQU OCR1BL 0000008a
-EQU OCR1BH 0000008b
-EQU OCR1AL 00000088
-EQU OCR1AH 00000089
-EQU ICR1L 00000086
-EQU ICR1H 00000087
-EQU TCNT1L 00000084
-EQU TCNT1H 00000085
-EQU TCCR1C 00000082
-EQU TCCR1B 00000081
-EQU TCCR1A 00000080
-EQU DIDR1 0000007f
-EQU DIDR0 0000007e
-EQU ADMUX 0000007c
-EQU ADCSRB 0000007b
-EQU ADCSRA 0000007a
-EQU ADCH 00000079
-EQU ADCL 00000078
-EQU PCMSK3 00000073
-EQU TIMSK3 00000071
-EQU TIMSK2 00000070
-EQU TIMSK1 0000006f
-EQU TIMSK0 0000006e
-EQU PCMSK2 0000006d
-EQU PCMSK1 0000006c
-EQU PCMSK0 0000006b
-EQU EICRA 00000069
-EQU PCICR 00000068
-EQU OSCCAL 00000066
-EQU PRR1 00000065
-EQU PRR0 00000064
-EQU CLKPR 00000061
-EQU WDTCSR 00000060
-EQU SREG 0000003f
-EQU SPL 0000003d
-EQU SPH 0000003e
-EQU RAMPZ 0000003b
-EQU SPMCSR 00000037
-EQU MCUCR 00000035
-EQU MCUSR 00000034
-EQU SMCR 00000033
-EQU OCDR 00000031
-EQU ACSR 00000030
-EQU SPDR 0000002e
-EQU SPSR 0000002d
-EQU SPCR 0000002c
-EQU GPIOR2 0000002b
-EQU GPIOR1 0000002a
-EQU OCR0B 00000028
-EQU OCR0A 00000027
-EQU TCNT0 00000026
-EQU TCCR0B 00000025
-EQU TCCR0A 00000024
-EQU GTCCR 00000023
-EQU EEARH 00000022
-EQU EEARL 00000021
-EQU EEDR 00000020
-EQU EECR 0000001f
-EQU GPIOR0 0000001e
-EQU EIMSK 0000001d
-EQU EIFR 0000001c
-EQU PCIFR 0000001b
-EQU TIFR3 00000018
-EQU TIFR2 00000017
-EQU TIFR1 00000016
-EQU TIFR0 00000015
-EQU PORTD 0000000b
-EQU DDRD 0000000a
-EQU PIND 00000009
-EQU PORTC 00000008
-EQU DDRC 00000007
-EQU PINC 00000006
-EQU PORTB 00000005
-EQU DDRB 00000004
-EQU PINB 00000003
-EQU PORTA 00000002
-EQU DDRA 00000001
-EQU PINA 00000000
-EQU ACME 00000006
-EQU ACIS0 00000000
-EQU ACIS1 00000001
-EQU ACIC 00000002
-EQU ACIE 00000003
-EQU ACI 00000004
-EQU ACO 00000005
-EQU ACBG 00000006
-EQU ACD 00000007
-EQU AIN0D 00000000
-EQU AIN1D 00000001
-EQU UDR0_0 00000000
-EQU UDR0_1 00000001
-EQU UDR0_2 00000002
-EQU UDR0_3 00000003
-EQU UDR0_4 00000004
-EQU UDR0_5 00000005
-EQU UDR0_6 00000006
-EQU UDR0_7 00000007
-EQU MPCM0 00000000
-EQU U2X0 00000001
-EQU UPE0 00000002
-EQU DOR0 00000003
-EQU FE0 00000004
-EQU UDRE0 00000005
-EQU TXC0 00000006
-EQU RXC0 00000007
-EQU TXB80 00000000
-EQU RXB80 00000001
-EQU UCSZ02 00000002
-EQU TXEN0 00000003
-EQU RXEN0 00000004
-EQU UDRIE0 00000005
-EQU TXCIE0 00000006
-EQU RXCIE0 00000007
-EQU UCPOL0 00000000
-EQU UCSZ00 00000001
-EQU UCPHA0 00000001
-EQU UCSZ01 00000002
-EQU UDORD0 00000002
-EQU USBS0 00000003
-EQU UPM00 00000004
-EQU UPM01 00000005
-EQU UMSEL00 00000006
-EQU UMSEL0 00000006
-EQU UMSEL01 00000007
-EQU UMSEL1 00000007
-EQU UBRR8 00000000
-EQU UBRR9 00000001
-EQU UBRR10 00000002
-EQU UBRR11 00000003
-EQU _UBRR0 00000000
-EQU _UBRR1 00000001
-EQU UBRR2 00000002
-EQU UBRR3 00000003
-EQU UBRR4 00000004
-EQU UBRR5 00000005
-EQU UBRR6 00000006
-EQU UBRR7 00000007
-EQU PORTA0 00000000
-EQU PA0 00000000
-EQU PORTA1 00000001
-EQU PA1 00000001
-EQU PORTA2 00000002
-EQU PA2 00000002
-EQU PORTA3 00000003
-EQU PA3 00000003
-EQU PORTA4 00000004
-EQU PA4 00000004
-EQU PORTA5 00000005
-EQU PA5 00000005
-EQU PORTA6 00000006
-EQU PA6 00000006
-EQU PORTA7 00000007
-EQU PA7 00000007
-EQU DDA0 00000000
-EQU DDA1 00000001
-EQU DDA2 00000002
-EQU DDA3 00000003
-EQU DDA4 00000004
-EQU DDA5 00000005
-EQU DDA6 00000006
-EQU DDA7 00000007
-EQU PINA0 00000000
-EQU PINA1 00000001
-EQU PINA2 00000002
-EQU PINA3 00000003
-EQU PINA4 00000004
-EQU PINA5 00000005
-EQU PINA6 00000006
-EQU PINA7 00000007
-EQU PORTB0 00000000
-EQU PB0 00000000
-EQU PORTB1 00000001
-EQU PB1 00000001
-EQU PORTB2 00000002
-EQU PB2 00000002
-EQU PORTB3 00000003
-EQU PB3 00000003
-EQU PORTB4 00000004
-EQU PB4 00000004
-EQU PORTB5 00000005
-EQU PB5 00000005
-EQU PORTB6 00000006
-EQU PB6 00000006
-EQU PORTB7 00000007
-EQU PB7 00000007
-EQU DDB0 00000000
-EQU DDB1 00000001
-EQU DDB2 00000002
-EQU DDB3 00000003
-EQU DDB4 00000004
-EQU DDB5 00000005
-EQU DDB6 00000006
-EQU DDB7 00000007
-EQU PINB0 00000000
-EQU PINB1 00000001
-EQU PINB2 00000002
-EQU PINB3 00000003
-EQU PINB4 00000004
-EQU PINB5 00000005
-EQU PINB6 00000006
-EQU PINB7 00000007
-EQU PORTC0 00000000
-EQU PC0 00000000
-EQU PORTC1 00000001
-EQU PC1 00000001
-EQU PORTC2 00000002
-EQU PC2 00000002
-EQU PORTC3 00000003
-EQU PC3 00000003
-EQU PORTC4 00000004
-EQU PC4 00000004
-EQU PORTC5 00000005
-EQU PC5 00000005
-EQU PORTC6 00000006
-EQU PC6 00000006
-EQU PORTC7 00000007
-EQU PC7 00000007
-EQU DDC0 00000000
-EQU DDC1 00000001
-EQU DDC2 00000002
-EQU DDC3 00000003
-EQU DDC4 00000004
-EQU DDC5 00000005
-EQU DDC6 00000006
-EQU DDC7 00000007
-EQU PINC0 00000000
-EQU PINC1 00000001
-EQU PINC2 00000002
-EQU PINC3 00000003
-EQU PINC4 00000004
-EQU PINC5 00000005
-EQU PINC6 00000006
-EQU PINC7 00000007
-EQU PORTD0 00000000
-EQU PD0 00000000
-EQU PORTD1 00000001
-EQU PD1 00000001
-EQU PORTD2 00000002
-EQU PD2 00000002
-EQU PORTD3 00000003
-EQU PD3 00000003
-EQU PORTD4 00000004
-EQU PD4 00000004
-EQU PORTD5 00000005
-EQU PD5 00000005
-EQU PORTD6 00000006
-EQU PD6 00000006
-EQU PORTD7 00000007
-EQU PD7 00000007
-EQU DDD0 00000000
-EQU DDD1 00000001
-EQU DDD2 00000002
-EQU DDD3 00000003
-EQU DDD4 00000004
-EQU DDD5 00000005
-EQU DDD6 00000006
-EQU DDD7 00000007
-EQU PIND0 00000000
-EQU PIND1 00000001
-EQU PIND2 00000002
-EQU PIND3 00000003
-EQU PIND4 00000004
-EQU PIND5 00000005
-EQU PIND6 00000006
-EQU PIND7 00000007
-EQU TOIE0 00000000
-EQU OCIE0A 00000001
-EQU OCIE0B 00000002
-EQU TOV0 00000000
-EQU OCF0A 00000001
-EQU OCF0B 00000002
-EQU WGM00 00000000
-EQU WGM01 00000001
-EQU COM0B0 00000004
-EQU COM0B1 00000005
-EQU COM0A0 00000006
-EQU COM0A1 00000007
-EQU CS00 00000000
-EQU CS01 00000001
-EQU CS02 00000002
-EQU WGM02 00000003
-EQU FOC0B 00000006
-EQU FOC0A 00000007
-EQU TCNT0_0 00000000
-EQU TCNT0_1 00000001
-EQU TCNT0_2 00000002
-EQU TCNT0_3 00000003
-EQU TCNT0_4 00000004
-EQU TCNT0_5 00000005
-EQU TCNT0_6 00000006
-EQU TCNT0_7 00000007
-EQU OCR0A_0 00000000
-EQU OCR0A_1 00000001
-EQU OCR0A_2 00000002
-EQU OCR0A_3 00000003
-EQU OCR0A_4 00000004
-EQU OCR0A_5 00000005
-EQU OCR0A_6 00000006
-EQU OCR0A_7 00000007
-EQU OCR0B_0 00000000
-EQU OCR0B_1 00000001
-EQU OCR0B_2 00000002
-EQU OCR0B_3 00000003
-EQU OCR0B_4 00000004
-EQU OCR0B_5 00000005
-EQU OCR0B_6 00000006
-EQU OCR0B_7 00000007
-EQU PSRSYNC 00000000
-EQU PSR10 00000000
-EQU TSM 00000007
-EQU TOIE1 00000000
-EQU OCIE1A 00000001
-EQU OCIE1B 00000002
-EQU ICIE1 00000005
-EQU TOV1 00000000
-EQU OCF1A 00000001
-EQU OCF1B 00000002
-EQU ICF1 00000005
-EQU WGM10 00000000
-EQU PWM10 00000000
-EQU WGM11 00000001
-EQU PWM11 00000001
-EQU COM1B0 00000004
-EQU COM1B1 00000005
-EQU COM1A0 00000006
-EQU COM1A1 00000007
-EQU CS10 00000000
-EQU CS11 00000001
-EQU CS12 00000002
-EQU WGM12 00000003
-EQU CTC1 00000003
-EQU WGM13 00000004
-EQU ICES1 00000006
-EQU ICNC1 00000007
-EQU FOC1B 00000006
-EQU FOC1A 00000007
-EQU TOIE2 00000000
-EQU TOIE2A 00000000
-EQU OCIE2A 00000001
-EQU OCIE2B 00000002
-EQU TOV2 00000000
-EQU OCF2A 00000001
-EQU OCF2B 00000002
-EQU WGM20 00000000
-EQU WGM21 00000001
-EQU COM2B0 00000004
-EQU COM2B1 00000005
-EQU COM2A0 00000006
-EQU COM2A1 00000007
-EQU CS20 00000000
-EQU CS21 00000001
-EQU CS22 00000002
-EQU WGM22 00000003
-EQU FOC2B 00000006
-EQU FOC2A 00000007
-EQU TCNT2_0 00000000
-EQU TCNT2_1 00000001
-EQU TCNT2_2 00000002
-EQU TCNT2_3 00000003
-EQU TCNT2_4 00000004
-EQU TCNT2_5 00000005
-EQU TCNT2_6 00000006
-EQU TCNT2_7 00000007
-EQU OCR2A_0 00000000
-EQU OCR2A_1 00000001
-EQU OCR2A_2 00000002
-EQU OCR2A_3 00000003
-EQU OCR2A_4 00000004
-EQU OCR2A_5 00000005
-EQU OCR2A_6 00000006
-EQU OCR2A_7 00000007
-EQU OCR2B_0 00000000
-EQU OCR2B_1 00000001
-EQU OCR2B_2 00000002
-EQU OCR2B_3 00000003
-EQU OCR2B_4 00000004
-EQU OCR2B_5 00000005
-EQU OCR2B_6 00000006
-EQU OCR2B_7 00000007
-EQU TCR2BUB 00000000
-EQU TCR2AUB 00000001
-EQU OCR2BUB 00000002
-EQU OCR2AUB 00000003
-EQU TCN2UB 00000004
-EQU AS2 00000005
-EQU EXCLK 00000006
-EQU PSRASY 00000001
-EQU PSR2 00000001
-EQU TOIE3 00000000
-EQU OCIE3A 00000001
-EQU OCIE3B 00000002
-EQU ICIE3 00000005
-EQU TOV3 00000000
-EQU OCF3A 00000001
-EQU OCF3B 00000002
-EQU ICF3 00000005
-EQU WGM30 00000000
-EQU WGM31 00000001
-EQU COM3B0 00000004
-EQU COM3B1 00000005
-EQU COM3A0 00000006
-EQU COM3A1 00000007
-EQU CS30 00000000
-EQU CS31 00000001
-EQU CS32 00000002
-EQU WGM32 00000003
-EQU WGM33 00000004
-EQU ICES3 00000006
-EQU ICNC3 00000007
-EQU FOC3B 00000006
-EQU FOC3A 00000007
-EQU OCR3AH0 00000000
-EQU OCR3AH1 00000001
-EQU OCR3AH2 00000002
-EQU OCR3AH3 00000003
-EQU OCR3AH4 00000004
-EQU OCR3AH5 00000005
-EQU OCR3AH6 00000006
-EQU OCR3AH7 00000007
-EQU OCR3AL0 00000000
-EQU OCR3AL1 00000001
-EQU OCR3AL2 00000002
-EQU OCR3AL3 00000003
-EQU OCR3AL4 00000004
-EQU OCR3AL5 00000005
-EQU OCR3AL6 00000006
-EQU OCR3AL7 00000007
-EQU SPMEN 00000000
-EQU PGERS 00000001
-EQU PGWRT 00000002
-EQU BLBSET 00000003
-EQU RWWSRE 00000004
-EQU SIGRD 00000005
-EQU RWWSB 00000006
-EQU SPMIE 00000007
-EQU ISC00 00000000
-EQU ISC01 00000001
-EQU ISC10 00000002
-EQU ISC11 00000003
-EQU ISC20 00000004
-EQU ISC21 00000005
-EQU INT0 00000000
-EQU INT1 00000001
-EQU INT2 00000002
-EQU INTF0 00000000
-EQU INTF1 00000001
-EQU INTF2 00000002
-EQU PCIE0 00000000
-EQU PCIE1 00000001
-EQU PCIE2 00000002
-EQU PCIE3 00000003
-EQU PCIF0 00000000
-EQU PCIF1 00000001
-EQU PCIF2 00000002
-EQU PCIF3 00000003
-EQU PCINT24 00000000
-EQU PCINT25 00000001
-EQU PCINT26 00000002
-EQU PCINT27 00000003
-EQU PCINT28 00000004
-EQU PCINT29 00000005
-EQU PCINT30 00000006
-EQU PCINT31 00000007
-EQU PCINT16 00000000
-EQU PCINT17 00000001
-EQU PCINT18 00000002
-EQU PCINT19 00000003
-EQU PCINT20 00000004
-EQU PCINT21 00000005
-EQU PCINT22 00000006
-EQU PCINT23 00000007
-EQU PCINT8 00000000
-EQU PCINT9 00000001
-EQU PCINT10 00000002
-EQU PCINT11 00000003
-EQU PCINT12 00000004
-EQU PCINT13 00000005
-EQU PCINT14 00000006
-EQU PCINT15 00000007
-EQU PCINT0 00000000
-EQU PCINT1 00000001
-EQU PCINT2 00000002
-EQU PCINT3 00000003
-EQU PCINT4 00000004
-EQU PCINT5 00000005
-EQU PCINT6 00000006
-EQU PCINT7 00000007
-EQU MUX0 00000000
-EQU MUX1 00000001
-EQU MUX2 00000002
-EQU MUX3 00000003
-EQU MUX4 00000004
-EQU ADLAR 00000005
-EQU REFS0 00000006
-EQU REFS1 00000007
-EQU ADPS0 00000000
-EQU ADPS1 00000001
-EQU ADPS2 00000002
-EQU ADIE 00000003
-EQU ADIF 00000004
-EQU ADATE 00000005
-EQU ADSC 00000006
-EQU ADEN 00000007
-EQU ADTS0 00000000
-EQU ADTS1 00000001
-EQU ADTS2 00000002
-EQU ADCH0 00000000
-EQU ADCH1 00000001
-EQU ADCH2 00000002
-EQU ADCH3 00000003
-EQU ADCH4 00000004
-EQU ADCH5 00000005
-EQU ADCH6 00000006
-EQU ADCH7 00000007
-EQU ADCL0 00000000
-EQU ADCL1 00000001
-EQU ADCL2 00000002
-EQU ADCL3 00000003
-EQU ADCL4 00000004
-EQU ADCL5 00000005
-EQU ADCL6 00000006
-EQU ADCL7 00000007
-EQU ADC0D 00000000
-EQU ADC1D 00000001
-EQU ADC2D 00000002
-EQU ADC3D 00000003
-EQU ADC4D 00000004
-EQU ADC5D 00000005
-EQU ADC6D 00000006
-EQU ADC7D 00000007
-EQU OCDR0 00000000
-EQU OCDR1 00000001
-EQU OCDR2 00000002
-EQU OCDR3 00000003
-EQU OCDR4 00000004
-EQU OCDR5 00000005
-EQU OCDR6 00000006
-EQU OCDR7 00000007
-EQU IDRD 00000007
-EQU JTD 00000007
-EQU JTRF 00000004
-EQU EEAR8 00000000
-EQU EEAR9 00000001
-EQU EEAR10 00000002
-EQU EEAR11 00000003
-EQU EEAR0 00000000
-EQU EEAR1 00000001
-EQU EEAR2 00000002
-EQU EEAR3 00000003
-EQU EEAR4 00000004
-EQU EEAR5 00000005
-EQU EEAR6 00000006
-EQU EEAR7 00000007
-EQU EEDR0 00000000
-EQU EEDR1 00000001
-EQU EEDR2 00000002
-EQU EEDR3 00000003
-EQU EEDR4 00000004
-EQU EEDR5 00000005
-EQU EEDR6 00000006
-EQU EEDR7 00000007
-EQU EERE 00000000
-EQU EEPE 00000001
-EQU EEMPE 00000002
-EQU EERIE 00000003
-EQU EEPM0 00000004
-EQU EEPM1 00000005
-EQU TWAM0 00000001
-EQU TWAMR0 00000001
-EQU TWAM1 00000002
-EQU TWAMR1 00000002
-EQU TWAM2 00000003
-EQU TWAMR2 00000003
-EQU TWAM3 00000004
-EQU TWAMR3 00000004
-EQU TWAM4 00000005
-EQU TWAMR4 00000005
-EQU TWAM5 00000006
-EQU TWAMR5 00000006
-EQU TWAM6 00000007
-EQU TWAMR6 00000007
-EQU TWBR0 00000000
-EQU TWBR1 00000001
-EQU TWBR2 00000002
-EQU TWBR3 00000003
-EQU TWBR4 00000004
-EQU TWBR5 00000005
-EQU TWBR6 00000006
-EQU TWBR7 00000007
-EQU TWIE 00000000
-EQU TWEN 00000002
-EQU TWWC 00000003
-EQU TWSTO 00000004
-EQU TWSTA 00000005
-EQU TWEA 00000006
-EQU TWINT 00000007
-EQU TWPS0 00000000
-EQU TWPS1 00000001
-EQU TWS3 00000003
-EQU TWS4 00000004
-EQU TWS5 00000005
-EQU TWS6 00000006
-EQU TWS7 00000007
-EQU TWD0 00000000
-EQU TWD1 00000001
-EQU TWD2 00000002
-EQU TWD3 00000003
-EQU TWD4 00000004
-EQU TWD5 00000005
-EQU TWD6 00000006
-EQU TWD7 00000007
-EQU TWGCE 00000000
-EQU TWA0 00000001
-EQU TWA1 00000002
-EQU TWA2 00000003
-EQU TWA3 00000004
-EQU TWA4 00000005
-EQU TWA5 00000006
-EQU TWA6 00000007
-EQU UDR1_0 00000000
-EQU UDR1_1 00000001
-EQU UDR1_2 00000002
-EQU UDR1_3 00000003
-EQU UDR1_4 00000004
-EQU UDR1_5 00000005
-EQU UDR1_6 00000006
-EQU UDR1_7 00000007
-EQU MPCM1 00000000
-EQU U2X1 00000001
-EQU UPE1 00000002
-EQU DOR1 00000003
-EQU FE1 00000004
-EQU UDRE1 00000005
-EQU TXC1 00000006
-EQU RXC1 00000007
-EQU TXB81 00000000
-EQU RXB81 00000001
-EQU UCSZ12 00000002
-EQU TXEN1 00000003
-EQU RXEN1 00000004
-EQU UDRIE1 00000005
-EQU TXCIE1 00000006
-EQU RXCIE1 00000007
-EQU UCPOL1 00000000
-EQU UCSZ10 00000001
-EQU UCPHA1 00000001
-EQU UCSZ11 00000002
-EQU UDORD1 00000002
-EQU USBS1 00000003
-EQU UPM10 00000004
-EQU UPM11 00000005
-EQU UMSEL10 00000006
-EQU UMSEL11 00000007
-EQU UBRR_8 00000000
-EQU UBRR_9 00000001
-EQU UBRR_10 00000002
-EQU UBRR_11 00000003
-EQU UBRR_0 00000000
-EQU UBRR_1 00000001
-EQU UBRR_2 00000002
-EQU UBRR_3 00000003
-EQU UBRR_4 00000004
-EQU UBRR_5 00000005
-EQU UBRR_6 00000006
-EQU UBRR_7 00000007
-EQU SPDR0 00000000
-EQU SPDR1 00000001
-EQU SPDR2 00000002
-EQU SPDR3 00000003
-EQU SPDR4 00000004
-EQU SPDR5 00000005
-EQU SPDR6 00000006
-EQU SPDR7 00000007
-EQU SPI2X 00000000
-EQU WCOL 00000006
-EQU SPIF 00000007
-EQU SPR0 00000000
-EQU SPR1 00000001
-EQU CPHA 00000002
-EQU CPOL 00000003
-EQU MSTR 00000004
-EQU DORD 00000005
-EQU SPE 00000006
-EQU SPIE 00000007
-EQU WDP0 00000000
-EQU WDP1 00000001
-EQU WDP2 00000002
-EQU WDE 00000003
-EQU WDCE 00000004
-EQU WDP3 00000005
-EQU WDIE 00000006
-EQU WDIF 00000007
-EQU SREG_C 00000000
-EQU SREG_Z 00000001
-EQU SREG_N 00000002
-EQU SREG_V 00000003
-EQU SREG_S 00000004
-EQU SREG_H 00000005
-EQU SREG_T 00000006
-EQU SREG_I 00000007
-EQU IVCE 00000000
-EQU IVSEL 00000001
-EQU PUD 00000004
-EQU BODSE 00000005
-EQU BODS 00000006
-EQU PORF 00000000
-EQU EXTRF 00000001
-EQU BORF 00000002
-EQU WDRF 00000003
-EQU CAL0 00000000
-EQU CAL1 00000001
-EQU CAL2 00000002
-EQU CAL3 00000003
-EQU CAL4 00000004
-EQU CAL5 00000005
-EQU CAL6 00000006
-EQU CAL7 00000007
-EQU CLKPS0 00000000
-EQU CLKPS1 00000001
-EQU CLKPS2 00000002
-EQU CLKPS3 00000003
-EQU CLKPCE 00000007
-EQU SE 00000000
-EQU SM0 00000001
-EQU SM1 00000002
-EQU SM2 00000003
-EQU RAMPZ0 00000000
-EQU GPIOR20 00000000
-EQU GPIOR21 00000001
-EQU GPIOR22 00000002
-EQU GPIOR23 00000003
-EQU GPIOR24 00000004
-EQU GPIOR25 00000005
-EQU GPIOR26 00000006
-EQU GPIOR27 00000007
-EQU GPIOR10 00000000
-EQU GPIOR11 00000001
-EQU GPIOR12 00000002
-EQU GPIOR13 00000003
-EQU GPIOR14 00000004
-EQU GPIOR15 00000005
-EQU GPIOR16 00000006
-EQU GPIOR17 00000007
-EQU GPIOR00 00000000
-EQU GPIOR01 00000001
-EQU GPIOR02 00000002
-EQU GPIOR03 00000003
-EQU GPIOR04 00000004
-EQU GPIOR05 00000005
-EQU GPIOR06 00000006
-EQU GPIOR07 00000007
-EQU PRADC 00000000
-EQU PRUSART0 00000001
-EQU PRSPI 00000002
-EQU PRTIM1 00000003
-EQU PRUSART1 00000004
-EQU PRTIM0 00000005
-EQU PRTIM2 00000006
-EQU PRTWI 00000007
-EQU PRTIM3 00000000
-EQU LB1 00000000
-EQU LB2 00000001
-EQU BLB01 00000002
-EQU BLB02 00000003
-EQU BLB11 00000004
-EQU BLB12 00000005
-EQU CKSEL0 00000000
-EQU CKSEL1 00000001
-EQU CKSEL2 00000002
-EQU CKSEL3 00000003
-EQU SUT0 00000004
-EQU SUT1 00000005
-EQU CKOUT 00000006
-EQU CKDIV8 00000007
-EQU BOOTRST 00000000
-EQU BOOTSZ0 00000001
-EQU BOOTSZ1 00000002
-EQU EESAVE 00000003
-EQU WDTON 00000004
-EQU SPIEN 00000005
-EQU JTAGEN 00000006
-EQU OCDEN 00000007
-EQU BODLEVEL0 00000000
-EQU BODLEVEL1 00000001
-EQU BODLEVEL2 00000002
-DEF XH r27
-DEF XL r26
-DEF YH r29
-DEF YL r28
-DEF ZH r31
-DEF ZL r30
-EQU FLASHEND 0000ffff
-EQU IOEND 000000ff
-EQU SRAM_START 00000100
-EQU SRAM_SIZE 00004000
-EQU RAMEND 000040ff
-EQU XRAMEND 00000000
-EQU E2END 00000fff
-EQU EEPROMEND 00000fff
-EQU EEADRBITS 0000000c
-EQU NRWW_START_ADDR 0000f000
-EQU NRWW_STOP_ADDR 0000ffff
-EQU RWW_START_ADDR 00000000
-EQU RWW_STOP_ADDR 0000efff
-EQU PAGESIZE 00000080
-EQU FIRSTBOOTSTART 0000fe00
-EQU SECONDBOOTSTART 0000fc00
-EQU THIRDBOOTSTART 0000f800
-EQU FOURTHBOOTSTART 0000f000
-EQU SMALLBOOTSTART 0000fe00
-EQU LARGEBOOTSTART 0000f000
-EQU INT0addr 00000002
-EQU INT1addr 00000004
-EQU INT2addr 00000006
-EQU PCI0addr 00000008
-EQU PCI1addr 0000000a
-EQU PCI2addr 0000000c
-EQU PCI3addr 0000000e
-EQU WDTaddr 00000010
-EQU OC2Aaddr 00000012
-EQU OC2Baddr 00000014
-EQU OVF2addr 00000016
-EQU ICP1addr 00000018
-EQU OC1Aaddr 0000001a
-EQU OC1Baddr 0000001c
-EQU OVF1addr 0000001e
-EQU OC0Aaddr 00000020
-EQU OC0Baddr 00000022
-EQU OVF0addr 00000024
-EQU SPIaddr 00000026
-EQU URXC0addr 00000028
-EQU UDRE0addr 0000002a
-EQU UTXC0addr 0000002c
-EQU ACIaddr 0000002e
-EQU ADCCaddr 00000030
-EQU ERDYaddr 00000032
-EQU TWIaddr 00000034
-EQU SPMRaddr 00000036
-EQU URXC1addr 00000038
-EQU UDRE1addr 0000003a
-EQU UTXC1addr 0000003c
-EQU ICP3addr 0000003e
-EQU OC3Aaddr 00000040
-EQU OC3Baddr 00000042
-EQU OVF3addr 00000044
-EQU INT_VECTORS_SIZE 00000046
-EQU ramstart 00000100
-EQU CELLSIZE 00000002
-SET WANT_ANALOG_COMPARATOR 00000000
-SET WANT_USART0 00000000
-SET WANT_PORTA 00000000
-SET WANT_PORTB 00000000
-SET WANT_PORTC 00000000
-SET WANT_PORTD 00000000
-SET WANT_TIMER_COUNTER_0 00000000
-SET WANT_TIMER_COUNTER_1 00000000
-SET WANT_TIMER_COUNTER_2 00000000
-SET WANT_TIMER_COUNTER_3 00000000
-SET WANT_BOOT_LOAD 00000000
-SET WANT_EXTERNAL_INTERRUPT 00000000
-SET WANT_AD_CONVERTER 00000000
-SET WANT_JTAG 00000000
-SET WANT_EEPROM 00000000
-SET WANT_TWI 00000000
-SET WANT_USART1 00000000
-SET WANT_SPI 00000000
-SET WANT_WATCHDOG 00000000
-SET WANT_CPU 00000000
-EQU intvecsize 00000002
-EQU pclen 00000002
-CSEG isr 000000f0
-EQU INTVECTORS 00000023
-CSEG mcu_info 00000045
-CSEG mcu_ramsize 00000045
-CSEG mcu_eepromsize 00000046
-CSEG mcu_maxdp 00000047
-CSEG mcu_numints 00000048
-CSEG mcu_name 00000049
-SET codestart 00000050
-SET WANT_INTERRUPTS 00000001
-SET WANT_INTERRUPT_COUNTERS 00000000
-SET WANT_ISR_RX 00000001
-SET WANT_IGNORECASE 00000001
-SET WANT_UNIFIED 00000000
-SET TIB_SIZE 0000005a
-SET APPUSERSIZE 0000000a
-SET rstackstart 000040ff
-SET stackstart 000040af
-SET NUMWORDLISTS 00000008
-SET NUMRECOGNIZERS 00000004
-SET BAUD 00009600
-SET BAUD_MAXERROR 0000000a
-SET VE_HEAD 0000fdb8
-SET VE_ENVHEAD 0000f54c
-SET AMFORTH_RO_SEG 0000f000
-EQU F_CPU 007a1200
-EQU BAUDRATE_LOW 000000c4
-EQU BAUDRATE_HIGH 000000c5
-EQU USART_C 000000c2
-EQU USART_B 000000c1
-EQU USART_A 000000c0
-EQU USART_DATA 000000c6
-EQU URXCaddr 00000028
-EQU UDREaddr 0000002a
-EQU bm_USART_RXRD 00000080
-EQU bm_USART_TXRD 00000020
-EQU bm_ENABLE_TX 00000008
-EQU bm_ENABLE_RX 00000010
-EQU bm_ENABLE_INT_RX 00000080
-EQU bm_ENABLE_INT_TX 00000020
-EQU bm_USARTC_en 00000000
-EQU bm_ASYNC 00000000
-EQU bm_SYNC 00000040
-EQU bm_NO_PARITY 00000000
-EQU bm_EVEN_PARITY 00000020
-EQU bm_ODD_PARITY 00000030
-EQU bm_1STOPBIT 00000000
-EQU bm_2STOPBIT 00000008
-EQU bm_5BIT 00000000
-EQU bm_6BIT 00000002
-EQU bm_7BIT 00000004
-EQU bm_8BIT 00000006
-SET USART_C_VALUE 00000006
-SET USART_B_VALUE 00000098
-EQU usart_rx_size 00000010
-EQU usart_rx_mask 0000000f
-DSEG usart_rx_data 00000100
-DSEG usart_rx_in 00000110
-DSEG usart_rx_out 00000111
-CSEG VE_TO_RXBUF 00000050
-CSEG XT_TO_RXBUF 00000056
-CSEG PFA_rx_tobuf 00000057
-CSEG DO_NEXT 0000f004
-CSEG VE_ISR_RX 00000067
-CSEG XT_ISR_RX 0000006c
-CSEG DO_COLON 0000f000
-CSEG usart_rx_isr 0000006d
-CSEG XT_DOLITERAL 0000f045
-CSEG XT_CFETCH 0000f0a9
-CSEG XT_DUP 0000f0c2
-CSEG XT_EQUAL 0000fdaa
-CSEG XT_DOCONDBRANCH 0000f03e
-CSEG usart_rx_isr1 00000077
-CSEG XT_COLD 0000fa73
-CSEG XT_EXIT 0000f025
-CSEG XT_USART_INIT_RX_BUFFER 00000079
-CSEG PFA_USART_INIT_RX_BUFFER 0000007a
-CSEG XT_INTSTORE 0000f4a1
-CSEG XT_ZERO 0000f165
-CSEG XT_FILL 0000f4e9
-CSEG VE_RX_BUFFER 00000086
-CSEG XT_RX_BUFFER 0000008b
-CSEG PFA_RX_BUFFER 0000008c
-CSEG XT_RXQ_BUFFER 000000a6
-CSEG XT_PLUS 0000f1ae
-CSEG XT_SWAP 0000f0d5
-CSEG XT_1PLUS 0000f240
-CSEG XT_AND 0000f224
-CSEG XT_CSTORE 0000f09e
-CSEG VE_RXQ_BUFFER 000000a0
-CSEG PFA_RXQ_BUFFER 000000a7
-CSEG XT_PAUSE 0000fa6b
-CSEG XT_NOTEQUAL 0000f124
-SET XT_RX 0000008b
-SET XT_RXQ 000000a6
-SET XT_USART_INIT_RX 00000079
-CSEG VE_TX_POLL 000000b0
-CSEG XT_TX_POLL 000000b6
-CSEG PFA_TX_POLL 000000b7
-CSEG XT_TXQ_POLL 000000c4
-CSEG VE_TXQ_POLL 000000be
-CSEG PFA_TXQ_POLL 000000c5
-SET XT_TX 000000b6
-SET XT_TXQ 000000c4
-SET XT_USART_INIT_TX 00000000
-CSEG VE_UBRR 000000cd
-CSEG XT_UBRR 000000d1
-CSEG PFA_DOVALUE1 0000f080
-CSEG PFA_UBRR 000000d2
-ESEG EE_UBRRVAL 0000009e
-CSEG XT_EDEFERFETCH 0000fbce
-CSEG XT_EDEFERSTORE 0000fbd8
-CSEG VE_USART 000000d5
-CSEG XT_USART 000000da
-CSEG PFA_USART 000000db
-CSEG XT_BYTESWAP 0000f30a
-SET AMFORTH_NRWW_SIZE 00001ffe
-SET corepc 000000f0
-CSEG PFA_COLD 0000fa74
-ESEG intvec 00000000
-DSEG intcnt 00000112
-CSEG VE_MPLUS 00000107
-CSEG XT_MPLUS 0000010a
-CSEG PFA_MPLUS 0000010b
-CSEG XT_S2D 0000fd92
-CSEG XT_DPLUS 0000f42f
-CSEG VE_UDSTAR 0000010e
-CSEG XT_UDSTAR 00000112
-CSEG PFA_UDSTAR 00000113
-CSEG XT_TO_R 0000f110
-CSEG XT_UMSTAR 0000f1f1
-CSEG XT_DROP 0000f0ea
-CSEG XT_R_FROM 0000f107
-CSEG XT_ROT 0000f0f2
-CSEG VE_UMAX 0000011d
-CSEG XT_UMAX 00000121
-CSEG PFA_UMAX 00000122
-CSEG XT_2DUP 0000f57f
-CSEG XT_ULESS 0000f16d
-CSEG UMAX1 00000127
-CSEG VE_UMIN 00000129
-CSEG XT_UMIN 0000012d
-CSEG PFA_UMIN 0000012e
-CSEG XT_UGREATER 0000f178
-CSEG UMIN1 00000133
-CSEG XT_IMMEDIATEQ 00000135
-CSEG PFA_IMMEDIATEQ 00000136
-CSEG XT_ZEROEQUAL 0000f12b
-CSEG IMMEDIATEQ1 0000013e
-CSEG XT_ONE 0000fdb1
-CSEG XT_TRUE 0000f15c
-CSEG VE_NAME2FLAGS 00000140
-CSEG XT_NAME2FLAGS 00000147
-CSEG PFA_NAME2FLAGS 00000148
-CSEG XT_FETCHI 0000f3e2
-CSEG VE_NEWEST 0000014d
-CSEG XT_NEWEST 00000152
-CSEG PFA_DOVARIABLE 0000f053
-CSEG PFA_NEWEST 00000153
-DSEG ram_newest 00000135
-CSEG VE_LATEST 00000154
-CSEG XT_LATEST 00000159
-CSEG PFA_LATEST 0000015a
-DSEG ram_latest 00000139
-CSEG VE_DOCREATE 0000015b
-CSEG XT_DOCREATE 00000161
-CSEG PFA_DOCREATE 00000162
-CSEG XT_PARSENAME 0000f9ce
-CSEG XT_WLSCOPE 000002b8
-CSEG XT_CELLPLUS 0000f578
-CSEG XT_STORE 0000f092
-CSEG XT_HEADER 0000029d
-CSEG VE_BACKSLASH 0000016c
-CSEG XT_BACKSLASH 0000016f
-CSEG PFA_BACKSLASH 00000170
-CSEG XT_SOURCE 0000f9b5
-CSEG XT_NIP 0000f101
-CSEG XT_TO_IN 0000f598
-CSEG VE_LPAREN 00000175
-CSEG XT_LPAREN 00000178
-CSEG PFA_LPAREN 00000179
-CSEG XT_PARSE 0000f9a1
-CSEG XT_2DROP 0000f588
-CSEG VE_COMPILE 0000017e
-CSEG XT_COMPILE 00000184
-CSEG PFA_COMPILE 00000185
-CSEG XT_ICELLPLUS 0000fbc5
-CSEG XT_COMMA 0000018f
-CSEG VE_COMMA 0000018c
-CSEG PFA_COMMA 00000190
-CSEG XT_DP 0000f5c8
-CSEG XT_STOREI 0000f384
-CSEG XT_DOTO 0000fbb3
-CSEG PFA_DP 0000f5c9
-CSEG VE_BRACKETTICK 00000197
-CSEG XT_BRACKETTICK 0000019b
-CSEG PFA_BRACKETTICK 0000019c
-CSEG XT_TICK 0000f824
-CSEG XT_LITERAL 000001a5
-CSEG VE_LITERAL 0000019f
-CSEG PFA_LITERAL 000001a6
-CSEG VE_SLITERAL 000001aa
-CSEG XT_SLITERAL 000001b0
-CSEG PFA_SLITERAL 000001b1
-CSEG XT_DOSLITERAL 0000f787
-CSEG XT_SCOMMA 0000f795
-CSEG XT_GMARK 000001b5
-CSEG PFA_GMARK 000001b6
-CSEG XT_GRESOLVE 000001ba
-CSEG PFA_GRESOLVE 000001bb
-CSEG XT_QSTACK 0000fb71
-CSEG XT_LMARK 000001c0
-CSEG PFA_LMARK 000001c1
-CSEG XT_LRESOLVE 000001c3
-CSEG PFA_LRESOLVE 000001c4
-CSEG VE_AHEAD 000001c7
-CSEG XT_AHEAD 000001cc
-CSEG PFA_AHEAD 000001cd
-CSEG XT_DOBRANCH 0000f034
-CSEG VE_IF 000001d1
-CSEG XT_IF 000001d4
-CSEG PFA_IF 000001d5
-CSEG VE_ELSE 000001d9
-CSEG XT_ELSE 000001dd
-CSEG PFA_ELSE 000001de
-CSEG VE_THEN 000001e4
-CSEG XT_THEN 000001e8
-CSEG PFA_THEN 000001e9
-CSEG VE_BEGIN 000001eb
-CSEG XT_BEGIN 000001f0
-CSEG PFA_BEGIN 000001f1
-CSEG VE_WHILE 000001f3
-CSEG XT_WHILE 000001f8
-CSEG PFA_WHILE 000001f9
-CSEG VE_REPEAT 000001fc
-CSEG XT_REPEAT 00000201
-CSEG PFA_REPEAT 00000202
-CSEG XT_AGAIN 00000215
-CSEG VE_UNTIL 00000205
-CSEG XT_UNTIL 0000020a
-CSEG PFA_UNTIL 0000020b
-CSEG VE_AGAIN 00000210
-CSEG PFA_AGAIN 00000216
-CSEG VE_DO 0000021a
-CSEG XT_DO 0000021d
-CSEG PFA_DO 0000021e
-CSEG XT_DODO 0000f2ac
-CSEG XT_TO_L 00000278
-CSEG VE_LOOP 00000224
-CSEG XT_LOOP 00000228
-CSEG PFA_LOOP 00000229
-CSEG XT_DOLOOP 0000f2da
-CSEG XT_ENDLOOP 0000025f
-CSEG VE_PLUSLOOP 0000022d
-CSEG XT_PLUSLOOP 00000232
-CSEG PFA_PLUSLOOP 00000233
-CSEG XT_DOPLUSLOOP 0000f2cb
-CSEG VE_LEAVE 00000237
-CSEG XT_LEAVE 0000023c
-CSEG PFA_LEAVE 0000023d
-CSEG XT_UNLOOP 0000f2e5
-CSEG VE_QDO 00000242
-CSEG XT_QDO 00000246
-CSEG PFA_QDO 00000247
-CSEG XT_QDOCHECK 0000024e
-CSEG PFA_QDOCHECK 0000024f
-CSEG PFA_QDOCHECK1 00000256
-CSEG XT_INVERT 0000f20e
-CSEG VE_ENDLOOP 00000259
-CSEG PFA_ENDLOOP 00000260
-CSEG LOOP1 00000261
-CSEG XT_L_FROM 0000026c
-CSEG XT_QDUP 0000f0ca
-CSEG LOOP2 00000268
-CSEG VE_L_FROM 00000269
-CSEG PFA_L_FROM 0000026d
-CSEG XT_LP 0000028b
-CSEG XT_FETCH 0000f08a
-CSEG XT_PLUSSTORE 0000f276
-CSEG VE_TO_L 00000275
-CSEG PFA_TO_L 00000279
-CSEG XT_TWO 0000fdb6
-CSEG VE_LP0 00000280
-CSEG XT_LP0 00000284
-CSEG PFA_LP0 00000285
-ESEG CFG_LP0 00000052
-CSEG VE_LP 00000288
-CSEG PFA_LP 0000028c
-DSEG ram_lp 0000013b
-CSEG VE_CREATE 0000028d
-CSEG XT_CREATE 00000292
-CSEG PFA_CREATE 00000293
-CSEG XT_REVEAL 000002c1
-CSEG PFA_DOCONSTANT 0000f060
-CSEG VE_HEADER 00000298
-CSEG PFA_HEADER 0000029e
-CSEG XT_GREATERZERO 0000f139
-CSEG PFA_HEADER1 000002af
-CSEG XT_OR 0000f22d
-CSEG XT_DOSCOMMA 0000f799
-CSEG XT_FETCHE 0000f370
-CSEG XT_THROW 0000f85b
-CSEG VE_WLSCOPE 000002b2
-CSEG PFA_DODEFER1 0000fc2d
-CSEG PFA_WLSCOPE 000002b9
-ESEG CFG_WLSCOPE 0000004e
-CSEG VE_REVEAL 000002bc
-CSEG PFA_REVEAL 000002c2
-CSEG REVEAL1 000002cc
-CSEG XT_STOREE 0000f34c
-CSEG VE_DOES 000002cd
-CSEG XT_DOES 000002d2
-CSEG PFA_DOES 000002d3
-CSEG XT_DODOES 000002e5
-CSEG DO_DODOES 000002da
-CSEG PFA_DODOES 000002e6
-CSEG XT_NFA2CFA 0000fc98
-CSEG VE_COLON 000002ee
-CSEG XT_COLON 000002f1
-CSEG PFA_COLON 000002f2
-CSEG XT_COLONNONAME 000002fc
-CSEG VE_COLONNONAME 000002f6
-CSEG PFA_COLONNONAME 000002fd
-CSEG XT_RBRACKET 00000311
-CSEG VE_SEMICOLON 00000305
-CSEG XT_SEMICOLON 00000308
-CSEG PFA_SEMICOLON 00000309
-CSEG XT_LBRACKET 00000319
-CSEG VE_RBRACKET 0000030e
-CSEG PFA_RBRACKET 00000312
-CSEG XT_STATE 0000f565
-CSEG VE_LBRACKET 00000316
-CSEG PFA_LBRACKET 0000031a
-CSEG VE_VARIABLE 0000031e
-CSEG XT_VARIABLE 00000324
-CSEG PFA_VARIABLE 00000325
-CSEG XT_HERE 0000f5d9
-CSEG XT_CONSTANT 00000330
-CSEG XT_ALLOT 0000f5e2
-CSEG VE_CONSTANT 0000032a
-CSEG PFA_CONSTANT 00000331
-CSEG VE_USER 00000337
-CSEG XT_USER 0000033b
-CSEG PFA_USER 0000033c
-CSEG PFA_DOUSER 0000f066
-CSEG VE_RECURSE 00000342
-CSEG XT_RECURSE 00000348
-CSEG PFA_RECURSE 00000349
-CSEG VE_IMMEDIATE 0000034d
-CSEG XT_IMMEDIATE 00000354
-CSEG PFA_IMMEDIATE 00000355
-CSEG XT_GET_CURRENT 000003f6
-CSEG VE_BRACKETCHAR 0000035f
-CSEG XT_BRACKETCHAR 00000364
-CSEG PFA_BRACKETCHAR 00000365
-CSEG XT_CHAR 0000f904
-CSEG VE_ABORTQUOTE 0000036a
-CSEG XT_ABORTQUOTE 0000036f
-CSEG PFA_ABORTQUOTE 00000370
-CSEG XT_SQUOTE 0000f4db
-CSEG XT_QABORT 00000381
-CSEG VE_ABORT 00000374
-CSEG XT_ABORT 00000379
-CSEG PFA_ABORT 0000037a
-CSEG VE_QABORT 0000037c
-CSEG PFA_QABORT 00000382
-CSEG QABO1 00000387
-CSEG XT_ITYPE 0000f7ba
-CSEG VE_GET_STACK 00000389
-CSEG XT_GET_STACK 00000390
-CSEG PFA_N_FETCH_E2 000003a7
-CSEG PFA_N_FETCH_E1 0000039d
-CSEG XT_I 0000f2bd
-CSEG XT_1MINUS 0000f246
-CSEG XT_CELLS 0000f572
-CSEG XT_OVER 0000f0e0
-CSEG VE_SET_STACK 000003aa
-CSEG XT_SET_STACK 000003b1
-CSEG PFA_SET_STACK 000003b2
-CSEG XT_ZEROLESS 0000f132
-CSEG PFA_SET_STACK0 000003b9
-CSEG PFA_SET_STACK2 000003c6
-CSEG PFA_SET_STACK1 000003c1
-CSEG XT_TUCK 0000f590
-CSEG VE_MAPSTACK 000003c8
-CSEG XT_MAPSTACK 000003cf
-CSEG PFA_MAPSTACK 000003d0
-CSEG XT_BOUNDS 0000fd89
-CSEG PFA_MAPSTACK3 000003eb
-CSEG PFA_MAPSTACK1 000003da
-CSEG XT_R_FETCH 0000f119
-CSEG XT_EXECUTE 0000f02f
-CSEG PFA_MAPSTACK2 000003e7
-CSEG VE_GET_CURRENT 000003ee
-CSEG PFA_GET_CURRENT 000003f7
-ESEG CFG_CURRENT 00000058
-CSEG VE_GET_ORDER 000003fb
-CSEG XT_GET_ORDER 00000402
-CSEG PFA_GET_ORDER 00000403
-ESEG CFG_ORDERLISTLEN 0000005c
-CSEG VE_CFG_ORDER 00000407
-CSEG XT_CFG_ORDER 0000040e
-CSEG PFA_CFG_ORDER 0000040f
-CSEG VE_COMPARE 00000410
-CSEG XT_COMPARE 00000416
-CSEG PFA_COMPARE 00000417
-CSEG PFA_COMPARE_LOOP 00000423
-CSEG PFA_COMPARE_NOTEQUAL 00000431
-CSEG PFA_COMPARE_ENDREACHED2 0000042c
-CSEG PFA_COMPARE_ENDREACHED 0000042d
-CSEG PFA_COMPARE_CHECKLASTCHAR 00000431
-CSEG PFA_COMPARE_DONE 00000433
-CSEG VE_NFA2LFA 00000438
-CSEG XT_NFA2LFA 0000043e
-CSEG PFA_NFA2LFA 0000043f
-CSEG XT_NAME2STRING 0000fc8c
-CSEG XT_2SLASH 0000f215
-CSEG VE_SET_CURRENT 00000444
-CSEG XT_SET_CURRENT 0000044c
-CSEG PFA_SET_CURRENT 0000044d
-CSEG VE_WORDLIST 00000451
-CSEG XT_WORDLIST 00000457
-CSEG PFA_WORDLIST 00000458
-CSEG XT_EHERE 0000f5d1
-CSEG PFA_EHERE 0000f5d2
-CSEG VE_FORTHWORDLIST 00000461
-CSEG XT_FORTHWORDLIST 0000046a
-CSEG PFA_FORTHWORDLIST 0000046b
-ESEG CFG_FORTHWORDLIST 0000005a
-CSEG VE_SET_ORDER 0000046c
-CSEG XT_SET_ORDER 00000473
-CSEG PFA_SET_ORDER 00000474
-CSEG VE_SET_RECOGNIZERS 00000478
-CSEG XT_SET_RECOGNIZERS 00000482
-CSEG PFA_SET_RECOGNIZERS 00000483
-ESEG CFG_RECOGNIZERLISTLEN 0000006e
-CSEG VE_GET_RECOGNIZERS 00000487
-CSEG XT_GET_RECOGNIZERS 00000491
-CSEG PFA_GET_RECOGNIZERS 00000492
-CSEG VE_CODE 00000496
-CSEG XT_CODE 0000049a
-CSEG PFA_CODE 0000049b
-CSEG VE_ENDCODE 000004a1
-CSEG XT_ENDCODE 000004a7
-CSEG PFA_ENDCODE 000004a8
-CSEG VE_MARKER 000004ad
-CSEG XT_MARKER 000004b3
-CSEG PFA_MARKER 000004b4
-ESEG EE_MARKER 0000007a
-CSEG VE_POSTPONE 000004b7
-CSEG XT_POSTPONE 000004bd
-CSEG PFA_POSTPONE 000004be
-CSEG XT_FORTHRECOGNIZER 0000fae6
-CSEG XT_RECOGNIZE 0000faf1
-CSEG VE_APPLTURNKEY 000004cc
-CSEG XT_APPLTURNKEY 000004d4
-CSEG PFA_APPLTURNKEY 000004d5
-CSEG XT_INTON 0000f493
-CSEG XT_DOT_VER 0000fb7e
-CSEG VE_DOTS 000004d9
-CSEG XT_DOTS 000004dc
-CSEG PFA_DOTS 000004dd
-CSEG XT_DEPTH 0000fabb
-CSEG XT_UDOT 0000f462
-CSEG XT_SPACE 0000f7fc
-CSEG PFA_DOTS2 000004eb
-CSEG PFA_DOTS1 000004e6
-CSEG XT_PICK 0000f4c9
-CSEG VE_BUILDINFO 000004ec
-CSEG XT_BUILDINFO 000004f3
-CSEG PFA_BUILDINFO 000004f4
-CSEG VE_PLACE 00000502
-CSEG XT_PLACE 00000507
-CSEG PFA_PLACE 00000508
-CSEG XT_CMOVE 0000fd17
-CSEG VE_WORD 0000050e
-CSEG XT_WORD 00000512
-CSEG PFA_WORD 00000513
-CSEG XT_SKIPSCANCHAR 0000f9d2
-SET DPSTART 00000518
-CSEG DO_INTERRUPT 0000f019
-CSEG DO_EXECUTE 0000f00f
-CSEG XT_ISREXEC 0000f4bc
-CSEG VE_EXIT 0000f021
-CSEG PFA_EXIT 0000f026
-CSEG VE_EXECUTE 0000f029
-CSEG PFA_EXECUTE 0000f030
-CSEG PFA_DOBRANCH 0000f035
-CSEG PFA_DOCONDBRANCH 0000f03f
-CSEG PFA_DOLITERAL 0000f046
-CSEG XT_DOVARIABLE 0000f052
-CSEG XT_DOCONSTANT 0000f05f
-CSEG XT_DOUSER 0000f065
-CSEG VE_DOVALUE 0000f074
-CSEG XT_DOVALUE 0000f07a
-CSEG PFA_DOVALUE 0000f07b
-CSEG VE_FETCH 0000f087
-CSEG PFA_FETCH 0000f08b
-CSEG PFA_FETCHRAM 0000f08b
-CSEG VE_STORE 0000f08f
-CSEG PFA_STORE 0000f093
-CSEG PFA_STORERAM 0000f093
-CSEG VE_CSTORE 0000f09b
-CSEG PFA_CSTORE 0000f09f
-CSEG VE_CFETCH 0000f0a6
-CSEG PFA_CFETCH 0000f0aa
-CSEG VE_FETCHU 0000f0ae
-CSEG XT_FETCHU 0000f0b1
-CSEG PFA_FETCHU 0000f0b2
-CSEG XT_UP_FETCH 0000f313
-CSEG VE_STOREU 0000f0b6
-CSEG XT_STOREU 0000f0b9
-CSEG PFA_STOREU 0000f0ba
-CSEG VE_DUP 0000f0be
-CSEG PFA_DUP 0000f0c3
-CSEG VE_QDUP 0000f0c6
-CSEG PFA_QDUP 0000f0cb
-CSEG PFA_QDUP1 0000f0d0
-CSEG VE_SWAP 0000f0d1
-CSEG PFA_SWAP 0000f0d6
-CSEG VE_OVER 0000f0dc
-CSEG PFA_OVER 0000f0e1
-CSEG VE_DROP 0000f0e6
-CSEG PFA_DROP 0000f0eb
-CSEG VE_ROT 0000f0ee
-CSEG PFA_ROT 0000f0f3
-CSEG VE_NIP 0000f0fd
-CSEG PFA_NIP 0000f102
-CSEG VE_R_FROM 0000f104
-CSEG PFA_R_FROM 0000f108
-CSEG VE_TO_R 0000f10d
-CSEG PFA_TO_R 0000f111
-CSEG VE_R_FETCH 0000f116
-CSEG PFA_R_FETCH 0000f11a
-CSEG VE_NOTEQUAL 0000f121
-CSEG PFA_NOTEQUAL 0000f125
-CSEG VE_ZEROEQUAL 0000f128
-CSEG PFA_ZEROEQUAL 0000f12c
-CSEG PFA_ZERO1 0000f168
-CSEG PFA_TRUE1 0000f15f
-CSEG VE_ZEROLESS 0000f12f
-CSEG PFA_ZEROLESS 0000f133
-CSEG VE_GREATERZERO 0000f136
-CSEG PFA_GREATERZERO 0000f13a
-CSEG VE_DGREATERZERO 0000f13f
-CSEG XT_DGREATERZERO 0000f143
-CSEG PFA_DGREATERZERO 0000f144
-CSEG VE_DXT_ZEROLESS 0000f14d
-CSEG XT_DXT_ZEROLESS 0000f151
-CSEG PFA_DXT_ZEROLESS 0000f152
-CSEG VE_TRUE 0000f158
-CSEG PFA_TRUE 0000f15d
-CSEG VE_ZERO 0000f162
-CSEG PFA_ZERO 0000f166
-CSEG VE_ULESS 0000f16a
-CSEG PFA_ULESS 0000f16e
-CSEG VE_UGREATER 0000f175
-CSEG PFA_UGREATER 0000f179
-CSEG VE_LESS 0000f17c
-CSEG XT_LESS 0000f17f
-CSEG PFA_LESS 0000f180
-CSEG PFA_LESSDONE 0000f184
-CSEG VE_GREATER 0000f186
-CSEG XT_GREATER 0000f189
-CSEG PFA_GREATER 0000f18a
-CSEG PFA_GREATERDONE 0000f18e
-CSEG VE_LOG2 0000f191
-CSEG XT_LOG2 0000f195
-CSEG PFA_LOG2 0000f196
-CSEG PFA_LOG2_1 0000f199
-CSEG PFA_LOG2_2 0000f19f
-CSEG VE_MINUS 0000f1a1
-CSEG XT_MINUS 0000f1a4
-CSEG PFA_MINUS 0000f1a5
-CSEG VE_PLUS 0000f1ab
-CSEG PFA_PLUS 0000f1af
-CSEG VE_MSTAR 0000f1b4
-CSEG XT_MSTAR 0000f1b7
-CSEG PFA_MSTAR 0000f1b8
-CSEG VE_UMSLASHMOD 0000f1ce
-CSEG XT_UMSLASHMOD 0000f1d3
-CSEG PFA_UMSLASHMOD 0000f1d4
-CSEG PFA_UMSLASHMODmod 0000f1d9
-CSEG PFA_UMSLASHMODmod_loop 0000f1da
-CSEG PFA_UMSLASHMODmod_loop_control 0000f1e7
-CSEG PFA_UMSLASHMODmod_subtract 0000f1e4
-CSEG PFA_UMSLASHMODmod_done 0000f1e9
-CSEG VE_UMSTAR 0000f1ed
-CSEG PFA_UMSTAR 0000f1f2
-CSEG VE_INVERT 0000f209
-CSEG PFA_INVERT 0000f20f
-CSEG VE_2SLASH 0000f212
-CSEG PFA_2SLASH 0000f216
-CSEG VE_2STAR 0000f219
-CSEG XT_2STAR 0000f21c
-CSEG PFA_2STAR 0000f21d
-CSEG VE_AND 0000f220
-CSEG PFA_AND 0000f225
-CSEG VE_OR 0000f22a
-CSEG PFA_OR 0000f22e
-CSEG VE_XOR 0000f233
-CSEG XT_XOR 0000f237
-CSEG PFA_XOR 0000f238
-CSEG VE_1PLUS 0000f23d
-CSEG PFA_1PLUS 0000f241
-CSEG VE_1MINUS 0000f243
-CSEG PFA_1MINUS 0000f247
-CSEG VE_QNEGATE 0000f249
-CSEG XT_QNEGATE 0000f24f
-CSEG PFA_QNEGATE 0000f250
-CSEG QNEG1 0000f254
-CSEG XT_NEGATE 0000f659
-CSEG VE_LSHIFT 0000f255
-CSEG XT_LSHIFT 0000f25a
-CSEG PFA_LSHIFT 0000f25b
-CSEG PFA_LSHIFT1 0000f25e
-CSEG PFA_LSHIFT2 0000f263
-CSEG VE_RSHIFT 0000f264
-CSEG XT_RSHIFT 0000f269
-CSEG PFA_RSHIFT 0000f26a
-CSEG PFA_RSHIFT1 0000f26d
-CSEG PFA_RSHIFT2 0000f272
-CSEG VE_PLUSSTORE 0000f273
-CSEG PFA_PLUSSTORE 0000f277
-CSEG VE_RP_FETCH 0000f283
-CSEG XT_RP_FETCH 0000f287
-CSEG PFA_RP_FETCH 0000f288
-CSEG VE_RP_STORE 0000f28d
-CSEG XT_RP_STORE 0000f291
-CSEG PFA_RP_STORE 0000f292
-CSEG VE_SP_FETCH 0000f29a
-CSEG XT_SP_FETCH 0000f29e
-CSEG PFA_SP_FETCH 0000f29f
-CSEG VE_SP_STORE 0000f2a3
-CSEG XT_SP_STORE 0000f2a7
-CSEG PFA_SP_STORE 0000f2a8
-CSEG PFA_DODO 0000f2ad
-CSEG PFA_DODO1 0000f2af
-CSEG VE_I 0000f2ba
-CSEG PFA_I 0000f2be
-CSEG PFA_DOPLUSLOOP 0000f2cc
-CSEG PFA_DOPLUSLOOP_LEAVE 0000f2d6
-CSEG PFA_DOPLUSLOOP_NEXT 0000f2d3
-CSEG PFA_DOLOOP 0000f2db
-CSEG VE_UNLOOP 0000f2e0
-CSEG PFA_UNLOOP 0000f2e6
-CSEG VE_CMOVE_G 0000f2eb
-CSEG XT_CMOVE_G 0000f2f0
-CSEG PFA_CMOVE_G 0000f2f1
-CSEG PFA_CMOVE_G1 0000f302
-CSEG PFA_CMOVE_G2 0000f2fe
-CSEG VE_BYTESWAP 0000f307
-CSEG PFA_BYTESWAP 0000f30b
-CSEG VE_UP_FETCH 0000f30f
-CSEG PFA_UP_FETCH 0000f314
-CSEG VE_UP_STORE 0000f318
-CSEG XT_UP_STORE 0000f31c
-CSEG PFA_UP_STORE 0000f31d
-CSEG VE_1MS 0000f321
-CSEG XT_1MS 0000f325
-CSEG PFA_1MS 0000f326
-SET cycles 00000000
-SET loop_cycles 000007d0
-CSEG VE_2TO_R 0000f32b
-CSEG XT_2TO_R 0000f32f
-CSEG PFA_2TO_R 0000f330
-CSEG VE_2R_FROM 0000f33a
-CSEG XT_2R_FROM 0000f33e
-CSEG PFA_2R_FROM 0000f33f
-CSEG VE_STOREE 0000f349
-CSEG PFA_STOREE 0000f34d
-CSEG PFA_STOREE0 0000f34d
-CSEG PFA_FETCHE2 0000f37b
-CSEG PFA_STOREE3 0000f357
-CSEG PFA_STOREE1 0000f362
-CSEG PFA_STOREE4 0000f35e
-CSEG PFA_STOREE2 0000f364
-CSEG VE_FETCHE 0000f36d
-CSEG PFA_FETCHE 0000f371
-CSEG PFA_FETCHE1 0000f371
-CSEG VE_STOREI 0000f381
-CSEG PFA_STOREI 0000f385
-ESEG EE_STOREI 00000078
-CSEG VE_DO_STOREI_NRWW 0000f388
-CSEG XT_DO_STOREI 0000f38f
-CSEG PFA_DO_STOREI_NRWW 0000f390
-CSEG DO_STOREI_atmega 0000f3a4
-CSEG pageload 0000f3b5
-CSEG DO_STOREI_writepage 0000f3ae
-CSEG dospm 0000f3d1
-EQU pagemask ffffff80
-CSEG pageload_loop 0000f3bb
-CSEG pageload_newdata 0000f3c9
-CSEG pageload_cont 0000f3cb
-CSEG pageload_done 0000f3d0
-CSEG dospm_wait_ee 0000f3d1
-CSEG dospm_wait_spm 0000f3d3
-CSEG VE_FETCHI 0000f3df
-CSEG PFA_FETCHI 0000f3e3
-CSEG VE_N_TO_R 0000f3ec
-CSEG XT_N_TO_R 0000f3f0
-CSEG PFA_N_TO_R 0000f3f1
-CSEG PFA_N_TO_R1 0000f3f3
-CSEG VE_N_R_FROM 0000f3fe
-CSEG XT_N_R_FROM 0000f402
-CSEG PFA_N_R_FROM 0000f403
-CSEG PFA_N_R_FROM1 0000f408
-CSEG VE_D2STAR 0000f410
-CSEG XT_D2STAR 0000f414
-CSEG PFA_D2STAR 0000f415
-CSEG VE_D2SLASH 0000f41e
-CSEG XT_D2SLASH 0000f422
-CSEG PFA_D2SLASH 0000f423
-CSEG VE_DPLUS 0000f42c
-CSEG PFA_DPLUS 0000f430
-CSEG VE_DMINUS 0000f43d
-CSEG XT_DMINUS 0000f440
-CSEG PFA_DMINUS 0000f441
-CSEG VE_DINVERT 0000f44f
-CSEG XT_DINVERT 0000f455
-CSEG PFA_DINVERT 0000f456
-CSEG VE_UDOT 0000f45f
-CSEG PFA_UDOT 0000f463
-CSEG XT_UDDOT 0000f744
-CSEG VE_UDOTR 0000f466
-CSEG XT_UDOTR 0000f46a
-CSEG PFA_UDOTR 0000f46b
-CSEG XT_UDDOTR 0000f74d
-CSEG VE_SHOWWORDLIST 0000f46f
-CSEG XT_SHOWWORDLIST 0000f478
-CSEG PFA_SHOWWORDLIST 0000f479
-CSEG XT_SHOWWORD 0000f47e
-CSEG XT_TRAVERSEWORDLIST 0000fc71
-CSEG PFA_SHOWWORD 0000f47f
-CSEG VE_WORDS 0000f484
-CSEG XT_WORDS 0000f489
-CSEG PFA_WORDS 0000f48a
-CSEG VE_INTON 0000f48f
-CSEG PFA_INTON 0000f494
-CSEG VE_INTOFF 0000f496
-CSEG XT_INTOFF 0000f49a
-CSEG PFA_INTOFF 0000f49b
-CSEG VE_INTSTORE 0000f49d
-CSEG PFA_INTSTORE 0000f4a2
-CSEG VE_INTFETCH 0000f4a7
-CSEG XT_INTFETCH 0000f4ab
-CSEG PFA_INTFETCH 0000f4ac
-CSEG VE_INTTRAP 0000f4b1
-CSEG XT_INTTRAP 0000f4b7
-CSEG PFA_INTTRAP 0000f4b8
-CSEG PFA_ISREXEC 0000f4bd
-CSEG XT_ISREND 0000f4c1
-CSEG PFA_ISREND 0000f4c2
-CSEG PFA_ISREND1 0000f4c4
-CSEG VE_PICK 0000f4c5
-CSEG PFA_PICK 0000f4ca
-CSEG VE_DOTSTRING 0000f4d0
-CSEG XT_DOTSTRING 0000f4d3
-CSEG PFA_DOTSTRING 0000f4d4
-CSEG VE_SQUOTE 0000f4d8
-CSEG PFA_SQUOTE 0000f4dc
-CSEG PFA_SQUOTE1 0000f4e4
-CSEG VE_FILL 0000f4e5
-CSEG PFA_FILL 0000f4ea
-CSEG PFA_FILL2 0000f4f6
-CSEG PFA_FILL1 0000f4f1
-CSEG VE_ENVIRONMENT 0000f4f8
-CSEG XT_ENVIRONMENT 0000f500
-CSEG PFA_ENVIRONMENT 0000f501
-ESEG CFG_ENVIRONMENT 00000056
-CSEG VE_ENVWORDLISTS 0000f502
-CSEG XT_ENVWORDLISTS 0000f509
-CSEG PFA_ENVWORDLISTS 0000f50a
-CSEG VE_ENVSLASHPAD 0000f50d
-CSEG XT_ENVSLASHPAD 0000f511
-CSEG PFA_ENVSLASHPAD 0000f512
-CSEG XT_PAD 0000f59e
-CSEG VE_ENVSLASHHOLD 0000f516
-CSEG XT_ENVSLASHHOLD 0000f51b
-CSEG PFA_ENVSLASHHOLD 0000f51c
-CSEG VE_ENV_FORTHNAME 0000f520
-CSEG XT_ENV_FORTHNAME 0000f527
-CSEG PFA_EN_FORTHNAME 0000f528
-CSEG VE_ENV_FORTHVERSION 0000f52f
-CSEG XT_ENV_FORTHVERSION 0000f535
-CSEG PFA_EN_FORTHVERSION 0000f536
-CSEG VE_ENV_CPU 0000f539
-CSEG XT_ENV_CPU 0000f53d
-CSEG PFA_EN_CPU 0000f53e
-CSEG XT_ICOUNT 0000f7e6
-CSEG VE_ENV_MCUINFO 0000f542
-CSEG XT_ENV_MCUINFO 0000f548
-CSEG PFA_EN_MCUINFO 0000f549
-CSEG VE_ENVUSERSIZE 0000f54c
-CSEG XT_ENVUSERSIZE 0000f551
-CSEG PFA_ENVUSERSIZE 0000f552
-CSEG VE_F_CPU 0000f555
-CSEG XT_F_CPU 0000f55a
-CSEG PFA_F_CPU 0000f55b
-CSEG VE_STATE 0000f560
-CSEG PFA_STATE 0000f566
-DSEG ram_state 0000013d
-CSEG VE_BASE 0000f567
-CSEG XT_BASE 0000f56b
-CSEG PFA_BASE 0000f56c
-CSEG VE_CELLS 0000f56d
-CSEG VE_CELLPLUS 0000f573
-CSEG PFA_CELLPLUS 0000f579
-CSEG VE_2DUP 0000f57b
-CSEG PFA_2DUP 0000f580
-CSEG VE_2DROP 0000f583
-CSEG PFA_2DROP 0000f589
-CSEG VE_TUCK 0000f58c
-CSEG PFA_TUCK 0000f591
-CSEG VE_TO_IN 0000f594
-CSEG PFA_TO_IN 0000f599
-CSEG VE_PAD 0000f59a
-CSEG PFA_PAD 0000f59f
-CSEG VE_EMIT 0000f5a4
-CSEG XT_EMIT 0000f5a8
-CSEG PFA_EMIT 0000f5a9
-CSEG XT_UDEFERFETCH 0000fbf6
-CSEG XT_UDEFERSTORE 0000fc02
-CSEG VE_EMITQ 0000f5ac
-CSEG XT_EMITQ 0000f5b1
-CSEG PFA_EMITQ 0000f5b2
-CSEG VE_KEY 0000f5b5
-CSEG XT_KEY 0000f5b9
-CSEG PFA_KEY 0000f5ba
-CSEG VE_KEYQ 0000f5bd
-CSEG XT_KEYQ 0000f5c1
-CSEG PFA_KEYQ 0000f5c2
-CSEG VE_DP 0000f5c5
-ESEG CFG_DP 00000048
-CSEG VE_EHERE 0000f5cc
-ESEG EE_EHERE 0000004c
-CSEG VE_HERE 0000f5d5
-CSEG PFA_HERE 0000f5da
-ESEG EE_HERE 0000004a
-CSEG VE_ALLOT 0000f5dd
-CSEG PFA_ALLOT 0000f5e3
-CSEG VE_BIN 0000f5e8
-CSEG XT_BIN 0000f5ec
-CSEG PFA_BIN 0000f5ed
-CSEG VE_DECIMAL 0000f5f1
-CSEG XT_DECIMAL 0000f5f7
-CSEG PFA_DECIMAL 0000f5f8
-CSEG VE_HEX 0000f5fd
-CSEG XT_HEX 0000f601
-CSEG PFA_HEX 0000f602
-CSEG VE_BL 0000f607
-CSEG XT_BL 0000f60a
-CSEG PFA_BL 0000f60b
-CSEG VE_TURNKEY 0000f60c
-CSEG XT_TURNKEY 0000f612
-CSEG PFA_TURNKEY 0000f613
-ESEG CFG_TURNKEY 00000054
-CSEG VE_SLASHMOD 0000f616
-CSEG XT_SLASHMOD 0000f61a
-CSEG PFA_SLASHMOD 0000f61b
-CSEG PFA_SLASHMOD_1 0000f626
-CSEG PFA_SLASHMOD_2 0000f62c
-CSEG PFA_SLASHMOD_3 0000f62f
-CSEG PFA_SLASHMOD_5 0000f63a
-CSEG PFA_SLASHMOD_4 0000f639
-CSEG PFA_SLASHMODmod_done 0000f645
-CSEG PFA_SLASHMOD_6 0000f643
-CSEG VE_USLASHMOD 0000f649
-CSEG XT_USLASHMOD 0000f64e
-CSEG PFA_USLASHMOD 0000f64f
-CSEG VE_NEGATE 0000f654
-CSEG PFA_NEGATE 0000f65a
-CSEG VE_SLASH 0000f65d
-CSEG XT_SLASH 0000f660
-CSEG PFA_SLASH 0000f661
-CSEG VE_MOD 0000f664
-CSEG XT_MOD 0000f668
-CSEG PFA_MOD 0000f669
-CSEG VE_ABS 0000f66c
-CSEG XT_ABS 0000f670
-CSEG PFA_ABS 0000f671
-CSEG VE_MIN 0000f674
-CSEG XT_MIN 0000f678
-CSEG PFA_MIN 0000f679
-CSEG PFA_MIN1 0000f67e
-CSEG VE_MAX 0000f680
-CSEG XT_MAX 0000f684
-CSEG PFA_MAX 0000f685
-CSEG PFA_MAX1 0000f68a
-CSEG VE_WITHIN 0000f68c
-CSEG XT_WITHIN 0000f691
-CSEG PFA_WITHIN 0000f692
-CSEG VE_TOUPPER 0000f699
-CSEG XT_TOUPPER 0000f69f
-CSEG PFA_TOUPPER 0000f6a0
-CSEG PFA_TOUPPER0 0000f6ab
-CSEG VE_TOLOWER 0000f6ac
-CSEG XT_TOLOWER 0000f6b2
-CSEG PFA_TOLOWER 0000f6b3
-CSEG PFA_TOLOWER0 0000f6be
-CSEG VE_HLD 0000f6bf
-CSEG XT_HLD 0000f6c3
-CSEG PFA_HLD 0000f6c4
-DSEG ram_hld 0000013f
-CSEG VE_HOLD 0000f6c5
-CSEG XT_HOLD 0000f6c9
-CSEG PFA_HOLD 0000f6ca
-CSEG VE_L_SHARP 0000f6d5
-CSEG XT_L_SHARP 0000f6d8
-CSEG PFA_L_SHARP 0000f6d9
-CSEG VE_SHARP 0000f6dd
-CSEG XT_SHARP 0000f6e0
-CSEG PFA_SHARP 0000f6e1
-CSEG XT_UDSLASHMOD 0000f75d
-CSEG PFA_SHARP1 0000f6ee
-CSEG VE_SHARP_S 0000f6f3
-CSEG XT_SHARP_S 0000f6f6
-CSEG PFA_SHARP_S 0000f6f7
-CSEG NUMS1 0000f6f7
-CSEG VE_SHARP_G 0000f6fe
-CSEG XT_SHARP_G 0000f701
-CSEG PFA_SHARP_G 0000f702
-CSEG VE_SIGN 0000f709
-CSEG XT_SIGN 0000f70d
-CSEG PFA_SIGN 0000f70e
-CSEG PFA_SIGN1 0000f714
-CSEG VE_DDOTR 0000f715
-CSEG XT_DDOTR 0000f719
-CSEG PFA_DDOTR 0000f71a
-CSEG XT_DABS 0000fcff
-CSEG XT_SPACES 0000f805
-CSEG XT_TYPE 0000f815
-CSEG VE_DOTR 0000f728
-CSEG XT_DOTR 0000f72b
-CSEG PFA_DOTR 0000f72c
-CSEG VE_DDOT 0000f731
-CSEG XT_DDOT 0000f734
-CSEG PFA_DDOT 0000f735
-CSEG VE_DOT 0000f739
-CSEG XT_DOT 0000f73c
-CSEG PFA_DOT 0000f73d
-CSEG VE_UDDOT 0000f740
-CSEG PFA_UDDOT 0000f745
-CSEG VE_UDDOTR 0000f749
-CSEG PFA_UDDOTR 0000f74e
-CSEG VE_UDSLASHMOD 0000f758
-CSEG PFA_UDSLASHMOD 0000f75e
-CSEG VE_DIGITQ 0000f768
-CSEG XT_DIGITQ 0000f76d
-CSEG PFA_DIGITQ 0000f76e
-CSEG PFA_DOSLITERAL 0000f788
-CSEG VE_SCOMMA 0000f792
-CSEG PFA_SCOMMA 0000f796
-CSEG PFA_DOSCOMMA 0000f79a
-CSEG PFA_SCOMMA2 0000f7ac
-CSEG PFA_SCOMMA1 0000f7a6
-CSEG PFA_SCOMMA3 0000f7b3
-CSEG VE_ITYPE 0000f7b5
-CSEG PFA_ITYPE 0000f7bb
-CSEG PFA_ITYPE2 0000f7ce
-CSEG PFA_ITYPE1 0000f7c6
-CSEG XT_LOWEMIT 0000f7db
-CSEG XT_HIEMIT 0000f7d7
-CSEG PFA_ITYPE3 0000f7d5
-CSEG PFA_HIEMIT 0000f7d8
-CSEG PFA_LOWEMIT 0000f7dc
-CSEG VE_ICOUNT 0000f7e1
-CSEG PFA_ICOUNT 0000f7e7
-CSEG VE_CR 0000f7ec
-CSEG XT_CR 0000f7ef
-CSEG PFA_CR 0000f7f0
-CSEG VE_SPACE 0000f7f7
-CSEG PFA_SPACE 0000f7fd
-CSEG VE_SPACES 0000f800
-CSEG PFA_SPACES 0000f806
-CSEG SPCS1 0000f808
-CSEG SPCS2 0000f80f
-CSEG VE_TYPE 0000f811
-CSEG PFA_TYPE 0000f816
-CSEG PFA_TYPE2 0000f820
-CSEG PFA_TYPE1 0000f81b
-CSEG VE_TICK 0000f821
-CSEG PFA_TICK 0000f825
-CSEG XT_DT_NULL 0000fb64
-CSEG XT_NOOP 0000fb99
-CSEG PFA_TICK1 0000f836
-CSEG VE_HANDLER 0000f838
-CSEG XT_HANDLER 0000f83e
-CSEG PFA_HANDLER 0000f83f
-CSEG VE_CATCH 0000f840
-CSEG XT_CATCH 0000f845
-CSEG PFA_CATCH 0000f846
-CSEG VE_THROW 0000f856
-CSEG PFA_THROW 0000f85c
-CSEG PFA_THROW1 0000f862
-CSEG VE_CSKIP 0000f86f
-CSEG XT_CSKIP 0000f874
-CSEG PFA_CSKIP 0000f875
-CSEG PFA_CSKIP1 0000f876
-CSEG PFA_CSKIP2 0000f883
-CSEG XT_SLASHSTRING 0000f9bf
-CSEG VE_CSCAN 0000f886
-CSEG XT_CSCAN 0000f88b
-CSEG PFA_CSCAN 0000f88c
-CSEG PFA_CSCAN1 0000f88e
-CSEG PFA_CSCAN2 0000f8a0
-CSEG VE_ACCEPT 0000f8a6
-CSEG XT_ACCEPT 0000f8ab
-CSEG PFA_ACCEPT 0000f8ac
-CSEG ACC1 0000f8b0
-CSEG XT_CRLFQ 0000f8ec
-CSEG ACC5 0000f8de
-CSEG ACC3 0000f8ce
-CSEG ACC6 0000f8cc
-CSEG XT_BS 0000f8e4
-CSEG ACC4 0000f8dc
-CSEG PFA_ACCEPT6 0000f8d5
-CSEG VE_REFILL 0000f8f7
-CSEG XT_REFILL 0000f8fc
-CSEG PFA_REFILL 0000f8fd
-CSEG VE_CHAR 0000f900
-CSEG PFA_CHAR 0000f905
-CSEG VE_NUMBER 0000f909
-CSEG XT_NUMBER 0000f90e
-CSEG PFA_NUMBER 0000f90f
-CSEG XT_QSIGN 0000f952
-CSEG XT_SET_BASE 0000f965
-CSEG PFA_NUMBER0 0000f925
-CSEG XT_TO_NUMBER 0000f983
-CSEG PFA_NUMBER1 0000f947
-CSEG PFA_NUMBER2 0000f93e
-CSEG PFA_NUMBER6 0000f93f
-CSEG PFA_NUMBER3 0000f93b
-CSEG XT_DNEGATE 0000fd0c
-CSEG PFA_NUMBER5 0000f94d
-CSEG PFA_NUMBER4 0000f94c
-CSEG PFA_QSIGN 0000f953
-CSEG PFA_NUMBERSIGN_DONE 0000f95e
-CSEG XT_BASES 0000f960
-CSEG PFA_SET_BASE 0000f966
-CSEG SET_BASE1 0000f97b
-CSEG SET_BASE2 0000f97c
-CSEG VE_TO_NUMBER 0000f97d
-CSEG TONUM1 0000f984
-CSEG TONUM3 0000f99b
-CSEG TONUM2 0000f98f
-CSEG XT_2SWAP 0000fd30
-CSEG VE_PARSE 0000f99c
-CSEG PFA_PARSE 0000f9a2
-CSEG VE_SOURCE 0000f9b0
-CSEG PFA_SOURCE 0000f9b6
-CSEG VE_SLASHSTRING 0000f9b9
-CSEG PFA_SLASHSTRING 0000f9c0
-CSEG VE_PARSENAME 0000f9c7
-CSEG PFA_PARSENAME 0000f9cf
-CSEG PFA_SKIPSCANCHAR 0000f9d3
-CSEG VE_FINDXT 0000f9e4
-CSEG XT_FINDXT 0000f9ea
-CSEG PFA_FINDXT 0000f9eb
-CSEG XT_FINDXTA 0000f9f6
-CSEG PFA_FINDXT1 0000f9f5
-CSEG PFA_FINDXTA 0000f9f7
-CSEG XT_SEARCH_WORDLIST 0000fc3f
-CSEG PFA_FINDXTA1 0000fa03
-CSEG XT_DEFAULT_PROMPTOK 0000fa04
-CSEG PFA_DEFAULT_PROMPTOK 0000fa05
-CSEG VE_PROMPTOK 0000fa0b
-CSEG XT_PROMPTOK 0000fa0f
-CSEG PFA_PROMPTOK 0000fa10
-CSEG XT_DEFAULT_PROMPTREADY 0000fa13
-CSEG PFA_DEFAULT_PROMPTREADY 0000fa14
-CSEG VE_PROMPTREADY 0000fa1a
-CSEG XT_PROMPTREADY 0000fa1f
-CSEG PFA_PROMPTREADY 0000fa20
-CSEG XT_DEFAULT_PROMPTERROR 0000fa23
-CSEG PFA_DEFAULT_PROMPTERROR 0000fa24
-CSEG VE_PROMPTERROR 0000fa35
-CSEG XT_PROMPTERROR 0000fa3a
-CSEG PFA_PROMPTERROR 0000fa3b
-CSEG VE_QUIT 0000fa3e
-CSEG XT_QUIT 0000fa42
-CSEG PFA_QUIT 0000fa43
-CSEG XT_SP0 0000faa3
-CSEG XT_RP0 0000fab0
-CSEG PFA_QUIT2 0000fa4b
-CSEG PFA_QUIT4 0000fa51
-CSEG PFA_QUIT3 0000fa63
-CSEG XT_INTERPRET 0000fac9
-CSEG PFA_QUIT5 0000fa61
-CSEG VE_PAUSE 0000fa66
-CSEG PFA_PAUSE 0000fa6c
-DSEG ram_pause 00000141
-CSEG XT_RDEFERFETCH 0000fbe2
-CSEG XT_RDEFERSTORE 0000fbec
-CSEG VE_COLD 0000fa6f
-CSEG clearloop 0000fa7b
-DSEG ram_user1 00000143
-CSEG PFA_WARM 0000fa96
-CSEG VE_WARM 0000fa91
-CSEG XT_WARM 0000fa95
-CSEG XT_INIT_RAM 0000fd7b
-CSEG XT_DEFERSTORE 0000fc0d
-CSEG VE_SP0 0000fa9f
-CSEG PFA_SP0 0000faa4
-CSEG VE_SP 0000faa7
-CSEG XT_SP 0000faaa
-CSEG PFA_SP 0000faab
-CSEG VE_RP0 0000faac
-CSEG PFA_RP0 0000fab1
-CSEG XT_DORP0 0000fab4
-CSEG PFA_DORP0 0000fab5
-CSEG VE_DEPTH 0000fab6
-CSEG PFA_DEPTH 0000fabc
-CSEG VE_INTERPRET 0000fac2
-CSEG PFA_INTERPRET 0000faca
-CSEG PFA_INTERPRET2 0000fada
-CSEG PFA_INTERPRET1 0000fad5
-CSEG VE_FORTHRECOGNIZER 0000fadc
-CSEG PFA_FORTHRECOGNIZER 0000fae7
-ESEG CFG_FORTHRECOGNIZER 00000050
-CSEG VE_RECOGNIZE 0000faea
-CSEG PFA_RECOGNIZE 0000faf2
-CSEG XT_RECOGNIZE_A 0000fafc
-CSEG PFA_RECOGNIZE1 0000fafb
-CSEG PFA_RECOGNIZE_A 0000fafd
-CSEG PFA_RECOGNIZE_A1 0000fb0d
-CSEG VE_DT_NUM 0000fb11
-CSEG XT_DT_NUM 0000fb16
-CSEG PFA_DT_NUM 0000fb17
-CSEG VE_DT_DNUM 0000fb1a
-CSEG XT_DT_DNUM 0000fb20
-CSEG PFA_DT_DNUM 0000fb21
-CSEG XT_2LITERAL 0000fda2
-CSEG VE_REC_NUM 0000fb24
-CSEG XT_REC_NUM 0000fb2a
-CSEG PFA_REC_NUM 0000fb2b
-CSEG PFA_REC_NONUMBER 0000fb36
-CSEG PFA_REC_INTNUM2 0000fb34
-CSEG VE_REC_FIND 0000fb38
-CSEG XT_REC_FIND 0000fb3e
-CSEG PFA_REC_FIND 0000fb3f
-CSEG PFA_REC_WORD_FOUND 0000fb47
-CSEG XT_DT_XT 0000fb4e
-CSEG VE_DT_XT 0000fb49
-CSEG PFA_DT_XT 0000fb4f
-CSEG XT_R_WORD_INTERPRET 0000fb52
-CSEG XT_R_WORD_COMPILE 0000fb56
-CSEG PFA_R_WORD_INTERPRET 0000fb53
-CSEG PFA_R_WORD_COMPILE 0000fb57
-CSEG PFA_R_WORD_COMPILE1 0000fb5c
-CSEG VE_DT_NULL 0000fb5e
-CSEG PFA_DT_NULL 0000fb65
-CSEG XT_FAIL 0000fb68
-CSEG PFA_FAIL 0000fb69
-CSEG VE_QSTACK 0000fb6c
-CSEG PFA_QSTACK 0000fb72
-CSEG PFA_QSTACK1 0000fb79
-CSEG VE_DOT_VER 0000fb7a
-CSEG PFA_DOT_VER 0000fb7f
-CSEG VE_NOOP 0000fb95
-CSEG PFA_NOOP 0000fb9a
-CSEG VE_UNUSED 0000fb9b
-CSEG XT_UNUSED 0000fba0
-CSEG PFA_UNUSED 0000fba1
-CSEG VE_TO 0000fba5
-CSEG XT_TO 0000fba8
-CSEG PFA_TO 0000fba9
-CSEG XT_TO_BODY 0000fd9b
-CSEG PFA_TO1 0000fbb9
-CSEG PFA_DOTO 0000fbb4
-CSEG VE_ICELLPLUS 0000fbbf
-CSEG PFA_ICELLPLUS 0000fbc6
-CSEG VE_EDEFERFETCH 0000fbc8
-CSEG PFA_EDEFERFETCH 0000fbcf
-CSEG VE_EDEFERSTORE 0000fbd2
-CSEG PFA_EDEFERSTORE 0000fbd9
-CSEG VE_RDEFERFETCH 0000fbdc
-CSEG PFA_RDEFERFETCH 0000fbe3
-CSEG VE_RDEFERSTORE 0000fbe6
-CSEG PFA_RDEFERSTORE 0000fbed
-CSEG VE_UDEFERFETCH 0000fbf0
-CSEG PFA_UDEFERFETCH 0000fbf7
-CSEG VE_UDEFERSTORE 0000fbfc
-CSEG PFA_UDEFERSTORE 0000fc03
-CSEG VE_DEFERSTORE 0000fc08
-CSEG PFA_DEFERSTORE 0000fc0e
-CSEG VE_DEFERFETCH 0000fc15
-CSEG XT_DEFERFETCH 0000fc1a
-CSEG PFA_DEFERFETCH 0000fc1b
-CSEG VE_DODEFER 0000fc21
-CSEG XT_DODEFER 0000fc27
-CSEG PFA_DODEFER 0000fc28
-CSEG VE_SEARCH_WORDLIST 0000fc35
-CSEG PFA_SEARCH_WORDLIST 0000fc40
-CSEG XT_ISWORD 0000fc54
-CSEG PFA_SEARCH_WORDLIST1 0000fc4e
-CSEG PFA_ISWORD 0000fc55
-CSEG XT_ICOMPARE 0000fca2
-CSEG PFA_ISWORD3 0000fc62
-CSEG VE_TRAVERSEWORDLIST 0000fc66
-CSEG PFA_TRAVERSEWORDLIST 0000fc72
-CSEG PFA_TRAVERSEWORDLIST1 0000fc73
-CSEG PFA_TRAVERSEWORDLIST2 0000fc82
-CSEG VE_NAME2STRING 0000fc84
-CSEG PFA_NAME2STRING 0000fc8d
-CSEG VE_NFA2CFA 0000fc92
-CSEG PFA_NFA2CFA 0000fc99
-CSEG VE_ICOMPARE 0000fc9c
-CSEG PFA_ICOMPARE 0000fca3
-CSEG PFA_ICOMPARE_SAMELEN 0000fcad
-CSEG PFA_ICOMPARE_DONE 0000fcd2
-CSEG PFA_ICOMPARE_LOOP 0000fcb3
-CSEG XT_ICOMPARE_LC 0000fcd5
-CSEG PFA_ICOMPARE_LASTCELL 0000fcc3
-CSEG PFA_ICOMPARE_NEXTLOOP 0000fcca
-CSEG PFA_ICOMPARE_LC 0000fcd6
-CSEG VE_STAR 0000fce4
-CSEG XT_STAR 0000fce7
-CSEG PFA_STAR 0000fce8
-CSEG VE_J 0000fceb
-CSEG XT_J 0000fcee
-CSEG PFA_J 0000fcef
-CSEG VE_DABS 0000fcfb
-CSEG PFA_DABS 0000fd00
-CSEG PFA_DABS1 0000fd05
-CSEG VE_DNEGATE 0000fd06
-CSEG PFA_DNEGATE 0000fd0d
-CSEG VE_CMOVE 0000fd12
-CSEG PFA_CMOVE 0000fd18
-CSEG PFA_CMOVE1 0000fd25
-CSEG PFA_CMOVE2 0000fd21
-CSEG VE_2SWAP 0000fd2b
-CSEG PFA_2SWAP 0000fd31
-CSEG VE_REFILLTIB 0000fd36
-CSEG XT_REFILLTIB 0000fd3d
-CSEG PFA_REFILLTIB 0000fd3e
-CSEG XT_TIB 0000fd59
-CSEG XT_NUMBERTIB 0000fd5f
-CSEG VE_SOURCETIB 0000fd49
-CSEG XT_SOURCETIB 0000fd50
-CSEG PFA_SOURCETIB 0000fd51
-CSEG VE_TIB 0000fd55
-CSEG PFA_TIB 0000fd5a
-DSEG ram_tib 0000016f
-CSEG VE_NUMBERTIB 0000fd5b
-CSEG PFA_NUMBERTIB 0000fd60
-DSEG ram_sharptib 000001c9
-CSEG VE_EE2RAM 0000fd61
-CSEG XT_EE2RAM 0000fd66
-CSEG PFA_EE2RAM 0000fd67
-CSEG PFA_EE2RAM_1 0000fd69
-CSEG PFA_EE2RAM_2 0000fd73
-CSEG VE_INIT_RAM 0000fd75
-CSEG PFA_INI_RAM 0000fd7c
-ESEG EE_INITUSER 0000007c
-CSEG VE_BOUNDS 0000fd84
-CSEG PFA_BOUNDS 0000fd8a
-CSEG VE_S2D 0000fd8e
-CSEG PFA_S2D 0000fd93
-CSEG VE_TO_BODY 0000fd96
-CSEG VE_2LITERAL 0000fd9c
-CSEG PFA_2LITERAL 0000fda3
-CSEG VE_EQUAL 0000fda7
-CSEG PFA_EQUAL 0000fdab
-CSEG VE_ONE 0000fdae
-CSEG PFA_ONE 0000fdb2
-CSEG VE_TWO 0000fdb3
-CSEG PFA_TWO 0000fdb7
-CSEG VE_MINUSONE 0000fdb8
-CSEG XT_MINUSONE 0000fdbb
-CSEG PFA_MINUSONE 0000fdbc
-SET flashlast 0000fdbd
-DSEG HERESTART 000001cb
-ESEG EHERESTART 000000a0
-ESEG CFG_ORDERLIST 0000005e
-ESEG CFG_RECOGNIZERLIST 00000070
-EQU UBRR_VAL 0000000c
-EQU BAUD_REAL 0000963d
-EQU BAUD_ERROR 00000001
diff --git a/amforth-6.5/appl/template/words/applturnkey.asm b/amforth-6.5/appl/template/words/applturnkey.asm
deleted file mode 100644
index b7c8aac..0000000
--- a/amforth-6.5/appl/template/words/applturnkey.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( -- ) System
-; R( -- )
-; application specific turnkey action
-VE_APPLTURNKEY:
- .dw $ff0b
- .db "applturnkey",0
- .dw VE_HEAD
- .set VE_HEAD = VE_APPLTURNKEY
-XT_APPLTURNKEY:
- .dw DO_COLON
-PFA_APPLTURNKEY:
- .dw XT_USART
-
-.if WANT_INTERRUPTS == 1
- .dw XT_INTON
-.endif
- .dw XT_DOT_VER
- .dw XT_EXIT
diff --git a/amforth-6.5/appl/template/words/build-info.asm b/amforth-6.5/appl/template/words/build-info.asm
deleted file mode 100644
index c97056d..0000000
--- a/amforth-6.5/appl/template/words/build-info.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( -- i-addr len ) System
-; R( -- )
-; Build Info as flash string
-
-.if cpu_msp430==1
- HEADER(XT_BUILDINFO,10,"build-info",DOCOLON)
- .dw XT_DOSLITERAL
- .db 21
- .db "Apr 30, 2017 20:10:14"
- .align 16
-.endif
-
-.if cpu_avr8==1
-VE_BUILDINFO:
- .dw $ff0a
- .db "build-info"
- .dw VE_HEAD
- .set VE_HEAD = VE_BUILDINFO
-XT_BUILDINFO:
- .dw DO_COLON
-PFA_BUILDINFO:
- .dw XT_DOSLITERAL
- .dw 21
- .db "Apr 30, 2017 20:10:14"
-.endif
- .dw XT_EXIT
diff --git a/amforth-6.5/appl/template/words/qmark.asm b/amforth-6.5/appl/template/words/qmark.asm
deleted file mode 100644
index 500a39e..0000000
--- a/amforth-6.5/appl/template/words/qmark.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( adr -- n ) Tools
-; R( -- )
-; print the content of addr
-VE_QMARK:
- .dw $ff01
- .db "?",0
- .dw VE_HEAD
- .set VE_HEAD = VE_QMARK
-XT_QMARK:
- .dw DO_COLON
-PFA_QMARK:
- .dw XT_FETCH
- .dw XT_DOT
- .dw XT_EXIT
-
-; : ? ( adr - n ) @ . ;
-; finis qmark \ No newline at end of file
diff --git a/amforth-6.5/avr8/amforth-eeprom.inc b/amforth-6.5/avr8/amforth-eeprom.inc
deleted file mode 100644
index d71eeb0..0000000
--- a/amforth-6.5/avr8/amforth-eeprom.inc
+++ /dev/null
@@ -1,64 +0,0 @@
- .dw -1 ; EEPROM Address 0 should not be used
-; some configs
-CFG_DP: .dw DPSTART ; Dictionary Pointer
-EE_HERE: .dw HERESTART ; Memory Allocation
-EE_EHERE: .dw EHERESTART ; EEProm Memory Allocation
-CFG_WLSCOPE: .dw XT_GET_CURRENT ; default wordlist scope
-CFG_FORTHRECOGNIZER: .dw CFG_RECOGNIZERLISTLEN ; Recognizer word set
-; LEAVE stack is between data stack and return stack.
-CFG_LP0: .dw stackstart+1
-CFG_TURNKEY: .dw XT_APPLTURNKEY ; TURNKEY
-CFG_ENVIRONMENT:.dw VE_ENVHEAD ; environmental queries
-CFG_CURRENT: .dw CFG_FORTHWORDLIST ; forth-wordlist
-CFG_FORTHWORDLIST:.dw VE_HEAD ; pre-defined (compiled in) wordlist
-CFG_ORDERLISTLEN:
- .dw 1
-CFG_ORDERLIST: ; list of wordlist id, exactly numwordlist entries
- .dw CFG_FORTHWORDLIST ; get/set-order
- .byte (NUMWORDLISTS-1)*CELLSIZE ; one slot is already used
-CFG_RECOGNIZERLISTLEN:
- .dw 2
-CFG_RECOGNIZERLIST:
- .dw XT_REC_FIND
- .dw XT_REC_NUM
- .byte (NUMRECOGNIZERS-2)*CELLSIZE ; two slots are already used
-
-EE_STOREI:
- .dw XT_DO_STOREI ; Store a cell into flash
-
-; MARKER saves everything up to here. Nothing beyond gets saved
-EE_MARKER:
- .dw EE_MARKER
-
-; default user area
-EE_INITUSER:
- .dw 0 ; USER_STATE
- .dw 0 ; USER_FOLLOWER
- .dw rstackstart ; USER_RP
- .dw stackstart ; USER_SP0
- .dw stackstart ; USER_SP
-
- .dw 0 ; USER_HANDLER
- .dw 10 ; USER_BASE
-
- .dw XT_TX ; USER_EMIT
- .dw XT_TXQ ; USER_EMITQ
- .dw XT_RX ; USER_KEY
- .dw XT_RXQ ; USER_KEYQ
- .dw XT_SOURCETIB ; USER_SOURCE
- .dw 0 ; USER_G_IN
- .dw XT_REFILLTIB ; USER_REFILL
- .dw XT_DEFAULT_PROMPTOK
- .dw XT_DEFAULT_PROMPTERROR
- .dw XT_DEFAULT_PROMPTREADY
-
-; calculate baud rate error
-.equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; smart round
-.equ BAUD_REAL = (F_CPU/(16*(UBRR_VAL+1))) ; effective baud rate
-.equ BAUD_ERROR = ((BAUD_REAL*1000)/BAUD-1000) ; error in pro mille
-
-.if ((BAUD_ERROR>BAUD_MAXERROR) || (BAUD_ERROR<-BAUD_MAXERROR))
- .error "Serial line cannot be set up properly (systematic baud error too high)"
-.endif
-EE_UBRRVAL:
- .dw UBRR_VAL ; BAUDRATE
diff --git a/amforth-6.5/avr8/amforth-interpreter.asm b/amforth-6.5/avr8/amforth-interpreter.asm
deleted file mode 100644
index 1d72745..0000000
--- a/amforth-6.5/avr8/amforth-interpreter.asm
+++ /dev/null
@@ -1,33 +0,0 @@
-; the inner interpreter.
-
-DO_COLON:
- push XH
- push XL ; PUSH IP
- movw XL, wl
- adiw xl, 1
-DO_NEXT:
-.if WANT_INTERRUPTS == 1
- cp isrflag, zerol
- brne DO_INTERRUPT
-.endif
- movw zl, XL ; READ IP
- readflashcell wl, wh
- adiw XL, 1 ; INC IP
-
-DO_EXECUTE:
- movw zl, wl
- readflashcell temp0,temp1
- movw zl, temp0
- ijmp
-
-.if WANT_INTERRUPTS == 1
-DO_INTERRUPT:
- ; here we deal with interrupts the forth way
- savetos
- mov tosl, isrflag
- clr tosh
- clr isrflag
- ldi wl, LOW(XT_ISREXEC)
- ldi wh, HIGH(XT_ISREXEC)
- rjmp DO_EXECUTE
-.endif \ No newline at end of file
diff --git a/amforth-6.5/avr8/amforth-low.asm b/amforth-6.5/avr8/amforth-low.asm
deleted file mode 100644
index 0bd5ece..0000000
--- a/amforth-6.5/avr8/amforth-low.asm
+++ /dev/null
@@ -1,31 +0,0 @@
-;;;; avr forth
-;;;;
-;;;; GPL V2 (only)
-
-.set pc_ = pc
-
-.org $0000
- jmp_ PFA_COLD
-.org pc_
-
-.include "amforth-interpreter.asm"
-.include "drivers/generic-isr.asm"
-.set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-; lower part of the dictionary
-.include "dict/rww.inc"
-.include "dict_appl.inc"
-.include "dict/nrww.inc" ; well, not really nrww, but simplifies things alot
-.include "dict_appl_core.inc"
-
-
-.set DPSTART = pc
-.set flashlast = pc
-
-.dseg
-HERESTART:
-.eseg
-.include "amforth-eeprom.inc"
-; 1st free address in EEPROM.
-EHERESTART:
-
-.cseg
diff --git a/amforth-6.5/avr8/amforth.asm b/amforth-6.5/avr8/amforth.asm
deleted file mode 100644
index 3e9a9f2..0000000
--- a/amforth-6.5/avr8/amforth.asm
+++ /dev/null
@@ -1,39 +0,0 @@
-;;;; avr forth
-;;;;
-;;;; GPL V2 (only)
-
-.set AMFORTH_NRWW_SIZE=(FLASHEND-AMFORTH_RO_SEG)*2
-
-.set corepc = pc
-.org $0000
- jmp_ PFA_COLD
-
-.org corepc
-.include "drivers/generic-isr.asm"
-; lower part of the dictionary
-.include "dict/rww.inc"
-.include "dict_appl.inc"
-
-.set DPSTART = pc
-.if(pc>AMFORTH_RO_SEG)
-.error "RWW Segment Overflow, please edit your dict_appl.inc"
-.endif
-
-.org AMFORTH_RO_SEG
-.include "amforth-interpreter.asm"
-.include "dict/nrww.inc"
-.include "dict_appl_core.inc"
-
-.set flashlast = pc
-.if (pc>FLASHEND)
- .error "*** Flash size exceeded, please edit your dict_appl_core file to use less space! Aborting."
-.endif
-
-.dseg
-; define a label for the 1st free ram address
-HERESTART:
-.eseg
-.include "amforth-eeprom.inc"
-; 1st free address in EEPROM.
-EHERESTART:
-.cseg
diff --git a/amforth-6.5/avr8/devices/at90can128/at90can128.frt b/amforth-6.5/avr8/devices/at90can128/at90can128.frt
deleted file mode 100644
index 28cb0af..0000000
--- a/amforth-6.5/avr8/devices/at90can128/at90can128.frt
+++ /dev/null
@@ -1,465 +0,0 @@
-\ Partname: AT90CAN128
-\ generated automatically
-
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ TWI
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register t Bytes
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register t Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ RAM Page Z Select Register
- $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2A \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2A \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVRG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt
- $08 constant CANGIT_SERG \ Stuff Error General
- $04 constant CANGIT_CERG \ CRC Error General
- $02 constant CANGIT_FERG \ Form Error General
- $01 constant CANGIT_AERG \ Ackknowledgement Error General
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register
-&221 constant CANEN1 \ Enable MOb Register
-&222 constant CANIE2 \ Enable Interrupt MOb Register
-&223 constant CANIE1 \ Enable Interrupt MOb Register
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register
-&226 constant CANBT1 \ Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width
- $0E constant CANBT2_PRS \ Propagation Time Segment
-&228 constant CANBT3 \ Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segments
- $0E constant CANBT3_PHS1 \ Phase Segment 1
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number Bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment
- $07 constant CANPAGE_INDX \ Data Buffer Index Bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning
- $40 constant CANSTMOB_TXOK \ Transmit OK
- $20 constant CANSTMOB_RXOK \ Receive OK
- $10 constant CANSTMOB_BERR \ Bit Error
- $08 constant CANSTMOB_SERR \ Stuff Error
- $04 constant CANSTMOB_CERR \ CRC Error
- $02 constant CANSTMOB_FERR \ Form Error
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config Bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code Bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CANITAddr \ CAN Transfer Complete or Error
-&38 constant OVRITAddr \ CAN Timer Overrun
-&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&42 constant USART0__RXAddr \ USART0, Rx Complete
-&44 constant USART0__UDREAddr \ USART0 Data Register Empty
-&46 constant USART0__TXAddr \ USART0, Tx Complete
-&48 constant ANALOG_COMPAddr \ Analog Comparator
-&50 constant ADCAddr \ ADC Conversion Complete
-&52 constant EE_READYAddr \ EEPROM Ready
-&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&64 constant USART1__RXAddr \ USART1, Rx Complete
-&66 constant USART1__UDREAddr \ USART1, Data Register Empty
-&68 constant USART1__TXAddr \ USART1, Tx Complete
-&70 constant TWIAddr \ 2-wire Serial Interface
-&72 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90can128/device.asm b/amforth-6.5/avr8/devices/at90can128/device.asm
deleted file mode 100644
index e669742..0000000
--- a/amforth-6.5/avr8/devices/at90can128/device.asm
+++ /dev/null
@@ -1,145 +0,0 @@
-; Partname: AT90CAN128
-; generated automatically, do not edit
-
-.nolist
- .include "can128def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_JTAG = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CAN = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Compare Match C
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN Transfer Complete or Error
-.org 38
- rcall isr ; CAN Timer Overrun
-.org 40
- rcall isr ; SPI Serial Transfer Complete
-.org 42
- rcall isr ; USART0, Rx Complete
-.org 44
- rcall isr ; USART0 Data Register Empty
-.org 46
- rcall isr ; USART0, Tx Complete
-.org 48
- rcall isr ; Analog Comparator
-.org 50
- rcall isr ; ADC Conversion Complete
-.org 52
- rcall isr ; EEPROM Ready
-.org 54
- rcall isr ; Timer/Counter3 Capture Event
-.org 56
- rcall isr ; Timer/Counter3 Compare Match A
-.org 58
- rcall isr ; Timer/Counter3 Compare Match B
-.org 60
- rcall isr ; Timer/Counter3 Compare Match C
-.org 62
- rcall isr ; Timer/Counter3 Overflow
-.org 64
- rcall isr ; USART1, Rx Complete
-.org 66
- rcall isr ; USART1, Data Register Empty
-.org 68
- rcall isr ; USART1, Tx Complete
-.org 70
- rcall isr ; 2-wire Serial Interface
-.org 72
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 37
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 37
-mcu_name:
- .dw 10
- .db "AT90CAN128"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90can128/device.inc b/amforth-6.5/avr8/devices/at90can128/device.inc
deleted file mode 100644
index 59c6d52..0000000
--- a/amforth-6.5/avr8/devices/at90can128/device.inc
+++ /dev/null
@@ -1,1707 +0,0 @@
-; Partname: AT90CAN128
-; generated automatically, no not edit
-
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register t Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register t Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90can128/device.py b/amforth-6.5/avr8/devices/at90can128/device.py
deleted file mode 100644
index 778b42e..0000000
--- a/amforth-6.5/avr8/devices/at90can128/device.py
+++ /dev/null
@@ -1,507 +0,0 @@
-# Generated Automatically
-
-# Partname AT90CAN128
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CANITAddr' : '#36', # CAN Transfer Complete or Error
- 'OVRITAddr' : '#38', # CAN Timer Overrun
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#42', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#46', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#48', # Analog Comparator
- 'ADCAddr' : '#50', # ADC Conversion Complete
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#64', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#68', # USART1, Tx Complete
- 'TWIAddr' : '#70', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#72', # Store Program Memory Read
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module TWI
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register t Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register t Byt
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2A': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Waveform Genration Mode
- 'TCCR2_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVRG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt
- 'CANGIT_SERG': '$8', # Stuff Error General
- 'CANGIT_CERG': '$4', # CRC Error General
- 'CANGIT_FERG': '$2', # Form Error General
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register
- 'CANEN1' : '$dd', # Enable MOb Register
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width
- 'CANBT2_PRS': '$e', # Propagation Time Segment
- 'CANBT3' : '$e4', # Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segments
- 'CANBT3_PHS1': '$e', # Phase Segment 1
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number Bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index Bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning
- 'CANSTMOB_TXOK': '$40', # Transmit OK
- 'CANSTMOB_RXOK': '$20', # Receive OK
- 'CANSTMOB_BERR': '$10', # Bit Error
- 'CANSTMOB_SERR': '$8', # Stuff Error
- 'CANSTMOB_CERR': '$4', # CRC Error
- 'CANSTMOB_FERR': '$2', # Form Error
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code Bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can128/words/sleep.asm b/amforth-6.5/avr8/devices/at90can128/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90can128/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can32/at90can32.frt b/amforth-6.5/avr8/devices/at90can32/at90can32.frt
deleted file mode 100644
index 56a906a..0000000
--- a/amforth-6.5/avr8/devices/at90can32/at90can32.frt
+++ /dev/null
@@ -1,465 +0,0 @@
-\ Partname: AT90CAN32
-\ generated automatically
-
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ TWI
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register t Bytes
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register t Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ RAM Page Z Select Register - Not used.
- $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2A \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2A \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVRG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt
- $08 constant CANGIT_SERG \ Stuff Error General
- $04 constant CANGIT_CERG \ CRC Error General
- $02 constant CANGIT_FERG \ Form Error General
- $01 constant CANGIT_AERG \ Ackknowledgement Error General
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register
-&221 constant CANEN1 \ Enable MOb Register
-&222 constant CANIE2 \ Enable Interrupt MOb Register
-&223 constant CANIE1 \ Enable Interrupt MOb Register
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register
-&226 constant CANBT1 \ Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width
- $0E constant CANBT2_PRS \ Propagation Time Segment
-&228 constant CANBT3 \ Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segments
- $0E constant CANBT3_PHS1 \ Phase Segment 1
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number Bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment
- $07 constant CANPAGE_INDX \ Data Buffer Index Bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning
- $40 constant CANSTMOB_TXOK \ Transmit OK
- $20 constant CANSTMOB_RXOK \ Receive OK
- $10 constant CANSTMOB_BERR \ Bit Error
- $08 constant CANSTMOB_SERR \ Stuff Error
- $04 constant CANSTMOB_CERR \ CRC Error
- $02 constant CANSTMOB_FERR \ Form Error
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config Bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code Bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CANITAddr \ CAN Transfer Complete or Error
-&38 constant OVRITAddr \ CAN Timer Overrun
-&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&42 constant USART0__RXAddr \ USART0, Rx Complete
-&44 constant USART0__UDREAddr \ USART0 Data Register Empty
-&46 constant USART0__TXAddr \ USART0, Tx Complete
-&48 constant ANALOG_COMPAddr \ Analog Comparator
-&50 constant ADCAddr \ ADC Conversion Complete
-&52 constant EE_READYAddr \ EEPROM Ready
-&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&64 constant USART1__RXAddr \ USART1, Rx Complete
-&66 constant USART1__UDREAddr \ USART1, Data Register Empty
-&68 constant USART1__TXAddr \ USART1, Tx Complete
-&70 constant TWIAddr \ 2-wire Serial Interface
-&72 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90can32/device.asm b/amforth-6.5/avr8/devices/at90can32/device.asm
deleted file mode 100644
index 3ca443f..0000000
--- a/amforth-6.5/avr8/devices/at90can32/device.asm
+++ /dev/null
@@ -1,139 +0,0 @@
-; Partname: AT90CAN32
-; generated automatically, do not edit
-
-.nolist
- .include "can32def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CAN = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Compare Match C
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN Transfer Complete or Error
-.org 38
- rcall isr ; CAN Timer Overrun
-.org 40
- rcall isr ; SPI Serial Transfer Complete
-.org 42
- rcall isr ; USART0, Rx Complete
-.org 44
- rcall isr ; USART0 Data Register Empty
-.org 46
- rcall isr ; USART0, Tx Complete
-.org 48
- rcall isr ; Analog Comparator
-.org 50
- rcall isr ; ADC Conversion Complete
-.org 52
- rcall isr ; EEPROM Ready
-.org 54
- rcall isr ; Timer/Counter3 Capture Event
-.org 56
- rcall isr ; Timer/Counter3 Compare Match A
-.org 58
- rcall isr ; Timer/Counter3 Compare Match B
-.org 60
- rcall isr ; Timer/Counter3 Compare Match C
-.org 62
- rcall isr ; Timer/Counter3 Overflow
-.org 64
- rcall isr ; USART1, Rx Complete
-.org 66
- rcall isr ; USART1, Data Register Empty
-.org 68
- rcall isr ; USART1, Tx Complete
-.org 70
- rcall isr ; 2-wire Serial Interface
-.org 72
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 37
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 24576
-mcu_numints:
- .dw 37
-mcu_name:
- .dw 9
- .db "AT90CAN32",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90can32/device.inc b/amforth-6.5/avr8/devices/at90can32/device.inc
deleted file mode 100644
index 4b27471..0000000
--- a/amforth-6.5/avr8/devices/at90can32/device.inc
+++ /dev/null
@@ -1,1707 +0,0 @@
-; Partname: AT90CAN32
-; generated automatically, no not edit
-
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register t Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register t Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register - Not used.
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90can32/device.py b/amforth-6.5/avr8/devices/at90can32/device.py
deleted file mode 100644
index b907435..0000000
--- a/amforth-6.5/avr8/devices/at90can32/device.py
+++ /dev/null
@@ -1,507 +0,0 @@
-# Generated Automatically
-
-# Partname AT90CAN32
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CANITAddr' : '#36', # CAN Transfer Complete or Error
- 'OVRITAddr' : '#38', # CAN Timer Overrun
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#42', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#46', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#48', # Analog Comparator
- 'ADCAddr' : '#50', # ADC Conversion Complete
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#64', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#68', # USART1, Tx Complete
- 'TWIAddr' : '#70', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#72', # Store Program Memory Read
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module TWI
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register t Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register t Byt
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # RAM Page Z Select Register - N
- 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2A': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Waveform Genration Mode
- 'TCCR2_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVRG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt
- 'CANGIT_SERG': '$8', # Stuff Error General
- 'CANGIT_CERG': '$4', # CRC Error General
- 'CANGIT_FERG': '$2', # Form Error General
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register
- 'CANEN1' : '$dd', # Enable MOb Register
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width
- 'CANBT2_PRS': '$e', # Propagation Time Segment
- 'CANBT3' : '$e4', # Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segments
- 'CANBT3_PHS1': '$e', # Phase Segment 1
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number Bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index Bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning
- 'CANSTMOB_TXOK': '$40', # Transmit OK
- 'CANSTMOB_RXOK': '$20', # Receive OK
- 'CANSTMOB_BERR': '$10', # Bit Error
- 'CANSTMOB_SERR': '$8', # Stuff Error
- 'CANSTMOB_CERR': '$4', # CRC Error
- 'CANSTMOB_FERR': '$2', # Form Error
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code Bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can32/words/sleep.asm b/amforth-6.5/avr8/devices/at90can32/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90can32/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can64/at90can64.frt b/amforth-6.5/avr8/devices/at90can64/at90can64.frt
deleted file mode 100644
index 41db98b..0000000
--- a/amforth-6.5/avr8/devices/at90can64/at90can64.frt
+++ /dev/null
@@ -1,465 +0,0 @@
-\ Partname: AT90CAN64
-\ generated automatically
-
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ TWI
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register t Bytes
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register t Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ RAM Page Z Select Register - Not used.
- $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2A \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2A \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVRG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt
- $08 constant CANGIT_SERG \ Stuff Error General
- $04 constant CANGIT_CERG \ CRC Error General
- $02 constant CANGIT_FERG \ Form Error General
- $01 constant CANGIT_AERG \ Ackknowledgement Error General
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register
-&221 constant CANEN1 \ Enable MOb Register
-&222 constant CANIE2 \ Enable Interrupt MOb Register
-&223 constant CANIE1 \ Enable Interrupt MOb Register
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register
-&226 constant CANBT1 \ Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width
- $0E constant CANBT2_PRS \ Propagation Time Segment
-&228 constant CANBT3 \ Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segments
- $0E constant CANBT3_PHS1 \ Phase Segment 1
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number Bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment
- $07 constant CANPAGE_INDX \ Data Buffer Index Bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning
- $40 constant CANSTMOB_TXOK \ Transmit OK
- $20 constant CANSTMOB_RXOK \ Receive OK
- $10 constant CANSTMOB_BERR \ Bit Error
- $08 constant CANSTMOB_SERR \ Stuff Error
- $04 constant CANSTMOB_CERR \ CRC Error
- $02 constant CANSTMOB_FERR \ Form Error
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config Bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code Bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CANITAddr \ CAN Transfer Complete or Error
-&38 constant OVRITAddr \ CAN Timer Overrun
-&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&42 constant USART0__RXAddr \ USART0, Rx Complete
-&44 constant USART0__UDREAddr \ USART0 Data Register Empty
-&46 constant USART0__TXAddr \ USART0, Tx Complete
-&48 constant ANALOG_COMPAddr \ Analog Comparator
-&50 constant ADCAddr \ ADC Conversion Complete
-&52 constant EE_READYAddr \ EEPROM Ready
-&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&64 constant USART1__RXAddr \ USART1, Rx Complete
-&66 constant USART1__UDREAddr \ USART1, Data Register Empty
-&68 constant USART1__TXAddr \ USART1, Tx Complete
-&70 constant TWIAddr \ 2-wire Serial Interface
-&72 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90can64/device.asm b/amforth-6.5/avr8/devices/at90can64/device.asm
deleted file mode 100644
index abcfaad..0000000
--- a/amforth-6.5/avr8/devices/at90can64/device.asm
+++ /dev/null
@@ -1,139 +0,0 @@
-; Partname: AT90CAN64
-; generated automatically, do not edit
-
-.nolist
- .include "can64def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_JTAG = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CAN = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Compare Match C
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN Transfer Complete or Error
-.org 38
- rcall isr ; CAN Timer Overrun
-.org 40
- rcall isr ; SPI Serial Transfer Complete
-.org 42
- rcall isr ; USART0, Rx Complete
-.org 44
- rcall isr ; USART0 Data Register Empty
-.org 46
- rcall isr ; USART0, Tx Complete
-.org 48
- rcall isr ; Analog Comparator
-.org 50
- rcall isr ; ADC Conversion Complete
-.org 52
- rcall isr ; EEPROM Ready
-.org 54
- rcall isr ; Timer/Counter3 Capture Event
-.org 56
- rcall isr ; Timer/Counter3 Compare Match A
-.org 58
- rcall isr ; Timer/Counter3 Compare Match B
-.org 60
- rcall isr ; Timer/Counter3 Compare Match C
-.org 62
- rcall isr ; Timer/Counter3 Overflow
-.org 64
- rcall isr ; USART1, Rx Complete
-.org 66
- rcall isr ; USART1, Data Register Empty
-.org 68
- rcall isr ; USART1, Tx Complete
-.org 70
- rcall isr ; 2-wire Serial Interface
-.org 72
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 37
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 37
-mcu_name:
- .dw 9
- .db "AT90CAN64",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90can64/device.inc b/amforth-6.5/avr8/devices/at90can64/device.inc
deleted file mode 100644
index 24b3493..0000000
--- a/amforth-6.5/avr8/devices/at90can64/device.inc
+++ /dev/null
@@ -1,1707 +0,0 @@
-; Partname: AT90CAN64
-; generated automatically, no not edit
-
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register t Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register t Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register - Not used.
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90can64/device.py b/amforth-6.5/avr8/devices/at90can64/device.py
deleted file mode 100644
index 3de7034..0000000
--- a/amforth-6.5/avr8/devices/at90can64/device.py
+++ /dev/null
@@ -1,507 +0,0 @@
-# Generated Automatically
-
-# Partname AT90CAN64
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CANITAddr' : '#36', # CAN Transfer Complete or Error
- 'OVRITAddr' : '#38', # CAN Timer Overrun
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#42', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#46', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#48', # Analog Comparator
- 'ADCAddr' : '#50', # ADC Conversion Complete
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#64', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#68', # USART1, Tx Complete
- 'TWIAddr' : '#70', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#72', # Store Program Memory Read
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module TWI
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register t Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register t Byt
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # RAM Page Z Select Register - N
- 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2A': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Waveform Genration Mode
- 'TCCR2_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVRG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt
- 'CANGIT_SERG': '$8', # Stuff Error General
- 'CANGIT_CERG': '$4', # CRC Error General
- 'CANGIT_FERG': '$2', # Form Error General
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register
- 'CANEN1' : '$dd', # Enable MOb Register
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width
- 'CANBT2_PRS': '$e', # Propagation Time Segment
- 'CANBT3' : '$e4', # Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segments
- 'CANBT3_PHS1': '$e', # Phase Segment 1
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number Bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index Bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning
- 'CANSTMOB_TXOK': '$40', # Transmit OK
- 'CANSTMOB_RXOK': '$20', # Receive OK
- 'CANSTMOB_BERR': '$10', # Bit Error
- 'CANSTMOB_SERR': '$8', # Stuff Error
- 'CANSTMOB_CERR': '$4', # CRC Error
- 'CANSTMOB_FERR': '$2', # Form Error
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code Bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can64/words/sleep.asm b/amforth-6.5/avr8/devices/at90can64/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90can64/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt b/amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt
deleted file mode 100644
index e17d4b8..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt
+++ /dev/null
@@ -1,381 +0,0 @@
-\ Partname: AT90PWM1
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PSC0
-&222 constant PICR0 \ PSC 0 Input Capture Register
-&221 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
- $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
-&220 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
- $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
-&219 constant PCTL0 \ PSC 0 Control Register
- $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
- $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
- $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
- $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- $01 constant PCTL0_PRUN0 \ PSC 0 Run
-&218 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
- $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
-&216 constant OCR0RB \ Output Compare RB Register
-&214 constant OCR0SB \ Output Compare SB Register
-&212 constant OCR0RA \ Output Compare RA Register
-&210 constant OCR0SA \ Output Compare SA Register
-&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
- $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
- $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
-&161 constant PIM0 \ PSC0 Interrupt Mask Register
- $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
- $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
- $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
-&160 constant PIFR0 \ PSC0 Interrupt Flag Register
- $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- $08 constant PIFR0_PEV0A \ External Event A Interrupt
- $06 constant PIFR0_PRN0 \ Ramp Number
- $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
-\ PSC2
-&254 constant PICR2 \ PSC 2 Input Capture Register
-&253 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
- $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
-&252 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
- $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
-&251 constant PCTL2 \ PSC 2 Control Register
- $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
- $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
- $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
- $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- $01 constant PCTL2_PRUN2 \ PSC 2 Run
-&250 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
- $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
-&248 constant OCR2RB \ Output Compare RB Register
-&246 constant OCR2SB \ Output Compare SB Register
-&244 constant OCR2RA \ Output Compare RA Register
-&242 constant OCR2SA \ Output Compare SA Register
-&241 constant POM2 \ PSC 2 Output Matrix
- $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
-&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
- $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
- $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
-&165 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
- $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
- $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
-&164 constant PIFR2 \ PSC2 Interrupt Flag Register
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- $08 constant PIFR2_PEV2A \ External Event A Interrupt
- $06 constant PIFR2_PRN2 \ Ramp Number
- $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&59 constant GPIOR3 \ General Purpose IO Register 3
- $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $E0 constant PRR_PRPSC \ Power Reduction PSC2
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
-&126 constant DIDR0 \ Digital Input Disable Register 0
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $20 constant DIDR1_ACMP0D \
- $10 constant DIDR1_AMP0PD \
- $08 constant DIDR1_AMP0ND \
- $04 constant DIDR1_ADC10D \
- $02 constant DIDR1_ADC9D \
- $01 constant DIDR1_ADC8D \
-&118 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $03 constant AMP0CSR_AMP0TS \
-&119 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $03 constant AMP1CSR_AMP1TS \
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ ANALOG_COMPARATOR
-&173 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&175 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ PSC1
-&238 constant PICR1 \ PSC 1 Input Capture Register
-&237 constant PFRC1B \ PSC 1 Input B Control
- $80 constant PFRC1B_PCAE1B \ PSC 1 Capture Enable Input Part B
- $40 constant PFRC1B_PISEL1B \ PSC 1 Input Select for Part B
- $20 constant PFRC1B_PELEV1B \ PSC 1 Edge Level Selector on Input Part B
- $10 constant PFRC1B_PFLTE1B \ PSC 1 Filter Enable on Input Part B
- $0F constant PFRC1B_PRFM1B \ PSC 1 Retrigger and Fault Mode for Part B
-&236 constant PFRC1A \ PSC 1 Input B Control
- $80 constant PFRC1A_PCAE1A \ PSC 1 Capture Enable Input Part A
- $40 constant PFRC1A_PISEL1A \ PSC 1 Input Select for Part A
- $20 constant PFRC1A_PELEV1A \ PSC 1 Edge Level Selector on Input Part A
- $10 constant PFRC1A_PFLTE1A \ PSC 1 Filter Enable on Input Part A
- $0F constant PFRC1A_PRFM1A \ PSC 1 Retrigger and Fault Mode for Part A
-&235 constant PCTL1 \ PSC 1 Control Register
- $C0 constant PCTL1_PPRE1 \ PSC 1 Prescaler Selects
- $20 constant PCTL1_PBFM1 \ Balance Flank Width Modulation
- $10 constant PCTL1_PAOC1B \ PSC 1 Asynchronous Output Control B
- $08 constant PCTL1_PAOC1A \ PSC 1 Asynchronous Output Control A
- $04 constant PCTL1_PARUN1 \ PSC1 Auto Run
- $02 constant PCTL1_PCCYC1 \ PSC1 Complete Cycle
- $01 constant PCTL1_PRUN1 \ PSC 1 Run
-&224 constant PSOC1 \ PSC1 Synchro and Output Configuration
- $30 constant PSOC1_PSYNC1_ \ Synchronization Out for ADC Selection
- $04 constant PSOC1_POEN1B \ PSCOUT11 Output Enable
- $01 constant PSOC1_POEN1A \ PSCOUT10 Output Enable
-
-\ Interrupts
-&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
-&2 constant PSC2_ECAddr \ PSC2 End Cycle
-&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
-&4 constant PSC1_ECAddr \ PSC1 End Cycle
-&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
-&6 constant PSC0_ECAddr \ PSC0 End Cycle
-&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-&10 constant INT0Addr \ External Interrupt Request 0
-&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&14 constant RESERVED15Addr \
-&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&18 constant ADCAddr \ ADC Conversion Complete
-&19 constant INT1Addr \ External Interrupt Request 1
-&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&21 constant USART__RXAddr \ USART, Rx Complete
-&22 constant USART__UDREAddr \ USART Data Register Empty
-&23 constant USART__TXAddr \ USART, Tx Complete
-&24 constant INT2Addr \ External Interrupt Request 2
-&25 constant WDTAddr \ Watchdog Timeout Interrupt
-&26 constant EE_READYAddr \ EEPROM Ready
-&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-&28 constant INT3Addr \ External Interrupt Request 3
-&29 constant RESERVED30Addr \
-&30 constant RESERVED31Addr \
-&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm1/device.asm b/amforth-6.5/avr8/devices/at90pwm1/device.asm
deleted file mode 100644
index af0c2c0..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/device.asm
+++ /dev/null
@@ -1,121 +0,0 @@
-; Partname: AT90PWM1
-; generated automatically, do not edit
-
-.nolist
- .include "pwm1def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC2 = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PSC1 = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; PSC2 Capture Event
-.org 2
- rcall isr ; PSC2 End Cycle
-.org 3
- rcall isr ; PSC1 Capture Event
-.org 4
- rcall isr ; PSC1 End Cycle
-.org 5
- rcall isr ; PSC0 Capture Event
-.org 6
- rcall isr ; PSC0 End Cycle
-.org 7
- rcall isr ; Analog Comparator 0
-.org 8
- rcall isr ; Analog Comparator 1
-.org 9
- rcall isr ; Analog Comparator 2
-.org 10
- rcall isr ; External Interrupt Request 0
-.org 11
- rcall isr ; Timer/Counter1 Capture Event
-.org 12
- rcall isr ; Timer/Counter1 Compare Match A
-.org 13
- rcall isr ; Timer/Counter Compare Match B
-.org 14
- rcall isr ;
-.org 15
- rcall isr ; Timer/Counter1 Overflow
-.org 16
- rcall isr ; Timer/Counter0 Compare Match A
-.org 17
- rcall isr ; Timer/Counter0 Overflow
-.org 18
- rcall isr ; ADC Conversion Complete
-.org 19
- rcall isr ; External Interrupt Request 1
-.org 20
- rcall isr ; SPI Serial Transfer Complete
-.org 21
- rcall isr ; USART, Rx Complete
-.org 22
- rcall isr ; USART Data Register Empty
-.org 23
- rcall isr ; USART, Tx Complete
-.org 24
- rcall isr ; External Interrupt Request 2
-.org 25
- rcall isr ; Watchdog Timeout Interrupt
-.org 26
- rcall isr ; EEPROM Ready
-.org 27
- rcall isr ; Timer Counter 0 Compare Match B
-.org 28
- rcall isr ; External Interrupt Request 3
-.org 29
- rcall isr ;
-.org 30
- rcall isr ;
-.org 31
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 32
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 8
- .db "AT90PWM1"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm1/device.inc b/amforth-6.5/avr8/devices/at90pwm1/device.inc
deleted file mode 100644
index 0b15f67..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/device.inc
+++ /dev/null
@@ -1,1143 +0,0 @@
-; Partname: AT90PWM1
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PSC0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register
-VE_PICR0:
- .dw $ff05
- .db "PICR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0
-XT_PICR0:
- .dw PFA_DOVARIABLE
-PFA_PICR0:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR0RB:
- .dw $ff06
- .db "OCR0RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RB
-XT_OCR0RB:
- .dw PFA_DOVARIABLE
-PFA_OCR0RB:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR0SB:
- .dw $ff06
- .db "OCR0SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SB
-XT_OCR0SB:
- .dw PFA_DOVARIABLE
-PFA_OCR0SB:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR0RA:
- .dw $ff06
- .db "OCR0RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RA
-XT_OCR0RA:
- .dw PFA_DOVARIABLE
-PFA_OCR0RA:
- .dw 212
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR0SA:
- .dw $ff06
- .db "OCR0SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SA
-XT_OCR0SA:
- .dw PFA_DOVARIABLE
-PFA_OCR0SA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw 160
-
-.endif
-.if WANT_PSC2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register
-VE_PICR2:
- .dw $ff05
- .db "PICR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2
-XT_PICR2:
- .dw PFA_DOVARIABLE
-PFA_PICR2:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR2RB:
- .dw $ff06
- .db "OCR2RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RB
-XT_OCR2RB:
- .dw PFA_DOVARIABLE
-PFA_OCR2RB:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR2SB:
- .dw $ff06
- .db "OCR2SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SB
-XT_OCR2SB:
- .dw PFA_DOVARIABLE
-PFA_OCR2SB:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR2RA:
- .dw $ff06
- .db "OCR2RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RA
-XT_OCR2RA:
- .dw PFA_DOVARIABLE
-PFA_OCR2RA:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR2SA:
- .dw $ff06
- .db "OCR2SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SA
-XT_OCR2SA:
- .dw PFA_DOVARIABLE
-PFA_OCR2SA:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw 164
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 119
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_PSC1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input Capture Register
-VE_PICR1:
- .dw $ff05
- .db "PICR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR1
-XT_PICR1:
- .dw PFA_DOVARIABLE
-PFA_PICR1:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1B:
- .dw $ff06
- .db "PFRC1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1B
-XT_PFRC1B:
- .dw PFA_DOVARIABLE
-PFA_PFRC1B:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1A:
- .dw $ff06
- .db "PFRC1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1A
-XT_PFRC1A:
- .dw PFA_DOVARIABLE
-PFA_PFRC1A:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Control Register
-VE_PCTL1:
- .dw $ff05
- .db "PCTL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL1
-XT_PCTL1:
- .dw PFA_DOVARIABLE
-PFA_PCTL1:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Synchro and Output Configuration
-VE_PSOC1:
- .dw $ff05
- .db "PSOC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC1
-XT_PSOC1:
- .dw PFA_DOVARIABLE
-PFA_PSOC1:
- .dw 224
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm1/device.py b/amforth-6.5/avr8/devices/at90pwm1/device.py
deleted file mode 100644
index a9cd0bd..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/device.py
+++ /dev/null
@@ -1,404 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM1
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
- 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
- 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
- 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
- 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'RESERVED15Addr' : '#28', #
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'ADCAddr' : '#36', # ADC Conversion Complete
- 'INT1Addr' : '#38', # External Interrupt Request 1
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#42', # USART, Rx Complete
- 'USART_UDREAddr' : '#44', # USART Data Register Empty
- 'USART_TXAddr' : '#46', # USART, Tx Complete
- 'INT2Addr' : '#48', # External Interrupt Request 2
- 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
- 'INT3Addr' : '#56', # External Interrupt Request 3
- 'RESERVED30Addr' : '#58', #
- 'RESERVED31Addr' : '#60', #
- 'SPM_READYAddr' : '#62', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PSC0
- 'PICR0' : '$de', # PSC 0 Input Capture Register
- 'PFRC0B' : '$dd', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$dc', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$db', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$da', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$d8', # Output Compare RB Register
- 'OCR0SB' : '$d6', # Output Compare SB Register
- 'OCR0RA' : '$d4', # Output Compare RA Register
- 'OCR0SA' : '$d2', # Output Compare SA Register
- 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
- 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
- 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
- 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC2
- 'PICR2' : '$fe', # PSC 2 Input Capture Register
- 'PFRC2B' : '$fd', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$fc', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$fb', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$fa', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'OCR2RB' : '$f8', # Output Compare RB Register
- 'OCR2SB' : '$f6', # Output Compare SB Register
- 'OCR2RA' : '$f4', # Output Compare RA Register
- 'OCR2SA' : '$f2', # Output Compare SA Register
- 'POM2' : '$f1', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR3' : '$3b', # General Purpose IO Register 3
- 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRPSC': '$e0', # Power Reduction PSC2
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_ACMP0D': '$20', #
- 'DIDR1_AMP0PD': '$10', #
- 'DIDR1_AMP0ND': '$8', #
- 'DIDR1_ADC10D': '$4', #
- 'DIDR1_ADC9D': '$2', #
- 'DIDR1_ADC8D': '$1', #
- 'AMP0CSR' : '$76', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0TS': '$3', #
- 'AMP1CSR' : '$77', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMP1TS': '$3', #
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC2CON' : '$af', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module PSC1
- 'PICR1' : '$ee', # PSC 1 Input Capture Register
- 'PFRC1B' : '$ed', # PSC 1 Input B Control
- 'PFRC1B_PCAE1B': '$80', # PSC 1 Capture Enable Input Par
- 'PFRC1B_PISEL1B': '$40', # PSC 1 Input Select for Part B
- 'PFRC1B_PELEV1B': '$20', # PSC 1 Edge Level Selector on I
- 'PFRC1B_PFLTE1B': '$10', # PSC 1 Filter Enable on Input P
- 'PFRC1B_PRFM1B': '$f', # PSC 1 Retrigger and Fault Mode
- 'PFRC1A' : '$ec', # PSC 1 Input B Control
- 'PFRC1A_PCAE1A': '$80', # PSC 1 Capture Enable Input Par
- 'PFRC1A_PISEL1A': '$40', # PSC 1 Input Select for Part A
- 'PFRC1A_PELEV1A': '$20', # PSC 1 Edge Level Selector on I
- 'PFRC1A_PFLTE1A': '$10', # PSC 1 Filter Enable on Input P
- 'PFRC1A_PRFM1A': '$f', # PSC 1 Retrigger and Fault Mode
- 'PCTL1' : '$eb', # PSC 1 Control Register
- 'PCTL1_PPRE1': '$c0', # PSC 1 Prescaler Selects
- 'PCTL1_PBFM1': '$20', # Balance Flank Width Modulation
- 'PCTL1_PAOC1B': '$10', # PSC 1 Asynchronous Output Cont
- 'PCTL1_PAOC1A': '$8', # PSC 1 Asynchronous Output Cont
- 'PCTL1_PARUN1': '$4', # PSC1 Auto Run
- 'PCTL1_PCCYC1': '$2', # PSC1 Complete Cycle
- 'PCTL1_PRUN1': '$1', # PSC 1 Run
- 'PSOC1' : '$e0', # PSC1 Synchro and Output Config
- 'PSOC1_PSYNC1_': '$30', # Synchronization Out for ADC Se
- 'PSOC1_POEN1B': '$4', # PSCOUT11 Output Enable
- 'PSOC1_POEN1A': '$1', # PSCOUT10 Output Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt
deleted file mode 100644
index 9464801..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,71 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$28 constant ADMUX \ The ADC multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 28 $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- 28 $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
- $f constant ADMUX_MUX \ Analog Channel and Gain Select
- 28 $f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$26 constant ADCSRA \ The ADC Control and Status reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 26 $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 26 $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 26 $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 26 $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 26 $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 26 $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$4c constant ADC \ ADC Data Register Bytes
-$27 constant ADCSRB \ ADC Control and Status Registe
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- 27 $80 bitmask: ADCSRB.ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
- 27 $40 bitmask: ADCSRB.ADNCDIS \ ADC Noise Canceller Disable
- $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC'
- 27 $10 bitmask: ADCSRB.ADSSEN \ ADC Single Shot Enable on PSC'
- $f constant ADCSRB_ADTS \ ADC Auto Trigger Sources
- 27 $f bitmask: ADCSRB.ADTS \ ADC Auto Trigger Sources
-$77 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- 77 $80 bitmask: DIDR0.ADC7D \
- $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
- 77 $40 bitmask: DIDR0.ADC6D \ ADC7 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- 77 $20 bitmask: DIDR0.ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- 77 $10 bitmask: DIDR0.ADC4D \ ADC4 Digital input Disable
- $8 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- 77 $8 bitmask: DIDR0.ADC3D \ ADC3 Digital input Disable
- $4 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- 77 $4 bitmask: DIDR0.ADC2D \ ADC2 Digital input Disable
- $2 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- 77 $2 bitmask: DIDR0.ADC1D \ ADC1 Digital input Disable
- $1 constant DIDR0_ADC0D \ ADC0 Digital input Disable
- 77 $1 bitmask: DIDR0.ADC0D \ ADC0 Digital input Disable
-$78 constant DIDR1 \ Digital Input Disable Register
- $8 constant DIDR1_ACMP1MD \
- 78 $8 bitmask: DIDR1.ACMP1MD \
- $4 constant DIDR1_AMP0POSD \
- 78 $4 bitmask: DIDR1.AMP0POSD \
- $2 constant DIDR1_ADC10D \
- 78 $2 bitmask: DIDR1.ADC10D \
- $1 constant DIDR1_ADC9D \
- 78 $1 bitmask: DIDR1.ADC9D \
-$79 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- 79 $80 bitmask: AMP0CSR.AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- 79 $40 bitmask: AMP0CSR.AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- 79 $30 bitmask: AMP0CSR.AMP0G \
- $8 constant AMP0CSR_AMP0GS \
- 79 $8 bitmask: AMP0CSR.AMP0GS \
- $3 constant AMP0CSR_AMP0TS \
- 79 $3 bitmask: AMP0CSR.AMP0TS \
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index 1db32bc..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,69 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7f constant AC3CON \ Analog Comparator3 Control Reg
- $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
- 7f $80 bitmask: AC3CON.AC3EN \ Analog Comparator3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt
- 7f $40 bitmask: AC3CON.AC3IE \ Analog Comparator 3 Interrupt
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt
- 7f $30 bitmask: AC3CON.AC3IS \ Analog Comparator 3 Interrupt
- $8 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate
- 7f $8 bitmask: AC3CON.AC3OEA \ Analog Comparator 3 Alternate
- $7 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexe
- 7f $7 bitmask: AC3CON.AC3M \ Analog Comparator 3 Multiplexe
-$7d constant AC1CON \ Analog Comparator 1 Control Re
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- 7d $80 bitmask: AC1CON.AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt
- 7d $40 bitmask: AC1CON.AC1IE \ Analog Comparator 1 Interrupt
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt
- 7d $30 bitmask: AC1CON.AC1IS \ Analog Comparator 1 Interrupt
- $7 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexe
- 7d $7 bitmask: AC1CON.AC1M \ Analog Comparator 1 Multiplexe
-$7e constant AC2CON \ Analog Comparator 2 Control Re
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- 7e $80 bitmask: AC2CON.AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt
- 7e $40 bitmask: AC2CON.AC2IE \ Analog Comparator 2 Interrupt
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt
- 7e $30 bitmask: AC2CON.AC2IS \ Analog Comparator 2 Interrupt
- $7 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexe
- 7e $7 bitmask: AC2CON.AC2M \ Analog Comparator 2 Multiplexe
-$20 constant ACSR \ Analog Comparator Status Regis
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt
- 20 $80 bitmask: ACSR.AC3IF \ Analog Comparator 3 Interrupt
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt
- 20 $40 bitmask: ACSR.AC2IF \ Analog Comparator 2 Interrupt
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt
- 20 $20 bitmask: ACSR.AC1IF \ Analog Comparator 1 Interrupt
- $8 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- 20 $8 bitmask: ACSR.AC3O \ Analog Comparator 3 Output Bit
- $4 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- 20 $4 bitmask: ACSR.AC2O \ Analog Comparator 2 Output Bit
- $2 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- 20 $2 bitmask: ACSR.AC1O \ Analog Comparator 1 Output Bit
-$7c constant AC3ECON \
- $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
- 7c $20 bitmask: AC3ECON.AC3OI \ Analog Comparator Ouput Invert
- $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
- 7c $10 bitmask: AC3ECON.AC3OE \ Analog Comparator Ouput Enable
- $7 constant AC3ECON_AC3H \ Analog Comparator Hysteresis S
- 7c $7 bitmask: AC3ECON.AC3H \ Analog Comparator Hysteresis S
-$7b constant AC2ECON \
- $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
- 7b $20 bitmask: AC2ECON.AC2OI \ Analog Comparator Ouput Invert
- $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
- 7b $10 bitmask: AC2ECON.AC2OE \ Analog Comparator Ouput Enable
- $7 constant AC2ECON_AC2H \ Analog Comparator Hysteresis S
- 7b $7 bitmask: AC2ECON.AC2H \ Analog Comparator Hysteresis S
-$7a constant AC1ECON \
- $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
- 7a $20 bitmask: AC1ECON.AC1OI \ Analog Comparator Ouput Invert
- $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
- 7a $10 bitmask: AC1ECON.AC1OE \ Analog Comparator Ouput Enable
- $8 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Ca
- 7a $8 bitmask: AC1ECON.AC1ICE \ Analog Comparator Interrupt Ca
- $7 constant AC1ECON_AC1H \ Analog Comparator Hysteresis S
- 7a $7 bitmask: AC1ECON.AC1H \ Analog Comparator Hysteresis S
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt
deleted file mode 100644
index 37089a7..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt
deleted file mode 100644
index 37032ab..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt
+++ /dev/null
@@ -1,114 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
- $8 constant MCUCR_RSTDIS \ Reset Pin Disable
- 55 $8 bitmask: MCUCR.RSTDIS \ Reset Pin Disable
- $4 constant MCUCR_CKRC81 \ Frequency Selection of the Cal
- 55 $4 bitmask: MCUCR.CKRC81 \ Frequency Selection of the Cal
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on reset flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
-$88 constant OSCCAL \ Oscillator Calibration Value
-$83 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- 83 $80 bitmask: CLKPR.CLKPCE \
- $f constant CLKPR_CLKPS \
- 83 $f bitmask: CLKPR.CLKPS \
-$53 constant SMCR \ Sleep Mode Control Register
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$3b constant GPIOR2 \ General Purpose IO Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
- 3b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
-$3a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
- 3a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
-$39 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
- 39 $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
- 39 $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
- 39 $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
- 39 $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
- 39 $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
- 39 $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
- 39 $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
- 39 $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
-$87 constant PLLCSR \ PLL Control And Status Registe
- $3c constant PLLCSR_PLLF \
- 87 $3c bitmask: PLLCSR.PLLF \
- $2 constant PLLCSR_PLLE \ PLL Enable
- 87 $2 bitmask: PLLCSR.PLLE \ PLL Enable
- $1 constant PLLCSR_PLOCK \ PLL Lock Detector
- 87 $1 bitmask: PLLCSR.PLOCK \ PLL Lock Detector
-$86 constant PRR \ Power Reduction Register
- $80 constant PRR_PRPSC2 \ Power Reduction PSC2
- 86 $80 bitmask: PRR.PRPSC2 \ Power Reduction PSC2
- $20 constant PRR_PRPSCR \ Power Reduction PSC0
- 86 $20 bitmask: PRR.PRPSCR \ Power Reduction PSC0
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- 86 $10 bitmask: PRR.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR_PRSPI \ Power Reduction Serial Periphe
- 86 $4 bitmask: PRR.PRSPI \ Power Reduction Serial Periphe
- $1 constant PRR_PRADC \ Power Reduction ADC
- 86 $1 bitmask: PRR.PRADC \ Power Reduction ADC
-$84 constant CLKCSR \
- $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
- 84 $80 bitmask: CLKCSR.CLKCCE \ Clock Control Change Enable
- $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
- 84 $10 bitmask: CLKCSR.CLKRDY \ Clock Ready Flag
- $f constant CLKCSR_CLKC \ Clock Control
- 84 $f bitmask: CLKCSR.CLKC \ Clock Control
-$85 constant CLKSELR \
- $40 constant CLKSELR_COUT \ Clock OUT
- 85 $40 bitmask: CLKSELR.COUT \ Clock OUT
- $30 constant CLKSELR_CSUT \ Clock Start up Time
- 85 $30 bitmask: CLKSELR.CSUT \ Clock Start up Time
- $f constant CLKSELR_CKSEL \ Clock Source Select
- 85 $f bitmask: CLKSELR.CKSEL \ Clock Source Select
-$81 constant BGCCR \ BandGap Current Calibration Re
- $f constant BGCCR_BGCC \
- 81 $f bitmask: BGCCR.BGCC \
-$80 constant BGCRR \ BandGap Resistor Calibration R
- $f constant BGCRR_BGCR \
- 80 $f bitmask: BGCRR.BGCR \
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt
deleted file mode 100644
index 9c36fb7..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ DA_CONVERTER
-$59 constant DACH \ DAC Data Register High Byte
- $ff constant DACH_DACH \ DAC Data Register High Byte Bi
- 59 $ff bitmask: DACH.DACH \ DAC Data Register High Byte Bi
-$58 constant DACL \ DAC Data Register Low Byte
- $ff constant DACL_DACL \ DAC Data Register Low Byte Bit
- 58 $ff bitmask: DACL.DACL \ DAC Data Register Low Byte Bit
-$76 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- 76 $80 bitmask: DACON.DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- 76 $70 bitmask: DACON.DATS \ DAC Trigger Selection Bits
- $4 constant DACON_DALA \ DAC Left Adjust
- 76 $4 bitmask: DACON.DALA \ DAC Left Adjust
- $1 constant DACON_DAEN \ DAC Enable Bit
- 76 $1 bitmask: DACON.DAEN \ DAC Enable Bit
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt
deleted file mode 100644
index b30d081..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ EEPROM
-$3e constant EEAR \ EEPROM Read/Write Access Byte
-$3d constant EEDR \ EEPROM Data Register
-$3c constant EECR \ EEPROM Control Register
- $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
- 3c $80 bitmask: EECR.NVMBSY \ None Volatile Busy Memory Busy
- $40 constant EECR_EEPAGE \ EEPROM Page Access
- 3c $40 bitmask: EECR.EEPAGE \ EEPROM Page Access
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3c $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3c $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMWE \ EEPROM Master Write Enable
- 3c $4 bitmask: EECR.EEMWE \ EEPROM Master Write Enable
- $2 constant EECR_EEWE \ EEPROM Write Enable
- 3c $2 bitmask: EECR.EEWE \ EEPROM Write Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3c $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 6a0ecdc..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,17 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$89 constant EICRA \ External Interrupt Control Reg
- $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
- 89 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
- $c constant EICRA_ISC1 \ External Interrupt Sense Contr
- 89 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
- $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
- 89 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
-$41 constant EIMSK \ External Interrupt Mask Regist
- $7 constant EIMSK_INT \ External Interrupt Request 2 E
- 41 $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
-$40 constant EIFR \ External Interrupt Flag Regist
- $7 constant EIFR_INTF \ External Interrupt Flags
- 40 $7 bitmask: EIFR.INTF \ External Interrupt Flags
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt
deleted file mode 100644
index 14612b5..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt
deleted file mode 100644
index a45e474..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt
deleted file mode 100644
index f774d19..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt
deleted file mode 100644
index 3774cfe..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt
+++ /dev/null
@@ -1,90 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ PSC0
-$68 constant PICR0 \ PSC 0 Input Capture Register
-$63 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Par
- 63 $80 bitmask: PFRC0B.PCAE0B \ PSC 0 Capture Enable Input Par
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- 63 $40 bitmask: PFRC0B.PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on I
- 63 $20 bitmask: PFRC0B.PELEV0B \ PSC 0 Edge Level Selector on I
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input P
- 63 $10 bitmask: PFRC0B.PFLTE0B \ PSC 0 Filter Enable on Input P
- $f constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode
- 63 $f bitmask: PFRC0B.PRFM0B \ PSC 0 Retrigger and Fault Mode
-$62 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Par
- 62 $80 bitmask: PFRC0A.PCAE0A \ PSC 0 Capture Enable Input Par
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- 62 $40 bitmask: PFRC0A.PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on I
- 62 $20 bitmask: PFRC0A.PELEV0A \ PSC 0 Edge Level Selector on I
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input P
- 62 $10 bitmask: PFRC0A.PFLTE0A \ PSC 0 Filter Enable on Input P
- $f constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode
- 62 $f bitmask: PFRC0A.PRFM0A \ PSC 0 Retrigger and Fault Mode
-$32 constant PCTL0 \ PSC 0 Control Register
- $c0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- 32 $c0 bitmask: PCTL0.PPRE0 \ PSC 0 Prescaler Selects
- $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modu
- 32 $24 bitmask: PCTL0.PBFM0 \ PSC 0 Balance Flank Width Modu
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Cont
- 32 $10 bitmask: PCTL0.PAOC0B \ PSC 0 Asynchronous Output Cont
- $8 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Cont
- 32 $8 bitmask: PCTL0.PAOC0A \ PSC 0 Asynchronous Output Cont
- $2 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- 32 $2 bitmask: PCTL0.PCCYC0 \ PSC0 Complete Cycle
- $1 constant PCTL0_PRUN0 \ PSC 0 Run
- 32 $1 bitmask: PCTL0.PRUN0 \ PSC 0 Run
-$31 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- 31 $80 bitmask: PCNF0.PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- 31 $40 bitmask: PCNF0.PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- 31 $20 bitmask: PCNF0.PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- 31 $18 bitmask: PCNF0.PMODE0 \ PSC 0 Mode
- $4 constant PCNF0_POP0 \ PSC 0 Output Polarity
- 31 $4 bitmask: PCNF0.POP0 \ PSC 0 Output Polarity
- $2 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
- 31 $2 bitmask: PCNF0.PCLKSEL0 \ PSC 0 Input Clock Select
-$44 constant OCR0RB \ Output Compare RB Register
-$42 constant OCR0SB \ Output Compare SB Register
-$4a constant OCR0RA \ Output Compare RA Register
-$60 constant OCR0SA \ Output Compare SA Register
-$6a constant PSOC0 \ PSC0 Synchro and Output Config
- $80 constant PSOC0_PISEL0A1 \ PSC Input Select
- 6a $80 bitmask: PSOC0.PISEL0A1 \ PSC Input Select
- $40 constant PSOC0_PISEL0B1 \ PSC Input Select
- 6a $40 bitmask: PSOC0.PISEL0B1 \ PSC Input Select
- $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC se
- 6a $30 bitmask: PSOC0.PSYNC0 \ Synchronisation out for ADC se
- $4 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- 6a $4 bitmask: PSOC0.POEN0B \ PSCOUT01 Output Enable
- $1 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
- 6a $1 bitmask: PSOC0.POEN0A \ PSCOUT00 Output Enable
-$2f constant PIM0 \ PSC0 Interrupt Mask Register
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Ena
- 2f $10 bitmask: PIM0.PEVE0B \ External Event B Interrupt Ena
- $8 constant PIM0_PEVE0A \ External Event A Interrupt Ena
- 2f $8 bitmask: PIM0.PEVE0A \ External Event A Interrupt Ena
- $2 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
- 2f $2 bitmask: PIM0.PEOEPE0 \ End of Enhanced Cycle Enable
- $1 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
- 2f $1 bitmask: PIM0.PEOPE0 \ End of Cycle Interrupt Enable
-$30 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- 30 $80 bitmask: PIFR0.POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- 30 $40 bitmask: PIFR0.POAC0A \ PSC 0 Output A Activity
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- 30 $10 bitmask: PIFR0.PEV0B \ External Event B Interrupt
- $8 constant PIFR0_PEV0A \ External Event A Interrupt
- 30 $8 bitmask: PIFR0.PEV0A \ External Event A Interrupt
- $6 constant PIFR0_PRN0 \ Ramp Number
- 30 $6 bitmask: PIFR0.PRN0 \ Ramp Number
- $1 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
- 30 $1 bitmask: PIFR0.PEOP0 \ End of PSC0 Interrupt
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt
deleted file mode 100644
index 68acc9f..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt
+++ /dev/null
@@ -1,126 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ PSC2
-$6d constant PICR2H \ PSC 2 Input Capture Register H
- $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger
- 6d $80 bitmask: PICR2H.PCST2 \ PSC 2 Capture Software Trigger
- $c constant PICR2H_PICR21 \
- 6d $c bitmask: PICR2H.PICR21 \
- $3 constant PICR2H_PICR2 \
- 6d $3 bitmask: PICR2H.PICR2 \
-$6c constant PICR2L \ PSC 2 Input Capture Register L
-$67 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Par
- 67 $80 bitmask: PFRC2B.PCAE2B \ PSC 2 Capture Enable Input Par
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- 67 $40 bitmask: PFRC2B.PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on I
- 67 $20 bitmask: PFRC2B.PELEV2B \ PSC 2 Edge Level Selector on I
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input P
- 67 $10 bitmask: PFRC2B.PFLTE2B \ PSC 2 Filter Enable on Input P
- $f constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode
- 67 $f bitmask: PFRC2B.PRFM2B \ PSC 2 Retrigger and Fault Mode
-$66 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Par
- 66 $80 bitmask: PFRC2A.PCAE2A \ PSC 2 Capture Enable Input Par
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- 66 $40 bitmask: PFRC2A.PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on I
- 66 $20 bitmask: PFRC2A.PELEV2A \ PSC 2 Edge Level Selector on I
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input P
- 66 $10 bitmask: PFRC2A.PFLTE2A \ PSC 2 Filter Enable on Input P
- $f constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode
- 66 $f bitmask: PFRC2A.PRFM2A \ PSC 2 Retrigger and Fault Mode
-$36 constant PCTL2 \ PSC 2 Control Register
- $c0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- 36 $c0 bitmask: PCTL2.PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- 36 $20 bitmask: PCTL2.PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Cont
- 36 $10 bitmask: PCTL2.PAOC2B \ PSC 2 Asynchronous Output Cont
- $8 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Cont
- 36 $8 bitmask: PCTL2.PAOC2A \ PSC 2 Asynchronous Output Cont
- $4 constant PCTL2_PARUN2 \ PSC2 Auto Run
- 36 $4 bitmask: PCTL2.PARUN2 \ PSC2 Auto Run
- $2 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- 36 $2 bitmask: PCTL2.PCCYC2 \ PSC2 Complete Cycle
- $1 constant PCTL2_PRUN2 \ PSC 2 Run
- 36 $1 bitmask: PCTL2.PRUN2 \ PSC 2 Run
-$35 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- 35 $80 bitmask: PCNF2.PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- 35 $40 bitmask: PCNF2.PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- 35 $20 bitmask: PCNF2.PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- 35 $18 bitmask: PCNF2.PMODE2 \ PSC 2 Mode
- $4 constant PCNF2_POP2 \ PSC 2 Output Polarity
- 35 $4 bitmask: PCNF2.POP2 \ PSC 2 Output Polarity
- $2 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- 35 $2 bitmask: PCNF2.PCLKSEL2 \ PSC 2 Input Clock Select
- $1 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
- 35 $1 bitmask: PCNF2.POME2 \ PSC 2 Output Matrix Enable
-$70 constant PCNFE2 \ PSC 2 Enhanced Configuration R
- $e0 constant PCNFE2_PASDLK2 \
- 70 $e0 bitmask: PCNFE2.PASDLK2 \
- $10 constant PCNFE2_PBFM21 \
- 70 $10 bitmask: PCNFE2.PBFM21 \
- $8 constant PCNFE2_PELEV2A1 \
- 70 $8 bitmask: PCNFE2.PELEV2A1 \
- $4 constant PCNFE2_PELEV2B1 \
- 70 $4 bitmask: PCNFE2.PELEV2B1 \
- $2 constant PCNFE2_PISEL2A1 \
- 70 $2 bitmask: PCNFE2.PISEL2A1 \
- $1 constant PCNFE2_PISEL2B1 \
- 70 $1 bitmask: PCNFE2.PISEL2B1 \
-$48 constant OCR2RB \ Output Compare RB Register
-$46 constant OCR2SB \ Output Compare SB Register
-$4e constant OCR2RA \ Output Compare RA Register
-$64 constant OCR2SA \ Output Compare SA Register
-$6f constant POM2 \ PSC 2 Output Matrix
- $f0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- 6f $f0 bitmask: POM2.POMV2B \ Output Matrix Output B Ramps
- $f constant POM2_POMV2A \ Output Matrix Output A Ramps
- 6f $f bitmask: POM2.POMV2A \ Output Matrix Output A Ramps
-$6e constant PSOC2 \ PSC2 Synchro and Output Config
- $c0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- 6e $c0 bitmask: PSOC2.POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Se
- 6e $30 bitmask: PSOC2.PSYNC2 \ Synchronization Out for ADC Se
- $8 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- 6e $8 bitmask: PSOC2.POEN2D \ PSCOUT23 Output Enable
- $4 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- 6e $4 bitmask: PSOC2.POEN2B \ PSCOUT21 Output Enable
- $2 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- 6e $2 bitmask: PSOC2.POEN2C \ PSCOUT22 Output Enable
- $1 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
- 6e $1 bitmask: PSOC2.POEN2A \ PSCOUT20 Output Enable
-$33 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt
- 33 $20 bitmask: PIM2.PSEIE2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Ena
- 33 $10 bitmask: PIM2.PEVE2B \ External Event B Interrupt Ena
- $8 constant PIM2_PEVE2A \ External Event A Interrupt Ena
- 33 $8 bitmask: PIM2.PEVE2A \ External Event A Interrupt Ena
- $2 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrup
- 33 $2 bitmask: PIM2.PEOEPE2 \ End of Enhanced Cycle Interrup
- $1 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
- 33 $1 bitmask: PIM2.PEOPE2 \ End of Cycle Interrupt Enable
-$34 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- 34 $80 bitmask: PIFR2.POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- 34 $40 bitmask: PIFR2.POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- 34 $20 bitmask: PIFR2.PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- 34 $10 bitmask: PIFR2.PEV2B \ External Event B Interrupt
- $8 constant PIFR2_PEV2A \ External Event A Interrupt
- 34 $8 bitmask: PIFR2.PEV2A \ External Event A Interrupt
- $6 constant PIFR2_PRN2 \ Ramp Number
- 34 $6 bitmask: PIFR2.PRN2 \ Ramp Number
- $1 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
- 34 $1 bitmask: PIFR2.PEOP2 \ End of PSC2 Interrupt
-$71 constant PASDLY2 \ Analog Synchronization Delay R
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt
deleted file mode 100644
index 190bab5..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ SPI
-$37 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 37 $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 37 $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 37 $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 37 $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Selects
- 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects
-$38 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$56 constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index 3e17b16..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,25 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$21 constant TIMSK1 \ Timer/Counter Interrupt Mask R
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 21 $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 21 $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$22 constant TIFR1 \ Timer/Counter Interrupt Flag r
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- 22 $20 bitmask: TIFR1.ICF1 \ Input Capture Flag 1
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 22 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-$8a constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- 8a $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 8a $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
- 8a $10 bitmask: TCCR1B.WGM13 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Prescaler source of Timer/Coun
- 8a $7 bitmask: TCCR1B.CS1 \ Prescaler source of Timer/Coun
-$5a constant TCNT1 \ Timer/Counter1 Bytes
-$8c constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt
deleted file mode 100644
index 1772bac..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for at90pwm161
-\ #require bitnames.frt
-
-\ WATCHDOG
-$82 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 82 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 82 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 82 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 82 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 82 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.asm b/amforth-6.5/avr8/devices/at90pwm161/device.asm
deleted file mode 100644
index 8bf16d2..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/device.asm
+++ /dev/null
@@ -1,52 +0,0 @@
-; Generated Automatically
-
-.nolist
- include "pwm161def.inc"
-.list
-FLASHSTART = 0
-FLASHSIZE = 16384
-RAMEND = 1280
-IRAMSTART = 256
-IRAMSIZE = 1024
-EEPROMSIZE = 512
-; Interrupt Vectors
-.overlap
-.org 2
- rcall isr ; PSC2 Capture Event
-.org 4
- rcall isr ; PSC2 End Cycle
-.org 6
- rcall isr ; PSC2 End Of Enhanced Cycle
-.org 8
- rcall isr ; PSC0 Capture Event
-.org 10
- rcall isr ; PSC0 End Cycle
-.org 12
- rcall isr ; PSC0 End Of Enhanced Cycle
-.org 14
- rcall isr ; Analog Comparator 1
-.org 16
- rcall isr ; Analog Comparator 2
-.org 18
- rcall isr ; Analog Comparator 3
-.org 20
- rcall isr ; External Interrupt Request 0
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Overflow
-.org 26
- rcall isr ; ADC Conversion Complete
-.org 28
- rcall isr ; External Interrupt Request 1
-.org 30
- rcall isr ; SPI Serial Transfer Complet
-.org 32
- rcall isr ; External Interrupt Request 2
-.org 34
- rcall isr ; Watchdog Timeout Interrupt
-.org 36
- rcall isr ; EEPROM Ready
-.org 38
- rcall isr ; Store Program Memory Read
-.nooverlap
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.frt b/amforth-6.5/avr8/devices/at90pwm161/device.frt
deleted file mode 100644
index 00c4728..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/device.frt
+++ /dev/null
@@ -1,613 +0,0 @@
-\ Generated Automatically
-
-\ Interrupt Vectors
-#2 constant PSC2_CAPTAddr \ PSC2 Capture Event
-#4 constant PSC2_ECAddr \ PSC2 End Cycle
-#6 constant PSC2_EECAddr \ PSC2 End Of Enhanced Cycle
-#8 constant PSC0_CAPTAddr \ PSC0 Capture Event
-#10 constant PSC0_ECAddr \ PSC0 End Cycle
-#12 constant PSC0_EECAddr \ PSC0 End Of Enhanced Cycle
-#14 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-#16 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-#18 constant ANALOG_COMP_3Addr \ Analog Comparator 3
-#20 constant INT0Addr \ External Interrupt Request 0
-#22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-#24 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-#26 constant ADCAddr \ ADC Conversion Complete
-#28 constant INT1Addr \ External Interrupt Request 1
-#30 constant SPI_STCAddr \ SPI Serial Transfer Complet
-#32 constant INT2Addr \ External Interrupt Request 2
-#34 constant WDTAddr \ Watchdog Timeout Interrupt
-#36 constant EE_READYAddr \ EEPROM Ready
-#38 constant SPM_READYAddr \ Store Program Memory Read
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins
-\ DA_CONVERTER
-$59 constant DACH \ DAC Data Register High Byte
- $ff constant DACH_DACH \ DAC Data Register High Byte Bi
- 59 $ff bitmask: DACH.DACH \ DAC Data Register High Byte Bi
-$58 constant DACL \ DAC Data Register Low Byte
- $ff constant DACL_DACL \ DAC Data Register Low Byte Bit
- 58 $ff bitmask: DACL.DACL \ DAC Data Register Low Byte Bit
-$76 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- 76 $80 bitmask: DACON.DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- 76 $70 bitmask: DACON.DATS \ DAC Trigger Selection Bits
- $4 constant DACON_DALA \ DAC Left Adjust
- 76 $4 bitmask: DACON.DALA \ DAC Left Adjust
- $1 constant DACON_DAEN \ DAC Enable Bit
- 76 $1 bitmask: DACON.DAEN \ DAC Enable Bit
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins
-\ SPI
-$37 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 37 $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 37 $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 37 $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 37 $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Selects
- 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects
-$38 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$56 constant SPDR \ SPI Data Register
-\ WATCHDOG
-$82 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 82 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 82 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 82 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 82 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 82 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-$89 constant EICRA \ External Interrupt Control Reg
- $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
- 89 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
- $c constant EICRA_ISC1 \ External Interrupt Sense Contr
- 89 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
- $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
- 89 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
-$41 constant EIMSK \ External Interrupt Mask Regist
- $7 constant EIMSK_INT \ External Interrupt Request 2 E
- 41 $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
-$40 constant EIFR \ External Interrupt Flag Regist
- $7 constant EIFR_INTF \ External Interrupt Flags
- 40 $7 bitmask: EIFR.INTF \ External Interrupt Flags
-\ AD_CONVERTER
-$28 constant ADMUX \ The ADC multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 28 $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- 28 $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
- $f constant ADMUX_MUX \ Analog Channel and Gain Select
- 28 $f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$26 constant ADCSRA \ The ADC Control and Status reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 26 $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 26 $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 26 $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 26 $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 26 $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 26 $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$4c constant ADC \ ADC Data Register Bytes
-$27 constant ADCSRB \ ADC Control and Status Registe
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- 27 $80 bitmask: ADCSRB.ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
- 27 $40 bitmask: ADCSRB.ADNCDIS \ ADC Noise Canceller Disable
- $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC'
- 27 $10 bitmask: ADCSRB.ADSSEN \ ADC Single Shot Enable on PSC'
- $f constant ADCSRB_ADTS \ ADC Auto Trigger Sources
- 27 $f bitmask: ADCSRB.ADTS \ ADC Auto Trigger Sources
-$77 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- 77 $80 bitmask: DIDR0.ADC7D \
- $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
- 77 $40 bitmask: DIDR0.ADC6D \ ADC7 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- 77 $20 bitmask: DIDR0.ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- 77 $10 bitmask: DIDR0.ADC4D \ ADC4 Digital input Disable
- $8 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- 77 $8 bitmask: DIDR0.ADC3D \ ADC3 Digital input Disable
- $4 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- 77 $4 bitmask: DIDR0.ADC2D \ ADC2 Digital input Disable
- $2 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- 77 $2 bitmask: DIDR0.ADC1D \ ADC1 Digital input Disable
- $1 constant DIDR0_ADC0D \ ADC0 Digital input Disable
- 77 $1 bitmask: DIDR0.ADC0D \ ADC0 Digital input Disable
-$78 constant DIDR1 \ Digital Input Disable Register
- $8 constant DIDR1_ACMP1MD \
- 78 $8 bitmask: DIDR1.ACMP1MD \
- $4 constant DIDR1_AMP0POSD \
- 78 $4 bitmask: DIDR1.AMP0POSD \
- $2 constant DIDR1_ADC10D \
- 78 $2 bitmask: DIDR1.ADC10D \
- $1 constant DIDR1_ADC9D \
- 78 $1 bitmask: DIDR1.ADC9D \
-$79 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- 79 $80 bitmask: AMP0CSR.AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- 79 $40 bitmask: AMP0CSR.AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- 79 $30 bitmask: AMP0CSR.AMP0G \
- $8 constant AMP0CSR_AMP0GS \
- 79 $8 bitmask: AMP0CSR.AMP0GS \
- $3 constant AMP0CSR_AMP0TS \
- 79 $3 bitmask: AMP0CSR.AMP0TS \
-\ ANALOG_COMPARATOR
-$7f constant AC3CON \ Analog Comparator3 Control Reg
- $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
- 7f $80 bitmask: AC3CON.AC3EN \ Analog Comparator3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt
- 7f $40 bitmask: AC3CON.AC3IE \ Analog Comparator 3 Interrupt
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt
- 7f $30 bitmask: AC3CON.AC3IS \ Analog Comparator 3 Interrupt
- $8 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate
- 7f $8 bitmask: AC3CON.AC3OEA \ Analog Comparator 3 Alternate
- $7 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexe
- 7f $7 bitmask: AC3CON.AC3M \ Analog Comparator 3 Multiplexe
-$7d constant AC1CON \ Analog Comparator 1 Control Re
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- 7d $80 bitmask: AC1CON.AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt
- 7d $40 bitmask: AC1CON.AC1IE \ Analog Comparator 1 Interrupt
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt
- 7d $30 bitmask: AC1CON.AC1IS \ Analog Comparator 1 Interrupt
- $7 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexe
- 7d $7 bitmask: AC1CON.AC1M \ Analog Comparator 1 Multiplexe
-$7e constant AC2CON \ Analog Comparator 2 Control Re
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- 7e $80 bitmask: AC2CON.AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt
- 7e $40 bitmask: AC2CON.AC2IE \ Analog Comparator 2 Interrupt
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt
- 7e $30 bitmask: AC2CON.AC2IS \ Analog Comparator 2 Interrupt
- $7 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexe
- 7e $7 bitmask: AC2CON.AC2M \ Analog Comparator 2 Multiplexe
-$20 constant ACSR \ Analog Comparator Status Regis
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt
- 20 $80 bitmask: ACSR.AC3IF \ Analog Comparator 3 Interrupt
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt
- 20 $40 bitmask: ACSR.AC2IF \ Analog Comparator 2 Interrupt
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt
- 20 $20 bitmask: ACSR.AC1IF \ Analog Comparator 1 Interrupt
- $8 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- 20 $8 bitmask: ACSR.AC3O \ Analog Comparator 3 Output Bit
- $4 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- 20 $4 bitmask: ACSR.AC2O \ Analog Comparator 2 Output Bit
- $2 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- 20 $2 bitmask: ACSR.AC1O \ Analog Comparator 1 Output Bit
-$7c constant AC3ECON \
- $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
- 7c $20 bitmask: AC3ECON.AC3OI \ Analog Comparator Ouput Invert
- $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
- 7c $10 bitmask: AC3ECON.AC3OE \ Analog Comparator Ouput Enable
- $7 constant AC3ECON_AC3H \ Analog Comparator Hysteresis S
- 7c $7 bitmask: AC3ECON.AC3H \ Analog Comparator Hysteresis S
-$7b constant AC2ECON \
- $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
- 7b $20 bitmask: AC2ECON.AC2OI \ Analog Comparator Ouput Invert
- $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
- 7b $10 bitmask: AC2ECON.AC2OE \ Analog Comparator Ouput Enable
- $7 constant AC2ECON_AC2H \ Analog Comparator Hysteresis S
- 7b $7 bitmask: AC2ECON.AC2H \ Analog Comparator Hysteresis S
-$7a constant AC1ECON \
- $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
- 7a $20 bitmask: AC1ECON.AC1OI \ Analog Comparator Ouput Invert
- $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
- 7a $10 bitmask: AC1ECON.AC1OE \ Analog Comparator Ouput Enable
- $8 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Ca
- 7a $8 bitmask: AC1ECON.AC1ICE \ Analog Comparator Interrupt Ca
- $7 constant AC1ECON_AC1H \ Analog Comparator Hysteresis S
- 7a $7 bitmask: AC1ECON.AC1H \ Analog Comparator Hysteresis S
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
- $8 constant MCUCR_RSTDIS \ Reset Pin Disable
- 55 $8 bitmask: MCUCR.RSTDIS \ Reset Pin Disable
- $4 constant MCUCR_CKRC81 \ Frequency Selection of the Cal
- 55 $4 bitmask: MCUCR.CKRC81 \ Frequency Selection of the Cal
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on reset flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
-$88 constant OSCCAL \ Oscillator Calibration Value
-$83 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- 83 $80 bitmask: CLKPR.CLKPCE \
- $f constant CLKPR_CLKPS \
- 83 $f bitmask: CLKPR.CLKPS \
-$53 constant SMCR \ Sleep Mode Control Register
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$3b constant GPIOR2 \ General Purpose IO Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
- 3b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
-$3a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
- 3a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
-$39 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
- 39 $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
- 39 $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
- 39 $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
- 39 $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
- 39 $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
- 39 $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
- 39 $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
- 39 $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
-$87 constant PLLCSR \ PLL Control And Status Registe
- $3c constant PLLCSR_PLLF \
- 87 $3c bitmask: PLLCSR.PLLF \
- $2 constant PLLCSR_PLLE \ PLL Enable
- 87 $2 bitmask: PLLCSR.PLLE \ PLL Enable
- $1 constant PLLCSR_PLOCK \ PLL Lock Detector
- 87 $1 bitmask: PLLCSR.PLOCK \ PLL Lock Detector
-$86 constant PRR \ Power Reduction Register
- $80 constant PRR_PRPSC2 \ Power Reduction PSC2
- 86 $80 bitmask: PRR.PRPSC2 \ Power Reduction PSC2
- $20 constant PRR_PRPSCR \ Power Reduction PSC0
- 86 $20 bitmask: PRR.PRPSCR \ Power Reduction PSC0
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- 86 $10 bitmask: PRR.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR_PRSPI \ Power Reduction Serial Periphe
- 86 $4 bitmask: PRR.PRSPI \ Power Reduction Serial Periphe
- $1 constant PRR_PRADC \ Power Reduction ADC
- 86 $1 bitmask: PRR.PRADC \ Power Reduction ADC
-$84 constant CLKCSR \
- $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
- 84 $80 bitmask: CLKCSR.CLKCCE \ Clock Control Change Enable
- $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
- 84 $10 bitmask: CLKCSR.CLKRDY \ Clock Ready Flag
- $f constant CLKCSR_CLKC \ Clock Control
- 84 $f bitmask: CLKCSR.CLKC \ Clock Control
-$85 constant CLKSELR \
- $40 constant CLKSELR_COUT \ Clock OUT
- 85 $40 bitmask: CLKSELR.COUT \ Clock OUT
- $30 constant CLKSELR_CSUT \ Clock Start up Time
- 85 $30 bitmask: CLKSELR.CSUT \ Clock Start up Time
- $f constant CLKSELR_CKSEL \ Clock Source Select
- 85 $f bitmask: CLKSELR.CKSEL \ Clock Source Select
-$81 constant BGCCR \ BandGap Current Calibration Re
- $f constant BGCCR_BGCC \
- 81 $f bitmask: BGCCR.BGCC \
-$80 constant BGCRR \ BandGap Resistor Calibration R
- $f constant BGCRR_BGCR \
- 80 $f bitmask: BGCRR.BGCR \
-\ EEPROM
-$3e constant EEAR \ EEPROM Read/Write Access Byte
-$3d constant EEDR \ EEPROM Data Register
-$3c constant EECR \ EEPROM Control Register
- $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
- 3c $80 bitmask: EECR.NVMBSY \ None Volatile Busy Memory Busy
- $40 constant EECR_EEPAGE \ EEPROM Page Access
- 3c $40 bitmask: EECR.EEPAGE \ EEPROM Page Access
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3c $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3c $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMWE \ EEPROM Master Write Enable
- 3c $4 bitmask: EECR.EEMWE \ EEPROM Master Write Enable
- $2 constant EECR_EEWE \ EEPROM Write Enable
- 3c $2 bitmask: EECR.EEWE \ EEPROM Write Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3c $1 bitmask: EECR.EERE \ EEPROM Read Enable
-\ PSC0
-$68 constant PICR0 \ PSC 0 Input Capture Register
-$63 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Par
- 63 $80 bitmask: PFRC0B.PCAE0B \ PSC 0 Capture Enable Input Par
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- 63 $40 bitmask: PFRC0B.PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on I
- 63 $20 bitmask: PFRC0B.PELEV0B \ PSC 0 Edge Level Selector on I
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input P
- 63 $10 bitmask: PFRC0B.PFLTE0B \ PSC 0 Filter Enable on Input P
- $f constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode
- 63 $f bitmask: PFRC0B.PRFM0B \ PSC 0 Retrigger and Fault Mode
-$62 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Par
- 62 $80 bitmask: PFRC0A.PCAE0A \ PSC 0 Capture Enable Input Par
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- 62 $40 bitmask: PFRC0A.PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on I
- 62 $20 bitmask: PFRC0A.PELEV0A \ PSC 0 Edge Level Selector on I
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input P
- 62 $10 bitmask: PFRC0A.PFLTE0A \ PSC 0 Filter Enable on Input P
- $f constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode
- 62 $f bitmask: PFRC0A.PRFM0A \ PSC 0 Retrigger and Fault Mode
-$32 constant PCTL0 \ PSC 0 Control Register
- $c0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- 32 $c0 bitmask: PCTL0.PPRE0 \ PSC 0 Prescaler Selects
- $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modu
- 32 $24 bitmask: PCTL0.PBFM0 \ PSC 0 Balance Flank Width Modu
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Cont
- 32 $10 bitmask: PCTL0.PAOC0B \ PSC 0 Asynchronous Output Cont
- $8 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Cont
- 32 $8 bitmask: PCTL0.PAOC0A \ PSC 0 Asynchronous Output Cont
- $2 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- 32 $2 bitmask: PCTL0.PCCYC0 \ PSC0 Complete Cycle
- $1 constant PCTL0_PRUN0 \ PSC 0 Run
- 32 $1 bitmask: PCTL0.PRUN0 \ PSC 0 Run
-$31 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- 31 $80 bitmask: PCNF0.PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- 31 $40 bitmask: PCNF0.PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- 31 $20 bitmask: PCNF0.PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- 31 $18 bitmask: PCNF0.PMODE0 \ PSC 0 Mode
- $4 constant PCNF0_POP0 \ PSC 0 Output Polarity
- 31 $4 bitmask: PCNF0.POP0 \ PSC 0 Output Polarity
- $2 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
- 31 $2 bitmask: PCNF0.PCLKSEL0 \ PSC 0 Input Clock Select
-$44 constant OCR0RB \ Output Compare RB Register
-$42 constant OCR0SB \ Output Compare SB Register
-$4a constant OCR0RA \ Output Compare RA Register
-$60 constant OCR0SA \ Output Compare SA Register
-$6a constant PSOC0 \ PSC0 Synchro and Output Config
- $80 constant PSOC0_PISEL0A1 \ PSC Input Select
- 6a $80 bitmask: PSOC0.PISEL0A1 \ PSC Input Select
- $40 constant PSOC0_PISEL0B1 \ PSC Input Select
- 6a $40 bitmask: PSOC0.PISEL0B1 \ PSC Input Select
- $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC se
- 6a $30 bitmask: PSOC0.PSYNC0 \ Synchronisation out for ADC se
- $4 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- 6a $4 bitmask: PSOC0.POEN0B \ PSCOUT01 Output Enable
- $1 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
- 6a $1 bitmask: PSOC0.POEN0A \ PSCOUT00 Output Enable
-$2f constant PIM0 \ PSC0 Interrupt Mask Register
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Ena
- 2f $10 bitmask: PIM0.PEVE0B \ External Event B Interrupt Ena
- $8 constant PIM0_PEVE0A \ External Event A Interrupt Ena
- 2f $8 bitmask: PIM0.PEVE0A \ External Event A Interrupt Ena
- $2 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
- 2f $2 bitmask: PIM0.PEOEPE0 \ End of Enhanced Cycle Enable
- $1 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
- 2f $1 bitmask: PIM0.PEOPE0 \ End of Cycle Interrupt Enable
-$30 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- 30 $80 bitmask: PIFR0.POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- 30 $40 bitmask: PIFR0.POAC0A \ PSC 0 Output A Activity
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- 30 $10 bitmask: PIFR0.PEV0B \ External Event B Interrupt
- $8 constant PIFR0_PEV0A \ External Event A Interrupt
- 30 $8 bitmask: PIFR0.PEV0A \ External Event A Interrupt
- $6 constant PIFR0_PRN0 \ Ramp Number
- 30 $6 bitmask: PIFR0.PRN0 \ Ramp Number
- $1 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
- 30 $1 bitmask: PIFR0.PEOP0 \ End of PSC0 Interrupt
-\ PSC2
-$6d constant PICR2H \ PSC 2 Input Capture Register H
- $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger
- 6d $80 bitmask: PICR2H.PCST2 \ PSC 2 Capture Software Trigger
- $c constant PICR2H_PICR21 \
- 6d $c bitmask: PICR2H.PICR21 \
- $3 constant PICR2H_PICR2 \
- 6d $3 bitmask: PICR2H.PICR2 \
-$6c constant PICR2L \ PSC 2 Input Capture Register L
-$67 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Par
- 67 $80 bitmask: PFRC2B.PCAE2B \ PSC 2 Capture Enable Input Par
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- 67 $40 bitmask: PFRC2B.PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on I
- 67 $20 bitmask: PFRC2B.PELEV2B \ PSC 2 Edge Level Selector on I
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input P
- 67 $10 bitmask: PFRC2B.PFLTE2B \ PSC 2 Filter Enable on Input P
- $f constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode
- 67 $f bitmask: PFRC2B.PRFM2B \ PSC 2 Retrigger and Fault Mode
-$66 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Par
- 66 $80 bitmask: PFRC2A.PCAE2A \ PSC 2 Capture Enable Input Par
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- 66 $40 bitmask: PFRC2A.PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on I
- 66 $20 bitmask: PFRC2A.PELEV2A \ PSC 2 Edge Level Selector on I
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input P
- 66 $10 bitmask: PFRC2A.PFLTE2A \ PSC 2 Filter Enable on Input P
- $f constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode
- 66 $f bitmask: PFRC2A.PRFM2A \ PSC 2 Retrigger and Fault Mode
-$36 constant PCTL2 \ PSC 2 Control Register
- $c0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- 36 $c0 bitmask: PCTL2.PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- 36 $20 bitmask: PCTL2.PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Cont
- 36 $10 bitmask: PCTL2.PAOC2B \ PSC 2 Asynchronous Output Cont
- $8 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Cont
- 36 $8 bitmask: PCTL2.PAOC2A \ PSC 2 Asynchronous Output Cont
- $4 constant PCTL2_PARUN2 \ PSC2 Auto Run
- 36 $4 bitmask: PCTL2.PARUN2 \ PSC2 Auto Run
- $2 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- 36 $2 bitmask: PCTL2.PCCYC2 \ PSC2 Complete Cycle
- $1 constant PCTL2_PRUN2 \ PSC 2 Run
- 36 $1 bitmask: PCTL2.PRUN2 \ PSC 2 Run
-$35 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- 35 $80 bitmask: PCNF2.PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- 35 $40 bitmask: PCNF2.PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- 35 $20 bitmask: PCNF2.PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- 35 $18 bitmask: PCNF2.PMODE2 \ PSC 2 Mode
- $4 constant PCNF2_POP2 \ PSC 2 Output Polarity
- 35 $4 bitmask: PCNF2.POP2 \ PSC 2 Output Polarity
- $2 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- 35 $2 bitmask: PCNF2.PCLKSEL2 \ PSC 2 Input Clock Select
- $1 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
- 35 $1 bitmask: PCNF2.POME2 \ PSC 2 Output Matrix Enable
-$70 constant PCNFE2 \ PSC 2 Enhanced Configuration R
- $e0 constant PCNFE2_PASDLK2 \
- 70 $e0 bitmask: PCNFE2.PASDLK2 \
- $10 constant PCNFE2_PBFM21 \
- 70 $10 bitmask: PCNFE2.PBFM21 \
- $8 constant PCNFE2_PELEV2A1 \
- 70 $8 bitmask: PCNFE2.PELEV2A1 \
- $4 constant PCNFE2_PELEV2B1 \
- 70 $4 bitmask: PCNFE2.PELEV2B1 \
- $2 constant PCNFE2_PISEL2A1 \
- 70 $2 bitmask: PCNFE2.PISEL2A1 \
- $1 constant PCNFE2_PISEL2B1 \
- 70 $1 bitmask: PCNFE2.PISEL2B1 \
-$48 constant OCR2RB \ Output Compare RB Register
-$46 constant OCR2SB \ Output Compare SB Register
-$4e constant OCR2RA \ Output Compare RA Register
-$64 constant OCR2SA \ Output Compare SA Register
-$6f constant POM2 \ PSC 2 Output Matrix
- $f0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- 6f $f0 bitmask: POM2.POMV2B \ Output Matrix Output B Ramps
- $f constant POM2_POMV2A \ Output Matrix Output A Ramps
- 6f $f bitmask: POM2.POMV2A \ Output Matrix Output A Ramps
-$6e constant PSOC2 \ PSC2 Synchro and Output Config
- $c0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- 6e $c0 bitmask: PSOC2.POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Se
- 6e $30 bitmask: PSOC2.PSYNC2 \ Synchronization Out for ADC Se
- $8 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- 6e $8 bitmask: PSOC2.POEN2D \ PSCOUT23 Output Enable
- $4 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- 6e $4 bitmask: PSOC2.POEN2B \ PSCOUT21 Output Enable
- $2 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- 6e $2 bitmask: PSOC2.POEN2C \ PSCOUT22 Output Enable
- $1 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
- 6e $1 bitmask: PSOC2.POEN2A \ PSCOUT20 Output Enable
-$33 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt
- 33 $20 bitmask: PIM2.PSEIE2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Ena
- 33 $10 bitmask: PIM2.PEVE2B \ External Event B Interrupt Ena
- $8 constant PIM2_PEVE2A \ External Event A Interrupt Ena
- 33 $8 bitmask: PIM2.PEVE2A \ External Event A Interrupt Ena
- $2 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrup
- 33 $2 bitmask: PIM2.PEOEPE2 \ End of Enhanced Cycle Interrup
- $1 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
- 33 $1 bitmask: PIM2.PEOPE2 \ End of Cycle Interrupt Enable
-$34 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- 34 $80 bitmask: PIFR2.POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- 34 $40 bitmask: PIFR2.POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- 34 $20 bitmask: PIFR2.PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- 34 $10 bitmask: PIFR2.PEV2B \ External Event B Interrupt
- $8 constant PIFR2_PEV2A \ External Event A Interrupt
- 34 $8 bitmask: PIFR2.PEV2A \ External Event A Interrupt
- $6 constant PIFR2_PRN2 \ Ramp Number
- 34 $6 bitmask: PIFR2.PRN2 \ Ramp Number
- $1 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
- 34 $1 bitmask: PIFR2.PEOP2 \ End of PSC2 Interrupt
-$71 constant PASDLY2 \ Analog Synchronization Delay R
-\ TIMER_COUNTER_1
-$21 constant TIMSK1 \ Timer/Counter Interrupt Mask R
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 21 $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 21 $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$22 constant TIFR1 \ Timer/Counter Interrupt Flag r
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- 22 $20 bitmask: TIFR1.ICF1 \ Input Capture Flag 1
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 22 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-$8a constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- 8a $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 8a $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
- 8a $10 bitmask: TCCR1B.WGM13 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Prescaler source of Timer/Coun
- 8a $7 bitmask: TCCR1B.CS1 \ Prescaler source of Timer/Coun
-$5a constant TCNT1 \ Timer/Counter1 Bytes
-$8c constant ICR1 \ Timer/Counter1 Input Capture R
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.py b/amforth-6.5/avr8/devices/at90pwm161/device.py
deleted file mode 100644
index 6a000b9..0000000
--- a/amforth-6.5/avr8/devices/at90pwm161/device.py
+++ /dev/null
@@ -1,389 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM161
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC2_EECAddr' : '#6', # PSC2 End Of Enhanced Cycle
- 'PSC0_CAPTAddr' : '#8', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#10', # PSC0 End Cycle
- 'PSC0_EECAddr' : '#12', # PSC0 End Of Enhanced Cycle
- 'ANALOG_COMP_1Addr' : '#14', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#16', # Analog Comparator 2
- 'ANALOG_COMP_3Addr' : '#18', # Analog Comparator 3
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_OVFAddr' : '#24', # Timer/Counter1 Overflow
- 'ADCAddr' : '#26', # ADC Conversion Complete
- 'INT1Addr' : '#28', # External Interrupt Request 1
- 'SPI_STCAddr' : '#30', # SPI Serial Transfer Complet
- 'INT2Addr' : '#32', # External Interrupt Request 2
- 'WDTAddr' : '#34', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#36', # EEPROM Ready
- 'SPM_READYAddr' : '#38', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module DA_CONVERTER
- 'DACH' : '$59', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$58', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$76', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module SPI
- 'SPCR' : '$37', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$38', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$56', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$82', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$89', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$41', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$40', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
-
-# Module AD_CONVERTER
- 'ADMUX' : '$28', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$4c', # ADC Data Register Bytes
- 'ADCSRB' : '$27', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADNCDIS': '$40', # ADC Noise Canceller Disable
- 'ADCSRB_ADSSEN': '$10', # ADC Single Shot Enable on PSC'
- 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
- 'DIDR0' : '$77', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', # ADC7 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR1' : '$78', # Digital Input Disable Register
- 'DIDR1_ACMP1MD': '$8', #
- 'DIDR1_AMP0POSD': '$4', #
- 'DIDR1_ADC10D': '$2', #
- 'DIDR1_ADC9D': '$1', #
- 'AMP0CSR' : '$79', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0GS': '$8', #
- 'AMP0CSR_AMP0TS': '$3', #
-
-# Module ANALOG_COMPARATOR
- 'AC3CON' : '$7f', # Analog Comparator3 Control Reg
- 'AC3CON_AC3EN': '$80', # Analog Comparator3 Enable Bit
- 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3OEA': '$8', # Analog Comparator 3 Alternate
- 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
- 'AC1CON' : '$7d', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$7e', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$20', # Analog Comparator Status Regis
- 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'AC3ECON' : '$7c', #
- 'AC3ECON_AC3OI': '$20', # Analog Comparator Ouput Invert
- 'AC3ECON_AC3OE': '$10', # Analog Comparator Ouput Enable
- 'AC3ECON_AC3H': '$7', # Analog Comparator Hysteresis S
- 'AC2ECON' : '$7b', #
- 'AC2ECON_AC2OI': '$20', # Analog Comparator Ouput Invert
- 'AC2ECON_AC2OE': '$10', # Analog Comparator Ouput Enable
- 'AC2ECON_AC2H': '$7', # Analog Comparator Hysteresis S
- 'AC1ECON' : '$7a', #
- 'AC1ECON_AC1OI': '$20', # Analog Comparator Ouput Invert
- 'AC1ECON_AC1OE': '$10', # Analog Comparator Ouput Enable
- 'AC1ECON_AC1ICE': '$8', # Analog Comparator Interrupt Ca
- 'AC1ECON_AC1H': '$7', # Analog Comparator Hysteresis S
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_RSTDIS': '$8', # Reset Pin Disable
- 'MCUCR_CKRC81': '$4', # Frequency Selection of the Cal
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$88', # Oscillator Calibration Value
- 'CLKPR' : '$83', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$3b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$3a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$39', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$87', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$3c', #
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$86', # Power Reduction Register
- 'PRR_PRPSC2': '$80', # Power Reduction PSC2
- 'PRR_PRPSCR': '$20', # Power Reduction PSC0
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'CLKCSR' : '$84', #
- 'CLKCSR_CLKCCE': '$80', # Clock Control Change Enable
- 'CLKCSR_CLKRDY': '$10', # Clock Ready Flag
- 'CLKCSR_CLKC': '$f', # Clock Control
- 'CLKSELR' : '$85', #
- 'CLKSELR_COUT': '$40', # Clock OUT
- 'CLKSELR_CSUT': '$30', # Clock Start up Time
- 'CLKSELR_CKSEL': '$f', # Clock Source Select
- 'BGCCR' : '$81', # BandGap Current Calibration Re
- 'BGCCR_BGCC': '$f', #
- 'BGCRR' : '$80', # BandGap Resistor Calibration R
- 'BGCRR_BGCR': '$f', #
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_NVMBSY': '$80', # None Volatile Busy Memory Busy
- 'EECR_EEPAGE': '$40', # EEPROM Page Access
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC0
- 'PICR0' : '$68', # PSC 0 Input Capture Register
- 'PFRC0B' : '$63', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$62', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$32', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$24', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$31', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$44', # Output Compare RB Register
- 'OCR0SB' : '$42', # Output Compare SB Register
- 'OCR0RA' : '$4a', # Output Compare RA Register
- 'OCR0SA' : '$60', # Output Compare SA Register
- 'PSOC0' : '$6a', # PSC0 Synchro and Output Config
- 'PSOC0_PISEL0A1': '$80', # PSC Input Select
- 'PSOC0_PISEL0B1': '$40', # PSC Input Select
- 'PSOC0_PSYNC0': '$30', # Synchronisation out for ADC se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$2f', # PSC0 Interrupt Mask Register
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOEPE0': '$2', # End of Enhanced Cycle Enable
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$30', # PSC0 Interrupt Flag Register
- 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
- 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC2
- 'PICR2H' : '$6d', # PSC 2 Input Capture Register H
- 'PICR2H_PCST2': '$80', # PSC 2 Capture Software Trigger
- 'PICR2H_PICR21': '$c', #
- 'PICR2H_PICR2': '$3', #
- 'PICR2L' : '$6c', # PSC 2 Input Capture Register L
- 'PFRC2B' : '$67', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$66', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$36', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$35', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'PCNFE2' : '$70', # PSC 2 Enhanced Configuration R
- 'PCNFE2_PASDLK2': '$e0', #
- 'PCNFE2_PBFM21': '$10', #
- 'PCNFE2_PELEV2A1': '$8', #
- 'PCNFE2_PELEV2B1': '$4', #
- 'PCNFE2_PISEL2A1': '$2', #
- 'PCNFE2_PISEL2B1': '$1', #
- 'OCR2RB' : '$48', # Output Compare RB Register
- 'OCR2SB' : '$46', # Output Compare SB Register
- 'OCR2RA' : '$4e', # Output Compare RA Register
- 'OCR2SA' : '$64', # Output Compare SA Register
- 'POM2' : '$6f', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$6e', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$33', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOEPE2': '$2', # End of Enhanced Cycle Interrup
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$34', # PSC2 Interrupt Flag Register
- 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
- 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
- 'PASDLY2' : '$71', # Analog Synchronization Delay R
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$21', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$22', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1B' : '$8a', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM13': '$10', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCNT1' : '$5a', # Timer/Counter1 Bytes
- 'ICR1' : '$8c', # Timer/Counter1 Input Capture R
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt b/amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt
deleted file mode 100644
index 828a39b..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt
+++ /dev/null
@@ -1,193 +0,0 @@
-\ Partname: AT90PWM2
-\ Built using part description XML file version 168
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant ADCH \ ADC Data Register High Byte
-78 constant ADCL \ ADC Data Register Low Byte
-7A constant ADCSRA \ The ADC Control and Status register
-7B constant ADCSRB \ ADC Control and Status Register B
-7C constant ADMUX \ The ADC multiplexer Selection Register
-76 constant AMP0CSR \
-77 constant AMP1CSR \
-7E constant DIDR0 \ Digital Input Disable Register 0
-7F constant DIDR1 \ Digital Input Disable Register 0
-
-\ ANALOG_COMPARATOR
-AD constant AC0CON \ Analog Comparator 0 Control Register
-AE constant AC1CON \ Analog Comparator 1 Control Register
-AF constant AC2CON \ Analog Comparator 2 Control Register
-50 constant ACSR \ Analog Comparator Status Register
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control Register
-
-\ CPU
-61 constant CLKPR \
-3E constant GPIOR0 \ General Purpose IO Register 0
-39 constant GPIOR1 \ General Purpose IO Register 1
-3A constant GPIOR2 \ General Purpose IO Register 2
-3B constant GPIOR3 \ General Purpose IO Register 3
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-66 constant OSCCAL \ Oscillator Calibration Value
-49 constant PLLCSR \ PLL Control And Status Register
-64 constant PRR \ Power Reduction Register
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ DA_CONVERTER
-AC constant DACH \ DAC Data Register High Byte
-AB constant DACL \ DAC Data Register Low Byte
-AA constant DACON \ DAC Control Register
-
-\ EEPROM
-42 constant EEARH \ EEPROM Read/Write Access High Byte
-41 constant EEARL \ EEPROM Read/Write Access Low Byte
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EUSART
-C8 constant EUCSRA \ EUSART Control and Status Register A
-C9 constant EUCSRB \ EUSART Control Register B
-CA constant EUCSRC \ EUSART Status Register C
-CE constant EUDR \ EUSART I/O Data Register
-CD constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
-CC constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register A
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-
-\ PORTB
-24 constant DDRB \ Port B Data Direction Register
-23 constant PINB \ Port B Input Pins
-25 constant PORTB \ Port B Data Register
-
-\ PORTD
-2A constant DDRD \ Port D Data Direction Register
-29 constant PIND \ Port D Input Pins
-2B constant PORTD \ Port D Data Register
-
-\ PORTE
-2D constant DDRE \ Port E Data Direction Register
-2C constant PINE \ Port E Input Pins
-2E constant PORTE \ Port E Data Register
-
-\ PSC0
-D5 constant OCR0RAH \ Output Compare RA Register High
-D4 constant OCR0RAL \ Output Compare RA Register Low
-D9 constant OCR0RBH \ Output Compare RB Register High
-D8 constant OCR0RBL \ Output Compare RB Register Low
-D3 constant OCR0SAH \ Output Compare SA Register High
-D2 constant OCR0SAL \ Output Compare SA Register Low
-D7 constant OCR0SBH \ Output Compare SB Register High
-D6 constant OCR0SBL \ Output Compare SB Register Low
-DA constant PCNF0 \ PSC 0 Configuration Register
-DB constant PCTL0 \ PSC 0 Control Register
-DC constant PFRC0A \ PSC 0 Input A Control
-DD constant PFRC0B \ PSC 0 Input B Control
-DF constant PICR0H \ PSC 0 Input Capture Register High
-DE constant PICR0L \ PSC 0 Input Capture Register Low
-A0 constant PIFR0 \ PSC0 Interrupt Flag Register
-A1 constant PIM0 \ PSC0 Interrupt Mask Register
-D0 constant PSOC0 \ PSC0 Synchro and Output Configuration
-
-\ PSC2
-F5 constant OCR2RAH \ Output Compare RA Register High
-F4 constant OCR2RAL \ Output Compare RA Register Low
-F9 constant OCR2RBH \ Output Compare RB Register High
-F8 constant OCR2RBL \ Output Compare RB Register Low
-F3 constant OCR2SAH \ Output Compare SA Register High
-F2 constant OCR2SAL \ Output Compare SA Register Low
-F7 constant OCR2SBH \ Output Compare SB Register High
-F6 constant OCR2SBL \ Output Compare SB Register Low
-FA constant PCNF2 \ PSC 2 Configuration Register
-FB constant PCTL2 \ PSC 2 Control Register
-FC constant PFRC2A \ PSC 2 Input B Control
-FD constant PFRC2B \ PSC 2 Input B Control
-FF constant PICR2H \ PSC 2 Input Capture Register High
-FE constant PICR2L \ PSC 2 Input Capture Register Low
-A4 constant PIFR2 \ PSC2 Interrupt Flag Register
-A5 constant PIM2 \ PSC2 Interrupt Mask Register
-F1 constant POM2 \ PSC 2 Output Matrix
-F0 constant PSOC2 \ PSC2 Synchro and Output Configuration
-
-\ SPI
-4C constant SPCR \ SPI Control Register
-4E constant SPDR \ SPI Data Register
-4D constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-43 constant GTCCR \ General Timer/Counter Control Register
-47 constant OCR0A \ Timer/Counter0 Output Compare Register
-48 constant OCR0B \ Timer/Counter0 Output Compare Register
-44 constant TCCR0A \ Timer/Counter Control Register A
-45 constant TCCR0B \ Timer/Counter Control Register B
-46 constant TCNT0 \ Timer/Counter0
-35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-89 constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-88 constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-8B constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-8A constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-80 constant TCCR1A \ Timer/Counter1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-82 constant TCCR1C \ Timer/Counter1 Control Register C
-85 constant TCNT1H \ Timer/Counter1 High Byte
-84 constant TCNT1L \ Timer/Counter1 Low Byte
-36 constant TIFR1 \ Timer/Counter Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
-
-\ USART
-C5 constant UBRRH \ USART Baud Rate Register High Byte
-C4 constant UBRRL \ USART Baud Rate Register Low Byte
-C0 constant UCSRA \ USART Control and Status register A
-C1 constant UCSRB \ USART Control an Status register B
-C2 constant UCSRC \ USART Control an Status register C
-C6 constant UDR \ USART I/O Data Register
-
-\ WATCHDOG
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-0001 constant PSC2_CAPTAddr \ PSC2 Capture Event
-0002 constant PSC2_ECAddr \ PSC2 End Cycle
-0003 constant PSC1_CAPTAddr \ PSC1 Capture Event
-0004 constant PSC1_ECAddr \ PSC1 End Cycle
-0005 constant PSC0_CAPTAddr \ PSC0 Capture Event
-0006 constant PSC0_ECAddr \ PSC0 End Cycle
-0007 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-0008 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-0009 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-000A constant INT0Addr \ External Interrupt Request 0
-000B constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-000C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-000D constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-000E constant RESERVED15Addr \
-000F constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-0010 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-0011 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-0012 constant ADCAddr \ ADC Conversion Complete
-0013 constant INT1Addr \ External Interrupt Request 1
-0014 constant SPI_STCAddr \ SPI Serial Transfer Complete
-0015 constant USART_RXAddr \ USART, Rx Complete
-0016 constant USART_UDREAddr \ USART Data Register Empty
-0017 constant USART_TXAddr \ USART, Tx Complete
-0018 constant INT2Addr \ External Interrupt Request 2
-0019 constant WDTAddr \ Watchdog Timeout Interrupt
-001A constant EE_READYAddr \ EEPROM Ready
-001B constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-001C constant INT3Addr \ External Interrupt Request 3
-001D constant RESERVED30Addr \
-001E constant RESERVED31Addr \
-001F constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm2/device.asm b/amforth-6.5/avr8/devices/at90pwm2/device.asm
deleted file mode 100644
index 71151f2..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2/device.asm
+++ /dev/null
@@ -1,137 +0,0 @@
-; Partname: AT90PWM2
-; Built using part description XML file version 168
-; generated automatically, do not edit
-
-.nolist
- .include "pwm2def.inc"
-.list
-
-.equ ramstart = $0100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_EEPROM = 0
-.set WANT_EUSART = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC2 = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_USART = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 32
-.org $0001
- rcall isr ; PSC2 Capture Event
-.org $0002
- rcall isr ; PSC2 End Cycle
-.org $0003
- rcall isr ; PSC1 Capture Event
-.org $0004
- rcall isr ; PSC1 End Cycle
-.org $0005
- rcall isr ; PSC0 Capture Event
-.org $0006
- rcall isr ; PSC0 End Cycle
-.org $0007
- rcall isr ; Analog Comparator 0
-.org $0008
- rcall isr ; Analog Comparator 1
-.org $0009
- rcall isr ; Analog Comparator 2
-.org $000A
- rcall isr ; External Interrupt Request 0
-.org $000B
- rcall isr ; Timer/Counter1 Capture Event
-.org $000C
- rcall isr ; Timer/Counter1 Compare Match A
-.org $000D
- rcall isr ; Timer/Counter Compare Match B
-.org $000E
- rcall isr ;
-.org $000F
- rcall isr ; Timer/Counter1 Overflow
-.org $0010
- rcall isr ; Timer/Counter0 Compare Match A
-.org $0011
- rcall isr ; Timer/Counter0 Overflow
-.org $0012
- rcall isr ; ADC Conversion Complete
-.org $0013
- rcall isr ; External Interrupt Request 1
-.org $0014
- rcall isr ; SPI Serial Transfer Complete
-.org $0015
- rcall isr ; USART, Rx Complete
-.org $0016
- rcall isr ; USART Data Register Empty
-.org $0017
- rcall isr ; USART, Tx Complete
-.org $0018
- rcall isr ; External Interrupt Request 2
-.org $0019
- rcall isr ; Watchdog Timeout Interrupt
-.org $001A
- rcall isr ; EEPROM Ready
-.org $001B
- rcall isr ; Timer Counter 0 Compare Match B
-.org $001C
- rcall isr ; External Interrupt Request 3
-.org $001D
- rcall isr ;
-.org $001E
- rcall isr ;
-.org $001F
- rcall isr ; Store Program Memory Read
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 3072 ; minimum of 0xC00 (from XML) and 0xffff
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 8
- .db "AT90PWM2"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm2/device.inc b/amforth-6.5/avr8/devices/at90pwm2/device.inc
deleted file mode 100644
index 8dd840b..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2/device.inc
+++ /dev/null
@@ -1,1539 +0,0 @@
-; Partname: AT90PWM2
-; Built using part description XML file version 168
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw $7B
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $7C
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw $76
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw $77
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw $7F
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw $AD
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw $AE
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw $AF
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $50
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw $3B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_DA_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw $AC
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw $AB
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw $AA
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EUSART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control and Status Register A
-VE_EUCSRA:
- .dw $ff06
- .db "EUCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRA
-XT_EUCSRA:
- .dw PFA_DOVARIABLE
-PFA_EUCSRA:
- .dw $C8
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control Register B
-VE_EUCSRB:
- .dw $ff06
- .db "EUCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRB
-XT_EUCSRB:
- .dw PFA_DOVARIABLE
-PFA_EUCSRB:
- .dw $C9
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Status Register C
-VE_EUCSRC:
- .dw $ff06
- .db "EUCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRC
-XT_EUCSRC:
- .dw PFA_DOVARIABLE
-PFA_EUCSRC:
- .dw $CA
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART I/O Data Register
-VE_EUDR:
- .dw $ff04
- .db "EUDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUDR
-XT_EUDR:
- .dw PFA_DOVARIABLE
-PFA_EUDR:
- .dw $CE
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register High Byte
-VE_MUBRRH:
- .dw $ff06
- .db "MUBRRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRH
-XT_MUBRRH:
- .dw PFA_DOVARIABLE
-PFA_MUBRRH:
- .dw $CD
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register Low Byte
-VE_MUBRRL:
- .dw $ff06
- .db "MUBRRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRL
-XT_MUBRRL:
- .dw PFA_DOVARIABLE
-PFA_MUBRRL:
- .dw $CC
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_PSC0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register High
-VE_OCR0RAH:
- .dw $ff07
- .db "OCR0RAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RAH
-XT_OCR0RAH:
- .dw PFA_DOVARIABLE
-PFA_OCR0RAH:
- .dw $D5
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register Low
-VE_OCR0RAL:
- .dw $ff07
- .db "OCR0RAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RAL
-XT_OCR0RAL:
- .dw PFA_DOVARIABLE
-PFA_OCR0RAL:
- .dw $D4
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register High
-VE_OCR0RBH:
- .dw $ff07
- .db "OCR0RBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RBH
-XT_OCR0RBH:
- .dw PFA_DOVARIABLE
-PFA_OCR0RBH:
- .dw $D9
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register Low
-VE_OCR0RBL:
- .dw $ff07
- .db "OCR0RBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RBL
-XT_OCR0RBL:
- .dw PFA_DOVARIABLE
-PFA_OCR0RBL:
- .dw $D8
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register High
-VE_OCR0SAH:
- .dw $ff07
- .db "OCR0SAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SAH
-XT_OCR0SAH:
- .dw PFA_DOVARIABLE
-PFA_OCR0SAH:
- .dw $D3
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register Low
-VE_OCR0SAL:
- .dw $ff07
- .db "OCR0SAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SAL
-XT_OCR0SAL:
- .dw PFA_DOVARIABLE
-PFA_OCR0SAL:
- .dw $D2
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register High
-VE_OCR0SBH:
- .dw $ff07
- .db "OCR0SBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SBH
-XT_OCR0SBH:
- .dw PFA_DOVARIABLE
-PFA_OCR0SBH:
- .dw $D7
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register Low
-VE_OCR0SBL:
- .dw $ff07
- .db "OCR0SBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SBL
-XT_OCR0SBL:
- .dw PFA_DOVARIABLE
-PFA_OCR0SBL:
- .dw $D6
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw $DA
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw $DB
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw $DC
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw $DD
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register High
-VE_PICR0H:
- .dw $ff06
- .db "PICR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0H
-XT_PICR0H:
- .dw PFA_DOVARIABLE
-PFA_PICR0H:
- .dw $DF
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register Low
-VE_PICR0L:
- .dw $ff06
- .db "PICR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0L
-XT_PICR0L:
- .dw PFA_DOVARIABLE
-PFA_PICR0L:
- .dw $DE
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw $A0
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw $A1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw $D0
-
-.endif
-
-; ********
-.if WANT_PSC2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register High
-VE_OCR2RAH:
- .dw $ff07
- .db "OCR2RAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RAH
-XT_OCR2RAH:
- .dw PFA_DOVARIABLE
-PFA_OCR2RAH:
- .dw $F5
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register Low
-VE_OCR2RAL:
- .dw $ff07
- .db "OCR2RAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RAL
-XT_OCR2RAL:
- .dw PFA_DOVARIABLE
-PFA_OCR2RAL:
- .dw $F4
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register High
-VE_OCR2RBH:
- .dw $ff07
- .db "OCR2RBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RBH
-XT_OCR2RBH:
- .dw PFA_DOVARIABLE
-PFA_OCR2RBH:
- .dw $F9
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register Low
-VE_OCR2RBL:
- .dw $ff07
- .db "OCR2RBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RBL
-XT_OCR2RBL:
- .dw PFA_DOVARIABLE
-PFA_OCR2RBL:
- .dw $F8
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register High
-VE_OCR2SAH:
- .dw $ff07
- .db "OCR2SAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SAH
-XT_OCR2SAH:
- .dw PFA_DOVARIABLE
-PFA_OCR2SAH:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register Low
-VE_OCR2SAL:
- .dw $ff07
- .db "OCR2SAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SAL
-XT_OCR2SAL:
- .dw PFA_DOVARIABLE
-PFA_OCR2SAL:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register High
-VE_OCR2SBH:
- .dw $ff07
- .db "OCR2SBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SBH
-XT_OCR2SBH:
- .dw PFA_DOVARIABLE
-PFA_OCR2SBH:
- .dw $F7
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register Low
-VE_OCR2SBL:
- .dw $ff07
- .db "OCR2SBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SBL
-XT_OCR2SBL:
- .dw PFA_DOVARIABLE
-PFA_OCR2SBL:
- .dw $F6
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw $FA
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw $FB
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw $FC
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw $FD
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register High
-VE_PICR2H:
- .dw $ff06
- .db "PICR2H"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2H
-XT_PICR2H:
- .dw PFA_DOVARIABLE
-PFA_PICR2H:
- .dw $FF
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register Low
-VE_PICR2L:
- .dw $ff06
- .db "PICR2L"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2L
-XT_PICR2L:
- .dw PFA_DOVARIABLE
-PFA_PICR2L:
- .dw $FE
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw $A4
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw $A5
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw $F1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw $F0
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4C
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4D
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $86
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $8B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $8A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw $82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_USART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw $C5
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw $C4
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw $C0
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw $C1
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw $C2
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw $C6
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm2/device.py b/amforth-6.5/avr8/devices/at90pwm2/device.py
deleted file mode 100644
index 48237b1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2/device.py
+++ /dev/null
@@ -1,155 +0,0 @@
-# Partname: AT90PWM2
-# Built using part description XML file version 168
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$79',
- 'ADCL': '$78',
- 'ADCSRA': '$7A',
- 'ADCSRB': '$7B',
- 'ADMUX': '$7C',
- 'AMP0CSR': '$76',
- 'AMP1CSR': '$77',
- 'DIDR0': '$7E',
- 'DIDR1': '$7F',
- 'AC0CON': '$AD',
- 'AC1CON': '$AE',
- 'AC2CON': '$AF',
- 'ACSR': '$50',
- 'SPMCSR': '$57',
- 'CLKPR': '$61',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$39',
- 'GPIOR2': '$3A',
- 'GPIOR3': '$3B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSCCAL': '$66',
- 'PLLCSR': '$49',
- 'PRR': '$64',
- 'SMCR': '$53',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'DACH': '$AC',
- 'DACL': '$AB',
- 'DACON': '$AA',
- 'EEARH': '$42',
- 'EEARL': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EUCSRA': '$C8',
- 'EUCSRB': '$C9',
- 'EUCSRC': '$CA',
- 'EUDR': '$CE',
- 'MUBRRH': '$CD',
- 'MUBRRL': '$CC',
- 'EICRA': '$69',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'DDRB': '$24',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'DDRD': '$2A',
- 'PIND': '$29',
- 'PORTD': '$2B',
- 'DDRE': '$2D',
- 'PINE': '$2C',
- 'PORTE': '$2E',
- 'OCR0RAH': '$D5',
- 'OCR0RAL': '$D4',
- 'OCR0RBH': '$D9',
- 'OCR0RBL': '$D8',
- 'OCR0SAH': '$D3',
- 'OCR0SAL': '$D2',
- 'OCR0SBH': '$D7',
- 'OCR0SBL': '$D6',
- 'PCNF0': '$DA',
- 'PCTL0': '$DB',
- 'PFRC0A': '$DC',
- 'PFRC0B': '$DD',
- 'PICR0H': '$DF',
- 'PICR0L': '$DE',
- 'PIFR0': '$A0',
- 'PIM0': '$A1',
- 'PSOC0': '$D0',
- 'OCR2RAH': '$F5',
- 'OCR2RAL': '$F4',
- 'OCR2RBH': '$F9',
- 'OCR2RBL': '$F8',
- 'OCR2SAH': '$F3',
- 'OCR2SAL': '$F2',
- 'OCR2SBH': '$F7',
- 'OCR2SBL': '$F6',
- 'PCNF2': '$FA',
- 'PCTL2': '$FB',
- 'PFRC2A': '$FC',
- 'PFRC2B': '$FD',
- 'PICR2H': '$FF',
- 'PICR2L': '$FE',
- 'PIFR2': '$A4',
- 'PIM2': '$A5',
- 'POM2': '$F1',
- 'PSOC2': '$F0',
- 'SPCR': '$4C',
- 'SPDR': '$4E',
- 'SPSR': '$4D',
- 'GTCCR': '$43',
- 'OCR0A': '$47',
- 'OCR0B': '$48',
- 'TCCR0A': '$44',
- 'TCCR0B': '$45',
- 'TCNT0': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'ICR1H': '$87',
- 'ICR1L': '$86',
- 'OCR1AH': '$89',
- 'OCR1AL': '$88',
- 'OCR1BH': '$8B',
- 'OCR1BL': '$8A',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCCR1C': '$82',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'UBRRH': '$C5',
- 'UBRRL': '$C4',
- 'UCSRA': '$C0',
- 'UCSRB': '$C1',
- 'UCSRC': '$C2',
- 'UDR': '$C6',
- 'WDTCSR': '$60',
- 'PSC2_CAPTAddr': '$0001',
- 'PSC2_ECAddr': '$0002',
- 'PSC1_CAPTAddr': '$0003',
- 'PSC1_ECAddr': '$0004',
- 'PSC0_CAPTAddr': '$0005',
- 'PSC0_ECAddr': '$0006',
- 'ANALOG_COMP_0Addr': '$0007',
- 'ANALOG_COMP_1Addr': '$0008',
- 'ANALOG_COMP_2Addr': '$0009',
- 'INT0Addr': '$000A',
- 'TIMER1_CAPTAddr': '$000B',
- 'TIMER1_COMPAAddr': '$000C',
- 'TIMER1_COMPBAddr': '$000D',
- 'RESERVED15Addr': '$000E',
- 'TIMER1_OVFAddr': '$000F',
- 'TIMER0_COMP_AAddr': '$0010',
- 'TIMER0_OVFAddr': '$0011',
- 'ADCAddr': '$0012',
- 'INT1Addr': '$0013',
- 'SPI_STCAddr': '$0014',
- 'USART_RXAddr': '$0015',
- 'USART_UDREAddr': '$0016',
- 'USART_TXAddr': '$0017',
- 'INT2Addr': '$0018',
- 'WDTAddr': '$0019',
- 'EE_READYAddr': '$001A',
- 'TIMER0_COMPBAddr': '$001B',
- 'INT3Addr': '$001C',
- 'RESERVED30Addr': '$001D',
- 'RESERVED31Addr': '$001E',
- 'SPM_READYAddr': '$001F'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt b/amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt
deleted file mode 100644
index cc489bc..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt
+++ /dev/null
@@ -1,423 +0,0 @@
-\ Partname: AT90PWM216
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EUSART
-&206 constant EUDR \ EUSART I/O Data Register
-&200 constant EUCSRA \ EUSART Control and Status Register A
- $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
- $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
-&201 constant EUCSRB \ EUSART Control Register B
- $10 constant EUCSRB_EUSART \ EUSART Enable Bit
- $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
- $02 constant EUCSRB_EMCH \ Manchester Mode Bit
- $01 constant EUCSRB_BODR \ Order Bit
-&202 constant EUCSRC \ EUSART Status Register C
- $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
- $04 constant EUCSRC_F1617 \ F1617 Bit
- $03 constant EUCSRC_STP \ Stop Bits
-&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
- $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
-&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
- $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
-\ ANALOG_COMPARATOR
-&173 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&174 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&175 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&172 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&171 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&170 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&59 constant GPIOR3 \ General Purpose IO Register 3
- $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $E0 constant PRR_PRPSC \ Power Reduction PSC2
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
-&126 constant DIDR0 \ Digital Input Disable Register 0
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $20 constant DIDR1_ACMP0D \
- $10 constant DIDR1_AMP0PD \
- $08 constant DIDR1_AMP0ND \
- $04 constant DIDR1_ADC10D \
- $02 constant DIDR1_ADC9D \
- $01 constant DIDR1_ADC8D \
-&118 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $03 constant AMP0CSR_AMP0TS \
-&119 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $03 constant AMP1CSR_AMP1TS \
-\ USART
-&198 constant UDR \ USART I/O Data Register
-&192 constant UCSRA \ USART Control and Status register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data Overrun
- $04 constant UCSRA_UPE \ USART Parity Error
- $02 constant UCSRA_U2X \ Double USART Transmission Bit
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&193 constant UCSRB \ USART Control an Status register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&194 constant UCSRC \ USART Control an Status register C
- $40 constant UCSRC_UMSEL0 \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size Bits
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&197 constant UBRRH \ USART Baud Rate Register High Byte
- $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
-&196 constant UBRRL \ USART Baud Rate Register Low Byte
- $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC0
-&222 constant PICR0 \ PSC 0 Input Capture Register
-&221 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
- $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
-&220 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
- $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
-&219 constant PCTL0 \ PSC 0 Control Register
- $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
- $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
- $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
- $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- $01 constant PCTL0_PRUN0 \ PSC 0 Run
-&218 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
- $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
-&216 constant OCR0RB \ Output Compare RB Register
-&214 constant OCR0SB \ Output Compare SB Register
-&212 constant OCR0RA \ Output Compare RA Register
-&210 constant OCR0SA \ Output Compare SA Register
-&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
- $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
- $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
-&161 constant PIM0 \ PSC0 Interrupt Mask Register
- $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
- $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
- $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
-&160 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- $08 constant PIFR0_PEV0A \ External Event A Interrupt
- $06 constant PIFR0_PRN0 \ Ramp Number
- $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
-\ PSC2
-&254 constant PICR2 \ PSC 2 Input Capture Register
-&253 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
- $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
-&252 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
- $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
-&251 constant PCTL2 \ PSC 2 Control Register
- $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
- $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
- $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
- $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- $01 constant PCTL2_PRUN2 \ PSC 2 Run
-&250 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
- $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
-&248 constant OCR2RB \ Output Compare RB Register
-&246 constant OCR2SB \ Output Compare SB Register
-&244 constant OCR2RA \ Output Compare RA Register
-&242 constant OCR2SA \ Output Compare SA Register
-&241 constant POM2 \ PSC 2 Output Matrix
- $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
-&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
- $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
- $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
-&165 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
- $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
- $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
-&164 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- $08 constant PIFR2_PEV2A \ External Event A Interrupt
- $06 constant PIFR2_PRN2 \ Ramp Number
- $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
-
-\ Interrupts
-&2 constant PSC2_CAPTAddr \ PSC2 Capture Event
-&4 constant PSC2_ECAddr \ PSC2 End Cycle
-&6 constant PSC1_CAPTAddr \ PSC1 Capture Event
-&8 constant PSC1_ECAddr \ PSC1 End Cycle
-&10 constant PSC0_CAPTAddr \ PSC0 Capture Event
-&12 constant PSC0_ECAddr \ PSC0 End Cycle
-&14 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-&16 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-&18 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-&20 constant INT0Addr \ External Interrupt Request 0
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant RESERVED15Addr \
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant ADCAddr \ ADC Conversion Complete
-&38 constant INT1Addr \ External Interrupt Request 1
-&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&42 constant USART__RXAddr \ USART, Rx Complete
-&44 constant USART__UDREAddr \ USART Data Register Empty
-&46 constant USART__TXAddr \ USART, Tx Complete
-&48 constant INT2Addr \ External Interrupt Request 2
-&50 constant WDTAddr \ Watchdog Timeout Interrupt
-&52 constant EE_READYAddr \ EEPROM Ready
-&54 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-&56 constant INT3Addr \ External Interrupt Request 3
-&58 constant RESERVED30Addr \
-&60 constant RESERVED31Addr \
-&62 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm216/device.asm b/amforth-6.5/avr8/devices/at90pwm216/device.asm
deleted file mode 100644
index 01c61c6..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/device.asm
+++ /dev/null
@@ -1,123 +0,0 @@
-; Partname: AT90PWM216
-; generated automatically, do not edit
-
-.nolist
- .include "pwm216def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EUSART = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_USART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC2 = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; PSC2 Capture Event
-.org 4
- rcall isr ; PSC2 End Cycle
-.org 6
- rcall isr ; PSC1 Capture Event
-.org 8
- rcall isr ; PSC1 End Cycle
-.org 10
- rcall isr ; PSC0 Capture Event
-.org 12
- rcall isr ; PSC0 End Cycle
-.org 14
- rcall isr ; Analog Comparator 0
-.org 16
- rcall isr ; Analog Comparator 1
-.org 18
- rcall isr ; Analog Comparator 2
-.org 20
- rcall isr ; External Interrupt Request 0
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ;
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; ADC Conversion Complete
-.org 38
- rcall isr ; External Interrupt Request 1
-.org 40
- rcall isr ; SPI Serial Transfer Complete
-.org 42
- rcall isr ; USART, Rx Complete
-.org 44
- rcall isr ; USART Data Register Empty
-.org 46
- rcall isr ; USART, Tx Complete
-.org 48
- rcall isr ; External Interrupt Request 2
-.org 50
- rcall isr ; Watchdog Timeout Interrupt
-.org 52
- rcall isr ; EEPROM Ready
-.org 54
- rcall isr ; Timer Counter 0 Compare Match B
-.org 56
- rcall isr ; External Interrupt Request 3
-.org 58
- rcall isr ;
-.org 60
- rcall isr ;
-.org 62
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 32
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 10
- .db "AT90PWM216"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm216/device.inc b/amforth-6.5/avr8/devices/at90pwm216/device.inc
deleted file mode 100644
index dd83403..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/device.inc
+++ /dev/null
@@ -1,1281 +0,0 @@
-; Partname: AT90PWM216
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EUSART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART I/O Data Register
-VE_EUDR:
- .dw $ff04
- .db "EUDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUDR
-XT_EUDR:
- .dw PFA_DOVARIABLE
-PFA_EUDR:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control and Status Register A
-VE_EUCSRA:
- .dw $ff06
- .db "EUCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRA
-XT_EUCSRA:
- .dw PFA_DOVARIABLE
-PFA_EUCSRA:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control Register B
-VE_EUCSRB:
- .dw $ff06
- .db "EUCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRB
-XT_EUCSRB:
- .dw PFA_DOVARIABLE
-PFA_EUCSRB:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Status Register C
-VE_EUCSRC:
- .dw $ff06
- .db "EUCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRC
-XT_EUCSRC:
- .dw PFA_DOVARIABLE
-PFA_EUCSRC:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register High Byte
-VE_MUBRRH:
- .dw $ff06
- .db "MUBRRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRH
-XT_MUBRRH:
- .dw PFA_DOVARIABLE
-PFA_MUBRRH:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register Low Byte
-VE_MUBRRL:
- .dw $ff06
- .db "MUBRRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRL
-XT_MUBRRL:
- .dw PFA_DOVARIABLE
-PFA_MUBRRL:
- .dw 204
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 170
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 119
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 197
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 196
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register
-VE_PICR0:
- .dw $ff05
- .db "PICR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0
-XT_PICR0:
- .dw PFA_DOVARIABLE
-PFA_PICR0:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR0RB:
- .dw $ff06
- .db "OCR0RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RB
-XT_OCR0RB:
- .dw PFA_DOVARIABLE
-PFA_OCR0RB:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR0SB:
- .dw $ff06
- .db "OCR0SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SB
-XT_OCR0SB:
- .dw PFA_DOVARIABLE
-PFA_OCR0SB:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR0RA:
- .dw $ff06
- .db "OCR0RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RA
-XT_OCR0RA:
- .dw PFA_DOVARIABLE
-PFA_OCR0RA:
- .dw 212
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR0SA:
- .dw $ff06
- .db "OCR0SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SA
-XT_OCR0SA:
- .dw PFA_DOVARIABLE
-PFA_OCR0SA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw 160
-
-.endif
-.if WANT_PSC2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register
-VE_PICR2:
- .dw $ff05
- .db "PICR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2
-XT_PICR2:
- .dw PFA_DOVARIABLE
-PFA_PICR2:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR2RB:
- .dw $ff06
- .db "OCR2RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RB
-XT_OCR2RB:
- .dw PFA_DOVARIABLE
-PFA_OCR2RB:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR2SB:
- .dw $ff06
- .db "OCR2SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SB
-XT_OCR2SB:
- .dw PFA_DOVARIABLE
-PFA_OCR2SB:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR2RA:
- .dw $ff06
- .db "OCR2RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RA
-XT_OCR2RA:
- .dw PFA_DOVARIABLE
-PFA_OCR2RA:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR2SA:
- .dw $ff06
- .db "OCR2SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SA
-XT_OCR2SA:
- .dw PFA_DOVARIABLE
-PFA_OCR2SA:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw 164
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm216/device.py b/amforth-6.5/avr8/devices/at90pwm216/device.py
deleted file mode 100644
index af38406..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/device.py
+++ /dev/null
@@ -1,448 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM216
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
- 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
- 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
- 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
- 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'RESERVED15Addr' : '#28', #
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'ADCAddr' : '#36', # ADC Conversion Complete
- 'INT1Addr' : '#38', # External Interrupt Request 1
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#42', # USART, Rx Complete
- 'USART_UDREAddr' : '#44', # USART Data Register Empty
- 'USART_TXAddr' : '#46', # USART, Tx Complete
- 'INT2Addr' : '#48', # External Interrupt Request 2
- 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
- 'INT3Addr' : '#56', # External Interrupt Request 3
- 'RESERVED30Addr' : '#58', #
- 'RESERVED31Addr' : '#60', #
- 'SPM_READYAddr' : '#62', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EUSART
- 'EUDR' : '$ce', # EUSART I/O Data Register
- 'EUCSRA' : '$c8', # EUSART Control and Status Regi
- 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
- 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
- 'EUCSRB' : '$c9', # EUSART Control Register B
- 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
- 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
- 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
- 'EUCSRB_BODR': '$1', # Order Bit
- 'EUCSRC' : '$ca', # EUSART Status Register C
- 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
- 'EUCSRC_F1617': '$4', # F1617 Bit
- 'EUCSRC_STP': '$3', # Stop Bits
- 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
- 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
- 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
- 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$af', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$ac', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$ab', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$aa', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR3' : '$3b', # General Purpose IO Register 3
- 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRPSC': '$e0', # Power Reduction PSC2
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_ACMP0D': '$20', #
- 'DIDR1_AMP0PD': '$10', #
- 'DIDR1_AMP0ND': '$8', #
- 'DIDR1_ADC10D': '$4', #
- 'DIDR1_ADC9D': '$2', #
- 'DIDR1_ADC8D': '$1', #
- 'AMP0CSR' : '$76', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0TS': '$3', #
- 'AMP1CSR' : '$77', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMP1TS': '$3', #
-
-# Module USART
- 'UDR' : '$c6', # USART I/O Data Register
- 'UCSRA' : '$c0', # USART Control and Status regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data Overrun
- 'UCSRA_UPE': '$4', # USART Parity Error
- 'UCSRA_U2X': '$2', # Double USART Transmission Bit
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$c1', # USART Control an Status regist
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$c2', # USART Control an Status regist
- 'UCSRC_UMSEL0': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size Bits
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$c5', # USART Baud Rate Register High
- 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
- 'UBRRL' : '$c4', # USART Baud Rate Register Low B
- 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC0
- 'PICR0' : '$de', # PSC 0 Input Capture Register
- 'PFRC0B' : '$dd', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$dc', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$db', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$da', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$d8', # Output Compare RB Register
- 'OCR0SB' : '$d6', # Output Compare SB Register
- 'OCR0RA' : '$d4', # Output Compare RA Register
- 'OCR0SA' : '$d2', # Output Compare SA Register
- 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
- 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
- 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
- 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
- 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
- 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC2
- 'PICR2' : '$fe', # PSC 2 Input Capture Register
- 'PFRC2B' : '$fd', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$fc', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$fb', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$fa', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'OCR2RB' : '$f8', # Output Compare RB Register
- 'OCR2SB' : '$f6', # Output Compare SB Register
- 'OCR2RA' : '$f4', # Output Compare RA Register
- 'OCR2SA' : '$f2', # Output Compare SA Register
- 'POM2' : '$f1', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
- 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
- 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt b/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt
deleted file mode 100644
index 30d6e54..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt
+++ /dev/null
@@ -1,423 +0,0 @@
-\ Partname: AT90PWM2B
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EUSART
-&206 constant EUDR \ EUSART I/O Data Register
-&200 constant EUCSRA \ EUSART Control and Status Register A
- $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
- $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
-&201 constant EUCSRB \ EUSART Control Register B
- $10 constant EUCSRB_EUSART \ EUSART Enable Bit
- $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
- $02 constant EUCSRB_EMCH \ Manchester Mode Bit
- $01 constant EUCSRB_BODR \ Order Bit
-&202 constant EUCSRC \ EUSART Status Register C
- $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
- $04 constant EUCSRC_F1617 \ F1617 Bit
- $03 constant EUCSRC_STP \ Stop Bits
-&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
- $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
-&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
- $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
-\ ANALOG_COMPARATOR
-&173 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&174 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&175 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&172 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&171 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&170 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&59 constant GPIOR3 \ General Purpose IO Register 3
- $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $E0 constant PRR_PRPSC \ Power Reduction PSC2
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
-&126 constant DIDR0 \ Digital Input Disable Register 0
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $20 constant DIDR1_ACMP0D \
- $10 constant DIDR1_AMP0PD \
- $08 constant DIDR1_AMP0ND \
- $04 constant DIDR1_ADC10D \
- $02 constant DIDR1_ADC9D \
- $01 constant DIDR1_ADC8D \
-&118 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $03 constant AMP0CSR_AMP0TS \
-&119 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $03 constant AMP1CSR_AMP1TS \
-\ USART
-&198 constant UDR \ USART I/O Data Register
-&192 constant UCSRA \ USART Control and Status register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data Overrun
- $04 constant UCSRA_UPE \ USART Parity Error
- $02 constant UCSRA_U2X \ Double USART Transmission Bit
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&193 constant UCSRB \ USART Control an Status register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&194 constant UCSRC \ USART Control an Status register C
- $40 constant UCSRC_UMSEL0 \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size Bits
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&197 constant UBRRH \ USART Baud Rate Register High Byte
- $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
-&196 constant UBRRL \ USART Baud Rate Register Low Byte
- $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC0
-&222 constant PICR0 \ PSC 0 Input Capture Register
-&221 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
- $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
-&220 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
- $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
-&219 constant PCTL0 \ PSC 0 Control Register
- $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
- $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
- $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
- $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- $01 constant PCTL0_PRUN0 \ PSC 0 Run
-&218 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
- $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
-&216 constant OCR0RB \ Output Compare RB Register
-&214 constant OCR0SB \ Output Compare SB Register
-&212 constant OCR0RA \ Output Compare RA Register
-&210 constant OCR0SA \ Output Compare SA Register
-&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
- $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
- $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
-&161 constant PIM0 \ PSC0 Interrupt Mask Register
- $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
- $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
- $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
-&160 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- $08 constant PIFR0_PEV0A \ External Event A Interrupt
- $06 constant PIFR0_PRN0 \ Ramp Number
- $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
-\ PSC2
-&254 constant PICR2 \ PSC 2 Input Capture Register
-&253 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
- $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
-&252 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
- $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
-&251 constant PCTL2 \ PSC 2 Control Register
- $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
- $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
- $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
- $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- $01 constant PCTL2_PRUN2 \ PSC 2 Run
-&250 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
- $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
-&248 constant OCR2RB \ Output Compare RB Register
-&246 constant OCR2SB \ Output Compare SB Register
-&244 constant OCR2RA \ Output Compare RA Register
-&242 constant OCR2SA \ Output Compare SA Register
-&241 constant POM2 \ PSC 2 Output Matrix
- $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
-&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
- $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
- $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
-&165 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
- $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
- $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
-&164 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- $08 constant PIFR2_PEV2A \ External Event A Interrupt
- $06 constant PIFR2_PRN2 \ Ramp Number
- $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
-
-\ Interrupts
-&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
-&2 constant PSC2_ECAddr \ PSC2 End Cycle
-&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
-&4 constant PSC1_ECAddr \ PSC1 End Cycle
-&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
-&6 constant PSC0_ECAddr \ PSC0 End Cycle
-&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-&10 constant INT0Addr \ External Interrupt Request 0
-&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&14 constant RESERVED15Addr \
-&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&18 constant ADCAddr \ ADC Conversion Complete
-&19 constant INT1Addr \ External Interrupt Request 1
-&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&21 constant USART__RXAddr \ USART, Rx Complete
-&22 constant USART__UDREAddr \ USART Data Register Empty
-&23 constant USART__TXAddr \ USART, Tx Complete
-&24 constant INT2Addr \ External Interrupt Request 2
-&25 constant WDTAddr \ Watchdog Timeout Interrupt
-&26 constant EE_READYAddr \ EEPROM Ready
-&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-&28 constant INT3Addr \ External Interrupt Request 3
-&29 constant RESERVED30Addr \
-&30 constant RESERVED31Addr \
-&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.asm b/amforth-6.5/avr8/devices/at90pwm2b/device.asm
deleted file mode 100644
index 6656395..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/device.asm
+++ /dev/null
@@ -1,123 +0,0 @@
-; Partname: AT90PWM2B
-; generated automatically, do not edit
-
-.nolist
- .include "pwm2Bdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EUSART = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_USART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC2 = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; PSC2 Capture Event
-.org 2
- rcall isr ; PSC2 End Cycle
-.org 3
- rcall isr ; PSC1 Capture Event
-.org 4
- rcall isr ; PSC1 End Cycle
-.org 5
- rcall isr ; PSC0 Capture Event
-.org 6
- rcall isr ; PSC0 End Cycle
-.org 7
- rcall isr ; Analog Comparator 0
-.org 8
- rcall isr ; Analog Comparator 1
-.org 9
- rcall isr ; Analog Comparator 2
-.org 10
- rcall isr ; External Interrupt Request 0
-.org 11
- rcall isr ; Timer/Counter1 Capture Event
-.org 12
- rcall isr ; Timer/Counter1 Compare Match A
-.org 13
- rcall isr ; Timer/Counter Compare Match B
-.org 14
- rcall isr ;
-.org 15
- rcall isr ; Timer/Counter1 Overflow
-.org 16
- rcall isr ; Timer/Counter0 Compare Match A
-.org 17
- rcall isr ; Timer/Counter0 Overflow
-.org 18
- rcall isr ; ADC Conversion Complete
-.org 19
- rcall isr ; External Interrupt Request 1
-.org 20
- rcall isr ; SPI Serial Transfer Complete
-.org 21
- rcall isr ; USART, Rx Complete
-.org 22
- rcall isr ; USART Data Register Empty
-.org 23
- rcall isr ; USART, Tx Complete
-.org 24
- rcall isr ; External Interrupt Request 2
-.org 25
- rcall isr ; Watchdog Timeout Interrupt
-.org 26
- rcall isr ; EEPROM Ready
-.org 27
- rcall isr ; Timer Counter 0 Compare Match B
-.org 28
- rcall isr ; External Interrupt Request 3
-.org 29
- rcall isr ;
-.org 30
- rcall isr ;
-.org 31
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 32
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 9
- .db "AT90PWM2B",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.inc b/amforth-6.5/avr8/devices/at90pwm2b/device.inc
deleted file mode 100644
index 3605e6b..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/device.inc
+++ /dev/null
@@ -1,1281 +0,0 @@
-; Partname: AT90PWM2B
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EUSART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART I/O Data Register
-VE_EUDR:
- .dw $ff04
- .db "EUDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUDR
-XT_EUDR:
- .dw PFA_DOVARIABLE
-PFA_EUDR:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control and Status Register A
-VE_EUCSRA:
- .dw $ff06
- .db "EUCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRA
-XT_EUCSRA:
- .dw PFA_DOVARIABLE
-PFA_EUCSRA:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control Register B
-VE_EUCSRB:
- .dw $ff06
- .db "EUCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRB
-XT_EUCSRB:
- .dw PFA_DOVARIABLE
-PFA_EUCSRB:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Status Register C
-VE_EUCSRC:
- .dw $ff06
- .db "EUCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRC
-XT_EUCSRC:
- .dw PFA_DOVARIABLE
-PFA_EUCSRC:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register High Byte
-VE_MUBRRH:
- .dw $ff06
- .db "MUBRRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRH
-XT_MUBRRH:
- .dw PFA_DOVARIABLE
-PFA_MUBRRH:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register Low Byte
-VE_MUBRRL:
- .dw $ff06
- .db "MUBRRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRL
-XT_MUBRRL:
- .dw PFA_DOVARIABLE
-PFA_MUBRRL:
- .dw 204
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 170
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 119
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 197
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 196
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register
-VE_PICR0:
- .dw $ff05
- .db "PICR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0
-XT_PICR0:
- .dw PFA_DOVARIABLE
-PFA_PICR0:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR0RB:
- .dw $ff06
- .db "OCR0RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RB
-XT_OCR0RB:
- .dw PFA_DOVARIABLE
-PFA_OCR0RB:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR0SB:
- .dw $ff06
- .db "OCR0SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SB
-XT_OCR0SB:
- .dw PFA_DOVARIABLE
-PFA_OCR0SB:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR0RA:
- .dw $ff06
- .db "OCR0RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RA
-XT_OCR0RA:
- .dw PFA_DOVARIABLE
-PFA_OCR0RA:
- .dw 212
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR0SA:
- .dw $ff06
- .db "OCR0SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SA
-XT_OCR0SA:
- .dw PFA_DOVARIABLE
-PFA_OCR0SA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw 160
-
-.endif
-.if WANT_PSC2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register
-VE_PICR2:
- .dw $ff05
- .db "PICR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2
-XT_PICR2:
- .dw PFA_DOVARIABLE
-PFA_PICR2:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR2RB:
- .dw $ff06
- .db "OCR2RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RB
-XT_OCR2RB:
- .dw PFA_DOVARIABLE
-PFA_OCR2RB:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR2SB:
- .dw $ff06
- .db "OCR2SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SB
-XT_OCR2SB:
- .dw PFA_DOVARIABLE
-PFA_OCR2SB:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR2RA:
- .dw $ff06
- .db "OCR2RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RA
-XT_OCR2RA:
- .dw PFA_DOVARIABLE
-PFA_OCR2RA:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR2SA:
- .dw $ff06
- .db "OCR2SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SA
-XT_OCR2SA:
- .dw PFA_DOVARIABLE
-PFA_OCR2SA:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw 164
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.py b/amforth-6.5/avr8/devices/at90pwm2b/device.py
deleted file mode 100644
index 4ef048e..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/device.py
+++ /dev/null
@@ -1,448 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM2B
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
- 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
- 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
- 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
- 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'RESERVED15Addr' : '#28', #
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'ADCAddr' : '#36', # ADC Conversion Complete
- 'INT1Addr' : '#38', # External Interrupt Request 1
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#42', # USART, Rx Complete
- 'USART_UDREAddr' : '#44', # USART Data Register Empty
- 'USART_TXAddr' : '#46', # USART, Tx Complete
- 'INT2Addr' : '#48', # External Interrupt Request 2
- 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
- 'INT3Addr' : '#56', # External Interrupt Request 3
- 'RESERVED30Addr' : '#58', #
- 'RESERVED31Addr' : '#60', #
- 'SPM_READYAddr' : '#62', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EUSART
- 'EUDR' : '$ce', # EUSART I/O Data Register
- 'EUCSRA' : '$c8', # EUSART Control and Status Regi
- 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
- 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
- 'EUCSRB' : '$c9', # EUSART Control Register B
- 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
- 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
- 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
- 'EUCSRB_BODR': '$1', # Order Bit
- 'EUCSRC' : '$ca', # EUSART Status Register C
- 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
- 'EUCSRC_F1617': '$4', # F1617 Bit
- 'EUCSRC_STP': '$3', # Stop Bits
- 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
- 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
- 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
- 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$af', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$ac', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$ab', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$aa', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR3' : '$3b', # General Purpose IO Register 3
- 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRPSC': '$e0', # Power Reduction PSC2
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_ACMP0D': '$20', #
- 'DIDR1_AMP0PD': '$10', #
- 'DIDR1_AMP0ND': '$8', #
- 'DIDR1_ADC10D': '$4', #
- 'DIDR1_ADC9D': '$2', #
- 'DIDR1_ADC8D': '$1', #
- 'AMP0CSR' : '$76', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0TS': '$3', #
- 'AMP1CSR' : '$77', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMP1TS': '$3', #
-
-# Module USART
- 'UDR' : '$c6', # USART I/O Data Register
- 'UCSRA' : '$c0', # USART Control and Status regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data Overrun
- 'UCSRA_UPE': '$4', # USART Parity Error
- 'UCSRA_U2X': '$2', # Double USART Transmission Bit
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$c1', # USART Control an Status regist
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$c2', # USART Control an Status regist
- 'UCSRC_UMSEL0': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size Bits
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$c5', # USART Baud Rate Register High
- 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
- 'UBRRL' : '$c4', # USART Baud Rate Register Low B
- 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC0
- 'PICR0' : '$de', # PSC 0 Input Capture Register
- 'PFRC0B' : '$dd', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$dc', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$db', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$da', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$d8', # Output Compare RB Register
- 'OCR0SB' : '$d6', # Output Compare SB Register
- 'OCR0RA' : '$d4', # Output Compare RA Register
- 'OCR0SA' : '$d2', # Output Compare SA Register
- 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
- 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
- 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
- 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
- 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
- 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC2
- 'PICR2' : '$fe', # PSC 2 Input Capture Register
- 'PFRC2B' : '$fd', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$fc', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$fb', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$fa', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'OCR2RB' : '$f8', # Output Compare RB Register
- 'OCR2SB' : '$f6', # Output Compare SB Register
- 'OCR2RA' : '$f4', # Output Compare RA Register
- 'OCR2SA' : '$f2', # Output Compare SA Register
- 'POM2' : '$f1', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
- 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
- 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt b/amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt
deleted file mode 100644
index b143f5d..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt
+++ /dev/null
@@ -1,217 +0,0 @@
-\ Partname: AT90PWM3
-\ Built using part description XML file version 179
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant ADCH \ ADC Data Register High Byte
-78 constant ADCL \ ADC Data Register Low Byte
-7A constant ADCSRA \ The ADC Control and Status register
-7B constant ADCSRB \ ADC Control and Status Register B
-7C constant ADMUX \ The ADC multiplexer Selection Register
-76 constant AMP0CSR \
-77 constant AMP1CSR \
-7E constant DIDR0 \ Digital Input Disable Register 0
-7F constant DIDR1 \ Digital Input Disable Register 0
-
-\ ANALOG_COMPARATOR
-AD constant AC0CON \ Analog Comparator 0 Control Register
-AE constant AC1CON \ Analog Comparator 1 Control Register
-AF constant AC2CON \ Analog Comparator 2 Control Register
-50 constant ACSR \ Analog Comparator Status Register
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control Register
-
-\ CPU
-61 constant CLKPR \
-3E constant GPIOR0 \ General Purpose IO Register 0
-39 constant GPIOR1 \ General Purpose IO Register 1
-3A constant GPIOR2 \ General Purpose IO Register 2
-3B constant GPIOR3 \ General Purpose IO Register 3
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-66 constant OSCCAL \ Oscillator Calibration Value
-49 constant PLLCSR \ PLL Control And Status Register
-64 constant PRR \ Power Reduction Register
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ DA_CONVERTER
-AC constant DACH \ DAC Data Register High Byte
-AB constant DACL \ DAC Data Register Low Byte
-AA constant DACON \ DAC Control Register
-
-\ EEPROM
-42 constant EEARH \ EEPROM Read/Write Access High Byte
-41 constant EEARL \ EEPROM Read/Write Access Low Byte
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EUSART
-C8 constant EUCSRA \ EUSART Control and Status Register A
-C9 constant EUCSRB \ EUSART Control Register B
-CA constant EUCSRC \ EUSART Status Register C
-CE constant EUDR \ EUSART I/O Data Register
-CD constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
-CC constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register A
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-
-\ PORTB
-24 constant DDRB \ Port B Data Direction Register
-23 constant PINB \ Port B Input Pins
-25 constant PORTB \ Port B Data Register
-
-\ PORTC
-27 constant DDRC \ Port C Data Direction Register
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ PORTD
-2A constant DDRD \ Port D Data Direction Register
-29 constant PIND \ Port D Input Pins
-2B constant PORTD \ Port D Data Register
-
-\ PORTE
-2D constant DDRE \ Port E Data Direction Register
-2C constant PINE \ Port E Input Pins
-2E constant PORTE \ Port E Data Register
-
-\ PSC0
-D5 constant OCR0RAH \ Output Compare RA Register High
-D4 constant OCR0RAL \ Output Compare RA Register Low
-D9 constant OCR0RBH \ Output Compare RB Register High
-D8 constant OCR0RBL \ Output Compare RB Register Low
-D3 constant OCR0SAH \ Output Compare SA Register High
-D2 constant OCR0SAL \ Output Compare SA Register Low
-D7 constant OCR0SBH \ Output Compare SB Register High
-D6 constant OCR0SBL \ Output Compare SB Register Low
-DA constant PCNF0 \ PSC 0 Configuration Register
-DB constant PCTL0 \ PSC 0 Control Register
-DC constant PFRC0A \ PSC 0 Input A Control
-DD constant PFRC0B \ PSC 0 Input B Control
-DF constant PICR0H \ PSC 0 Input Capture Register High
-DE constant PICR0L \ PSC 0 Input Capture Register Low
-A0 constant PIFR0 \ PSC0 Interrupt Flag Register
-A1 constant PIM0 \ PSC0 Interrupt Mask Register
-D0 constant PSOC0 \ PSC0 Synchro and Output Configuration
-
-\ PSC1
-E5 constant OCR1RAH \ Output Compare RA Register High
-E4 constant OCR1RAL \ Output Compare RA Register Low
-E9 constant OCR1RBH \ Output Compare RB Register High
-E8 constant OCR1RBL \ Output Compare RB Register Low
-E3 constant OCR1SAH \ Output Compare SA Register High
-E2 constant OCR1SAL \ Output Compare SA Register Low
-E7 constant OCR1SBH \ Output Compare SB Register High
-E6 constant OCR1SBL \ Output Compare SB Register Low
-EA constant PCNF1 \ PSC 1 Configuration Register
-EB constant PCTL1 \ PSC 1 Control Register
-EC constant PFRC1A \ PSC 1 Input B Control
-ED constant PFRC1B \ PSC 1 Input B Control
-EF constant PICR1H \ PSC 1 Input Capture Register High
-EE constant PICR1L \ PSC 1 Input Capture Register Low
-A2 constant PIFR1 \ PSC1 Interrupt Flag Register
-A3 constant PIM1 \ PSC1 Interrupt Mask Register
-E0 constant PSOC1 \ PSC1 Synchro and Output Configuration
-
-\ PSC2
-F5 constant OCR2RAH \ Output Compare RA Register High
-F4 constant OCR2RAL \ Output Compare RA Register Low
-F9 constant OCR2RBH \ Output Compare RB Register High
-F8 constant OCR2RBL \ Output Compare RB Register Low
-F3 constant OCR2SAH \ Output Compare SA Register High
-F2 constant OCR2SAL \ Output Compare SA Register Low
-F7 constant OCR2SBH \ Output Compare SB Register High
-F6 constant OCR2SBL \ Output Compare SB Register Low
-FA constant PCNF2 \ PSC 2 Configuration Register
-FB constant PCTL2 \ PSC 2 Control Register
-FC constant PFRC2A \ PSC 2 Input B Control
-FD constant PFRC2B \ PSC 2 Input B Control
-FF constant PICR2H \ PSC 2 Input Capture Register High
-FE constant PICR2L \ PSC 2 Input Capture Register Low
-A4 constant PIFR2 \ PSC2 Interrupt Flag Register
-A5 constant PIM2 \ PSC2 Interrupt Mask Register
-F1 constant POM2 \ PSC 2 Output Matrix
-F0 constant PSOC2 \ PSC2 Synchro and Output Configuration
-
-\ SPI
-4C constant SPCR \ SPI Control Register
-4E constant SPDR \ SPI Data Register
-4D constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-43 constant GTCCR \ General Timer/Counter Control Register
-47 constant OCR0A \ Timer/Counter0 Output Compare Register
-48 constant OCR0B \ Timer/Counter0 Output Compare Register
-44 constant TCCR0A \ Timer/Counter Control Register A
-45 constant TCCR0B \ Timer/Counter Control Register B
-46 constant TCNT0 \ Timer/Counter0
-35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-89 constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-88 constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-8B constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-8A constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-80 constant TCCR1A \ Timer/Counter1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-82 constant TCCR1C \ Timer/Counter1 Control Register C
-85 constant TCNT1H \ Timer/Counter1 High Byte
-84 constant TCNT1L \ Timer/Counter1 Low Byte
-36 constant TIFR1 \ Timer/Counter Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
-
-\ USART
-C5 constant UBRRH \ USART Baud Rate Register High Byte
-C4 constant UBRRL \ USART Baud Rate Register Low Byte
-C0 constant UCSRA \ USART Control and Status register A
-C1 constant UCSRB \ USART Control an Status register B
-C2 constant UCSRC \ USART Control an Status register C
-C6 constant UDR \ USART I/O Data Register
-
-\ WATCHDOG
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-0001 constant PSC2_CAPTAddr \ PSC2 Capture Event
-0002 constant PSC2_ECAddr \ PSC2 End Cycle
-0003 constant PSC1_CAPTAddr \ PSC1 Capture Event
-0004 constant PSC1_ECAddr \ PSC1 End Cycle
-0005 constant PSC0_CAPTAddr \ PSC0 Capture Event
-0006 constant PSC0_ECAddr \ PSC0 End Cycle
-0007 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-0008 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-0009 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-000A constant INT0Addr \ External Interrupt Request 0
-000B constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-000C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-000D constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-000E constant RESERVED15Addr \
-000F constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-0010 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-0011 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-0012 constant ADCAddr \ ADC Conversion Complete
-0013 constant INT1Addr \ External Interrupt Request 1
-0014 constant SPI_STCAddr \ SPI Serial Transfer Complete
-0015 constant USART_RXAddr \ USART, Rx Complete
-0016 constant USART_UDREAddr \ USART Data Register Empty
-0017 constant USART_TXAddr \ USART, Tx Complete
-0018 constant INT2Addr \ External Interrupt Request 2
-0019 constant WDTAddr \ Watchdog Timeout Interrupt
-001A constant EE_READYAddr \ EEPROM Ready
-001B constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-001C constant INT3Addr \ External Interrupt Request 3
-001D constant RESERVED30Addr \
-001E constant RESERVED31Addr \
-001F constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm3/device.asm b/amforth-6.5/avr8/devices/at90pwm3/device.asm
deleted file mode 100644
index 3386fce..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3/device.asm
+++ /dev/null
@@ -1,139 +0,0 @@
-; Partname: AT90PWM3
-; Built using part description XML file version 179
-; generated automatically, do not edit
-
-.nolist
- .include "pwm3def.inc"
-.list
-
-.equ ramstart = $0100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_EEPROM = 0
-.set WANT_EUSART = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC1 = 0
-.set WANT_PSC2 = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_USART = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 32
-.org $0001
- rcall isr ; PSC2 Capture Event
-.org $0002
- rcall isr ; PSC2 End Cycle
-.org $0003
- rcall isr ; PSC1 Capture Event
-.org $0004
- rcall isr ; PSC1 End Cycle
-.org $0005
- rcall isr ; PSC0 Capture Event
-.org $0006
- rcall isr ; PSC0 End Cycle
-.org $0007
- rcall isr ; Analog Comparator 0
-.org $0008
- rcall isr ; Analog Comparator 1
-.org $0009
- rcall isr ; Analog Comparator 2
-.org $000A
- rcall isr ; External Interrupt Request 0
-.org $000B
- rcall isr ; Timer/Counter1 Capture Event
-.org $000C
- rcall isr ; Timer/Counter1 Compare Match A
-.org $000D
- rcall isr ; Timer/Counter Compare Match B
-.org $000E
- rcall isr ;
-.org $000F
- rcall isr ; Timer/Counter1 Overflow
-.org $0010
- rcall isr ; Timer/Counter0 Compare Match A
-.org $0011
- rcall isr ; Timer/Counter0 Overflow
-.org $0012
- rcall isr ; ADC Conversion Complete
-.org $0013
- rcall isr ; External Interrupt Request 1
-.org $0014
- rcall isr ; SPI Serial Transfer Complete
-.org $0015
- rcall isr ; USART, Rx Complete
-.org $0016
- rcall isr ; USART Data Register Empty
-.org $0017
- rcall isr ; USART, Tx Complete
-.org $0018
- rcall isr ; External Interrupt Request 2
-.org $0019
- rcall isr ; Watchdog Timeout Interrupt
-.org $001A
- rcall isr ; EEPROM Ready
-.org $001B
- rcall isr ; Timer Counter 0 Compare Match B
-.org $001C
- rcall isr ; External Interrupt Request 3
-.org $001D
- rcall isr ;
-.org $001E
- rcall isr ;
-.org $001F
- rcall isr ; Store Program Memory Read
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 3072 ; minimum of 0xC00 (from XML) and 0xffff
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 8
- .db "AT90PWM3"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm3/device.inc b/amforth-6.5/avr8/devices/at90pwm3/device.inc
deleted file mode 100644
index 6240e36..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3/device.inc
+++ /dev/null
@@ -1,1791 +0,0 @@
-; Partname: AT90PWM3
-; Built using part description XML file version 179
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw $7B
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $7C
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw $76
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw $77
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw $7F
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw $AD
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw $AE
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw $AF
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $50
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw $3B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_DA_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw $AC
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw $AB
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw $AA
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EUSART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control and Status Register A
-VE_EUCSRA:
- .dw $ff06
- .db "EUCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRA
-XT_EUCSRA:
- .dw PFA_DOVARIABLE
-PFA_EUCSRA:
- .dw $C8
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control Register B
-VE_EUCSRB:
- .dw $ff06
- .db "EUCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRB
-XT_EUCSRB:
- .dw PFA_DOVARIABLE
-PFA_EUCSRB:
- .dw $C9
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Status Register C
-VE_EUCSRC:
- .dw $ff06
- .db "EUCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRC
-XT_EUCSRC:
- .dw PFA_DOVARIABLE
-PFA_EUCSRC:
- .dw $CA
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART I/O Data Register
-VE_EUDR:
- .dw $ff04
- .db "EUDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUDR
-XT_EUDR:
- .dw PFA_DOVARIABLE
-PFA_EUDR:
- .dw $CE
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register High Byte
-VE_MUBRRH:
- .dw $ff06
- .db "MUBRRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRH
-XT_MUBRRH:
- .dw PFA_DOVARIABLE
-PFA_MUBRRH:
- .dw $CD
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register Low Byte
-VE_MUBRRL:
- .dw $ff06
- .db "MUBRRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRL
-XT_MUBRRL:
- .dw PFA_DOVARIABLE
-PFA_MUBRRL:
- .dw $CC
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $27
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_PSC0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register High
-VE_OCR0RAH:
- .dw $ff07
- .db "OCR0RAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RAH
-XT_OCR0RAH:
- .dw PFA_DOVARIABLE
-PFA_OCR0RAH:
- .dw $D5
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register Low
-VE_OCR0RAL:
- .dw $ff07
- .db "OCR0RAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RAL
-XT_OCR0RAL:
- .dw PFA_DOVARIABLE
-PFA_OCR0RAL:
- .dw $D4
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register High
-VE_OCR0RBH:
- .dw $ff07
- .db "OCR0RBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RBH
-XT_OCR0RBH:
- .dw PFA_DOVARIABLE
-PFA_OCR0RBH:
- .dw $D9
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register Low
-VE_OCR0RBL:
- .dw $ff07
- .db "OCR0RBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RBL
-XT_OCR0RBL:
- .dw PFA_DOVARIABLE
-PFA_OCR0RBL:
- .dw $D8
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register High
-VE_OCR0SAH:
- .dw $ff07
- .db "OCR0SAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SAH
-XT_OCR0SAH:
- .dw PFA_DOVARIABLE
-PFA_OCR0SAH:
- .dw $D3
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register Low
-VE_OCR0SAL:
- .dw $ff07
- .db "OCR0SAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SAL
-XT_OCR0SAL:
- .dw PFA_DOVARIABLE
-PFA_OCR0SAL:
- .dw $D2
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register High
-VE_OCR0SBH:
- .dw $ff07
- .db "OCR0SBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SBH
-XT_OCR0SBH:
- .dw PFA_DOVARIABLE
-PFA_OCR0SBH:
- .dw $D7
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register Low
-VE_OCR0SBL:
- .dw $ff07
- .db "OCR0SBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SBL
-XT_OCR0SBL:
- .dw PFA_DOVARIABLE
-PFA_OCR0SBL:
- .dw $D6
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw $DA
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw $DB
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw $DC
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw $DD
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register High
-VE_PICR0H:
- .dw $ff06
- .db "PICR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0H
-XT_PICR0H:
- .dw PFA_DOVARIABLE
-PFA_PICR0H:
- .dw $DF
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register Low
-VE_PICR0L:
- .dw $ff06
- .db "PICR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0L
-XT_PICR0L:
- .dw PFA_DOVARIABLE
-PFA_PICR0L:
- .dw $DE
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw $A0
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw $A1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw $D0
-
-.endif
-
-; ********
-.if WANT_PSC1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register High
-VE_OCR1RAH:
- .dw $ff07
- .db "OCR1RAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RAH
-XT_OCR1RAH:
- .dw PFA_DOVARIABLE
-PFA_OCR1RAH:
- .dw $E5
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register Low
-VE_OCR1RAL:
- .dw $ff07
- .db "OCR1RAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RAL
-XT_OCR1RAL:
- .dw PFA_DOVARIABLE
-PFA_OCR1RAL:
- .dw $E4
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register High
-VE_OCR1RBH:
- .dw $ff07
- .db "OCR1RBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RBH
-XT_OCR1RBH:
- .dw PFA_DOVARIABLE
-PFA_OCR1RBH:
- .dw $E9
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register Low
-VE_OCR1RBL:
- .dw $ff07
- .db "OCR1RBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RBL
-XT_OCR1RBL:
- .dw PFA_DOVARIABLE
-PFA_OCR1RBL:
- .dw $E8
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register High
-VE_OCR1SAH:
- .dw $ff07
- .db "OCR1SAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SAH
-XT_OCR1SAH:
- .dw PFA_DOVARIABLE
-PFA_OCR1SAH:
- .dw $E3
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register Low
-VE_OCR1SAL:
- .dw $ff07
- .db "OCR1SAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SAL
-XT_OCR1SAL:
- .dw PFA_DOVARIABLE
-PFA_OCR1SAL:
- .dw $E2
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register High
-VE_OCR1SBH:
- .dw $ff07
- .db "OCR1SBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SBH
-XT_OCR1SBH:
- .dw PFA_DOVARIABLE
-PFA_OCR1SBH:
- .dw $E7
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register Low
-VE_OCR1SBL:
- .dw $ff07
- .db "OCR1SBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SBL
-XT_OCR1SBL:
- .dw PFA_DOVARIABLE
-PFA_OCR1SBL:
- .dw $E6
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Configuration Register
-VE_PCNF1:
- .dw $ff05
- .db "PCNF1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF1
-XT_PCNF1:
- .dw PFA_DOVARIABLE
-PFA_PCNF1:
- .dw $EA
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Control Register
-VE_PCTL1:
- .dw $ff05
- .db "PCTL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL1
-XT_PCTL1:
- .dw PFA_DOVARIABLE
-PFA_PCTL1:
- .dw $EB
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1A:
- .dw $ff06
- .db "PFRC1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1A
-XT_PFRC1A:
- .dw PFA_DOVARIABLE
-PFA_PFRC1A:
- .dw $EC
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1B:
- .dw $ff06
- .db "PFRC1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1B
-XT_PFRC1B:
- .dw PFA_DOVARIABLE
-PFA_PFRC1B:
- .dw $ED
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input Capture Register High
-VE_PICR1H:
- .dw $ff06
- .db "PICR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR1H
-XT_PICR1H:
- .dw PFA_DOVARIABLE
-PFA_PICR1H:
- .dw $EF
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input Capture Register Low
-VE_PICR1L:
- .dw $ff06
- .db "PICR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR1L
-XT_PICR1L:
- .dw PFA_DOVARIABLE
-PFA_PICR1L:
- .dw $EE
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Interrupt Flag Register
-VE_PIFR1:
- .dw $ff05
- .db "PIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR1
-XT_PIFR1:
- .dw PFA_DOVARIABLE
-PFA_PIFR1:
- .dw $A2
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Interrupt Mask Register
-VE_PIM1:
- .dw $ff04
- .db "PIM1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM1
-XT_PIM1:
- .dw PFA_DOVARIABLE
-PFA_PIM1:
- .dw $A3
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Synchro and Output Configuration
-VE_PSOC1:
- .dw $ff05
- .db "PSOC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC1
-XT_PSOC1:
- .dw PFA_DOVARIABLE
-PFA_PSOC1:
- .dw $E0
-
-.endif
-
-; ********
-.if WANT_PSC2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register High
-VE_OCR2RAH:
- .dw $ff07
- .db "OCR2RAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RAH
-XT_OCR2RAH:
- .dw PFA_DOVARIABLE
-PFA_OCR2RAH:
- .dw $F5
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register Low
-VE_OCR2RAL:
- .dw $ff07
- .db "OCR2RAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RAL
-XT_OCR2RAL:
- .dw PFA_DOVARIABLE
-PFA_OCR2RAL:
- .dw $F4
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register High
-VE_OCR2RBH:
- .dw $ff07
- .db "OCR2RBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RBH
-XT_OCR2RBH:
- .dw PFA_DOVARIABLE
-PFA_OCR2RBH:
- .dw $F9
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register Low
-VE_OCR2RBL:
- .dw $ff07
- .db "OCR2RBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RBL
-XT_OCR2RBL:
- .dw PFA_DOVARIABLE
-PFA_OCR2RBL:
- .dw $F8
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register High
-VE_OCR2SAH:
- .dw $ff07
- .db "OCR2SAH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SAH
-XT_OCR2SAH:
- .dw PFA_DOVARIABLE
-PFA_OCR2SAH:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register Low
-VE_OCR2SAL:
- .dw $ff07
- .db "OCR2SAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SAL
-XT_OCR2SAL:
- .dw PFA_DOVARIABLE
-PFA_OCR2SAL:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register High
-VE_OCR2SBH:
- .dw $ff07
- .db "OCR2SBH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SBH
-XT_OCR2SBH:
- .dw PFA_DOVARIABLE
-PFA_OCR2SBH:
- .dw $F7
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register Low
-VE_OCR2SBL:
- .dw $ff07
- .db "OCR2SBL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SBL
-XT_OCR2SBL:
- .dw PFA_DOVARIABLE
-PFA_OCR2SBL:
- .dw $F6
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw $FA
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw $FB
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw $FC
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw $FD
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register High
-VE_PICR2H:
- .dw $ff06
- .db "PICR2H"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2H
-XT_PICR2H:
- .dw PFA_DOVARIABLE
-PFA_PICR2H:
- .dw $FF
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register Low
-VE_PICR2L:
- .dw $ff06
- .db "PICR2L"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2L
-XT_PICR2L:
- .dw PFA_DOVARIABLE
-PFA_PICR2L:
- .dw $FE
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw $A4
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw $A5
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw $F1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw $F0
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4C
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4D
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $86
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $8B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $8A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw $82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_USART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw $C5
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw $C4
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw $C0
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw $C1
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw $C2
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw $C6
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm3/device.py b/amforth-6.5/avr8/devices/at90pwm3/device.py
deleted file mode 100644
index c300eee..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3/device.py
+++ /dev/null
@@ -1,175 +0,0 @@
-# Partname: AT90PWM3
-# Built using part description XML file version 179
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$79',
- 'ADCL': '$78',
- 'ADCSRA': '$7A',
- 'ADCSRB': '$7B',
- 'ADMUX': '$7C',
- 'AMP0CSR': '$76',
- 'AMP1CSR': '$77',
- 'DIDR0': '$7E',
- 'DIDR1': '$7F',
- 'AC0CON': '$AD',
- 'AC1CON': '$AE',
- 'AC2CON': '$AF',
- 'ACSR': '$50',
- 'SPMCSR': '$57',
- 'CLKPR': '$61',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$39',
- 'GPIOR2': '$3A',
- 'GPIOR3': '$3B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSCCAL': '$66',
- 'PLLCSR': '$49',
- 'PRR': '$64',
- 'SMCR': '$53',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'DACH': '$AC',
- 'DACL': '$AB',
- 'DACON': '$AA',
- 'EEARH': '$42',
- 'EEARL': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EUCSRA': '$C8',
- 'EUCSRB': '$C9',
- 'EUCSRC': '$CA',
- 'EUDR': '$CE',
- 'MUBRRH': '$CD',
- 'MUBRRL': '$CC',
- 'EICRA': '$69',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'DDRB': '$24',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'DDRC': '$27',
- 'PINC': '$26',
- 'PORTC': '$28',
- 'DDRD': '$2A',
- 'PIND': '$29',
- 'PORTD': '$2B',
- 'DDRE': '$2D',
- 'PINE': '$2C',
- 'PORTE': '$2E',
- 'OCR0RAH': '$D5',
- 'OCR0RAL': '$D4',
- 'OCR0RBH': '$D9',
- 'OCR0RBL': '$D8',
- 'OCR0SAH': '$D3',
- 'OCR0SAL': '$D2',
- 'OCR0SBH': '$D7',
- 'OCR0SBL': '$D6',
- 'PCNF0': '$DA',
- 'PCTL0': '$DB',
- 'PFRC0A': '$DC',
- 'PFRC0B': '$DD',
- 'PICR0H': '$DF',
- 'PICR0L': '$DE',
- 'PIFR0': '$A0',
- 'PIM0': '$A1',
- 'PSOC0': '$D0',
- 'OCR1RAH': '$E5',
- 'OCR1RAL': '$E4',
- 'OCR1RBH': '$E9',
- 'OCR1RBL': '$E8',
- 'OCR1SAH': '$E3',
- 'OCR1SAL': '$E2',
- 'OCR1SBH': '$E7',
- 'OCR1SBL': '$E6',
- 'PCNF1': '$EA',
- 'PCTL1': '$EB',
- 'PFRC1A': '$EC',
- 'PFRC1B': '$ED',
- 'PICR1H': '$EF',
- 'PICR1L': '$EE',
- 'PIFR1': '$A2',
- 'PIM1': '$A3',
- 'PSOC1': '$E0',
- 'OCR2RAH': '$F5',
- 'OCR2RAL': '$F4',
- 'OCR2RBH': '$F9',
- 'OCR2RBL': '$F8',
- 'OCR2SAH': '$F3',
- 'OCR2SAL': '$F2',
- 'OCR2SBH': '$F7',
- 'OCR2SBL': '$F6',
- 'PCNF2': '$FA',
- 'PCTL2': '$FB',
- 'PFRC2A': '$FC',
- 'PFRC2B': '$FD',
- 'PICR2H': '$FF',
- 'PICR2L': '$FE',
- 'PIFR2': '$A4',
- 'PIM2': '$A5',
- 'POM2': '$F1',
- 'PSOC2': '$F0',
- 'SPCR': '$4C',
- 'SPDR': '$4E',
- 'SPSR': '$4D',
- 'GTCCR': '$43',
- 'OCR0A': '$47',
- 'OCR0B': '$48',
- 'TCCR0A': '$44',
- 'TCCR0B': '$45',
- 'TCNT0': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'ICR1H': '$87',
- 'ICR1L': '$86',
- 'OCR1AH': '$89',
- 'OCR1AL': '$88',
- 'OCR1BH': '$8B',
- 'OCR1BL': '$8A',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCCR1C': '$82',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'UBRRH': '$C5',
- 'UBRRL': '$C4',
- 'UCSRA': '$C0',
- 'UCSRB': '$C1',
- 'UCSRC': '$C2',
- 'UDR': '$C6',
- 'WDTCSR': '$60',
- 'PSC2_CAPTAddr': '$0001',
- 'PSC2_ECAddr': '$0002',
- 'PSC1_CAPTAddr': '$0003',
- 'PSC1_ECAddr': '$0004',
- 'PSC0_CAPTAddr': '$0005',
- 'PSC0_ECAddr': '$0006',
- 'ANALOG_COMP_0Addr': '$0007',
- 'ANALOG_COMP_1Addr': '$0008',
- 'ANALOG_COMP_2Addr': '$0009',
- 'INT0Addr': '$000A',
- 'TIMER1_CAPTAddr': '$000B',
- 'TIMER1_COMPAAddr': '$000C',
- 'TIMER1_COMPBAddr': '$000D',
- 'RESERVED15Addr': '$000E',
- 'TIMER1_OVFAddr': '$000F',
- 'TIMER0_COMP_AAddr': '$0010',
- 'TIMER0_OVFAddr': '$0011',
- 'ADCAddr': '$0012',
- 'INT1Addr': '$0013',
- 'SPI_STCAddr': '$0014',
- 'USART_RXAddr': '$0015',
- 'USART_UDREAddr': '$0016',
- 'USART_TXAddr': '$0017',
- 'INT2Addr': '$0018',
- 'WDTAddr': '$0019',
- 'EE_READYAddr': '$001A',
- 'TIMER0_COMPBAddr': '$001B',
- 'INT3Addr': '$001C',
- 'RESERVED30Addr': '$001D',
- 'RESERVED31Addr': '$001E',
- 'SPM_READYAddr': '$001F'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt b/amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt
deleted file mode 100644
index b31592b..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt
+++ /dev/null
@@ -1,478 +0,0 @@
-\ Partname: AT90PWM316
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EUSART
-&206 constant EUDR \ EUSART I/O Data Register
-&200 constant EUCSRA \ EUSART Control and Status Register A
- $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
- $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
-&201 constant EUCSRB \ EUSART Control Register B
- $10 constant EUCSRB_EUSART \ EUSART Enable Bit
- $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
- $02 constant EUCSRB_EMCH \ Manchester Mode Bit
- $01 constant EUCSRB_BODR \ Order Bit
-&202 constant EUCSRC \ EUSART Status Register C
- $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
- $04 constant EUCSRC_F1617 \ F1617 Bit
- $03 constant EUCSRC_STP \ Stop Bits
-&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
- $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
-&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
- $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
-\ ANALOG_COMPARATOR
-&173 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&174 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&175 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&172 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&171 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&170 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&59 constant GPIOR3 \ General Purpose IO Register 3
- $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $E0 constant PRR_PRPSC \ Power Reduction PSC2
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
-&126 constant DIDR0 \ Digital Input Disable Register 0
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $20 constant DIDR1_ACMP0D \
- $10 constant DIDR1_AMP0PD \
- $08 constant DIDR1_AMP0ND \
- $04 constant DIDR1_ADC10D \
- $02 constant DIDR1_ADC9D \
- $01 constant DIDR1_ADC8D \
-&118 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $03 constant AMP0CSR_AMP0TS \
-&119 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $03 constant AMP1CSR_AMP1TS \
-\ USART
-&198 constant UDR \ USART I/O Data Register
-&192 constant UCSRA \ USART Control and Status register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data Overrun
- $04 constant UCSRA_UPE \ USART Parity Error
- $02 constant UCSRA_U2X \ Double USART Transmission Bit
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&193 constant UCSRB \ USART Control an Status register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&194 constant UCSRC \ USART Control an Status register C
- $40 constant UCSRC_UMSEL0 \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size Bits
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&197 constant UBRRH \ USART Baud Rate Register High Byte
- $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
-&196 constant UBRRL \ USART Baud Rate Register Low Byte
- $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC0
-&222 constant PICR0 \ PSC 0 Input Capture Register
-&221 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
- $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
-&220 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
- $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
-&219 constant PCTL0 \ PSC 0 Control Register
- $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
- $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
- $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
- $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- $01 constant PCTL0_PRUN0 \ PSC 0 Run
-&218 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
- $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
-&216 constant OCR0RB \ Output Compare RB Register
-&214 constant OCR0SB \ Output Compare SB Register
-&212 constant OCR0RA \ Output Compare RA Register
-&210 constant OCR0SA \ Output Compare SA Register
-&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
- $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
- $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
-&161 constant PIM0 \ PSC0 Interrupt Mask Register
- $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
- $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
- $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
-&160 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- $08 constant PIFR0_PEV0A \ External Event A Interrupt
- $06 constant PIFR0_PRN0 \ Ramp Number
- $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
-\ PSC1
-&238 constant PICR1 \ PSC 1 Input Capture Register
-&237 constant PFRC1B \ PSC 1 Input B Control
- $80 constant PFRC1B_PCAE1B \ PSC 1 Capture Enable Input Part B
- $40 constant PFRC1B_PISEL1B \ PSC 1 Input Select for Part B
- $20 constant PFRC1B_PELEV1B \ PSC 1 Edge Level Selector on Input Part B
- $10 constant PFRC1B_PFLTE1B \ PSC 1 Filter Enable on Input Part B
- $0F constant PFRC1B_PRFM1B \ PSC 1 Retrigger and Fault Mode for Part B
-&236 constant PFRC1A \ PSC 1 Input B Control
- $80 constant PFRC1A_PCAE1A \ PSC 1 Capture Enable Input Part A
- $40 constant PFRC1A_PISEL1A \ PSC 1 Input Select for Part A
- $20 constant PFRC1A_PELEV1A \ PSC 1 Edge Level Selector on Input Part A
- $10 constant PFRC1A_PFLTE1A \ PSC 1 Filter Enable on Input Part A
- $0F constant PFRC1A_PRFM1A \ PSC 1 Retrigger and Fault Mode for Part A
-&235 constant PCTL1 \ PSC 1 Control Register
- $C0 constant PCTL1_PPRE1 \ PSC 1 Prescaler Selects
- $20 constant PCTL1_PBFM1 \ Balance Flank Width Modulation
- $10 constant PCTL1_PAOC1B \ PSC 1 Asynchronous Output Control B
- $08 constant PCTL1_PAOC1A \ PSC 1 Asynchronous Output Control A
- $04 constant PCTL1_PARUN1 \ PSC1 Auto Run
- $02 constant PCTL1_PCCYC1 \ PSC1 Complete Cycle
- $01 constant PCTL1_PRUN1 \ PSC 1 Run
-&234 constant PCNF1 \ PSC 1 Configuration Register
- $80 constant PCNF1_PFIFTY1 \ PSC 1 Fifty
- $40 constant PCNF1_PALOCK1 \ PSC 1 Autolock
- $20 constant PCNF1_PLOCK1 \ PSC 1 Lock
- $18 constant PCNF1_PMODE1 \ PSC 1 Mode
- $04 constant PCNF1_POP1 \ PSC 1 Output Polarity
- $02 constant PCNF1_PCLKSEL1 \ PSC 1 Input Clock Select
-&232 constant OCR1RB \ Output Compare RB Register
-&230 constant OCR1SB \ Output Compare SB Register
-&228 constant OCR1RA \ Output Compare RA Register
-&226 constant OCR1SA \ Output Compare SA Register
-&224 constant PSOC1 \ PSC1 Synchro and Output Configuration
- $30 constant PSOC1_PSYNC1_ \ Synchronization Out for ADC Selection
- $04 constant PSOC1_POEN1B \ PSCOUT11 Output Enable
- $01 constant PSOC1_POEN1A \ PSCOUT10 Output Enable
-&163 constant PIM1 \ PSC1 Interrupt Mask Register
- $20 constant PIM1_PSEIE1 \ PSC 1 Synchro Error Interrupt Enable
- $10 constant PIM1_PEVE1B \ External Event B Interrupt Enable
- $08 constant PIM1_PEVE1A \ External Event A Interrupt Enable
- $01 constant PIM1_PEOPE1 \ End of Cycle Interrupt Enable
-&162 constant PIFR1 \ PSC1 Interrupt Flag Register
- $80 constant PIFR1_POAC1B \ PSC 1 Output B Activity
- $40 constant PIFR1_POAC1A \ PSC 1 Output A Activity
- $20 constant PIFR1_PSEI1 \ PSC 1 Synchro Error Interrupt
- $10 constant PIFR1_PEV1B \ External Event B Interrupt
- $08 constant PIFR1_PEV1A \ External Event A Interrupt
- $06 constant PIFR1_PRN1 \ Ramp Number
- $01 constant PIFR1_PEOP1 \ End of PSC1 Interrupt
-\ PSC2
-&254 constant PICR2 \ PSC 2 Input Capture Register
-&253 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
- $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
-&252 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
- $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
-&251 constant PCTL2 \ PSC 2 Control Register
- $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
- $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
- $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
- $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- $01 constant PCTL2_PRUN2 \ PSC 2 Run
-&250 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
- $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
-&248 constant OCR2RB \ Output Compare RB Register
-&246 constant OCR2SB \ Output Compare SB Register
-&244 constant OCR2RA \ Output Compare RA Register
-&242 constant OCR2SA \ Output Compare SA Register
-&241 constant POM2 \ PSC 2 Output Matrix
- $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
-&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
- $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
- $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
-&165 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
- $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
- $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
-&164 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- $08 constant PIFR2_PEV2A \ External Event A Interrupt
- $06 constant PIFR2_PRN2 \ Ramp Number
- $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
-
-\ Interrupts
-&2 constant PSC2_CAPTAddr \ PSC2 Capture Event
-&4 constant PSC2_ECAddr \ PSC2 End Cycle
-&6 constant PSC1_CAPTAddr \ PSC1 Capture Event
-&8 constant PSC1_ECAddr \ PSC1 End Cycle
-&10 constant PSC0_CAPTAddr \ PSC0 Capture Event
-&12 constant PSC0_ECAddr \ PSC0 End Cycle
-&14 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-&16 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-&18 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-&20 constant INT0Addr \ External Interrupt Request 0
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant RESERVED15Addr \
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant ADCAddr \ ADC Conversion Complete
-&38 constant INT1Addr \ External Interrupt Request 1
-&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&42 constant USART__RXAddr \ USART, Rx Complete
-&44 constant USART__UDREAddr \ USART Data Register Empty
-&46 constant USART__TXAddr \ USART, Tx Complete
-&48 constant INT2Addr \ External Interrupt Request 2
-&50 constant WDTAddr \ Watchdog Timeout Interrupt
-&52 constant EE_READYAddr \ EEPROM Ready
-&54 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-&56 constant INT3Addr \ External Interrupt Request 3
-&58 constant RESERVED30Addr \
-&60 constant RESERVED31Addr \
-&62 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm316/device.asm b/amforth-6.5/avr8/devices/at90pwm316/device.asm
deleted file mode 100644
index c36c5ad..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/device.asm
+++ /dev/null
@@ -1,125 +0,0 @@
-; Partname: AT90PWM316
-; generated automatically, do not edit
-
-.nolist
- .include "pwm316def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EUSART = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_USART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC1 = 0
-.set WANT_PSC2 = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; PSC2 Capture Event
-.org 4
- rcall isr ; PSC2 End Cycle
-.org 6
- rcall isr ; PSC1 Capture Event
-.org 8
- rcall isr ; PSC1 End Cycle
-.org 10
- rcall isr ; PSC0 Capture Event
-.org 12
- rcall isr ; PSC0 End Cycle
-.org 14
- rcall isr ; Analog Comparator 0
-.org 16
- rcall isr ; Analog Comparator 1
-.org 18
- rcall isr ; Analog Comparator 2
-.org 20
- rcall isr ; External Interrupt Request 0
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ;
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; ADC Conversion Complete
-.org 38
- rcall isr ; External Interrupt Request 1
-.org 40
- rcall isr ; SPI Serial Transfer Complete
-.org 42
- rcall isr ; USART, Rx Complete
-.org 44
- rcall isr ; USART Data Register Empty
-.org 46
- rcall isr ; USART, Tx Complete
-.org 48
- rcall isr ; External Interrupt Request 2
-.org 50
- rcall isr ; Watchdog Timeout Interrupt
-.org 52
- rcall isr ; EEPROM Ready
-.org 54
- rcall isr ; Timer Counter 0 Compare Match B
-.org 56
- rcall isr ; External Interrupt Request 3
-.org 58
- rcall isr ;
-.org 60
- rcall isr ;
-.org 62
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 32
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 10
- .db "AT90PWM316"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm316/device.inc b/amforth-6.5/avr8/devices/at90pwm316/device.inc
deleted file mode 100644
index b85c36d..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/device.inc
+++ /dev/null
@@ -1,1467 +0,0 @@
-; Partname: AT90PWM316
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EUSART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART I/O Data Register
-VE_EUDR:
- .dw $ff04
- .db "EUDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUDR
-XT_EUDR:
- .dw PFA_DOVARIABLE
-PFA_EUDR:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control and Status Register A
-VE_EUCSRA:
- .dw $ff06
- .db "EUCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRA
-XT_EUCSRA:
- .dw PFA_DOVARIABLE
-PFA_EUCSRA:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control Register B
-VE_EUCSRB:
- .dw $ff06
- .db "EUCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRB
-XT_EUCSRB:
- .dw PFA_DOVARIABLE
-PFA_EUCSRB:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Status Register C
-VE_EUCSRC:
- .dw $ff06
- .db "EUCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRC
-XT_EUCSRC:
- .dw PFA_DOVARIABLE
-PFA_EUCSRC:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register High Byte
-VE_MUBRRH:
- .dw $ff06
- .db "MUBRRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRH
-XT_MUBRRH:
- .dw PFA_DOVARIABLE
-PFA_MUBRRH:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register Low Byte
-VE_MUBRRL:
- .dw $ff06
- .db "MUBRRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRL
-XT_MUBRRL:
- .dw PFA_DOVARIABLE
-PFA_MUBRRL:
- .dw 204
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 170
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 119
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 197
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 196
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register
-VE_PICR0:
- .dw $ff05
- .db "PICR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0
-XT_PICR0:
- .dw PFA_DOVARIABLE
-PFA_PICR0:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR0RB:
- .dw $ff06
- .db "OCR0RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RB
-XT_OCR0RB:
- .dw PFA_DOVARIABLE
-PFA_OCR0RB:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR0SB:
- .dw $ff06
- .db "OCR0SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SB
-XT_OCR0SB:
- .dw PFA_DOVARIABLE
-PFA_OCR0SB:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR0RA:
- .dw $ff06
- .db "OCR0RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RA
-XT_OCR0RA:
- .dw PFA_DOVARIABLE
-PFA_OCR0RA:
- .dw 212
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR0SA:
- .dw $ff06
- .db "OCR0SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SA
-XT_OCR0SA:
- .dw PFA_DOVARIABLE
-PFA_OCR0SA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw 160
-
-.endif
-.if WANT_PSC1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input Capture Register
-VE_PICR1:
- .dw $ff05
- .db "PICR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR1
-XT_PICR1:
- .dw PFA_DOVARIABLE
-PFA_PICR1:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1B:
- .dw $ff06
- .db "PFRC1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1B
-XT_PFRC1B:
- .dw PFA_DOVARIABLE
-PFA_PFRC1B:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1A:
- .dw $ff06
- .db "PFRC1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1A
-XT_PFRC1A:
- .dw PFA_DOVARIABLE
-PFA_PFRC1A:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Control Register
-VE_PCTL1:
- .dw $ff05
- .db "PCTL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL1
-XT_PCTL1:
- .dw PFA_DOVARIABLE
-PFA_PCTL1:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Configuration Register
-VE_PCNF1:
- .dw $ff05
- .db "PCNF1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF1
-XT_PCNF1:
- .dw PFA_DOVARIABLE
-PFA_PCNF1:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR1RB:
- .dw $ff06
- .db "OCR1RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RB
-XT_OCR1RB:
- .dw PFA_DOVARIABLE
-PFA_OCR1RB:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR1SB:
- .dw $ff06
- .db "OCR1SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SB
-XT_OCR1SB:
- .dw PFA_DOVARIABLE
-PFA_OCR1SB:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR1RA:
- .dw $ff06
- .db "OCR1RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RA
-XT_OCR1RA:
- .dw PFA_DOVARIABLE
-PFA_OCR1RA:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR1SA:
- .dw $ff06
- .db "OCR1SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SA
-XT_OCR1SA:
- .dw PFA_DOVARIABLE
-PFA_OCR1SA:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Synchro and Output Configuration
-VE_PSOC1:
- .dw $ff05
- .db "PSOC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC1
-XT_PSOC1:
- .dw PFA_DOVARIABLE
-PFA_PSOC1:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Interrupt Mask Register
-VE_PIM1:
- .dw $ff04
- .db "PIM1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM1
-XT_PIM1:
- .dw PFA_DOVARIABLE
-PFA_PIM1:
- .dw 163
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Interrupt Flag Register
-VE_PIFR1:
- .dw $ff05
- .db "PIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR1
-XT_PIFR1:
- .dw PFA_DOVARIABLE
-PFA_PIFR1:
- .dw 162
-
-.endif
-.if WANT_PSC2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register
-VE_PICR2:
- .dw $ff05
- .db "PICR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2
-XT_PICR2:
- .dw PFA_DOVARIABLE
-PFA_PICR2:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR2RB:
- .dw $ff06
- .db "OCR2RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RB
-XT_OCR2RB:
- .dw PFA_DOVARIABLE
-PFA_OCR2RB:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR2SB:
- .dw $ff06
- .db "OCR2SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SB
-XT_OCR2SB:
- .dw PFA_DOVARIABLE
-PFA_OCR2SB:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR2RA:
- .dw $ff06
- .db "OCR2RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RA
-XT_OCR2RA:
- .dw PFA_DOVARIABLE
-PFA_OCR2RA:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR2SA:
- .dw $ff06
- .db "OCR2SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SA
-XT_OCR2SA:
- .dw PFA_DOVARIABLE
-PFA_OCR2SA:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw 164
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm316/device.py b/amforth-6.5/avr8/devices/at90pwm316/device.py
deleted file mode 100644
index 233602f..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/device.py
+++ /dev/null
@@ -1,505 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM316
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
- 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
- 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
- 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
- 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'RESERVED15Addr' : '#28', #
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'ADCAddr' : '#36', # ADC Conversion Complete
- 'INT1Addr' : '#38', # External Interrupt Request 1
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#42', # USART, Rx Complete
- 'USART_UDREAddr' : '#44', # USART Data Register Empty
- 'USART_TXAddr' : '#46', # USART, Tx Complete
- 'INT2Addr' : '#48', # External Interrupt Request 2
- 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
- 'INT3Addr' : '#56', # External Interrupt Request 3
- 'RESERVED30Addr' : '#58', #
- 'RESERVED31Addr' : '#60', #
- 'SPM_READYAddr' : '#62', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EUSART
- 'EUDR' : '$ce', # EUSART I/O Data Register
- 'EUCSRA' : '$c8', # EUSART Control and Status Regi
- 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
- 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
- 'EUCSRB' : '$c9', # EUSART Control Register B
- 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
- 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
- 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
- 'EUCSRB_BODR': '$1', # Order Bit
- 'EUCSRC' : '$ca', # EUSART Status Register C
- 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
- 'EUCSRC_F1617': '$4', # F1617 Bit
- 'EUCSRC_STP': '$3', # Stop Bits
- 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
- 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
- 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
- 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$af', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$ac', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$ab', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$aa', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR3' : '$3b', # General Purpose IO Register 3
- 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRPSC': '$e0', # Power Reduction PSC2
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_ACMP0D': '$20', #
- 'DIDR1_AMP0PD': '$10', #
- 'DIDR1_AMP0ND': '$8', #
- 'DIDR1_ADC10D': '$4', #
- 'DIDR1_ADC9D': '$2', #
- 'DIDR1_ADC8D': '$1', #
- 'AMP0CSR' : '$76', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0TS': '$3', #
- 'AMP1CSR' : '$77', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMP1TS': '$3', #
-
-# Module USART
- 'UDR' : '$c6', # USART I/O Data Register
- 'UCSRA' : '$c0', # USART Control and Status regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data Overrun
- 'UCSRA_UPE': '$4', # USART Parity Error
- 'UCSRA_U2X': '$2', # Double USART Transmission Bit
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$c1', # USART Control an Status regist
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$c2', # USART Control an Status regist
- 'UCSRC_UMSEL0': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size Bits
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$c5', # USART Baud Rate Register High
- 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
- 'UBRRL' : '$c4', # USART Baud Rate Register Low B
- 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC0
- 'PICR0' : '$de', # PSC 0 Input Capture Register
- 'PFRC0B' : '$dd', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$dc', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$db', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$da', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$d8', # Output Compare RB Register
- 'OCR0SB' : '$d6', # Output Compare SB Register
- 'OCR0RA' : '$d4', # Output Compare RA Register
- 'OCR0SA' : '$d2', # Output Compare SA Register
- 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
- 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
- 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
- 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
- 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
- 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC1
- 'PICR1' : '$ee', # PSC 1 Input Capture Register
- 'PFRC1B' : '$ed', # PSC 1 Input B Control
- 'PFRC1B_PCAE1B': '$80', # PSC 1 Capture Enable Input Par
- 'PFRC1B_PISEL1B': '$40', # PSC 1 Input Select for Part B
- 'PFRC1B_PELEV1B': '$20', # PSC 1 Edge Level Selector on I
- 'PFRC1B_PFLTE1B': '$10', # PSC 1 Filter Enable on Input P
- 'PFRC1B_PRFM1B': '$f', # PSC 1 Retrigger and Fault Mode
- 'PFRC1A' : '$ec', # PSC 1 Input B Control
- 'PFRC1A_PCAE1A': '$80', # PSC 1 Capture Enable Input Par
- 'PFRC1A_PISEL1A': '$40', # PSC 1 Input Select for Part A
- 'PFRC1A_PELEV1A': '$20', # PSC 1 Edge Level Selector on I
- 'PFRC1A_PFLTE1A': '$10', # PSC 1 Filter Enable on Input P
- 'PFRC1A_PRFM1A': '$f', # PSC 1 Retrigger and Fault Mode
- 'PCTL1' : '$eb', # PSC 1 Control Register
- 'PCTL1_PPRE1': '$c0', # PSC 1 Prescaler Selects
- 'PCTL1_PBFM1': '$20', # Balance Flank Width Modulation
- 'PCTL1_PAOC1B': '$10', # PSC 1 Asynchronous Output Cont
- 'PCTL1_PAOC1A': '$8', # PSC 1 Asynchronous Output Cont
- 'PCTL1_PARUN1': '$4', # PSC1 Auto Run
- 'PCTL1_PCCYC1': '$2', # PSC1 Complete Cycle
- 'PCTL1_PRUN1': '$1', # PSC 1 Run
- 'PCNF1' : '$ea', # PSC 1 Configuration Register
- 'PCNF1_PFIFTY1': '$80', # PSC 1 Fifty
- 'PCNF1_PALOCK1': '$40', # PSC 1 Autolock
- 'PCNF1_PLOCK1': '$20', # PSC 1 Lock
- 'PCNF1_PMODE1': '$18', # PSC 1 Mode
- 'PCNF1_POP1': '$4', # PSC 1 Output Polarity
- 'PCNF1_PCLKSEL1': '$2', # PSC 1 Input Clock Select
- 'OCR1RB' : '$e8', # Output Compare RB Register
- 'OCR1SB' : '$e6', # Output Compare SB Register
- 'OCR1RA' : '$e4', # Output Compare RA Register
- 'OCR1SA' : '$e2', # Output Compare SA Register
- 'PSOC1' : '$e0', # PSC1 Synchro and Output Config
- 'PSOC1_PSYNC1_': '$30', # Synchronization Out for ADC Se
- 'PSOC1_POEN1B': '$4', # PSCOUT11 Output Enable
- 'PSOC1_POEN1A': '$1', # PSCOUT10 Output Enable
- 'PIM1' : '$a3', # PSC1 Interrupt Mask Register
- 'PIM1_PSEIE1': '$20', # PSC 1 Synchro Error Interrupt
- 'PIM1_PEVE1B': '$10', # External Event B Interrupt Ena
- 'PIM1_PEVE1A': '$8', # External Event A Interrupt Ena
- 'PIM1_PEOPE1': '$1', # End of Cycle Interrupt Enable
- 'PIFR1' : '$a2', # PSC1 Interrupt Flag Register
- 'PIFR1_POAC1B': '$80', # PSC 1 Output B Activity
- 'PIFR1_POAC1A': '$40', # PSC 1 Output A Activity
- 'PIFR1_PSEI1': '$20', # PSC 1 Synchro Error Interrupt
- 'PIFR1_PEV1B': '$10', # External Event B Interrupt
- 'PIFR1_PEV1A': '$8', # External Event A Interrupt
- 'PIFR1_PRN1': '$6', # Ramp Number
- 'PIFR1_PEOP1': '$1', # End of PSC1 Interrupt
-
-# Module PSC2
- 'PICR2' : '$fe', # PSC 2 Input Capture Register
- 'PFRC2B' : '$fd', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$fc', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$fb', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$fa', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'OCR2RB' : '$f8', # Output Compare RB Register
- 'OCR2SB' : '$f6', # Output Compare SB Register
- 'OCR2RA' : '$f4', # Output Compare RA Register
- 'OCR2SA' : '$f2', # Output Compare SA Register
- 'POM2' : '$f1', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
- 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
- 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt b/amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt
deleted file mode 100644
index 94c96ac..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt
+++ /dev/null
@@ -1,478 +0,0 @@
-\ Partname: AT90PWM3B
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EUSART
-&206 constant EUDR \ EUSART I/O Data Register
-&200 constant EUCSRA \ EUSART Control and Status Register A
- $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
- $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
-&201 constant EUCSRB \ EUSART Control Register B
- $10 constant EUCSRB_EUSART \ EUSART Enable Bit
- $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
- $02 constant EUCSRB_EMCH \ Manchester Mode Bit
- $01 constant EUCSRB_BODR \ Order Bit
-&202 constant EUCSRC \ EUSART Status Register C
- $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
- $04 constant EUCSRC_F1617 \ F1617 Bit
- $03 constant EUCSRC_STP \ Stop Bits
-&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
- $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
-&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
- $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
-\ ANALOG_COMPARATOR
-&173 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&174 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&175 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&172 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&171 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&170 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&59 constant GPIOR3 \ General Purpose IO Register 3
- $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $E0 constant PRR_PRPSC \ Power Reduction PSC2
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
-&126 constant DIDR0 \ Digital Input Disable Register 0
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $20 constant DIDR1_ACMP0D \
- $10 constant DIDR1_AMP0PD \
- $08 constant DIDR1_AMP0ND \
- $04 constant DIDR1_ADC10D \
- $02 constant DIDR1_ADC9D \
- $01 constant DIDR1_ADC8D \
-&118 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $03 constant AMP0CSR_AMP0TS \
-&119 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $03 constant AMP1CSR_AMP1TS \
-\ USART
-&198 constant UDR \ USART I/O Data Register
-&192 constant UCSRA \ USART Control and Status register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data Overrun
- $04 constant UCSRA_UPE \ USART Parity Error
- $02 constant UCSRA_U2X \ Double USART Transmission Bit
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&193 constant UCSRB \ USART Control an Status register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&194 constant UCSRC \ USART Control an Status register C
- $40 constant UCSRC_UMSEL0 \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size Bits
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&197 constant UBRRH \ USART Baud Rate Register High Byte
- $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
-&196 constant UBRRL \ USART Baud Rate Register Low Byte
- $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC0
-&222 constant PICR0 \ PSC 0 Input Capture Register
-&221 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
- $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
-&220 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
- $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
-&219 constant PCTL0 \ PSC 0 Control Register
- $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
- $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
- $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
- $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- $01 constant PCTL0_PRUN0 \ PSC 0 Run
-&218 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
- $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
-&216 constant OCR0RB \ Output Compare RB Register
-&214 constant OCR0SB \ Output Compare SB Register
-&212 constant OCR0RA \ Output Compare RA Register
-&210 constant OCR0SA \ Output Compare SA Register
-&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
- $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
- $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
-&161 constant PIM0 \ PSC0 Interrupt Mask Register
- $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
- $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
- $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
-&160 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- $08 constant PIFR0_PEV0A \ External Event A Interrupt
- $06 constant PIFR0_PRN0 \ Ramp Number
- $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
-\ PSC1
-&238 constant PICR1 \ PSC 1 Input Capture Register
-&237 constant PFRC1B \ PSC 1 Input B Control
- $80 constant PFRC1B_PCAE1B \ PSC 1 Capture Enable Input Part B
- $40 constant PFRC1B_PISEL1B \ PSC 1 Input Select for Part B
- $20 constant PFRC1B_PELEV1B \ PSC 1 Edge Level Selector on Input Part B
- $10 constant PFRC1B_PFLTE1B \ PSC 1 Filter Enable on Input Part B
- $0F constant PFRC1B_PRFM1B \ PSC 1 Retrigger and Fault Mode for Part B
-&236 constant PFRC1A \ PSC 1 Input B Control
- $80 constant PFRC1A_PCAE1A \ PSC 1 Capture Enable Input Part A
- $40 constant PFRC1A_PISEL1A \ PSC 1 Input Select for Part A
- $20 constant PFRC1A_PELEV1A \ PSC 1 Edge Level Selector on Input Part A
- $10 constant PFRC1A_PFLTE1A \ PSC 1 Filter Enable on Input Part A
- $0F constant PFRC1A_PRFM1A \ PSC 1 Retrigger and Fault Mode for Part A
-&235 constant PCTL1 \ PSC 1 Control Register
- $C0 constant PCTL1_PPRE1 \ PSC 1 Prescaler Selects
- $20 constant PCTL1_PBFM1 \ Balance Flank Width Modulation
- $10 constant PCTL1_PAOC1B \ PSC 1 Asynchronous Output Control B
- $08 constant PCTL1_PAOC1A \ PSC 1 Asynchronous Output Control A
- $04 constant PCTL1_PARUN1 \ PSC1 Auto Run
- $02 constant PCTL1_PCCYC1 \ PSC1 Complete Cycle
- $01 constant PCTL1_PRUN1 \ PSC 1 Run
-&234 constant PCNF1 \ PSC 1 Configuration Register
- $80 constant PCNF1_PFIFTY1 \ PSC 1 Fifty
- $40 constant PCNF1_PALOCK1 \ PSC 1 Autolock
- $20 constant PCNF1_PLOCK1 \ PSC 1 Lock
- $18 constant PCNF1_PMODE1 \ PSC 1 Mode
- $04 constant PCNF1_POP1 \ PSC 1 Output Polarity
- $02 constant PCNF1_PCLKSEL1 \ PSC 1 Input Clock Select
-&232 constant OCR1RB \ Output Compare RB Register
-&230 constant OCR1SB \ Output Compare SB Register
-&228 constant OCR1RA \ Output Compare RA Register
-&226 constant OCR1SA \ Output Compare SA Register
-&224 constant PSOC1 \ PSC1 Synchro and Output Configuration
- $30 constant PSOC1_PSYNC1_ \ Synchronization Out for ADC Selection
- $04 constant PSOC1_POEN1B \ PSCOUT11 Output Enable
- $01 constant PSOC1_POEN1A \ PSCOUT10 Output Enable
-&163 constant PIM1 \ PSC1 Interrupt Mask Register
- $20 constant PIM1_PSEIE1 \ PSC 1 Synchro Error Interrupt Enable
- $10 constant PIM1_PEVE1B \ External Event B Interrupt Enable
- $08 constant PIM1_PEVE1A \ External Event A Interrupt Enable
- $01 constant PIM1_PEOPE1 \ End of Cycle Interrupt Enable
-&162 constant PIFR1 \ PSC1 Interrupt Flag Register
- $80 constant PIFR1_POAC1B \ PSC 1 Output B Activity
- $40 constant PIFR1_POAC1A \ PSC 1 Output A Activity
- $20 constant PIFR1_PSEI1 \ PSC 1 Synchro Error Interrupt
- $10 constant PIFR1_PEV1B \ External Event B Interrupt
- $08 constant PIFR1_PEV1A \ External Event A Interrupt
- $06 constant PIFR1_PRN1 \ Ramp Number
- $01 constant PIFR1_PEOP1 \ End of PSC1 Interrupt
-\ PSC2
-&254 constant PICR2 \ PSC 2 Input Capture Register
-&253 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
- $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
-&252 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
- $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
-&251 constant PCTL2 \ PSC 2 Control Register
- $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
- $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
- $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
- $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- $01 constant PCTL2_PRUN2 \ PSC 2 Run
-&250 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
- $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
-&248 constant OCR2RB \ Output Compare RB Register
-&246 constant OCR2SB \ Output Compare SB Register
-&244 constant OCR2RA \ Output Compare RA Register
-&242 constant OCR2SA \ Output Compare SA Register
-&241 constant POM2 \ PSC 2 Output Matrix
- $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
-&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
- $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
- $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
-&165 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
- $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
- $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
-&164 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- $08 constant PIFR2_PEV2A \ External Event A Interrupt
- $06 constant PIFR2_PRN2 \ Ramp Number
- $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
-
-\ Interrupts
-&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
-&2 constant PSC2_ECAddr \ PSC2 End Cycle
-&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
-&4 constant PSC1_ECAddr \ PSC1 End Cycle
-&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
-&6 constant PSC0_ECAddr \ PSC0 End Cycle
-&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
-&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-&10 constant INT0Addr \ External Interrupt Request 0
-&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&14 constant RESERVED15Addr \
-&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
-&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&18 constant ADCAddr \ ADC Conversion Complete
-&19 constant INT1Addr \ External Interrupt Request 1
-&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&21 constant USART__RXAddr \ USART, Rx Complete
-&22 constant USART__UDREAddr \ USART Data Register Empty
-&23 constant USART__TXAddr \ USART, Tx Complete
-&24 constant INT2Addr \ External Interrupt Request 2
-&25 constant WDTAddr \ Watchdog Timeout Interrupt
-&26 constant EE_READYAddr \ EEPROM Ready
-&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
-&28 constant INT3Addr \ External Interrupt Request 3
-&29 constant RESERVED30Addr \
-&30 constant RESERVED31Addr \
-&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/device.asm b/amforth-6.5/avr8/devices/at90pwm3b/device.asm
deleted file mode 100644
index e3fafb9..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/device.asm
+++ /dev/null
@@ -1,125 +0,0 @@
-; Partname: AT90PWM3B
-; generated automatically, do not edit
-
-.nolist
- .include "pwm3Bdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EUSART = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_USART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC1 = 0
-.set WANT_PSC2 = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; PSC2 Capture Event
-.org 2
- rcall isr ; PSC2 End Cycle
-.org 3
- rcall isr ; PSC1 Capture Event
-.org 4
- rcall isr ; PSC1 End Cycle
-.org 5
- rcall isr ; PSC0 Capture Event
-.org 6
- rcall isr ; PSC0 End Cycle
-.org 7
- rcall isr ; Analog Comparator 0
-.org 8
- rcall isr ; Analog Comparator 1
-.org 9
- rcall isr ; Analog Comparator 2
-.org 10
- rcall isr ; External Interrupt Request 0
-.org 11
- rcall isr ; Timer/Counter1 Capture Event
-.org 12
- rcall isr ; Timer/Counter1 Compare Match A
-.org 13
- rcall isr ; Timer/Counter Compare Match B
-.org 14
- rcall isr ;
-.org 15
- rcall isr ; Timer/Counter1 Overflow
-.org 16
- rcall isr ; Timer/Counter0 Compare Match A
-.org 17
- rcall isr ; Timer/Counter0 Overflow
-.org 18
- rcall isr ; ADC Conversion Complete
-.org 19
- rcall isr ; External Interrupt Request 1
-.org 20
- rcall isr ; SPI Serial Transfer Complete
-.org 21
- rcall isr ; USART, Rx Complete
-.org 22
- rcall isr ; USART Data Register Empty
-.org 23
- rcall isr ; USART, Tx Complete
-.org 24
- rcall isr ; External Interrupt Request 2
-.org 25
- rcall isr ; Watchdog Timeout Interrupt
-.org 26
- rcall isr ; EEPROM Ready
-.org 27
- rcall isr ; Timer Counter 0 Compare Match B
-.org 28
- rcall isr ; External Interrupt Request 3
-.org 29
- rcall isr ;
-.org 30
- rcall isr ;
-.org 31
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 32
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 32
-mcu_name:
- .dw 9
- .db "AT90PWM3B",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/device.inc b/amforth-6.5/avr8/devices/at90pwm3b/device.inc
deleted file mode 100644
index 8b83af9..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/device.inc
+++ /dev/null
@@ -1,1467 +0,0 @@
-; Partname: AT90PWM3B
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EUSART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART I/O Data Register
-VE_EUDR:
- .dw $ff04
- .db "EUDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUDR
-XT_EUDR:
- .dw PFA_DOVARIABLE
-PFA_EUDR:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control and Status Register A
-VE_EUCSRA:
- .dw $ff06
- .db "EUCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRA
-XT_EUCSRA:
- .dw PFA_DOVARIABLE
-PFA_EUCSRA:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Control Register B
-VE_EUCSRB:
- .dw $ff06
- .db "EUCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRB
-XT_EUCSRB:
- .dw PFA_DOVARIABLE
-PFA_EUCSRB:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; EUSART Status Register C
-VE_EUCSRC:
- .dw $ff06
- .db "EUCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_EUCSRC
-XT_EUCSRC:
- .dw PFA_DOVARIABLE
-PFA_EUCSRC:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register High Byte
-VE_MUBRRH:
- .dw $ff06
- .db "MUBRRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRH
-XT_MUBRRH:
- .dw PFA_DOVARIABLE
-PFA_MUBRRH:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; Manchester Receiver Baud Rate Register Low Byte
-VE_MUBRRL:
- .dw $ff06
- .db "MUBRRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_MUBRRL
-XT_MUBRRL:
- .dw PFA_DOVARIABLE
-PFA_MUBRRL:
- .dw 204
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 170
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 3
-VE_GPIOR3:
- .dw $ff06
- .db "GPIOR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR3
-XT_GPIOR3:
- .dw PFA_DOVARIABLE
-PFA_GPIOR3:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 119
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control an Status register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 197
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 196
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register
-VE_PICR0:
- .dw $ff05
- .db "PICR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0
-XT_PICR0:
- .dw PFA_DOVARIABLE
-PFA_PICR0:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR0RB:
- .dw $ff06
- .db "OCR0RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RB
-XT_OCR0RB:
- .dw PFA_DOVARIABLE
-PFA_OCR0RB:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR0SB:
- .dw $ff06
- .db "OCR0SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SB
-XT_OCR0SB:
- .dw PFA_DOVARIABLE
-PFA_OCR0SB:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR0RA:
- .dw $ff06
- .db "OCR0RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RA
-XT_OCR0RA:
- .dw PFA_DOVARIABLE
-PFA_OCR0RA:
- .dw 212
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR0SA:
- .dw $ff06
- .db "OCR0SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SA
-XT_OCR0SA:
- .dw PFA_DOVARIABLE
-PFA_OCR0SA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw 160
-
-.endif
-.if WANT_PSC1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input Capture Register
-VE_PICR1:
- .dw $ff05
- .db "PICR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR1
-XT_PICR1:
- .dw PFA_DOVARIABLE
-PFA_PICR1:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1B:
- .dw $ff06
- .db "PFRC1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1B
-XT_PFRC1B:
- .dw PFA_DOVARIABLE
-PFA_PFRC1B:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Input B Control
-VE_PFRC1A:
- .dw $ff06
- .db "PFRC1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC1A
-XT_PFRC1A:
- .dw PFA_DOVARIABLE
-PFA_PFRC1A:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Control Register
-VE_PCTL1:
- .dw $ff05
- .db "PCTL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL1
-XT_PCTL1:
- .dw PFA_DOVARIABLE
-PFA_PCTL1:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 1 Configuration Register
-VE_PCNF1:
- .dw $ff05
- .db "PCNF1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF1
-XT_PCNF1:
- .dw PFA_DOVARIABLE
-PFA_PCNF1:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR1RB:
- .dw $ff06
- .db "OCR1RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RB
-XT_OCR1RB:
- .dw PFA_DOVARIABLE
-PFA_OCR1RB:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR1SB:
- .dw $ff06
- .db "OCR1SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SB
-XT_OCR1SB:
- .dw PFA_DOVARIABLE
-PFA_OCR1SB:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR1RA:
- .dw $ff06
- .db "OCR1RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1RA
-XT_OCR1RA:
- .dw PFA_DOVARIABLE
-PFA_OCR1RA:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR1SA:
- .dw $ff06
- .db "OCR1SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1SA
-XT_OCR1SA:
- .dw PFA_DOVARIABLE
-PFA_OCR1SA:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Synchro and Output Configuration
-VE_PSOC1:
- .dw $ff05
- .db "PSOC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC1
-XT_PSOC1:
- .dw PFA_DOVARIABLE
-PFA_PSOC1:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Interrupt Mask Register
-VE_PIM1:
- .dw $ff04
- .db "PIM1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM1
-XT_PIM1:
- .dw PFA_DOVARIABLE
-PFA_PIM1:
- .dw 163
-; ( -- addr ) System Constant
-; R( -- )
-; PSC1 Interrupt Flag Register
-VE_PIFR1:
- .dw $ff05
- .db "PIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR1
-XT_PIFR1:
- .dw PFA_DOVARIABLE
-PFA_PIFR1:
- .dw 162
-
-.endif
-.if WANT_PSC2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register
-VE_PICR2:
- .dw $ff05
- .db "PICR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2
-XT_PICR2:
- .dw PFA_DOVARIABLE
-PFA_PICR2:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR2RB:
- .dw $ff06
- .db "OCR2RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RB
-XT_OCR2RB:
- .dw PFA_DOVARIABLE
-PFA_OCR2RB:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR2SB:
- .dw $ff06
- .db "OCR2SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SB
-XT_OCR2SB:
- .dw PFA_DOVARIABLE
-PFA_OCR2SB:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR2RA:
- .dw $ff06
- .db "OCR2RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RA
-XT_OCR2RA:
- .dw PFA_DOVARIABLE
-PFA_OCR2RA:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR2SA:
- .dw $ff06
- .db "OCR2SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SA
-XT_OCR2SA:
- .dw PFA_DOVARIABLE
-PFA_OCR2SA:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw 164
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/device.py b/amforth-6.5/avr8/devices/at90pwm3b/device.py
deleted file mode 100644
index a547e53..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/device.py
+++ /dev/null
@@ -1,505 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM3B
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
- 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
- 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
- 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
- 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'RESERVED15Addr' : '#28', #
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'ADCAddr' : '#36', # ADC Conversion Complete
- 'INT1Addr' : '#38', # External Interrupt Request 1
- 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#42', # USART, Rx Complete
- 'USART_UDREAddr' : '#44', # USART Data Register Empty
- 'USART_TXAddr' : '#46', # USART, Tx Complete
- 'INT2Addr' : '#48', # External Interrupt Request 2
- 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#52', # EEPROM Ready
- 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
- 'INT3Addr' : '#56', # External Interrupt Request 3
- 'RESERVED30Addr' : '#58', #
- 'RESERVED31Addr' : '#60', #
- 'SPM_READYAddr' : '#62', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EUSART
- 'EUDR' : '$ce', # EUSART I/O Data Register
- 'EUCSRA' : '$c8', # EUSART Control and Status Regi
- 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
- 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
- 'EUCSRB' : '$c9', # EUSART Control Register B
- 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
- 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
- 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
- 'EUCSRB_BODR': '$1', # Order Bit
- 'EUCSRC' : '$ca', # EUSART Status Register C
- 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
- 'EUCSRC_F1617': '$4', # F1617 Bit
- 'EUCSRC_STP': '$3', # Stop Bits
- 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
- 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
- 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
- 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$af', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$ac', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$ab', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$aa', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR3' : '$3b', # General Purpose IO Register 3
- 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRPSC': '$e0', # Power Reduction PSC2
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_ACMP0D': '$20', #
- 'DIDR1_AMP0PD': '$10', #
- 'DIDR1_AMP0ND': '$8', #
- 'DIDR1_ADC10D': '$4', #
- 'DIDR1_ADC9D': '$2', #
- 'DIDR1_ADC8D': '$1', #
- 'AMP0CSR' : '$76', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0TS': '$3', #
- 'AMP1CSR' : '$77', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMP1TS': '$3', #
-
-# Module USART
- 'UDR' : '$c6', # USART I/O Data Register
- 'UCSRA' : '$c0', # USART Control and Status regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data Overrun
- 'UCSRA_UPE': '$4', # USART Parity Error
- 'UCSRA_U2X': '$2', # Double USART Transmission Bit
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$c1', # USART Control an Status regist
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$c2', # USART Control an Status regist
- 'UCSRC_UMSEL0': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size Bits
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$c5', # USART Baud Rate Register High
- 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
- 'UBRRL' : '$c4', # USART Baud Rate Register Low B
- 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC0
- 'PICR0' : '$de', # PSC 0 Input Capture Register
- 'PFRC0B' : '$dd', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$dc', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$db', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$da', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$d8', # Output Compare RB Register
- 'OCR0SB' : '$d6', # Output Compare SB Register
- 'OCR0RA' : '$d4', # Output Compare RA Register
- 'OCR0SA' : '$d2', # Output Compare SA Register
- 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
- 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
- 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
- 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
- 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
- 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC1
- 'PICR1' : '$ee', # PSC 1 Input Capture Register
- 'PFRC1B' : '$ed', # PSC 1 Input B Control
- 'PFRC1B_PCAE1B': '$80', # PSC 1 Capture Enable Input Par
- 'PFRC1B_PISEL1B': '$40', # PSC 1 Input Select for Part B
- 'PFRC1B_PELEV1B': '$20', # PSC 1 Edge Level Selector on I
- 'PFRC1B_PFLTE1B': '$10', # PSC 1 Filter Enable on Input P
- 'PFRC1B_PRFM1B': '$f', # PSC 1 Retrigger and Fault Mode
- 'PFRC1A' : '$ec', # PSC 1 Input B Control
- 'PFRC1A_PCAE1A': '$80', # PSC 1 Capture Enable Input Par
- 'PFRC1A_PISEL1A': '$40', # PSC 1 Input Select for Part A
- 'PFRC1A_PELEV1A': '$20', # PSC 1 Edge Level Selector on I
- 'PFRC1A_PFLTE1A': '$10', # PSC 1 Filter Enable on Input P
- 'PFRC1A_PRFM1A': '$f', # PSC 1 Retrigger and Fault Mode
- 'PCTL1' : '$eb', # PSC 1 Control Register
- 'PCTL1_PPRE1': '$c0', # PSC 1 Prescaler Selects
- 'PCTL1_PBFM1': '$20', # Balance Flank Width Modulation
- 'PCTL1_PAOC1B': '$10', # PSC 1 Asynchronous Output Cont
- 'PCTL1_PAOC1A': '$8', # PSC 1 Asynchronous Output Cont
- 'PCTL1_PARUN1': '$4', # PSC1 Auto Run
- 'PCTL1_PCCYC1': '$2', # PSC1 Complete Cycle
- 'PCTL1_PRUN1': '$1', # PSC 1 Run
- 'PCNF1' : '$ea', # PSC 1 Configuration Register
- 'PCNF1_PFIFTY1': '$80', # PSC 1 Fifty
- 'PCNF1_PALOCK1': '$40', # PSC 1 Autolock
- 'PCNF1_PLOCK1': '$20', # PSC 1 Lock
- 'PCNF1_PMODE1': '$18', # PSC 1 Mode
- 'PCNF1_POP1': '$4', # PSC 1 Output Polarity
- 'PCNF1_PCLKSEL1': '$2', # PSC 1 Input Clock Select
- 'OCR1RB' : '$e8', # Output Compare RB Register
- 'OCR1SB' : '$e6', # Output Compare SB Register
- 'OCR1RA' : '$e4', # Output Compare RA Register
- 'OCR1SA' : '$e2', # Output Compare SA Register
- 'PSOC1' : '$e0', # PSC1 Synchro and Output Config
- 'PSOC1_PSYNC1_': '$30', # Synchronization Out for ADC Se
- 'PSOC1_POEN1B': '$4', # PSCOUT11 Output Enable
- 'PSOC1_POEN1A': '$1', # PSCOUT10 Output Enable
- 'PIM1' : '$a3', # PSC1 Interrupt Mask Register
- 'PIM1_PSEIE1': '$20', # PSC 1 Synchro Error Interrupt
- 'PIM1_PEVE1B': '$10', # External Event B Interrupt Ena
- 'PIM1_PEVE1A': '$8', # External Event A Interrupt Ena
- 'PIM1_PEOPE1': '$1', # End of Cycle Interrupt Enable
- 'PIFR1' : '$a2', # PSC1 Interrupt Flag Register
- 'PIFR1_POAC1B': '$80', # PSC 1 Output B Activity
- 'PIFR1_POAC1A': '$40', # PSC 1 Output A Activity
- 'PIFR1_PSEI1': '$20', # PSC 1 Synchro Error Interrupt
- 'PIFR1_PEV1B': '$10', # External Event B Interrupt
- 'PIFR1_PEV1A': '$8', # External Event A Interrupt
- 'PIFR1_PRN1': '$6', # Ramp Number
- 'PIFR1_PEOP1': '$1', # End of PSC1 Interrupt
-
-# Module PSC2
- 'PICR2' : '$fe', # PSC 2 Input Capture Register
- 'PFRC2B' : '$fd', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$fc', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$fb', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$fa', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'OCR2RB' : '$f8', # Output Compare RB Register
- 'OCR2SB' : '$f6', # Output Compare SB Register
- 'OCR2RA' : '$f4', # Output Compare RA Register
- 'OCR2SA' : '$f2', # Output Compare SA Register
- 'POM2' : '$f1', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
- 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
- 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt b/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt
deleted file mode 100644
index a25970a..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt
+++ /dev/null
@@ -1,370 +0,0 @@
-\ Partname: AT90PWM81
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ DA_CONVERTER
-&89 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&88 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&118 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ SPI
-&55 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&56 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&86 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&130 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&137 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&65 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&64 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-\ AD_CONVERTER
-&40 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&76 constant ADC \ ADC Data Register Bytes
-&39 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
- $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC's Synchronisation Signals
- $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&119 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&120 constant DIDR1 \ Digital Input Disable Register 0
- $08 constant DIDR1_ACMP1MD \
- $04 constant DIDR1_AMP0POSD \
- $02 constant DIDR1_ADC10D \
- $01 constant DIDR1_ADC9D \
-&121 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $08 constant AMP0CSR_AMP0GS \
- $03 constant AMP0CSR_AMP0TS \
-\ ANALOG_COMPARATOR
-&127 constant AC3CON \ Analog Comparator3 Control Register
- $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
- $08 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate Output Enable
- $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
-&125 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&126 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&32 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
-&124 constant AC3ECON \
- $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
- $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
- $07 constant AC3ECON_AC3H \ Analog Comparator Hysteresis Select
-&123 constant AC2ECON \
- $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
- $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
- $07 constant AC2ECON_AC2H \ Analog Comparator Hysteresis Select
-&122 constant AC1ECON \
- $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
- $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
- $08 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Capture Enable
- $07 constant AC1ECON_AC1H \ Analog Comparator Hysteresis Select
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $08 constant MCUCR_RSTDIS \ Reset Pin Disable
- $04 constant MCUCR_CKRC81 \ Frequency Selection of the Calibrated RC Oscillator
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&136 constant OSCCAL \ Oscillator Calibration Value
-&131 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&59 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&58 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&57 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&135 constant PLLCSR \ PLL Control And Status Register
- $3C constant PLLCSR_PLLF \
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&134 constant PRR \ Power Reduction Register
- $80 constant PRR_PRPSC2 \ Power Reduction PSC2
- $20 constant PRR_PRPSCR \ Power Reduction PSC0
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR_PRADC \ Power Reduction ADC
-&132 constant CLKCSR \
- $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
- $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
- $0F constant CLKCSR_CLKC \ Clock Control
-&133 constant CLKSELR \
- $40 constant CLKSELR_COUT \ Clock OUT
- $30 constant CLKSELR_CSUT \ Clock Start up Time
- $0F constant CLKSELR_CKSEL \ Clock Source Select
-&129 constant BGCCR \ BandGap Current Calibration Register
- $0F constant BGCCR_BGCC \
-&128 constant BGCRR \ BandGap Resistor Calibration Register
- $0F constant BGCRR_BGCR \
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
- $40 constant EECR_EEPAGE \ EEPROM Page Access
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC0
-&104 constant PICR0 \ PSC 0 Input Capture Register
-&99 constant PFRC0B \ PSC 0 Input B Control
- $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
- $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
- $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
- $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
- $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
-&98 constant PFRC0A \ PSC 0 Input A Control
- $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
- $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
- $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
- $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
- $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
-&50 constant PCTL0 \ PSC 0 Control Register
- $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
- $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
- $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
- $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
- $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
- $01 constant PCTL0_PRUN0 \ PSC 0 Run
-&49 constant PCNF0 \ PSC 0 Configuration Register
- $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
- $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
- $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
- $18 constant PCNF0_PMODE0 \ PSC 0 Mode
- $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
- $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
-&68 constant OCR0RB \ Output Compare RB Register
-&66 constant OCR0SB \ Output Compare SB Register
-&74 constant OCR0RA \ Output Compare RA Register
-&96 constant OCR0SA \ Output Compare SA Register
-&106 constant PSOC0 \ PSC0 Synchro and Output Configuration
- $80 constant PSOC0_PISEL0A1 \ PSC Input Select
- $40 constant PSOC0_PISEL0B1 \ PSC Input Select
- $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC selection
- $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
- $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
-&47 constant PIM0 \ PSC0 Interrupt Mask Register
- $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
- $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
- $02 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
- $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
-&48 constant PIFR0 \ PSC0 Interrupt Flag Register
- $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
- $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
- $10 constant PIFR0_PEV0B \ External Event B Interrupt
- $08 constant PIFR0_PEV0A \ External Event A Interrupt
- $06 constant PIFR0_PRN0 \ Ramp Number
- $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
-\ PSC2
-&109 constant PICR2H \ PSC 2 Input Capture Register High
- $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger Bit
- $0C constant PICR2H_PICR21 \
- $03 constant PICR2H_PICR2 \
-&108 constant PICR2L \ PSC 2 Input Capture Register Low
-&103 constant PFRC2B \ PSC 2 Input B Control
- $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
- $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
- $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
- $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
- $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
-&102 constant PFRC2A \ PSC 2 Input B Control
- $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
- $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
- $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
- $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
- $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
-&54 constant PCTL2 \ PSC 2 Control Register
- $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
- $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
- $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
- $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
- $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
- $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
- $01 constant PCTL2_PRUN2 \ PSC 2 Run
-&53 constant PCNF2 \ PSC 2 Configuration Register
- $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
- $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
- $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
- $18 constant PCNF2_PMODE2 \ PSC 2 Mode
- $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
- $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
- $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
-&112 constant PCNFE2 \ PSC 2 Enhanced Configuration Register
- $E0 constant PCNFE2_PASDLK2 \
- $10 constant PCNFE2_PBFM21 \
- $08 constant PCNFE2_PELEV2A1 \
- $04 constant PCNFE2_PELEV2B1 \
- $02 constant PCNFE2_PISEL2A1 \
- $01 constant PCNFE2_PISEL2B1 \
-&72 constant OCR2RB \ Output Compare RB Register
-&70 constant OCR2SB \ Output Compare SB Register
-&78 constant OCR2RA \ Output Compare RA Register
-&100 constant OCR2SA \ Output Compare SA Register
-&111 constant POM2 \ PSC 2 Output Matrix
- $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
- $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
-&110 constant PSOC2 \ PSC2 Synchro and Output Configuration
- $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
- $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Selection
- $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
- $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
- $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
- $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
-&51 constant PIM2 \ PSC2 Interrupt Mask Register
- $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
- $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
- $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
- $02 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrupt Enable
- $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
-&52 constant PIFR2 \ PSC2 Interrupt Flag Register
- $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
- $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
- $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
- $10 constant PIFR2_PEV2B \ External Event B Interrupt
- $08 constant PIFR2_PEV2A \ External Event A Interrupt
- $06 constant PIFR2_PRN2 \ Ramp Number
- $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
-&113 constant PASDLY2 \ Analog Synchronization Delay Register
-\ TIMER_COUNTER_1
-&33 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&34 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&138 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&90 constant TCNT1 \ Timer/Counter1 Bytes
-&140 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-
-\ Interrupts
-&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
-&2 constant PSC2_ECAddr \ PSC2 End Cycle
-&3 constant PSC2_EECAddr \ PSC2 End Of Enhanced Cycle
-&4 constant PSC0_CAPTAddr \ PSC0 Capture Event
-&5 constant PSC0_ECAddr \ PSC0 End Cycle
-&6 constant PSC0_EECAddr \ PSC0 End Of Enhanced Cycle
-&7 constant ANALOG_COMP_1Addr \ Analog Comparator 1
-&8 constant ANALOG_COMP_2Addr \ Analog Comparator 2
-&9 constant ANALOG_COMP_3Addr \ Analog Comparator 3
-&10 constant INT0Addr \ External Interrupt Request 0
-&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&12 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&13 constant ADCAddr \ ADC Conversion Complete
-&14 constant INT1Addr \ External Interrupt Request 1
-&15 constant SPI__STCAddr \ SPI Serial Transfer Complet
-&16 constant INT2Addr \ External Interrupt Request 2
-&17 constant WDTAddr \ Watchdog Timeout Interrupt
-&18 constant EE_READYAddr \ EEPROM Ready
-&19 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.asm b/amforth-6.5/avr8/devices/at90pwm81/device.asm
deleted file mode 100644
index b836c8e..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/device.asm
+++ /dev/null
@@ -1,96 +0,0 @@
-; Partname: AT90PWM81
-; generated automatically, do not edit
-
-.nolist
- .include "pwm81def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_PORTE = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC0 = 0
-.set WANT_PSC2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_BOOT_LOAD = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; PSC2 Capture Event
-.org 2
- rcall isr ; PSC2 End Cycle
-.org 3
- rcall isr ; PSC2 End Of Enhanced Cycle
-.org 4
- rcall isr ; PSC0 Capture Event
-.org 5
- rcall isr ; PSC0 End Cycle
-.org 6
- rcall isr ; PSC0 End Of Enhanced Cycle
-.org 7
- rcall isr ; Analog Comparator 1
-.org 8
- rcall isr ; Analog Comparator 2
-.org 9
- rcall isr ; Analog Comparator 3
-.org 10
- rcall isr ; External Interrupt Request 0
-.org 11
- rcall isr ; Timer/Counter1 Capture Event
-.org 12
- rcall isr ; Timer/Counter1 Overflow
-.org 13
- rcall isr ; ADC Conversion Complete
-.org 14
- rcall isr ; External Interrupt Request 1
-.org 15
- rcall isr ; SPI Serial Transfer Complet
-.org 16
- rcall isr ; External Interrupt Request 2
-.org 17
- rcall isr ; Watchdog Timeout Interrupt
-.org 18
- rcall isr ; EEPROM Ready
-.org 19
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 20
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 256
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 20
-mcu_name:
- .dw 9
- .db "AT90PWM81",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.inc b/amforth-6.5/avr8/devices/at90pwm81/device.inc
deleted file mode 100644
index 64c1370..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/device.inc
+++ /dev/null
@@ -1,1080 +0,0 @@
-; Partname: AT90PWM81
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 118
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 86
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 130
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 137
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 64
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 119
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 121
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator3 Control Register
-VE_AC3CON:
- .dw $ff06
- .db "AC3CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3CON
-XT_AC3CON:
- .dw PFA_DOVARIABLE
-PFA_AC3CON:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AC3ECON:
- .dw $ff07
- .db "AC3ECON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3ECON
-XT_AC3ECON:
- .dw PFA_DOVARIABLE
-PFA_AC3ECON:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AC2ECON:
- .dw $ff07
- .db "AC2ECON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2ECON
-XT_AC2ECON:
- .dw PFA_DOVARIABLE
-PFA_AC2ECON:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AC1ECON:
- .dw $ff07
- .db "AC1ECON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1ECON
-XT_AC1ECON:
- .dw PFA_DOVARIABLE
-PFA_AC1ECON:
- .dw 122
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 131
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 135
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKCSR:
- .dw $ff06
- .db "CLKCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKCSR
-XT_CLKCSR:
- .dw PFA_DOVARIABLE
-PFA_CLKCSR:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSELR:
- .dw $ff07
- .db "CLKSELR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSELR
-XT_CLKSELR:
- .dw PFA_DOVARIABLE
-PFA_CLKSELR:
- .dw 133
-; ( -- addr ) System Constant
-; R( -- )
-; BandGap Current Calibration Register
-VE_BGCCR:
- .dw $ff05
- .db "BGCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCCR
-XT_BGCCR:
- .dw PFA_DOVARIABLE
-PFA_BGCCR:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; BandGap Resistor Calibration Register
-VE_BGCRR:
- .dw $ff05
- .db "BGCRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRR
-XT_BGCRR:
- .dw PFA_DOVARIABLE
-PFA_BGCRR:
- .dw 128
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_PSC0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input Capture Register
-VE_PICR0:
- .dw $ff05
- .db "PICR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR0
-XT_PICR0:
- .dw PFA_DOVARIABLE
-PFA_PICR0:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input B Control
-VE_PFRC0B:
- .dw $ff06
- .db "PFRC0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0B
-XT_PFRC0B:
- .dw PFA_DOVARIABLE
-PFA_PFRC0B:
- .dw 99
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Input A Control
-VE_PFRC0A:
- .dw $ff06
- .db "PFRC0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC0A
-XT_PFRC0A:
- .dw PFA_DOVARIABLE
-PFA_PFRC0A:
- .dw 98
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Control Register
-VE_PCTL0:
- .dw $ff05
- .db "PCTL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL0
-XT_PCTL0:
- .dw PFA_DOVARIABLE
-PFA_PCTL0:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 0 Configuration Register
-VE_PCNF0:
- .dw $ff05
- .db "PCNF0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF0
-XT_PCNF0:
- .dw PFA_DOVARIABLE
-PFA_PCNF0:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR0RB:
- .dw $ff06
- .db "OCR0RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RB
-XT_OCR0RB:
- .dw PFA_DOVARIABLE
-PFA_OCR0RB:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR0SB:
- .dw $ff06
- .db "OCR0SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SB
-XT_OCR0SB:
- .dw PFA_DOVARIABLE
-PFA_OCR0SB:
- .dw 66
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR0RA:
- .dw $ff06
- .db "OCR0RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0RA
-XT_OCR0RA:
- .dw PFA_DOVARIABLE
-PFA_OCR0RA:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR0SA:
- .dw $ff06
- .db "OCR0SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0SA
-XT_OCR0SA:
- .dw PFA_DOVARIABLE
-PFA_OCR0SA:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Synchro and Output Configuration
-VE_PSOC0:
- .dw $ff05
- .db "PSOC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC0
-XT_PSOC0:
- .dw PFA_DOVARIABLE
-PFA_PSOC0:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Mask Register
-VE_PIM0:
- .dw $ff04
- .db "PIM0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM0
-XT_PIM0:
- .dw PFA_DOVARIABLE
-PFA_PIM0:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; PSC0 Interrupt Flag Register
-VE_PIFR0:
- .dw $ff05
- .db "PIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR0
-XT_PIFR0:
- .dw PFA_DOVARIABLE
-PFA_PIFR0:
- .dw 48
-
-.endif
-.if WANT_PSC2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register High
-VE_PICR2H:
- .dw $ff06
- .db "PICR2H"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2H
-XT_PICR2H:
- .dw PFA_DOVARIABLE
-PFA_PICR2H:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input Capture Register Low
-VE_PICR2L:
- .dw $ff06
- .db "PICR2L"
- .dw VE_HEAD
- .set VE_HEAD=VE_PICR2L
-XT_PICR2L:
- .dw PFA_DOVARIABLE
-PFA_PICR2L:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2B:
- .dw $ff06
- .db "PFRC2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2B
-XT_PFRC2B:
- .dw PFA_DOVARIABLE
-PFA_PFRC2B:
- .dw 103
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Input B Control
-VE_PFRC2A:
- .dw $ff06
- .db "PFRC2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_PFRC2A
-XT_PFRC2A:
- .dw PFA_DOVARIABLE
-PFA_PFRC2A:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Control Register
-VE_PCTL2:
- .dw $ff05
- .db "PCTL2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL2
-XT_PCTL2:
- .dw PFA_DOVARIABLE
-PFA_PCTL2:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Configuration Register
-VE_PCNF2:
- .dw $ff05
- .db "PCNF2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF2
-XT_PCNF2:
- .dw PFA_DOVARIABLE
-PFA_PCNF2:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Enhanced Configuration Register
-VE_PCNFE2:
- .dw $ff06
- .db "PCNFE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNFE2
-XT_PCNFE2:
- .dw PFA_DOVARIABLE
-PFA_PCNFE2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RB Register
-VE_OCR2RB:
- .dw $ff06
- .db "OCR2RB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RB
-XT_OCR2RB:
- .dw PFA_DOVARIABLE
-PFA_OCR2RB:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SB Register
-VE_OCR2SB:
- .dw $ff06
- .db "OCR2SB"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SB
-XT_OCR2SB:
- .dw PFA_DOVARIABLE
-PFA_OCR2SB:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare RA Register
-VE_OCR2RA:
- .dw $ff06
- .db "OCR2RA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2RA
-XT_OCR2RA:
- .dw PFA_DOVARIABLE
-PFA_OCR2RA:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare SA Register
-VE_OCR2SA:
- .dw $ff06
- .db "OCR2SA"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2SA
-XT_OCR2SA:
- .dw PFA_DOVARIABLE
-PFA_OCR2SA:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; PSC 2 Output Matrix
-VE_POM2:
- .dw $ff04
- .db "POM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_POM2
-XT_POM2:
- .dw PFA_DOVARIABLE
-PFA_POM2:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Synchro and Output Configuration
-VE_PSOC2:
- .dw $ff05
- .db "PSOC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSOC2
-XT_PSOC2:
- .dw PFA_DOVARIABLE
-PFA_PSOC2:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Mask Register
-VE_PIM2:
- .dw $ff04
- .db "PIM2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM2
-XT_PIM2:
- .dw PFA_DOVARIABLE
-PFA_PIM2:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; PSC2 Interrupt Flag Register
-VE_PIFR2:
- .dw $ff05
- .db "PIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR2
-XT_PIFR2:
- .dw PFA_DOVARIABLE
-PFA_PIFR2:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Synchronization Delay Register
-VE_PASDLY2:
- .dw $ff07
- .db "PASDLY2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PASDLY2
-XT_PASDLY2:
- .dw PFA_DOVARIABLE
-PFA_PASDLY2:
- .dw 113
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 140
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.py b/amforth-6.5/avr8/devices/at90pwm81/device.py
deleted file mode 100644
index 853ac3a..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/device.py
+++ /dev/null
@@ -1,389 +0,0 @@
-# Generated Automatically
-
-# Partname AT90PWM81
-
-MCUREGS = {
-# Interrupt Vectors
- 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
- 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
- 'PSC2_EECAddr' : '#6', # PSC2 End Of Enhanced Cycle
- 'PSC0_CAPTAddr' : '#8', # PSC0 Capture Event
- 'PSC0_ECAddr' : '#10', # PSC0 End Cycle
- 'PSC0_EECAddr' : '#12', # PSC0 End Of Enhanced Cycle
- 'ANALOG_COMP_1Addr' : '#14', # Analog Comparator 1
- 'ANALOG_COMP_2Addr' : '#16', # Analog Comparator 2
- 'ANALOG_COMP_3Addr' : '#18', # Analog Comparator 3
- 'INT0Addr' : '#20', # External Interrupt Request 0
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_OVFAddr' : '#24', # Timer/Counter1 Overflow
- 'ADCAddr' : '#26', # ADC Conversion Complete
- 'INT1Addr' : '#28', # External Interrupt Request 1
- 'SPI_STCAddr' : '#30', # SPI Serial Transfer Complet
- 'INT2Addr' : '#32', # External Interrupt Request 2
- 'WDTAddr' : '#34', # Watchdog Timeout Interrupt
- 'EE_READYAddr' : '#36', # EEPROM Ready
- 'SPM_READYAddr' : '#38', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module DA_CONVERTER
- 'DACH' : '$59', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$58', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$76', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module SPI
- 'SPCR' : '$37', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$38', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$56', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$82', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$89', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$41', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$40', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
-
-# Module AD_CONVERTER
- 'ADMUX' : '$28', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$4c', # ADC Data Register Bytes
- 'ADCSRB' : '$27', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADNCDIS': '$40', # ADC Noise Canceller Disable
- 'ADCSRB_ADSSEN': '$10', # ADC Single Shot Enable on PSC'
- 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
- 'DIDR0' : '$77', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', # ADC7 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR1' : '$78', # Digital Input Disable Register
- 'DIDR1_ACMP1MD': '$8', #
- 'DIDR1_AMP0POSD': '$4', #
- 'DIDR1_ADC10D': '$2', #
- 'DIDR1_ADC9D': '$1', #
- 'AMP0CSR' : '$79', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMP0GS': '$8', #
- 'AMP0CSR_AMP0TS': '$3', #
-
-# Module ANALOG_COMPARATOR
- 'AC3CON' : '$7f', # Analog Comparator3 Control Reg
- 'AC3CON_AC3EN': '$80', # Analog Comparator3 Enable Bit
- 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3OEA': '$8', # Analog Comparator 3 Alternate
- 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
- 'AC1CON' : '$7d', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$7e', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'ACSR' : '$20', # Analog Comparator Status Regis
- 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'AC3ECON' : '$7c', #
- 'AC3ECON_AC3OI': '$20', # Analog Comparator Ouput Invert
- 'AC3ECON_AC3OE': '$10', # Analog Comparator Ouput Enable
- 'AC3ECON_AC3H': '$7', # Analog Comparator Hysteresis S
- 'AC2ECON' : '$7b', #
- 'AC2ECON_AC2OI': '$20', # Analog Comparator Ouput Invert
- 'AC2ECON_AC2OE': '$10', # Analog Comparator Ouput Enable
- 'AC2ECON_AC2H': '$7', # Analog Comparator Hysteresis S
- 'AC1ECON' : '$7a', #
- 'AC1ECON_AC1OI': '$20', # Analog Comparator Ouput Invert
- 'AC1ECON_AC1OE': '$10', # Analog Comparator Ouput Enable
- 'AC1ECON_AC1ICE': '$8', # Analog Comparator Interrupt Ca
- 'AC1ECON_AC1H': '$7', # Analog Comparator Hysteresis S
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_RSTDIS': '$8', # Reset Pin Disable
- 'MCUCR_CKRC81': '$4', # Frequency Selection of the Cal
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$88', # Oscillator Calibration Value
- 'CLKPR' : '$83', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$3b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$3a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$39', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$87', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$3c', #
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$86', # Power Reduction Register
- 'PRR_PRPSC2': '$80', # Power Reduction PSC2
- 'PRR_PRPSCR': '$20', # Power Reduction PSC0
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'CLKCSR' : '$84', #
- 'CLKCSR_CLKCCE': '$80', # Clock Control Change Enable
- 'CLKCSR_CLKRDY': '$10', # Clock Ready Flag
- 'CLKCSR_CLKC': '$f', # Clock Control
- 'CLKSELR' : '$85', #
- 'CLKSELR_COUT': '$40', # Clock OUT
- 'CLKSELR_CSUT': '$30', # Clock Start up Time
- 'CLKSELR_CKSEL': '$f', # Clock Source Select
- 'BGCCR' : '$81', # BandGap Current Calibration Re
- 'BGCCR_BGCC': '$f', #
- 'BGCRR' : '$80', # BandGap Resistor Calibration R
- 'BGCRR_BGCR': '$f', #
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_NVMBSY': '$80', # None Volatile Busy Memory Busy
- 'EECR_EEPAGE': '$40', # EEPROM Page Access
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC0
- 'PICR0' : '$68', # PSC 0 Input Capture Register
- 'PFRC0B' : '$63', # PSC 0 Input B Control
- 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
- 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
- 'PFRC0A' : '$62', # PSC 0 Input A Control
- 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
- 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
- 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
- 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
- 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
- 'PCTL0' : '$32', # PSC 0 Control Register
- 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
- 'PCTL0_PBFM0': '$24', # PSC 0 Balance Flank Width Modu
- 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
- 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
- 'PCTL0_PRUN0': '$1', # PSC 0 Run
- 'PCNF0' : '$31', # PSC 0 Configuration Register
- 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
- 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
- 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
- 'PCNF0_PMODE0': '$18', # PSC 0 Mode
- 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
- 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
- 'OCR0RB' : '$44', # Output Compare RB Register
- 'OCR0SB' : '$42', # Output Compare SB Register
- 'OCR0RA' : '$4a', # Output Compare RA Register
- 'OCR0SA' : '$60', # Output Compare SA Register
- 'PSOC0' : '$6a', # PSC0 Synchro and Output Config
- 'PSOC0_PISEL0A1': '$80', # PSC Input Select
- 'PSOC0_PISEL0B1': '$40', # PSC Input Select
- 'PSOC0_PSYNC0': '$30', # Synchronisation out for ADC se
- 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
- 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
- 'PIM0' : '$2f', # PSC0 Interrupt Mask Register
- 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
- 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
- 'PIM0_PEOEPE0': '$2', # End of Enhanced Cycle Enable
- 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
- 'PIFR0' : '$30', # PSC0 Interrupt Flag Register
- 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
- 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
- 'PIFR0_PEV0B': '$10', # External Event B Interrupt
- 'PIFR0_PEV0A': '$8', # External Event A Interrupt
- 'PIFR0_PRN0': '$6', # Ramp Number
- 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
-
-# Module PSC2
- 'PICR2H' : '$6d', # PSC 2 Input Capture Register H
- 'PICR2H_PCST2': '$80', # PSC 2 Capture Software Trigger
- 'PICR2H_PICR21': '$c', #
- 'PICR2H_PICR2': '$3', #
- 'PICR2L' : '$6c', # PSC 2 Input Capture Register L
- 'PFRC2B' : '$67', # PSC 2 Input B Control
- 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
- 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
- 'PFRC2A' : '$66', # PSC 2 Input B Control
- 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
- 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
- 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
- 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
- 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
- 'PCTL2' : '$36', # PSC 2 Control Register
- 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
- 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
- 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
- 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
- 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
- 'PCTL2_PRUN2': '$1', # PSC 2 Run
- 'PCNF2' : '$35', # PSC 2 Configuration Register
- 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
- 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
- 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
- 'PCNF2_PMODE2': '$18', # PSC 2 Mode
- 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
- 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
- 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
- 'PCNFE2' : '$70', # PSC 2 Enhanced Configuration R
- 'PCNFE2_PASDLK2': '$e0', #
- 'PCNFE2_PBFM21': '$10', #
- 'PCNFE2_PELEV2A1': '$8', #
- 'PCNFE2_PELEV2B1': '$4', #
- 'PCNFE2_PISEL2A1': '$2', #
- 'PCNFE2_PISEL2B1': '$1', #
- 'OCR2RB' : '$48', # Output Compare RB Register
- 'OCR2SB' : '$46', # Output Compare SB Register
- 'OCR2RA' : '$4e', # Output Compare RA Register
- 'OCR2SA' : '$64', # Output Compare SA Register
- 'POM2' : '$6f', # PSC 2 Output Matrix
- 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
- 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
- 'PSOC2' : '$6e', # PSC2 Synchro and Output Config
- 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
- 'PSOC2_PSYNC2': '$30', # Synchronization Out for ADC Se
- 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
- 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
- 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
- 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
- 'PIM2' : '$33', # PSC2 Interrupt Mask Register
- 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
- 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
- 'PIM2_PEOEPE2': '$2', # End of Enhanced Cycle Interrup
- 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
- 'PIFR2' : '$34', # PSC2 Interrupt Flag Register
- 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
- 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
- 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
- 'PIFR2_PEV2B': '$10', # External Event B Interrupt
- 'PIFR2_PEV2A': '$8', # External Event A Interrupt
- 'PIFR2_PRN2': '$6', # Ramp Number
- 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
- 'PASDLY2' : '$71', # Analog Synchronization Delay R
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$21', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$22', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1B' : '$8a', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM13': '$10', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCNT1' : '$5a', # Timer/Counter1 Bytes
- 'ICR1' : '$8c', # Timer/Counter1 Input Capture R
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt b/amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt
deleted file mode 100644
index 850e5e7..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt
+++ /dev/null
@@ -1,486 +0,0 @@
-\ Partname: AT90USB1286
-\ generated automatically
-
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ USB_DEVICE
-&244 constant UEINT \
-&243 constant UEBCHX \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $7F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_LSM \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_GLOBAL
-&218 constant USBINT \
- $02 constant USBINT_IDTI \
- $01 constant USBINT_VBUSTI \
-&217 constant USBSTA \
- $08 constant USBSTA_SPEED \
- $02 constant USBSTA_ID \
- $01 constant USBSTA_VBUS \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $40 constant USBCON_HOST \
- $20 constant USBCON_FRZCLK \
- $10 constant USBCON_OTGPADE \
- $02 constant USBCON_IDTE \
- $01 constant USBCON_VBUSTE \
-&215 constant UHWCON \ USB Hardware Configuration Register
- $80 constant UHWCON_UIMOD \
- $40 constant UHWCON_UIDE \
- $10 constant UHWCON_UVCONE \
- $01 constant UHWCON_UVREGE \
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant USB_GENAddr \ USB General Interrupt Request
-&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART1__RXAddr \ USART1, Rx Complete
-&52 constant USART1__UDREAddr \ USART1 Data register Empty
-&54 constant USART1__TXAddr \ USART1, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant TWIAddr \ 2-wire Serial Interface
-&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb1286/device.asm b/amforth-6.5/avr8/devices/at90usb1286/device.asm
deleted file mode 100644
index 74159f0..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/device.asm
+++ /dev/null
@@ -1,145 +0,0 @@
-; Partname: AT90USB1286
-; generated automatically, do not edit
-
-.nolist
- .include "usb1286def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_WATCHDOG = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_CPU = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_USART1 = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PLL = 0
-.set WANT_USB_GLOBAL = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; USB General Interrupt Request
-.org 22
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART1, Rx Complete
-.org 52
- rcall isr ; USART1 Data register Empty
-.org 54
- rcall isr ; USART1, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; 2-wire Serial Interface
-.org 74
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 38
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 38
-mcu_name:
- .dw 11
- .db "AT90USB1286",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb1286/device.inc b/amforth-6.5/avr8/devices/at90usb1286/device.inc
deleted file mode 100644
index dd2e63c..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/device.inc
+++ /dev/null
@@ -1,1611 +0,0 @@
-; Partname: AT90USB1286
-; generated automatically, no not edit
-
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_GLOBAL == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; USB Hardware Configuration Register
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw 215
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90usb1286/device.py b/amforth-6.5/avr8/devices/at90usb1286/device.py
deleted file mode 100644
index 48ce421..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/device.py
+++ /dev/null
@@ -1,523 +0,0 @@
-# Generated Automatically
-
-# Partname AT90USB1286
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'USB_GENAddr' : '#20', # USB General Interrupt Request
- 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#50', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
- 'USART1_TXAddr' : '#54', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'TWIAddr' : '#72', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#74', # Store Program Memory Read
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCHX' : '$f3', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$7f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_LSM': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
-# Module USB_GLOBAL
- 'USBINT' : '$da', #
- 'USBINT_IDTI': '$2', #
- 'USBINT_VBUSTI': '$1', #
- 'USBSTA' : '$d9', #
- 'USBSTA_SPEED': '$8', #
- 'USBSTA_ID': '$2', #
- 'USBSTA_VBUS': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_HOST': '$40', #
- 'USBCON_FRZCLK': '$20', #
- 'USBCON_OTGPADE': '$10', #
- 'USBCON_IDTE': '$2', #
- 'USBCON_VBUSTE': '$1', #
- 'UHWCON' : '$d7', # USB Hardware Configuration Reg
- 'UHWCON_UIMOD': '$80', #
- 'UHWCON_UIDE': '$40', #
- 'UHWCON_UVCONE': '$10', #
- 'UHWCON_UVREGE': '$1', #
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt b/amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt
deleted file mode 100644
index 5cf3ed4..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt
+++ /dev/null
@@ -1,587 +0,0 @@
-\ Partname: AT90USB1287
-\ generated automatically
-
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ USB_DEVICE
-&244 constant UEINT \
-&243 constant UEBCHX \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $7F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_LSM \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-\ USB_GLOBAL
-&223 constant OTGINT \
- $20 constant OTGINT_STOI \
- $10 constant OTGINT_HNPERRI \
- $08 constant OTGINT_ROLEEXI \
- $04 constant OTGINT_BCERRI \
- $02 constant OTGINT_VBERRI \
- $01 constant OTGINT_SRPI \
-&222 constant OTGIEN \
- $20 constant OTGIEN_STOE \
- $10 constant OTGIEN_HNPERRE \
- $08 constant OTGIEN_ROLEEXE \
- $04 constant OTGIEN_BCERRE \
- $02 constant OTGIEN_VBERRE \
- $01 constant OTGIEN_SRPE \
-&221 constant OTGCON \
- $20 constant OTGCON_HNPREQ \
- $10 constant OTGCON_SRPREQ \
- $08 constant OTGCON_SRPSEL \
- $04 constant OTGCON_VBUSHWC \
- $02 constant OTGCON_VBUSREQ \
- $01 constant OTGCON_VBUSRQC \
-&249 constant OTGTCON \
- $80 constant OTGTCON_OTGTCON_7 \
- $60 constant OTGTCON_PAGE \
- $07 constant OTGTCON_VALUE_2 \
-&218 constant USBINT \
- $02 constant USBINT_IDTI \
- $01 constant USBINT_VBUSTI \
-&217 constant USBSTA \
- $08 constant USBSTA_SPEED \
- $02 constant USBSTA_ID \
- $01 constant USBSTA_VBUS \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $40 constant USBCON_HOST \
- $20 constant USBCON_FRZCLK \
- $10 constant USBCON_OTGPADE \
- $02 constant USBCON_IDTE \
- $01 constant USBCON_VBUSTE \
-&215 constant UHWCON \ USB Hardware Configuration Register
- $80 constant UHWCON_UIMOD \
- $40 constant UHWCON_UIDE \
- $10 constant UHWCON_UVCONE \
- $01 constant UHWCON_UVREGE \
-\ USB_HOST
-&245 constant UPERRX \
- $60 constant UPERRX_COUNTER \
- $10 constant UPERRX_CRC16 \
- $08 constant UPERRX_TIMEOUT \
- $04 constant UPERRX_PID \
- $02 constant UPERRX_DATAPID \
- $01 constant UPERRX_DATATGL \
-&248 constant UPINT \
-&247 constant UPBCHX \
-&246 constant UPBCLX \
-&175 constant UPDATX \
-&174 constant UPIENX \
- $80 constant UPIENX_FLERRE \
- $40 constant UPIENX_NAKEDE \
- $10 constant UPIENX_PERRE \
- $08 constant UPIENX_TXSTPE \
- $04 constant UPIENX_TXOUTE \
- $02 constant UPIENX_RXSTALLE \
- $01 constant UPIENX_RXINE \
-&173 constant UPCFG2X \
-&172 constant UPSTAX \
- $80 constant UPSTAX_CFGOK \
- $40 constant UPSTAX_OVERFI \
- $20 constant UPSTAX_UNDERFI \
- $0C constant UPSTAX_DTSEQ \
- $03 constant UPSTAX_NBUSYK \
-&171 constant UPCFG1X \
- $70 constant UPCFG1X_PSIZE \
- $0C constant UPCFG1X_PBK \
- $02 constant UPCFG1X_ALLOC \
-&170 constant UPCFG0X \
- $C0 constant UPCFG0X_PTYPE \
- $30 constant UPCFG0X_PTOKEN \
- $0F constant UPCFG0X_PEPNUM \
-&169 constant UPCONX \
- $40 constant UPCONX_PFREEZE \
- $20 constant UPCONX_INMODE \
- $08 constant UPCONX_RSTDT \
- $01 constant UPCONX_PEN \
-&168 constant UPRST \
- $7F constant UPRST_PRST \
-&167 constant UPNUM \
-&166 constant UPINTX \
- $80 constant UPINTX_FIFOCON \
- $40 constant UPINTX_NAKEDI \
- $20 constant UPINTX_RWAL \
- $10 constant UPINTX_PERRI \
- $08 constant UPINTX_TXSTPI \
- $04 constant UPINTX_TXOUTI \
- $02 constant UPINTX_RXSTALLI \
- $01 constant UPINTX_RXINI \
-&165 constant UPINRQX \
-&164 constant UHFLEN \
-&162 constant UHFNUM \
-&161 constant UHADDR \
-&160 constant UHIEN \
- $40 constant UHIEN_HWUPE \
- $20 constant UHIEN_HSOFE \
- $10 constant UHIEN_RXRSME \
- $08 constant UHIEN_RSMEDE \
- $04 constant UHIEN_RSTE \
- $02 constant UHIEN_DDISCE \
- $01 constant UHIEN_DCONNE \
-&159 constant UHINT \
- $40 constant UHINT_UHUPI \
- $20 constant UHINT_HSOFI \
- $10 constant UHINT_RXRSMI \
- $08 constant UHINT_RSMEDI \
- $04 constant UHINT_RSTI \
- $02 constant UHINT_DDISCI \
- $01 constant UHINT_DCONNI \
-&158 constant UHCON \
- $04 constant UHCON_RESUME \
- $02 constant UHCON_RESET \
- $01 constant UHCON_SOFEN \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant USB_GENAddr \ USB General Interrupt Request
-&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART1__RXAddr \ USART1, Rx Complete
-&52 constant USART1__UDREAddr \ USART1 Data register Empty
-&54 constant USART1__TXAddr \ USART1, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant TWIAddr \ 2-wire Serial Interface
-&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb1287/device.asm b/amforth-6.5/avr8/devices/at90usb1287/device.asm
deleted file mode 100644
index 496a474..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/device.asm
+++ /dev/null
@@ -1,146 +0,0 @@
-; Partname: AT90USB1287
-; generated automatically, do not edit
-
-.nolist
- .include "usb1287def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_WATCHDOG = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_CPU = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_USART1 = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_USB_GLOBAL = 0
-.set WANT_USB_HOST = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PLL = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; USB General Interrupt Request
-.org 22
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART1, Rx Complete
-.org 52
- rcall isr ; USART1 Data register Empty
-.org 54
- rcall isr ; USART1, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; 2-wire Serial Interface
-.org 74
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 38
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 38
-mcu_name:
- .dw 11
- .db "AT90USB1287",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb1287/device.inc b/amforth-6.5/avr8/devices/at90usb1287/device.inc
deleted file mode 100644
index 7772255..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/device.inc
+++ /dev/null
@@ -1,1914 +0,0 @@
-; Partname: AT90USB1287
-; generated automatically, no not edit
-
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-
-.endif
-.if WANT_USB_GLOBAL == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGINT:
- .dw $ff06
- .db "OTGINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGINT
-XT_OTGINT:
- .dw PFA_DOVARIABLE
-PFA_OTGINT:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGIEN:
- .dw $ff06
- .db "OTGIEN"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGIEN
-XT_OTGIEN:
- .dw PFA_DOVARIABLE
-PFA_OTGIEN:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGCON:
- .dw $ff06
- .db "OTGCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGCON
-XT_OTGCON:
- .dw PFA_DOVARIABLE
-PFA_OTGCON:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGTCON:
- .dw $ff07
- .db "OTGTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGTCON
-XT_OTGTCON:
- .dw PFA_DOVARIABLE
-PFA_OTGTCON:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; USB Hardware Configuration Register
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw 215
-
-.endif
-.if WANT_USB_HOST == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPERRX:
- .dw $ff06
- .db "UPERRX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPERRX
-XT_UPERRX:
- .dw PFA_DOVARIABLE
-PFA_UPERRX:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINT:
- .dw $ff05
- .db "UPINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINT
-XT_UPINT:
- .dw PFA_DOVARIABLE
-PFA_UPINT:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPBCHX:
- .dw $ff06
- .db "UPBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPBCHX
-XT_UPBCHX:
- .dw PFA_DOVARIABLE
-PFA_UPBCHX:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPBCLX:
- .dw $ff06
- .db "UPBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPBCLX
-XT_UPBCLX:
- .dw PFA_DOVARIABLE
-PFA_UPBCLX:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPDATX:
- .dw $ff06
- .db "UPDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPDATX
-XT_UPDATX:
- .dw PFA_DOVARIABLE
-PFA_UPDATX:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPIENX:
- .dw $ff06
- .db "UPIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPIENX
-XT_UPIENX:
- .dw PFA_DOVARIABLE
-PFA_UPIENX:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG2X:
- .dw $ff07
- .db "UPCFG2X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG2X
-XT_UPCFG2X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG2X:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPSTAX:
- .dw $ff06
- .db "UPSTAX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPSTAX
-XT_UPSTAX:
- .dw PFA_DOVARIABLE
-PFA_UPSTAX:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG1X:
- .dw $ff07
- .db "UPCFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG1X
-XT_UPCFG1X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG1X:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG0X:
- .dw $ff07
- .db "UPCFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG0X
-XT_UPCFG0X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG0X:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCONX:
- .dw $ff06
- .db "UPCONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCONX
-XT_UPCONX:
- .dw PFA_DOVARIABLE
-PFA_UPCONX:
- .dw 169
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPRST:
- .dw $ff05
- .db "UPRST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPRST
-XT_UPRST:
- .dw PFA_DOVARIABLE
-PFA_UPRST:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPNUM:
- .dw $ff05
- .db "UPNUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPNUM
-XT_UPNUM:
- .dw PFA_DOVARIABLE
-PFA_UPNUM:
- .dw 167
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINTX:
- .dw $ff06
- .db "UPINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINTX
-XT_UPINTX:
- .dw PFA_DOVARIABLE
-PFA_UPINTX:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINRQX:
- .dw $ff07
- .db "UPINRQX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINRQX
-XT_UPINRQX:
- .dw PFA_DOVARIABLE
-PFA_UPINRQX:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHFLEN:
- .dw $ff06
- .db "UHFLEN"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHFLEN
-XT_UHFLEN:
- .dw PFA_DOVARIABLE
-PFA_UHFLEN:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHFNUM:
- .dw $ff06
- .db "UHFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHFNUM
-XT_UHFNUM:
- .dw PFA_DOVARIABLE
-PFA_UHFNUM:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHADDR:
- .dw $ff06
- .db "UHADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHADDR
-XT_UHADDR:
- .dw PFA_DOVARIABLE
-PFA_UHADDR:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHIEN:
- .dw $ff05
- .db "UHIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHIEN
-XT_UHIEN:
- .dw PFA_DOVARIABLE
-PFA_UHIEN:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHINT:
- .dw $ff05
- .db "UHINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHINT
-XT_UHINT:
- .dw PFA_DOVARIABLE
-PFA_UHINT:
- .dw 159
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHCON:
- .dw $ff05
- .db "UHCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHCON
-XT_UHCON:
- .dw PFA_DOVARIABLE
-PFA_UHCON:
- .dw 158
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90usb1287/device.py b/amforth-6.5/avr8/devices/at90usb1287/device.py
deleted file mode 100644
index bae6439..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/device.py
+++ /dev/null
@@ -1,625 +0,0 @@
-# Generated Automatically
-
-# Partname AT90USB1287
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'USB_GENAddr' : '#20', # USB General Interrupt Request
- 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#50', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
- 'USART1_TXAddr' : '#54', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'TWIAddr' : '#72', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#74', # Store Program Memory Read
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCHX' : '$f3', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$7f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_LSM': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
-
-# Module USB_GLOBAL
- 'OTGINT' : '$df', #
- 'OTGINT_STOI': '$20', #
- 'OTGINT_HNPERRI': '$10', #
- 'OTGINT_ROLEEXI': '$8', #
- 'OTGINT_BCERRI': '$4', #
- 'OTGINT_VBERRI': '$2', #
- 'OTGINT_SRPI': '$1', #
- 'OTGIEN' : '$de', #
- 'OTGIEN_STOE': '$20', #
- 'OTGIEN_HNPERRE': '$10', #
- 'OTGIEN_ROLEEXE': '$8', #
- 'OTGIEN_BCERRE': '$4', #
- 'OTGIEN_VBERRE': '$2', #
- 'OTGIEN_SRPE': '$1', #
- 'OTGCON' : '$dd', #
- 'OTGCON_HNPREQ': '$20', #
- 'OTGCON_SRPREQ': '$10', #
- 'OTGCON_SRPSEL': '$8', #
- 'OTGCON_VBUSHWC': '$4', #
- 'OTGCON_VBUSREQ': '$2', #
- 'OTGCON_VBUSRQC': '$1', #
- 'OTGTCON' : '$f9', #
- 'OTGTCON_OTGTCON_7': '$80', #
- 'OTGTCON_PAGE': '$60', #
- 'OTGTCON_VALUE_2': '$7', #
- 'USBINT' : '$da', #
- 'USBINT_IDTI': '$2', #
- 'USBINT_VBUSTI': '$1', #
- 'USBSTA' : '$d9', #
- 'USBSTA_SPEED': '$8', #
- 'USBSTA_ID': '$2', #
- 'USBSTA_VBUS': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_HOST': '$40', #
- 'USBCON_FRZCLK': '$20', #
- 'USBCON_OTGPADE': '$10', #
- 'USBCON_IDTE': '$2', #
- 'USBCON_VBUSTE': '$1', #
- 'UHWCON' : '$d7', # USB Hardware Configuration Reg
- 'UHWCON_UIMOD': '$80', #
- 'UHWCON_UIDE': '$40', #
- 'UHWCON_UVCONE': '$10', #
- 'UHWCON_UVREGE': '$1', #
-
-# Module USB_HOST
- 'UPERRX' : '$f5', #
- 'UPERRX_COUNTER': '$60', #
- 'UPERRX_CRC16': '$10', #
- 'UPERRX_TIMEOUT': '$8', #
- 'UPERRX_PID': '$4', #
- 'UPERRX_DATAPID': '$2', #
- 'UPERRX_DATATGL': '$1', #
- 'UPINT' : '$f8', #
- 'UPBCHX' : '$f7', #
- 'UPBCLX' : '$f6', #
- 'UPDATX' : '$af', #
- 'UPIENX' : '$ae', #
- 'UPIENX_FLERRE': '$80', #
- 'UPIENX_NAKEDE': '$40', #
- 'UPIENX_PERRE': '$10', #
- 'UPIENX_TXSTPE': '$8', #
- 'UPIENX_TXOUTE': '$4', #
- 'UPIENX_RXSTALLE': '$2', #
- 'UPIENX_RXINE': '$1', #
- 'UPCFG2X' : '$ad', #
- 'UPSTAX' : '$ac', #
- 'UPSTAX_CFGOK': '$80', #
- 'UPSTAX_OVERFI': '$40', #
- 'UPSTAX_UNDERFI': '$20', #
- 'UPSTAX_DTSEQ': '$c', #
- 'UPSTAX_NBUSYK': '$3', #
- 'UPCFG1X' : '$ab', #
- 'UPCFG1X_PSIZE': '$70', #
- 'UPCFG1X_PBK': '$c', #
- 'UPCFG1X_ALLOC': '$2', #
- 'UPCFG0X' : '$aa', #
- 'UPCFG0X_PTYPE': '$c0', #
- 'UPCFG0X_PTOKEN': '$30', #
- 'UPCFG0X_PEPNUM': '$f', #
- 'UPCONX' : '$a9', #
- 'UPCONX_PFREEZE': '$40', #
- 'UPCONX_INMODE': '$20', #
- 'UPCONX_RSTDT': '$8', #
- 'UPCONX_PEN': '$1', #
- 'UPRST' : '$a8', #
- 'UPRST_PRST': '$7f', #
- 'UPNUM' : '$a7', #
- 'UPINTX' : '$a6', #
- 'UPINTX_FIFOCON': '$80', #
- 'UPINTX_NAKEDI': '$40', #
- 'UPINTX_RWAL': '$20', #
- 'UPINTX_PERRI': '$10', #
- 'UPINTX_TXSTPI': '$8', #
- 'UPINTX_TXOUTI': '$4', #
- 'UPINTX_RXSTALLI': '$2', #
- 'UPINTX_RXINI': '$1', #
- 'UPINRQX' : '$a5', #
- 'UHFLEN' : '$a4', #
- 'UHFNUM' : '$a2', #
- 'UHADDR' : '$a1', #
- 'UHIEN' : '$a0', #
- 'UHIEN_HWUPE': '$40', #
- 'UHIEN_HSOFE': '$20', #
- 'UHIEN_RXRSME': '$10', #
- 'UHIEN_RSMEDE': '$8', #
- 'UHIEN_RSTE': '$4', #
- 'UHIEN_DDISCE': '$2', #
- 'UHIEN_DCONNE': '$1', #
- 'UHINT' : '$9f', #
- 'UHINT_UHUPI': '$40', #
- 'UHINT_HSOFI': '$20', #
- 'UHINT_RXRSMI': '$10', #
- 'UHINT_RSMEDI': '$8', #
- 'UHINT_RSTI': '$4', #
- 'UHINT_DDISCI': '$2', #
- 'UHINT_DCONNI': '$1', #
- 'UHCON' : '$9e', #
- 'UHCON_RESUME': '$4', #
- 'UHCON_RESET': '$2', #
- 'UHCON_SOFEN': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb162/at90usb162.frt b/amforth-6.5/avr8/devices/at90usb162/at90usb162.frt
deleted file mode 100644
index a17ffca..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/at90usb162.frt
+++ /dev/null
@@ -1,367 +0,0 @@
-\ Partname: AT90USB162
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_DEVICE
-&244 constant UEINT \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $1F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
-&99 constant REGCR \ Regulator Control Register
- $01 constant REGCR_REGDIS \
-\ PS2
-&251 constant UPOE \
- $C0 constant UPOE_UPWE \
- $30 constant UPOE_UPDRV \
- $08 constant UPOE_SCKI \
- $04 constant UPOE_DATAI \
- $02 constant UPOE_DPI \
- $01 constant UPOE_DMI \
-&250 constant PS2CON \ PS2 Pad Enable register
- $01 constant PS2CON_PS2EN \ Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $20 constant MCUSR_USBRF \ USB reset flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
-&210 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&209 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&208 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-&81 constant DWDR \ debugWire communication register
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $1F constant PCMSK1_PCINT \
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&203 constant UCSR1D \ USART Control and Status Register D
- $02 constant UCSR1D_CTSEN \ CTS Enable
- $01 constant UCSR1D_RTSEN \ RTS Enable
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-&98 constant WDTCKD \ Watchdog Timer Clock Divider
- $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
- $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
- $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTC
-&40 constant PORTC \ Port C Data Register
- $F0 constant PORTC_PORTC \ Port C Data Register bits
- $07 constant PORTC_PORTC \ Port C Data Register bits
-&39 constant DDRC \ Port C Data Direction Register
- $F0 constant DDRC_DDC \ Port C Data Direction Register bits
- $07 constant DDRC_DDC \ Port C Data Direction Register bits
-&38 constant PINC \ Port C Input Pins
- $F0 constant PINC_PINC \ Port C Input Pins bits
- $07 constant PINC_PINC \ Port C Input Pins bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant USB_GENAddr \ USB General Interrupt Request
-&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&26 constant WDTAddr \ Watchdog Time-out Interrupt
-&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
-&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
-&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
-&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
-&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&46 constant USART1__RXAddr \ USART1, Rx Complete
-&48 constant USART1__UDREAddr \ USART1 Data register Empty
-&50 constant USART1__TXAddr \ USART1, Tx Complete
-&52 constant ANALOG_COMPAddr \ Analog Comparator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb162/device.asm b/amforth-6.5/avr8/devices/at90usb162/device.asm
deleted file mode 100644
index 2cb7d4b..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: AT90USB162
-; generated automatically, do not edit
-
-.nolist
- .include "usb162def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_PS2 = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTC = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; USB General Interrupt Request
-.org 24
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 26
- rcall isr ; Watchdog Time-out Interrupt
-.org 28
- rcall isr ; Timer/Counter2 Capture Event
-.org 30
- rcall isr ; Timer/Counter2 Compare Match B
-.org 32
- rcall isr ; Timer/Counter2 Compare Match B
-.org 34
- rcall isr ; Timer/Counter2 Compare Match C
-.org 36
- rcall isr ; Timer/Counter1 Overflow
-.org 38
- rcall isr ; Timer/Counter0 Compare Match A
-.org 40
- rcall isr ; Timer/Counter0 Compare Match B
-.org 42
- rcall isr ; Timer/Counter0 Overflow
-.org 44
- rcall isr ; SPI Serial Transfer Complete
-.org 46
- rcall isr ; USART1, Rx Complete
-.org 48
- rcall isr ; USART1 Data register Empty
-.org 50
- rcall isr ; USART1, Tx Complete
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 10
- .db "AT90USB162"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb162/device.inc b/amforth-6.5/avr8/devices/at90usb162/device.inc
deleted file mode 100644
index 97b1bc3..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/device.inc
+++ /dev/null
@@ -1,1155 +0,0 @@
-; Partname: AT90USB162
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Control Register
-VE_REGCR:
- .dw $ff05
- .db "REGCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_REGCR
-XT_REGCR:
- .dw PFA_DOVARIABLE
-PFA_REGCR:
- .dw 99
-
-.endif
-.if WANT_PS2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPOE:
- .dw $ff04
- .db "UPOE"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPOE
-XT_UPOE:
- .dw PFA_DOVARIABLE
-PFA_UPOE:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PS2 Pad Enable register
-VE_PS2CON:
- .dw $ff06
- .db "PS2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_PS2CON
-XT_PS2CON:
- .dw PFA_DOVARIABLE
-PFA_PS2CON:
- .dw 250
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; debugWire communication register
-VE_DWDR:
- .dw $ff04
- .db "DWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_DWDR
-XT_DWDR:
- .dw PFA_DOVARIABLE
-PFA_DWDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register D
-VE_UCSR1D:
- .dw $ff06
- .db "UCSR1D"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1D
-XT_UCSR1D:
- .dw PFA_DOVARIABLE
-PFA_UCSR1D:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Clock Divider
-VE_WDTCKD:
- .dw $ff06
- .db "WDTCKD"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCKD
-XT_WDTCKD:
- .dw PFA_DOVARIABLE
-PFA_WDTCKD:
- .dw 98
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90usb162/device.py b/amforth-6.5/avr8/devices/at90usb162/device.py
deleted file mode 100644
index 5787585..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/device.py
+++ /dev/null
@@ -1,387 +0,0 @@
-# Generated Automatically
-
-# Partname AT90USB162
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'USB_GENAddr' : '#22', # USB General Interrupt Request
- 'USB_COMAddr' : '#24', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#26', # Watchdog Time-out Interrupt
- 'TIMER1_CAPTAddr' : '#28', # Timer/Counter2 Capture Event
- 'TIMER1_COMPAAddr' : '#30', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPBAddr' : '#32', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPCAddr' : '#34', # Timer/Counter2 Compare Match C
- 'TIMER1_OVFAddr' : '#36', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#38', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#40', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#42', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#44', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#46', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#48', # USART1 Data register Empty
- 'USART1_TXAddr' : '#50', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#52', # Analog Comparator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPM_READYAddr' : '#56', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$1f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_RSTCPU': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_FRZCLK': '$20', #
- 'REGCR' : '$63', # Regulator Control Register
- 'REGCR_REGDIS': '$1', #
-
-# Module PS2
- 'UPOE' : '$fb', #
- 'UPOE_UPWE': '$c0', #
- 'UPOE_UPDRV': '$30', #
- 'UPOE_SCKI': '$8', #
- 'UPOE_DATAI': '$4', #
- 'UPOE_DPI': '$2', #
- 'UPOE_DMI': '$1', #
- 'PS2CON' : '$fa', # PS2 Pad Enable register
- 'PS2CON_PS2EN': '$1', # Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_USBRF': '$20', # USB reset flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'CLKSTA' : '$d2', #
- 'CLKSTA_RCON': '$2', #
- 'CLKSTA_EXTON': '$1', #
- 'CLKSEL1' : '$d1', #
- 'CLKSEL1_RCCKSEL': '$f0', #
- 'CLKSEL1_EXCKSEL': '$f', #
- 'CLKSEL0' : '$d0', #
- 'CLKSEL0_RCSUT': '$c0', #
- 'CLKSEL0_EXSUT': '$30', #
- 'CLKSEL0_RCE': '$8', #
- 'CLKSEL0_EXTE': '$4', #
- 'CLKSEL0_CLKS': '$1', #
- 'DWDR' : '$51', # debugWire communication regist
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$1f', #
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UCSR1D' : '$cb', # USART Control and Status Regis
- 'UCSR1D_CTSEN': '$2', # CTS Enable
- 'UCSR1D_RTSEN': '$1', # RTS Enable
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
- 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
- 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
- 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
- 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PORTC_PORTC': '$f0', # Port C Data Register bits
- 'PORTC_PORTC': '$7', # Port C Data Register bits
- 'DDRC' : '$27', # Port C Data Direction Register
- 'DDRC_DDC': '$f0', # Port C Data Direction Register
- 'DDRC_DDC': '$7', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
- 'PINC_PINC': '$f0', # Port C Input Pins bits
- 'PINC_PINC': '$7', # Port C Input Pins bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb162/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb162/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90usb162/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb646/at90usb646.frt b/amforth-6.5/avr8/devices/at90usb646/at90usb646.frt
deleted file mode 100644
index 0f1b47c..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/at90usb646.frt
+++ /dev/null
@@ -1,587 +0,0 @@
-\ Partname: AT90USB646
-\ generated automatically
-
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ USB_DEVICE
-&244 constant UEINT \
-&243 constant UEBCHX \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $7F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_LSM \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-\ USB_GLOBAL
-&223 constant OTGINT \
- $20 constant OTGINT_STOI \
- $10 constant OTGINT_HNPERRI \
- $08 constant OTGINT_ROLEEXI \
- $04 constant OTGINT_BCERRI \
- $02 constant OTGINT_VBERRI \
- $01 constant OTGINT_SRPI \
-&222 constant OTGIEN \
- $20 constant OTGIEN_STOE \
- $10 constant OTGIEN_HNPERRE \
- $08 constant OTGIEN_ROLEEXE \
- $04 constant OTGIEN_BCERRE \
- $02 constant OTGIEN_VBERRE \
- $01 constant OTGIEN_SRPE \
-&221 constant OTGCON \
- $20 constant OTGCON_HNPREQ \
- $10 constant OTGCON_SRPREQ \
- $08 constant OTGCON_SRPSEL \
- $04 constant OTGCON_VBUSHWC \
- $02 constant OTGCON_VBUSREQ \
- $01 constant OTGCON_VBUSRQC \
-&249 constant OTGTCON \
- $80 constant OTGTCON_OTGTCON_7 \
- $60 constant OTGTCON_PAGE \
- $07 constant OTGTCON_VALUE_2 \
-&218 constant USBINT \
- $02 constant USBINT_IDTI \
- $01 constant USBINT_VBUSTI \
-&217 constant USBSTA \
- $08 constant USBSTA_SPEED \
- $02 constant USBSTA_ID \
- $01 constant USBSTA_VBUS \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $40 constant USBCON_HOST \
- $20 constant USBCON_FRZCLK \
- $10 constant USBCON_OTGPADE \
- $02 constant USBCON_IDTE \
- $01 constant USBCON_VBUSTE \
-&215 constant UHWCON \ USB Hardware Configuration Register
- $80 constant UHWCON_UIMOD \
- $40 constant UHWCON_UIDE \
- $10 constant UHWCON_UVCONE \
- $01 constant UHWCON_UVREGE \
-\ USB_HOST
-&245 constant UPERRX \
- $60 constant UPERRX_COUNTER \
- $10 constant UPERRX_CRC16 \
- $08 constant UPERRX_TIMEOUT \
- $04 constant UPERRX_PID \
- $02 constant UPERRX_DATAPID \
- $01 constant UPERRX_DATATGL \
-&248 constant UPINT \
-&247 constant UPBCHX \
-&246 constant UPBCLX \
-&175 constant UPDATX \
-&174 constant UPIENX \
- $80 constant UPIENX_FLERRE \
- $40 constant UPIENX_NAKEDE \
- $10 constant UPIENX_PERRE \
- $08 constant UPIENX_TXSTPE \
- $04 constant UPIENX_TXOUTE \
- $02 constant UPIENX_RXSTALLE \
- $01 constant UPIENX_RXINE \
-&173 constant UPCFG2X \
-&172 constant UPSTAX \
- $80 constant UPSTAX_CFGOK \
- $40 constant UPSTAX_OVERFI \
- $20 constant UPSTAX_UNDERFI \
- $0C constant UPSTAX_DTSEQ \
- $03 constant UPSTAX_NBUSYK \
-&171 constant UPCFG1X \
- $70 constant UPCFG1X_PSIZE \
- $0C constant UPCFG1X_PBK \
- $02 constant UPCFG1X_ALLOC \
-&170 constant UPCFG0X \
- $C0 constant UPCFG0X_PTYPE \
- $30 constant UPCFG0X_PTOKEN \
- $0F constant UPCFG0X_PEPNUM \
-&169 constant UPCONX \
- $40 constant UPCONX_PFREEZE \
- $20 constant UPCONX_INMODE \
- $08 constant UPCONX_RSTDT \
- $01 constant UPCONX_PEN \
-&168 constant UPRST \
- $7F constant UPRST_PRST \
-&167 constant UPNUM \
-&166 constant UPINTX \
- $80 constant UPINTX_FIFOCON \
- $40 constant UPINTX_NAKEDI \
- $20 constant UPINTX_RWAL \
- $10 constant UPINTX_PERRI \
- $08 constant UPINTX_TXSTPI \
- $04 constant UPINTX_TXOUTI \
- $02 constant UPINTX_RXSTALLI \
- $01 constant UPINTX_RXINI \
-&165 constant UPINRQX \
-&164 constant UHFLEN \
-&162 constant UHFNUM \
-&161 constant UHADDR \
-&160 constant UHIEN \
- $40 constant UHIEN_HWUPE \
- $20 constant UHIEN_HSOFE \
- $10 constant UHIEN_RXRSME \
- $08 constant UHIEN_RSMEDE \
- $04 constant UHIEN_RSTE \
- $02 constant UHIEN_DDISCE \
- $01 constant UHIEN_DCONNE \
-&159 constant UHINT \
- $40 constant UHINT_UHUPI \
- $20 constant UHINT_HSOFI \
- $10 constant UHINT_RXRSMI \
- $08 constant UHINT_RSMEDI \
- $04 constant UHINT_RSTI \
- $02 constant UHINT_DDISCI \
- $01 constant UHINT_DCONNI \
-&158 constant UHCON \
- $04 constant UHCON_RESUME \
- $02 constant UHCON_RESET \
- $01 constant UHCON_SOFEN \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant USB_GENAddr \ USB General Interrupt Request
-&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART1__RXAddr \ USART1, Rx Complete
-&52 constant USART1__UDREAddr \ USART1 Data register Empty
-&54 constant USART1__TXAddr \ USART1, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant TWIAddr \ 2-wire Serial Interface
-&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb646/device.asm b/amforth-6.5/avr8/devices/at90usb646/device.asm
deleted file mode 100644
index f088ca3..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/device.asm
+++ /dev/null
@@ -1,140 +0,0 @@
-; Partname: AT90USB646
-; generated automatically, do not edit
-
-.nolist
- .include "usb646def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_WATCHDOG = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_CPU = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_USART1 = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_USB_GLOBAL = 0
-.set WANT_USB_HOST = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PLL = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; USB General Interrupt Request
-.org 22
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART1, Rx Complete
-.org 52
- rcall isr ; USART1 Data register Empty
-.org 54
- rcall isr ; USART1, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; 2-wire Serial Interface
-.org 74
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 38
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 38
-mcu_name:
- .dw 10
- .db "AT90USB646"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb646/device.inc b/amforth-6.5/avr8/devices/at90usb646/device.inc
deleted file mode 100644
index 7a90f23..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/device.inc
+++ /dev/null
@@ -1,1914 +0,0 @@
-; Partname: AT90USB646
-; generated automatically, no not edit
-
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-
-.endif
-.if WANT_USB_GLOBAL == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGINT:
- .dw $ff06
- .db "OTGINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGINT
-XT_OTGINT:
- .dw PFA_DOVARIABLE
-PFA_OTGINT:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGIEN:
- .dw $ff06
- .db "OTGIEN"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGIEN
-XT_OTGIEN:
- .dw PFA_DOVARIABLE
-PFA_OTGIEN:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGCON:
- .dw $ff06
- .db "OTGCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGCON
-XT_OTGCON:
- .dw PFA_DOVARIABLE
-PFA_OTGCON:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGTCON:
- .dw $ff07
- .db "OTGTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGTCON
-XT_OTGTCON:
- .dw PFA_DOVARIABLE
-PFA_OTGTCON:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; USB Hardware Configuration Register
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw 215
-
-.endif
-.if WANT_USB_HOST == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPERRX:
- .dw $ff06
- .db "UPERRX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPERRX
-XT_UPERRX:
- .dw PFA_DOVARIABLE
-PFA_UPERRX:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINT:
- .dw $ff05
- .db "UPINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINT
-XT_UPINT:
- .dw PFA_DOVARIABLE
-PFA_UPINT:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPBCHX:
- .dw $ff06
- .db "UPBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPBCHX
-XT_UPBCHX:
- .dw PFA_DOVARIABLE
-PFA_UPBCHX:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPBCLX:
- .dw $ff06
- .db "UPBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPBCLX
-XT_UPBCLX:
- .dw PFA_DOVARIABLE
-PFA_UPBCLX:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPDATX:
- .dw $ff06
- .db "UPDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPDATX
-XT_UPDATX:
- .dw PFA_DOVARIABLE
-PFA_UPDATX:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPIENX:
- .dw $ff06
- .db "UPIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPIENX
-XT_UPIENX:
- .dw PFA_DOVARIABLE
-PFA_UPIENX:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG2X:
- .dw $ff07
- .db "UPCFG2X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG2X
-XT_UPCFG2X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG2X:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPSTAX:
- .dw $ff06
- .db "UPSTAX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPSTAX
-XT_UPSTAX:
- .dw PFA_DOVARIABLE
-PFA_UPSTAX:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG1X:
- .dw $ff07
- .db "UPCFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG1X
-XT_UPCFG1X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG1X:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG0X:
- .dw $ff07
- .db "UPCFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG0X
-XT_UPCFG0X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG0X:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCONX:
- .dw $ff06
- .db "UPCONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCONX
-XT_UPCONX:
- .dw PFA_DOVARIABLE
-PFA_UPCONX:
- .dw 169
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPRST:
- .dw $ff05
- .db "UPRST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPRST
-XT_UPRST:
- .dw PFA_DOVARIABLE
-PFA_UPRST:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPNUM:
- .dw $ff05
- .db "UPNUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPNUM
-XT_UPNUM:
- .dw PFA_DOVARIABLE
-PFA_UPNUM:
- .dw 167
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINTX:
- .dw $ff06
- .db "UPINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINTX
-XT_UPINTX:
- .dw PFA_DOVARIABLE
-PFA_UPINTX:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINRQX:
- .dw $ff07
- .db "UPINRQX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINRQX
-XT_UPINRQX:
- .dw PFA_DOVARIABLE
-PFA_UPINRQX:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHFLEN:
- .dw $ff06
- .db "UHFLEN"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHFLEN
-XT_UHFLEN:
- .dw PFA_DOVARIABLE
-PFA_UHFLEN:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHFNUM:
- .dw $ff06
- .db "UHFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHFNUM
-XT_UHFNUM:
- .dw PFA_DOVARIABLE
-PFA_UHFNUM:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHADDR:
- .dw $ff06
- .db "UHADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHADDR
-XT_UHADDR:
- .dw PFA_DOVARIABLE
-PFA_UHADDR:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHIEN:
- .dw $ff05
- .db "UHIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHIEN
-XT_UHIEN:
- .dw PFA_DOVARIABLE
-PFA_UHIEN:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHINT:
- .dw $ff05
- .db "UHINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHINT
-XT_UHINT:
- .dw PFA_DOVARIABLE
-PFA_UHINT:
- .dw 159
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHCON:
- .dw $ff05
- .db "UHCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHCON
-XT_UHCON:
- .dw PFA_DOVARIABLE
-PFA_UHCON:
- .dw 158
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90usb646/device.py b/amforth-6.5/avr8/devices/at90usb646/device.py
deleted file mode 100644
index 94d5083..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/device.py
+++ /dev/null
@@ -1,625 +0,0 @@
-# Generated Automatically
-
-# Partname AT90USB646
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'USB_GENAddr' : '#20', # USB General Interrupt Request
- 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#50', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
- 'USART1_TXAddr' : '#54', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'TWIAddr' : '#72', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#74', # Store Program Memory Read
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCHX' : '$f3', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$7f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_LSM': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
-
-# Module USB_GLOBAL
- 'OTGINT' : '$df', #
- 'OTGINT_STOI': '$20', #
- 'OTGINT_HNPERRI': '$10', #
- 'OTGINT_ROLEEXI': '$8', #
- 'OTGINT_BCERRI': '$4', #
- 'OTGINT_VBERRI': '$2', #
- 'OTGINT_SRPI': '$1', #
- 'OTGIEN' : '$de', #
- 'OTGIEN_STOE': '$20', #
- 'OTGIEN_HNPERRE': '$10', #
- 'OTGIEN_ROLEEXE': '$8', #
- 'OTGIEN_BCERRE': '$4', #
- 'OTGIEN_VBERRE': '$2', #
- 'OTGIEN_SRPE': '$1', #
- 'OTGCON' : '$dd', #
- 'OTGCON_HNPREQ': '$20', #
- 'OTGCON_SRPREQ': '$10', #
- 'OTGCON_SRPSEL': '$8', #
- 'OTGCON_VBUSHWC': '$4', #
- 'OTGCON_VBUSREQ': '$2', #
- 'OTGCON_VBUSRQC': '$1', #
- 'OTGTCON' : '$f9', #
- 'OTGTCON_OTGTCON_7': '$80', #
- 'OTGTCON_PAGE': '$60', #
- 'OTGTCON_VALUE_2': '$7', #
- 'USBINT' : '$da', #
- 'USBINT_IDTI': '$2', #
- 'USBINT_VBUSTI': '$1', #
- 'USBSTA' : '$d9', #
- 'USBSTA_SPEED': '$8', #
- 'USBSTA_ID': '$2', #
- 'USBSTA_VBUS': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_HOST': '$40', #
- 'USBCON_FRZCLK': '$20', #
- 'USBCON_OTGPADE': '$10', #
- 'USBCON_IDTE': '$2', #
- 'USBCON_VBUSTE': '$1', #
- 'UHWCON' : '$d7', # USB Hardware Configuration Reg
- 'UHWCON_UIMOD': '$80', #
- 'UHWCON_UIDE': '$40', #
- 'UHWCON_UVCONE': '$10', #
- 'UHWCON_UVREGE': '$1', #
-
-# Module USB_HOST
- 'UPERRX' : '$f5', #
- 'UPERRX_COUNTER': '$60', #
- 'UPERRX_CRC16': '$10', #
- 'UPERRX_TIMEOUT': '$8', #
- 'UPERRX_PID': '$4', #
- 'UPERRX_DATAPID': '$2', #
- 'UPERRX_DATATGL': '$1', #
- 'UPINT' : '$f8', #
- 'UPBCHX' : '$f7', #
- 'UPBCLX' : '$f6', #
- 'UPDATX' : '$af', #
- 'UPIENX' : '$ae', #
- 'UPIENX_FLERRE': '$80', #
- 'UPIENX_NAKEDE': '$40', #
- 'UPIENX_PERRE': '$10', #
- 'UPIENX_TXSTPE': '$8', #
- 'UPIENX_TXOUTE': '$4', #
- 'UPIENX_RXSTALLE': '$2', #
- 'UPIENX_RXINE': '$1', #
- 'UPCFG2X' : '$ad', #
- 'UPSTAX' : '$ac', #
- 'UPSTAX_CFGOK': '$80', #
- 'UPSTAX_OVERFI': '$40', #
- 'UPSTAX_UNDERFI': '$20', #
- 'UPSTAX_DTSEQ': '$c', #
- 'UPSTAX_NBUSYK': '$3', #
- 'UPCFG1X' : '$ab', #
- 'UPCFG1X_PSIZE': '$70', #
- 'UPCFG1X_PBK': '$c', #
- 'UPCFG1X_ALLOC': '$2', #
- 'UPCFG0X' : '$aa', #
- 'UPCFG0X_PTYPE': '$c0', #
- 'UPCFG0X_PTOKEN': '$30', #
- 'UPCFG0X_PEPNUM': '$f', #
- 'UPCONX' : '$a9', #
- 'UPCONX_PFREEZE': '$40', #
- 'UPCONX_INMODE': '$20', #
- 'UPCONX_RSTDT': '$8', #
- 'UPCONX_PEN': '$1', #
- 'UPRST' : '$a8', #
- 'UPRST_PRST': '$7f', #
- 'UPNUM' : '$a7', #
- 'UPINTX' : '$a6', #
- 'UPINTX_FIFOCON': '$80', #
- 'UPINTX_NAKEDI': '$40', #
- 'UPINTX_RWAL': '$20', #
- 'UPINTX_PERRI': '$10', #
- 'UPINTX_TXSTPI': '$8', #
- 'UPINTX_TXOUTI': '$4', #
- 'UPINTX_RXSTALLI': '$2', #
- 'UPINTX_RXINI': '$1', #
- 'UPINRQX' : '$a5', #
- 'UHFLEN' : '$a4', #
- 'UHFNUM' : '$a2', #
- 'UHADDR' : '$a1', #
- 'UHIEN' : '$a0', #
- 'UHIEN_HWUPE': '$40', #
- 'UHIEN_HSOFE': '$20', #
- 'UHIEN_RXRSME': '$10', #
- 'UHIEN_RSMEDE': '$8', #
- 'UHIEN_RSTE': '$4', #
- 'UHIEN_DDISCE': '$2', #
- 'UHIEN_DCONNE': '$1', #
- 'UHINT' : '$9f', #
- 'UHINT_UHUPI': '$40', #
- 'UHINT_HSOFI': '$20', #
- 'UHINT_RXRSMI': '$10', #
- 'UHINT_RSMEDI': '$8', #
- 'UHINT_RSTI': '$4', #
- 'UHINT_DDISCI': '$2', #
- 'UHINT_DCONNI': '$1', #
- 'UHCON' : '$9e', #
- 'UHCON_RESUME': '$4', #
- 'UHCON_RESET': '$2', #
- 'UHCON_SOFEN': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb646/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb646/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90usb646/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb647/at90usb647.frt b/amforth-6.5/avr8/devices/at90usb647/at90usb647.frt
deleted file mode 100644
index 4c7bc8e..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/at90usb647.frt
+++ /dev/null
@@ -1,587 +0,0 @@
-\ Partname: AT90USB647
-\ generated automatically
-
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ USB_DEVICE
-&244 constant UEINT \
-&243 constant UEBCHX \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $7F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_LSM \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-\ USB_GLOBAL
-&223 constant OTGINT \
- $20 constant OTGINT_STOI \
- $10 constant OTGINT_HNPERRI \
- $08 constant OTGINT_ROLEEXI \
- $04 constant OTGINT_BCERRI \
- $02 constant OTGINT_VBERRI \
- $01 constant OTGINT_SRPI \
-&222 constant OTGIEN \
- $20 constant OTGIEN_STOE \
- $10 constant OTGIEN_HNPERRE \
- $08 constant OTGIEN_ROLEEXE \
- $04 constant OTGIEN_BCERRE \
- $02 constant OTGIEN_VBERRE \
- $01 constant OTGIEN_SRPE \
-&221 constant OTGCON \
- $20 constant OTGCON_HNPREQ \
- $10 constant OTGCON_SRPREQ \
- $08 constant OTGCON_SRPSEL \
- $04 constant OTGCON_VBUSHWC \
- $02 constant OTGCON_VBUSREQ \
- $01 constant OTGCON_VBUSRQC \
-&249 constant OTGTCON \
- $80 constant OTGTCON_OTGTCON_7 \
- $60 constant OTGTCON_PAGE \
- $07 constant OTGTCON_VALUE_2 \
-&218 constant USBINT \
- $02 constant USBINT_IDTI \
- $01 constant USBINT_VBUSTI \
-&217 constant USBSTA \
- $08 constant USBSTA_SPEED \
- $02 constant USBSTA_ID \
- $01 constant USBSTA_VBUS \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $40 constant USBCON_HOST \
- $20 constant USBCON_FRZCLK \
- $10 constant USBCON_OTGPADE \
- $02 constant USBCON_IDTE \
- $01 constant USBCON_VBUSTE \
-&215 constant UHWCON \ USB Hardware Configuration Register
- $80 constant UHWCON_UIMOD \
- $40 constant UHWCON_UIDE \
- $10 constant UHWCON_UVCONE \
- $01 constant UHWCON_UVREGE \
-\ USB_HOST
-&245 constant UPERRX \
- $60 constant UPERRX_COUNTER \
- $10 constant UPERRX_CRC16 \
- $08 constant UPERRX_TIMEOUT \
- $04 constant UPERRX_PID \
- $02 constant UPERRX_DATAPID \
- $01 constant UPERRX_DATATGL \
-&248 constant UPINT \
-&247 constant UPBCHX \
-&246 constant UPBCLX \
-&175 constant UPDATX \
-&174 constant UPIENX \
- $80 constant UPIENX_FLERRE \
- $40 constant UPIENX_NAKEDE \
- $10 constant UPIENX_PERRE \
- $08 constant UPIENX_TXSTPE \
- $04 constant UPIENX_TXOUTE \
- $02 constant UPIENX_RXSTALLE \
- $01 constant UPIENX_RXINE \
-&173 constant UPCFG2X \
-&172 constant UPSTAX \
- $80 constant UPSTAX_CFGOK \
- $40 constant UPSTAX_OVERFI \
- $20 constant UPSTAX_UNDERFI \
- $0C constant UPSTAX_DTSEQ \
- $03 constant UPSTAX_NBUSYK \
-&171 constant UPCFG1X \
- $70 constant UPCFG1X_PSIZE \
- $0C constant UPCFG1X_PBK \
- $02 constant UPCFG1X_ALLOC \
-&170 constant UPCFG0X \
- $C0 constant UPCFG0X_PTYPE \
- $30 constant UPCFG0X_PTOKEN \
- $0F constant UPCFG0X_PEPNUM \
-&169 constant UPCONX \
- $40 constant UPCONX_PFREEZE \
- $20 constant UPCONX_INMODE \
- $08 constant UPCONX_RSTDT \
- $01 constant UPCONX_PEN \
-&168 constant UPRST \
- $7F constant UPRST_PRST \
-&167 constant UPNUM \
-&166 constant UPINTX \
- $80 constant UPINTX_FIFOCON \
- $40 constant UPINTX_NAKEDI \
- $20 constant UPINTX_RWAL \
- $10 constant UPINTX_PERRI \
- $08 constant UPINTX_TXSTPI \
- $04 constant UPINTX_TXOUTI \
- $02 constant UPINTX_RXSTALLI \
- $01 constant UPINTX_RXINI \
-&165 constant UPINRQX \
-&164 constant UHFLEN \
-&162 constant UHFNUM \
-&161 constant UHADDR \
-&160 constant UHIEN \
- $40 constant UHIEN_HWUPE \
- $20 constant UHIEN_HSOFE \
- $10 constant UHIEN_RXRSME \
- $08 constant UHIEN_RSMEDE \
- $04 constant UHIEN_RSTE \
- $02 constant UHIEN_DDISCE \
- $01 constant UHIEN_DCONNE \
-&159 constant UHINT \
- $40 constant UHINT_UHUPI \
- $20 constant UHINT_HSOFI \
- $10 constant UHINT_RXRSMI \
- $08 constant UHINT_RSMEDI \
- $04 constant UHINT_RSTI \
- $02 constant UHINT_DDISCI \
- $01 constant UHINT_DCONNI \
-&158 constant UHCON \
- $04 constant UHCON_RESUME \
- $02 constant UHCON_RESET \
- $01 constant UHCON_SOFEN \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant USB_GENAddr \ USB General Interrupt Request
-&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART1__RXAddr \ USART1, Rx Complete
-&52 constant USART1__UDREAddr \ USART1 Data register Empty
-&54 constant USART1__TXAddr \ USART1, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant TWIAddr \ 2-wire Serial Interface
-&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb647/device.asm b/amforth-6.5/avr8/devices/at90usb647/device.asm
deleted file mode 100644
index 12cadca..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/device.asm
+++ /dev/null
@@ -1,140 +0,0 @@
-; Partname: AT90USB647
-; generated automatically, do not edit
-
-.nolist
- .include "usb647def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_WATCHDOG = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_CPU = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_USART1 = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_USB_GLOBAL = 0
-.set WANT_USB_HOST = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PLL = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; USB General Interrupt Request
-.org 22
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART1, Rx Complete
-.org 52
- rcall isr ; USART1 Data register Empty
-.org 54
- rcall isr ; USART1, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; 2-wire Serial Interface
-.org 74
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 38
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 38
-mcu_name:
- .dw 10
- .db "AT90USB647"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb647/device.inc b/amforth-6.5/avr8/devices/at90usb647/device.inc
deleted file mode 100644
index b6d73ec..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/device.inc
+++ /dev/null
@@ -1,1914 +0,0 @@
-; Partname: AT90USB647
-; generated automatically, no not edit
-
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-
-.endif
-.if WANT_USB_GLOBAL == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGINT:
- .dw $ff06
- .db "OTGINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGINT
-XT_OTGINT:
- .dw PFA_DOVARIABLE
-PFA_OTGINT:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGIEN:
- .dw $ff06
- .db "OTGIEN"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGIEN
-XT_OTGIEN:
- .dw PFA_DOVARIABLE
-PFA_OTGIEN:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGCON:
- .dw $ff06
- .db "OTGCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGCON
-XT_OTGCON:
- .dw PFA_DOVARIABLE
-PFA_OTGCON:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_OTGTCON:
- .dw $ff07
- .db "OTGTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OTGTCON
-XT_OTGTCON:
- .dw PFA_DOVARIABLE
-PFA_OTGTCON:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; USB Hardware Configuration Register
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw 215
-
-.endif
-.if WANT_USB_HOST == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPERRX:
- .dw $ff06
- .db "UPERRX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPERRX
-XT_UPERRX:
- .dw PFA_DOVARIABLE
-PFA_UPERRX:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINT:
- .dw $ff05
- .db "UPINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINT
-XT_UPINT:
- .dw PFA_DOVARIABLE
-PFA_UPINT:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPBCHX:
- .dw $ff06
- .db "UPBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPBCHX
-XT_UPBCHX:
- .dw PFA_DOVARIABLE
-PFA_UPBCHX:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPBCLX:
- .dw $ff06
- .db "UPBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPBCLX
-XT_UPBCLX:
- .dw PFA_DOVARIABLE
-PFA_UPBCLX:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPDATX:
- .dw $ff06
- .db "UPDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPDATX
-XT_UPDATX:
- .dw PFA_DOVARIABLE
-PFA_UPDATX:
- .dw 175
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPIENX:
- .dw $ff06
- .db "UPIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPIENX
-XT_UPIENX:
- .dw PFA_DOVARIABLE
-PFA_UPIENX:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG2X:
- .dw $ff07
- .db "UPCFG2X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG2X
-XT_UPCFG2X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG2X:
- .dw 173
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPSTAX:
- .dw $ff06
- .db "UPSTAX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPSTAX
-XT_UPSTAX:
- .dw PFA_DOVARIABLE
-PFA_UPSTAX:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG1X:
- .dw $ff07
- .db "UPCFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG1X
-XT_UPCFG1X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG1X:
- .dw 171
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCFG0X:
- .dw $ff07
- .db "UPCFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCFG0X
-XT_UPCFG0X:
- .dw PFA_DOVARIABLE
-PFA_UPCFG0X:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPCONX:
- .dw $ff06
- .db "UPCONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPCONX
-XT_UPCONX:
- .dw PFA_DOVARIABLE
-PFA_UPCONX:
- .dw 169
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPRST:
- .dw $ff05
- .db "UPRST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPRST
-XT_UPRST:
- .dw PFA_DOVARIABLE
-PFA_UPRST:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPNUM:
- .dw $ff05
- .db "UPNUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPNUM
-XT_UPNUM:
- .dw PFA_DOVARIABLE
-PFA_UPNUM:
- .dw 167
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINTX:
- .dw $ff06
- .db "UPINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINTX
-XT_UPINTX:
- .dw PFA_DOVARIABLE
-PFA_UPINTX:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPINRQX:
- .dw $ff07
- .db "UPINRQX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UPINRQX
-XT_UPINRQX:
- .dw PFA_DOVARIABLE
-PFA_UPINRQX:
- .dw 165
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHFLEN:
- .dw $ff06
- .db "UHFLEN"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHFLEN
-XT_UHFLEN:
- .dw PFA_DOVARIABLE
-PFA_UHFLEN:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHFNUM:
- .dw $ff06
- .db "UHFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHFNUM
-XT_UHFNUM:
- .dw PFA_DOVARIABLE
-PFA_UHFNUM:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHADDR:
- .dw $ff06
- .db "UHADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHADDR
-XT_UHADDR:
- .dw PFA_DOVARIABLE
-PFA_UHADDR:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHIEN:
- .dw $ff05
- .db "UHIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHIEN
-XT_UHIEN:
- .dw PFA_DOVARIABLE
-PFA_UHIEN:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHINT:
- .dw $ff05
- .db "UHINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHINT
-XT_UHINT:
- .dw PFA_DOVARIABLE
-PFA_UHINT:
- .dw 159
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHCON:
- .dw $ff05
- .db "UHCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UHCON
-XT_UHCON:
- .dw PFA_DOVARIABLE
-PFA_UHCON:
- .dw 158
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90usb647/device.py b/amforth-6.5/avr8/devices/at90usb647/device.py
deleted file mode 100644
index 485b265..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/device.py
+++ /dev/null
@@ -1,625 +0,0 @@
-# Generated Automatically
-
-# Partname AT90USB647
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'USB_GENAddr' : '#20', # USB General Interrupt Request
- 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#50', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
- 'USART1_TXAddr' : '#54', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'TWIAddr' : '#72', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#74', # Store Program Memory Read
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCHX' : '$f3', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$7f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_LSM': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
-
-# Module USB_GLOBAL
- 'OTGINT' : '$df', #
- 'OTGINT_STOI': '$20', #
- 'OTGINT_HNPERRI': '$10', #
- 'OTGINT_ROLEEXI': '$8', #
- 'OTGINT_BCERRI': '$4', #
- 'OTGINT_VBERRI': '$2', #
- 'OTGINT_SRPI': '$1', #
- 'OTGIEN' : '$de', #
- 'OTGIEN_STOE': '$20', #
- 'OTGIEN_HNPERRE': '$10', #
- 'OTGIEN_ROLEEXE': '$8', #
- 'OTGIEN_BCERRE': '$4', #
- 'OTGIEN_VBERRE': '$2', #
- 'OTGIEN_SRPE': '$1', #
- 'OTGCON' : '$dd', #
- 'OTGCON_HNPREQ': '$20', #
- 'OTGCON_SRPREQ': '$10', #
- 'OTGCON_SRPSEL': '$8', #
- 'OTGCON_VBUSHWC': '$4', #
- 'OTGCON_VBUSREQ': '$2', #
- 'OTGCON_VBUSRQC': '$1', #
- 'OTGTCON' : '$f9', #
- 'OTGTCON_OTGTCON_7': '$80', #
- 'OTGTCON_PAGE': '$60', #
- 'OTGTCON_VALUE_2': '$7', #
- 'USBINT' : '$da', #
- 'USBINT_IDTI': '$2', #
- 'USBINT_VBUSTI': '$1', #
- 'USBSTA' : '$d9', #
- 'USBSTA_SPEED': '$8', #
- 'USBSTA_ID': '$2', #
- 'USBSTA_VBUS': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_HOST': '$40', #
- 'USBCON_FRZCLK': '$20', #
- 'USBCON_OTGPADE': '$10', #
- 'USBCON_IDTE': '$2', #
- 'USBCON_VBUSTE': '$1', #
- 'UHWCON' : '$d7', # USB Hardware Configuration Reg
- 'UHWCON_UIMOD': '$80', #
- 'UHWCON_UIDE': '$40', #
- 'UHWCON_UVCONE': '$10', #
- 'UHWCON_UVREGE': '$1', #
-
-# Module USB_HOST
- 'UPERRX' : '$f5', #
- 'UPERRX_COUNTER': '$60', #
- 'UPERRX_CRC16': '$10', #
- 'UPERRX_TIMEOUT': '$8', #
- 'UPERRX_PID': '$4', #
- 'UPERRX_DATAPID': '$2', #
- 'UPERRX_DATATGL': '$1', #
- 'UPINT' : '$f8', #
- 'UPBCHX' : '$f7', #
- 'UPBCLX' : '$f6', #
- 'UPDATX' : '$af', #
- 'UPIENX' : '$ae', #
- 'UPIENX_FLERRE': '$80', #
- 'UPIENX_NAKEDE': '$40', #
- 'UPIENX_PERRE': '$10', #
- 'UPIENX_TXSTPE': '$8', #
- 'UPIENX_TXOUTE': '$4', #
- 'UPIENX_RXSTALLE': '$2', #
- 'UPIENX_RXINE': '$1', #
- 'UPCFG2X' : '$ad', #
- 'UPSTAX' : '$ac', #
- 'UPSTAX_CFGOK': '$80', #
- 'UPSTAX_OVERFI': '$40', #
- 'UPSTAX_UNDERFI': '$20', #
- 'UPSTAX_DTSEQ': '$c', #
- 'UPSTAX_NBUSYK': '$3', #
- 'UPCFG1X' : '$ab', #
- 'UPCFG1X_PSIZE': '$70', #
- 'UPCFG1X_PBK': '$c', #
- 'UPCFG1X_ALLOC': '$2', #
- 'UPCFG0X' : '$aa', #
- 'UPCFG0X_PTYPE': '$c0', #
- 'UPCFG0X_PTOKEN': '$30', #
- 'UPCFG0X_PEPNUM': '$f', #
- 'UPCONX' : '$a9', #
- 'UPCONX_PFREEZE': '$40', #
- 'UPCONX_INMODE': '$20', #
- 'UPCONX_RSTDT': '$8', #
- 'UPCONX_PEN': '$1', #
- 'UPRST' : '$a8', #
- 'UPRST_PRST': '$7f', #
- 'UPNUM' : '$a7', #
- 'UPINTX' : '$a6', #
- 'UPINTX_FIFOCON': '$80', #
- 'UPINTX_NAKEDI': '$40', #
- 'UPINTX_RWAL': '$20', #
- 'UPINTX_PERRI': '$10', #
- 'UPINTX_TXSTPI': '$8', #
- 'UPINTX_TXOUTI': '$4', #
- 'UPINTX_RXSTALLI': '$2', #
- 'UPINTX_RXINI': '$1', #
- 'UPINRQX' : '$a5', #
- 'UHFLEN' : '$a4', #
- 'UHFNUM' : '$a2', #
- 'UHADDR' : '$a1', #
- 'UHIEN' : '$a0', #
- 'UHIEN_HWUPE': '$40', #
- 'UHIEN_HSOFE': '$20', #
- 'UHIEN_RXRSME': '$10', #
- 'UHIEN_RSMEDE': '$8', #
- 'UHIEN_RSTE': '$4', #
- 'UHIEN_DDISCE': '$2', #
- 'UHIEN_DCONNE': '$1', #
- 'UHINT' : '$9f', #
- 'UHINT_UHUPI': '$40', #
- 'UHINT_HSOFI': '$20', #
- 'UHINT_RXRSMI': '$10', #
- 'UHINT_RSMEDI': '$8', #
- 'UHINT_RSTI': '$4', #
- 'UHINT_DDISCI': '$2', #
- 'UHINT_DCONNI': '$1', #
- 'UHCON' : '$9e', #
- 'UHCON_RESUME': '$4', #
- 'UHCON_RESET': '$2', #
- 'UHCON_SOFEN': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb647/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb647/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90usb647/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb82/at90usb82.frt b/amforth-6.5/avr8/devices/at90usb82/at90usb82.frt
deleted file mode 100644
index 26ab16b..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/at90usb82.frt
+++ /dev/null
@@ -1,367 +0,0 @@
-\ Partname: AT90USB82
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_DEVICE
-&244 constant UEINT \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $1F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
-&99 constant REGCR \ Regulator Control Register
- $01 constant REGCR_REGDIS \
-\ PS2
-&251 constant UPOE \
- $C0 constant UPOE_UPWE \
- $30 constant UPOE_UPDRV \
- $08 constant UPOE_SCKI \
- $04 constant UPOE_DATAI \
- $02 constant UPOE_DPI \
- $01 constant UPOE_DMI \
-&250 constant PS2CON \ PS2 Pad Enable register
- $01 constant PS2CON_PS2EN \ Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $20 constant MCUSR_USBRF \ USB reset flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
-&210 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&209 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&208 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-&81 constant DWDR \ debugWire communication register
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $1F constant PCMSK1_PCINT \
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&203 constant UCSR1D \ USART Control and Status Register D
- $02 constant UCSR1D_CTSEN \ CTS Enable
- $01 constant UCSR1D_RTSEN \ RTS Enable
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-&98 constant WDTCKD \ Watchdog Timer Clock Divider
- $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
- $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
- $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTC
-&40 constant PORTC \ Port C Data Register
- $F0 constant PORTC_PORTC \ Port C Data Register bits
- $07 constant PORTC_PORTC \ Port C Data Register bits
-&39 constant DDRC \ Port C Data Direction Register
- $F0 constant DDRC_DDC \ Port C Data Direction Register bits
- $07 constant DDRC_DDC \ Port C Data Direction Register bits
-&38 constant PINC \ Port C Input Pins
- $F0 constant PINC_PINC \ Port C Input Pins bits
- $07 constant PINC_PINC \ Port C Input Pins bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant USB_GENAddr \ USB General Interrupt Request
-&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&26 constant WDTAddr \ Watchdog Time-out Interrupt
-&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
-&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
-&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
-&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
-&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&46 constant USART1__RXAddr \ USART1, Rx Complete
-&48 constant USART1__UDREAddr \ USART1 Data register Empty
-&50 constant USART1__TXAddr \ USART1, Tx Complete
-&52 constant ANALOG_COMPAddr \ Analog Comparator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb82/device.asm b/amforth-6.5/avr8/devices/at90usb82/device.asm
deleted file mode 100644
index 9432dca..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: AT90USB82
-; generated automatically, do not edit
-
-.nolist
- .include "usb82def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_PS2 = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTC = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; USB General Interrupt Request
-.org 24
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 26
- rcall isr ; Watchdog Time-out Interrupt
-.org 28
- rcall isr ; Timer/Counter2 Capture Event
-.org 30
- rcall isr ; Timer/Counter2 Compare Match B
-.org 32
- rcall isr ; Timer/Counter2 Compare Match B
-.org 34
- rcall isr ; Timer/Counter2 Compare Match C
-.org 36
- rcall isr ; Timer/Counter1 Overflow
-.org 38
- rcall isr ; Timer/Counter0 Compare Match A
-.org 40
- rcall isr ; Timer/Counter0 Compare Match B
-.org 42
- rcall isr ; Timer/Counter0 Overflow
-.org 44
- rcall isr ; SPI Serial Transfer Complete
-.org 46
- rcall isr ; USART1, Rx Complete
-.org 48
- rcall isr ; USART1 Data register Empty
-.org 50
- rcall isr ; USART1, Tx Complete
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 4096
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 9
- .db "AT90USB82",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb82/device.inc b/amforth-6.5/avr8/devices/at90usb82/device.inc
deleted file mode 100644
index 7ca46fb..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/device.inc
+++ /dev/null
@@ -1,1155 +0,0 @@
-; Partname: AT90USB82
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Control Register
-VE_REGCR:
- .dw $ff05
- .db "REGCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_REGCR
-XT_REGCR:
- .dw PFA_DOVARIABLE
-PFA_REGCR:
- .dw 99
-
-.endif
-.if WANT_PS2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPOE:
- .dw $ff04
- .db "UPOE"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPOE
-XT_UPOE:
- .dw PFA_DOVARIABLE
-PFA_UPOE:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PS2 Pad Enable register
-VE_PS2CON:
- .dw $ff06
- .db "PS2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_PS2CON
-XT_PS2CON:
- .dw PFA_DOVARIABLE
-PFA_PS2CON:
- .dw 250
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; debugWire communication register
-VE_DWDR:
- .dw $ff04
- .db "DWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_DWDR
-XT_DWDR:
- .dw PFA_DOVARIABLE
-PFA_DWDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register D
-VE_UCSR1D:
- .dw $ff06
- .db "UCSR1D"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1D
-XT_UCSR1D:
- .dw PFA_DOVARIABLE
-PFA_UCSR1D:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Clock Divider
-VE_WDTCKD:
- .dw $ff06
- .db "WDTCKD"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCKD
-XT_WDTCKD:
- .dw PFA_DOVARIABLE
-PFA_WDTCKD:
- .dw 98
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
diff --git a/amforth-6.5/avr8/devices/at90usb82/device.py b/amforth-6.5/avr8/devices/at90usb82/device.py
deleted file mode 100644
index 2a45f1d..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/device.py
+++ /dev/null
@@ -1,387 +0,0 @@
-# Generated Automatically
-
-# Partname AT90USB82
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#4', # External Interrupt Request 0
- 'INT1Addr' : '#8', # External Interrupt Request 1
- 'INT2Addr' : '#12', # External Interrupt Request 2
- 'INT3Addr' : '#16', # External Interrupt Request 3
- 'INT4Addr' : '#20', # External Interrupt Request 4
- 'INT5Addr' : '#24', # External Interrupt Request 5
- 'INT6Addr' : '#28', # External Interrupt Request 6
- 'INT7Addr' : '#32', # External Interrupt Request 7
- 'PCINT0Addr' : '#36', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#40', # Pin Change Interrupt Request 1
- 'USB_GENAddr' : '#44', # USB General Interrupt Request
- 'USB_COMAddr' : '#48', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#52', # Watchdog Time-out Interrupt
- 'TIMER1_CAPTAddr' : '#56', # Timer/Counter2 Capture Event
- 'TIMER1_COMPAAddr' : '#60', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPBAddr' : '#64', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPCAddr' : '#68', # Timer/Counter2 Compare Match C
- 'TIMER1_OVFAddr' : '#72', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#76', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#80', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#84', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#88', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#92', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#96', # USART1 Data register Empty
- 'USART1_TXAddr' : '#100', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#104', # Analog Comparator
- 'EE_READYAddr' : '#108', # EEPROM Ready
- 'SPM_READYAddr' : '#112', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$1f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_RSTCPU': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_FRZCLK': '$20', #
- 'REGCR' : '$63', # Regulator Control Register
- 'REGCR_REGDIS': '$1', #
-
-# Module PS2
- 'UPOE' : '$fb', #
- 'UPOE_UPWE': '$c0', #
- 'UPOE_UPDRV': '$30', #
- 'UPOE_SCKI': '$8', #
- 'UPOE_DATAI': '$4', #
- 'UPOE_DPI': '$2', #
- 'UPOE_DMI': '$1', #
- 'PS2CON' : '$fa', # PS2 Pad Enable register
- 'PS2CON_PS2EN': '$1', # Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_USBRF': '$20', # USB reset flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'CLKSTA' : '$d2', #
- 'CLKSTA_RCON': '$2', #
- 'CLKSTA_EXTON': '$1', #
- 'CLKSEL1' : '$d1', #
- 'CLKSEL1_RCCKSEL': '$f0', #
- 'CLKSEL1_EXCKSEL': '$f', #
- 'CLKSEL0' : '$d0', #
- 'CLKSEL0_RCSUT': '$c0', #
- 'CLKSEL0_EXSUT': '$30', #
- 'CLKSEL0_RCE': '$8', #
- 'CLKSEL0_EXTE': '$4', #
- 'CLKSEL0_CLKS': '$1', #
- 'DWDR' : '$51', # debugWire communication regist
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$1f', #
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UCSR1D' : '$cb', # USART Control and Status Regis
- 'UCSR1D_CTSEN': '$2', # CTS Enable
- 'UCSR1D_RTSEN': '$1', # RTS Enable
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
- 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
- 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
- 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
- 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PORTC_PORTC': '$f0', # Port C Data Register bits
- 'PORTC_PORTC': '$7', # Port C Data Register bits
- 'DDRC' : '$27', # Port C Data Direction Register
- 'DDRC_DDC': '$f0', # Port C Data Direction Register
- 'DDRC_DDC': '$7', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
- 'PINC_PINC': '$f0', # Port C Input Pins bits
- 'PINC_PINC': '$7', # Port C Input Pins bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb82/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb82/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/at90usb82/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega103/atmega103.frt b/amforth-6.5/avr8/devices/atmega103/atmega103.frt
deleted file mode 100644
index 6130f93..0000000
--- a/amforth-6.5/avr8/devices/atmega103/atmega103.frt
+++ /dev/null
@@ -1,124 +0,0 @@
-\ Partname: ATmega103
-\ Built using part description XML file version 236
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-25 constant ADCH \ ADC Data Register High Byte
-24 constant ADCL \ ADC Data Register Low Byte
-26 constant ADCSR \ The ADC Control and Status register
-27 constant ADMUX \ The ADC multiplexer Selection Register
-
-\ ANALOG_COMPARATOR
-28 constant ACSR \ Analog Comparator Control And Status Register
-
-\ CPU
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-5B constant RAMPZ \ RAM Page Z Select Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-5C constant XDIV \ XTAL Divide Control Register
-
-\ EEPROM
-3F constant EEARH \ EEPROM Read/Write Access High Byte
-3E constant EEARL \ EEPROM Read/Write Access Low Byte
-3C constant EECR \ EEPROM Control Register
-3D constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-5A constant EICR \ External Interrupt Control Register B
-58 constant EIFR \ External Interrupt Flag Register
-59 constant EIMSK \ External Interrupt Mask Register
-
-\ PORTA
-3A constant DDRA \ Port A Data Direction Register
-39 constant PINA \ Port A Input Pins
-3B constant PORTA \ Port A Data Register
-
-\ PORTB
-37 constant DDRB \ Port B Data Direction Register
-36 constant PINB \ Port B Input Pins
-38 constant PORTB \ Port B Data Register
-
-\ PORTC
-35 constant PORTC \ Port C Data Register
-
-\ PORTD
-31 constant DDRD \ Port D Data Direction Register
-30 constant PIND \ Port D Input Pins
-32 constant PORTD \ Port D Data Register
-
-\ PORTE
-22 constant DDRE \ Data Direction Register, Port E
-21 constant PINE \ Input Pins, Port E
-23 constant PORTE \ Data Register, Port E
-
-\ PORTF
-20 constant PINF \ Input Pins, Port F
-
-\ SPI
-2D constant SPCR \ SPI Control Register
-2F constant SPDR \ SPI Data Register
-2E constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-50 constant ASSR \ Asynchronus Status Register
-51 constant OCR0 \ Output Compare Register
-53 constant TCCR0 \ Timer/Counter Control Register
-52 constant TCNT0 \ Timer/Counter Register
-56 constant TIFR \ Timer/Counter Interrupt Flag register
-57 constant TIMSK \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-4F constant TCCR1A \ Timer/Counter1 Control Register A
-4E constant TCCR1B \ Timer/Counter1 Control Register B
-4D constant TCNT1H \ Timer/Counter1 High Byte
-4C constant TCNT1L \ Timer/Counter1 Low Byte
-
-\ TIMER_COUNTER_2
-43 constant OCR2 \ Timer/Counter2 Output Compare Register
-45 constant TCCR2 \ Timer/Counter2 Control Register
-44 constant TCNT2 \ Timer/Counter2
-
-\ UART
-29 constant UBRR \ UART BAUD Rate Register
-2A constant UCR \ UART Control Register
-2C constant UDR \ UART I/O Data Register
-2B constant USR \ UART Status Register
-
-\ WATCHDOG
-41 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt 0
-004 constant INT1Addr \ External Interrupt 1
-006 constant INT2Addr \ External Interrupt 2
-008 constant INT3Addr \ External Interrupt 3
-00A constant INT4Addr \ External Interrupt 4
-00C constant INT5Addr \ External Interrupt 5
-00E constant INT6Addr \ External Interrupt 6
-010 constant INT7Addr \ External Interrupt 7
-012 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-014 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-016 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-018 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-01A constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-01C constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-01E constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-020 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-022 constant SPISTCAddr \ SPI Serial Transfer Complete
-024 constant UARTRXAddr \ UART, Rx Complete
-026 constant UARTUDREAddr \ UART Data Register Empty
-028 constant UARTTXAddr \ UART, Tx Complete
-02A constant ADCAddr \ ADC Conversion Complete
-02C constant EE_READYAddr \ EEPROM Ready
-02E constant ANALOG_COMPAddr \ Analog Comparator
diff --git a/amforth-6.5/avr8/devices/atmega103/device.asm b/amforth-6.5/avr8/devices/atmega103/device.asm
deleted file mode 100644
index efcb78f..0000000
--- a/amforth-6.5/avr8/devices/atmega103/device.asm
+++ /dev/null
@@ -1,126 +0,0 @@
-; Partname: ATmega103
-; Built using part description XML file version 236
-; generated automatically, do not edit
-
-.nolist
- .include "m103def.inc"
-.list
-
-.equ ramstart = $60
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_UART = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 24
-.org $002
- rcall isr ; External Interrupt 0
-.org $004
- rcall isr ; External Interrupt 1
-.org $006
- rcall isr ; External Interrupt 2
-.org $008
- rcall isr ; External Interrupt 3
-.org $00A
- rcall isr ; External Interrupt 4
-.org $00C
- rcall isr ; External Interrupt 5
-.org $00E
- rcall isr ; External Interrupt 6
-.org $010
- rcall isr ; External Interrupt 7
-.org $012
- rcall isr ; Timer/Counter2 Compare Match
-.org $014
- rcall isr ; Timer/Counter2 Overflow
-.org $016
- rcall isr ; Timer/Counter1 Capture Event
-.org $018
- rcall isr ; Timer/Counter1 Compare Match A
-.org $01A
- rcall isr ; Timer/Counter1 Compare Match B
-.org $01C
- rcall isr ; Timer/Counter1 Overflow
-.org $01E
- rcall isr ; Timer/Counter0 Compare Match
-.org $020
- rcall isr ; Timer/Counter0 Overflow
-.org $022
- rcall isr ; SPI Serial Transfer Complete
-.org $024
- rcall isr ; UART, Rx Complete
-.org $026
- rcall isr ; UART Data Register Empty
-.org $028
- rcall isr ; UART, Tx Complete
-.org $02A
- rcall isr ; ADC Conversion Complete
-.org $02C
- rcall isr ; EEPROM Ready
-.org $02E
- rcall isr ; Analog Comparator
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 4000
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 0 ; minimum of (from XML) and 0xffff
-mcu_numints:
- .dw 24
-mcu_name:
- .dw 9
- .db "ATmega103",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega103/device.inc b/amforth-6.5/avr8/devices/atmega103/device.inc
deleted file mode 100644
index f52a85e..0000000
--- a/amforth-6.5/avr8/devices/atmega103/device.inc
+++ /dev/null
@@ -1,825 +0,0 @@
-; Partname: ATmega103
-; Built using part description XML file version 236
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $25
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSR:
- .dw $ff05
- .db "ADCSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSR
-XT_ADCSR:
- .dw PFA_DOVARIABLE
-PFA_ADCSR:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $27
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw $5B
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-; ( -- addr ) System Constant
-; R( -- )
-; XTAL Divide Control Register
-VE_XDIV:
- .dw $ff04
- .db "XDIV"
- .dw VE_HEAD
- .set VE_HEAD=VE_XDIV
-XT_XDIV:
- .dw PFA_DOVARIABLE
-PFA_XDIV:
- .dw $5C
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICR:
- .dw $ff04
- .db "EICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EICR
-XT_EICR:
- .dw PFA_DOVARIABLE
-PFA_EICR:
- .dw $5A
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $58
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $59
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $3B
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $38
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $35
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $31
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $32
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $22
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $23
-
-.endif
-
-; ********
-.if WANT_PORTF == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw $20
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronus Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $50
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw $51
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $52
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw $56
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $4F
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $4D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $4C
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $44
-
-.endif
-
-; ********
-.if WANT_UART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; UART BAUD Rate Register
-VE_UBRR:
- .dw $ff04
- .db "UBRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR
-XT_UBRR:
- .dw PFA_DOVARIABLE
-PFA_UBRR:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; UART Control Register
-VE_UCR:
- .dw $ff03
- .db "UCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCR
-XT_UCR:
- .dw PFA_DOVARIABLE
-PFA_UCR:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; UART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; UART Status Register
-VE_USR:
- .dw $ff03
- .db "USR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USR
-XT_USR:
- .dw PFA_DOVARIABLE
-PFA_USR:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $41
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega103/device.py b/amforth-6.5/avr8/devices/atmega103/device.py
deleted file mode 100644
index fcd3341..0000000
--- a/amforth-6.5/avr8/devices/atmega103/device.py
+++ /dev/null
@@ -1,88 +0,0 @@
-# Partname: ATmega103
-# Built using part description XML file version 236
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$25',
- 'ADCL': '$24',
- 'ADCSR': '$26',
- 'ADMUX': '$27',
- 'ACSR': '$28',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'RAMPZ': '$5B',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'XDIV': '$5C',
- 'EEARH': '$3F',
- 'EEARL': '$3E',
- 'EECR': '$3C',
- 'EEDR': '$3D',
- 'EICR': '$5A',
- 'EIFR': '$58',
- 'EIMSK': '$59',
- 'DDRA': '$3A',
- 'PINA': '$39',
- 'PORTA': '$3B',
- 'DDRB': '$37',
- 'PINB': '$36',
- 'PORTB': '$38',
- 'PORTC': '$35',
- 'DDRD': '$31',
- 'PIND': '$30',
- 'PORTD': '$32',
- 'DDRE': '$22',
- 'PINE': '$21',
- 'PORTE': '$23',
- 'PINF': '$20',
- 'SPCR': '$2D',
- 'SPDR': '$2F',
- 'SPSR': '$2E',
- 'ASSR': '$50',
- 'OCR0': '$51',
- 'TCCR0': '$53',
- 'TCNT0': '$52',
- 'TIFR': '$56',
- 'TIMSK': '$57',
- 'ICR1H': '$47',
- 'ICR1L': '$46',
- 'OCR1AH': '$4B',
- 'OCR1AL': '$4A',
- 'OCR1BH': '$49',
- 'OCR1BL': '$48',
- 'TCCR1A': '$4F',
- 'TCCR1B': '$4E',
- 'TCNT1H': '$4D',
- 'TCNT1L': '$4C',
- 'OCR2': '$43',
- 'TCCR2': '$45',
- 'TCNT2': '$44',
- 'UBRR': '$29',
- 'UCR': '$2A',
- 'UDR': '$2C',
- 'USR': '$2B',
- 'WDTCR': '$41',
- 'INT0Addr': '$002',
- 'INT1Addr': '$004',
- 'INT2Addr': '$006',
- 'INT3Addr': '$008',
- 'INT4Addr': '$00A',
- 'INT5Addr': '$00C',
- 'INT6Addr': '$00E',
- 'INT7Addr': '$010',
- 'TIMER2_COMPAddr': '$012',
- 'TIMER2_OVFAddr': '$014',
- 'TIMER1_CAPTAddr': '$016',
- 'TIMER1_COMPAAddr': '$018',
- 'TIMER1_COMPBAddr': '$01A',
- 'TIMER1_OVFAddr': '$01C',
- 'TIMER0_COMPAddr': '$01E',
- 'TIMER0_OVFAddr': '$020',
- 'SPISTCAddr': '$022',
- 'UARTRXAddr': '$024',
- 'UARTUDREAddr': '$026',
- 'UARTTXAddr': '$028',
- 'ADCAddr': '$02A',
- 'EE_READYAddr': '$02C',
- 'ANALOG_COMPAddr': '$02E'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega128/atmega128.frt b/amforth-6.5/avr8/devices/atmega128/atmega128.frt
deleted file mode 100644
index 7441912..0000000
--- a/amforth-6.5/avr8/devices/atmega128/atmega128.frt
+++ /dev/null
@@ -1,329 +0,0 @@
-\ Partname: ATmega128
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&64 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ TWI
-&112 constant TWBR \ TWI Bit Rate register
-&116 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&113 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&115 constant TWDR \ TWI Data register
-&114 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&44 constant UDR0 \ USART I/O Data Register
-&43 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&42 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&149 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
-&41 constant UBRR0L \ USART Baud Rate Register Low Byte
-\ USART1
-&156 constant UDR1 \ USART I/O Data Register
-&155 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&154 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&157 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
-&153 constant UBRR1L \ USART Baud Rate Register Low Byte
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SRE \ External SRAM Enable
- $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
- $20 constant MCUCR_SE \ Sleep Enable
- $18 constant MCUCR_SM \ Sleep Mode Select
- $04 constant MCUCR_SM2 \ Sleep Mode Select
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUCSR \ MCU Control And Status Register
- $80 constant MCUCSR_JTD \ JTAG Interface Disable
- $10 constant MCUCSR_JTRF \ JTAG Reset Flag
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&109 constant XMCRA \ External Memory Control Register A
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW0 \ Wait state select bit lower page
- $02 constant XMCRA_SRW11 \ Wait state select bit upper page
-&108 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&111 constant OSCCAL \ Oscillator Calibration Value
-&92 constant XDIV \ XTAL Divide Control Register
-&91 constant RAMPZ \ RAM Page Z Select Register
- $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
-\ BOOT_LOAD
-&104 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ MISC
-\ EXTERNAL_INTERRUPT
-&106 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&90 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&89 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&88 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ PORTE
-&35 constant PORTE \ Data Register, Port E
-&34 constant DDRE \ Data Direction Register, Port E
-&33 constant PINE \ Input Pins, Port E
-\ PORTF
-&98 constant PORTF \ Data Register, Port F
-&97 constant DDRF \ Data Direction Register, Port F
-&32 constant PINF \ Input Pins, Port F
-\ PORTG
-&101 constant PORTG \ Data Register, Port G
-&100 constant DDRG \ Data Direction Register, Port G
-&99 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&81 constant OCR0 \ Output Compare Register
-&80 constant ASSR \ Asynchronus Status Register
- $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
- $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
- $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
- $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
-&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&86 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_1
-&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
- $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
-&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
- $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&122 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
- $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
- $30 constant TCCR2_COM2 \ Compare Match Output Mode
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select
-&68 constant TCNT2 \ Timer/Counter Register
-&67 constant OCR2 \ Output Compare Register
-\ TIMER_COUNTER_3
-&139 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
-&138 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&140 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
- $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
-&136 constant TCNT3 \ Timer/Counter3 Bytes
-&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
-&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADFR \ ADC Free Running Select
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART0__RXAddr \ USART0, Rx Complete
-&38 constant USART0__UDREAddr \ USART0 Data Register Empty
-&40 constant USART0__TXAddr \ USART0, Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&60 constant USART1__RXAddr \ USART1, Rx Complete
-&62 constant USART1__UDREAddr \ USART1, Data Register Empty
-&64 constant USART1__TXAddr \ USART1, Tx Complete
-&66 constant TWIAddr \ 2-wire Serial Interface
-&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega128/device.asm b/amforth-6.5/avr8/devices/atmega128/device.asm
deleted file mode 100644
index 2466ed0..0000000
--- a/amforth-6.5/avr8/devices/atmega128/device.asm
+++ /dev/null
@@ -1,141 +0,0 @@
-; Partname: ATmega128
-; generated automatically, do not edit
-
-.nolist
- .include "m128def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_MISC = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_AD_CONVERTER = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match
-.org 32
- rcall isr ; Timer/Counter0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART0, Rx Complete
-.org 38
- rcall isr ; USART0 Data Register Empty
-.org 40
- rcall isr ; USART0, Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Timer/Counter1 Compare Match C
-.org 50
- rcall isr ; Timer/Counter3 Capture Event
-.org 52
- rcall isr ; Timer/Counter3 Compare Match A
-.org 54
- rcall isr ; Timer/Counter3 Compare Match B
-.org 56
- rcall isr ; Timer/Counter3 Compare Match C
-.org 58
- rcall isr ; Timer/Counter3 Overflow
-.org 60
- rcall isr ; USART1, Rx Complete
-.org 62
- rcall isr ; USART1, Data Register Empty
-.org 64
- rcall isr ; USART1, Tx Complete
-.org 66
- rcall isr ; 2-wire Serial Interface
-.org 68
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 35
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 35
-mcu_name:
- .dw 9
- .db "ATmega128",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128/device.inc b/amforth-6.5/avr8/devices/atmega128/device.inc
deleted file mode 100644
index e6ee249..0000000
--- a/amforth-6.5/avr8/devices/atmega128/device.inc
+++ /dev/null
@@ -1,1179 +0,0 @@
-; Partname: ATmega128
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 114
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw 41
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 155
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 157
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR1H:
- .dw $ff06
- .db "UBRR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1H
-XT_UBRR1H:
- .dw PFA_DOVARIABLE
-PFA_UBRR1H:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR1L:
- .dw $ff06
- .db "UBRR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1L
-XT_UBRR1L:
- .dw PFA_DOVARIABLE
-PFA_UBRR1L:
- .dw 153
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; XTAL Divide Control Register
-VE_XDIV:
- .dw $ff04
- .db "XDIV"
- .dw VE_HEAD
- .set VE_HEAD=VE_XDIV
-XT_XDIV:
- .dw PFA_DOVARIABLE
-PFA_XDIV:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 104
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 66
-
-.endif
-.if WANT_MISC == 1
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 88
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 33
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 98
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 32
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 99
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronus Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 86
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Mask Register
-VE_ETIMSK:
- .dw $ff06
- .db "ETIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIMSK
-XT_ETIMSK:
- .dw PFA_DOVARIABLE
-PFA_ETIMSK:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Flag register
-VE_ETIFR:
- .dw $ff05
- .db "ETIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIFR
-XT_ETIFR:
- .dw PFA_DOVARIABLE
-PFA_ETIFR:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 139
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output compare Register C Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 128
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega128/device.py b/amforth-6.5/avr8/devices/atmega128/device.py
deleted file mode 100644
index fbb8cb1..0000000
--- a/amforth-6.5/avr8/devices/atmega128/device.py
+++ /dev/null
@@ -1,403 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega128
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#36', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#40', # USART0, Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
- 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#60', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#64', # USART1, Tx Complete
- 'TWIAddr' : '#66', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#68', # Store Program Memory Read
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module TWI
- 'TWBR' : '$70', # TWI Bit Rate register
- 'TWCR' : '$74', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$71', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$73', # TWI Data register
- 'TWAR' : '$72', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$2c', # USART I/O Data Register
- 'UCSR0A' : '$2b', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$2a', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$95', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0H' : '$90', # USART Baud Rate Register Hight
- 'UBRR0L' : '$29', # USART Baud Rate Register Low B
-
-# Module USART1
- 'UDR1' : '$9c', # USART I/O Data Register
- 'UCSR1A' : '$9b', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$9a', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$9d', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1H' : '$98', # USART Baud Rate Register Hight
- 'UBRR1L' : '$99', # USART Baud Rate Register Low B
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SRE': '$80', # External SRAM Enable
- 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
- 'MCUCR_SE': '$20', # Sleep Enable
- 'MCUCR_SM': '$18', # Sleep Mode Select
- 'MCUCR_SM2': '$4', # Sleep Mode Select
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$6d', # External Memory Control Regist
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
- 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
- 'XMCRB' : '$6c', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$6f', # Oscillator Calibration Value
- 'XDIV' : '$5c', # XTAL Divide Control Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$68', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$42', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module MISC
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'SFIOR_PUD': '$4', # Pull Up Disable
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
- 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$6a', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$5a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$59', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$58', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$23', # Data Register, Port E
- 'DDRE' : '$22', # Data Direction Register, Port
- 'PINE' : '$21', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$62', # Data Register, Port F
- 'DDRF' : '$61', # Data Direction Register, Port
- 'PINF' : '$20', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$65', # Data Register, Port G
- 'DDRG' : '$64', # Data Direction Register, Port
- 'PING' : '$63', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$51', # Output Compare Register
- 'ASSR' : '$50', # Asynchronus Status Register
- 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
- 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
- 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
- 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'OCR1C' : '$78', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$45', # Timer/Counter Control Register
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
- 'TCCR2_COM2': '$30', # Compare Match Output Mode
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select
- 'TCNT2' : '$44', # Timer/Counter Register
- 'OCR2' : '$43', # Output Compare Register
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TIMSK' : '$57', #
- 'TIMSK_OCIE2': '$80', #
- 'TIMSK_TOIE2': '$40', #
-
-# Module TIMER_COUNTER_3
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
- 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
- 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
- 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
- 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_ICF3': '$20', # Input Capture Flag 1
- 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
- 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
- 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
- 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
- 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
- 'TCNT3' : '$88', # Timer/Counter3 Bytes
- 'OCR3A' : '$86', # Timer/Counter3 Output Compare
- 'OCR3B' : '$84', # Timer/Counter3 Output Compare
- 'OCR3C' : '$82', # Timer/Counter3 Output compare
- 'ICR3' : '$80', # Timer/Counter3 Input Capture R
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADFR': '$20', # ADC Free Running Select
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$24', # ADC Data Register Bytes
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega128/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1280/atmega1280.frt b/amforth-6.5/avr8/devices/atmega1280/atmega1280.frt
deleted file mode 100644
index 6fef8ef..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/atmega1280.frt
+++ /dev/null
@@ -1,580 +0,0 @@
-\ Partname: ATmega1280
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ PORTH
-&258 constant PORTH \ PORT H Data Register
-&257 constant DDRH \ PORT H Data Direction Register
-&256 constant PINH \ PORT H Input Pins
-\ PORTJ
-&261 constant PORTJ \ PORT J Data Register
-&260 constant DDRJ \ PORT J Data Direction Register
-&259 constant PINJ \ PORT J Input Pins
-\ PORTK
-&264 constant PORTK \ PORT K Data Register
-&263 constant DDRK \ PORT K Data Direction Register
-&262 constant PINK \ PORT K Input Pins
-\ PORTL
-&267 constant PORTL \ PORT L Data Register
-&266 constant DDRL \ PORT L Data Direction Register
-&265 constant PINL \ PORT L Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
- $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
- $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
-&290 constant TCCR5C \ Timer/Counter 5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
- $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
- $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
- $20 constant TIFR5_ICF5 \ Input Capture Flag 5
- $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
- $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
- $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
-&162 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
- $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
- $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $20 constant TIFR4_ICF4 \ Input Capture Flag 4
- $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
- $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Power Reduction USART3
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&125 constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \
- $40 constant DIDR2_ADC14D \
- $20 constant DIDR2_ADC13D \
- $10 constant DIDR2_ADC12D \
- $08 constant DIDR2_ADC11D \
- $04 constant DIDR2_ADC10D \
- $02 constant DIDR2_ADC9D \
- $01 constant DIDR2_ADC8D \
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART2
-&214 constant UDR2 \ USART I/O Data Register
-&208 constant UCSR2A \ USART Control and Status Register A
- $80 constant UCSR2A_RXC2 \ USART Receive Complete
- $40 constant UCSR2A_TXC2 \ USART Transmitt Complete
- $20 constant UCSR2A_UDRE2 \ USART Data Register Empty
- $10 constant UCSR2A_FE2 \ Framing Error
- $08 constant UCSR2A_DOR2 \ Data overRun
- $04 constant UCSR2A_UPE2 \ Parity Error
- $02 constant UCSR2A_U2X2 \ Double the USART transmission speed
- $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode
-&209 constant UCSR2B \ USART Control and Status Register B
- $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
- $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
- $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR2B_RXEN2 \ Receiver Enable
- $08 constant UCSR2B_TXEN2 \ Transmitter Enable
- $04 constant UCSR2B_UCSZ22 \ Character Size
- $02 constant UCSR2B_RXB82 \ Receive Data Bit 8
- $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8
-&210 constant UCSR2C \ USART Control and Status Register C
- $C0 constant UCSR2C_UMSEL2 \ USART Mode Select
- $30 constant UCSR2C_UPM2 \ Parity Mode Bits
- $08 constant UCSR2C_USBS2 \ Stop Bit Select
- $06 constant UCSR2C_UCSZ2 \ Character Size
- $01 constant UCSR2C_UCPOL2 \ Clock Polarity
-&212 constant UBRR2 \ USART Baud Rate Register Bytes
-\ USART3
-&310 constant UDR3 \ USART I/O Data Register
-&304 constant UCSR3A \ USART Control and Status Register A
- $80 constant UCSR3A_RXC3 \ USART Receive Complete
- $40 constant UCSR3A_TXC3 \ USART Transmitt Complete
- $20 constant UCSR3A_UDRE3 \ USART Data Register Empty
- $10 constant UCSR3A_FE3 \ Framing Error
- $08 constant UCSR3A_DOR3 \ Data overRun
- $04 constant UCSR3A_UPE3 \ Parity Error
- $02 constant UCSR3A_U2X3 \ Double the USART transmission speed
- $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode
-&305 constant UCSR3B \ USART Control and Status Register B
- $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
- $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
- $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR3B_RXEN3 \ Receiver Enable
- $08 constant UCSR3B_TXEN3 \ Transmitter Enable
- $04 constant UCSR3B_UCSZ32 \ Character Size
- $02 constant UCSR3B_RXB83 \ Receive Data Bit 8
- $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8
-&306 constant UCSR3C \ USART Control and Status Register C
- $C0 constant UCSR3C_UMSEL3 \ USART Mode Select
- $30 constant UCSR3C_UPM3 \ Parity Mode Bits
- $08 constant UCSR3C_USBS3 \ Stop Bit Select
- $06 constant UCSR3C_UCSZ3 \ Character Size
- $01 constant UCSR3C_UCPOL3 \ Clock Polarity
-&308 constant UBRR3 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0__RXAddr \ USART0, Rx Complete
-&52 constant USART0__UDREAddr \ USART0 Data register Empty
-&54 constant USART0__TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1__RXAddr \ USART1, Rx Complete
-&74 constant USART1__UDREAddr \ USART1 Data register Empty
-&76 constant USART1__TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2__RXAddr \ USART2, Rx Complete
-&104 constant USART2__UDREAddr \ USART2 Data register Empty
-&106 constant USART2__TXAddr \ USART2, Tx Complete
-&108 constant USART3__RXAddr \ USART3, Rx Complete
-&110 constant USART3__UDREAddr \ USART3 Data register Empty
-&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega1280/device.asm b/amforth-6.5/avr8/devices/atmega1280/device.asm
deleted file mode 100644
index c30b89b..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/device.asm
+++ /dev/null
@@ -1,190 +0,0 @@
-; Partname: ATmega1280
-; generated automatically, do not edit
-
-.nolist
- .include "m1280def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_PORTK = 0
-.set WANT_PORTL = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_USART1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART2 = 0
-.set WANT_USART3 = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.equ INTVECTORS = 57
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 57
-mcu_name:
- .dw 10
- .db "ATmega1280"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1280/device.inc b/amforth-6.5/avr8/devices/atmega1280/device.inc
deleted file mode 100644
index 48553d2..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/device.inc
+++ /dev/null
@@ -1,1980 +0,0 @@
-; Partname: ATmega1280
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 258
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 257
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 256
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 261
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 260
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 259
-
-.endif
-.if WANT_PORTK == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Data Register
-VE_PORTK:
- .dw $ff05
- .db "PORTK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTK
-XT_PORTK:
- .dw PFA_DOVARIABLE
-PFA_PORTK:
- .dw 264
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Data Direction Register
-VE_DDRK:
- .dw $ff04
- .db "DDRK"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRK
-XT_DDRK:
- .dw PFA_DOVARIABLE
-PFA_DDRK:
- .dw 263
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Input Pins
-VE_PINK:
- .dw $ff04
- .db "PINK"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINK
-XT_PINK:
- .dw PFA_DOVARIABLE
-PFA_PINK:
- .dw 262
-
-.endif
-.if WANT_PORTL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Data Register
-VE_PORTL:
- .dw $ff05
- .db "PORTL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTL
-XT_PORTL:
- .dw PFA_DOVARIABLE
-PFA_PORTL:
- .dw 267
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Data Direction Register
-VE_DDRL:
- .dw $ff04
- .db "DDRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRL
-XT_DDRL:
- .dw PFA_DOVARIABLE
-PFA_DDRL:
- .dw 266
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Input Pins
-VE_PINL:
- .dw $ff04
- .db "PINL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINL
-XT_PINL:
- .dw PFA_DOVARIABLE
-PFA_PINL:
- .dw 265
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR2:
- .dw $ff04
- .db "UDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR2
-XT_UDR2:
- .dw PFA_DOVARIABLE
-PFA_UDR2:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR2A:
- .dw $ff06
- .db "UCSR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2A
-XT_UCSR2A:
- .dw PFA_DOVARIABLE
-PFA_UCSR2A:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR2B:
- .dw $ff06
- .db "UCSR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2B
-XT_UCSR2B:
- .dw PFA_DOVARIABLE
-PFA_UCSR2B:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR2C:
- .dw $ff06
- .db "UCSR2C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2C
-XT_UCSR2C:
- .dw PFA_DOVARIABLE
-PFA_UCSR2C:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR2:
- .dw $ff05
- .db "UBRR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR2
-XT_UBRR2:
- .dw PFA_DOVARIABLE
-PFA_UBRR2:
- .dw 212
-
-.endif
-.if WANT_USART3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR3:
- .dw $ff04
- .db "UDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR3
-XT_UDR3:
- .dw PFA_DOVARIABLE
-PFA_UDR3:
- .dw 310
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR3A:
- .dw $ff06
- .db "UCSR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3A
-XT_UCSR3A:
- .dw PFA_DOVARIABLE
-PFA_UCSR3A:
- .dw 304
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR3B:
- .dw $ff06
- .db "UCSR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3B
-XT_UCSR3B:
- .dw PFA_DOVARIABLE
-PFA_UCSR3B:
- .dw 305
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR3C:
- .dw $ff06
- .db "UCSR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3C
-XT_UCSR3C:
- .dw PFA_DOVARIABLE
-PFA_UCSR3C:
- .dw 306
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR3:
- .dw $ff05
- .db "UBRR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR3
-XT_UBRR3:
- .dw PFA_DOVARIABLE
-PFA_UBRR3:
- .dw 308
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega1280/device.py b/amforth-6.5/avr8/devices/atmega1280/device.py
deleted file mode 100644
index 8750d77..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/device.py
+++ /dev/null
@@ -1,633 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega1280
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module PORTH
- 'PORTH' : '$102', # PORT H Data Register
- 'DDRH' : '$101', # PORT H Data Direction Register
- 'PINH' : '$100', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$105', # PORT J Data Register
- 'DDRJ' : '$104', # PORT J Data Direction Register
- 'PINJ' : '$103', # PORT J Input Pins
-
-# Module PORTK
- 'PORTK' : '$108', # PORT K Data Register
- 'DDRK' : '$107', # PORT K Data Direction Register
- 'PINK' : '$106', # PORT K Input Pins
-
-# Module PORTL
- 'PORTL' : '$10b', # PORT L Data Register
- 'DDRL' : '$10a', # PORT L Data Direction Register
- 'PINL' : '$109', # PORT L Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
- 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
- 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
- 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
- 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
- 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_ICF5': '$20', # Input Capture Flag 5
- 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
- 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
- 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
- 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
- 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
- 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
- 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_ICF4': '$20', # Input Capture Flag 4
- 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
- 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
- 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Power Reduction USART3
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', #
- 'DIDR2_ADC14D': '$40', #
- 'DIDR2_ADC13D': '$20', #
- 'DIDR2_ADC12D': '$10', #
- 'DIDR2_ADC11D': '$8', #
- 'DIDR2_ADC10D': '$4', #
- 'DIDR2_ADC9D': '$2', #
- 'DIDR2_ADC8D': '$1', #
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART2
- 'UDR2' : '$d6', # USART I/O Data Register
- 'UCSR2A' : '$d0', # USART Control and Status Regis
- 'UCSR2A_RXC2': '$80', # USART Receive Complete
- 'UCSR2A_TXC2': '$40', # USART Transmitt Complete
- 'UCSR2A_UDRE2': '$20', # USART Data Register Empty
- 'UCSR2A_FE2': '$10', # Framing Error
- 'UCSR2A_DOR2': '$8', # Data overRun
- 'UCSR2A_UPE2': '$4', # Parity Error
- 'UCSR2A_U2X2': '$2', # Double the USART transmission
- 'UCSR2A_MPCM2': '$1', # Multi-processor Communication
- 'UCSR2B' : '$d1', # USART Control and Status Regis
- 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable
- 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable
- 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte
- 'UCSR2B_RXEN2': '$10', # Receiver Enable
- 'UCSR2B_TXEN2': '$8', # Transmitter Enable
- 'UCSR2B_UCSZ22': '$4', # Character Size
- 'UCSR2B_RXB82': '$2', # Receive Data Bit 8
- 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8
- 'UCSR2C' : '$d2', # USART Control and Status Regis
- 'UCSR2C_UMSEL2': '$c0', # USART Mode Select
- 'UCSR2C_UPM2': '$30', # Parity Mode Bits
- 'UCSR2C_USBS2': '$8', # Stop Bit Select
- 'UCSR2C_UCSZ2': '$6', # Character Size
- 'UCSR2C_UCPOL2': '$1', # Clock Polarity
- 'UBRR2' : '$d4', # USART Baud Rate Register Byte
-
-# Module USART3
- 'UDR3' : '$136', # USART I/O Data Register
- 'UCSR3A' : '$130', # USART Control and Status Regis
- 'UCSR3A_RXC3': '$80', # USART Receive Complete
- 'UCSR3A_TXC3': '$40', # USART Transmitt Complete
- 'UCSR3A_UDRE3': '$20', # USART Data Register Empty
- 'UCSR3A_FE3': '$10', # Framing Error
- 'UCSR3A_DOR3': '$8', # Data overRun
- 'UCSR3A_UPE3': '$4', # Parity Error
- 'UCSR3A_U2X3': '$2', # Double the USART transmission
- 'UCSR3A_MPCM3': '$1', # Multi-processor Communication
- 'UCSR3B' : '$131', # USART Control and Status Regis
- 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable
- 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable
- 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte
- 'UCSR3B_RXEN3': '$10', # Receiver Enable
- 'UCSR3B_TXEN3': '$8', # Transmitter Enable
- 'UCSR3B_UCSZ32': '$4', # Character Size
- 'UCSR3B_RXB83': '$2', # Receive Data Bit 8
- 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8
- 'UCSR3C' : '$132', # USART Control and Status Regis
- 'UCSR3C_UMSEL3': '$c0', # USART Mode Select
- 'UCSR3C_UPM3': '$30', # Parity Mode Bits
- 'UCSR3C_USBS3': '$8', # Stop Bit Select
- 'UCSR3C_UCSZ3': '$6', # Character Size
- 'UCSR3C_UCPOL3': '$1', # Clock Polarity
- 'UBRR3' : '$134', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1280/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1280/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega1280/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1281/atmega1281.frt b/amforth-6.5/avr8/devices/atmega1281/atmega1281.frt
deleted file mode 100644
index 2c2516b..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/atmega1281.frt
+++ /dev/null
@@ -1,509 +0,0 @@
-\ Partname: ATmega1281
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
- $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
- $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
-&290 constant TCCR5C \ Timer/Counter 5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
- $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
- $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
- $20 constant TIFR5_ICF5 \ Input Capture Flag 5
- $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
- $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
- $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
-&162 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
- $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
- $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $20 constant TIFR4_ICF4 \ Input Capture Flag 4
- $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
- $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&125 constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \
- $40 constant DIDR2_ADC14D \
- $20 constant DIDR2_ADC13D \
- $10 constant DIDR2_ADC12D \
- $08 constant DIDR2_ADC11D \
- $04 constant DIDR2_ADC10D \
- $02 constant DIDR2_ADC9D \
- $01 constant DIDR2_ADC8D \
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Power Reduction USART3
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0__RXAddr \ USART0, Rx Complete
-&52 constant USART0__UDREAddr \ USART0 Data register Empty
-&54 constant USART0__TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1__RXAddr \ USART1, Rx Complete
-&74 constant USART1__UDREAddr \ USART1 Data register Empty
-&76 constant USART1__TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2__RXAddr \ USART2, Rx Complete
-&104 constant USART2__UDREAddr \ USART2 Data register Empty
-&106 constant USART2__TXAddr \ USART2, Tx Complete
-&108 constant USART3__RXAddr \ USART3, Rx Complete
-&110 constant USART3__UDREAddr \ USART3 Data register Empty
-&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega1281/device.asm b/amforth-6.5/avr8/devices/atmega1281/device.asm
deleted file mode 100644
index cc65436..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/device.asm
+++ /dev/null
@@ -1,184 +0,0 @@
-; Partname: ATmega1281
-; generated automatically, do not edit
-
-.nolist
- .include "m1281def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.equ INTVECTORS = 57
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 57
-mcu_name:
- .dw 10
- .db "ATmega1281"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1281/device.inc b/amforth-6.5/avr8/devices/atmega1281/device.inc
deleted file mode 100644
index f9f4a06..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/device.inc
+++ /dev/null
@@ -1,1686 +0,0 @@
-; Partname: ATmega1281
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega1281/device.py b/amforth-6.5/avr8/devices/atmega1281/device.py
deleted file mode 100644
index 8f3d69e..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/device.py
+++ /dev/null
@@ -1,556 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega1281
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
- 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
- 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
- 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
- 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
- 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_ICF5': '$20', # Input Capture Flag 5
- 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
- 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
- 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
- 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
- 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
- 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
- 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_ICF4': '$20', # Input Capture Flag 4
- 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
- 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
- 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', #
- 'DIDR2_ADC14D': '$40', #
- 'DIDR2_ADC13D': '$20', #
- 'DIDR2_ADC12D': '$10', #
- 'DIDR2_ADC11D': '$8', #
- 'DIDR2_ADC10D': '$4', #
- 'DIDR2_ADC9D': '$2', #
- 'DIDR2_ADC8D': '$1', #
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Power Reduction USART3
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1281/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1281/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega1281/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284/atmega1284.frt b/amforth-6.5/avr8/devices/atmega1284/atmega1284.frt
deleted file mode 100644
index 6b3a352..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/atmega1284.frt
+++ /dev/null
@@ -1,380 +0,0 @@
-\ Partname: ATmega1284
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
- $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
- $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode Bits
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&146 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-&101 constant PRR1 \ Power Reduction Register1
- $01 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
diff --git a/amforth-6.5/avr8/devices/atmega1284/device.asm b/amforth-6.5/avr8/devices/atmega1284/device.asm
deleted file mode 100644
index 6d89a60..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/device.asm
+++ /dev/null
@@ -1,135 +0,0 @@
-; Partname: ATmega1284
-; generated automatically, do not edit
-
-.nolist
- .include "m1284def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Overflow
-.equ INTVECTORS = 35
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 16384
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 35
-mcu_name:
- .dw 10
- .db "ATmega1284"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1284/device.inc b/amforth-6.5/avr8/devices/atmega1284/device.inc
deleted file mode 100644
index 0242304..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/device.inc
+++ /dev/null
@@ -1,1263 +0,0 @@
-; Partname: ATmega1284
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega1284/device.py b/amforth-6.5/avr8/devices/atmega1284/device.py
deleted file mode 100644
index 0b316cb..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/device.py
+++ /dev/null
@@ -1,421 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega1284
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_OVFAddr' : '#68', # Timer/Counter3 Overflow
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module TIMER_COUNTER_3
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode Bits
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM3': '$1', # Power Reduction Timer/Counter3
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1284/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega1284/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt b/amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt
deleted file mode 100644
index 2419609..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt
+++ /dev/null
@@ -1,380 +0,0 @@
-\ Partname: ATmega1284P
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
- $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
- $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode Bits
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&146 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-&101 constant PRR1 \ Power Reduction Register1
- $01 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
diff --git a/amforth-6.5/avr8/devices/atmega1284p/device.asm b/amforth-6.5/avr8/devices/atmega1284p/device.asm
deleted file mode 100644
index e8d1391..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/device.asm
+++ /dev/null
@@ -1,135 +0,0 @@
-; Partname: ATmega1284P
-; generated automatically, do not edit
-
-.nolist
- .include "m1284Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Overflow
-.equ INTVECTORS = 35
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 16384
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 35
-mcu_name:
- .dw 11
- .db "ATmega1284P",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1284p/device.inc b/amforth-6.5/avr8/devices/atmega1284p/device.inc
deleted file mode 100644
index 718a658..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/device.inc
+++ /dev/null
@@ -1,1263 +0,0 @@
-; Partname: ATmega1284P
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega1284p/device.py b/amforth-6.5/avr8/devices/atmega1284p/device.py
deleted file mode 100644
index 73725c6..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/device.py
+++ /dev/null
@@ -1,423 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega1284P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_OVFAddr' : '#68', # Timer/Counter3 Overflow
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module TIMER_COUNTER_3
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode Bits
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM3': '$1', # Power Reduction Timer/Counter3
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt
deleted file mode 100644
index 5920fc8..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,79 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index 0479c7f..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt
deleted file mode 100644
index 8d5a583..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt
deleted file mode 100644
index ba7a278..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt
+++ /dev/null
@@ -1,128 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fe constant RAMPZ_Res \ Reserved
- 5b $fe bitmask: RAMPZ.Res \ Reserved
- $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
- 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt
deleted file mode 100644
index 50cdbc0..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 2db4353..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,45 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt
deleted file mode 100644
index de5d33e..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt
+++ /dev/null
@@ -1,16 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt
deleted file mode 100644
index 52b3f90..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt
deleted file mode 100644
index e369e36..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt
deleted file mode 100644
index 1dd5691..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt
deleted file mode 100644
index f3b7289..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt
deleted file mode 100644
index 50a7df1..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt
deleted file mode 100644
index acc7ee9..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt
deleted file mode 100644
index a7a1d12..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt
deleted file mode 100644
index 7b07cf8..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt
deleted file mode 100644
index 1a76e14..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt
+++ /dev/null
@@ -1,81 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt
deleted file mode 100644
index e4945a3..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt
deleted file mode 100644
index fe7500d..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt
+++ /dev/null
@@ -1,156 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt
deleted file mode 100644
index c3d1a1f..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index 1f9a23d..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt
deleted file mode 100644
index 785cfdd..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt
+++ /dev/null
@@ -1,67 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt
deleted file mode 100644
index 3a545ee..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt
deleted file mode 100644
index 0ccc3bd..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt
deleted file mode 100644
index b3b9e55..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt
deleted file mode 100644
index 12d310a..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt
+++ /dev/null
@@ -1,495 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt
deleted file mode 100644
index bb68925..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt
+++ /dev/null
@@ -1,40 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt
deleted file mode 100644
index 7532d38..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt
deleted file mode 100644
index cde1b1b..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt
deleted file mode 100644
index 9656f84..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt
deleted file mode 100644
index 701f21f..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt
deleted file mode 100644
index ae1c311..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for atmega1284rfr2
-\ #require bitnames.frt
-
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/device.asm b/amforth-6.5/avr8/devices/atmega1284rfr2/device.asm
deleted file mode 100644
index 49846c0..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/device.asm
+++ /dev/null
@@ -1,166 +0,0 @@
-; Generated Automatically
-
-.nolist
- include "m1284RFR2def.inc"
-.list
-FLASHSTART = 0
-FLASHSIZE = 131072
-RAMEND = 16896
-IRAMSTART = 512
-IRAMSIZE = 16384
-EEPROMSIZE = 4096
-; Interrupt Vectors
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.org 114
- rcall isr ; TRX24 - PLL lock interrupt
-.org 116
- rcall isr ; TRX24 - PLL unlock interrupt
-.org 118
- rcall isr ; TRX24 - Receive start interrupt
-.org 120
- rcall isr ; TRX24 - RX_END interrupt
-.org 122
- rcall isr ; TRX24 - CCA/ED done interrupt
-.org 124
- rcall isr ; TRX24 - XAH - AMI
-.org 126
- rcall isr ; TRX24 - TX_END interrupt
-.org 128
- rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-.org 130
- rcall isr ; Symbol counter - compare match 1 interrupt
-.org 132
- rcall isr ; Symbol counter - compare match 2 interrupt
-.org 134
- rcall isr ; Symbol counter - compare match 3 interrupt
-.org 136
- rcall isr ; Symbol counter - overflow interrupt
-.org 138
- rcall isr ; Symbol counter - backoff interrupt
-.org 140
- rcall isr ; AES engine ready interrupt
-.org 142
- rcall isr ; Battery monitor indicates supply voltage below threshold
-.org 144
- rcall isr ; TRX24 TX start interrupt
-.org 146
- rcall isr ; Address match interrupt of address filter 0
-.org 148
- rcall isr ; Address match interrupt of address filter 1
-.org 150
- rcall isr ; Address match interrupt of address filter 2
-.org 152
- rcall isr ; Address match interrupt of address filter 3
-.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/device.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/device.frt
deleted file mode 100644
index a844898..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/device.frt
+++ /dev/null
@@ -1,1752 +0,0 @@
-\ Generated Automatically
-
-\ Interrupt Vectors
-#2 constant INT0Addr \ External Interrupt Request 0
-#4 constant INT1Addr \ External Interrupt Request 1
-#6 constant INT2Addr \ External Interrupt Request 2
-#8 constant INT3Addr \ External Interrupt Request 3
-#10 constant INT4Addr \ External Interrupt Request 4
-#12 constant INT5Addr \ External Interrupt Request 5
-#14 constant INT6Addr \ External Interrupt Request 6
-#16 constant INT7Addr \ External Interrupt Request 7
-#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-#24 constant WDTAddr \ Watchdog Time-out Interrupt
-#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
-#50 constant USART0_RXAddr \ USART0, Rx Complete
-#52 constant USART0_UDREAddr \ USART0 Data register Empty
-#54 constant USART0_TXAddr \ USART0, Tx Complete
-#56 constant ANALOG_COMPAddr \ Analog Comparator
-#58 constant ADCAddr \ ADC Conversion Complete
-#60 constant EE_READYAddr \ EEPROM Ready
-#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-#72 constant USART1_RXAddr \ USART1, Rx Complete
-#74 constant USART1_UDREAddr \ USART1 Data register Empty
-#76 constant USART1_TXAddr \ USART1, Tx Complete
-#78 constant TWIAddr \ 2-wire Serial Interface
-#80 constant SPM_READYAddr \ Store Program Memory Read
-#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-#102 constant USART2_RXAddr \ USART2, Rx Complete
-#104 constant USART2_UDREAddr \ USART2 Data register Empty
-#106 constant USART2_TXAddr \ USART2, Tx Complete
-#108 constant USART3_RXAddr \ USART3, Rx Complete
-#110 constant USART3_UDREAddr \ USART3 Data register Empty
-#112 constant USART3_TXAddr \ USART3, Tx Complete
-#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
-#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
-#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
-#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
-#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
-#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
-#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
-#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
-#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
-#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
-#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
-#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
-#140 constant AES_READYAddr \ AES engine ready interrupt
-#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
-#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
-#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
-#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
-#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
-#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fe constant RAMPZ_Res \ Reserved
- 5b $fe bitmask: RAMPZ.Res \ Reserved
- $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
- 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/device.py b/amforth-6.5/avr8/devices/atmega1284rfr2/device.py
deleted file mode 100644
index fbea858..0000000
--- a/amforth-6.5/avr8/devices/atmega1284rfr2/device.py
+++ /dev/null
@@ -1,1103 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega1284RFR2
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
- 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
- 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
- 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
- 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
- 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
- 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
- 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
- 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
- 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
- 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
- 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
- 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
- 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
- 'AES_READYAddr' : '#140', # AES engine ready interrupt
- 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
- 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
- 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
- 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
- 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
- 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART0 I/O Data Register
- 'UCSR0A' : '$c0', # USART0 Control and Status Regi
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Frame Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART0 Control and Status Regi
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART0 Control and Status Regi
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART1 I/O Data Register
- 'UCSR1A' : '$c8', # USART1 Control and Status Regi
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Frame Error
- 'UCSR1A_DOR1': '$8', # Data OverRun
- 'UCSR1A_UPE1': '$4', # USART Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART Transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART1 Control and Status Regi
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART1 Control and Status Regi
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', # TWI Address Mask
- 'TWAMR_Res': '$1', # Reserved Bit
- 'TWBR' : '$b8', # TWI Bit Rate Register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI START Condition Bit
- 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collision Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_Res': '$2', # Reserved Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_Res': '$4', # Reserved Bit
- 'TWSR_TWPS': '$3', # TWI Prescaler Bits
- 'TWDR' : '$bb', # TWI Data Register
- 'TWAR' : '$ba', # TWI (Slave) Address Register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_Res': '$3e', # Reserved
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins Address
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins Address
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins Address
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins Address
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins Address
-
-# Module PORTF
- 'PORTF' : '$31', # Port F Data Register
- 'DDRF' : '$30', # Port F Data Direction Register
- 'PINF' : '$2f', # Port F Input Pins Address
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins Address
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0 Register
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_Res': '$30', # Reserved Bit
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
- 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
- 'TCCR0A_Res': '$c', # Reserved Bit
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_Res': '$f8', # Reserved
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_Res': '$f8', # Reserved
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_Res': '$7c', # Reserved
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_Res': '$f8', # Reserved Bit
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_Res': '$f8', # Reserved Bit
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
- 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
- 'TCCR2A_Res': '$c', # Reserved
- 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_Res': '$30', # Reserved
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
- 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
- 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
- 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
- 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
- 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_Res': '$20', # Reserved Bit
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Clock Select
- 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
- 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
- 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
- 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
- 'TCCR5C_Res': '$1f', # Reserved
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_Res': '$c0', # Reserved Bit
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_Res': '$10', # Reserved Bit
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_Res': '$c0', # Reserved Bit
- 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
- 'TIFR5_Res': '$10', # Reserved Bit
- 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
- 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
- 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_Res': '$20', # Reserved Bit
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Clock Select
- 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
- 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
- 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
- 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
- 'TCCR4C_Res': '$1f', # Reserved
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_Res': '$c0', # Reserved Bit
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_Res': '$10', # Reserved Bit
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_Res': '$c0', # Reserved Bit
- 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
- 'TIFR4_Res': '$10', # Reserved Bit
- 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
- 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
- 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_Res': '$20', # Reserved Bit
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
- 'TCCR3C_Res': '$1f', # Reserved
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_Res': '$c0', # Reserved Bit
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_Res': '$10', # Reserved Bit
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_Res': '$c0', # Reserved Bit
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_Res': '$10', # Reserved Bit
- 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
- 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
- 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_Res': '$20', # Reserved Bit
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
- 'TCCR1C_Res': '$1f', # Reserved
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_Res': '$c0', # Reserved Bit
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_Res': '$10', # Reserved Bit
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_Res': '$c0', # Reserved Bit
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_Res': '$10', # Reserved Bit
- 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TRX24
- 'PARCR' : '$138', # Power Amplifier Ramp up/down C
- 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
- 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
- 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
- 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
- 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
- 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
- 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
- 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
- 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
- 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA1L' : '$112', # Transceiver MAC Short Address
- 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
- 'MAFSA1H' : '$113', # Transceiver MAC Short Address
- 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
- 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
- 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA2L' : '$116', # Transceiver MAC Short Address
- 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
- 'MAFSA2H' : '$117', # Transceiver MAC Short Address
- 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
- 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
- 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
- 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
- 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
- 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
- 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
- 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
- 'MAFCR0' : '$10c', # Multiple Address Filter Config
- 'MAFCR0_Res': '$f0', # Reserved Bit
- 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
- 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
- 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
- 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
- 'MAFCR1' : '$10d', # Multiple Address Filter Config
- 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
- 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
- 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
- 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
- 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
- 'AES_CTRL' : '$13c', # AES Control Register
- 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
- 'AES_CTRL_Res': '$40', # Reserved Bit
- 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
- 'AES_CTRL_Res': '$10', # Reserved Bit
- 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
- 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
- 'AES_CTRL_Res': '$3', # Reserved Bit
- 'AES_STATUS' : '$13d', # AES Status Register
- 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
- 'AES_STATUS_Res': '$7e', # Reserved
- 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
- 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
- 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
- 'AES_KEY' : '$13f', # AES Encryption and Decryption
- 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
- 'TRX_STATUS' : '$141', # Transceiver Status Register
- 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
- 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
- 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
- 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
- 'TRX_STATE' : '$142', # Transceiver State Control Regi
- 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
- 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
- 'TRX_CTRL_0' : '$143', # Reserved
- 'TRX_CTRL_0_Res7': '$80', # Reserved
- 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
- 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
- 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
- 'TRX_CTRL_0_Res': '$f', # Reserved
- 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
- 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
- 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
- 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
- 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
- 'TRX_CTRL_1_Res': '$f', # Reserved
- 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
- 'PHY_TX_PWR_Res': '$f0', # Reserved
- 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
- 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
- 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
- 'PHY_RSSI_RND_VALUE': '$60', # Random Value
- 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
- 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
- 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
- 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
- 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
- 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
- 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
- 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
- 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
- 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
- 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
- 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
- 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
- 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
- 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
- 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
- 'TRX_CTRL_2_Res': '$7c', # Reserved
- 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
- 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
- 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
- 'ANT_DIV_Res': '$70', # Reserved
- 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
- 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
- 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
- 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
- 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
- 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
- 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
- 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
- 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
- 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
- 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
- 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
- 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
- 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
- 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
- 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
- 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
- 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
- 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
- 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
- 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
- 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
- 'IRQ_MASK1_Res': '$e0', # Reserved Bit
- 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
- 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
- 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
- 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
- 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
- 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
- 'VREG_CTRL' : '$150', # Voltage Regulator Control and
- 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
- 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
- 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
- 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
- 'BATMON' : '$151', # Battery Monitor Control and St
- 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
- 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
- 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
- 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
- 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
- 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
- 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
- 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
- 'CC_CTRL_0' : '$153', # Channel Control Register 0
- 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
- 'CC_CTRL_1' : '$154', # Channel Control Register 1
- 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
- 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
- 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
- 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
- 'RX_SYN_Res': '$30', # Reserved
- 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
- 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
- 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
- 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
- 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
- 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
- 'TRX_RPC_Res0': '$4', # Reserved
- 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
- 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
- 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
- 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
- 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
- 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
- 'XAH_CTRL_1_Res': '$8', # Reserved Bit
- 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
- 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
- 'XAH_CTRL_1_Res': '$1', # Reserved Bit
- 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
- 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
- 'PLL_CF' : '$15a', # Transceiver Center Frequency C
- 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
- 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
- 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
- 'PART_NUM' : '$15c', # Device Identification Register
- 'PART_NUM_PART_NUM': '$ff', # Part Number
- 'VERSION_NUM' : '$15d', # Device Identification Register
- 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
- 'MAN_ID_0' : '$15e', # Device Identification Register
- 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
- 'MAN_ID_1' : '$15f', # Device Identification Register
- 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
- 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
- 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
- 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
- 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
- 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
- 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
- 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
- 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
- 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
- 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
- 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
- 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
- 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
- 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
- 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
- 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
- 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
- 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
- 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
- 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
- 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
- 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
- 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
- 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
- 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
- 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
- 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
- 'TRXFBST' : '$180', # Start of frame buffer
- 'TRXFBEND' : '$1ff', # End of frame buffer
-
-# Module SYMCNT
- 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
- 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
- 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
- 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
- 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
- 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
- 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
- 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
- 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
- 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
- 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
- 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
- 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
- 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
- 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
- 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
- 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
- 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
- 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
- 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
- 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
- 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
- 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
- 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
- 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
- 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
- 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
- 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
- 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
- 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
- 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
- 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
- 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
- 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
- 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
- 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
- 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
- 'SCIRQS_Res': '$e0', # Reserved Bit
- 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
- 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
- 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
- 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
- 'SCIRQM_Res': '$e0', # Reserved Bit
- 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
- 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
- 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
- 'SCSR' : '$de', # Symbol Counter Status Register
- 'SCSR_Res': '$fe', # Reserved Bit
- 'SCSR_SCBSY': '$1', # Symbol Counter busy
- 'SCCR1' : '$dd', # Symbol Counter Control Registe
- 'SCCR1_Res': '$c0', # Reserved Bit
- 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
- 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
- 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
- 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
- 'SCCR0' : '$dc', # Symbol Counter Control Registe
- 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
- 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
- 'SCCR0_SCEN': '$20', # Symbol Counter enable
- 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
- 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
- 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
- 'SCCSR' : '$db', # Symbol Counter Compare Source
- 'SCCSR_Res': '$c0', # Reserved Bit
- 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
- 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
- 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
- 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
- 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
- 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
- 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
- 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_Res': '$c0', # Reserved
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
- 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
- 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
- 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
- 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
- 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
- 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request Ena
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flag
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_Res': '$f8', # Reserved Bit
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_Res': '$f8', # Reserved Bit
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC Multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status Reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status Reg
- 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ADCSRB_REFOK': '$20', # Reference Voltage OK
- 'ADCSRB_ACCH': '$10', # Analog Channel Change
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
- 'ADCSRC' : '$77', # The ADC Control and Status Reg
- 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
- 'ADCSRC_Res0': '$20', # Reserved
- 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', # Reserved Bits
- 'DIDR2_ADC14D': '$40', # Reserved Bits
- 'DIDR2_ADC13D': '$20', # Reserved Bits
- 'DIDR2_ADC12D': '$10', # Reserved Bits
- 'DIDR2_ADC11D': '$8', # Reserved Bits
- 'DIDR2_ADC10D': '$4', # Reserved Bits
- 'DIDR2_ADC9D': '$2', # Reserved Bits
- 'DIDR2_ADC8D': '$1', # Reserved Bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_Res': '$60', # Reserved
- 'MCUCR_PUD': '$10', # Pull-up Disable
- 'MCUCR_Res': '$c', # Reserved
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_Res': '$e0', # Reserved
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on Reset Flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_Res': '$70', # Reserved
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_Res': '$f0', # Reserved
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
- 'RAMPZ_Res': '$fe', # Reserved
- 'RAMPZ_RAMPZ0': '$1', # Extended Z-Pointer Value
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
- 'PRR2' : '$63', # Power Reduction Register 2
- 'PRR2_Res': '$f0', # Reserved Bit
- 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
- 'PRR1' : '$65', # Power Reduction Register 1
- 'PRR1_Res': '$80', # Reserved Bit
- 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRPGA': '$10', # Power Reduction PGA
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module FLASH
- 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
- 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
- 'NEMCR_AEAM': '$30', # Address for Extended Address M
- 'BGCR' : '$67', # Reference Voltage Calibration
- 'BGCR_Res': '$80', # Reserved Bit
- 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
- 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
-
-# Module PWRCTRL
- 'TRXPR' : '$139', # Transceiver Pin Register
- 'TRXPR_Res': '$f0', # Reserved
- 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
- 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
- 'DRTRAM0' : '$135', # Data Retention Configuration R
- 'DRTRAM0_Res': '$c0', # Reserved
- 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM1' : '$134', # Data Retention Configuration R
- 'DRTRAM1_Res': '$c0', # Reserved
- 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM2' : '$133', # Data Retention Configuration R
- 'DRTRAM2_Res': '$40', # Reserved Bit
- 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM3' : '$132', # Data Retention Configuration R
- 'DRTRAM3_Res': '$c0', # Reserved
- 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
- 'LLDRL' : '$130', # Low Leakage Voltage Regulator
- 'LLDRL_Res': '$f0', # Reserved
- 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
- 'LLDRH' : '$131', # Low Leakage Voltage Regulator
- 'LLDRH_Res': '$e0', # Reserved
- 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
- 'LLCR' : '$12f', # Low Leakage Voltage Regulator
- 'LLCR_Res': '$c0', # Reserved Bit
- 'LLCR_LLDONE': '$20', # Calibration Done
- 'LLCR_LLCOMP': '$10', # Comparator Output
- 'LLCR_LLCAL': '$8', # Calibration Active
- 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
- 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
- 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
- 'DPDS0' : '$136', # Port Driver Strength Register
- 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
- 'DPDS0_PEDRV': '$30', # Driver Strength Port E
- 'DPDS0_PDDRV': '$c', # Driver Strength Port D
- 'DPDS0_PBDRV': '$3', # Driver Strength Port B
- 'DPDS1' : '$137', # Port Driver Strength Register
- 'DPDS1_Res': '$fc', # Reserved
- 'DPDS1_PGDRV': '$3', # Driver Strength Port G
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up Disable
-
-# Module USART0_SPI
- 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
- 'UCSR0C_UDORD0': '$4', # Data Order
- 'UCSR0C_UCPHA0': '$2', # Clock Phase
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
-
-# Module USART1_SPI
- 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
- 'UCSR1C_UDORD1': '$4', # Data Order
- 'UCSR1C_UCPHA1': '$2', # Clock Phase
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega128a/atmega128a.frt b/amforth-6.5/avr8/devices/atmega128a/atmega128a.frt
deleted file mode 100644
index 83b4185..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/atmega128a.frt
+++ /dev/null
@@ -1,329 +0,0 @@
-\ Partname: ATmega128A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&64 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ TWI
-&112 constant TWBR \ TWI Bit Rate register
-&116 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&113 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&115 constant TWDR \ TWI Data register
-&114 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&44 constant UDR0 \ USART I/O Data Register
-&43 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&42 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&149 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
-&41 constant UBRR0L \ USART Baud Rate Register Low Byte
-\ USART1
-&156 constant UDR1 \ USART I/O Data Register
-&155 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&154 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&157 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
-&153 constant UBRR1L \ USART Baud Rate Register Low Byte
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SRE \ External SRAM Enable
- $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
- $20 constant MCUCR_SE \ Sleep Enable
- $18 constant MCUCR_SM \ Sleep Mode Select
- $04 constant MCUCR_SM2 \ Sleep Mode Select
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUCSR \ MCU Control And Status Register
- $80 constant MCUCSR_JTD \ JTAG Interface Disable
- $10 constant MCUCSR_JTRF \ JTAG Reset Flag
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&109 constant XMCRA \ External Memory Control Register A
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW0 \ Wait state select bit lower page
- $02 constant XMCRA_SRW11 \ Wait state select bit upper page
-&108 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&111 constant OSCCAL \ Oscillator Calibration Value
-&92 constant XDIV \ XTAL Divide Control Register
-&91 constant RAMPZ \ RAM Page Z Select Register
- $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
-\ BOOT_LOAD
-&104 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ MISC
-\ EXTERNAL_INTERRUPT
-&106 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&90 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&89 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&88 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ PORTE
-&35 constant PORTE \ Data Register, Port E
-&34 constant DDRE \ Data Direction Register, Port E
-&33 constant PINE \ Input Pins, Port E
-\ PORTF
-&98 constant PORTF \ Data Register, Port F
-&97 constant DDRF \ Data Direction Register, Port F
-&32 constant PINF \ Input Pins, Port F
-\ PORTG
-&101 constant PORTG \ Data Register, Port G
-&100 constant DDRG \ Data Direction Register, Port G
-&99 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&81 constant OCR0 \ Output Compare Register
-&80 constant ASSR \ Asynchronus Status Register
- $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
- $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
- $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
- $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
-&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&86 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_1
-&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
- $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
-&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
- $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&122 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
- $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
- $30 constant TCCR2_COM2 \ Compare Match Output Mode
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select
-&68 constant TCNT2 \ Timer/Counter Register
-&67 constant OCR2 \ Output Compare Register
-\ TIMER_COUNTER_3
-&139 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
-&138 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&140 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
- $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
-&136 constant TCNT3 \ Timer/Counter3 Bytes
-&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
-&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADFR \ ADC Free Running Select
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART0__RXAddr \ USART0, Rx Complete
-&38 constant USART0__UDREAddr \ USART0 Data Register Empty
-&40 constant USART0__TXAddr \ USART0, Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&60 constant USART1__RXAddr \ USART1, Rx Complete
-&62 constant USART1__UDREAddr \ USART1, Data Register Empty
-&64 constant USART1__TXAddr \ USART1, Tx Complete
-&66 constant TWIAddr \ 2-wire Serial Interface
-&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega128a/device.asm b/amforth-6.5/avr8/devices/atmega128a/device.asm
deleted file mode 100644
index a0f8692..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/device.asm
+++ /dev/null
@@ -1,141 +0,0 @@
-; Partname: ATmega128A
-; generated automatically, do not edit
-
-.nolist
- .include "m128Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_MISC = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_AD_CONVERTER = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match
-.org 32
- rcall isr ; Timer/Counter0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART0, Rx Complete
-.org 38
- rcall isr ; USART0 Data Register Empty
-.org 40
- rcall isr ; USART0, Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Timer/Counter1 Compare Match C
-.org 50
- rcall isr ; Timer/Counter3 Capture Event
-.org 52
- rcall isr ; Timer/Counter3 Compare Match A
-.org 54
- rcall isr ; Timer/Counter3 Compare Match B
-.org 56
- rcall isr ; Timer/Counter3 Compare Match C
-.org 58
- rcall isr ; Timer/Counter3 Overflow
-.org 60
- rcall isr ; USART1, Rx Complete
-.org 62
- rcall isr ; USART1, Data Register Empty
-.org 64
- rcall isr ; USART1, Tx Complete
-.org 66
- rcall isr ; 2-wire Serial Interface
-.org 68
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 35
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 35
-mcu_name:
- .dw 10
- .db "ATmega128A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128a/device.inc b/amforth-6.5/avr8/devices/atmega128a/device.inc
deleted file mode 100644
index 3252433..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/device.inc
+++ /dev/null
@@ -1,1179 +0,0 @@
-; Partname: ATmega128A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 114
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw 41
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 155
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 157
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR1H:
- .dw $ff06
- .db "UBRR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1H
-XT_UBRR1H:
- .dw PFA_DOVARIABLE
-PFA_UBRR1H:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR1L:
- .dw $ff06
- .db "UBRR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1L
-XT_UBRR1L:
- .dw PFA_DOVARIABLE
-PFA_UBRR1L:
- .dw 153
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; XTAL Divide Control Register
-VE_XDIV:
- .dw $ff04
- .db "XDIV"
- .dw VE_HEAD
- .set VE_HEAD=VE_XDIV
-XT_XDIV:
- .dw PFA_DOVARIABLE
-PFA_XDIV:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 104
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 66
-
-.endif
-.if WANT_MISC == 1
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 88
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 33
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 98
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 32
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 99
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronus Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 86
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Mask Register
-VE_ETIMSK:
- .dw $ff06
- .db "ETIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIMSK
-XT_ETIMSK:
- .dw PFA_DOVARIABLE
-PFA_ETIMSK:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Flag register
-VE_ETIFR:
- .dw $ff05
- .db "ETIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIFR
-XT_ETIFR:
- .dw PFA_DOVARIABLE
-PFA_ETIFR:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 139
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output compare Register C Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 128
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega128a/device.py b/amforth-6.5/avr8/devices/atmega128a/device.py
deleted file mode 100644
index ee2580a..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/device.py
+++ /dev/null
@@ -1,403 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega128A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#36', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#40', # USART0, Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
- 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#60', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#64', # USART1, Tx Complete
- 'TWIAddr' : '#66', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#68', # Store Program Memory Read
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module TWI
- 'TWBR' : '$70', # TWI Bit Rate register
- 'TWCR' : '$74', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$71', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$73', # TWI Data register
- 'TWAR' : '$72', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$2c', # USART I/O Data Register
- 'UCSR0A' : '$2b', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$2a', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$95', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0H' : '$90', # USART Baud Rate Register Hight
- 'UBRR0L' : '$29', # USART Baud Rate Register Low B
-
-# Module USART1
- 'UDR1' : '$9c', # USART I/O Data Register
- 'UCSR1A' : '$9b', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$9a', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$9d', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1H' : '$98', # USART Baud Rate Register Hight
- 'UBRR1L' : '$99', # USART Baud Rate Register Low B
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SRE': '$80', # External SRAM Enable
- 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
- 'MCUCR_SE': '$20', # Sleep Enable
- 'MCUCR_SM': '$18', # Sleep Mode Select
- 'MCUCR_SM2': '$4', # Sleep Mode Select
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$6d', # External Memory Control Regist
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
- 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
- 'XMCRB' : '$6c', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$6f', # Oscillator Calibration Value
- 'XDIV' : '$5c', # XTAL Divide Control Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$68', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$42', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module MISC
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'SFIOR_PUD': '$4', # Pull Up Disable
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
- 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$6a', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$5a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$59', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$58', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$23', # Data Register, Port E
- 'DDRE' : '$22', # Data Direction Register, Port
- 'PINE' : '$21', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$62', # Data Register, Port F
- 'DDRF' : '$61', # Data Direction Register, Port
- 'PINF' : '$20', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$65', # Data Register, Port G
- 'DDRG' : '$64', # Data Direction Register, Port
- 'PING' : '$63', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$51', # Output Compare Register
- 'ASSR' : '$50', # Asynchronus Status Register
- 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
- 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
- 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
- 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'OCR1C' : '$78', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$45', # Timer/Counter Control Register
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
- 'TCCR2_COM2': '$30', # Compare Match Output Mode
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select
- 'TCNT2' : '$44', # Timer/Counter Register
- 'OCR2' : '$43', # Output Compare Register
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TIMSK' : '$57', #
- 'TIMSK_OCIE2': '$80', #
- 'TIMSK_TOIE2': '$40', #
-
-# Module TIMER_COUNTER_3
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
- 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
- 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
- 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
- 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_ICF3': '$20', # Input Capture Flag 1
- 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
- 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
- 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
- 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
- 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
- 'TCNT3' : '$88', # Timer/Counter3 Bytes
- 'OCR3A' : '$86', # Timer/Counter3 Output Compare
- 'OCR3B' : '$84', # Timer/Counter3 Output Compare
- 'OCR3C' : '$82', # Timer/Counter3 Output compare
- 'ICR3' : '$80', # Timer/Counter3 Input Capture R
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADFR': '$20', # ADC Free Running Select
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$24', # ADC Data Register Bytes
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128a/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega128a/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt b/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt
deleted file mode 100644
index 317ebd2..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt
+++ /dev/null
@@ -1,902 +0,0 @@
-\ Partname: ATmega128RFA1
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART0 I/O Data Register
-&192 constant UCSR0A \ USART0 Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART0 Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART0 Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART0 Baud Rate Register Bytes
-\ USART1
-&206 constant UDR1 \ USART1 I/O Data Register
-&200 constant UCSR1A \ USART1 Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- $08 constant UCSR1A_DOR1 \ Data OverRun
- $04 constant UCSR1A_UPE1 \ USART Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART Transmission Speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART1 Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART1 Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART1 Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \ TWI Address Mask
- $01 constant TWAMR_Res \ Reserved Bit
-&184 constant TWBR \ TWI Bit Rate Register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collision Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $02 constant TWCR_Res \ Reserved Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $04 constant TWSR_Res \ Reserved Bit
- $03 constant TWSR_TWPS \ TWI Prescaler Bits
-&187 constant TWDR \ TWI Data Register
-&186 constant TWAR \ TWI (Slave) Address Register
- $FE constant TWAR_TWA \ TWI (Slave) Address
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $3E constant SPSR_Res \ Reserved
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins Address
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins Address
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins Address
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins Address
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins Address
-\ PORTF
-&49 constant PORTF \ Port F Data Register
-&48 constant DDRF \ Port F Data Direction Register
-&47 constant PINF \ Port F Input Pins Address
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins Address
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register B
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0 Register
-&69 constant TCCR0B \ Timer/Counter0 Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter0 Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- $0C constant TCCR0A_Res \ Reserved Bit
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $F8 constant TIMSK0_Res \ Reserved
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag Register
- $F8 constant TIFR0_Res \ Reserved
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare B Match Flag
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare A Match Flag
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $7C constant GTCCR_Res \ Reserved
- $02 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronous Timer/Counters
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $F8 constant TIMSK2_Res \ Reserved Bit
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $F8 constant TIFR2_Res \ Reserved Bit
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- $0C constant TCCR2A_Res \ Reserved
- $03 constant TCCR2A_WGM2 \ Waveform Generation Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input for AMR
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mode
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare Register A Update Busy
- $04 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare Register B Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter2 Control Register A Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter2 Control Register B Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode for Channel A
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channel B
- $0C constant TCCR5A_COM5C \ Compare Output Mode for Channel C
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceller
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Clock Select
-&290 constant TCCR5C \ Timer/Counter5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Channel A
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Channel B
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Channel C
- $1F constant TCCR5C_Res \ Reserved
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register C Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $C0 constant TIMSK5_Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $10 constant TIMSK5_Res \ Reserved Bit
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag Register
- $C0 constant TIFR5_Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture Flag
- $10 constant TIFR5_Res \ Reserved Bit
- $08 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare C Match Flag
- $04 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare B Match Flag
- $02 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare A Match Flag
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode for Channel A
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channel B
- $0C constant TCCR4A_COM4C \ Compare Output Mode for Channel C
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceller
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Clock Select
-&162 constant TCCR4C \ Timer/Counter4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Channel A
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Channel B
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Channel C
- $1F constant TCCR4C_Res \ Reserved
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register C Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $C0 constant TIMSK4_Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $10 constant TIMSK4_Res \ Reserved Bit
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag Register
- $C0 constant TIFR4_Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture Flag
- $10 constant TIFR4_Res \ Reserved Bit
- $08 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare C Match Flag
- $04 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare B Match Flag
- $02 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare A Match Flag
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode for Channel A
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channel B
- $0C constant TCCR3A_COM3C \ Compare Output Mode for Channel C
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceller
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Clock Select
-&146 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Channel C
- $1F constant TCCR3C_Res \ Reserved
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register C Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $C0 constant TIMSK3_Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $10 constant TIMSK3_Res \ Reserved Bit
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag Register
- $C0 constant TIFR3_Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
- $10 constant TIFR3_Res \ Reserved Bit
- $08 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare C Match Flag
- $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
- $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode for Channel A
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channel B
- $0C constant TCCR1A_COM1C \ Compare Output Mode for Channel C
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceller
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Clock Select
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Channel C
- $1F constant TCCR1C_Res \ Reserved
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $C0 constant TIMSK1_Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $10 constant TIMSK1_Res \ Reserved Bit
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag Register
- $C0 constant TIFR1_Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $10 constant TIFR1_Res \ Reserved Bit
- $08 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare C Match Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TRX24
-&316 constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- $08 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- $04 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- $03 constant AES_CTRL_Res \ Reserved Bit
-&317 constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Error
- $7E constant AES_STATUS_Res \ Reserved
- $01 constant AES_STATUS_AES_DONE \ AES Operation Finished with Success
-&318 constant AES_STATE \ AES Plain and Cipher Text Buffer Register
- $FF constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buffer
-&319 constant AES_KEY \ AES Encryption and Decryption Key Buffer Register
- $FF constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key Buffer
-&321 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- $1F constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
-&322 constant TRX_STATE \ Transceiver State Control Register
- $E0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- $1F constant TRX_STATE_TRX_CMD \ State Control Command
-&323 constant TRX_CTRL_0 \ Reserved
- $FF constant TRX_CTRL_0_Res \ Reserved
-&324 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculation
- $1F constant TRX_CTRL_1_Res \ Reserved
-&325 constant PHY_TX_PWR \ Transceiver Transmit Power Control Register
- $C0 constant PHY_TX_PWR_PA_BUF_LT \ Power Amplifier Buffer Lead Time
- $30 constant PHY_TX_PWR_PA_LT \ Power Amplifier Lead Time
- $0F constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
-&326 constant PHY_RSSI \ Receiver Signal Strength Indicator Register
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- $1F constant PHY_RSSI_RSSI \ Receiver Signal Strength Indicator
-&327 constant PHY_ED_LEVEL \ Transceiver Energy Detection Level Register
- $FF constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
-&328 constant PHY_CC_CCA \ Transceiver Clear Channel Assessment (CCA) Control Register
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- $1F constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
-&329 constant CCA_THRES \ Transceiver CCA Threshold Setting Register
- $F0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Measurement
- $0F constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Measurement
-&330 constant RX_CTRL \ Transceiver Receive Control Register
- $0F constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
-&331 constant SFD_VALUE \ Start of Frame Delimiter Value Register
- $FF constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
-&332 constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- $7C constant TRX_CTRL_2_Res \ Reserved
- $03 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
-&333 constant ANT_DIV \ Antenna Diversity Control Register
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Status
- $70 constant ANT_DIV_Res \ Reserved
- $08 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- $04 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch Control
- $03 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switch Control
-&334 constant IRQ_MASK \ Transceiver Interrupt Enable Register
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrupt Enable
- $08 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- $04 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- $02 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $01 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
-&335 constant IRQ_STATUS \ Transceiver Interrupt Status Register
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrupt Status
- $08 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- $04 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- $02 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- $01 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
-&336 constant VREG_CTRL \ Voltage Regulator Control and Status Register
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- $08 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- $04 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
-&337 constant BATMON \ Battery Monitor Control and Status Register
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Status
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enable
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- $0F constant BATMON_BATMON_VTH \ Battery Monitor Threshold Voltage
-&338 constant XOSC_CTRL \ Crystal Oscillator Control Register
- $F0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating Mode
- $0F constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capacitance Trimming
-&341 constant RX_SYN \ Transceiver Receiver Sensitivity Control Register
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- $70 constant RX_SYN_Res \ Reserved
- $0F constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-&343 constant XAH_CTRL_1 \ Transceiver Acknowledgment Frame Control Register 1
- $C0 constant XAH_CTRL_1_Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- $08 constant XAH_CTRL_1_Res \ Reserved Bit
- $04 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- $02 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- $01 constant XAH_CTRL_1_Res \ Reserved Bit
-&344 constant FTN_CTRL \ Transceiver Filter Tuning Control Register
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filter Tuning Network
-&346 constant PLL_CF \ Transceiver Center Frequency Calibration Control Register
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibration
-&347 constant PLL_DCU \ Transceiver Delay Cell Calibration Control Register
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
-&348 constant PART_NUM \ Device Identification Register (Part Number)
- $FF constant PART_NUM_PART_NUM \ Part Number
-&349 constant VERSION_NUM \ Device Identification Register (Version Number)
- $FF constant VERSION_NUM_VERSION_NUM \ Version Number
-&350 constant MAN_ID_0 \ Device Identification Register (Manufacture ID Low Byte)
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- $08 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- $04 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- $02 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- $01 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
-&351 constant MAN_ID_1 \ Device Identification Register (Manufacture ID High Byte)
- $FF constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
-&352 constant SHORT_ADDR_0 \ Transceiver MAC Short Address Register (Low Byte)
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- $08 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- $04 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- $02 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- $01 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
-&353 constant SHORT_ADDR_1 \ Transceiver MAC Short Address Register (High Byte)
- $FF constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
-&354 constant PAN_ID_0 \ Transceiver Personal Area Network ID Register (Low Byte)
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- $08 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- $04 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- $02 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- $01 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
-&355 constant PAN_ID_1 \ Transceiver Personal Area Network ID Register (High Byte)
- $FF constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
-&356 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address Register 0
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- $08 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- $04 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- $02 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- $01 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
-&357 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address Register 1
- $FF constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
-&358 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address Register 2
- $FF constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
-&359 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address Register 3
- $FF constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
-&360 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address Register 4
- $FF constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
-&361 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address Register 5
- $FF constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
-&362 constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address Register 6
- $FF constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
-&363 constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address Register 7
- $FF constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
-&364 constant XAH_CTRL_0 \ Transceiver Extended Operating Mode Control Register
- $F0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-transmission Attempts
- $0E constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Procedure Repetition Attempts
- $01 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
-&365 constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Number Generator Seed Register
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Number Generator
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Number Generator
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Number Generator
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Number Generator
- $08 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Number Generator
- $04 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Number Generator
- $02 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Number Generator
- $01 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Number Generator
-&366 constant CSMA_SEED_1 \ Transceiver Acknowledgment Frame Control Register 2
- $C0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mode
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame Transmission
- $08 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coordinator
- $07 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Number Generator
-&367 constant CSMA_BE \ Transceiver CSMA-CA Back-off Exponent Control Register
- $F0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- $0F constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
-&374 constant TST_CTRL_DIGI \ Transceiver Digital Test Control Register
- $0F constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Register
-&379 constant TST_RX_LENGTH \ Transceiver Received Frame Length Register
- $FF constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
-&384 constant TRXFBST \ Start of frame buffer
-&511 constant TRXFBEND \ End of frame buffer
-\ SYMCNT
-&248 constant SCOCR1HH \ Symbol Counter Output Compare Register 1 HH-Byte
- $FF constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare Register 1 HH-Byte
-&247 constant SCOCR1HL \ Symbol Counter Output Compare Register 1 HL-Byte
- $FF constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare Register 1 HL-Byte
-&246 constant SCOCR1LH \ Symbol Counter Output Compare Register 1 LH-Byte
- $FF constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare Register 1 LH-Byte
-&245 constant SCOCR1LL \ Symbol Counter Output Compare Register 1 LL-Byte
- $FF constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare Register 1 LL-Byte
-&244 constant SCOCR2HH \ Symbol Counter Output Compare Register 2 HH-Byte
- $FF constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare Register 2 HH-Byte
-&243 constant SCOCR2HL \ Symbol Counter Output Compare Register 2 HL-Byte
- $FF constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare Register 2 HL-Byte
-&242 constant SCOCR2LH \ Symbol Counter Output Compare Register 2 LH-Byte
- $FF constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare Register 2 LH-Byte
-&241 constant SCOCR2LL \ Symbol Counter Output Compare Register 2 LL-Byte
- $FF constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare Register 2 LL-Byte
-&240 constant SCOCR3HH \ Symbol Counter Output Compare Register 3 HH-Byte
- $FF constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare Register 3 HH-Byte
-&239 constant SCOCR3HL \ Symbol Counter Output Compare Register 3 HL-Byte
- $FF constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare Register 3 HL-Byte
-&238 constant SCOCR3LH \ Symbol Counter Output Compare Register 3 LH-Byte
- $FF constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare Register 3 LH-Byte
-&237 constant SCOCR3LL \ Symbol Counter Output Compare Register 3 LL-Byte
- $FF constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare Register 3 LL-Byte
-&236 constant SCTSRHH \ Symbol Counter Frame Timestamp Register HH-Byte
- $FF constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp Register HH-Byte
-&235 constant SCTSRHL \ Symbol Counter Frame Timestamp Register HL-Byte
- $FF constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp Register HL-Byte
-&234 constant SCTSRLH \ Symbol Counter Frame Timestamp Register LH-Byte
- $FF constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp Register LH-Byte
-&233 constant SCTSRLL \ Symbol Counter Frame Timestamp Register LL-Byte
- $FF constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp Register LL-Byte
-&232 constant SCBTSRHH \ Symbol Counter Beacon Timestamp Register HH-Byte
- $FF constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestamp Register HH-Byte
-&231 constant SCBTSRHL \ Symbol Counter Beacon Timestamp Register HL-Byte
- $FF constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestamp Register HL-Byte
-&230 constant SCBTSRLH \ Symbol Counter Beacon Timestamp Register LH-Byte
- $FF constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestamp Register LH-Byte
-&229 constant SCBTSRLL \ Symbol Counter Beacon Timestamp Register LL-Byte
- $FF constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestamp Register LL-Byte
-&228 constant SCCNTHH \ Symbol Counter Register HH-Byte
- $FF constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byte
-&227 constant SCCNTHL \ Symbol Counter Register HL-Byte
- $FF constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byte
-&226 constant SCCNTLH \ Symbol Counter Register LH-Byte
- $FF constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byte
-&225 constant SCCNTLL \ Symbol Counter Register LL-Byte
- $FF constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byte
-&224 constant SCIRQS \ Symbol Counter Interrupt Status Register
- $E0 constant SCIRQS_Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- $08 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- $07 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match IRQ
-&223 constant SCIRQM \ Symbol Counter Interrupt Mask Register
- $E0 constant SCIRQM_Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enable
- $08 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ enable
- $07 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3 IRQ enable
-&222 constant SCSR \ Symbol Counter Status Register
- $FE constant SCSR_Res \ Reserved Bit
- $01 constant SCSR_SCBSY \ Symbol Counter busy
-&221 constant SCCR1 \ Symbol Counter Control Register 1
- $FE constant SCCR1_Res \ Reserved Bit
- $01 constant SCCR1_SCENBO \ Backoff Slot Counter enable
-&220 constant SCCR0 \ Symbol Counter Control Register 0
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source select
- $08 constant SCCR0_SCTSE \ Symbol Counter Automatic Timestamping enable
- $07 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3 Mode select
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $C0 constant EECR_Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Programming Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Register
- $FF constant OCDR_OCDR \ On-Chip Debug Register Data
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt 3 Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt 1 Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt 0 Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 5 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flag
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Mask
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Mask
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $F8 constant PCIFR_Res \ Reserved Bit
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $F8 constant PCICR_Res \ Reserved Bit
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC Multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status Register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&119 constant ADCSRC \ The ADC Control and Status Register C
- $C0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- $1F constant ADCSRC_ADSUT \ ADC Start-up Time
-&125 constant DIDR2 \ Digital Input Disable Register 2
- $80 constant DIDR2_ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- $08 constant DIDR2_ADC11D \ Reserved Bits
- $04 constant DIDR2_ADC10D \ Reserved Bits
- $02 constant DIDR2_ADC9D \ Reserved Bits
- $01 constant DIDR2_ADC8D \ Reserved Bits
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- $08 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- $04 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- $02 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- $01 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read Enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
- $FF constant OSCCAL_CAL \ Oscillator Calibration Tuning Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&83 constant SMCR \ Sleep Mode Control Register
- $F0 constant SMCR_Res \ Reserved
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ Extended Z-pointer Register for ELPM/SPM
- $FC constant RAMPZ_Res \ Reserved
- $03 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
-&75 constant GPIOR2 \ General Purpose I/O Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose I/O Register 2 Value
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose I/O Register 1 Value
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0 Value
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0 Value
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0 Value
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0 Value
- $08 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0 Value
- $04 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0 Value
- $02 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0 Value
- $01 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0 Value
-&99 constant PRR2 \ Power Reduction Register 2
- $F0 constant PRR2_Res \ Reserved Bit
- $0F constant PRR2_PRRAM \ Power Reduction SRAMs
-&101 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Reserved
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ FLASH
-&117 constant NEMCR \ Flash Extended-Mode Control-Register
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode for Extra Rows
- $30 constant NEMCR_AEAM \ Address for Extended Address Mode of Extra Rows
-&103 constant BGCR \ Reference Voltage Calibration Register
- $80 constant BGCR_Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- $07 constant BGCR_BGCAL \ Coarse Calibration Bits
-\ PWRCTRL
-&313 constant TRXPR \ Transceiver Pin Register
- $F0 constant TRXPR_Res \ Reserved
- $02 constant TRXPR_SLPTR \ Multi-purpose Transceiver Control Bit
- $01 constant TRXPR_TRXRST \ Force Transceiver Reset
-&309 constant DRTRAM0 \ Data Retention Configuration Register of SRAM 0
- $C0 constant DRTRAM0_Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
-&308 constant DRTRAM1 \ Data Retention Configuration Register of SRAM 1
- $C0 constant DRTRAM1_Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
-&307 constant DRTRAM2 \ Data Retention Configuration Register of SRAM 2
- $40 constant DRTRAM2_Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
-&306 constant DRTRAM3 \ Data Retention Configuration Register of SRAM 3
- $C0 constant DRTRAM3_Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
-&304 constant LLDRL \ Low Leakage Voltage Regulator Data Register (Low-Byte)
- $F0 constant LLDRL_Res \ Reserved
- $0F constant LLDRL_LLDRL \ Low-Byte Data Register Bits
-&305 constant LLDRH \ Low Leakage Voltage Regulator Data Register (High-Byte)
- $E0 constant LLDRH_Res \ Reserved
- $1F constant LLDRH_LLDRH \ High-Byte Data Register Bits
-&303 constant LLCR \ Low Leakage Voltage Regulator Control Register
- $C0 constant LLCR_Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- $08 constant LLCR_LLCAL \ Calibration Active
- $04 constant LLCR_LLTCO \ Temperature Coefficient of Current Source
- $02 constant LLCR_LLSHORT \ Short Lower Calibration Circuit
- $01 constant LLCR_LLENCAL \ Enable Automatic Calibration
-&310 constant DPDS0 \ Port Driver Strength Register 0
- $C0 constant DPDS0_PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- $0C constant DPDS0_PDDRV \ Driver Strength Port D
- $03 constant DPDS0_PBDRV \ Driver Strength Port B
-&311 constant DPDS1 \ Port Driver Strength Register 1
- $FC constant DPDS1_Res \ Reserved
- $03 constant DPDS1_PGDRV \ Driver Strength Port G
-\ USART0_SPI
-\ USART1_SPI
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI_STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0_RXAddr \ USART0, Rx Complete
-&52 constant USART0_UDREAddr \ USART0 Data register Empty
-&54 constant USART0_TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1_RXAddr \ USART1, Rx Complete
-&74 constant USART1_UDREAddr \ USART1 Data register Empty
-&76 constant USART1_TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2_RXAddr \ USART2, Rx Complete
-&104 constant USART2_UDREAddr \ USART2 Data register Empty
-&106 constant USART2_TXAddr \ USART2, Tx Complete
-&108 constant USART3_RXAddr \ USART3, Rx Complete
-&110 constant USART3_UDREAddr \ USART3 Data register Empty
-&112 constant USART3_TXAddr \ USART3, Tx Complete
-&114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
-&116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
-&118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
-&120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
-&122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
-&124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
-&126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
-&128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state
-&130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
-&132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
-&134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
-&136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
-&138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
-&140 constant AES_READYAddr \ AES engine ready interrupt
-&142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.asm b/amforth-6.5/avr8/devices/atmega128rfa1/device.asm
deleted file mode 100644
index e81539e..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/device.asm
+++ /dev/null
@@ -1,220 +0,0 @@
-; Partname: ATmega128RFA1
-; generated automatically, do not edit
-
-.nolist
- .include "m128RFA1def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TRX24 = 0
-.set WANT_SYMCNT = 0
-.set WANT_EEPROM = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_FLASH = 0
-.set WANT_PWRCTRL = 0
-.set WANT_USART0_SPI = 0
-.set WANT_USART1_SPI = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.org 114
- rcall isr ; TRX24 - PLL lock interrupt
-.org 116
- rcall isr ; TRX24 - PLL unlock interrupt
-.org 118
- rcall isr ; TRX24 - Receive start interrupt
-.org 120
- rcall isr ; TRX24 - RX_END interrupt
-.org 122
- rcall isr ; TRX24 - CCA/ED done interrupt
-.org 124
- rcall isr ; TRX24 - XAH - AMI
-.org 126
- rcall isr ; TRX24 - TX_END interrupt
-.org 128
- rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-.org 130
- rcall isr ; Symbol counter - compare match 1 interrupt
-.org 132
- rcall isr ; Symbol counter - compare match 2 interrupt
-.org 134
- rcall isr ; Symbol counter - compare match 3 interrupt
-.org 136
- rcall isr ; Symbol counter - overflow interrupt
-.org 138
- rcall isr ; Symbol counter - backoff interrupt
-.org 140
- rcall isr ; AES engine ready interrupt
-.org 142
- rcall isr ; Battery monitor indicates supply voltage below threshold
-.equ INTVECTORS = 72
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 16384
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 72
-mcu_name:
- .dw 13
- .db "ATmega128RFA1",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.inc b/amforth-6.5/avr8/devices/atmega128rfa1/device.inc
deleted file mode 100644
index 503bb63..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/device.inc
+++ /dev/null
@@ -1,2808 +0,0 @@
-; Partname: ATmega128RFA1
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate Register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data Register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins Address
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins Address
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins Address
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins Address
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins Address
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port F Data Register
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port F Data Direction Register
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Port F Input Pins Address
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins Address
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag Register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register C Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag Register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register C Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag Register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register C Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag Register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag Register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TRX24 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; AES Control Register
-VE_AES_CTRL:
- .dw $ff08
- .db "AES_CTRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_CTRL
-XT_AES_CTRL:
- .dw PFA_DOVARIABLE
-PFA_AES_CTRL:
- .dw 316
-; ( -- addr ) System Constant
-; R( -- )
-; AES Status Register
-VE_AES_STATUS:
- .dw $ff10
- .db "AES_STATUS"
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_STATUS
-XT_AES_STATUS:
- .dw PFA_DOVARIABLE
-PFA_AES_STATUS:
- .dw 317
-; ( -- addr ) System Constant
-; R( -- )
-; AES Plain and Cipher Text Buffer Register
-VE_AES_STATE:
- .dw $ff09
- .db "AES_STATE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_STATE
-XT_AES_STATE:
- .dw PFA_DOVARIABLE
-PFA_AES_STATE:
- .dw 318
-; ( -- addr ) System Constant
-; R( -- )
-; AES Encryption and Decryption Key Buffer Register
-VE_AES_KEY:
- .dw $ff07
- .db "AES_KEY",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_KEY
-XT_AES_KEY:
- .dw PFA_DOVARIABLE
-PFA_AES_KEY:
- .dw 319
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Status Register
-VE_TRX_STATUS:
- .dw $ff10
- .db "TRX_STATUS"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_STATUS
-XT_TRX_STATUS:
- .dw PFA_DOVARIABLE
-PFA_TRX_STATUS:
- .dw 321
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver State Control Register
-VE_TRX_STATE:
- .dw $ff09
- .db "TRX_STATE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_STATE
-XT_TRX_STATE:
- .dw PFA_DOVARIABLE
-PFA_TRX_STATE:
- .dw 322
-; ( -- addr ) System Constant
-; R( -- )
-; Reserved
-VE_TRX_CTRL_0:
- .dw $ff10
- .db "TRX_CTRL_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_CTRL_0
-XT_TRX_CTRL_0:
- .dw PFA_DOVARIABLE
-PFA_TRX_CTRL_0:
- .dw 323
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Control Register 1
-VE_TRX_CTRL_1:
- .dw $ff10
- .db "TRX_CTRL_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_CTRL_1
-XT_TRX_CTRL_1:
- .dw PFA_DOVARIABLE
-PFA_TRX_CTRL_1:
- .dw 324
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Transmit Power Control Register
-VE_PHY_TX_PWR:
- .dw $ff10
- .db "PHY_TX_PWR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_TX_PWR
-XT_PHY_TX_PWR:
- .dw PFA_DOVARIABLE
-PFA_PHY_TX_PWR:
- .dw 325
-; ( -- addr ) System Constant
-; R( -- )
-; Receiver Signal Strength Indicator Register
-VE_PHY_RSSI:
- .dw $ff08
- .db "PHY_RSSI"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_RSSI
-XT_PHY_RSSI:
- .dw PFA_DOVARIABLE
-PFA_PHY_RSSI:
- .dw 326
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Energy Detection Level Register
-VE_PHY_ED_LEVEL:
- .dw $ff12
- .db "PHY_ED_LEVEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_ED_LEVEL
-XT_PHY_ED_LEVEL:
- .dw PFA_DOVARIABLE
-PFA_PHY_ED_LEVEL:
- .dw 327
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Clear Channel Assessment (CCA) Control Register
-VE_PHY_CC_CCA:
- .dw $ff10
- .db "PHY_CC_CCA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_CC_CCA
-XT_PHY_CC_CCA:
- .dw PFA_DOVARIABLE
-PFA_PHY_CC_CCA:
- .dw 328
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver CCA Threshold Setting Register
-VE_CCA_THRES:
- .dw $ff09
- .db "CCA_THRES",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CCA_THRES
-XT_CCA_THRES:
- .dw PFA_DOVARIABLE
-PFA_CCA_THRES:
- .dw 329
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Receive Control Register
-VE_RX_CTRL:
- .dw $ff07
- .db "RX_CTRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RX_CTRL
-XT_RX_CTRL:
- .dw PFA_DOVARIABLE
-PFA_RX_CTRL:
- .dw 330
-; ( -- addr ) System Constant
-; R( -- )
-; Start of Frame Delimiter Value Register
-VE_SFD_VALUE:
- .dw $ff09
- .db "SFD_VALUE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFD_VALUE
-XT_SFD_VALUE:
- .dw PFA_DOVARIABLE
-PFA_SFD_VALUE:
- .dw 331
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Control Register 2
-VE_TRX_CTRL_2:
- .dw $ff10
- .db "TRX_CTRL_2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_CTRL_2
-XT_TRX_CTRL_2:
- .dw PFA_DOVARIABLE
-PFA_TRX_CTRL_2:
- .dw 332
-; ( -- addr ) System Constant
-; R( -- )
-; Antenna Diversity Control Register
-VE_ANT_DIV:
- .dw $ff07
- .db "ANT_DIV",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ANT_DIV
-XT_ANT_DIV:
- .dw PFA_DOVARIABLE
-PFA_ANT_DIV:
- .dw 333
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Interrupt Enable Register
-VE_IRQ_MASK:
- .dw $ff08
- .db "IRQ_MASK"
- .dw VE_HEAD
- .set VE_HEAD=VE_IRQ_MASK
-XT_IRQ_MASK:
- .dw PFA_DOVARIABLE
-PFA_IRQ_MASK:
- .dw 334
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Interrupt Status Register
-VE_IRQ_STATUS:
- .dw $ff10
- .db "IRQ_STATUS"
- .dw VE_HEAD
- .set VE_HEAD=VE_IRQ_STATUS
-XT_IRQ_STATUS:
- .dw PFA_DOVARIABLE
-PFA_IRQ_STATUS:
- .dw 335
-; ( -- addr ) System Constant
-; R( -- )
-; Voltage Regulator Control and Status Register
-VE_VREG_CTRL:
- .dw $ff09
- .db "VREG_CTRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VREG_CTRL
-XT_VREG_CTRL:
- .dw PFA_DOVARIABLE
-PFA_VREG_CTRL:
- .dw 336
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Monitor Control and Status Register
-VE_BATMON:
- .dw $ff06
- .db "BATMON"
- .dw VE_HEAD
- .set VE_HEAD=VE_BATMON
-XT_BATMON:
- .dw PFA_DOVARIABLE
-PFA_BATMON:
- .dw 337
-; ( -- addr ) System Constant
-; R( -- )
-; Crystal Oscillator Control Register
-VE_XOSC_CTRL:
- .dw $ff09
- .db "XOSC_CTRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XOSC_CTRL
-XT_XOSC_CTRL:
- .dw PFA_DOVARIABLE
-PFA_XOSC_CTRL:
- .dw 338
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Receiver Sensitivity Control Register
-VE_RX_SYN:
- .dw $ff06
- .db "RX_SYN"
- .dw VE_HEAD
- .set VE_HEAD=VE_RX_SYN
-XT_RX_SYN:
- .dw PFA_DOVARIABLE
-PFA_RX_SYN:
- .dw 341
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Acknowledgment Frame Control Register 1
-VE_XAH_CTRL_1:
- .dw $ff10
- .db "XAH_CTRL_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_XAH_CTRL_1
-XT_XAH_CTRL_1:
- .dw PFA_DOVARIABLE
-PFA_XAH_CTRL_1:
- .dw 343
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Filter Tuning Control Register
-VE_FTN_CTRL:
- .dw $ff08
- .db "FTN_CTRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_FTN_CTRL
-XT_FTN_CTRL:
- .dw PFA_DOVARIABLE
-PFA_FTN_CTRL:
- .dw 344
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Center Frequency Calibration Control Register
-VE_PLL_CF:
- .dw $ff06
- .db "PLL_CF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLL_CF
-XT_PLL_CF:
- .dw PFA_DOVARIABLE
-PFA_PLL_CF:
- .dw 346
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Delay Cell Calibration Control Register
-VE_PLL_DCU:
- .dw $ff07
- .db "PLL_DCU",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PLL_DCU
-XT_PLL_DCU:
- .dw PFA_DOVARIABLE
-PFA_PLL_DCU:
- .dw 347
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Part Number)
-VE_PART_NUM:
- .dw $ff08
- .db "PART_NUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_PART_NUM
-XT_PART_NUM:
- .dw PFA_DOVARIABLE
-PFA_PART_NUM:
- .dw 348
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Version Number)
-VE_VERSION_NUM:
- .dw $ff11
- .db "VERSION_NUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VERSION_NUM
-XT_VERSION_NUM:
- .dw PFA_DOVARIABLE
-PFA_VERSION_NUM:
- .dw 349
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Manufacture ID Low Byte)
-VE_MAN_ID_0:
- .dw $ff08
- .db "MAN_ID_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_MAN_ID_0
-XT_MAN_ID_0:
- .dw PFA_DOVARIABLE
-PFA_MAN_ID_0:
- .dw 350
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Manufacture ID High Byte)
-VE_MAN_ID_1:
- .dw $ff08
- .db "MAN_ID_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_MAN_ID_1
-XT_MAN_ID_1:
- .dw PFA_DOVARIABLE
-PFA_MAN_ID_1:
- .dw 351
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC Short Address Register (Low Byte)
-VE_SHORT_ADDR_0:
- .dw $ff12
- .db "SHORT_ADDR_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_SHORT_ADDR_0
-XT_SHORT_ADDR_0:
- .dw PFA_DOVARIABLE
-PFA_SHORT_ADDR_0:
- .dw 352
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC Short Address Register (High Byte)
-VE_SHORT_ADDR_1:
- .dw $ff12
- .db "SHORT_ADDR_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_SHORT_ADDR_1
-XT_SHORT_ADDR_1:
- .dw PFA_DOVARIABLE
-PFA_SHORT_ADDR_1:
- .dw 353
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Personal Area Network ID Register (Low Byte)
-VE_PAN_ID_0:
- .dw $ff08
- .db "PAN_ID_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PAN_ID_0
-XT_PAN_ID_0:
- .dw PFA_DOVARIABLE
-PFA_PAN_ID_0:
- .dw 354
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Personal Area Network ID Register (High Byte)
-VE_PAN_ID_1:
- .dw $ff08
- .db "PAN_ID_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PAN_ID_1
-XT_PAN_ID_1:
- .dw PFA_DOVARIABLE
-PFA_PAN_ID_1:
- .dw 355
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 0
-VE_IEEE_ADDR_0:
- .dw $ff11
- .db "IEEE_ADDR_0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_0
-XT_IEEE_ADDR_0:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_0:
- .dw 356
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 1
-VE_IEEE_ADDR_1:
- .dw $ff11
- .db "IEEE_ADDR_1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_1
-XT_IEEE_ADDR_1:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_1:
- .dw 357
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 2
-VE_IEEE_ADDR_2:
- .dw $ff11
- .db "IEEE_ADDR_2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_2
-XT_IEEE_ADDR_2:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_2:
- .dw 358
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 3
-VE_IEEE_ADDR_3:
- .dw $ff11
- .db "IEEE_ADDR_3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_3
-XT_IEEE_ADDR_3:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_3:
- .dw 359
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 4
-VE_IEEE_ADDR_4:
- .dw $ff11
- .db "IEEE_ADDR_4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_4
-XT_IEEE_ADDR_4:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_4:
- .dw 360
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 5
-VE_IEEE_ADDR_5:
- .dw $ff11
- .db "IEEE_ADDR_5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_5
-XT_IEEE_ADDR_5:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_5:
- .dw 361
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 6
-VE_IEEE_ADDR_6:
- .dw $ff11
- .db "IEEE_ADDR_6",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_6
-XT_IEEE_ADDR_6:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_6:
- .dw 362
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 7
-VE_IEEE_ADDR_7:
- .dw $ff11
- .db "IEEE_ADDR_7",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_7
-XT_IEEE_ADDR_7:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_7:
- .dw 363
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Extended Operating Mode Control Register
-VE_XAH_CTRL_0:
- .dw $ff10
- .db "XAH_CTRL_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_XAH_CTRL_0
-XT_XAH_CTRL_0:
- .dw PFA_DOVARIABLE
-PFA_XAH_CTRL_0:
- .dw 364
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver CSMA-CA Random Number Generator Seed Register
-VE_CSMA_SEED_0:
- .dw $ff11
- .db "CSMA_SEED_0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CSMA_SEED_0
-XT_CSMA_SEED_0:
- .dw PFA_DOVARIABLE
-PFA_CSMA_SEED_0:
- .dw 365
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Acknowledgment Frame Control Register 2
-VE_CSMA_SEED_1:
- .dw $ff11
- .db "CSMA_SEED_1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CSMA_SEED_1
-XT_CSMA_SEED_1:
- .dw PFA_DOVARIABLE
-PFA_CSMA_SEED_1:
- .dw 366
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver CSMA-CA Back-off Exponent Control Register
-VE_CSMA_BE:
- .dw $ff07
- .db "CSMA_BE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CSMA_BE
-XT_CSMA_BE:
- .dw PFA_DOVARIABLE
-PFA_CSMA_BE:
- .dw 367
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Digital Test Control Register
-VE_TST_CTRL_DIGI:
- .dw $ff13
- .db "TST_CTRL_DIGI",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TST_CTRL_DIGI
-XT_TST_CTRL_DIGI:
- .dw PFA_DOVARIABLE
-PFA_TST_CTRL_DIGI:
- .dw 374
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Received Frame Length Register
-VE_TST_RX_LENGTH:
- .dw $ff13
- .db "TST_RX_LENGTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TST_RX_LENGTH
-XT_TST_RX_LENGTH:
- .dw PFA_DOVARIABLE
-PFA_TST_RX_LENGTH:
- .dw 379
-; ( -- addr ) System Constant
-; R( -- )
-; Start of frame buffer
-VE_TRXFBST:
- .dw $ff07
- .db "TRXFBST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TRXFBST
-XT_TRXFBST:
- .dw PFA_DOVARIABLE
-PFA_TRXFBST:
- .dw 384
-; ( -- addr ) System Constant
-; R( -- )
-; End of frame buffer
-VE_TRXFBEND:
- .dw $ff08
- .db "TRXFBEND"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRXFBEND
-XT_TRXFBEND:
- .dw PFA_DOVARIABLE
-PFA_TRXFBEND:
- .dw 511
-
-.endif
-.if WANT_SYMCNT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 HH-Byte
-VE_SCOCR1HH:
- .dw $ff08
- .db "SCOCR1HH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1HH
-XT_SCOCR1HH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1HH:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 HL-Byte
-VE_SCOCR1HL:
- .dw $ff08
- .db "SCOCR1HL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1HL
-XT_SCOCR1HL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1HL:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 LH-Byte
-VE_SCOCR1LH:
- .dw $ff08
- .db "SCOCR1LH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1LH
-XT_SCOCR1LH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1LH:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 LL-Byte
-VE_SCOCR1LL:
- .dw $ff08
- .db "SCOCR1LL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1LL
-XT_SCOCR1LL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1LL:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 HH-Byte
-VE_SCOCR2HH:
- .dw $ff08
- .db "SCOCR2HH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2HH
-XT_SCOCR2HH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2HH:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 HL-Byte
-VE_SCOCR2HL:
- .dw $ff08
- .db "SCOCR2HL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2HL
-XT_SCOCR2HL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2HL:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 LH-Byte
-VE_SCOCR2LH:
- .dw $ff08
- .db "SCOCR2LH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2LH
-XT_SCOCR2LH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2LH:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 LL-Byte
-VE_SCOCR2LL:
- .dw $ff08
- .db "SCOCR2LL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2LL
-XT_SCOCR2LL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2LL:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 HH-Byte
-VE_SCOCR3HH:
- .dw $ff08
- .db "SCOCR3HH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3HH
-XT_SCOCR3HH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3HH:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 HL-Byte
-VE_SCOCR3HL:
- .dw $ff08
- .db "SCOCR3HL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3HL
-XT_SCOCR3HL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3HL:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 LH-Byte
-VE_SCOCR3LH:
- .dw $ff08
- .db "SCOCR3LH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3LH
-XT_SCOCR3LH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3LH:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 LL-Byte
-VE_SCOCR3LL:
- .dw $ff08
- .db "SCOCR3LL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3LL
-XT_SCOCR3LL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3LL:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register HH-Byte
-VE_SCTSRHH:
- .dw $ff07
- .db "SCTSRHH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRHH
-XT_SCTSRHH:
- .dw PFA_DOVARIABLE
-PFA_SCTSRHH:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register HL-Byte
-VE_SCTSRHL:
- .dw $ff07
- .db "SCTSRHL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRHL
-XT_SCTSRHL:
- .dw PFA_DOVARIABLE
-PFA_SCTSRHL:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register LH-Byte
-VE_SCTSRLH:
- .dw $ff07
- .db "SCTSRLH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRLH
-XT_SCTSRLH:
- .dw PFA_DOVARIABLE
-PFA_SCTSRLH:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register LL-Byte
-VE_SCTSRLL:
- .dw $ff07
- .db "SCTSRLL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRLL
-XT_SCTSRLL:
- .dw PFA_DOVARIABLE
-PFA_SCTSRLL:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register HH-Byte
-VE_SCBTSRHH:
- .dw $ff08
- .db "SCBTSRHH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRHH
-XT_SCBTSRHH:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRHH:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register HL-Byte
-VE_SCBTSRHL:
- .dw $ff08
- .db "SCBTSRHL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRHL
-XT_SCBTSRHL:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRHL:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register LH-Byte
-VE_SCBTSRLH:
- .dw $ff08
- .db "SCBTSRLH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRLH
-XT_SCBTSRLH:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRLH:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register LL-Byte
-VE_SCBTSRLL:
- .dw $ff08
- .db "SCBTSRLL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRLL
-XT_SCBTSRLL:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRLL:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register HH-Byte
-VE_SCCNTHH:
- .dw $ff07
- .db "SCCNTHH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTHH
-XT_SCCNTHH:
- .dw PFA_DOVARIABLE
-PFA_SCCNTHH:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register HL-Byte
-VE_SCCNTHL:
- .dw $ff07
- .db "SCCNTHL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTHL
-XT_SCCNTHL:
- .dw PFA_DOVARIABLE
-PFA_SCCNTHL:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register LH-Byte
-VE_SCCNTLH:
- .dw $ff07
- .db "SCCNTLH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTLH
-XT_SCCNTLH:
- .dw PFA_DOVARIABLE
-PFA_SCCNTLH:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register LL-Byte
-VE_SCCNTLL:
- .dw $ff07
- .db "SCCNTLL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTLL
-XT_SCCNTLL:
- .dw PFA_DOVARIABLE
-PFA_SCCNTLL:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Interrupt Status Register
-VE_SCIRQS:
- .dw $ff06
- .db "SCIRQS"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCIRQS
-XT_SCIRQS:
- .dw PFA_DOVARIABLE
-PFA_SCIRQS:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Interrupt Mask Register
-VE_SCIRQM:
- .dw $ff06
- .db "SCIRQM"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCIRQM
-XT_SCIRQM:
- .dw PFA_DOVARIABLE
-PFA_SCIRQM:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Status Register
-VE_SCSR:
- .dw $ff04
- .db "SCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCSR
-XT_SCSR:
- .dw PFA_DOVARIABLE
-PFA_SCSR:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Control Register 1
-VE_SCCR1:
- .dw $ff05
- .db "SCCR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCR1
-XT_SCCR1:
- .dw PFA_DOVARIABLE
-PFA_SCCR1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Control Register 0
-VE_SCCR0:
- .dw $ff05
- .db "SCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCR0
-XT_SCCR0:
- .dw PFA_DOVARIABLE
-PFA_SCCR0:
- .dw 220
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Register
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status Register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status Register C
-VE_ADCSRC:
- .dw $ff06
- .db "ADCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRC
-XT_ADCSRC:
- .dw PFA_DOVARIABLE
-PFA_ADCSRC:
- .dw 119
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 2
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Z-pointer Register for ELPM/SPM
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 2
-VE_PRR2:
- .dw $ff04
- .db "PRR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR2
-XT_PRR2:
- .dw PFA_DOVARIABLE
-PFA_PRR2:
- .dw 99
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_FLASH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Flash Extended-Mode Control-Register
-VE_NEMCR:
- .dw $ff05
- .db "NEMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_NEMCR
-XT_NEMCR:
- .dw PFA_DOVARIABLE
-PFA_NEMCR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Reference Voltage Calibration Register
-VE_BGCR:
- .dw $ff04
- .db "BGCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCR
-XT_BGCR:
- .dw PFA_DOVARIABLE
-PFA_BGCR:
- .dw 103
-
-.endif
-.if WANT_PWRCTRL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Pin Register
-VE_TRXPR:
- .dw $ff05
- .db "TRXPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TRXPR
-XT_TRXPR:
- .dw PFA_DOVARIABLE
-PFA_TRXPR:
- .dw 313
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 0
-VE_DRTRAM0:
- .dw $ff07
- .db "DRTRAM0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM0
-XT_DRTRAM0:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM0:
- .dw 309
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 1
-VE_DRTRAM1:
- .dw $ff07
- .db "DRTRAM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM1
-XT_DRTRAM1:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM1:
- .dw 308
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 2
-VE_DRTRAM2:
- .dw $ff07
- .db "DRTRAM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM2
-XT_DRTRAM2:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM2:
- .dw 307
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 3
-VE_DRTRAM3:
- .dw $ff07
- .db "DRTRAM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM3
-XT_DRTRAM3:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM3:
- .dw 306
-; ( -- addr ) System Constant
-; R( -- )
-; Low Leakage Voltage Regulator Data Register (Low-Byte)
-VE_LLDRL:
- .dw $ff05
- .db "LLDRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LLDRL
-XT_LLDRL:
- .dw PFA_DOVARIABLE
-PFA_LLDRL:
- .dw 304
-; ( -- addr ) System Constant
-; R( -- )
-; Low Leakage Voltage Regulator Data Register (High-Byte)
-VE_LLDRH:
- .dw $ff05
- .db "LLDRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LLDRH
-XT_LLDRH:
- .dw PFA_DOVARIABLE
-PFA_LLDRH:
- .dw 305
-; ( -- addr ) System Constant
-; R( -- )
-; Low Leakage Voltage Regulator Control Register
-VE_LLCR:
- .dw $ff04
- .db "LLCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LLCR
-XT_LLCR:
- .dw PFA_DOVARIABLE
-PFA_LLCR:
- .dw 303
-; ( -- addr ) System Constant
-; R( -- )
-; Port Driver Strength Register 0
-VE_DPDS0:
- .dw $ff05
- .db "DPDS0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DPDS0
-XT_DPDS0:
- .dw PFA_DOVARIABLE
-PFA_DPDS0:
- .dw 310
-; ( -- addr ) System Constant
-; R( -- )
-; Port Driver Strength Register 1
-VE_DPDS1:
- .dw $ff05
- .db "DPDS1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DPDS1
-XT_DPDS1:
- .dw PFA_DOVARIABLE
-PFA_DPDS1:
- .dw 311
-
-.endif
-.if WANT_USART0_SPI == 1
-
-.endif
-.if WANT_USART1_SPI == 1
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.py b/amforth-6.5/avr8/devices/atmega128rfa1/device.py
deleted file mode 100644
index 3e24dfa..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/device.py
+++ /dev/null
@@ -1,991 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega128RFA1
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
- 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
- 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
- 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
- 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
- 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
- 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
- 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
- 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
- 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
- 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
- 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
- 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
- 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
- 'AES_READYAddr' : '#140', # AES engine ready interrupt
- 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART0 I/O Data Register
- 'UCSR0A' : '$c0', # USART0 Control and Status Regi
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Frame Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART0 Control and Status Regi
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART0 Control and Status Regi
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART1 I/O Data Register
- 'UCSR1A' : '$c8', # USART1 Control and Status Regi
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Frame Error
- 'UCSR1A_DOR1': '$8', # Data OverRun
- 'UCSR1A_UPE1': '$4', # USART Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART Transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART1 Control and Status Regi
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART1 Control and Status Regi
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', # TWI Address Mask
- 'TWAMR_Res': '$1', # Reserved Bit
- 'TWBR' : '$b8', # TWI Bit Rate Register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI START Condition Bit
- 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collision Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_Res': '$2', # Reserved Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_Res': '$4', # Reserved Bit
- 'TWSR_TWPS': '$3', # TWI Prescaler Bits
- 'TWDR' : '$bb', # TWI Data Register
- 'TWAR' : '$ba', # TWI (Slave) Address Register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_Res': '$3e', # Reserved
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins Address
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins Address
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins Address
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins Address
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins Address
-
-# Module PORTF
- 'PORTF' : '$31', # Port F Data Register
- 'DDRF' : '$30', # Port F Data Direction Register
- 'PINF' : '$2f', # Port F Input Pins Address
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins Address
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0 Register
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_Res': '$30', # Reserved Bit
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
- 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
- 'TCCR0A_Res': '$c', # Reserved Bit
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_Res': '$f8', # Reserved
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_Res': '$f8', # Reserved
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_Res': '$7c', # Reserved
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_Res': '$f8', # Reserved Bit
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_Res': '$f8', # Reserved Bit
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
- 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
- 'TCCR2A_Res': '$c', # Reserved
- 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_Res': '$30', # Reserved
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
- 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
- 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
- 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
- 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
- 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_Res': '$20', # Reserved Bit
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Clock Select
- 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
- 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
- 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
- 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
- 'TCCR5C_Res': '$1f', # Reserved
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_Res': '$c0', # Reserved Bit
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_Res': '$10', # Reserved Bit
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_Res': '$c0', # Reserved Bit
- 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
- 'TIFR5_Res': '$10', # Reserved Bit
- 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
- 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
- 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_Res': '$20', # Reserved Bit
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Clock Select
- 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
- 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
- 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
- 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
- 'TCCR4C_Res': '$1f', # Reserved
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_Res': '$c0', # Reserved Bit
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_Res': '$10', # Reserved Bit
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_Res': '$c0', # Reserved Bit
- 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
- 'TIFR4_Res': '$10', # Reserved Bit
- 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
- 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
- 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_Res': '$20', # Reserved Bit
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
- 'TCCR3C_Res': '$1f', # Reserved
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_Res': '$c0', # Reserved Bit
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_Res': '$10', # Reserved Bit
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_Res': '$c0', # Reserved Bit
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_Res': '$10', # Reserved Bit
- 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
- 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
- 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_Res': '$20', # Reserved Bit
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
- 'TCCR1C_Res': '$1f', # Reserved
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_Res': '$c0', # Reserved Bit
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_Res': '$10', # Reserved Bit
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_Res': '$c0', # Reserved Bit
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_Res': '$10', # Reserved Bit
- 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TRX24
- 'AES_CTRL' : '$13c', # AES Control Register
- 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
- 'AES_CTRL_Res': '$40', # Reserved Bit
- 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
- 'AES_CTRL_Res': '$10', # Reserved Bit
- 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
- 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
- 'AES_CTRL_Res': '$3', # Reserved Bit
- 'AES_STATUS' : '$13d', # AES Status Register
- 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
- 'AES_STATUS_Res': '$7e', # Reserved
- 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
- 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
- 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
- 'AES_KEY' : '$13f', # AES Encryption and Decryption
- 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
- 'TRX_STATUS' : '$141', # Transceiver Status Register
- 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
- 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
- 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
- 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
- 'TRX_STATE' : '$142', # Transceiver State Control Regi
- 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
- 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
- 'TRX_CTRL_0' : '$143', # Reserved
- 'TRX_CTRL_0_Res': '$ff', # Reserved
- 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
- 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
- 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
- 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
- 'TRX_CTRL_1_Res': '$1f', # Reserved
- 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
- 'PHY_TX_PWR_PA_BUF_LT': '$c0', # Power Amplifier Buffer Lead Ti
- 'PHY_TX_PWR_PA_LT': '$30', # Power Amplifier Lead Time
- 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
- 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
- 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
- 'PHY_RSSI_RND_VALUE': '$60', # Random Value
- 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
- 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
- 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
- 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
- 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
- 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
- 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
- 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
- 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
- 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
- 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
- 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
- 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
- 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
- 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
- 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
- 'TRX_CTRL_2_Res': '$7c', # Reserved
- 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
- 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
- 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
- 'ANT_DIV_Res': '$70', # Reserved
- 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
- 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
- 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
- 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
- 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
- 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
- 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
- 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
- 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
- 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
- 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
- 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
- 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
- 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
- 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
- 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
- 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
- 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
- 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
- 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
- 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
- 'VREG_CTRL' : '$150', # Voltage Regulator Control and
- 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
- 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
- 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
- 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
- 'BATMON' : '$151', # Battery Monitor Control and St
- 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
- 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
- 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
- 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
- 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
- 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
- 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
- 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
- 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
- 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
- 'RX_SYN_Res': '$70', # Reserved
- 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
- 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
- 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
- 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
- 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
- 'XAH_CTRL_1_Res': '$8', # Reserved Bit
- 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
- 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
- 'XAH_CTRL_1_Res': '$1', # Reserved Bit
- 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
- 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
- 'PLL_CF' : '$15a', # Transceiver Center Frequency C
- 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
- 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
- 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
- 'PART_NUM' : '$15c', # Device Identification Register
- 'PART_NUM_PART_NUM': '$ff', # Part Number
- 'VERSION_NUM' : '$15d', # Device Identification Register
- 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
- 'MAN_ID_0' : '$15e', # Device Identification Register
- 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
- 'MAN_ID_1' : '$15f', # Device Identification Register
- 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
- 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
- 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
- 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
- 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
- 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
- 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
- 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
- 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
- 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
- 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
- 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
- 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
- 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
- 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
- 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
- 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
- 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
- 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
- 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
- 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
- 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
- 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
- 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
- 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
- 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
- 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
- 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
- 'TRXFBST' : '$180', # Start of frame buffer
- 'TRXFBEND' : '$1ff', # End of frame buffer
-
-# Module SYMCNT
- 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
- 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
- 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
- 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
- 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
- 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
- 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
- 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
- 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
- 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
- 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
- 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
- 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
- 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
- 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
- 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
- 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
- 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
- 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
- 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
- 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
- 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
- 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
- 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
- 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
- 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
- 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
- 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
- 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
- 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
- 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
- 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
- 'SCIRQS_Res': '$e0', # Reserved Bit
- 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
- 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
- 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
- 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
- 'SCIRQM_Res': '$e0', # Reserved Bit
- 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
- 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
- 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
- 'SCSR' : '$de', # Symbol Counter Status Register
- 'SCSR_Res': '$fe', # Reserved Bit
- 'SCSR_SCBSY': '$1', # Symbol Counter busy
- 'SCCR1' : '$dd', # Symbol Counter Control Registe
- 'SCCR1_Res': '$fe', # Reserved Bit
- 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
- 'SCCR0' : '$dc', # Symbol Counter Control Registe
- 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
- 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
- 'SCCR0_SCEN': '$20', # Symbol Counter enable
- 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
- 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
- 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_Res': '$c0', # Reserved
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
- 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
- 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
- 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
- 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
- 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
- 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request Ena
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flag
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_Res': '$f8', # Reserved Bit
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_Res': '$f8', # Reserved Bit
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC Multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status Reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status Reg
- 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ADCSRB_REFOK': '$20', # Reference Voltage OK
- 'ADCSRB_ACCH': '$10', # Analog Channel Change
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
- 'ADCSRC' : '$77', # The ADC Control and Status Reg
- 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
- 'ADCSRC_Res0': '$20', # Reserved
- 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', # Reserved Bits
- 'DIDR2_ADC14D': '$40', # Reserved Bits
- 'DIDR2_ADC13D': '$20', # Reserved Bits
- 'DIDR2_ADC12D': '$10', # Reserved Bits
- 'DIDR2_ADC11D': '$8', # Reserved Bits
- 'DIDR2_ADC10D': '$4', # Reserved Bits
- 'DIDR2_ADC9D': '$2', # Reserved Bits
- 'DIDR2_ADC8D': '$1', # Reserved Bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_Res': '$60', # Reserved
- 'MCUCR_PUD': '$10', # Pull-up Disable
- 'MCUCR_Res': '$c', # Reserved
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_Res': '$e0', # Reserved
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on Reset Flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_Res': '$70', # Reserved
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_Res': '$f0', # Reserved
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
- 'RAMPZ_Res': '$fc', # Reserved
- 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
- 'PRR2' : '$63', # Power Reduction Register 2
- 'PRR2_Res': '$f0', # Reserved Bit
- 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
- 'PRR1' : '$65', # Power Reduction Register 1
- 'PRR1_Res': '$80', # Reserved Bit
- 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Reserved
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRPGA': '$10', # Power Reduction PGA
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module FLASH
- 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
- 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
- 'NEMCR_AEAM': '$30', # Address for Extended Address M
- 'BGCR' : '$67', # Reference Voltage Calibration
- 'BGCR_Res': '$80', # Reserved Bit
- 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
- 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
-
-# Module PWRCTRL
- 'TRXPR' : '$139', # Transceiver Pin Register
- 'TRXPR_Res': '$f0', # Reserved
- 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
- 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
- 'DRTRAM0' : '$135', # Data Retention Configuration R
- 'DRTRAM0_Res': '$c0', # Reserved
- 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM1' : '$134', # Data Retention Configuration R
- 'DRTRAM1_Res': '$c0', # Reserved
- 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM2' : '$133', # Data Retention Configuration R
- 'DRTRAM2_Res': '$40', # Reserved Bit
- 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM3' : '$132', # Data Retention Configuration R
- 'DRTRAM3_Res': '$c0', # Reserved
- 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
- 'LLDRL' : '$130', # Low Leakage Voltage Regulator
- 'LLDRL_Res': '$f0', # Reserved
- 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
- 'LLDRH' : '$131', # Low Leakage Voltage Regulator
- 'LLDRH_Res': '$e0', # Reserved
- 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
- 'LLCR' : '$12f', # Low Leakage Voltage Regulator
- 'LLCR_Res': '$c0', # Reserved Bit
- 'LLCR_LLDONE': '$20', # Calibration Done
- 'LLCR_LLCOMP': '$10', # Comparator Output
- 'LLCR_LLCAL': '$8', # Calibration Active
- 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
- 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
- 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
- 'DPDS0' : '$136', # Port Driver Strength Register
- 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
- 'DPDS0_PEDRV': '$30', # Driver Strength Port E
- 'DPDS0_PDDRV': '$c', # Driver Strength Port D
- 'DPDS0_PBDRV': '$3', # Driver Strength Port B
- 'DPDS1' : '$137', # Port Driver Strength Register
- 'DPDS1_Res': '$fc', # Reserved
- 'DPDS1_PGDRV': '$3', # Driver Strength Port G
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up Disable
-
-# Module USART0_SPI
- 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
- 'UCSR0C_UDORD0': '$4', # Data Order
- 'UCSR0C_UCPHA0': '$2', # Clock Phase
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
-
-# Module USART1_SPI
- 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
- 'UCSR1C_UDORD1': '$4', # Data Order
- 'UCSR1C_UCPHA1': '$2', # Clock Phase
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt
deleted file mode 100644
index 89b8933..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,79 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index d93c680..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt
deleted file mode 100644
index 20127b2..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt
deleted file mode 100644
index 311193c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt
+++ /dev/null
@@ -1,128 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fe constant RAMPZ_Res \ Reserved
- 5b $fe bitmask: RAMPZ.Res \ Reserved
- $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
- 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt
deleted file mode 100644
index b2d892c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 0bda9c6..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,45 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt
deleted file mode 100644
index 0b34424..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt
+++ /dev/null
@@ -1,16 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/JTAG.frt
deleted file mode 100644
index 8179040..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/JTAG.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTA.frt
deleted file mode 100644
index 65e46f6..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTA.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTB.frt
deleted file mode 100644
index b001eab..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTC.frt
deleted file mode 100644
index 7205bbc..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTC.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTD.frt
deleted file mode 100644
index 075c075..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTE.frt
deleted file mode 100644
index f1aee5d..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTE.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTF.frt
deleted file mode 100644
index d153c62..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTF.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTG.frt
deleted file mode 100644
index 9f0cbf5..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTG.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PWRCTRL.frt
deleted file mode 100644
index ab5d139..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PWRCTRL.frt
+++ /dev/null
@@ -1,81 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SPI.frt
deleted file mode 100644
index 5380282..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SYMCNT.frt
deleted file mode 100644
index 3f52468..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SYMCNT.frt
+++ /dev/null
@@ -1,156 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_0.frt
deleted file mode 100644
index 2cc8dd3..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_0.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index 1b4a1ea..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_2.frt
deleted file mode 100644
index c694b06..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_2.frt
+++ /dev/null
@@ -1,67 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_3.frt
deleted file mode 100644
index 52e7b4c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_3.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_4.frt
deleted file mode 100644
index ffd3366..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_4.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_5.frt
deleted file mode 100644
index 93077e5..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_5.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TRX24.frt
deleted file mode 100644
index 820424b..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TRX24.frt
+++ /dev/null
@@ -1,495 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TWI.frt
deleted file mode 100644
index e4d558c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TWI.frt
+++ /dev/null
@@ -1,40 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0.frt
deleted file mode 100644
index 46bedc3..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0_SPI.frt
deleted file mode 100644
index f5992b7..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1.frt
deleted file mode 100644
index d884da0..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1_SPI.frt
deleted file mode 100644
index 29dbd95..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/WATCHDOG.frt
deleted file mode 100644
index 7cc4b2a..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for atmega128rfr2
-\ #require bitnames.frt
-
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/device.asm b/amforth-6.5/avr8/devices/atmega128rfr2/device.asm
deleted file mode 100644
index 2b8ddbb..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/device.asm
+++ /dev/null
@@ -1,166 +0,0 @@
-; Generated Automatically
-
-.nolist
- include "m128RFR2def.inc"
-.list
-FLASHSTART = 0
-FLASHSIZE = 131072
-RAMEND = 16896
-IRAMSTART = 512
-IRAMSIZE = 16384
-EEPROMSIZE = 4096
-; Interrupt Vectors
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.org 114
- rcall isr ; TRX24 - PLL lock interrupt
-.org 116
- rcall isr ; TRX24 - PLL unlock interrupt
-.org 118
- rcall isr ; TRX24 - Receive start interrupt
-.org 120
- rcall isr ; TRX24 - RX_END interrupt
-.org 122
- rcall isr ; TRX24 - CCA/ED done interrupt
-.org 124
- rcall isr ; TRX24 - XAH - AMI
-.org 126
- rcall isr ; TRX24 - TX_END interrupt
-.org 128
- rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-.org 130
- rcall isr ; Symbol counter - compare match 1 interrupt
-.org 132
- rcall isr ; Symbol counter - compare match 2 interrupt
-.org 134
- rcall isr ; Symbol counter - compare match 3 interrupt
-.org 136
- rcall isr ; Symbol counter - overflow interrupt
-.org 138
- rcall isr ; Symbol counter - backoff interrupt
-.org 140
- rcall isr ; AES engine ready interrupt
-.org 142
- rcall isr ; Battery monitor indicates supply voltage below threshold
-.org 144
- rcall isr ; TRX24 TX start interrupt
-.org 146
- rcall isr ; Address match interrupt of address filter 0
-.org 148
- rcall isr ; Address match interrupt of address filter 1
-.org 150
- rcall isr ; Address match interrupt of address filter 2
-.org 152
- rcall isr ; Address match interrupt of address filter 3
-.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/device.frt b/amforth-6.5/avr8/devices/atmega128rfr2/device.frt
deleted file mode 100644
index a844898..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/device.frt
+++ /dev/null
@@ -1,1752 +0,0 @@
-\ Generated Automatically
-
-\ Interrupt Vectors
-#2 constant INT0Addr \ External Interrupt Request 0
-#4 constant INT1Addr \ External Interrupt Request 1
-#6 constant INT2Addr \ External Interrupt Request 2
-#8 constant INT3Addr \ External Interrupt Request 3
-#10 constant INT4Addr \ External Interrupt Request 4
-#12 constant INT5Addr \ External Interrupt Request 5
-#14 constant INT6Addr \ External Interrupt Request 6
-#16 constant INT7Addr \ External Interrupt Request 7
-#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-#24 constant WDTAddr \ Watchdog Time-out Interrupt
-#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
-#50 constant USART0_RXAddr \ USART0, Rx Complete
-#52 constant USART0_UDREAddr \ USART0 Data register Empty
-#54 constant USART0_TXAddr \ USART0, Tx Complete
-#56 constant ANALOG_COMPAddr \ Analog Comparator
-#58 constant ADCAddr \ ADC Conversion Complete
-#60 constant EE_READYAddr \ EEPROM Ready
-#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-#72 constant USART1_RXAddr \ USART1, Rx Complete
-#74 constant USART1_UDREAddr \ USART1 Data register Empty
-#76 constant USART1_TXAddr \ USART1, Tx Complete
-#78 constant TWIAddr \ 2-wire Serial Interface
-#80 constant SPM_READYAddr \ Store Program Memory Read
-#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-#102 constant USART2_RXAddr \ USART2, Rx Complete
-#104 constant USART2_UDREAddr \ USART2 Data register Empty
-#106 constant USART2_TXAddr \ USART2, Tx Complete
-#108 constant USART3_RXAddr \ USART3, Rx Complete
-#110 constant USART3_UDREAddr \ USART3 Data register Empty
-#112 constant USART3_TXAddr \ USART3, Tx Complete
-#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
-#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
-#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
-#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
-#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
-#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
-#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
-#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
-#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
-#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
-#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
-#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
-#140 constant AES_READYAddr \ AES engine ready interrupt
-#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
-#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
-#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
-#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
-#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
-#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fe constant RAMPZ_Res \ Reserved
- 5b $fe bitmask: RAMPZ.Res \ Reserved
- $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
- 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/device.py b/amforth-6.5/avr8/devices/atmega128rfr2/device.py
deleted file mode 100644
index 3d65d6c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfr2/device.py
+++ /dev/null
@@ -1,1103 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega128RFR2
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
- 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
- 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
- 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
- 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
- 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
- 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
- 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
- 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
- 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
- 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
- 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
- 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
- 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
- 'AES_READYAddr' : '#140', # AES engine ready interrupt
- 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
- 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
- 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
- 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
- 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
- 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART0 I/O Data Register
- 'UCSR0A' : '$c0', # USART0 Control and Status Regi
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Frame Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART0 Control and Status Regi
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART0 Control and Status Regi
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART1 I/O Data Register
- 'UCSR1A' : '$c8', # USART1 Control and Status Regi
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Frame Error
- 'UCSR1A_DOR1': '$8', # Data OverRun
- 'UCSR1A_UPE1': '$4', # USART Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART Transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART1 Control and Status Regi
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART1 Control and Status Regi
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', # TWI Address Mask
- 'TWAMR_Res': '$1', # Reserved Bit
- 'TWBR' : '$b8', # TWI Bit Rate Register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI START Condition Bit
- 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collision Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_Res': '$2', # Reserved Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_Res': '$4', # Reserved Bit
- 'TWSR_TWPS': '$3', # TWI Prescaler Bits
- 'TWDR' : '$bb', # TWI Data Register
- 'TWAR' : '$ba', # TWI (Slave) Address Register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_Res': '$3e', # Reserved
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins Address
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins Address
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins Address
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins Address
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins Address
-
-# Module PORTF
- 'PORTF' : '$31', # Port F Data Register
- 'DDRF' : '$30', # Port F Data Direction Register
- 'PINF' : '$2f', # Port F Input Pins Address
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins Address
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0 Register
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_Res': '$30', # Reserved Bit
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
- 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
- 'TCCR0A_Res': '$c', # Reserved Bit
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_Res': '$f8', # Reserved
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_Res': '$f8', # Reserved
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_Res': '$7c', # Reserved
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_Res': '$f8', # Reserved Bit
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_Res': '$f8', # Reserved Bit
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
- 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
- 'TCCR2A_Res': '$c', # Reserved
- 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_Res': '$30', # Reserved
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
- 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
- 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
- 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
- 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
- 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_Res': '$20', # Reserved Bit
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Clock Select
- 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
- 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
- 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
- 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
- 'TCCR5C_Res': '$1f', # Reserved
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_Res': '$c0', # Reserved Bit
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_Res': '$10', # Reserved Bit
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_Res': '$c0', # Reserved Bit
- 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
- 'TIFR5_Res': '$10', # Reserved Bit
- 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
- 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
- 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_Res': '$20', # Reserved Bit
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Clock Select
- 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
- 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
- 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
- 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
- 'TCCR4C_Res': '$1f', # Reserved
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_Res': '$c0', # Reserved Bit
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_Res': '$10', # Reserved Bit
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_Res': '$c0', # Reserved Bit
- 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
- 'TIFR4_Res': '$10', # Reserved Bit
- 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
- 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
- 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_Res': '$20', # Reserved Bit
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
- 'TCCR3C_Res': '$1f', # Reserved
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_Res': '$c0', # Reserved Bit
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_Res': '$10', # Reserved Bit
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_Res': '$c0', # Reserved Bit
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_Res': '$10', # Reserved Bit
- 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
- 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
- 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_Res': '$20', # Reserved Bit
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
- 'TCCR1C_Res': '$1f', # Reserved
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_Res': '$c0', # Reserved Bit
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_Res': '$10', # Reserved Bit
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_Res': '$c0', # Reserved Bit
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_Res': '$10', # Reserved Bit
- 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TRX24
- 'PARCR' : '$138', # Power Amplifier Ramp up/down C
- 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
- 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
- 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
- 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
- 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
- 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
- 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
- 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
- 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
- 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA1L' : '$112', # Transceiver MAC Short Address
- 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
- 'MAFSA1H' : '$113', # Transceiver MAC Short Address
- 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
- 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
- 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA2L' : '$116', # Transceiver MAC Short Address
- 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
- 'MAFSA2H' : '$117', # Transceiver MAC Short Address
- 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
- 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
- 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
- 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
- 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
- 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
- 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
- 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
- 'MAFCR0' : '$10c', # Multiple Address Filter Config
- 'MAFCR0_Res': '$f0', # Reserved Bit
- 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
- 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
- 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
- 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
- 'MAFCR1' : '$10d', # Multiple Address Filter Config
- 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
- 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
- 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
- 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
- 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
- 'AES_CTRL' : '$13c', # AES Control Register
- 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
- 'AES_CTRL_Res': '$40', # Reserved Bit
- 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
- 'AES_CTRL_Res': '$10', # Reserved Bit
- 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
- 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
- 'AES_CTRL_Res': '$3', # Reserved Bit
- 'AES_STATUS' : '$13d', # AES Status Register
- 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
- 'AES_STATUS_Res': '$7e', # Reserved
- 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
- 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
- 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
- 'AES_KEY' : '$13f', # AES Encryption and Decryption
- 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
- 'TRX_STATUS' : '$141', # Transceiver Status Register
- 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
- 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
- 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
- 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
- 'TRX_STATE' : '$142', # Transceiver State Control Regi
- 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
- 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
- 'TRX_CTRL_0' : '$143', # Reserved
- 'TRX_CTRL_0_Res7': '$80', # Reserved
- 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
- 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
- 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
- 'TRX_CTRL_0_Res': '$f', # Reserved
- 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
- 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
- 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
- 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
- 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
- 'TRX_CTRL_1_Res': '$f', # Reserved
- 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
- 'PHY_TX_PWR_Res': '$f0', # Reserved
- 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
- 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
- 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
- 'PHY_RSSI_RND_VALUE': '$60', # Random Value
- 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
- 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
- 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
- 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
- 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
- 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
- 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
- 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
- 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
- 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
- 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
- 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
- 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
- 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
- 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
- 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
- 'TRX_CTRL_2_Res': '$7c', # Reserved
- 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
- 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
- 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
- 'ANT_DIV_Res': '$70', # Reserved
- 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
- 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
- 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
- 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
- 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
- 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
- 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
- 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
- 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
- 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
- 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
- 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
- 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
- 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
- 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
- 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
- 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
- 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
- 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
- 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
- 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
- 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
- 'IRQ_MASK1_Res': '$e0', # Reserved Bit
- 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
- 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
- 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
- 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
- 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
- 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
- 'VREG_CTRL' : '$150', # Voltage Regulator Control and
- 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
- 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
- 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
- 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
- 'BATMON' : '$151', # Battery Monitor Control and St
- 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
- 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
- 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
- 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
- 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
- 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
- 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
- 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
- 'CC_CTRL_0' : '$153', # Channel Control Register 0
- 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
- 'CC_CTRL_1' : '$154', # Channel Control Register 1
- 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
- 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
- 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
- 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
- 'RX_SYN_Res': '$30', # Reserved
- 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
- 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
- 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
- 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
- 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
- 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
- 'TRX_RPC_Res0': '$4', # Reserved
- 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
- 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
- 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
- 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
- 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
- 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
- 'XAH_CTRL_1_Res': '$8', # Reserved Bit
- 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
- 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
- 'XAH_CTRL_1_Res': '$1', # Reserved Bit
- 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
- 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
- 'PLL_CF' : '$15a', # Transceiver Center Frequency C
- 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
- 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
- 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
- 'PART_NUM' : '$15c', # Device Identification Register
- 'PART_NUM_PART_NUM': '$ff', # Part Number
- 'VERSION_NUM' : '$15d', # Device Identification Register
- 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
- 'MAN_ID_0' : '$15e', # Device Identification Register
- 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
- 'MAN_ID_1' : '$15f', # Device Identification Register
- 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
- 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
- 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
- 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
- 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
- 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
- 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
- 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
- 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
- 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
- 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
- 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
- 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
- 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
- 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
- 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
- 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
- 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
- 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
- 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
- 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
- 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
- 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
- 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
- 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
- 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
- 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
- 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
- 'TRXFBST' : '$180', # Start of frame buffer
- 'TRXFBEND' : '$1ff', # End of frame buffer
-
-# Module SYMCNT
- 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
- 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
- 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
- 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
- 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
- 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
- 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
- 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
- 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
- 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
- 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
- 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
- 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
- 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
- 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
- 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
- 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
- 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
- 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
- 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
- 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
- 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
- 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
- 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
- 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
- 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
- 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
- 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
- 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
- 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
- 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
- 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
- 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
- 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
- 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
- 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
- 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
- 'SCIRQS_Res': '$e0', # Reserved Bit
- 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
- 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
- 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
- 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
- 'SCIRQM_Res': '$e0', # Reserved Bit
- 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
- 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
- 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
- 'SCSR' : '$de', # Symbol Counter Status Register
- 'SCSR_Res': '$fe', # Reserved Bit
- 'SCSR_SCBSY': '$1', # Symbol Counter busy
- 'SCCR1' : '$dd', # Symbol Counter Control Registe
- 'SCCR1_Res': '$c0', # Reserved Bit
- 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
- 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
- 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
- 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
- 'SCCR0' : '$dc', # Symbol Counter Control Registe
- 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
- 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
- 'SCCR0_SCEN': '$20', # Symbol Counter enable
- 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
- 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
- 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
- 'SCCSR' : '$db', # Symbol Counter Compare Source
- 'SCCSR_Res': '$c0', # Reserved Bit
- 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
- 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
- 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
- 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
- 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
- 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
- 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
- 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_Res': '$c0', # Reserved
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
- 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
- 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
- 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
- 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
- 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
- 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request Ena
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flag
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_Res': '$f8', # Reserved Bit
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_Res': '$f8', # Reserved Bit
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC Multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status Reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status Reg
- 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ADCSRB_REFOK': '$20', # Reference Voltage OK
- 'ADCSRB_ACCH': '$10', # Analog Channel Change
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
- 'ADCSRC' : '$77', # The ADC Control and Status Reg
- 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
- 'ADCSRC_Res0': '$20', # Reserved
- 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', # Reserved Bits
- 'DIDR2_ADC14D': '$40', # Reserved Bits
- 'DIDR2_ADC13D': '$20', # Reserved Bits
- 'DIDR2_ADC12D': '$10', # Reserved Bits
- 'DIDR2_ADC11D': '$8', # Reserved Bits
- 'DIDR2_ADC10D': '$4', # Reserved Bits
- 'DIDR2_ADC9D': '$2', # Reserved Bits
- 'DIDR2_ADC8D': '$1', # Reserved Bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_Res': '$60', # Reserved
- 'MCUCR_PUD': '$10', # Pull-up Disable
- 'MCUCR_Res': '$c', # Reserved
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_Res': '$e0', # Reserved
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on Reset Flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_Res': '$70', # Reserved
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_Res': '$f0', # Reserved
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
- 'RAMPZ_Res': '$fe', # Reserved
- 'RAMPZ_RAMPZ0': '$1', # Extended Z-Pointer Value
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
- 'PRR2' : '$63', # Power Reduction Register 2
- 'PRR2_Res': '$f0', # Reserved Bit
- 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
- 'PRR1' : '$65', # Power Reduction Register 1
- 'PRR1_Res': '$80', # Reserved Bit
- 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRPGA': '$10', # Power Reduction PGA
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module FLASH
- 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
- 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
- 'NEMCR_AEAM': '$30', # Address for Extended Address M
- 'BGCR' : '$67', # Reference Voltage Calibration
- 'BGCR_Res': '$80', # Reserved Bit
- 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
- 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
-
-# Module PWRCTRL
- 'TRXPR' : '$139', # Transceiver Pin Register
- 'TRXPR_Res': '$f0', # Reserved
- 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
- 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
- 'DRTRAM0' : '$135', # Data Retention Configuration R
- 'DRTRAM0_Res': '$c0', # Reserved
- 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM1' : '$134', # Data Retention Configuration R
- 'DRTRAM1_Res': '$c0', # Reserved
- 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM2' : '$133', # Data Retention Configuration R
- 'DRTRAM2_Res': '$40', # Reserved Bit
- 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM3' : '$132', # Data Retention Configuration R
- 'DRTRAM3_Res': '$c0', # Reserved
- 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
- 'LLDRL' : '$130', # Low Leakage Voltage Regulator
- 'LLDRL_Res': '$f0', # Reserved
- 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
- 'LLDRH' : '$131', # Low Leakage Voltage Regulator
- 'LLDRH_Res': '$e0', # Reserved
- 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
- 'LLCR' : '$12f', # Low Leakage Voltage Regulator
- 'LLCR_Res': '$c0', # Reserved Bit
- 'LLCR_LLDONE': '$20', # Calibration Done
- 'LLCR_LLCOMP': '$10', # Comparator Output
- 'LLCR_LLCAL': '$8', # Calibration Active
- 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
- 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
- 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
- 'DPDS0' : '$136', # Port Driver Strength Register
- 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
- 'DPDS0_PEDRV': '$30', # Driver Strength Port E
- 'DPDS0_PDDRV': '$c', # Driver Strength Port D
- 'DPDS0_PBDRV': '$3', # Driver Strength Port B
- 'DPDS1' : '$137', # Port Driver Strength Register
- 'DPDS1_Res': '$fc', # Reserved
- 'DPDS1_PGDRV': '$3', # Driver Strength Port G
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up Disable
-
-# Module USART0_SPI
- 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
- 'UCSR0C_UDORD0': '$4', # Data Order
- 'UCSR0C_UCPHA0': '$2', # Clock Phase
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
-
-# Module USART1_SPI
- 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
- 'UCSR1C_UDORD1': '$4', # Data Order
- 'UCSR1C_UCPHA1': '$2', # Clock Phase
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16/atmega16.frt b/amforth-6.5/avr8/devices/atmega16/atmega16.frt
deleted file mode 100644
index 2f95ec1..0000000
--- a/amforth-6.5/avr8/devices/atmega16/atmega16.frt
+++ /dev/null
@@ -1,221 +0,0 @@
-\ Partname: ATmega16
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&92 constant OCR0 \ Output Compare Register
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-&80 constant SFIOR \ Special Function IO Register
- $01 constant SFIOR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
-&85 constant MCUCR \ General Interrupt Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&81 constant OSCCAL \ Oscillator Calibration Value
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ ANALOG_COMPARATOR
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDTOE \ RW
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&8 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&14 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&16 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&18 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&20 constant SPI_STCAddr \ Serial Transfer Complete
-&22 constant USART_RXCAddr \ USART, Rx Complete
-&24 constant USART_UDREAddr \ USART Data Register Empty
-&26 constant USART_TXCAddr \ USART, Tx Complete
-&28 constant ADCAddr \ ADC Conversion Complete
-&30 constant EE_RDYAddr \ EEPROM Ready
-&32 constant ANA_COMPAddr \ Analog Comparator
-&34 constant TWIAddr \ 2-wire Serial Interface
-&36 constant INT2Addr \ External Interrupt Request 2
-&38 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega16/device.asm b/amforth-6.5/avr8/devices/atmega16/device.asm
deleted file mode 100644
index f0ec3af..0000000
--- a/amforth-6.5/avr8/devices/atmega16/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega16
-; generated automatically, do not edit
-
-.nolist
- .include "m16def.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_SPI = 0
-.set WANT_USART = 0
-.set WANT_TWI = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_WATCHDOG = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Timer/Counter2 Compare Match
-.org 8
- rcall isr ; Timer/Counter2 Overflow
-.org 10
- rcall isr ; Timer/Counter1 Capture Event
-.org 12
- rcall isr ; Timer/Counter1 Compare Match A
-.org 14
- rcall isr ; Timer/Counter1 Compare Match B
-.org 16
- rcall isr ; Timer/Counter1 Overflow
-.org 18
- rcall isr ; Timer/Counter0 Overflow
-.org 20
- rcall isr ; Serial Transfer Complete
-.org 22
- rcall isr ; USART, Rx Complete
-.org 24
- rcall isr ; USART Data Register Empty
-.org 26
- rcall isr ; USART, Tx Complete
-.org 28
- rcall isr ; ADC Conversion Complete
-.org 30
- rcall isr ; EEPROM Ready
-.org 32
- rcall isr ; Analog Comparator
-.org 34
- rcall isr ; 2-wire Serial Interface
-.org 36
- rcall isr ; External Interrupt Request 2
-.org 38
- rcall isr ; Timer/Counter0 Compare Match
-.org 40
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 21
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 8
- .db "ATmega16"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16/device.inc b/amforth-6.5/avr8/devices/atmega16/device.inc
deleted file mode 100644
index 04e4766..0000000
--- a/amforth-6.5/avr8/devices/atmega16/device.inc
+++ /dev/null
@@ -1,765 +0,0 @@
-; Partname: ATmega16
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16/device.py b/amforth-6.5/avr8/devices/atmega16/device.py
deleted file mode 100644
index cd9f581..0000000
--- a/amforth-6.5/avr8/devices/atmega16/device.py
+++ /dev/null
@@ -1,284 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'TIMER2_COMPAddr' : '#6', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#8', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#10', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#12', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#14', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#16', # Timer/Counter1 Overflow
- 'TIMER0_OVFAddr' : '#18', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#20', # Serial Transfer Complete
- 'USART_RXCAddr' : '#22', # USART, Rx Complete
- 'USART_UDREAddr' : '#24', # USART Data Register Empty
- 'USART_TXCAddr' : '#26', # USART, Tx Complete
- 'ADCAddr' : '#28', # ADC Conversion Complete
- 'EE_RDYAddr' : '#30', # EEPROM Ready
- 'ANA_COMPAddr' : '#32', # Analog Comparator
- 'TWIAddr' : '#34', # 2-wire Serial Interface
- 'INT2Addr' : '#36', # External Interrupt Request 2
- 'TIMER0_COMPAddr' : '#38', # Timer/Counter0 Compare Match
- 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$5c', # Output Compare Register
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
- 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module EXTERNAL_INTERRUPT
- 'GICR' : '$5b', # General Interrupt Control Regi
- 'GICR_INT': '$c0', # External Interrupt Request 1 E
- 'GICR_INT2': '$20', # External Interrupt Request 2 E
- 'GICR_IVSEL': '$2', # Interrupt Vector Select
- 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
- 'GIFR' : '$5a', # General Interrupt Flag Registe
- 'GIFR_INTF': '$c0', # External Interrupt Flags
- 'GIFR_INTF2': '$20', # External Interrupt Flag 2
- 'MCUCR' : '$55', # General Interrupt Control Regi
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Address Register Bytes
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SM': '$b0', # Sleep Mode Select
- 'MCUCR_SE': '$40', # Sleep Enable
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$51', # Oscillator Calibration Value
- 'SFIOR' : '$50', # Special function I/O register
- 'SFIOR_PUD': '$4', # Pull-up Disable
- 'SFIOR_PSR2': '$2', # Prescaler reset
- 'SFIOR_PSR10': '$1', # Prescaler reset
-
-# Module TIMER_COUNTER_2
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
- 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
- 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TCCR2' : '$45', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Waveform Genration Mode
- 'TCCR2_COM2': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$44', # Timer/Counter2
- 'OCR2' : '$43', # Timer/Counter2 Output Compare
- 'ASSR' : '$42', # Asynchronous Status Register
- 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
- 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module USART
- 'UDR' : '$2c', # USART I/O Data Register
- 'UCSRA' : '$2b', # USART Control and Status Regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data overRun
- 'UCSRA_UPE': '$4', # Parity Error
- 'UCSRA_U2X': '$2', # Double the USART transmission
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$2a', # USART Control and Status Regis
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$40', # USART Control and Status Regis
- 'UCSRC_URSEL': '$80', # Register Select
- 'UCSRC_UMSEL': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$40', # USART Baud Rate Register Hight
- 'UBRRL' : '$29', # USART Baud Rate Register Low B
-
-# Module TWI
- 'TWBR' : '$20', # TWI Bit Rate register
- 'TWCR' : '$56', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$21', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$23', # TWI Data register
- 'TWAR' : '$22', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # When this bit is written to on
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$24', # ADC Data Register Bytes
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDTOE': '$10', # RW
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega16/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega161/atmega161.frt b/amforth-6.5/avr8/devices/atmega161/atmega161.frt
deleted file mode 100644
index e8d2119..0000000
--- a/amforth-6.5/avr8/devices/atmega161/atmega161.frt
+++ /dev/null
@@ -1,121 +0,0 @@
-\ Partname: ATmega161
-\ Built using part description XML file version 233
-\ generated automatically
-
-hex
-
-\ ANALOG_COMPARATOR
-28 constant ACSR \ Analog Comparator Control And Status Register
-
-\ CPU
-56 constant EMCUCR \ Extended MCU Control Register
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-57 constant SPMCR \ Store Program Memory Control Register
-5F constant SREG \ Status Register
-
-\ EEPROM
-3F constant EEARH \ EEPROM Address Register High Byte
-3E constant EEARL \ EEPROM Address Register Low Byte
-3C constant EECR \ EEPROM Control Register
-3D constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-5A constant GIFR \ General Interrupt Flag Register
-5B constant GIMSK \ General Interrupt Mask Register
-
-\ PORTA
-3A constant DDRA \ Port A Data Direction Register
-39 constant PINA \ Port A Input Pins
-3B constant PORTA \ Port A Data Register
-
-\ PORTB
-37 constant DDRB \ Port B Data Direction Register
-36 constant PINB \ Port B Input Pins
-38 constant PORTB \ Port B Data Register
-
-\ PORTC
-34 constant DDRC \ Port C Data Direction Register
-33 constant PINC \ Port C Input Pins
-35 constant PORTC \ Port C Data Register
-
-\ PORTD
-31 constant DDRD \ Port D Data Direction Register
-30 constant PIND \ Port D Input Pins
-32 constant PORTD \ Port D Data Register
-
-\ PORTE
-26 constant DDRE \ Port E Data Direction Register
-25 constant PINE \ Port E Input Pins
-27 constant PORTE \ Port E Data Register
-
-\ SPI
-2D constant SPCR \ SPI Control Register
-2F constant SPDR \ SPI Data Register
-2E constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-51 constant OCR0 \ Output Compare Register
-50 constant SFIOR \ Special Function IO Register
-53 constant TCCR0 \ Timer/Counter Control Register
-52 constant TCNT0 \ Timer/Counter Register
-58 constant TIFR \ Timer/Counter Interrupt Flag register
-59 constant TIMSK \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-45 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-44 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-4F constant TCCR1A \ Timer/Counter1 Control Register A
-4E constant TCCR1B \ Timer/Counter1 Control Register B
-4D constant TCNT1H \ Timer/Counter1 High Byte
-4C constant TCNT1L \ Timer/Counter1 Low Byte
-
-\ TIMER_COUNTER_2
-46 constant ASSR \ Asynchronous Status Register
-42 constant OCR2 \ Timer/Counter2 Output Compare Register
-47 constant TCCR2 \ Timer/Counter2 Control Register
-43 constant TCNT2 \ Timer/Counter2
-
-\ USART0
-29 constant UBRR0 \ USART Baud Rate Register Byte
-40 constant UBRRHI \ High Byte Baud Rate Register
-2B constant UCSR0A \ USART Control and Status Register A
-2A constant UCSR0B \ USART Control and Status Register B
-2C constant UDR0 \ USART I/O Data Register
-
-\ USART1
-20 constant UBRR1 \ USART Baud Rate Register Byte
-22 constant UCSR1A \ USART Control and Status Register A
-21 constant UCSR1B \ USART Control and Status Register B
-23 constant UDR1 \ USART I/O Data Register
-
-\ WATCHDOG
-41 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt 0
-004 constant INT1Addr \ External Interrupt 1
-006 constant INT2Addr \ External Interrupt 2
-008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-010 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-018 constant SPISTCAddr \ Serial Transfer Complete
-01A constant UART0RXAddr \ UART0, Rx Complete
-01C constant UART1RXAddr \ UART1, Rx Complete
-01E constant UART0UDREAddr \ UART0 Data Register Empty
-020 constant UART1UDREAddr \ UART1 Data Register Empty
-022 constant UART0TXAddr \ UART0, Tx Complete
-024 constant UART1TXAddr \ UART1, Tx Complete
-026 constant EE_RDYAddr \ EEPROM Ready
-028 constant ANA_COMPAddr \ Analog Comparator
diff --git a/amforth-6.5/avr8/devices/atmega161/device.asm b/amforth-6.5/avr8/devices/atmega161/device.asm
deleted file mode 100644
index 6208a6e..0000000
--- a/amforth-6.5/avr8/devices/atmega161/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: ATmega161
-; Built using part description XML file version 233
-; generated automatically, do not edit
-
-.nolist
- .include "m161def.inc"
-.list
-
-.equ ramstart = $60
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 21
-.org $002
- rcall isr ; External Interrupt 0
-.org $004
- rcall isr ; External Interrupt 1
-.org $006
- rcall isr ; External Interrupt 2
-.org $008
- rcall isr ; Timer/Counter2 Compare Match
-.org $00A
- rcall isr ; Timer/Counter2 Overflow
-.org $00C
- rcall isr ; Timer/Counter1 Capture Event
-.org $00E
- rcall isr ; Timer/Counter1 Compare Match A
-.org $010
- rcall isr ; Timer/Counter1 Compare Match B
-.org $012
- rcall isr ; Timer/Counter1 Overflow
-.org $014
- rcall isr ; Timer/Counter0 Compare Match
-.org $016
- rcall isr ; Timer/Counter0 Overflow
-.org $018
- rcall isr ; Serial Transfer Complete
-.org $01A
- rcall isr ; UART0, Rx Complete
-.org $01C
- rcall isr ; UART1, Rx Complete
-.org $01E
- rcall isr ; UART0 Data Register Empty
-.org $020
- rcall isr ; UART1 Data Register Empty
-.org $022
- rcall isr ; UART0, Tx Complete
-.org $024
- rcall isr ; UART1, Tx Complete
-.org $026
- rcall isr ; EEPROM Ready
-.org $028
- rcall isr ; Analog Comparator
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 0 ; minimum of 0 (from XML) and 0xffff
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 9
- .db "ATmega161",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega161/device.inc b/amforth-6.5/avr8/devices/atmega161/device.inc
deleted file mode 100644
index 0cedf69..0000000
--- a/amforth-6.5/avr8/devices/atmega161/device.inc
+++ /dev/null
@@ -1,843 +0,0 @@
-; Partname: ATmega161
-; Built using part description XML file version 233
-; generated automatically, no not edit
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Extended MCU Control Register
-VE_EMCUCR:
- .dw $ff06
- .db "EMCUCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EMCUCR
-XT_EMCUCR:
- .dw PFA_DOVARIABLE
-PFA_EMCUCR:
- .dw $56
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw $57
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw $5A
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Mask Register
-VE_GIMSK:
- .dw $ff05
- .db "GIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GIMSK
-XT_GIMSK:
- .dw PFA_DOVARIABLE
-PFA_GIMSK:
- .dw $5B
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $3B
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $38
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $34
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $33
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $35
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $31
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $32
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $25
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $27
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw $51
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw $50
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $52
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw $58
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw $59
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $4F
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $4D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $4C
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $43
-
-.endif
-
-; ********
-.if WANT_USART0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Byte
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; High Byte Baud Rate Register
-VE_UBRRHI:
- .dw $ff06
- .db "UBRRHI"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRHI
-XT_UBRRHI:
- .dw PFA_DOVARIABLE
-PFA_UBRRHI:
- .dw $40
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw $2B
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw $2C
-
-.endif
-
-; ********
-.if WANT_USART1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Byte
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw $22
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw $23
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $41
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega161/device.py b/amforth-6.5/avr8/devices/atmega161/device.py
deleted file mode 100644
index 3f30afc..0000000
--- a/amforth-6.5/avr8/devices/atmega161/device.py
+++ /dev/null
@@ -1,87 +0,0 @@
-# Partname: ATmega161
-# Built using part description XML file version 233
-# generated automatically, do not edit
-MCUREGS = {
- 'ACSR': '$28',
- 'EMCUCR': '$56',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SPMCR': '$57',
- 'SREG': '$5F',
- 'EEARH': '$3F',
- 'EEARL': '$3E',
- 'EECR': '$3C',
- 'EEDR': '$3D',
- 'GIFR': '$5A',
- 'GIMSK': '$5B',
- 'DDRA': '$3A',
- 'PINA': '$39',
- 'PORTA': '$3B',
- 'DDRB': '$37',
- 'PINB': '$36',
- 'PORTB': '$38',
- 'DDRC': '$34',
- 'PINC': '$33',
- 'PORTC': '$35',
- 'DDRD': '$31',
- 'PIND': '$30',
- 'PORTD': '$32',
- 'DDRE': '$26',
- 'PINE': '$25',
- 'PORTE': '$27',
- 'SPCR': '$2D',
- 'SPDR': '$2F',
- 'SPSR': '$2E',
- 'OCR0': '$51',
- 'SFIOR': '$50',
- 'TCCR0': '$53',
- 'TCNT0': '$52',
- 'TIFR': '$58',
- 'TIMSK': '$59',
- 'ICR1H': '$45',
- 'ICR1L': '$44',
- 'OCR1AH': '$4B',
- 'OCR1AL': '$4A',
- 'OCR1BH': '$49',
- 'OCR1BL': '$48',
- 'TCCR1A': '$4F',
- 'TCCR1B': '$4E',
- 'TCNT1H': '$4D',
- 'TCNT1L': '$4C',
- 'ASSR': '$46',
- 'OCR2': '$42',
- 'TCCR2': '$47',
- 'TCNT2': '$43',
- 'UBRR0': '$29',
- 'UBRRHI': '$40',
- 'UCSR0A': '$2B',
- 'UCSR0B': '$2A',
- 'UDR0': '$2C',
- 'UBRR1': '$20',
- 'UCSR1A': '$22',
- 'UCSR1B': '$21',
- 'UDR1': '$23',
- 'WDTCR': '$41',
- 'INT0Addr': '$002',
- 'INT1Addr': '$004',
- 'INT2Addr': '$006',
- 'TIMER2_COMPAddr': '$008',
- 'TIMER2_OVFAddr': '$00A',
- 'TIMER1_CAPTAddr': '$00C',
- 'TIMER1_COMPAAddr': '$00E',
- 'TIMER1_COMPBAddr': '$010',
- 'TIMER1_OVFAddr': '$012',
- 'TIMER0_COMPAddr': '$014',
- 'TIMER0_OVFAddr': '$016',
- 'SPISTCAddr': '$018',
- 'UART0RXAddr': '$01A',
- 'UART1RXAddr': '$01C',
- 'UART0UDREAddr': '$01E',
- 'UART1UDREAddr': '$020',
- 'UART0TXAddr': '$022',
- 'UART1TXAddr': '$024',
- 'EE_RDYAddr': '$026',
- 'ANA_COMPAddr': '$028'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega162/atmega162.frt b/amforth-6.5/avr8/devices/atmega162/atmega162.frt
deleted file mode 100644
index e656277..0000000
--- a/amforth-6.5/avr8/devices/atmega162/atmega162.frt
+++ /dev/null
@@ -1,289 +0,0 @@
-\ Partname: ATmega162
-\ generated automatically
-
-\ TIMER_COUNTER_1
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $80 constant TIMSK_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
- $40 constant TIMSK_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $20 constant TIMSK_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $08 constant TIMSK_TICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $80 constant TIFR_TOV1 \ Timer/Counter1 Overflow Flag
- $40 constant TIFR_OCF1A \ Output Compare Flag 1A
- $20 constant TIFR_OCF1B \ Output Compare Flag 1B
- $08 constant TIFR_ICF1 \ Input Capture Flag 1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare for Channel A
- $04 constant TCCR1A_FOC1B \ Force Output Compare for Channel B
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Pulse Width Modulator Select Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&68 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&71 constant TCCR2 \ Timer/Counter Control Register
- $80 constant TCCR2_FOC2 \ Forde Output Compare
- $40 constant TCCR2_WGM20 \ Pulse Width Modulator Select Bit 0
- $30 constant TCCR2_COM2 \ Compare Match Output Mode
- $08 constant TCCR2_WGM21 \ Pulse Width Modulator Select Bit 1
- $07 constant TCCR2_CS2 \ Clock Select
-&67 constant TCNT2 \ Timer/Counter Register
-&66 constant OCR2 \ Output Compare Register
-&70 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer 2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_3
-&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
- $20 constant ETIMSK_TICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $10 constant ETIMSK_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
- $08 constant ETIMSK_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
- $04 constant ETIMSK_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
- $20 constant ETIFR_ICF3 \ Input Capture Flag 3
- $10 constant ETIFR_OCF3A \ Output Compare Flag 3A
- $08 constant ETIFR_OCF3B \ Output Compare Flag 3B
- $04 constant ETIFR_TOV3 \ Timer/Counter3 Overflow Flag
-&139 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $08 constant TCCR3A_FOC3A \ Force Output Compare for Channel A
- $04 constant TCCR3A_FOC3B \ Force Output Compare for Channel B
- $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits
-&138 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Pulse Width Modulator Select Bits
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&136 constant TCNT3 \ Timer/Counter3 Bytes
-&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&132 constant OCR3B \ Timer/Counte3 Output Compare Register B Bytes
-&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ ANALOG_COMPARATOR
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ USART0
-&44 constant UDR0 \ USART I/O Data Register
-&43 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&42 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&64 constant UCSR0C \ USART Control and Status Register C
- $80 constant UCSR0C_URSEL0 \ Register Select
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&64 constant UBRR0H \ USART Baud Rate Register Hight Byte
-&41 constant UBRR0L \ USART Baud Rate Register Low Byte
-\ USART1
-&35 constant UDR \ USART I/O Data Register
-&34 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&33 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&92 constant UCSR1C \ USART Control and Status Register C
- $80 constant UCSR1C_URSEL1 \ Register Select
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&92 constant UBRR1H \ USART Baud Rate Register Highg Byte
-&32 constant UBRR1L \ USART Baud Rate Register Low Byte
-\ SPI
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&47 constant SPDR \ SPI Data Register
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SRE \ External SRAM Enable
- $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
- $20 constant MCUCR_SE \ Sleep Enable
- $10 constant MCUCR_SM1 \ Sleep Mode Select
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $80 constant MCUCSR_JDT \ JTAG Interface Disable
- $20 constant MCUCSR_SM2 \ Sleep Mode Select Bit 2
- $10 constant MCUCSR_JTRF \ JTAG Reset Flag
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&86 constant EMCUCR \ Extended MCU Control Register
- $80 constant EMCUCR_SM0 \ Sleep mode Select Bit 0
- $70 constant EMCUCR_SRL \ Wait State Sector Limit Bits
- $0C constant EMCUCR_SRW0 \ Wait State Select Bit 1 for Lower Sector
- $02 constant EMCUCR_SRW11 \ Wait State Select Bit 1 for Upper Sector
- $01 constant EMCUCR_ISC2 \ Interrupt Sense Control 2
-&36 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock prescale register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&80 constant SFIOR \ Special Function IO Register
- $80 constant SFIOR_TSM \ Timer/Counter Synchronization Mode
- $40 constant SFIOR_XMBK \ External Memory Bus Keeper Enable
- $38 constant SFIOR_XMM \ External Memory High Mask Bits
- $04 constant SFIOR_PUD \ Pull-up Disable
- $02 constant SFIOR_PSR2 \ Prescaler Reset Timer/Counter2
- $01 constant SFIOR_PSR310 \ Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0
-\ JTAG
-&36 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ BOOT_LOAD
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read While Write secion read enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter 0 Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter 0 Register
-&81 constant OCR0 \ Timer/Counter 0 Output Compare Register
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ PORTE
-&39 constant PORTE \ Data Register, Port E
-&38 constant DDRE \ Data Direction Register, Port E
-&37 constant PINE \ Input Pins, Port E
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $18 constant GICR_PCIE \ Pin Change Interrupt Enables
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
- $18 constant GIFR_PCIF \ Pin Change Interrupt Flags
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Enable Mask
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&14 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&16 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&18 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&20 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&38 constant USART0__RXCAddr \ USART0, Rx Complete
-&40 constant USART1__RXCAddr \ USART1, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART1__UDREAddr \ USART1, Data register Empty
-&46 constant USART0__TXCAddr \ USART0, Tx Complete
-&48 constant USART1__TXCAddr \ USART1, Tx Complete
-&50 constant EE_RDYAddr \ EEPROM Ready
-&52 constant ANA_COMPAddr \ Analog Comparator
-&54 constant SPM_RDYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega162/device.asm b/amforth-6.5/avr8/devices/atmega162/device.asm
deleted file mode 100644
index b61f439..0000000
--- a/amforth-6.5/avr8/devices/atmega162/device.asm
+++ /dev/null
@@ -1,117 +0,0 @@
-; Partname: ATmega162
-; generated automatically, do not edit
-
-.nolist
- .include "m162def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_PORTE = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Timer/Counter3 Capture Event
-.org 14
- rcall isr ; Timer/Counter3 Compare Match A
-.org 16
- rcall isr ; Timer/Counter3 Compare Match B
-.org 18
- rcall isr ; Timer/Counter3 Overflow
-.org 20
- rcall isr ; Timer/Counter2 Compare Match
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; SPI Serial Transfer Complete
-.org 38
- rcall isr ; USART0, Rx Complete
-.org 40
- rcall isr ; USART1, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART1, Data register Empty
-.org 46
- rcall isr ; USART0, Tx Complete
-.org 48
- rcall isr ; USART1, Tx Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 28
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 28
-mcu_name:
- .dw 9
- .db "ATmega162",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega162/device.inc b/amforth-6.5/avr8/devices/atmega162/device.inc
deleted file mode 100644
index 8d0e695..0000000
--- a/amforth-6.5/avr8/devices/atmega162/device.inc
+++ /dev/null
@@ -1,924 +0,0 @@
-; Partname: ATmega162
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 68
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 66
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Mask Register
-VE_ETIMSK:
- .dw $ff06
- .db "ETIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIMSK
-XT_ETIMSK:
- .dw PFA_DOVARIABLE
-PFA_ETIMSK:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Flag register
-VE_ETIFR:
- .dw $ff05
- .db "ETIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIFR
-XT_ETIFR:
- .dw PFA_DOVARIABLE
-PFA_ETIFR:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 139
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counte3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 128
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw 41
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Highg Byte
-VE_UBRR1H:
- .dw $ff06
- .db "UBRR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1H
-XT_UBRR1H:
- .dw PFA_DOVARIABLE
-PFA_UBRR1H:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR1L:
- .dw $ff06
- .db "UBRR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1L
-XT_UBRR1L:
- .dw PFA_DOVARIABLE
-PFA_UBRR1L:
- .dw 32
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Extended MCU Control Register
-VE_EMCUCR:
- .dw $ff06
- .db "EMCUCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EMCUCR
-XT_EMCUCR:
- .dw PFA_DOVARIABLE
-PFA_EMCUCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Clock prescale register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 36
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 81
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 37
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Enable Mask
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega162/device.py b/amforth-6.5/avr8/devices/atmega162/device.py
deleted file mode 100644
index 850bee2..0000000
--- a/amforth-6.5/avr8/devices/atmega162/device.py
+++ /dev/null
@@ -1,332 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega162
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'TIMER3_CAPTAddr' : '#12', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#14', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#16', # Timer/Counter3 Compare Match B
- 'TIMER3_OVFAddr' : '#18', # Timer/Counter3 Overflow
- 'TIMER2_COMPAddr' : '#20', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#36', # SPI Serial Transfer Complete
- 'USART0_RXCAddr' : '#38', # USART0, Rx Complete
- 'USART1_RXCAddr' : '#40', # USART1, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART1_UDREAddr' : '#44', # USART1, Data register Empty
- 'USART0_TXCAddr' : '#46', # USART0, Tx Complete
- 'USART1_TXCAddr' : '#48', # USART1, Tx Complete
- 'EE_RDYAddr' : '#50', # EEPROM Ready
- 'ANA_COMPAddr' : '#52', # Analog Comparator
- 'SPM_RDYAddr' : '#54', # Store Program Memory Read
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_TOIE1': '$80', # Timer/Counter1 Overflow Interr
- 'TIMSK_OCIE1A': '$40', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$20', # Timer/Counter1 Output CompareB
- 'TIMSK_TICIE1': '$8', # Timer/Counter1 Input Capture I
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_TOV1': '$80', # Timer/Counter1 Overflow Flag
- 'TIFR_OCF1A': '$40', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$20', # Output Compare Flag 1B
- 'TIFR_ICF1': '$8', # Input Capture Flag 1
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_FOC1A': '$8', # Force Output Compare for Chann
- 'TCCR1A_FOC1B': '$4', # Force Output Compare for Chann
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Pulse Width Modulator Select B
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'ICR1' : '$44', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$47', # Timer/Counter Control Register
- 'TCCR2_FOC2': '$80', # Forde Output Compare
- 'TCCR2_WGM20': '$40', # Pulse Width Modulator Select B
- 'TCCR2_COM2': '$30', # Compare Match Output Mode
- 'TCCR2_WGM21': '$8', # Pulse Width Modulator Select B
- 'TCCR2_CS2': '$7', # Clock Select
- 'TCNT2' : '$43', # Timer/Counter Register
- 'OCR2' : '$42', # Output Compare Register
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE2': '$10', # Timer/Counter2 Output Compare
- 'TIMSK_TOIE2': '$4', # Timer/Counter2 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$10', # Output Compare Flag 2
- 'TIFR_TOV2': '$4', # Timer/Counter2 Overflow Flag
- 'ASSR' : '$46', # Asynchronous Status Register
- 'ASSR_AS2': '$8', # Asynchronous Timer 2
- 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # Timer/Counter Control Register
-
-# Module TIMER_COUNTER_3
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
- 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
- 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
- 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_ICF3': '$20', # Input Capture Flag 3
- 'ETIFR_OCF3A': '$10', # Output Compare Flag 3A
- 'ETIFR_OCF3B': '$8', # Output Compare Flag 3B
- 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
- 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_FOC3A': '$8', # Force Output Compare for Chann
- 'TCCR3A_FOC3B': '$4', # Force Output Compare for Chann
- 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B
- 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Pulse Width Modulator Select B
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCNT3' : '$88', # Timer/Counter3 Bytes
- 'OCR3A' : '$86', # Timer/Counter3 Output Compare
- 'OCR3B' : '$84', # Timer/Counte3 Output Compare R
- 'ICR3' : '$80', # Timer/Counter3 Input Capture R
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module USART0
- 'UDR0' : '$2c', # USART I/O Data Register
- 'UCSR0A' : '$2b', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$2a', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$40', # USART Control and Status Regis
- 'UCSR0C_URSEL0': '$80', # Register Select
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0H' : '$40', # USART Baud Rate Register Hight
- 'UBRR0L' : '$29', # USART Baud Rate Register Low B
-
-# Module USART1
- 'UDR' : '$23', # USART I/O Data Register
- 'UCSR1A' : '$22', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$21', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$5c', # USART Control and Status Regis
- 'UCSR1C_URSEL1': '$80', # Register Select
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1H' : '$5c', # USART Baud Rate Register Highg
- 'UBRR1L' : '$20', # USART Baud Rate Register Low B
-
-# Module SPI
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$2f', # SPI Data Register
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SRE': '$80', # External SRAM Enable
- 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
- 'MCUCR_SE': '$20', # Sleep Enable
- 'MCUCR_SM1': '$10', # Sleep Mode Select
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JDT': '$80', # JTAG Interface Disable
- 'MCUCSR_SM2': '$20', # Sleep Mode Select Bit 2
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'EMCUCR' : '$56', # Extended MCU Control Register
- 'EMCUCR_SM0': '$80', # Sleep mode Select Bit 0
- 'EMCUCR_SRL': '$70', # Wait State Sector Limit Bits
- 'EMCUCR_SRW0': '$c', # Wait State Select Bit 1 for Lo
- 'EMCUCR_SRW11': '$2', # Wait State Select Bit 1 for Up
- 'EMCUCR_ISC2': '$1', # Interrupt Sense Control 2
- 'OSCCAL' : '$24', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock prescale register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_XMBK': '$40', # External Memory Bus Keeper Ena
- 'SFIOR_XMM': '$38', # External Memory High Mask Bits
- 'SFIOR_PUD': '$4', # Pull-up Disable
- 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'SFIOR_PSR310': '$1', # Prescaler Reset Timer/Counter3
-
-# Module JTAG
- 'OCDR' : '$24', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCR' : '$57', # Store Program Memory Control R
- 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCR_RWWSRE': '$10', # Read While Write secion read e
- 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCR_PGWRT': '$4', # Page Write
- 'SPMCR_PGERS': '$2', # Page Erase
- 'SPMCR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Address Register Bytes
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter 0 Control Regist
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter 0 Register
- 'OCR0' : '$51', # Timer/Counter 0 Output Compare
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_TOIE0': '$2', # Timer/Counter0 Overflow Interr
- 'TIMSK_OCIE0': '$1', # Timer/Counter0 Output Compare
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_TOV0': '$2', # Timer/Counter0 Overflow Flag
- 'TIFR_OCF0': '$1', # Output Compare Flag 0
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module PORTE
- 'PORTE' : '$27', # Data Register, Port E
- 'DDRE' : '$26', # Data Direction Register, Port
- 'PINE' : '$25', # Input Pins, Port E
-
-# Module EXTERNAL_INTERRUPT
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'EMCUCR' : '$56', # Extended MCU Control Register
- 'EMCUCR_ISC2': '$1', # Interrupt Sense Control 2
- 'GICR' : '$5b', # General Interrupt Control Regi
- 'GICR_INT': '$c0', # External Interrupt Request 1 E
- 'GICR_INT2': '$20', # External Interrupt Request 2 E
- 'GICR_PCIE': '$18', # Pin Change Interrupt Enables
- 'GICR_IVSEL': '$2', # Interrupt Vector Select
- 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
- 'GIFR' : '$5a', # General Interrupt Flag Registe
- 'GIFR_INTF': '$c0', # External Interrupt Flags
- 'GIFR_INTF2': '$20', # External Interrupt Flag 2
- 'GIFR_PCIF': '$18', # Pin Change Interrupt Flags
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Enable Mask
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega162/words/sleep.asm b/amforth-6.5/avr8/devices/atmega162/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega162/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega163/atmega163.frt b/amforth-6.5/avr8/devices/atmega163/atmega163.frt
deleted file mode 100644
index 796fd3f..0000000
--- a/amforth-6.5/avr8/devices/atmega163/atmega163.frt
+++ /dev/null
@@ -1,121 +0,0 @@
-\ Partname: ATmega163
-\ Built using part description XML file version 207
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-25 constant ADCH \ ADC Data Register High Byte
-24 constant ADCL \ ADC Data Register Low Byte
-26 constant ADCSR \ The ADC Control and Status register
-27 constant ADMUX \ The ADC multiplexer Selection Register
-
-\ ANALOG_COMPARATOR
-28 constant ACSR \ Analog Comparator Control And Status Register
-50 constant SFIOR \ Special Function IO Register
-
-\ BOOT_LOAD
-57 constant SPMCR \ Store Program Memory Control Register
-
-\ CPU
-55 constant MCUCR \ MCU Control register
-54 constant MCUSR \ MCU Status Register
-51 constant OSCCAL \ Oscillator Calibration Value
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-3F constant EEARH \ EEPROM Address Register High Byte
-3E constant EEARL \ EEPROM Address Register Low Byte
-3C constant EECR \ EEPROM Control Register
-3D constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-5A constant GIFR \ General Interrupt Flag register
-5B constant GIMSK \ General Interrupt Mask Register
-
-\ PORTA
-3A constant DDRA \ Port A Data Direction Register
-39 constant PINA \ Port A Input Pins
-3B constant PORTA \ Port A Data Register
-
-\ PORTB
-37 constant DDRB \ Port B Data Direction Register
-36 constant PINB \ Port B Input Pins
-38 constant PORTB \ Port B Data Register
-
-\ PORTC
-34 constant DDRC \ Port C Data Direction Register
-33 constant PINC \ Port C Input Pins
-35 constant PORTC \ Port C Data Register
-
-\ PORTD
-31 constant DDRD \ Port D Data Direction Register
-30 constant PIND \ Port D Input Pins
-32 constant PORTD \ Port D Data Register
-
-\ SPI
-2D constant SPCR \ SPI Control Register
-2F constant SPDR \ SPI Data Register
-2E constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-53 constant TCCR0 \ Timer/Counter0 Control Register
-52 constant TCNT0 \ Timer Counter 0
-58 constant TIFR \ Timer/Counter Interrupt Flag register
-59 constant TIMSK \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-4F constant TCCR1A \ Timer/Counter1 Control Register A
-4E constant TCCR1B \ Timer/Counter1 Control Register B
-4D constant TCNT1H \ Timer/Counter1 High Byte
-4C constant TCNT1L \ Timer/Counter1 Low Byte
-
-\ TIMER_COUNTER_2
-42 constant ASSR \ Asynchronous Status Register
-43 constant OCR2 \ Timer/Counter2 Output Compare Register
-45 constant TCCR2 \ Timer/Counter2 Control Register
-44 constant TCNT2 \ Timer/Counter2
-
-\ TWI
-22 constant TWAR \ TWI (Slave) Address register
-20 constant TWBR \ TWI Bit Rate register
-56 constant TWCR \ TWI Control Register
-23 constant TWDR \ TWI Data register
-21 constant TWSR \ TWI Status Register
-
-\ UART
-29 constant UBRR \ UART Baud Rate Register
-40 constant UBRRHI \ UART Baud Rate Register High Byte
-2B constant UCSRA \ UART Control and Status register A
-2A constant UCSRB \ UART Control an Status register B
-2C constant UDR \ UART I/O Data Register
-
-\ WATCHDOG
-41 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt 0
-004 constant INT1Addr \ External Interrupt 1
-006 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-008 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-00A constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-00C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-00E constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-010 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-012 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-014 constant SPISTCAddr \ SPI Serial Transfer Complete
-016 constant UARTRXAddr \ UART, RX Complete
-018 constant UARTUDREAddr \ UART Data Register Empty
-01A constant UARTTXAddr \ UART, TX Complete
-01C constant ADCAddr \ ADC Conversion Complete
-01E constant EE_RDYAddr \ EEPROM Ready
-020 constant ANA_COMPAddr \ Analog Comparator
-022 constant TWIAddr \ 2-Wire Serial Interface
diff --git a/amforth-6.5/avr8/devices/atmega163/device.asm b/amforth-6.5/avr8/devices/atmega163/device.asm
deleted file mode 100644
index 2a6a80f..0000000
--- a/amforth-6.5/avr8/devices/atmega163/device.asm
+++ /dev/null
@@ -1,108 +0,0 @@
-; Partname: ATmega163
-; Built using part description XML file version 207
-; generated automatically, do not edit
-
-.nolist
- .include "m163def.inc"
-.list
-
-.equ ramstart = $60
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TWI = 0
-.set WANT_UART = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 18
-.org $002
- rcall isr ; External Interrupt 0
-.org $004
- rcall isr ; External Interrupt 1
-.org $006
- rcall isr ; Timer/Counter2 Compare Match
-.org $008
- rcall isr ; Timer/Counter2 Overflow
-.org $00A
- rcall isr ; Timer/Counter1 Capture Event
-.org $00C
- rcall isr ; Timer/Counter1 Compare Match A
-.org $00E
- rcall isr ; Timer/Counter1 Compare Match B
-.org $010
- rcall isr ; Timer/Counter1 Overflow
-.org $012
- rcall isr ; Timer/Counter0 Overflow
-.org $014
- rcall isr ; SPI Serial Transfer Complete
-.org $016
- rcall isr ; UART, RX Complete
-.org $018
- rcall isr ; UART Data Register Empty
-.org $01A
- rcall isr ; UART, TX Complete
-.org $01C
- rcall isr ; ADC Conversion Complete
-.org $01E
- rcall isr ; EEPROM Ready
-.org $020
- rcall isr ; Analog Comparator
-.org $022
- rcall isr ; 2-Wire Serial Interface
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 0 ; minimum of 0 (from XML) and 0xffff
-mcu_numints:
- .dw 18
-mcu_name:
- .dw 9
- .db "ATmega163",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega163/device.inc b/amforth-6.5/avr8/devices/atmega163/device.inc
deleted file mode 100644
index 6f6359e..0000000
--- a/amforth-6.5/avr8/devices/atmega163/device.inc
+++ /dev/null
@@ -1,861 +0,0 @@
-; Partname: ATmega163
-; Built using part description XML file version 207
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $25
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSR:
- .dw $ff05
- .db "ADCSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSR
-XT_ADCSR:
- .dw PFA_DOVARIABLE
-PFA_ADCSR:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $27
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $28
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw $50
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $51
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw $5A
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Mask Register
-VE_GIMSK:
- .dw $ff05
- .db "GIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GIMSK
-XT_GIMSK:
- .dw PFA_DOVARIABLE
-PFA_GIMSK:
- .dw $5B
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $3B
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $38
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $34
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $33
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $35
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $31
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $32
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $52
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw $58
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw $59
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $4F
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $4D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $4C
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $44
-
-.endif
-
-; ********
-.if WANT_TWI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw $22
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw $56
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw $21
-
-.endif
-
-; ********
-.if WANT_UART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; UART Baud Rate Register
-VE_UBRR:
- .dw $ff04
- .db "UBRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR
-XT_UBRR:
- .dw PFA_DOVARIABLE
-PFA_UBRR:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; UART Baud Rate Register High Byte
-VE_UBRRHI:
- .dw $ff06
- .db "UBRRHI"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRHI
-XT_UBRRHI:
- .dw PFA_DOVARIABLE
-PFA_UBRRHI:
- .dw $40
-; ( -- addr ) System Constant
-; R( -- )
-; UART Control and Status register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw $2B
-; ( -- addr ) System Constant
-; R( -- )
-; UART Control an Status register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; UART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw $2C
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $41
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega163/device.py b/amforth-6.5/avr8/devices/atmega163/device.py
deleted file mode 100644
index f344075..0000000
--- a/amforth-6.5/avr8/devices/atmega163/device.py
+++ /dev/null
@@ -1,85 +0,0 @@
-# Partname: ATmega163
-# Built using part description XML file version 207
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$25',
- 'ADCL': '$24',
- 'ADCSR': '$26',
- 'ADMUX': '$27',
- 'ACSR': '$28',
- 'SFIOR': '$50',
- 'SPMCR': '$57',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSCCAL': '$51',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'EEARH': '$3F',
- 'EEARL': '$3E',
- 'EECR': '$3C',
- 'EEDR': '$3D',
- 'GIFR': '$5A',
- 'GIMSK': '$5B',
- 'DDRA': '$3A',
- 'PINA': '$39',
- 'PORTA': '$3B',
- 'DDRB': '$37',
- 'PINB': '$36',
- 'PORTB': '$38',
- 'DDRC': '$34',
- 'PINC': '$33',
- 'PORTC': '$35',
- 'DDRD': '$31',
- 'PIND': '$30',
- 'PORTD': '$32',
- 'SPCR': '$2D',
- 'SPDR': '$2F',
- 'SPSR': '$2E',
- 'TCCR0': '$53',
- 'TCNT0': '$52',
- 'TIFR': '$58',
- 'TIMSK': '$59',
- 'ICR1H': '$47',
- 'ICR1L': '$46',
- 'OCR1AH': '$4B',
- 'OCR1AL': '$4A',
- 'OCR1BH': '$49',
- 'OCR1BL': '$48',
- 'TCCR1A': '$4F',
- 'TCCR1B': '$4E',
- 'TCNT1H': '$4D',
- 'TCNT1L': '$4C',
- 'ASSR': '$42',
- 'OCR2': '$43',
- 'TCCR2': '$45',
- 'TCNT2': '$44',
- 'TWAR': '$22',
- 'TWBR': '$20',
- 'TWCR': '$56',
- 'TWDR': '$23',
- 'TWSR': '$21',
- 'UBRR': '$29',
- 'UBRRHI': '$40',
- 'UCSRA': '$2B',
- 'UCSRB': '$2A',
- 'UDR': '$2C',
- 'WDTCR': '$41',
- 'INT0Addr': '$002',
- 'INT1Addr': '$004',
- 'TIMER2_COMPAddr': '$006',
- 'TIMER2_OVFAddr': '$008',
- 'TIMER1_CAPTAddr': '$00A',
- 'TIMER1_COMPAAddr': '$00C',
- 'TIMER1_COMPBAddr': '$00E',
- 'TIMER1_OVFAddr': '$010',
- 'TIMER0_OVFAddr': '$012',
- 'SPISTCAddr': '$014',
- 'UARTRXAddr': '$016',
- 'UARTUDREAddr': '$018',
- 'UARTTXAddr': '$01A',
- 'ADCAddr': '$01C',
- 'EE_RDYAddr': '$01E',
- 'ANA_COMPAddr': '$020',
- 'TWIAddr': '$022'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt b/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt
deleted file mode 100644
index 52631ae..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega164A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
deleted file mode 100644
index 12944ca..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,47 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status reg
- $40 constant ADCSRB_ACME \
- 7b $40 bitmask: ADCSRB.ACME \
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- 7e $80 bitmask: DIDR0.ADC7D \
- $40 constant DIDR0_ADC6D \
- 7e $40 bitmask: DIDR0.ADC6D \
- $20 constant DIDR0_ADC5D \
- 7e $20 bitmask: DIDR0.ADC5D \
- $10 constant DIDR0_ADC4D \
- 7e $10 bitmask: DIDR0.ADC4D \
- $8 constant DIDR0_ADC3D \
- 7e $8 bitmask: DIDR0.ADC3D \
- $4 constant DIDR0_ADC2D \
- 7e $4 bitmask: DIDR0.ADC2D \
- $2 constant DIDR0_ADC1D \
- 7e $2 bitmask: DIDR0.ADC1D \
- $1 constant DIDR0_ADC0D \
- 7e $1 bitmask: DIDR0.ADC0D \
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index b7caf2f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
deleted file mode 100644
index d229c7f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
deleted file mode 100644
index bbf9d5c..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
+++ /dev/null
@@ -1,91 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on reset flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
-$66 constant OSCCAL \ Oscillator Calibration Value
-$61 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- 61 $80 bitmask: CLKPR.CLKPCE \
- $f constant CLKPR_CLKPS \
- 61 $f bitmask: CLKPR.CLKPS \
-$53 constant SMCR \ Sleep Mode Control Register
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$4b constant GPIOR2 \ General Purpose IO Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- 64 $12 bitmask: PRR0.PRUSART \ Power Reduction USARTs
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
deleted file mode 100644
index b18c275..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
+++ /dev/null
@@ -1,17 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Low By
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode Bits
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Write Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Write Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 13ed947..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,35 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
- $c constant EICRA_ISC1 \ External Interrupt Sense Contr
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
- $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
-$3d constant EIMSK \ External Interrupt Mask Regist
- $7 constant EIMSK_INT \ External Interrupt Request 2 E
- 3d $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
-$3c constant EIFR \ External Interrupt Flag Regist
- $7 constant EIFR_INTF \ External Interrupt Flags
- 3c $7 bitmask: EIFR.INTF \ External Interrupt Flags
-$73 constant PCMSK3 \ Pin Change Mask Register 3
- $ff constant PCMSK3_PCINT \ Pin Change Enable Masks
- 73 $ff bitmask: PCMSK3.PCINT \ Pin Change Enable Masks
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Masks
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Masks
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Masks
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Masks
-$6b constant PCMSK0 \ Pin Change Mask Register 0
- $ff constant PCMSK0_PCINT \ Pin Change Enable Masks
- 6b $ff bitmask: PCMSK0.PCINT \ Pin Change Enable Masks
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $f bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $f bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
deleted file mode 100644
index cd82742..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Related Register
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
deleted file mode 100644
index afbaa67..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
deleted file mode 100644
index 0ec791c..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
deleted file mode 100644
index 9855199..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
deleted file mode 100644
index 9015b02..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
deleted file mode 100644
index c548ee9..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ SPI
-$4e constant SPDR0 \ SPI Data Register
-$4d constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR0.SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- 4d $40 bitmask: SPSR0.WCOL0 \ Write Collision Flag
- $1 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR0.SPI2X0 \ Double SPI Speed Bit
-$4c constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR0.SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- 4c $40 bitmask: SPCR0.SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- 4c $20 bitmask: SPCR0.DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- 4c $10 bitmask: SPCR0.MSTR0 \ Master/Slave Select
- $8 constant SPCR0_CPOL0 \ Clock polarity
- 4c $8 bitmask: SPCR0.CPOL0 \ Clock polarity
- $4 constant SPCR0_CPHA0 \ Clock Phase
- 4c $4 bitmask: SPCR0.CPHA0 \ Clock Phase
- $2 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- 4c $2 bitmask: SPCR0.SPR10 \ SPI Clock Rate Select 1
- $1 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
- 4c $1 bitmask: SPCR0.SPR00 \ SPI Clock Rate Select 0
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
deleted file mode 100644
index c2de345..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
+++ /dev/null
@@ -1,42 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0
-$45 constant TCCR0B \ Timer/Counter Control Register
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Cor
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Output Mode, Phase Cor
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Output Mode, Fast PWm
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset Timer/Counter1
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index 43e5db2..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,47 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter Interrupt Flag r
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode 1B, bits
- $3 constant TCCR1A_WGM1 \ Pulse Width Modulator Select B
- 80 $3 bitmask: TCCR1A.WGM1 \ Pulse Width Modulator Select B
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode Bits
- $7 constant TCCR1B_CS1 \ Clock Select1 bits
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select1 bits
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
deleted file mode 100644
index 2dd0720..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
+++ /dev/null
@@ -1,57 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Output Mode bits
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Output Mode bits
- $3 constant TCCR2A_WGM2 \ Waveform Genration Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Genration Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select bits
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select bits
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- b6 $20 bitmask: ASSR.AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Output Compare Register2 Updat
- b6 $8 bitmask: ASSR.OCR2AUB \ Output Compare Register2 Updat
- $4 constant ASSR_OCR2BUB \ Output Compare Register 2 Upda
- b6 $4 bitmask: ASSR.OCR2BUB \ Output Compare Register 2 Upda
- $2 constant ASSR_TCR2AUB \ Timer/Counter Control Register
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter Control Register
- $1 constant ASSR_TCR2BUB \ Timer/Counter Control Register
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter Control Register
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
deleted file mode 100644
index d30b667..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
+++ /dev/null
@@ -1,34 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \
- bd $fe bitmask: TWAMR.TWAM \
-$b8 constant TWBR \ TWI Bit Rate register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI Stop Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collition Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collition Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $3 constant TWSR_TWPS \ TWI Prescaler
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler
-$bb constant TWDR \ TWI Data register
-$ba constant TWAR \ TWI (Slave) Address register
- $fe constant TWAR_TWA \ TWI (Slave) Address register B
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address register B
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
deleted file mode 100644
index ae51362..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ USART0
-$c6 constant UDR0 \ USART I/O Data Register
-$c0 constant UCSR0A \ USART Control and Status Regis
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- c0 $10 bitmask: UCSR0A.FE0 \ Framing Error
- $8 constant UCSR0A_DOR0 \ Data overRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data overRun
- $4 constant UCSR0A_UPE0 \ Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART Control and Status Regis
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART Control and Status Regis
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode Bits
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
deleted file mode 100644
index 6bb4ff9..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ USART1
-$ce constant UDR1 \ USART I/O Data Register
-$c8 constant UCSR1A \ USART Control and Status Regis
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- c8 $10 bitmask: UCSR1A.FE1 \ Framing Error
- $8 constant UCSR1A_DOR1 \ Data overRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data overRun
- $4 constant UCSR1A_UPE1 \ Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART Control and Status Regis
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART Control and Status Regis
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode Bits
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
deleted file mode 100644
index 3dc985f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.asm b/amforth-6.5/avr8/devices/atmega164a/device.asm
deleted file mode 100644
index dc12da8..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega164A
-; generated automatically, do not edit
-
-.nolist
- .include "m164Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega164A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.inc b/amforth-6.5/avr8/devices/atmega164a/device.inc
deleted file mode 100644
index 79c054f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega164A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.py b/amforth-6.5/avr8/devices/atmega164a/device.py
deleted file mode 100644
index ea2ebc4..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/device.py
+++ /dev/null
@@ -1,387 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega164A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164p/atmega164p.frt b/amforth-6.5/avr8/devices/atmega164p/atmega164p.frt
deleted file mode 100644
index da5cdf7..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/atmega164p.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega164P
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164p/device.asm b/amforth-6.5/avr8/devices/atmega164p/device.asm
deleted file mode 100644
index 5fad484..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega164P
-; generated automatically, do not edit
-
-.nolist
- .include "m164Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega164P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164p/device.inc b/amforth-6.5/avr8/devices/atmega164p/device.inc
deleted file mode 100644
index 47d31fe..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega164P
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega164p/device.py b/amforth-6.5/avr8/devices/atmega164p/device.py
deleted file mode 100644
index 31eda10..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/device.py
+++ /dev/null
@@ -1,389 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega164P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega164p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega164p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164pa/atmega164pa.frt b/amforth-6.5/avr8/devices/atmega164pa/atmega164pa.frt
deleted file mode 100644
index f1b72e3..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/atmega164pa.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega164PA
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164pa/device.asm b/amforth-6.5/avr8/devices/atmega164pa/device.asm
deleted file mode 100644
index 95ce3e5..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega164PA
-; generated automatically, do not edit
-
-.nolist
- .include "m164PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 11
- .db "ATmega164PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164pa/device.inc b/amforth-6.5/avr8/devices/atmega164pa/device.inc
deleted file mode 100644
index 2c39861..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega164PA
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega164pa/device.py b/amforth-6.5/avr8/devices/atmega164pa/device.py
deleted file mode 100644
index 5dd57e8..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/device.py
+++ /dev/null
@@ -1,389 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega164PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega164pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164pa/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega164pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165/atmega165.frt b/amforth-6.5/avr8/devices/atmega165/atmega165.frt
deleted file mode 100644
index 25fea57..0000000
--- a/amforth-6.5/avr8/devices/atmega165/atmega165.frt
+++ /dev/null
@@ -1,160 +0,0 @@
-\ Partname: ATmega165
-\ Built using part description XML file version 126
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant ADCH \ ADC Data Register High Byte
-78 constant ADCL \ ADC Data Register Low Byte
-7A constant ADCSRA \ The ADC Control and Status register
-7B constant ADCSRB \ ADC Control and Status Register B
-7C constant ADMUX \ The ADC multiplexer Selection Register
-7E constant DIDR0 \ Digital Input Disable Register 0
-
-\ ANALOG_COMPARATOR
-50 constant ACSR \ Analog Comparator Control And Status Register
-7F constant DIDR1 \ Digital Input Disable Register 1
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control Register
-
-\ CPU
-61 constant CLKPR \ Clock Prescale Register
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-66 constant OSCCAL \ Oscillator Calibration Value
-64 constant PRR \ Power Reduction Register
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-42 constant EEARH \ EEPROM Address Register High Byte
-41 constant EEARL \ EEPROM Address Register Low Byte
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-6B constant PCMSK0 \ Pin Change Mask Register 0
-6C constant PCMSK1 \ Pin Change Mask Register 1
-
-\ JTAG
-51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Port B Data Direction Register
-23 constant PINB \ Port B Input Pins
-25 constant PORTB \ Port B Data Register
-
-\ PORTC
-27 constant DDRC \ Port C Data Direction Register
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ PORTD
-2A constant DDRD \ Port D Data Direction Register
-29 constant PIND \ Port D Input Pins
-2B constant PORTD \ Port D Data Register
-
-\ PORTE
-2D constant DDRE \ Data Direction Register, Port E
-2C constant PINE \ Input Pins, Port E
-2E constant PORTE \ Data Register, Port E
-
-\ PORTF
-30 constant DDRF \ Data Direction Register, Port F
-2F constant PINF \ Input Pins, Port F
-31 constant PORTF \ Data Register, Port F
-
-\ PORTG
-33 constant DDRG \ Port G Data Direction Register
-32 constant PING \ Port G Input Pins
-34 constant PORTG \ Port G Data Register
-
-\ SPI
-4C constant SPCR \ SPI Control Register
-4E constant SPDR \ SPI Data Register
-4D constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-43 constant GTCCR \ General Timer/Control Register
-47 constant OCR0A \ Timer/Counter0 Output Compare Register
-44 constant TCCR0A \ Timer/Counter0 Control Register
-46 constant TCNT0 \ Timer/Counter0
-35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
-88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
-8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
-8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
-80 constant TCCR1A \ Timer/Counter1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-82 constant TCCR1C \ Timer/Counter 1 Control Register C
-85 constant TCNT1H \ Timer/Counter1 High Byte
-84 constant TCNT1L \ Timer/Counter1 Low Byte
-36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
-
-\ TIMER_COUNTER_2
-B6 constant ASSR \ Asynchronous Status Register
-B3 constant OCR2A \ Timer/Counter2 Output Compare Register
-B0 constant TCCR2A \ Timer/Counter2 Control Register
-B2 constant TCNT2 \ Timer/Counter2
-37 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
-70 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
-
-\ USART0
-C5 constant UBRR0H \ USART Baud Rate Register High Byte
-C4 constant UBRR0L \ USART Baud Rate Register Low Byte
-C0 constant UCSR0A \ USART Control and Status Register A
-C1 constant UCSR0B \ USART Control and Status Register B
-C2 constant UCSR0C \ USART Control and Status Register C
-C6 constant UDR0 \ USART I/O Data Register
-
-\ USI
-B8 constant USICR \ USI Control Register
-BA constant USIDR \ USI Data Register
-B9 constant USISR \ USI Status Register
-
-\ WATCHDOG
-60 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt Request 0
-004 constant PCINT0Addr \ Pin Change Interrupt Request 0
-006 constant PCINT1Addr \ Pin Change Interrupt Request 1
-008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-010 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-018 constant SPI_STCAddr \ SPI Serial Transfer Complete
-01A constant USART0_RXAddr \ USART0, Rx Complete
-01C constant USART0_UDREAddr \ USART0 Data register Empty
-01E constant USART0_TXAddr \ USART0, Tx Complete
-020 constant USI_STARTAddr \ USI Start Condition
-022 constant USI_OVERFLOWAddr \ USI Overflow
-024 constant ANALOG_COMPAddr \ Analog Comparator
-026 constant ADCAddr \ ADC Conversion Complete
-028 constant EE_READYAddr \ EEPROM Ready
-02A constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165/device.asm b/amforth-6.5/avr8/devices/atmega165/device.asm
deleted file mode 100644
index 87aad59..0000000
--- a/amforth-6.5/avr8/devices/atmega165/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega165
-; Built using part description XML file version 126
-; generated automatically, do not edit
-
-.nolist
- .include "m165def.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_JTAG = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_USART0 = 0
-.set WANT_USI = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 22
-.org $002
- rcall isr ; External Interrupt Request 0
-.org $004
- rcall isr ; Pin Change Interrupt Request 0
-.org $006
- rcall isr ; Pin Change Interrupt Request 1
-.org $008
- rcall isr ; Timer/Counter2 Compare Match
-.org $00A
- rcall isr ; Timer/Counter2 Overflow
-.org $00C
- rcall isr ; Timer/Counter1 Capture Event
-.org $00E
- rcall isr ; Timer/Counter1 Compare Match A
-.org $010
- rcall isr ; Timer/Counter Compare Match B
-.org $012
- rcall isr ; Timer/Counter1 Overflow
-.org $014
- rcall isr ; Timer/Counter0 Compare Match
-.org $016
- rcall isr ; Timer/Counter0 Overflow
-.org $018
- rcall isr ; SPI Serial Transfer Complete
-.org $01A
- rcall isr ; USART0, Rx Complete
-.org $01C
- rcall isr ; USART0 Data register Empty
-.org $01E
- rcall isr ; USART0, Tx Complete
-.org $020
- rcall isr ; USI Start Condition
-.org $022
- rcall isr ; USI Overflow
-.org $024
- rcall isr ; Analog Comparator
-.org $026
- rcall isr ; ADC Conversion Complete
-.org $028
- rcall isr ; EEPROM Ready
-.org $02A
- rcall isr ; Store Program Memory Read
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 7168 ; minimum of 0x1C00 (from XML) and 0xffff
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 9
- .db "ATmega165",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165/device.inc b/amforth-6.5/avr8/devices/atmega165/device.inc
deleted file mode 100644
index 739f874..0000000
--- a/amforth-6.5/avr8/devices/atmega165/device.inc
+++ /dev/null
@@ -1,1209 +0,0 @@
-; Partname: ATmega165
-; Built using part description XML file version 126
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw $7B
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $7C
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $50
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw $7F
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw $6B
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw $6C
-
-.endif
-
-; ********
-.if WANT_JTAG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw $51
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $27
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_PORTF == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw $31
-
-.endif
-
-; ********
-.if WANT_PORTG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw $33
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw $32
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw $34
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4C
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4D
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $86
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $8B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $8A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw $82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $B6
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw $B3
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw $B0
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $B2
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw $70
-
-.endif
-
-; ********
-.if WANT_USART0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw $C5
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw $C4
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw $C0
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw $C1
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw $C2
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw $C6
-
-.endif
-
-; ********
-.if WANT_USI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw $B8
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw $BA
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw $B9
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega165/device.py b/amforth-6.5/avr8/devices/atmega165/device.py
deleted file mode 100644
index bd637ca..0000000
--- a/amforth-6.5/avr8/devices/atmega165/device.py
+++ /dev/null
@@ -1,319 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega165A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega165a/atmega165a.frt b/amforth-6.5/avr8/devices/atmega165a/atmega165a.frt
deleted file mode 100644
index 8ed9a41..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/atmega165a.frt
+++ /dev/null
@@ -1,280 +0,0 @@
-\ Partname: ATmega165A
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165a/device.asm b/amforth-6.5/avr8/devices/atmega165a/device.asm
deleted file mode 100644
index f060f41..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega165A
-; generated automatically, do not edit
-
-.nolist
- .include "m165Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 10
- .db "ATmega165A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165a/device.inc b/amforth-6.5/avr8/devices/atmega165a/device.inc
deleted file mode 100644
index 8fb0e73..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega165A
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega165a/device.py b/amforth-6.5/avr8/devices/atmega165a/device.py
deleted file mode 100644
index e5790dd..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/device.py
+++ /dev/null
@@ -1,258 +0,0 @@
-# Partname: ATmega165A
-# generated automatically, do not edit
-MCUREGS = {
- 'TCCR0A': '&68',
- 'TCCR0A_FOC0A': '$80',
- 'TCCR0A_WGM00': '$40',
- 'TCCR0A_COM0A': '$30',
- 'TCCR0A_WGM01': '$08',
- 'TCCR0A_CS0': '$07',
- 'TCNT0': '&70',
- 'OCR0A': '&71',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSR310': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'ICR1': '&134',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'TCCR2A': '&176',
- 'TCCR2A_FOC2A': '$80',
- 'TCCR2A_WGM20': '$40',
- 'TCCR2A_COM2A': '$30',
- 'TCCR2A_WGM21': '$08',
- 'TCCR2A_CS2': '$07',
- 'TCNT2': '&178',
- 'OCR2A': '&179',
- 'TIMSK2': '&112',
- 'TIMSK2_OCIE2A': '$02',
- 'TIMSK2_TOIE2': '$01',
- 'TIFR2': '&55',
- 'TIFR2_OCF2A': '$02',
- 'TIFR2_TOV2': '$01',
- 'ASSR': '&182',
- 'ASSR_EXCLK': '$10',
- 'ASSR_AS2': '$08',
- 'ASSR_TCN2UB': '$04',
- 'ASSR_OCR2UB': '$02',
- 'ASSR_TCR2UB': '$01',
- 'WDTCR': '&96',
- 'WDTCR_WDCE': '$10',
- 'WDTCR_WDE': '$08',
- 'WDTCR_WDP': '$07',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPDR': '&78',
- 'PORTA': '&34',
- 'DDRA': '&33',
- 'PINA': '&32',
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTC': '&40',
- 'DDRC': '&39',
- 'PINC': '&38',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'ADCSRB': '&123',
- 'ADCSRB_ACME': '$40',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTE': '&46',
- 'DDRE': '&45',
- 'PINE': '&44',
- 'PORTF': '&49',
- 'DDRF': '&48',
- 'PINF': '&47',
- 'PORTG': '&52',
- 'DDRG': '&51',
- 'PING': '&50',
- 'OCDR': '&81',
- 'MCUCR': '&85',
- 'MCUCR_JTD': '$80',
- 'MCUSR': '&84',
- 'MCUSR_JTRF': '$10',
- 'USIDR': '&186',
- 'USISR': '&185',
- 'USISR_USISIF': '$80',
- 'USISR_USIOIF': '$40',
- 'USISR_USIPF': '$20',
- 'USISR_USIDC': '$10',
- 'USISR_USICNT': '$0F',
- 'USICR': '&184',
- 'USICR_USISIE': '$80',
- 'USICR_USIOIE': '$40',
- 'USICR_USIWM': '$30',
- 'USICR_USICS': '$0C',
- 'USICR_USICLK': '$02',
- 'USICR_USITC': '$01',
- 'ADMUX': '&124',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$1F',
- 'ADCSRA': '&122',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADC': '&120',
- 'DIDR0': '&126',
- 'DIDR0_ADC7D': '$80',
- 'DIDR0_ADC6D': '$40',
- 'DIDR0_ADC5D': '$20',
- 'DIDR0_ADC4D': '$10',
- 'DIDR0_ADC3D': '$08',
- 'DIDR0_ADC2D': '$04',
- 'DIDR0_ADC1D': '$02',
- 'DIDR0_ADC0D': '$01',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SPMEN': '$01',
- 'UDR0': '&198',
- 'UCSR0A': '&192',
- 'UCSR0A_RXC0': '$80',
- 'UCSR0A_TXC0': '$40',
- 'UCSR0A_UDRE0': '$20',
- 'UCSR0A_FE0': '$10',
- 'UCSR0A_DOR0': '$08',
- 'UCSR0A_UPE0': '$04',
- 'UCSR0A_U2X0': '$02',
- 'UCSR0A_MPCM0': '$01',
- 'UCSR0B': '&193',
- 'UCSR0B_RXCIE0': '$80',
- 'UCSR0B_TXCIE0': '$40',
- 'UCSR0B_UDRIE0': '$20',
- 'UCSR0B_RXEN0': '$10',
- 'UCSR0B_TXEN0': '$08',
- 'UCSR0B_UCSZ02': '$04',
- 'UCSR0B_RXB80': '$02',
- 'UCSR0B_TXB80': '$01',
- 'UCSR0C': '&194',
- 'UCSR0C_UMSEL0': '$40',
- 'UCSR0C_UPM0': '$30',
- 'UCSR0C_USBS0': '$08',
- 'UCSR0C_UCSZ0': '$06',
- 'UCSR0C_UCPOL0': '$01',
- 'UBRR0': '&196',
- 'EICRA': '&105',
- 'EICRA_ISC01': '$02',
- 'EICRA_ISC00': '$01',
- 'EIMSK': '&61',
- 'EIMSK_PCIE': '$30',
- 'EIMSK_INT0': '$01',
- 'EIFR': '&60',
- 'EIFR_PCIF': '$30',
- 'EIFR_INTF0': '$01',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$FF',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'PRR': '&100',
- 'PRR_PRTIM1': '$08',
- 'PRR_PRSPI': '$04',
- 'PRR_PRUSART0': '$02',
- 'PRR_PRADC': '$01',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'GPIOR2': '&75',
- 'GPIOR1': '&74',
- 'GPIOR0': '&62',
- 'INT0Addr': '2',
- 'PCINT0Addr': '4',
- 'PCINT1Addr': '6',
- 'TIMER2_COMPAddr': '8',
- 'TIMER2_OVFAddr': '10',
- 'TIMER1_CAPTAddr': '12',
- 'TIMER1_COMPAAddr': '14',
- 'TIMER1_COMPBAddr': '16',
- 'TIMER1_OVFAddr': '18',
- 'TIMER0_COMPAddr': '20',
- 'TIMER0_OVFAddr': '22',
- 'SPI__STCAddr': '24',
- 'USART0__RXAddr': '26',
- 'USART0__UDREAddr': '28',
- 'USART0__TXAddr': '30',
- 'USI_STARTAddr': '32',
- 'USI_OVERFLOWAddr': '34',
- 'ANALOG_COMPAddr': '36',
- 'ADCAddr': '38',
- 'EE_READYAddr': '40',
- 'SPM_READYAddr': '42'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega165a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega165a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega165a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega165a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega165a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165p/atmega165p.frt b/amforth-6.5/avr8/devices/atmega165p/atmega165p.frt
deleted file mode 100644
index 914aac0..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/atmega165p.frt
+++ /dev/null
@@ -1,280 +0,0 @@
-\ Partname: ATmega165P
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $C0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $C0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165p/device.asm b/amforth-6.5/avr8/devices/atmega165p/device.asm
deleted file mode 100644
index ee78665..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega165P
-; generated automatically, do not edit
-
-.nolist
- .include "m165Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 10
- .db "ATmega165P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165p/device.inc b/amforth-6.5/avr8/devices/atmega165p/device.inc
deleted file mode 100644
index 9760615..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega165P
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega165p/device.py b/amforth-6.5/avr8/devices/atmega165p/device.py
deleted file mode 100644
index 1b63682..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/device.py
+++ /dev/null
@@ -1,319 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega165P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$c0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$c0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega165p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega165p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega165p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega165p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega165p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165pa/atmega165pa.frt b/amforth-6.5/avr8/devices/atmega165pa/atmega165pa.frt
deleted file mode 100644
index 4a85d66..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/atmega165pa.frt
+++ /dev/null
@@ -1,280 +0,0 @@
-\ Partname: ATmega165PA
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165pa/device.asm b/amforth-6.5/avr8/devices/atmega165pa/device.asm
deleted file mode 100644
index 3d624b8..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega165PA
-; generated automatically, do not edit
-
-.nolist
- .include "m165PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 11
- .db "ATmega165PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165pa/device.inc b/amforth-6.5/avr8/devices/atmega165pa/device.inc
deleted file mode 100644
index 311d06f..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega165PA
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega165pa/device.py b/amforth-6.5/avr8/devices/atmega165pa/device.py
deleted file mode 100644
index f970f06..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/device.py
+++ /dev/null
@@ -1,321 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega165PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega165pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega165pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega165pa/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega165pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega165pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/atmega168.frt b/amforth-6.5/avr8/devices/atmega168/atmega168.frt
deleted file mode 100644
index df0b666..0000000
--- a/amforth-6.5/avr8/devices/atmega168/atmega168.frt
+++ /dev/null
@@ -1,297 +0,0 @@
-\ Partname: ATmega168
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \
- $0E constant SMCR_SM \
- $01 constant SMCR_SE \
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168/device.asm b/amforth-6.5/avr8/devices/atmega168/device.asm
deleted file mode 100644
index 74bda58..0000000
--- a/amforth-6.5/avr8/devices/atmega168/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega168
-; generated automatically, do not edit
-
-.nolist
- .include "m168def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 9
- .db "ATmega168",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168/device.inc b/amforth-6.5/avr8/devices/atmega168/device.inc
deleted file mode 100644
index 47d5dcd..0000000
--- a/amforth-6.5/avr8/devices/atmega168/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega168
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega168/device.py b/amforth-6.5/avr8/devices/atmega168/device.py
deleted file mode 100644
index f2179e8..0000000
--- a/amforth-6.5/avr8/devices/atmega168/device.py
+++ /dev/null
@@ -1,322 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega168
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', #
- 'SMCR_SM': '$e', #
- 'SMCR_SE': '$1', #
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega168/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168a/atmega168a.frt b/amforth-6.5/avr8/devices/atmega168a/atmega168a.frt
deleted file mode 100644
index 6ec7083..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/atmega168a.frt
+++ /dev/null
@@ -1,297 +0,0 @@
-\ Partname: ATmega168A
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168a/device.asm b/amforth-6.5/avr8/devices/atmega168a/device.asm
deleted file mode 100644
index ffb34ff..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega168A
-; generated automatically, do not edit
-
-.nolist
- .include "m168Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 10
- .db "ATmega168A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168a/device.inc b/amforth-6.5/avr8/devices/atmega168a/device.inc
deleted file mode 100644
index d497913..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega168A
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega168a/device.py b/amforth-6.5/avr8/devices/atmega168a/device.py
deleted file mode 100644
index 7bb795d..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/device.py
+++ /dev/null
@@ -1,322 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega168A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select Bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega168a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168a/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega168a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168p/atmega168p.frt b/amforth-6.5/avr8/devices/atmega168p/atmega168p.frt
deleted file mode 100644
index 5e3d702..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/atmega168p.frt
+++ /dev/null
@@ -1,299 +0,0 @@
-\ Partname: ATmega168P
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $40 constant MCUCR_BODS \ BOD Sleep
- $20 constant MCUCR_BODSE \ BOD Sleep Enable
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168p/device.asm b/amforth-6.5/avr8/devices/atmega168p/device.asm
deleted file mode 100644
index 81583e4..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega168P
-; generated automatically, do not edit
-
-.nolist
- .include "m168Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 10
- .db "ATmega168P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168p/device.inc b/amforth-6.5/avr8/devices/atmega168p/device.inc
deleted file mode 100644
index e544ad4..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega168P
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega168p/device.py b/amforth-6.5/avr8/devices/atmega168p/device.py
deleted file mode 100644
index 50c5f5b..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/device.py
+++ /dev/null
@@ -1,324 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega168P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select Bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega168p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega168p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168pa/atmega168pa.frt b/amforth-6.5/avr8/devices/atmega168pa/atmega168pa.frt
deleted file mode 100644
index 120d837..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/atmega168pa.frt
+++ /dev/null
@@ -1,299 +0,0 @@
-\ Partname: ATmega168PA
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $40 constant MCUCR_BODS \ BOD Sleep
- $20 constant MCUCR_BODSE \ BOD Sleep Enable
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168pa/device.asm b/amforth-6.5/avr8/devices/atmega168pa/device.asm
deleted file mode 100644
index 2b9e346..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega168PA
-; generated automatically, do not edit
-
-.nolist
- .include "m168PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 11
- .db "ATmega168PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168pa/device.inc b/amforth-6.5/avr8/devices/atmega168pa/device.inc
deleted file mode 100644
index dc2ad5b..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega168PA
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega168pa/device.py b/amforth-6.5/avr8/devices/atmega168pa/device.py
deleted file mode 100644
index 8001e5c..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/device.py
+++ /dev/null
@@ -1,324 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega168PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select Bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega168pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168pa/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega168pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169/atmega169.frt b/amforth-6.5/avr8/devices/atmega169/atmega169.frt
deleted file mode 100644
index 97e7d87..0000000
--- a/amforth-6.5/avr8/devices/atmega169/atmega169.frt
+++ /dev/null
@@ -1,183 +0,0 @@
-\ Partname: ATmega169
-\ Built using part description XML file version 300
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant ADCH \ ADC Data Register High Byte
-78 constant ADCL \ ADC Data Register Low Byte
-7A constant ADCSRA \ The ADC Control and Status register
-7B constant ADCSRB \ ADC Control and Status Register B
-7C constant ADMUX \ The ADC multiplexer Selection Register
-7E constant DIDR0 \ Digital Input Disable Register 0
-
-\ ANALOG_COMPARATOR
-50 constant ACSR \ Analog Comparator Control And Status Register
-7F constant DIDR1 \ Digital Input Disable Register 1
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control Register
-
-\ CPU
-61 constant CLKPR \ Clock Prescale Register
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-66 constant OSCCAL \ Oscillator Calibration Value
-64 constant PRR \ Power Reduction Register
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-42 constant EEARH \ EEPROM Address Register High Byte
-41 constant EEARL \ EEPROM Address Register Low Byte
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-6B constant PCMSK0 \ Pin Change Mask Register 0
-6C constant PCMSK1 \ Pin Change Mask Register 1
-
-\ JTAG
-51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-
-\ LCD
-E7 constant LCDCCR \ LCD Contrast Control Register
-E4 constant LCDCRA \ LCD Control Register A
-E5 constant LCDCRB \ LCD Control and Status Register B
-EC constant LCDDR0 \ LCD Data Register 0
-ED constant LCDDR1 \ LCD Data Register 1
-F6 constant LCDDR10 \ LCD Data Register 10
-F7 constant LCDDR11 \ LCD Data Register 11
-F8 constant LCDDR12 \ LCD Data Register 12
-F9 constant LCDDR13 \ LCD Data Register 13
-FB constant LCDDR15 \ LCD Data Register 15
-FC constant LCDDR16 \ LCD Data Register 16
-FD constant LCDDR17 \ LCD Data Register 17
-FE constant LCDDR18 \ LCD Data Register 18
-EE constant LCDDR2 \ LCD Data Register 2
-EF constant LCDDR3 \ LCD Data Register 3
-F1 constant LCDDR5 \ LCD Data Register 5
-F2 constant LCDDR6 \ LCD Data Register 6
-F3 constant LCDDR7 \ LCD Data Register 7
-F4 constant LCDDR8 \ LCD Data Register 8
-E6 constant LCDFRR \ LCD Frame Rate Register
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Port B Data Direction Register
-23 constant PINB \ Port B Input Pins
-25 constant PORTB \ Port B Data Register
-
-\ PORTC
-27 constant DDRC \ Port C Data Direction Register
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ PORTD
-2A constant DDRD \ Port D Data Direction Register
-29 constant PIND \ Port D Input Pins
-2B constant PORTD \ Port D Data Register
-
-\ PORTE
-2D constant DDRE \ Data Direction Register, Port E
-2C constant PINE \ Input Pins, Port E
-2E constant PORTE \ Data Register, Port E
-
-\ PORTF
-30 constant DDRF \ Data Direction Register, Port F
-2F constant PINF \ Input Pins, Port F
-31 constant PORTF \ Data Register, Port F
-
-\ PORTG
-33 constant DDRG \ Port G Data Direction Register
-32 constant PING \ Port G Input Pins
-34 constant PORTG \ Port G Data Register
-
-\ SPI
-4C constant SPCR \ SPI Control Register
-4E constant SPDR \ SPI Data Register
-4D constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-43 constant GTCCR \ General Timer/Control Register
-47 constant OCR0A \ Timer/Counter0 Output Compare Register
-44 constant TCCR0A \ Timer/Counter0 Control Register
-46 constant TCNT0 \ Timer/Counter0
-35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
-88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
-8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
-8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
-80 constant TCCR1A \ Timer/Counter1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-82 constant TCCR1C \ Timer/Counter 1 Control Register C
-85 constant TCNT1H \ Timer/Counter1 High Byte
-84 constant TCNT1L \ Timer/Counter1 Low Byte
-36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
-
-\ TIMER_COUNTER_2
-B6 constant ASSR \ Asynchronous Status Register
-B3 constant OCR2A \ Timer/Counter2 Output Compare Register
-B0 constant TCCR2A \ Timer/Counter2 Control Register
-B2 constant TCNT2 \ Timer/Counter2
-37 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
-70 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
-
-\ USART0
-C5 constant UBRR0H \ USART Baud Rate Register High Byte
-C4 constant UBRR0L \ USART Baud Rate Register Low Byte
-C0 constant UCSR0A \ USART Control and Status Register A
-C1 constant UCSR0B \ USART Control and Status Register B
-C2 constant UCSR0C \ USART Control and Status Register C
-C6 constant UDR0 \ USART I/O Data Register
-
-\ USI
-B8 constant USICR \ USI Control Register
-BA constant USIDR \ USI Data Register
-B9 constant USISR \ USI Status Register
-
-\ WATCHDOG
-60 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt Request 0
-004 constant PCINT0Addr \ Pin Change Interrupt Request 0
-006 constant PCINT1Addr \ Pin Change Interrupt Request 1
-008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-010 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-018 constant SPI_STCAddr \ SPI Serial Transfer Complete
-01A constant USART0_RXAddr \ USART0, Rx Complete
-01C constant USART0_UDREAddr \ USART0 Data register Empty
-01E constant USART0_TXAddr \ USART0, Tx Complete
-020 constant USI_STARTAddr \ USI Start Condition
-022 constant USI_OVERFLOWAddr \ USI Overflow
-024 constant ANALOG_COMPAddr \ Analog Comparator
-026 constant ADCAddr \ ADC Conversion Complete
-028 constant EE_READYAddr \ EEPROM Ready
-02A constant SPM_READYAddr \ Store Program Memory Read
-02C constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169/device.asm b/amforth-6.5/avr8/devices/atmega169/device.asm
deleted file mode 100644
index e80445b..0000000
--- a/amforth-6.5/avr8/devices/atmega169/device.asm
+++ /dev/null
@@ -1,123 +0,0 @@
-; Partname: ATmega169
-; Built using part description XML file version 300
-; generated automatically, do not edit
-
-.nolist
- .include "m169def.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_USART0 = 0
-.set WANT_USI = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 23
-.org $002
- rcall isr ; External Interrupt Request 0
-.org $004
- rcall isr ; Pin Change Interrupt Request 0
-.org $006
- rcall isr ; Pin Change Interrupt Request 1
-.org $008
- rcall isr ; Timer/Counter2 Compare Match
-.org $00A
- rcall isr ; Timer/Counter2 Overflow
-.org $00C
- rcall isr ; Timer/Counter1 Capture Event
-.org $00E
- rcall isr ; Timer/Counter1 Compare Match A
-.org $010
- rcall isr ; Timer/Counter Compare Match B
-.org $012
- rcall isr ; Timer/Counter1 Overflow
-.org $014
- rcall isr ; Timer/Counter0 Compare Match
-.org $016
- rcall isr ; Timer/Counter0 Overflow
-.org $018
- rcall isr ; SPI Serial Transfer Complete
-.org $01A
- rcall isr ; USART0, Rx Complete
-.org $01C
- rcall isr ; USART0 Data register Empty
-.org $01E
- rcall isr ; USART0, Tx Complete
-.org $020
- rcall isr ; USI Start Condition
-.org $022
- rcall isr ; USI Overflow
-.org $024
- rcall isr ; Analog Comparator
-.org $026
- rcall isr ; ADC Conversion Complete
-.org $028
- rcall isr ; EEPROM Ready
-.org $02A
- rcall isr ; Store Program Memory Read
-.org $02C
- rcall isr ; LCD Start of Frame
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 7168 ; minimum of 0x1C00 (from XML) and 0xffff
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 9
- .db "ATmega169",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169/device.inc b/amforth-6.5/avr8/devices/atmega169/device.inc
deleted file mode 100644
index 84d4954..0000000
--- a/amforth-6.5/avr8/devices/atmega169/device.inc
+++ /dev/null
@@ -1,1455 +0,0 @@
-; Partname: ATmega169
-; Built using part description XML file version 300
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw $7B
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $7C
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $50
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw $7F
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw $6B
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw $6C
-
-.endif
-
-; ********
-.if WANT_JTAG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw $51
-
-.endif
-
-; ********
-.if WANT_LCD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw $E7
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw $E4
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw $E5
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw $EC
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw $ED
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw $F6
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw $F7
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw $F8
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw $F9
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw $FB
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw $FC
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw $FD
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw $FE
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw $EE
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw $EF
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw $F1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw $F4
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw $E6
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $27
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_PORTF == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw $31
-
-.endif
-
-; ********
-.if WANT_PORTG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw $33
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw $32
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw $34
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4C
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4D
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $86
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $8B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $8A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw $82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $B6
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw $B3
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw $B0
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $B2
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw $70
-
-.endif
-
-; ********
-.if WANT_USART0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw $C5
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw $C4
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw $C0
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw $C1
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw $C2
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw $C6
-
-.endif
-
-; ********
-.if WANT_USI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw $B8
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw $BA
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw $B9
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega169/device.py b/amforth-6.5/avr8/devices/atmega169/device.py
deleted file mode 100644
index 4dc59ba..0000000
--- a/amforth-6.5/avr8/devices/atmega169/device.py
+++ /dev/null
@@ -1,137 +0,0 @@
-# Partname: ATmega169
-# Built using part description XML file version 300
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$79',
- 'ADCL': '$78',
- 'ADCSRA': '$7A',
- 'ADCSRB': '$7B',
- 'ADMUX': '$7C',
- 'DIDR0': '$7E',
- 'ACSR': '$50',
- 'DIDR1': '$7F',
- 'SPMCSR': '$57',
- 'CLKPR': '$61',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$4A',
- 'GPIOR2': '$4B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSCCAL': '$66',
- 'PRR': '$64',
- 'SMCR': '$53',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'EEARH': '$42',
- 'EEARL': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EICRA': '$69',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'PCMSK0': '$6B',
- 'PCMSK1': '$6C',
- 'OCDR': '$51',
- 'LCDCCR': '$E7',
- 'LCDCRA': '$E4',
- 'LCDCRB': '$E5',
- 'LCDDR0': '$EC',
- 'LCDDR1': '$ED',
- 'LCDDR10': '$F6',
- 'LCDDR11': '$F7',
- 'LCDDR12': '$F8',
- 'LCDDR13': '$F9',
- 'LCDDR15': '$FB',
- 'LCDDR16': '$FC',
- 'LCDDR17': '$FD',
- 'LCDDR18': '$FE',
- 'LCDDR2': '$EE',
- 'LCDDR3': '$EF',
- 'LCDDR5': '$F1',
- 'LCDDR6': '$F2',
- 'LCDDR7': '$F3',
- 'LCDDR8': '$F4',
- 'LCDFRR': '$E6',
- 'DDRA': '$21',
- 'PINA': '$20',
- 'PORTA': '$22',
- 'DDRB': '$24',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'DDRC': '$27',
- 'PINC': '$26',
- 'PORTC': '$28',
- 'DDRD': '$2A',
- 'PIND': '$29',
- 'PORTD': '$2B',
- 'DDRE': '$2D',
- 'PINE': '$2C',
- 'PORTE': '$2E',
- 'DDRF': '$30',
- 'PINF': '$2F',
- 'PORTF': '$31',
- 'DDRG': '$33',
- 'PING': '$32',
- 'PORTG': '$34',
- 'SPCR': '$4C',
- 'SPDR': '$4E',
- 'SPSR': '$4D',
- 'GTCCR': '$43',
- 'OCR0A': '$47',
- 'TCCR0A': '$44',
- 'TCNT0': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'ICR1H': '$87',
- 'ICR1L': '$86',
- 'OCR1AH': '$89',
- 'OCR1AL': '$88',
- 'OCR1BH': '$8B',
- 'OCR1BL': '$8A',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCCR1C': '$82',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'ASSR': '$B6',
- 'OCR2A': '$B3',
- 'TCCR2A': '$B0',
- 'TCNT2': '$B2',
- 'TIFR2': '$37',
- 'TIMSK2': '$70',
- 'UBRR0H': '$C5',
- 'UBRR0L': '$C4',
- 'UCSR0A': '$C0',
- 'UCSR0B': '$C1',
- 'UCSR0C': '$C2',
- 'UDR0': '$C6',
- 'USICR': '$B8',
- 'USIDR': '$BA',
- 'USISR': '$B9',
- 'WDTCR': '$60',
- 'INT0Addr': '$002',
- 'PCINT0Addr': '$004',
- 'PCINT1Addr': '$006',
- 'TIMER2_COMPAddr': '$008',
- 'TIMER2_OVFAddr': '$00A',
- 'TIMER1_CAPTAddr': '$00C',
- 'TIMER1_COMPAAddr': '$00E',
- 'TIMER1_COMPBAddr': '$010',
- 'TIMER1_OVFAddr': '$012',
- 'TIMER0_COMPAddr': '$014',
- 'TIMER0_OVFAddr': '$016',
- 'SPI_STCAddr': '$018',
- 'USART0_RXAddr': '$01A',
- 'USART0_UDREAddr': '$01C',
- 'USART0_TXAddr': '$01E',
- 'USI_STARTAddr': '$020',
- 'USI_OVERFLOWAddr': '$022',
- 'ANALOG_COMPAddr': '$024',
- 'ADCAddr': '$026',
- 'EE_READYAddr': '$028',
- 'SPM_READYAddr': '$02A',
- 'LCDAddr': '$02C'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega169a/atmega169a.frt b/amforth-6.5/avr8/devices/atmega169a/atmega169a.frt
deleted file mode 100644
index 3cde548..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/atmega169a.frt
+++ /dev/null
@@ -1,319 +0,0 @@
-\ Partname: ATmega169A
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ LCD
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $07 constant LCDCRB_LCDPM \ LCD Port Masks
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \ LCD Display Configuration Bits
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169a/device.asm b/amforth-6.5/avr8/devices/atmega169a/device.asm
deleted file mode 100644
index 6723bf7..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega169A
-; generated automatically, do not edit
-
-.nolist
- .include "m169Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 10
- .db "ATmega169A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169a/device.inc b/amforth-6.5/avr8/devices/atmega169a/device.inc
deleted file mode 100644
index 6e926e1..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega169A
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega169a/device.py b/amforth-6.5/avr8/devices/atmega169a/device.py
deleted file mode 100644
index ad1432d..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/device.py
+++ /dev/null
@@ -1,359 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega169A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$7', # LCD Port Masks
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', # LCD Display Configuration Bits
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega169a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega169a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega169a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega169a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega169a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169p/atmega169p.frt b/amforth-6.5/avr8/devices/atmega169p/atmega169p.frt
deleted file mode 100644
index e4cc0e8..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/atmega169p.frt
+++ /dev/null
@@ -1,319 +0,0 @@
-\ Partname: ATmega169P
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ LCD
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $07 constant LCDCRB_LCDPM \ LCD Port Masks
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \ LCD Display Configuration Bits
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $C0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $C0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169p/device.asm b/amforth-6.5/avr8/devices/atmega169p/device.asm
deleted file mode 100644
index cbd28a2..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega169P
-; generated automatically, do not edit
-
-.nolist
- .include "m169Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_PORTG = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 10
- .db "ATmega169P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169p/device.inc b/amforth-6.5/avr8/devices/atmega169p/device.inc
deleted file mode 100644
index f4b9135..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega169P
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega169p/device.py b/amforth-6.5/avr8/devices/atmega169p/device.py
deleted file mode 100644
index 71d9500..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/device.py
+++ /dev/null
@@ -1,359 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega169P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$7', # LCD Port Masks
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', # LCD Display Configuration Bits
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$c0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$c0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega169p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega169p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega169p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega169p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega169p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169pa/atmega169pa.frt b/amforth-6.5/avr8/devices/atmega169pa/atmega169pa.frt
deleted file mode 100644
index a4be875..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/atmega169pa.frt
+++ /dev/null
@@ -1,319 +0,0 @@
-\ Partname: ATmega169PA
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ LCD
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $07 constant LCDCRB_LCDPM \ LCD Port Masks
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \ LCD Display Configuration Bits
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169pa/device.asm b/amforth-6.5/avr8/devices/atmega169pa/device.asm
deleted file mode 100644
index af233d4..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega169PA
-; generated automatically, do not edit
-
-.nolist
- .include "m169PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 11
- .db "ATmega169PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169pa/device.inc b/amforth-6.5/avr8/devices/atmega169pa/device.inc
deleted file mode 100644
index 6c34070..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega169PA
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega169pa/device.py b/amforth-6.5/avr8/devices/atmega169pa/device.py
deleted file mode 100644
index 728dd6f..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/device.py
+++ /dev/null
@@ -1,361 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega169PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$7', # LCD Port Masks
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', # LCD Display Configuration Bits
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega169pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega169pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega169pa/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega169pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega169pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16a/atmega16a.frt b/amforth-6.5/avr8/devices/atmega16a/atmega16a.frt
deleted file mode 100644
index 2552e5b..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/atmega16a.frt
+++ /dev/null
@@ -1,221 +0,0 @@
-\ Partname: ATmega16A
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&92 constant OCR0 \ Output Compare Register
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-&80 constant SFIOR \ Special Function IO Register
- $01 constant SFIOR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
-&85 constant MCUCR \ General Interrupt Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&81 constant OSCCAL \ Oscillator Calibration Value
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ ANALOG_COMPARATOR
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDTOE \ RW
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&8 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&14 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&16 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&18 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&20 constant SPI_STCAddr \ Serial Transfer Complete
-&22 constant USART_RXCAddr \ USART, Rx Complete
-&24 constant USART_UDREAddr \ USART Data Register Empty
-&26 constant USART_TXCAddr \ USART, Tx Complete
-&28 constant ADCAddr \ ADC Conversion Complete
-&30 constant EE_RDYAddr \ EEPROM Ready
-&32 constant ANA_COMPAddr \ Analog Comparator
-&34 constant TWIAddr \ 2-wire Serial Interface
-&36 constant INT2Addr \ External Interrupt Request 2
-&38 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega16a/device.asm b/amforth-6.5/avr8/devices/atmega16a/device.asm
deleted file mode 100644
index 1a01ca4..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega16A
-; generated automatically, do not edit
-
-.nolist
- .include "m16Adef.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_SPI = 0
-.set WANT_USART = 0
-.set WANT_TWI = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_WATCHDOG = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Timer/Counter2 Compare Match
-.org 8
- rcall isr ; Timer/Counter2 Overflow
-.org 10
- rcall isr ; Timer/Counter1 Capture Event
-.org 12
- rcall isr ; Timer/Counter1 Compare Match A
-.org 14
- rcall isr ; Timer/Counter1 Compare Match B
-.org 16
- rcall isr ; Timer/Counter1 Overflow
-.org 18
- rcall isr ; Timer/Counter0 Overflow
-.org 20
- rcall isr ; Serial Transfer Complete
-.org 22
- rcall isr ; USART, Rx Complete
-.org 24
- rcall isr ; USART Data Register Empty
-.org 26
- rcall isr ; USART, Tx Complete
-.org 28
- rcall isr ; ADC Conversion Complete
-.org 30
- rcall isr ; EEPROM Ready
-.org 32
- rcall isr ; Analog Comparator
-.org 34
- rcall isr ; 2-wire Serial Interface
-.org 36
- rcall isr ; External Interrupt Request 2
-.org 38
- rcall isr ; Timer/Counter0 Compare Match
-.org 40
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 21
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 9
- .db "ATmega16A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16a/device.inc b/amforth-6.5/avr8/devices/atmega16a/device.inc
deleted file mode 100644
index 03920ee..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/device.inc
+++ /dev/null
@@ -1,765 +0,0 @@
-; Partname: ATmega16A
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16a/device.py b/amforth-6.5/avr8/devices/atmega16a/device.py
deleted file mode 100644
index 9d8e095..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/device.py
+++ /dev/null
@@ -1,284 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'TIMER2_COMPAddr' : '#6', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#8', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#10', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#12', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#14', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#16', # Timer/Counter1 Overflow
- 'TIMER0_OVFAddr' : '#18', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#20', # Serial Transfer Complete
- 'USART_RXCAddr' : '#22', # USART, Rx Complete
- 'USART_UDREAddr' : '#24', # USART Data Register Empty
- 'USART_TXCAddr' : '#26', # USART, Tx Complete
- 'ADCAddr' : '#28', # ADC Conversion Complete
- 'EE_RDYAddr' : '#30', # EEPROM Ready
- 'ANA_COMPAddr' : '#32', # Analog Comparator
- 'TWIAddr' : '#34', # 2-wire Serial Interface
- 'INT2Addr' : '#36', # External Interrupt Request 2
- 'TIMER0_COMPAddr' : '#38', # Timer/Counter0 Compare Match
- 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$5c', # Output Compare Register
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
- 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module EXTERNAL_INTERRUPT
- 'GICR' : '$5b', # General Interrupt Control Regi
- 'GICR_INT': '$c0', # External Interrupt Request 1 E
- 'GICR_INT2': '$20', # External Interrupt Request 2 E
- 'GICR_IVSEL': '$2', # Interrupt Vector Select
- 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
- 'GIFR' : '$5a', # General Interrupt Flag Registe
- 'GIFR_INTF': '$c0', # External Interrupt Flags
- 'GIFR_INTF2': '$20', # External Interrupt Flag 2
- 'MCUCR' : '$55', # General Interrupt Control Regi
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Address Register Bytes
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SM': '$b0', # Sleep Mode Select
- 'MCUCR_SE': '$40', # Sleep Enable
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$51', # Oscillator Calibration Value
- 'SFIOR' : '$50', # Special function I/O register
- 'SFIOR_PUD': '$4', # Pull-up Disable
- 'SFIOR_PSR2': '$2', # Prescaler reset
- 'SFIOR_PSR10': '$1', # Prescaler reset
-
-# Module TIMER_COUNTER_2
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
- 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
- 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TCCR2' : '$45', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Waveform Genration Mode
- 'TCCR2_COM2': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$44', # Timer/Counter2
- 'OCR2' : '$43', # Timer/Counter2 Output Compare
- 'ASSR' : '$42', # Asynchronous Status Register
- 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
- 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module USART
- 'UDR' : '$2c', # USART I/O Data Register
- 'UCSRA' : '$2b', # USART Control and Status Regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data overRun
- 'UCSRA_UPE': '$4', # Parity Error
- 'UCSRA_U2X': '$2', # Double the USART transmission
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$2a', # USART Control and Status Regis
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$40', # USART Control and Status Regis
- 'UCSRC_URSEL': '$80', # Register Select
- 'UCSRC_UMSEL': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$40', # USART Baud Rate Register Hight
- 'UBRRL' : '$29', # USART Baud Rate Register Low B
-
-# Module TWI
- 'TWBR' : '$20', # TWI Bit Rate register
- 'TWCR' : '$56', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$21', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$23', # TWI Data register
- 'TWAR' : '$22', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # When this bit is written to on
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$24', # ADC Data Register Bytes
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDTOE': '$10', # RW
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16a/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega16a/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hva/atmega16hva.frt b/amforth-6.5/avr8/devices/atmega16hva/atmega16hva.frt
deleted file mode 100644
index 6e3bec4..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva/atmega16hva.frt
+++ /dev/null
@@ -1,140 +0,0 @@
-\ Partname: ATmega16HVA
-\ Built using part description XML file version 40
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant VADCH \ VADC Data Register High Byte
-78 constant VADCL \ VADC Data Register Low Byte
-7A constant VADCSR \ The VADC Control and Status register
-7C constant VADMUX \ The VADC multiplexer Selection Register
-
-\ BANDGAP
-D0 constant BGCCR \ Bandgap Calibration Register
-D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder
-
-\ BATTERY_PROTECTION
-F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register
-F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register
-FD constant BPCR \ Battery Protection Control Register
-F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register
-F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register
-FC constant BPHCTR \ Battery Protection Short-current Timing Register
-F3 constant BPIFR \ Battery Protection Interrupt Flag Register
-F2 constant BPIMSK \ Battery Protection Interrupt Mask Register
-FB constant BPOCTR \ Battery Protection Over-current Timing Register
-FE constant BPPLR \ Battery Protection Parameter Lock Register
-F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
-FA constant BPSCTR \ Battery Protection Short-current Timing Register
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control and Status Register
-
-\ COULOMB_COUNTER
-E0 constant CADAC0 \ ADC Accumulate Current
-E1 constant CADAC1 \ ADC Accumulate Current
-E2 constant CADAC2 \ ADC Accumulate Current
-E3 constant CADAC3 \ ADC Accumulate Current
-E4 constant CADCSRA \ CC-ADC Control and Status Register A
-E5 constant CADCSRB \ CC-ADC Control and Status Register B
-E9 constant CADICH \ CC-ADC Instantaneous Current
-E8 constant CADICL \ CC-ADC Instantaneous Current
-E6 constant CADRC \ CC-ADC Regular Current
-
-\ CPU
-61 constant CLKPR \ Clock Prescale Register
-7E constant DIDR0 \ Digital Input Disable Register
-66 constant FOSCCAL \ Fast Oscillator Calibration Value
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register
-64 constant PRR0 \ Power Reduction Register 0
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-41 constant EEAR \ EEPROM Read/Write Access
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-
-\ FET
-F0 constant FCSR \ FET Control and Status Register
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Data Direction Register, Port B
-23 constant PINB \ Input Pins, Port B
-25 constant PORTB \ Data Register, Port B
-
-\ PORTC
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ SPI
-4c constant SPCR \ SPI Control Register
-4e constant SPDR \ SPI Data Register
-4d constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-48 constant OCR0A \ Output compare Register A
-49 constant OCR0B \ Output compare Register B
-44 constant TCCR0A \ Timer/Counter0 Control Register
-45 constant TCCR0B \ Timer/Counter0 Control Register
-47 constant TCNT0H \ Timer Counter 0 High Byte
-46 constant TCNT0L \ Timer Counter 0 Low Byte
-35 constant TIFR0 \ Timer/Counter Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-43 constant GTCCR \ General Timer/Counter Control Register
-88 constant OCR1A \ Output Compare Register 1A
-89 constant OCR1B \ Output Compare Register B
-80 constant TCCR1A \ Timer/Counter 1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-85 constant TCNT1H \ Timer Counter 1 High Byte
-84 constant TCNT1L \ Timer Counter 1 Low Byte
-36 constant TIFR1 \ Timer/Counter Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
-
-\ VOLTAGE_REGULATOR
-C8 constant ROCR \ Regulator Operating Condition Register
-
-\ WATCHDOG
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-0002 constant BPINTAddr \ Battery Protection Interrupt
-0004 constant VREGMONAddr \ Voltage regulator monitor interrupt
-0006 constant INT0Addr \ External Interrupt Request 0
-0008 constant INT1Addr \ External Interrupt Request 1
-000A constant INT2Addr \ External Interrupt Request 2
-000C constant WDTAddr \ Watchdog Timeout Interrupt
-000E constant TIMER1_ICAddr \ Timer 1 Input capture
-0010 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-0012 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-0014 constant TIMER1_OVFAddr \ Timer 1 overflow
-0016 constant TIMER0_ICAddr \ Timer 0 Input Capture
-0018 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-001A constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-001C constant TIMER0_OVFAddr \ Timer 0 Overflow
-001E constant SPI;STCAddr \ SPI Serial transfer complete
-0020 constant VADCAddr \ Voltage ADC Conversion Complete
-0022 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-0024 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-0026 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-028 constant EE_READYAddr \ EEPROM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hva/device.asm b/amforth-6.5/avr8/devices/atmega16hva/device.asm
deleted file mode 100644
index 1f5b109..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega16HVA
-; Built using part description XML file version 40
-; generated automatically, do not edit
-
-.nolist
- .include "m16HVAdef.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_BANDGAP = 0
-.set WANT_BATTERY_PROTECTION = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_COULOMB_COUNTER = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_FET = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_VOLTAGE_REGULATOR = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 21
-.org $0002
- rcall isr ; Battery Protection Interrupt
-.org $0004
- rcall isr ; Voltage regulator monitor interrupt
-.org $0006
- rcall isr ; External Interrupt Request 0
-.org $0008
- rcall isr ; External Interrupt Request 1
-.org $000A
- rcall isr ; External Interrupt Request 2
-.org $000C
- rcall isr ; Watchdog Timeout Interrupt
-.org $000E
- rcall isr ; Timer 1 Input capture
-.org $0010
- rcall isr ; Timer 1 Compare Match A
-.org $0012
- rcall isr ; Timer 1 Compare Match B
-.org $0014
- rcall isr ; Timer 1 overflow
-.org $0016
- rcall isr ; Timer 0 Input Capture
-.org $0018
- rcall isr ; Timer 0 Comapre Match A
-.org $001A
- rcall isr ; Timer 0 Compare Match B
-.org $001C
- rcall isr ; Timer 0 Overflow
-.org $001E
- rcall isr ; SPI Serial transfer complete
-.org $0020
- rcall isr ; Voltage ADC Conversion Complete
-.org $0022
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org $0024
- rcall isr ; Coloumb Counter ADC Regular Current
-.org $0026
- rcall isr ; Coloumb Counter ADC Accumulator
-.org $028
- rcall isr ; EEPROM Ready
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 256
-mcu_maxdp:
- .dw 0 ; minimum of 0 (from XML) and 0xffff
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 11
- .db "ATmega16HVA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hva/device.inc b/amforth-6.5/avr8/devices/atmega16hva/device.inc
deleted file mode 100644
index 8664a17..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva/device.inc
+++ /dev/null
@@ -1,1053 +0,0 @@
-; Partname: ATmega16HVA
-; Built using part description XML file version 40
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register High Byte
-VE_VADCH:
- .dw $ff05
- .db "VADCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCH
-XT_VADCH:
- .dw PFA_DOVARIABLE
-PFA_VADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register Low Byte
-VE_VADCL:
- .dw $ff05
- .db "VADCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCL
-XT_VADCL:
- .dw PFA_DOVARIABLE
-PFA_VADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC Control and Status register
-VE_VADCSR:
- .dw $ff06
- .db "VADCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCSR
-XT_VADCSR:
- .dw PFA_DOVARIABLE
-PFA_VADCSR:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC multiplexer Selection Register
-VE_VADMUX:
- .dw $ff06
- .db "VADMUX"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADMUX
-XT_VADMUX:
- .dw PFA_DOVARIABLE
-PFA_VADMUX:
- .dw $7C
-
-.endif
-
-; ********
-.if WANT_BANDGAP == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration Register
-VE_BGCCR:
- .dw $ff05
- .db "BGCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCCR
-XT_BGCCR:
- .dw PFA_DOVARIABLE
-PFA_BGCCR:
- .dw $D0
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration of Resistor Ladder
-VE_BGCRR:
- .dw $ff05
- .db "BGCRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRR
-XT_BGCRR:
- .dw PFA_DOVARIABLE
-PFA_BGCRR:
- .dw $D1
-
-.endif
-
-; ********
-.if WANT_BATTERY_PROTECTION == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Charge-High-current Detection Level Register
-VE_BPCHCD:
- .dw $ff06
- .db "BPCHCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCHCD
-XT_BPCHCD:
- .dw PFA_DOVARIABLE
-PFA_BPCHCD:
- .dw $F9
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Charge-Over-current Detection Level Register
-VE_BPCOCD:
- .dw $ff06
- .db "BPCOCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCOCD
-XT_BPCOCD:
- .dw PFA_DOVARIABLE
-PFA_BPCOCD:
- .dw $F7
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Control Register
-VE_BPCR:
- .dw $ff04
- .db "BPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCR
-XT_BPCR:
- .dw PFA_DOVARIABLE
-PFA_BPCR:
- .dw $FD
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Discharge-High-current Detection Level Register
-VE_BPDHCD:
- .dw $ff06
- .db "BPDHCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDHCD
-XT_BPDHCD:
- .dw PFA_DOVARIABLE
-PFA_BPDHCD:
- .dw $F8
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Discharge-Over-current Detection Level Register
-VE_BPDOCD:
- .dw $ff06
- .db "BPDOCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDOCD
-XT_BPDOCD:
- .dw PFA_DOVARIABLE
-PFA_BPDOCD:
- .dw $F6
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-current Timing Register
-VE_BPHCTR:
- .dw $ff06
- .db "BPHCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPHCTR
-XT_BPHCTR:
- .dw PFA_DOVARIABLE
-PFA_BPHCTR:
- .dw $FC
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Flag Register
-VE_BPIFR:
- .dw $ff05
- .db "BPIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIFR
-XT_BPIFR:
- .dw PFA_DOVARIABLE
-PFA_BPIFR:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Mask Register
-VE_BPIMSK:
- .dw $ff06
- .db "BPIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIMSK
-XT_BPIMSK:
- .dw PFA_DOVARIABLE
-PFA_BPIMSK:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Over-current Timing Register
-VE_BPOCTR:
- .dw $ff06
- .db "BPOCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPOCTR
-XT_BPOCTR:
- .dw PFA_DOVARIABLE
-PFA_BPOCTR:
- .dw $FB
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Parameter Lock Register
-VE_BPPLR:
- .dw $ff05
- .db "BPPLR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPPLR
-XT_BPPLR:
- .dw PFA_DOVARIABLE
-PFA_BPPLR:
- .dw $FE
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-Circuit Detection Level Register
-VE_BPSCD:
- .dw $ff05
- .db "BPSCD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCD
-XT_BPSCD:
- .dw PFA_DOVARIABLE
-PFA_BPSCD:
- .dw $F5
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-current Timing Register
-VE_BPSCTR:
- .dw $ff06
- .db "BPSCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCTR
-XT_BPSCTR:
- .dw PFA_DOVARIABLE
-PFA_BPSCTR:
- .dw $FA
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_COULOMB_COUNTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC0:
- .dw $ff06
- .db "CADAC0"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC0
-XT_CADAC0:
- .dw PFA_DOVARIABLE
-PFA_CADAC0:
- .dw $E0
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC1:
- .dw $ff06
- .db "CADAC1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC1
-XT_CADAC1:
- .dw PFA_DOVARIABLE
-PFA_CADAC1:
- .dw $E1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC2:
- .dw $ff06
- .db "CADAC2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC2
-XT_CADAC2:
- .dw PFA_DOVARIABLE
-PFA_CADAC2:
- .dw $E2
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC3:
- .dw $ff06
- .db "CADAC3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC3
-XT_CADAC3:
- .dw PFA_DOVARIABLE
-PFA_CADAC3:
- .dw $E3
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register A
-VE_CADCSRA:
- .dw $ff07
- .db "CADCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRA
-XT_CADCSRA:
- .dw PFA_DOVARIABLE
-PFA_CADCSRA:
- .dw $E4
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register B
-VE_CADCSRB:
- .dw $ff07
- .db "CADCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRB
-XT_CADCSRB:
- .dw PFA_DOVARIABLE
-PFA_CADCSRB:
- .dw $E5
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADICH:
- .dw $ff06
- .db "CADICH"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICH
-XT_CADICH:
- .dw PFA_DOVARIABLE
-PFA_CADICH:
- .dw $E9
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADICL:
- .dw $ff06
- .db "CADICL"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICL
-XT_CADICL:
- .dw PFA_DOVARIABLE
-PFA_CADICL:
- .dw $E8
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regular Current
-VE_CADRC:
- .dw $ff05
- .db "CADRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRC
-XT_CADRC:
- .dw PFA_DOVARIABLE
-PFA_CADRC:
- .dw $E6
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-; ( -- addr ) System Constant
-; R( -- )
-; Fast Oscillator Calibration Value
-VE_FOSCCAL:
- .dw $ff07
- .db "FOSCCAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_FOSCCAL
-XT_FOSCCAL:
- .dw PFA_DOVARIABLE
-PFA_FOSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Sampling Interface Control and Status Register
-VE_OSICSR:
- .dw $ff06
- .db "OSICSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSICSR
-XT_OSICSR:
- .dw PFA_DOVARIABLE
-PFA_OSICSR:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_FET == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; FET Control and Status Register
-VE_FCSR:
- .dw $ff04
- .db "FCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_FCSR
-XT_FCSR:
- .dw PFA_DOVARIABLE
-PFA_FCSR:
- .dw $F0
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port B
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port B
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port B
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4c
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4e
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4d
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register A
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 High Byte
-VE_TCNT0H:
- .dw $ff06
- .db "TCNT0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0H
-XT_TCNT0H:
- .dw PFA_DOVARIABLE
-PFA_TCNT0H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 Low Byte
-VE_TCNT0L:
- .dw $ff06
- .db "TCNT0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0L
-XT_TCNT0L:
- .dw PFA_DOVARIABLE
-PFA_TCNT0L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 1A
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register B
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_VOLTAGE_REGULATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Operating Condition Register
-VE_ROCR:
- .dw $ff04
- .db "ROCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ROCR
-XT_ROCR:
- .dw PFA_DOVARIABLE
-PFA_ROCR:
- .dw $C8
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16hva/device.py b/amforth-6.5/avr8/devices/atmega16hva/device.py
deleted file mode 100644
index fdbd4c4..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva/device.py
+++ /dev/null
@@ -1,274 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16HVA
-
-MCUREGS = {
-# Interrupt Vectors
- 'BPINTAddr' : '#2', # Battery Protection Interrupt
- 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
- 'INT0Addr' : '#6', # External Interrupt Request 0
- 'INT1Addr' : '#8', # External Interrupt Request 1
- 'INT2Addr' : '#10', # External Interrupt Request 2
- 'WDTAddr' : '#12', # Watchdog Timeout Interrupt
- 'TIMER1_ICAddr' : '#14', # Timer 1 Input capture
- 'TIMER1_COMPAAddr' : '#16', # Timer 1 Compare Match A
- 'TIMER1_COMPBAddr' : '#18', # Timer 1 Compare Match B
- 'TIMER1_OVFAddr' : '#20', # Timer 1 overflow
- 'TIMER0_ICAddr' : '#22', # Timer 0 Input Capture
- 'TIMER0_COMPAAddr' : '#24', # Timer 0 Comapre Match A
- 'TIMER0_COMPBAddr' : '#26', # Timer 0 Compare Match B
- 'TIMER0_OVFAddr' : '#28', # Timer 0 Overflow
- 'SPI_STCAddr' : '#30', # SPI Serial transfer complete
- 'VADCAddr' : '#32', # Voltage ADC Conversion Complete
- 'CCADC_CONVAddr' : '#34', # Coulomb Counter ADC Conversion Complete
- 'CCADC_REG_CURAddr' : '#36', # Coloumb Counter ADC Regular Current
- 'CCADC_ACCAddr' : '#38', # Coloumb Counter ADC Accumulator
- 'EE_READYAddr' : '#40', # EEPROM Ready
-
-# Module AD_CONVERTER
- 'VADMUX' : '$7c', # The VADC multiplexer Selection
- 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
- 'VADC' : '$78', # VADC Data Register Bytes
- 'VADCSR' : '$7a', # The VADC Control and Status re
- 'VADCSR_VADEN': '$8', # VADC Enable
- 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
- 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
- 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module BANDGAP
- 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
- 'BGCCR' : '$d0', # Bandgap Calibration Register
- 'BGCCR_BGD': '$80', # Setting the BGD bit to one wil
- 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module FET
- 'FCSR' : '$f0', # FET Control and Status Registe
- 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
- 'FCSR_CPS': '$4', # Current Protection Status
- 'FCSR_DFE': '$2', # Discharge FET Enable
- 'FCSR_CFE': '$1', # Charge FET Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_CTPB': '$10', # Clear Temporary Page Buffer
- 'SPMCSR_RFLB': '$8', # Read Fuse and Lock Bits
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTB
- 'PORTB' : '$25', # Data Register, Port B
- 'DDRB' : '$24', # Data Direction Register, Port
- 'PINB' : '$23', # Input Pins, Port B
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_CKOE': '$20', # Clock Output Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_OCDRF': '$10', # OCD Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
- 'OSICSR' : '$37', # Oscillator Sampling Interface
- 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
- 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
- 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_PA1DID': '$2', # When this bit is written logic
- 'DIDR0_PA0DID': '$1', # When this bit is written logic
- 'PRR0' : '$64', # Power Reduction Register 0
- 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
- 'PRR0_PRSPI': '$8', # Power reduction SPI
- 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
- 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
- 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
-
-# Module BATTERY_PROTECTION
- 'BPPLR' : '$fe', # Battery Protection Parameter L
- 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
- 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
- 'BPCR' : '$fd', # Battery Protection Control Reg
- 'BPCR_SCD': '$10', # Short Circuit Protection Disab
- 'BPCR_DOCD': '$8', # Discharge Over-current Protect
- 'BPCR_COCD': '$4', # Charge Over-current Protection
- 'BPCR_DHCD': '$2', # Discharge High-current Protect
- 'BPCR_CHCD': '$1', # Charge High-current Protection
- 'BPHCTR' : '$fc', # Battery Protection Short-curre
- 'BPOCTR' : '$fb', # Battery Protection Over-curren
- 'BPSCTR' : '$fa', # Battery Protection Short-curre
- 'BPCHCD' : '$f9', # Battery Protection Charge-High
- 'BPDHCD' : '$f8', # Battery Protection Discharge-H
- 'BPCOCD' : '$f7', # Battery Protection Charge-Over
- 'BPDOCD' : '$f6', # Battery Protection Discharge-O
- 'BPSCD' : '$f5', # Battery Protection Short-Circu
- 'BPIFR' : '$f3', # Battery Protection Interrupt F
- 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
- 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
- 'BPIFR_COCIF': '$4', # Charge Over-current Protection
- 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
- 'BPIFR_CHCIF': '$1', # Charge High-current Protection
- 'BPIMSK' : '$f2', # Battery Protection Interrupt M
- 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
- 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
- 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
- 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
- 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_1
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_CS': '$7', # Clock Select1 bis
- 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
- 'TCCR1A_TCW1': '$80', # Timer/Counter Width
- 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
- 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
- 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
- 'TCCR1A_ICS1': '$8', # Input Capture Select
- 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
- 'TCNT1' : '$84', # Timer Counter 1 Bytes
- 'OCR1A' : '$88', # Output Compare Register 1A
- 'OCR1B' : '$89', # Output Compare Register B
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module COULOMB_COUNTER
- 'CADCSRA' : '$e4', # CC-ADC Control and Status Regi
- 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
- 'CADCSRA_CADPOL': '$40', #
- 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
- 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
- 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
- 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
- 'CADCSRB' : '$e5', # CC-ADC Control and Status Regi
- 'CADCSRB_CADACIE': '$40', #
- 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
- 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
- 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
- 'CADIC' : '$e8', # CC-ADC Instantaneous Current
- 'CADAC3' : '$e3', # ADC Accumulate Current
- 'CADAC2' : '$e2', # ADC Accumulate Current
- 'CADAC1' : '$e1', # ADC Accumulate Current
- 'CADAC0' : '$e0', # ADC Accumulate Current
- 'CADRC' : '$e6', # CC-ADC Regular Current
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_TCW0': '$80', # Timer/Counter Width
- 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
- 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
- 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
- 'TCCR0A_ICS0': '$8', # Input Capture Select
- 'TCCR0A_WGM00': '$1', # Clock Select0 bit 0
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
- 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
- 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
- 'TCNT0' : '$46', # Timer Counter 0 Bytes
- 'OCR0A' : '$48', # Output compare Register A
- 'OCR0B' : '$49', # Output compare Register B
- 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
- 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
- 'TIMSK0_OCIE0B': '$4', # Output Compare Interrupt Enabl
- 'TIMSK0_OCIE0A': '$2', # Output Compare Interrupt Enabl
- 'TIMSK0_TOIE0': '$1', # Overflow Interrupt Enable
- 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
- 'TIFR0_ICF0': '$8', # Timer/Counter Interrupt Flag R
- 'TIFR0_OCF0B': '$4', # Output Compare Flag
- 'TIFR0_OCF0A': '$2', # Output Compare Flag
- 'TIFR0_TOV0': '$1', # Overflow Flag
-
-# Module VOLTAGE_REGULATOR
- 'ROCR' : '$c8', # Regulator Operating Condition
- 'ROCR_ROCS': '$80', # ROC Status
- 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
- 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/atmega16hva2.frt b/amforth-6.5/avr8/devices/atmega16hva2/atmega16hva2.frt
deleted file mode 100644
index fe9f503..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva2/atmega16hva2.frt
+++ /dev/null
@@ -1,144 +0,0 @@
-\ Partname: ATmega16HVA2
-\ Built using part description XML file version 1
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant VADCH \ VADC Data Register High Byte
-78 constant VADCL \ VADC Data Register Low Byte
-7A constant VADCSR \ The VADC Control and Status register
-7C constant VADMUX \ The VADC multiplexer Selection Register
-
-\ BANDGAP
-D0 constant BGCCR \ Bandgap Calibration Register
-D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder
-
-\ BATTERY_PROTECTION
-F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register
-F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register
-FD constant BPCR \ Battery Protection Control Register
-F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register
-F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register
-FC constant BPHCTR \ Battery Protection Short-current Timing Register
-F3 constant BPIFR \ Battery Protection Interrupt Flag Register
-F2 constant BPIMSK \ Battery Protection Interrupt Mask Register
-FB constant BPOCTR \ Battery Protection Over-current Timing Register
-FE constant BPPLR \ Battery Protection Parameter Lock Register
-F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
-FA constant BPSCTR \ Battery Protection Short-current Timing Register
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control and Status Register
-
-\ COULOMB_COUNTER
-E0 constant CADAC0 \ ADC Accumulate Current
-E1 constant CADAC1 \ ADC Accumulate Current
-E2 constant CADAC2 \ ADC Accumulate Current
-E3 constant CADAC3 \ ADC Accumulate Current
-E4 constant CADCSRA \ CC-ADC Control and Status Register A
-E5 constant CADCSRB \ CC-ADC Control and Status Register B
-E9 constant CADICH \ CC-ADC Instantaneous Current
-E8 constant CADICL \ CC-ADC Instantaneous Current
-E6 constant CADRC \ CC-ADC Regular Current
-
-\ CPU
-61 constant CLKPR \ Clock Prescale Register
-7E constant DIDR0 \ Digital Input Disable Register
-66 constant FOSCCAL \ Fast Oscillator Calibration Value
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register
-64 constant PRR0 \ Power Reduction Register 0
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-41 constant EEAR \ EEPROM Read/Write Access
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-68 constant PCICR \ Pin Change Interrupt Control Register
-3B constant PCIFR \ Pin Change Interrupt Flag Register
-6B constant PCMSK0 \ Pin Change Mask Register 0
-
-\ FET
-F0 constant FCSR \ FET Control and Status Register
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Data Direction Register, Port B
-23 constant PINB \ Input Pins, Port B
-25 constant PORTB \ Data Register, Port B
-
-\ PORTC
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ SPI
-4c constant SPCR \ SPI Control Register
-4e constant SPDR \ SPI Data Register
-4d constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-48 constant OCR0A \ Output compare Register A
-49 constant OCR0B \ Output compare Register B
-44 constant TCCR0A \ Timer/Counter0 Control Register
-45 constant TCCR0B \ Timer/Counter0 Control Register
-47 constant TCNT0H \ Timer Counter 0 High Byte
-46 constant TCNT0L \ Timer Counter 0 Low Byte
-35 constant TIFR0 \ Timer/Counter Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-43 constant GTCCR \ General Timer/Counter Control Register
-88 constant OCR1A \ Output Compare Register 1A
-89 constant OCR1B \ Output Compare Register B
-80 constant TCCR1A \ Timer/Counter 1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-85 constant TCNT1H \ Timer Counter 1 High Byte
-84 constant TCNT1L \ Timer Counter 1 Low Byte
-36 constant TIFR1 \ Timer/Counter Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
-
-\ VOLTAGE_REGULATOR
-C8 constant ROCR \ Regulator Operating Condition Register
-
-\ WATCHDOG
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-0002 constant BPINTAddr \ Battery Protection Interrupt
-0004 constant VREGMONAddr \ Voltage regulator monitor interrupt
-0006 constant INT0Addr \ External Interrupt Request 0
-0008 constant INT1Addr \ External Interrupt Request 1
-000A constant INT2Addr \ External Interrupt Request 2
-000C constant PCINT0Addr \ Pin Change Interrupt Request 0
-000E constant WDTAddr \ Watchdog Timeout Interrupt
-0010 constant TIMER1_ICAddr \ Timer 1 Input capture
-0012 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-0014 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-0016 constant TIMER1_OVFAddr \ Timer 1 overflow
-0018 constant TIMER0_ICAddr \ Timer 0 Input Capture
-001A constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-001C constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-001E constant TIMER0_OVFAddr \ Timer 0 Overflow
-0020 constant SPI;STCAddr \ SPI Serial transfer complete
-0022 constant VADCAddr \ Voltage ADC Conversion Complete
-0024 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-0026 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-0028 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-02A constant EE_READYAddr \ EEPROM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/device.asm b/amforth-6.5/avr8/devices/atmega16hva2/device.asm
deleted file mode 100644
index 7ce9455..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva2/device.asm
+++ /dev/null
@@ -1,116 +0,0 @@
-; Partname: ATmega16HVA2
-; Built using part description XML file version 1
-; generated automatically, do not edit
-
-.nolist
- .include "m16HVA2def.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_BANDGAP = 0
-.set WANT_BATTERY_PROTECTION = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_COULOMB_COUNTER = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_FET = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_VOLTAGE_REGULATOR = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 22
-.org $0002
- rcall isr ; Battery Protection Interrupt
-.org $0004
- rcall isr ; Voltage regulator monitor interrupt
-.org $0006
- rcall isr ; External Interrupt Request 0
-.org $0008
- rcall isr ; External Interrupt Request 1
-.org $000A
- rcall isr ; External Interrupt Request 2
-.org $000C
- rcall isr ; Pin Change Interrupt Request 0
-.org $000E
- rcall isr ; Watchdog Timeout Interrupt
-.org $0010
- rcall isr ; Timer 1 Input capture
-.org $0012
- rcall isr ; Timer 1 Compare Match A
-.org $0014
- rcall isr ; Timer 1 Compare Match B
-.org $0016
- rcall isr ; Timer 1 overflow
-.org $0018
- rcall isr ; Timer 0 Input Capture
-.org $001A
- rcall isr ; Timer 0 Comapre Match A
-.org $001C
- rcall isr ; Timer 0 Compare Match B
-.org $001E
- rcall isr ; Timer 0 Overflow
-.org $0020
- rcall isr ; SPI Serial transfer complete
-.org $0022
- rcall isr ; Voltage ADC Conversion Complete
-.org $0024
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org $0026
- rcall isr ; Coloumb Counter ADC Regular Current
-.org $0028
- rcall isr ; Coloumb Counter ADC Accumulator
-.org $02A
- rcall isr ; EEPROM Ready
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 256
-mcu_maxdp:
- .dw 0 ; minimum of 0 (from XML) and 0xffff
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 12
- .db "ATmega16HVA2"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/device.inc b/amforth-6.5/avr8/devices/atmega16hva2/device.inc
deleted file mode 100644
index c0f9e0a..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva2/device.inc
+++ /dev/null
@@ -1,1089 +0,0 @@
-; Partname: ATmega16HVA2
-; Built using part description XML file version 1
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register High Byte
-VE_VADCH:
- .dw $ff05
- .db "VADCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCH
-XT_VADCH:
- .dw PFA_DOVARIABLE
-PFA_VADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register Low Byte
-VE_VADCL:
- .dw $ff05
- .db "VADCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCL
-XT_VADCL:
- .dw PFA_DOVARIABLE
-PFA_VADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC Control and Status register
-VE_VADCSR:
- .dw $ff06
- .db "VADCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCSR
-XT_VADCSR:
- .dw PFA_DOVARIABLE
-PFA_VADCSR:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC multiplexer Selection Register
-VE_VADMUX:
- .dw $ff06
- .db "VADMUX"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADMUX
-XT_VADMUX:
- .dw PFA_DOVARIABLE
-PFA_VADMUX:
- .dw $7C
-
-.endif
-
-; ********
-.if WANT_BANDGAP == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration Register
-VE_BGCCR:
- .dw $ff05
- .db "BGCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCCR
-XT_BGCCR:
- .dw PFA_DOVARIABLE
-PFA_BGCCR:
- .dw $D0
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration of Resistor Ladder
-VE_BGCRR:
- .dw $ff05
- .db "BGCRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRR
-XT_BGCRR:
- .dw PFA_DOVARIABLE
-PFA_BGCRR:
- .dw $D1
-
-.endif
-
-; ********
-.if WANT_BATTERY_PROTECTION == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Charge-High-current Detection Level Register
-VE_BPCHCD:
- .dw $ff06
- .db "BPCHCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCHCD
-XT_BPCHCD:
- .dw PFA_DOVARIABLE
-PFA_BPCHCD:
- .dw $F9
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Charge-Over-current Detection Level Register
-VE_BPCOCD:
- .dw $ff06
- .db "BPCOCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCOCD
-XT_BPCOCD:
- .dw PFA_DOVARIABLE
-PFA_BPCOCD:
- .dw $F7
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Control Register
-VE_BPCR:
- .dw $ff04
- .db "BPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCR
-XT_BPCR:
- .dw PFA_DOVARIABLE
-PFA_BPCR:
- .dw $FD
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Discharge-High-current Detection Level Register
-VE_BPDHCD:
- .dw $ff06
- .db "BPDHCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDHCD
-XT_BPDHCD:
- .dw PFA_DOVARIABLE
-PFA_BPDHCD:
- .dw $F8
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Discharge-Over-current Detection Level Register
-VE_BPDOCD:
- .dw $ff06
- .db "BPDOCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDOCD
-XT_BPDOCD:
- .dw PFA_DOVARIABLE
-PFA_BPDOCD:
- .dw $F6
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-current Timing Register
-VE_BPHCTR:
- .dw $ff06
- .db "BPHCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPHCTR
-XT_BPHCTR:
- .dw PFA_DOVARIABLE
-PFA_BPHCTR:
- .dw $FC
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Flag Register
-VE_BPIFR:
- .dw $ff05
- .db "BPIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIFR
-XT_BPIFR:
- .dw PFA_DOVARIABLE
-PFA_BPIFR:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Mask Register
-VE_BPIMSK:
- .dw $ff06
- .db "BPIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIMSK
-XT_BPIMSK:
- .dw PFA_DOVARIABLE
-PFA_BPIMSK:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Over-current Timing Register
-VE_BPOCTR:
- .dw $ff06
- .db "BPOCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPOCTR
-XT_BPOCTR:
- .dw PFA_DOVARIABLE
-PFA_BPOCTR:
- .dw $FB
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Parameter Lock Register
-VE_BPPLR:
- .dw $ff05
- .db "BPPLR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPPLR
-XT_BPPLR:
- .dw PFA_DOVARIABLE
-PFA_BPPLR:
- .dw $FE
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-Circuit Detection Level Register
-VE_BPSCD:
- .dw $ff05
- .db "BPSCD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCD
-XT_BPSCD:
- .dw PFA_DOVARIABLE
-PFA_BPSCD:
- .dw $F5
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-current Timing Register
-VE_BPSCTR:
- .dw $ff06
- .db "BPSCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCTR
-XT_BPSCTR:
- .dw PFA_DOVARIABLE
-PFA_BPSCTR:
- .dw $FA
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_COULOMB_COUNTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC0:
- .dw $ff06
- .db "CADAC0"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC0
-XT_CADAC0:
- .dw PFA_DOVARIABLE
-PFA_CADAC0:
- .dw $E0
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC1:
- .dw $ff06
- .db "CADAC1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC1
-XT_CADAC1:
- .dw PFA_DOVARIABLE
-PFA_CADAC1:
- .dw $E1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC2:
- .dw $ff06
- .db "CADAC2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC2
-XT_CADAC2:
- .dw PFA_DOVARIABLE
-PFA_CADAC2:
- .dw $E2
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC3:
- .dw $ff06
- .db "CADAC3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC3
-XT_CADAC3:
- .dw PFA_DOVARIABLE
-PFA_CADAC3:
- .dw $E3
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register A
-VE_CADCSRA:
- .dw $ff07
- .db "CADCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRA
-XT_CADCSRA:
- .dw PFA_DOVARIABLE
-PFA_CADCSRA:
- .dw $E4
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register B
-VE_CADCSRB:
- .dw $ff07
- .db "CADCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRB
-XT_CADCSRB:
- .dw PFA_DOVARIABLE
-PFA_CADCSRB:
- .dw $E5
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADICH:
- .dw $ff06
- .db "CADICH"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICH
-XT_CADICH:
- .dw PFA_DOVARIABLE
-PFA_CADICH:
- .dw $E9
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADICL:
- .dw $ff06
- .db "CADICL"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICL
-XT_CADICL:
- .dw PFA_DOVARIABLE
-PFA_CADICL:
- .dw $E8
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regular Current
-VE_CADRC:
- .dw $ff05
- .db "CADRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRC
-XT_CADRC:
- .dw PFA_DOVARIABLE
-PFA_CADRC:
- .dw $E6
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-; ( -- addr ) System Constant
-; R( -- )
-; Fast Oscillator Calibration Value
-VE_FOSCCAL:
- .dw $ff07
- .db "FOSCCAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_FOSCCAL
-XT_FOSCCAL:
- .dw PFA_DOVARIABLE
-PFA_FOSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Sampling Interface Control and Status Register
-VE_OSICSR:
- .dw $ff06
- .db "OSICSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSICSR
-XT_OSICSR:
- .dw PFA_DOVARIABLE
-PFA_OSICSR:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw $68
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw $3B
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw $6B
-
-.endif
-
-; ********
-.if WANT_FET == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; FET Control and Status Register
-VE_FCSR:
- .dw $ff04
- .db "FCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_FCSR
-XT_FCSR:
- .dw PFA_DOVARIABLE
-PFA_FCSR:
- .dw $F0
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port B
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port B
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port B
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4c
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4e
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4d
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register A
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 High Byte
-VE_TCNT0H:
- .dw $ff06
- .db "TCNT0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0H
-XT_TCNT0H:
- .dw PFA_DOVARIABLE
-PFA_TCNT0H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 Low Byte
-VE_TCNT0L:
- .dw $ff06
- .db "TCNT0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0L
-XT_TCNT0L:
- .dw PFA_DOVARIABLE
-PFA_TCNT0L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 1A
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register B
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_VOLTAGE_REGULATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Operating Condition Register
-VE_ROCR:
- .dw $ff04
- .db "ROCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ROCR
-XT_ROCR:
- .dw PFA_DOVARIABLE
-PFA_ROCR:
- .dw $C8
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/device.py b/amforth-6.5/avr8/devices/atmega16hva2/device.py
deleted file mode 100644
index fb080dc..0000000
--- a/amforth-6.5/avr8/devices/atmega16hva2/device.py
+++ /dev/null
@@ -1,108 +0,0 @@
-# Partname: ATmega16HVA2
-# Built using part description XML file version 1
-# generated automatically, do not edit
-MCUREGS = {
- 'VADCH': '$79',
- 'VADCL': '$78',
- 'VADCSR': '$7A',
- 'VADMUX': '$7C',
- 'BGCCR': '$D0',
- 'BGCRR': '$D1',
- 'BPCHCD': '$F9',
- 'BPCOCD': '$F7',
- 'BPCR': '$FD',
- 'BPDHCD': '$F8',
- 'BPDOCD': '$F6',
- 'BPHCTR': '$FC',
- 'BPIFR': '$F3',
- 'BPIMSK': '$F2',
- 'BPOCTR': '$FB',
- 'BPPLR': '$FE',
- 'BPSCD': '$F5',
- 'BPSCTR': '$FA',
- 'SPMCSR': '$57',
- 'CADAC0': '$E0',
- 'CADAC1': '$E1',
- 'CADAC2': '$E2',
- 'CADAC3': '$E3',
- 'CADCSRA': '$E4',
- 'CADCSRB': '$E5',
- 'CADICH': '$E9',
- 'CADICL': '$E8',
- 'CADRC': '$E6',
- 'CLKPR': '$61',
- 'DIDR0': '$7E',
- 'FOSCCAL': '$66',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$4A',
- 'GPIOR2': '$4B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSICSR': '$37',
- 'PRR0': '$64',
- 'SMCR': '$53',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'EEAR': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EICRA': '$69',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'PCICR': '$68',
- 'PCIFR': '$3B',
- 'PCMSK0': '$6B',
- 'FCSR': '$F0',
- 'DDRA': '$21',
- 'PINA': '$20',
- 'PORTA': '$22',
- 'DDRB': '$24',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'PINC': '$26',
- 'PORTC': '$28',
- 'SPCR': '$4c',
- 'SPDR': '$4e',
- 'SPSR': '$4d',
- 'OCR0A': '$48',
- 'OCR0B': '$49',
- 'TCCR0A': '$44',
- 'TCCR0B': '$45',
- 'TCNT0H': '$47',
- 'TCNT0L': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'GTCCR': '$43',
- 'OCR1A': '$88',
- 'OCR1B': '$89',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'ROCR': '$C8',
- 'WDTCSR': '$60',
- 'BPINTAddr': '$0002',
- 'VREGMONAddr': '$0004',
- 'INT0Addr': '$0006',
- 'INT1Addr': '$0008',
- 'INT2Addr': '$000A',
- 'PCINT0Addr': '$000C',
- 'WDTAddr': '$000E',
- 'TIMER1_ICAddr': '$0010',
- 'TIMER1_COMPAAddr': '$0012',
- 'TIMER1_COMPBAddr': '$0014',
- 'TIMER1_OVFAddr': '$0016',
- 'TIMER0_ICAddr': '$0018',
- 'TIMER0_COMPAAddr': '$001A',
- 'TIMER0_COMPBAddr': '$001C',
- 'TIMER0_OVFAddr': '$001E',
- 'SPI;STCAddr': '$0020',
- 'VADCAddr': '$0022',
- 'CCADC_CONVAddr': '$0024',
- 'CCADC_REG_CURAddr': '$0026',
- 'CCADC_ACCAddr': '$0028',
- 'EE_READYAddr': '$02A'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/atmega16hvb.frt b/amforth-6.5/avr8/devices/atmega16hvb/atmega16hvb.frt
deleted file mode 100644
index 90542af..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/atmega16hvb.frt
+++ /dev/null
@@ -1,33 +0,0 @@
-\ Partname: ATmega16HVB
-\ generated automatically
-
-
-\ Interrupts
-&2 constant BPINTAddr \ Battery Protection Interrupt
-&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
-&6 constant INT0Addr \ External Interrupt Request 0
-&8 constant INT1Addr \ External Interrupt Request 1
-&10 constant INT2Addr \ External Interrupt Request 2
-&12 constant INT3Addr \ External Interrupt Request 3
-&14 constant PCINT0Addr \ Pin Change Interrupt 0
-&16 constant PCINT1Addr \ Pin Change Interrupt 1
-&18 constant WDTAddr \ Watchdog Timeout Interrupt
-&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
-&22 constant CHDETAddr \ Charger Detect
-&24 constant TIMER1_ICAddr \ Timer 1 Input capture
-&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer 1 overflow
-&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
-&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
-&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
-&42 constant TWIAddr \ Two-Wire Serial Interface
-&44 constant SPI_STCAddr \ SPI Serial transfer complete
-&46 constant VADCAddr \ Voltage ADC Conversion Complete
-&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/device.asm b/amforth-6.5/avr8/devices/atmega16hvb/device.asm
deleted file mode 100644
index f128900..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega16HVB
-; generated automatically, do not edit
-
-.nolist
- .include "m16HVBdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Battery Protection Interrupt
-.org 4
- rcall isr ; Voltage regulator monitor interrupt
-.org 6
- rcall isr ; External Interrupt Request 0
-.org 8
- rcall isr ; External Interrupt Request 1
-.org 10
- rcall isr ; External Interrupt Request 2
-.org 12
- rcall isr ; External Interrupt Request 3
-.org 14
- rcall isr ; Pin Change Interrupt 0
-.org 16
- rcall isr ; Pin Change Interrupt 1
-.org 18
- rcall isr ; Watchdog Timeout Interrupt
-.org 20
- rcall isr ; Bandgap Buffer Short Circuit Detected
-.org 22
- rcall isr ; Charger Detect
-.org 24
- rcall isr ; Timer 1 Input capture
-.org 26
- rcall isr ; Timer 1 Compare Match A
-.org 28
- rcall isr ; Timer 1 Compare Match B
-.org 30
- rcall isr ; Timer 1 overflow
-.org 32
- rcall isr ; Timer 0 Input Capture
-.org 34
- rcall isr ; Timer 0 Comapre Match A
-.org 36
- rcall isr ; Timer 0 Compare Match B
-.org 38
- rcall isr ; Timer 0 Overflow
-.org 40
- rcall isr ; Two-Wire Bus Connect/Disconnect
-.org 42
- rcall isr ; Two-Wire Serial Interface
-.org 44
- rcall isr ; SPI Serial transfer complete
-.org 46
- rcall isr ; Voltage ADC Conversion Complete
-.org 48
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org 50
- rcall isr ; Coloumb Counter ADC Regular Current
-.org 52
- rcall isr ; Coloumb Counter ADC Accumulator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; SPM Ready
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 11
- .db "ATmega16HVB",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/device.inc b/amforth-6.5/avr8/devices/atmega16hvb/device.inc
deleted file mode 100644
index 1f86f17..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/device.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-; Partname: ATmega16HVB
-; generated automatically, no not edit
-
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/device.py b/amforth-6.5/avr8/devices/atmega16hvb/device.py
deleted file mode 100644
index f5b504f..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/device.py
+++ /dev/null
@@ -1,342 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16HVB
-
-MCUREGS = {
-# Interrupt Vectors
- 'BPINTAddr' : '#2', # Battery Protection Interrupt
- 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
- 'INT0Addr' : '#6', # External Interrupt Request 0
- 'INT1Addr' : '#8', # External Interrupt Request 1
- 'INT2Addr' : '#10', # External Interrupt Request 2
- 'INT3Addr' : '#12', # External Interrupt Request 3
- 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
- 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
- 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
- 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
- 'CHDETAddr' : '#22', # Charger Detect
- 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
- 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
- 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
- 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
- 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
- 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
- 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
- 'TWIAddr' : '#42', # Two-Wire Serial Interface
- 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
- 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
- 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
- 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
- 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPMAddr' : '#56', # SPM Ready
-
-# Module AD_CONVERTER
- 'VADMUX' : '$7c', # The VADC multiplexer Selection
- 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
- 'VADC' : '$78', # VADC Data Register Bytes
- 'VADCSR' : '$7a', # The VADC Control and Status re
- 'VADCSR_VADEN': '$8', # VADC Enable
- 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
- 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
- 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module FET
- 'FCSR' : '$f0', # FET Control and Status Registe
- 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
- 'FCSR_CPS': '$4', # Current Protection Status
- 'FCSR_DFE': '$2', # Discharge FET Enable
- 'FCSR_CFE': '$1', # Charge FET Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module COULOMB_COUNTER
- 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
- 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
- 'CADCSRA_CADPOL': '$40', #
- 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
- 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
- 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
- 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
- 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
- 'CADCSRB_CADACIE': '$40', #
- 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
- 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
- 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
- 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
- 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
- 'CADIC' : '$e4', # CC-ADC Instantaneous Current
- 'CADAC3' : '$e3', # ADC Accumulate Current
- 'CADAC2' : '$e2', # ADC Accumulate Current
- 'CADAC1' : '$e1', # ADC Accumulate Current
- 'CADAC0' : '$e0', # ADC Accumulate Current
- 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
- 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
-
-# Module TWI
- 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
- 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
- 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
- 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
-
-# Module TIMER_COUNTER_1
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_CS': '$7', # Clock Select1 bis
- 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
- 'TCCR1A_TCW1': '$80', # Timer/Counter Width
- 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
- 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
- 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
- 'TCCR1A_ICS1': '$8', # Input Capture Select
- 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
- 'TCNT1' : '$84', # Timer Counter 1 Bytes
- 'OCR1A' : '$88', # Output Compare Register 1A
- 'OCR1B' : '$89', # Output Compare Register B
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module CELL_BALANCING
- 'CBCR' : '$f1', # Cell Balancing Control Registe
- 'CBCR_CBE': '$f', # Cell Balancing Enables
-
-# Module BATTERY_PROTECTION
- 'BPPLR' : '$fe', # Battery Protection Parameter L
- 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
- 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
- 'BPCR' : '$fd', # Battery Protection Control Reg
- 'BPCR_EPID': '$20', # External Protection Input Disa
- 'BPCR_SCD': '$10', # Short Circuit Protection Disab
- 'BPCR_DOCD': '$8', # Discharge Over-current Protect
- 'BPCR_COCD': '$4', # Charge Over-current Protection
- 'BPCR_DHCD': '$2', # Discharge High-current Protect
- 'BPCR_CHCD': '$1', # Charge High-current Protection
- 'BPHCTR' : '$fc', # Battery Protection Short-curre
- 'BPOCTR' : '$fb', # Battery Protection Over-curren
- 'BPSCTR' : '$fa', # Battery Protection Short-curre
- 'BPCHCD' : '$f9', # Battery Protection Charge-High
- 'BPDHCD' : '$f8', # Battery Protection Discharge-H
- 'BPCOCD' : '$f7', # Battery Protection Charge-Over
- 'BPDOCD' : '$f6', # Battery Protection Discharge-O
- 'BPSCD' : '$f5', # Battery Protection Short-Circu
- 'BPIFR' : '$f3', # Battery Protection Interrupt F
- 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
- 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
- 'BPIFR_COCIF': '$4', # Charge Over-current Protection
- 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
- 'BPIFR_CHCIF': '$1', # Charge High-current Protection
- 'BPIMSK' : '$f2', # Battery Protection Interrupt M
- 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
- 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
- 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
- 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
- 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
-
-# Module CHARGER_DETECT
- 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
- 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
- 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
- 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
- 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
-
-# Module VOLTAGE_REGULATOR
- 'ROCR' : '$c8', # Regulator Operating Condition
- 'ROCR_ROCS': '$80', # ROC Status
- 'ROCR_ROCD': '$10', # ROC Disable
- 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
- 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
-
-# Module BANDGAP
- 'BGCSR' : '$d2', # Bandgap Control and Status Reg
- 'BGCSR_BGD': '$20', # Bandgap Disable
- 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
- 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
- 'BGCCR' : '$d0', # Bandgap Calibration Register
- 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_CKOE': '$20', # Clock Output Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_OCDRF': '$10', # OCD Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
- 'OSICSR' : '$37', # Oscillator Sampling Interface
- 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
- 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
- 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_PA1DID': '$2', # When this bit is written logic
- 'DIDR0_PA0DID': '$1', # When this bit is written logic
- 'PRR0' : '$64', # Power Reduction Register 0
- 'PRR0_PRTWI': '$40', # Power Reduction TWI
- 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
- 'PRR0_PRSPI': '$8', # Power reduction SPI
- 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
- 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
- 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
- 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
- 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
- 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
- 'TCCR0A_TCW0': '$80', # Timer/Counter Width
- 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
- 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
- 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
- 'TCCR0A_ICS0': '$8', # Input Capture Select
- 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
- 'TCNT0' : '$46', # Timer Counter 0 Bytes
- 'OCR0A' : '$48', # Output Compare Register 0A
- 'OCR0B' : '$49', # Output Compare Register B
- 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
- 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
- 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
- 'SPMCSR_LBSET': '$8', # Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16hvb/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16hvb/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16hvb/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvb/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/atmega16hvbrevb.frt b/amforth-6.5/avr8/devices/atmega16hvbrevb/atmega16hvbrevb.frt
deleted file mode 100644
index 77246ab..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/atmega16hvbrevb.frt
+++ /dev/null
@@ -1,33 +0,0 @@
-\ Partname: ATmega16HVBrevB
-\ generated automatically
-
-
-\ Interrupts
-&2 constant BPINTAddr \ Battery Protection Interrupt
-&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
-&6 constant INT0Addr \ External Interrupt Request 0
-&8 constant INT1Addr \ External Interrupt Request 1
-&10 constant INT2Addr \ External Interrupt Request 2
-&12 constant INT3Addr \ External Interrupt Request 3
-&14 constant PCINT0Addr \ Pin Change Interrupt 0
-&16 constant PCINT1Addr \ Pin Change Interrupt 1
-&18 constant WDTAddr \ Watchdog Timeout Interrupt
-&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
-&22 constant CHDETAddr \ Charger Detect
-&24 constant TIMER1_ICAddr \ Timer 1 Input capture
-&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer 1 overflow
-&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
-&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
-&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
-&42 constant TWIAddr \ Two-Wire Serial Interface
-&44 constant SPI_STCAddr \ SPI Serial transfer complete
-&46 constant VADCAddr \ Voltage ADC Conversion Complete
-&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.asm
deleted file mode 100644
index c9dcb8c..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega16HVBrevB
-; generated automatically, do not edit
-
-.nolist
- .include "m16HVBrevBdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Battery Protection Interrupt
-.org 4
- rcall isr ; Voltage regulator monitor interrupt
-.org 6
- rcall isr ; External Interrupt Request 0
-.org 8
- rcall isr ; External Interrupt Request 1
-.org 10
- rcall isr ; External Interrupt Request 2
-.org 12
- rcall isr ; External Interrupt Request 3
-.org 14
- rcall isr ; Pin Change Interrupt 0
-.org 16
- rcall isr ; Pin Change Interrupt 1
-.org 18
- rcall isr ; Watchdog Timeout Interrupt
-.org 20
- rcall isr ; Bandgap Buffer Short Circuit Detected
-.org 22
- rcall isr ; Charger Detect
-.org 24
- rcall isr ; Timer 1 Input capture
-.org 26
- rcall isr ; Timer 1 Compare Match A
-.org 28
- rcall isr ; Timer 1 Compare Match B
-.org 30
- rcall isr ; Timer 1 overflow
-.org 32
- rcall isr ; Timer 0 Input Capture
-.org 34
- rcall isr ; Timer 0 Comapre Match A
-.org 36
- rcall isr ; Timer 0 Compare Match B
-.org 38
- rcall isr ; Timer 0 Overflow
-.org 40
- rcall isr ; Two-Wire Bus Connect/Disconnect
-.org 42
- rcall isr ; Two-Wire Serial Interface
-.org 44
- rcall isr ; SPI Serial transfer complete
-.org 46
- rcall isr ; Voltage ADC Conversion Complete
-.org 48
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org 50
- rcall isr ; Coloumb Counter ADC Regular Current
-.org 52
- rcall isr ; Coloumb Counter ADC Accumulator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; SPM Ready
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 15
- .db "ATmega16HVBrevB",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.inc b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.inc
deleted file mode 100644
index 6765fb4..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-; Partname: ATmega16HVBrevB
-; generated automatically, no not edit
-
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.py b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.py
deleted file mode 100644
index 9f1a319..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.py
+++ /dev/null
@@ -1,342 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16HVBrevB
-
-MCUREGS = {
-# Interrupt Vectors
- 'BPINTAddr' : '#2', # Battery Protection Interrupt
- 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
- 'INT0Addr' : '#6', # External Interrupt Request 0
- 'INT1Addr' : '#8', # External Interrupt Request 1
- 'INT2Addr' : '#10', # External Interrupt Request 2
- 'INT3Addr' : '#12', # External Interrupt Request 3
- 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
- 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
- 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
- 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
- 'CHDETAddr' : '#22', # Charger Detect
- 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
- 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
- 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
- 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
- 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
- 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
- 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
- 'TWIAddr' : '#42', # Two-Wire Serial Interface
- 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
- 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
- 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
- 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
- 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPMAddr' : '#56', # SPM Ready
-
-# Module AD_CONVERTER
- 'VADMUX' : '$7c', # The VADC multiplexer Selection
- 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
- 'VADC' : '$78', # VADC Data Register Bytes
- 'VADCSR' : '$7a', # The VADC Control and Status re
- 'VADCSR_VADEN': '$8', # VADC Enable
- 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
- 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
- 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module FET
- 'FCSR' : '$f0', # FET Control and Status Registe
- 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
- 'FCSR_CPS': '$4', # Current Protection Status
- 'FCSR_DFE': '$2', # Discharge FET Enable
- 'FCSR_CFE': '$1', # Charge FET Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module COULOMB_COUNTER
- 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
- 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
- 'CADCSRA_CADPOL': '$40', #
- 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
- 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
- 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
- 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
- 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
- 'CADCSRB_CADACIE': '$40', #
- 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
- 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
- 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
- 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
- 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
- 'CADIC' : '$e4', # CC-ADC Instantaneous Current
- 'CADAC3' : '$e3', # ADC Accumulate Current
- 'CADAC2' : '$e2', # ADC Accumulate Current
- 'CADAC1' : '$e1', # ADC Accumulate Current
- 'CADAC0' : '$e0', # ADC Accumulate Current
- 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
- 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
-
-# Module TWI
- 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
- 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
- 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
- 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
-
-# Module TIMER_COUNTER_1
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_CS': '$7', # Clock Select1 bis
- 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
- 'TCCR1A_TCW1': '$80', # Timer/Counter Width
- 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
- 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
- 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
- 'TCCR1A_ICS1': '$8', # Input Capture Select
- 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
- 'TCNT1' : '$84', # Timer Counter 1 Bytes
- 'OCR1A' : '$88', # Output Compare Register 1A
- 'OCR1B' : '$89', # Output Compare Register B
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module CELL_BALANCING
- 'CBCR' : '$f1', # Cell Balancing Control Registe
- 'CBCR_CBE': '$f', # Cell Balancing Enables
-
-# Module BATTERY_PROTECTION
- 'BPPLR' : '$fe', # Battery Protection Parameter L
- 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
- 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
- 'BPCR' : '$fd', # Battery Protection Control Reg
- 'BPCR_EPID': '$20', # External Protection Input Disa
- 'BPCR_SCD': '$10', # Short Circuit Protection Disab
- 'BPCR_DOCD': '$8', # Discharge Over-current Protect
- 'BPCR_COCD': '$4', # Charge Over-current Protection
- 'BPCR_DHCD': '$2', # Discharge High-current Protect
- 'BPCR_CHCD': '$1', # Charge High-current Protection
- 'BPHCTR' : '$fc', # Battery Protection Short-curre
- 'BPOCTR' : '$fb', # Battery Protection Over-curren
- 'BPSCTR' : '$fa', # Battery Protection Short-curre
- 'BPCHCD' : '$f9', # Battery Protection Charge-High
- 'BPDHCD' : '$f8', # Battery Protection Discharge-H
- 'BPCOCD' : '$f7', # Battery Protection Charge-Over
- 'BPDOCD' : '$f6', # Battery Protection Discharge-O
- 'BPSCD' : '$f5', # Battery Protection Short-Circu
- 'BPIFR' : '$f3', # Battery Protection Interrupt F
- 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
- 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
- 'BPIFR_COCIF': '$4', # Charge Over-current Protection
- 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
- 'BPIFR_CHCIF': '$1', # Charge High-current Protection
- 'BPIMSK' : '$f2', # Battery Protection Interrupt M
- 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
- 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
- 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
- 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
- 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
-
-# Module CHARGER_DETECT
- 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
- 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
- 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
- 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
- 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
-
-# Module VOLTAGE_REGULATOR
- 'ROCR' : '$c8', # Regulator Operating Condition
- 'ROCR_ROCS': '$80', # ROC Status
- 'ROCR_ROCD': '$10', # ROC Disable
- 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
- 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
-
-# Module BANDGAP
- 'BGCSR' : '$d2', # Bandgap Control and Status Reg
- 'BGCSR_BGD': '$20', # Bandgap Disable
- 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
- 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
- 'BGCCR' : '$d0', # Bandgap Calibration Register
- 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_CKOE': '$20', # Clock Output Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_OCDRF': '$10', # OCD Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
- 'OSICSR' : '$37', # Oscillator Sampling Interface
- 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
- 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
- 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_PA1DID': '$2', # When this bit is written logic
- 'DIDR0_PA0DID': '$1', # When this bit is written logic
- 'PRR0' : '$64', # Power Reduction Register 0
- 'PRR0_PRTWI': '$40', # Power Reduction TWI
- 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
- 'PRR0_PRSPI': '$8', # Power reduction SPI
- 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
- 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
- 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
- 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
- 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
- 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
- 'TCCR0A_TCW0': '$80', # Timer/Counter Width
- 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
- 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
- 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
- 'TCCR0A_ICS0': '$8', # Input Capture Select
- 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
- 'TCNT0' : '$46', # Timer Counter 0 Bytes
- 'OCR0A' : '$48', # Output Compare Register 0A
- 'OCR0B' : '$49', # Output Compare Register B
- 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
- 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
- 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
- 'SPMCSR_LBSET': '$8', # Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16m1/atmega16m1.frt b/amforth-6.5/avr8/devices/atmega16m1/atmega16m1.frt
deleted file mode 100644
index 3d6977c..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/atmega16m1.frt
+++ /dev/null
@@ -1,513 +0,0 @@
-\ Partname: ATmega16M1
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVFG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register Flags
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
- $08 constant CANGIT_SERG \ Stuff Error General Flag
- $04 constant CANGIT_CERG \ CRC Error General Flag
- $02 constant CANGIT_FERG \ Form Error General Flag
- $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register 2
- $3F constant CANEN2_ENMOB \ Enable MObs
-&221 constant CANEN1 \ Enable MOb Register 1(empty)
-&222 constant CANIE2 \ Enable Interrupt MOb Register 2
- $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
-&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
- $3F constant CANSIT2_SIT \ Status of Interrupt MObs
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
-&226 constant CANBT1 \ CAN Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ CAN Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
- $0E constant CANBT2_PRS \ Propagation Time Segment bits
-&228 constant CANBT3 \ CAN Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
- $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
- $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
- $0F constant CANHPMOB_CGP \ CAN General Purpose bits
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
- $07 constant CANPAGE_INDX \ Data Buffer Index bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
- $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
- $20 constant CANSTMOB_RXOK \ Receive OK on MOb
- $10 constant CANSTMOB_BERR \ Bit Error on MOb
- $08 constant CANSTMOB_SERR \ Stuff Error on MOb
- $04 constant CANSTMOB_CERR \ CRC Error on MOb
- $02 constant CANSTMOB_FERR \ Form Error on MOb
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
- $F8 constant CANIDT4_IDT \
- $04 constant CANIDT4_RTRTAG \
- $02 constant CANIDT4_RB1TAG \
- $01 constant CANIDT4_RB0TAG \
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-\ ANALOG_COMPARATOR
-&148 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
- $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&149 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&150 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&151 constant AC3CON \ Analog Comparator 3 Control Register
- $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
- $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&146 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&145 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&144 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $40 constant PRR_PRCAN \ Power Reduction CAN
- $20 constant PRR_PRPSC \ Power Reduction PSC
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRLIN \ Power Reduction LIN UART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ISRCEN \ Current Source Enable
- $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
- $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
- $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
- $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
- $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
- $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
- $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
- $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
-&117 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
- $07 constant AMP0CSR_AMP0TS \
-&118 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
- $07 constant AMP1CSR_AMP1TS \
-&119 constant AMP2CSR \
- $80 constant AMP2CSR_AMP2EN \
- $40 constant AMP2CSR_AMP2IS \
- $30 constant AMP2CSR_AMP2G \
- $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
- $07 constant AMP2CSR_AMP2TS \
-\ LINUART
-&200 constant LINCR \ LIN Control Register
- $80 constant LINCR_LSWRES \ Software Reset
- $40 constant LINCR_LIN13 \ LIN Standard
- $30 constant LINCR_LCONF \ LIN Configuration bits
- $08 constant LINCR_LENA \ LIN or UART Enable
- $07 constant LINCR_LCMD \ LIN Command and Mode bits
-&201 constant LINSIR \ LIN Status and Interrupt Register
- $E0 constant LINSIR_LIDST \ Identifier Status bits
- $10 constant LINSIR_LBUSY \ Busy Signal
- $08 constant LINSIR_LERR \ Error Interrupt
- $04 constant LINSIR_LIDOK \ Identifier Interrupt
- $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
- $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
-&202 constant LINENIR \ LIN Enable Interrupt Register
- $08 constant LINENIR_LENERR \ Enable Error Interrupt
- $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
- $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
- $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
-&203 constant LINERR \ LIN Error Register
- $80 constant LINERR_LABORT \ Abort Flag
- $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
- $20 constant LINERR_LOVERR \ Overrun Error Flag
- $10 constant LINERR_LFERR \ Framing Error Flag
- $08 constant LINERR_LSERR \ Synchronization Error Flag
- $04 constant LINERR_LPERR \ Parity Error Flag
- $02 constant LINERR_LCERR \ Checksum Error Flag
- $01 constant LINERR_LBERR \ Bit Error Flag
-&204 constant LINBTR \ LIN Bit Timing Register
- $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
- $3F constant LINBTR_LBT \ LIN Bit Timing bits
-&205 constant LINBRRL \ LIN Baud Rate Low Register
- $FF constant LINBRRL_LDIV \
-&206 constant LINBRRH \ LIN Baud Rate High Register
- $0F constant LINBRRH_LDIV \
-&207 constant LINDLR \ LIN Data Length Register
- $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
- $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
-&208 constant LINIDR \ LIN Identifier Register
- $C0 constant LINIDR_LP \ Parity bits
- $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
-&209 constant LINSEL \ LIN Data Buffer Selection Register
- $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
- $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
-&210 constant LINDAT \ LIN Data Register
- $FF constant LINDAT_LDATA \
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK3 \ Pin Change Mask Register 3
- $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&106 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \
- $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC
-&188 constant PIFR \ PSC Interrupt Flag Register
- $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
- $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
-&187 constant PIM \ PSC Interrupt Mask Register
- $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
- $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
-&186 constant PMIC2 \ PSC Module 2 Input Control Register
- $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
- $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
- $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
- $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
- $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
- $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
-&185 constant PMIC1 \ PSC Module 1 Input Control Register
- $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
- $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
- $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
- $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
- $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
- $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
-&184 constant PMIC0 \ PSC Module 0 Input Control Register
- $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
- $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
- $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
- $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
- $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
- $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
-&183 constant PCTL \ PSC Control Register
- $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
- $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
- $02 constant PCTL_PCCYC \ PSC Complete Cycle
- $01 constant PCTL_PRUN \ PSC Run
-&182 constant POC \ PSC Output Configuration
- $20 constant POC_POEN2B \ PSC Output 2B Enable
- $10 constant POC_POEN2A \ PSC Output 2A Enable
- $08 constant POC_POEN1B \ PSC Output 1B Enable
- $04 constant POC_POEN1A \ PSC Output 1A Enable
- $02 constant POC_POEN0B \ PSC Output 0B Enable
- $01 constant POC_POEN0A \ PSC Output 0A Enable
-&181 constant PCNF \ PSC Configuration Register
- $20 constant PCNF_PULOCK \ PSC Update Lock
- $10 constant PCNF_PMODE \ PSC Mode
- $08 constant PCNF_POPB \ PSC Output B Polarity
- $04 constant PCNF_POPA \ PSC Output A Polarity
-&180 constant PSYNC \ PSC Synchro Configuration
- $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
- $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
- $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
-&178 constant POCR_RB \ PSC Output Compare RB Register
-&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
-&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
-&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
-&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
-&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
-&166 constant POCR1SA \ PSC Output Compare SA Register
-&164 constant POCR0SB \ PSC Output Compare SB Register
-&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
-&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
-
-\ Interrupts
-&2 constant ANACOMP0Addr \ Analog Comparator 0
-&4 constant ANACOMP1Addr \ Analog Comparator 1
-&6 constant ANACOMP2Addr \ Analog Comparator 2
-&8 constant ANACOMP3Addr \ Analog Comparator 3
-&10 constant PSC_FAULTAddr \ PSC Fault
-&12 constant PSC_ECAddr \ PSC End of Cycle
-&14 constant INT0Addr \ External Interrupt Request 0
-&16 constant INT1Addr \ External Interrupt Request 1
-&18 constant INT2Addr \ External Interrupt Request 2
-&20 constant INT3Addr \ External Interrupt Request 3
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
-&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
-&38 constant CAN_TOVFAddr \ CAN Timer Overflow
-&40 constant LIN_TCAddr \ LIN Transfer Complete
-&42 constant LIN_ERRAddr \ LIN Error
-&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&54 constant ADCAddr \ ADC Conversion Complete
-&56 constant WDTAddr \ Watchdog Time-Out Interrupt
-&58 constant EE_READYAddr \ EEPROM Ready
-&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega16m1/device.asm b/amforth-6.5/avr8/devices/atmega16m1/device.asm
deleted file mode 100644
index f214c92..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega16M1
-; generated automatically, do not edit
-
-.nolist
- .include "m16M1def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CAN = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_LINUART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Analog Comparator 0
-.org 4
- rcall isr ; Analog Comparator 1
-.org 6
- rcall isr ; Analog Comparator 2
-.org 8
- rcall isr ; Analog Comparator 3
-.org 10
- rcall isr ; PSC Fault
-.org 12
- rcall isr ; PSC End of Cycle
-.org 14
- rcall isr ; External Interrupt Request 0
-.org 16
- rcall isr ; External Interrupt Request 1
-.org 18
- rcall isr ; External Interrupt Request 2
-.org 20
- rcall isr ; External Interrupt Request 3
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter1 Compare Match B
-.org 28
- rcall isr ; Timer1/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match A
-.org 32
- rcall isr ; Timer/Counter0 Compare Match B
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN MOB, Burst, General Errors
-.org 38
- rcall isr ; CAN Timer Overflow
-.org 40
- rcall isr ; LIN Transfer Complete
-.org 42
- rcall isr ; LIN Error
-.org 44
- rcall isr ; Pin Change Interrupt Request 0
-.org 46
- rcall isr ; Pin Change Interrupt Request 1
-.org 48
- rcall isr ; Pin Change Interrupt Request 2
-.org 50
- rcall isr ; Pin Change Interrupt Request 3
-.org 52
- rcall isr ; SPI Serial Transfer Complete
-.org 54
- rcall isr ; ADC Conversion Complete
-.org 56
- rcall isr ; Watchdog Time-Out Interrupt
-.org 58
- rcall isr ; EEPROM Ready
-.org 60
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega16M1"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16m1/device.inc b/amforth-6.5/avr8/devices/atmega16m1/device.inc
deleted file mode 100644
index 27ba973..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/device.inc
+++ /dev/null
@@ -1,1734 +0,0 @@
-; Partname: ATmega16M1
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register Flags
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 2
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 1(empty)
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 2
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 1 (empty)
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 2
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 1 (empty)
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 3 Control Register
-VE_AC3CON:
- .dw $ff06
- .db "AC3CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3CON
-XT_AC3CON:
- .dw PFA_DOVARIABLE
-PFA_AC3CON:
- .dw 151
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 144
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP2CSR:
- .dw $ff07
- .db "AMP2CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP2CSR
-XT_AMP2CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP2CSR:
- .dw 119
-
-.endif
-.if WANT_LINUART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Control Register
-VE_LINCR:
- .dw $ff05
- .db "LINCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINCR
-XT_LINCR:
- .dw PFA_DOVARIABLE
-PFA_LINCR:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Status and Interrupt Register
-VE_LINSIR:
- .dw $ff06
- .db "LINSIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSIR
-XT_LINSIR:
- .dw PFA_DOVARIABLE
-PFA_LINSIR:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Enable Interrupt Register
-VE_LINENIR:
- .dw $ff07
- .db "LINENIR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINENIR
-XT_LINENIR:
- .dw PFA_DOVARIABLE
-PFA_LINENIR:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Error Register
-VE_LINERR:
- .dw $ff06
- .db "LINERR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINERR
-XT_LINERR:
- .dw PFA_DOVARIABLE
-PFA_LINERR:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Bit Timing Register
-VE_LINBTR:
- .dw $ff06
- .db "LINBTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBTR
-XT_LINBTR:
- .dw PFA_DOVARIABLE
-PFA_LINBTR:
- .dw 204
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate Low Register
-VE_LINBRRL:
- .dw $ff07
- .db "LINBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRL
-XT_LINBRRL:
- .dw PFA_DOVARIABLE
-PFA_LINBRRL:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate High Register
-VE_LINBRRH:
- .dw $ff07
- .db "LINBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRH
-XT_LINBRRH:
- .dw PFA_DOVARIABLE
-PFA_LINBRRH:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Length Register
-VE_LINDLR:
- .dw $ff06
- .db "LINDLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDLR
-XT_LINDLR:
- .dw PFA_DOVARIABLE
-PFA_LINDLR:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Identifier Register
-VE_LINIDR:
- .dw $ff06
- .db "LINIDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINIDR
-XT_LINIDR:
- .dw PFA_DOVARIABLE
-PFA_LINIDR:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Buffer Selection Register
-VE_LINSEL:
- .dw $ff06
- .db "LINSEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSEL
-XT_LINSEL:
- .dw PFA_DOVARIABLE
-PFA_LINSEL:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Register
-VE_LINDAT:
- .dw $ff06
- .db "LINDAT"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDAT
-XT_LINDAT:
- .dw PFA_DOVARIABLE
-PFA_LINDAT:
- .dw 210
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Interrupt Flag Register
-VE_PIFR:
- .dw $ff04
- .db "PIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR
-XT_PIFR:
- .dw PFA_DOVARIABLE
-PFA_PIFR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Interrupt Mask Register
-VE_PIM:
- .dw $ff03
- .db "PIM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM
-XT_PIM:
- .dw PFA_DOVARIABLE
-PFA_PIM:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Input Control Register
-VE_PMIC2:
- .dw $ff05
- .db "PMIC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC2
-XT_PMIC2:
- .dw PFA_DOVARIABLE
-PFA_PMIC2:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Input Control Register
-VE_PMIC1:
- .dw $ff05
- .db "PMIC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC1
-XT_PMIC1:
- .dw PFA_DOVARIABLE
-PFA_PMIC1:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Input Control Register
-VE_PMIC0:
- .dw $ff05
- .db "PMIC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC0
-XT_PMIC0:
- .dw PFA_DOVARIABLE
-PFA_PMIC0:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Control Register
-VE_PCTL:
- .dw $ff04
- .db "PCTL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL
-XT_PCTL:
- .dw PFA_DOVARIABLE
-PFA_PCTL:
- .dw 183
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Configuration
-VE_POC:
- .dw $ff03
- .db "POC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POC
-XT_POC:
- .dw PFA_DOVARIABLE
-PFA_POC:
- .dw 182
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Configuration Register
-VE_PCNF:
- .dw $ff04
- .db "PCNF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF
-XT_PCNF:
- .dw PFA_DOVARIABLE
-PFA_PCNF:
- .dw 181
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Synchro Configuration
-VE_PSYNC:
- .dw $ff05
- .db "PSYNC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSYNC
-XT_PSYNC:
- .dw PFA_DOVARIABLE
-PFA_PSYNC:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare RB Register
-VE_POCR_RB:
- .dw $ff07
- .db "POCR_RB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR_RB
-XT_POCR_RB:
- .dw PFA_DOVARIABLE
-PFA_POCR_RB:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare SB Register
-VE_POCR2SB:
- .dw $ff07
- .db "POCR2SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2SB
-XT_POCR2SB:
- .dw PFA_DOVARIABLE
-PFA_POCR2SB:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare RA Register
-VE_POCR2RA:
- .dw $ff07
- .db "POCR2RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2RA
-XT_POCR2RA:
- .dw PFA_DOVARIABLE
-PFA_POCR2RA:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare SA Register
-VE_POCR2SA:
- .dw $ff07
- .db "POCR2SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2SA
-XT_POCR2SA:
- .dw PFA_DOVARIABLE
-PFA_POCR2SA:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Output Compare SB Register
-VE_POCR1SB:
- .dw $ff07
- .db "POCR1SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1SB
-XT_POCR1SB:
- .dw PFA_DOVARIABLE
-PFA_POCR1SB:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Output Compare RA Register
-VE_POCR1RA:
- .dw $ff07
- .db "POCR1RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1RA
-XT_POCR1RA:
- .dw PFA_DOVARIABLE
-PFA_POCR1RA:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare SA Register
-VE_POCR1SA:
- .dw $ff07
- .db "POCR1SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1SA
-XT_POCR1SA:
- .dw PFA_DOVARIABLE
-PFA_POCR1SA:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare SB Register
-VE_POCR0SB:
- .dw $ff07
- .db "POCR0SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0SB
-XT_POCR0SB:
- .dw PFA_DOVARIABLE
-PFA_POCR0SB:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Output Compare RA Register
-VE_POCR0RA:
- .dw $ff07
- .db "POCR0RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0RA
-XT_POCR0RA:
- .dw PFA_DOVARIABLE
-PFA_POCR0RA:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Output Compare SA Register
-VE_POCR0SA:
- .dw $ff07
- .db "POCR0SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0SA
-XT_POCR0SA:
- .dw PFA_DOVARIABLE
-PFA_POCR0SA:
- .dw 160
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16m1/device.py b/amforth-6.5/avr8/devices/atmega16m1/device.py
deleted file mode 100644
index a25c529..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/device.py
+++ /dev/null
@@ -1,537 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16M1
-
-MCUREGS = {
-# Interrupt Vectors
- 'ANACOMP0Addr' : '#2', # Analog Comparator 0
- 'ANACOMP1Addr' : '#4', # Analog Comparator 1
- 'ANACOMP2Addr' : '#6', # Analog Comparator 2
- 'ANACOMP3Addr' : '#8', # Analog Comparator 3
- 'PSC_FAULTAddr' : '#10', # PSC Fault
- 'PSC_ECAddr' : '#12', # PSC End of Cycle
- 'INT0Addr' : '#14', # External Interrupt Request 0
- 'INT1Addr' : '#16', # External Interrupt Request 1
- 'INT2Addr' : '#18', # External Interrupt Request 2
- 'INT3Addr' : '#20', # External Interrupt Request 3
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
- 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
- 'LIN_TCAddr' : '#40', # LIN Transfer Complete
- 'LIN_ERRAddr' : '#42', # LIN Error
- 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
- 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
- 'ADCAddr' : '#54', # ADC Conversion Complete
- 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
- 'EE_READYAddr' : '#58', # EEPROM Ready
- 'SPM_READYAddr' : '#60', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVFG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
- 'CANGIT_SERG': '$8', # Stuff Error General Flag
- 'CANGIT_CERG': '$4', # CRC Error General Flag
- 'CANGIT_FERG': '$2', # Form Error General Flag
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register 2
- 'CANEN2_ENMOB': '$3f', # Enable MObs
- 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # CAN Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # CAN Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
- 'CANBT2_PRS': '$e', # Propagation Time Segment bits
- 'CANBT3' : '$e4', # CAN Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
- 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
- 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
- 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
- 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
- 'CANSTMOB_BERR': '$10', # Bit Error on MOb
- 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
- 'CANSTMOB_CERR': '$4', # CRC Error on MOb
- 'CANSTMOB_FERR': '$2', # Form Error on MOb
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT4_IDT': '$f8', #
- 'CANIDT4_RTRTAG': '$4', #
- 'CANIDT4_RB1TAG': '$2', #
- 'CANIDT4_RB0TAG': '$1', #
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$94', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$95', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$96', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'AC3CON' : '$97', # Analog Comparator 3 Control Re
- 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
- 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$92', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$91', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$90', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRCAN': '$40', # Power Reduction CAN
- 'PRR_PRPSC': '$20', # Power Reduction PSC
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRLIN': '$2', # Power Reduction LIN UART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ISRCEN': '$40', # Current Source Enable
- 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
- 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
- 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
- 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
- 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
- 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
- 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
- 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
- 'AMP0CSR' : '$75', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
- 'AMP0CSR_AMP0TS': '$7', #
- 'AMP1CSR' : '$76', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
- 'AMP1CSR_AMP1TS': '$7', #
- 'AMP2CSR' : '$77', #
- 'AMP2CSR_AMP2EN': '$80', #
- 'AMP2CSR_AMP2IS': '$40', #
- 'AMP2CSR_AMP2G': '$30', #
- 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
- 'AMP2CSR_AMP2TS': '$7', #
-
-# Module LINUART
- 'LINCR' : '$c8', # LIN Control Register
- 'LINCR_LSWRES': '$80', # Software Reset
- 'LINCR_LIN13': '$40', # LIN Standard
- 'LINCR_LCONF': '$30', # LIN Configuration bits
- 'LINCR_LENA': '$8', # LIN or UART Enable
- 'LINCR_LCMD': '$7', # LIN Command and Mode bits
- 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
- 'LINSIR_LIDST': '$e0', # Identifier Status bits
- 'LINSIR_LBUSY': '$10', # Busy Signal
- 'LINSIR_LERR': '$8', # Error Interrupt
- 'LINSIR_LIDOK': '$4', # Identifier Interrupt
- 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
- 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
- 'LINENIR' : '$ca', # LIN Enable Interrupt Register
- 'LINENIR_LENERR': '$8', # Enable Error Interrupt
- 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
- 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
- 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
- 'LINERR' : '$cb', # LIN Error Register
- 'LINERR_LABORT': '$80', # Abort Flag
- 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
- 'LINERR_LOVERR': '$20', # Overrun Error Flag
- 'LINERR_LFERR': '$10', # Framing Error Flag
- 'LINERR_LSERR': '$8', # Synchronization Error Flag
- 'LINERR_LPERR': '$4', # Parity Error Flag
- 'LINERR_LCERR': '$2', # Checksum Error Flag
- 'LINERR_LBERR': '$1', # Bit Error Flag
- 'LINBTR' : '$cc', # LIN Bit Timing Register
- 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
- 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
- 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
- 'LINBRRL_LDIV': '$ff', #
- 'LINBRRH' : '$ce', # LIN Baud Rate High Register
- 'LINBRRH_LDIV': '$f', #
- 'LINDLR' : '$cf', # LIN Data Length Register
- 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
- 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
- 'LINIDR' : '$d0', # LIN Identifier Register
- 'LINIDR_LP': '$c0', # Parity bits
- 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
- 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
- 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
- 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
- 'LINDAT' : '$d2', # LIN Data Register
- 'LINDAT_LDATA': '$ff', #
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
- 'PCMSK3' : '$6d', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
- 'PCMSK2' : '$6c', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6b', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6a', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC
- 'PIFR' : '$bc', # PSC Interrupt Flag Register
- 'PIFR_PEV': '$e', # PSC External Event 2 Interrupt
- 'PIFR_PEOP': '$1', # PSC End of Cycle Interrupt
- 'PIM' : '$bb', # PSC Interrupt Mask Register
- 'PIM_PEVE': '$e', # External Event 2 Interrupt Ena
- 'PIM_PEOPE': '$1', # PSC End of Cycle Interrupt Ena
- 'PMIC2' : '$ba', # PSC Module 2 Input Control Reg
- 'PMIC2_POVEN2': '$80', # PSC Module 2 Overlap Enable
- 'PMIC2_PISEL2': '$40', # PSC Module 2 Input Select
- 'PMIC2_PELEV2': '$20', # PSC Module 2 Input Level Selec
- 'PMIC2_PFLTE2': '$10', # PSC Module 2 Input Filter Enab
- 'PMIC2_PAOC2': '$8', # PSC Module 2 Asynchronous Outp
- 'PMIC2_PRFM2': '$7', # PSC Module 2 Input Mode bits
- 'PMIC1' : '$b9', # PSC Module 1 Input Control Reg
- 'PMIC1_POVEN1': '$80', # PSC Module 1 Overlap Enable
- 'PMIC1_PISEL1': '$40', # PSC Module 1 Input Select
- 'PMIC1_PELEV1': '$20', # PSC Module 1 Input Level Selec
- 'PMIC1_PFLTE1': '$10', # PSC Module 1 Input Filter Enab
- 'PMIC1_PAOC1': '$8', # PSC Module 1 Asynchronous Outp
- 'PMIC1_PRFM1': '$7', # PSC Module 1 Input Mode bits
- 'PMIC0' : '$b8', # PSC Module 0 Input Control Reg
- 'PMIC0_POVEN0': '$80', # PSC Module 0 Overlap Enable
- 'PMIC0_PISEL0': '$40', # PSC Module 0 Input Select
- 'PMIC0_PELEV0': '$20', # PSC Module 0 Input Level Selec
- 'PMIC0_PFLTE0': '$10', # PSC Module 0 Input Filter Enab
- 'PMIC0_PAOC0': '$8', # PSC Module 0 Asynchronous Outp
- 'PMIC0_PRFM0': '$7', # PSC Module 0 Input Mode bits
- 'PCTL' : '$b7', # PSC Control Register
- 'PCTL_PPRE': '$c0', # PSC Prescaler Select bits
- 'PCTL_PCLKSEL': '$20', # PSC Input Clock Select
- 'PCTL_PCCYC': '$2', # PSC Complete Cycle
- 'PCTL_PRUN': '$1', # PSC Run
- 'POC' : '$b6', # PSC Output Configuration
- 'POC_POEN2B': '$20', # PSC Output 2B Enable
- 'POC_POEN2A': '$10', # PSC Output 2A Enable
- 'POC_POEN1B': '$8', # PSC Output 1B Enable
- 'POC_POEN1A': '$4', # PSC Output 1A Enable
- 'POC_POEN0B': '$2', # PSC Output 0B Enable
- 'POC_POEN0A': '$1', # PSC Output 0A Enable
- 'PCNF' : '$b5', # PSC Configuration Register
- 'PCNF_PULOCK': '$20', # PSC Update Lock
- 'PCNF_PMODE': '$10', # PSC Mode
- 'PCNF_POPB': '$8', # PSC Output B Polarity
- 'PCNF_POPA': '$4', # PSC Output A Polarity
- 'PSYNC' : '$b4', # PSC Synchro Configuration
- 'PSYNC_PSYNC2': '$30', # Selection of Synchronization O
- 'PSYNC_PSYNC1': '$c', # Selection of Synchronization O
- 'PSYNC_PSYNC0': '$3', # Selection of Synchronization O
- 'POCR_RB' : '$b2', # PSC Output Compare RB Register
- 'POCR2SB' : '$b0', # PSC Module 2 Output Compare SB
- 'POCR2RA' : '$ae', # PSC Module 2 Output Compare RA
- 'POCR2SA' : '$ac', # PSC Module 2 Output Compare SA
- 'POCR1SB' : '$aa', # PSC Module 1 Output Compare SB
- 'POCR1RA' : '$a8', # PSC Module 1 Output Compare RA
- 'POCR1SA' : '$a6', # PSC Output Compare SA Register
- 'POCR0SB' : '$a4', # PSC Output Compare SB Register
- 'POCR0RA' : '$a2', # PSC Module 0 Output Compare RA
- 'POCR0SA' : '$a0', # PSC Module 0 Output Compare SA
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16m1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16m1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16m1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega16m1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u2/atmega16u2.frt b/amforth-6.5/avr8/devices/atmega16u2/atmega16u2.frt
deleted file mode 100644
index 89a6927..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/atmega16u2.frt
+++ /dev/null
@@ -1,367 +0,0 @@
-\ Partname: ATmega16U2
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_DEVICE
-&244 constant UEINT \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $1F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
-&99 constant REGCR \ Regulator Control Register
- $01 constant REGCR_REGDIS \
-\ PS2
-&251 constant UPOE \
- $C0 constant UPOE_UPWE \
- $30 constant UPOE_UPDRV \
- $08 constant UPOE_SCKI \
- $04 constant UPOE_DATAI \
- $02 constant UPOE_DPI \
- $01 constant UPOE_DMI \
-&250 constant PS2CON \ PS2 Pad Enable register
- $01 constant PS2CON_PS2EN \ Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $20 constant MCUSR_USBRF \ USB reset flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
-&210 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&209 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&208 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-&81 constant DWDR \ debugWire communication register
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $1F constant PCMSK1_PCINT \
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&203 constant UCSR1D \ USART Control and Status Register D
- $02 constant UCSR1D_CTSEN \ CTS Enable
- $01 constant UCSR1D_RTSEN \ RTS Enable
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-&98 constant WDTCKD \ Watchdog Timer Clock Divider
- $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
- $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
- $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTC
-&40 constant PORTC \ Port C Data Register
- $F0 constant PORTC_PORTC \ Port C Data Register bits
- $07 constant PORTC_PORTC \ Port C Data Register bits
-&39 constant DDRC \ Port C Data Direction Register
- $F0 constant DDRC_DDC \ Port C Data Direction Register bits
- $07 constant DDRC_DDC \ Port C Data Direction Register bits
-&38 constant PINC \ Port C Input Pins
- $F0 constant PINC_PINC \ Port C Input Pins bits
- $07 constant PINC_PINC \ Port C Input Pins bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant USB_GENAddr \ USB General Interrupt Request
-&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&26 constant WDTAddr \ Watchdog Time-out Interrupt
-&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
-&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
-&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
-&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
-&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&46 constant USART1__RXAddr \ USART1, Rx Complete
-&48 constant USART1__UDREAddr \ USART1 Data register Empty
-&50 constant USART1__TXAddr \ USART1, Tx Complete
-&52 constant ANALOG_COMPAddr \ Analog Comparator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega16u2/device.asm b/amforth-6.5/avr8/devices/atmega16u2/device.asm
deleted file mode 100644
index a70caa8..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: ATmega16U2
-; generated automatically, do not edit
-
-.nolist
- .include "m16U2def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_PS2 = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTC = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; USB General Interrupt Request
-.org 24
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 26
- rcall isr ; Watchdog Time-out Interrupt
-.org 28
- rcall isr ; Timer/Counter2 Capture Event
-.org 30
- rcall isr ; Timer/Counter2 Compare Match B
-.org 32
- rcall isr ; Timer/Counter2 Compare Match B
-.org 34
- rcall isr ; Timer/Counter2 Compare Match C
-.org 36
- rcall isr ; Timer/Counter1 Overflow
-.org 38
- rcall isr ; Timer/Counter0 Compare Match A
-.org 40
- rcall isr ; Timer/Counter0 Compare Match B
-.org 42
- rcall isr ; Timer/Counter0 Overflow
-.org 44
- rcall isr ; SPI Serial Transfer Complete
-.org 46
- rcall isr ; USART1, Rx Complete
-.org 48
- rcall isr ; USART1 Data register Empty
-.org 50
- rcall isr ; USART1, Tx Complete
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 10
- .db "ATmega16U2"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16u2/device.inc b/amforth-6.5/avr8/devices/atmega16u2/device.inc
deleted file mode 100644
index 667ef57..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/device.inc
+++ /dev/null
@@ -1,1155 +0,0 @@
-; Partname: ATmega16U2
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Control Register
-VE_REGCR:
- .dw $ff05
- .db "REGCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_REGCR
-XT_REGCR:
- .dw PFA_DOVARIABLE
-PFA_REGCR:
- .dw 99
-
-.endif
-.if WANT_PS2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPOE:
- .dw $ff04
- .db "UPOE"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPOE
-XT_UPOE:
- .dw PFA_DOVARIABLE
-PFA_UPOE:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PS2 Pad Enable register
-VE_PS2CON:
- .dw $ff06
- .db "PS2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_PS2CON
-XT_PS2CON:
- .dw PFA_DOVARIABLE
-PFA_PS2CON:
- .dw 250
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; debugWire communication register
-VE_DWDR:
- .dw $ff04
- .db "DWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_DWDR
-XT_DWDR:
- .dw PFA_DOVARIABLE
-PFA_DWDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register D
-VE_UCSR1D:
- .dw $ff06
- .db "UCSR1D"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1D
-XT_UCSR1D:
- .dw PFA_DOVARIABLE
-PFA_UCSR1D:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Clock Divider
-VE_WDTCKD:
- .dw $ff06
- .db "WDTCKD"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCKD
-XT_WDTCKD:
- .dw PFA_DOVARIABLE
-PFA_WDTCKD:
- .dw 98
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16u2/device.py b/amforth-6.5/avr8/devices/atmega16u2/device.py
deleted file mode 100644
index 592910d..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/device.py
+++ /dev/null
@@ -1,387 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16U2
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'USB_GENAddr' : '#22', # USB General Interrupt Request
- 'USB_COMAddr' : '#24', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#26', # Watchdog Time-out Interrupt
- 'TIMER1_CAPTAddr' : '#28', # Timer/Counter2 Capture Event
- 'TIMER1_COMPAAddr' : '#30', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPBAddr' : '#32', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPCAddr' : '#34', # Timer/Counter2 Compare Match C
- 'TIMER1_OVFAddr' : '#36', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#38', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#40', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#42', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#44', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#46', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#48', # USART1 Data register Empty
- 'USART1_TXAddr' : '#50', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#52', # Analog Comparator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPM_READYAddr' : '#56', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$1f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_RSTCPU': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_FRZCLK': '$20', #
- 'REGCR' : '$63', # Regulator Control Register
- 'REGCR_REGDIS': '$1', #
-
-# Module PS2
- 'UPOE' : '$fb', #
- 'UPOE_UPWE': '$c0', #
- 'UPOE_UPDRV': '$30', #
- 'UPOE_SCKI': '$8', #
- 'UPOE_DATAI': '$4', #
- 'UPOE_DPI': '$2', #
- 'UPOE_DMI': '$1', #
- 'PS2CON' : '$fa', # PS2 Pad Enable register
- 'PS2CON_PS2EN': '$1', # Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_USBRF': '$20', # USB reset flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'CLKSTA' : '$d2', #
- 'CLKSTA_RCON': '$2', #
- 'CLKSTA_EXTON': '$1', #
- 'CLKSEL1' : '$d1', #
- 'CLKSEL1_RCCKSEL': '$f0', #
- 'CLKSEL1_EXCKSEL': '$f', #
- 'CLKSEL0' : '$d0', #
- 'CLKSEL0_RCSUT': '$c0', #
- 'CLKSEL0_EXSUT': '$30', #
- 'CLKSEL0_RCE': '$8', #
- 'CLKSEL0_EXTE': '$4', #
- 'CLKSEL0_CLKS': '$1', #
- 'DWDR' : '$51', # debugWire communication regist
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$1f', #
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UCSR1D' : '$cb', # USART Control and Status Regis
- 'UCSR1D_CTSEN': '$2', # CTS Enable
- 'UCSR1D_RTSEN': '$1', # RTS Enable
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
- 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
- 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
- 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
- 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PORTC_PORTC': '$f0', # Port C Data Register bits
- 'PORTC_PORTC': '$7', # Port C Data Register bits
- 'DDRC' : '$27', # Port C Data Direction Register
- 'DDRC_DDC': '$f0', # Port C Data Direction Register
- 'DDRC_DDC': '$7', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
- 'PINC_PINC': '$f0', # Port C Input Pins bits
- 'PINC_PINC': '$7', # Port C Input Pins bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16u2/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16u2/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16u2/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega16u2/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u4/atmega16u4.frt b/amforth-6.5/avr8/devices/atmega16u4/atmega16u4.frt
deleted file mode 100644
index 44c50e1..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/atmega16u4.frt
+++ /dev/null
@@ -1,496 +0,0 @@
-\ Partname: ATmega16U4
-\ generated automatically
-
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
-\ TIMER_COUNTER_4
-&192 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $08 constant TCCR4A_FOC4A \ Force Output Compare Match 4A
- $04 constant TCCR4A_FOC4B \ Force Output Compare Match 4B
- $02 constant TCCR4A_PWM4A \
- $01 constant TCCR4A_PWM4B \
-&193 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_PWM4X \ PWM Inversion Mode
- $40 constant TCCR4B_PSR4 \ Prescaler Reset Timer/Counter 4
- $30 constant TCCR4B_DTPS4 \ Dead Time Prescaler Bits
- $0F constant TCCR4B_CS4 \ Clock Select Bits
-&194 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_COM4A1S \ Comparator A Output Mode
- $40 constant TCCR4C_COM4A0S \ Comparator A Output Mode
- $20 constant TCCR4C_COM4B1S \ Comparator B Output Mode
- $10 constant TCCR4C_COM4B0S \ Comparator B Output Mode
- $0C constant TCCR4C_COM4D \ Comparator D Output Mode
- $02 constant TCCR4C_FOC4D \ Force Output Compare Match 4D
- $01 constant TCCR4C_PWM4D \ Pulse Width Modulator D Enable
-&195 constant TCCR4D \ Timer/Counter 4 Control Register D
- $80 constant TCCR4D_FPIE4 \ Fault Protection Interrupt Enable
- $40 constant TCCR4D_FPEN4 \ Fault Protection Mode Enable
- $20 constant TCCR4D_FPNC4 \ Fault Protection Noise Canceler
- $10 constant TCCR4D_FPES4 \ Fault Protection Edge Select
- $08 constant TCCR4D_FPAC4 \ Fault Protection Analog Comparator Enable
- $04 constant TCCR4D_FPF4 \ Fault Protection Interrupt Flag
- $03 constant TCCR4D_WGM4 \ Waveform Generation Mode bits
-&196 constant TCCR4E \ Timer/Counter 4 Control Register E
- $80 constant TCCR4E_TLOCK4 \ Register Update Lock
- $40 constant TCCR4E_ENHC4 \ Enhanced Compare/PWM Mode
- $3F constant TCCR4E_OC4OE \ Output Compare Override Enable bit
-&190 constant TCNT4 \ Timer/Counter4 Low Bytes
-&191 constant TC4H \ Timer/Counter4
-&207 constant OCR4A \ Timer/Counter4 Output Compare Register A
-&208 constant OCR4B \ Timer/Counter4 Output Compare Register B
-&209 constant OCR4C \ Timer/Counter4 Output Compare Register C
-&210 constant OCR4D \ Timer/Counter4 Output Compare Register D
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $80 constant TIMSK4_OCIE4D \ Timer/Counter4 Output Compare D Match Interrupt Enable
- $40 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $20 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $04 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $80 constant TIFR4_OCF4D \ Output Compare Flag 4D
- $40 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $20 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $04 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-&212 constant DT4 \ Timer/Counter 4 Dead Time Value
- $FF constant DT4_DT4L \ Timer/Counter 4 Dead Time Value Bits
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $20 constant ADCSRB_MUX5 \ Analog Channel and Gain Selection Bits
- $17 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&125 constant DIDR2 \ Digital Input Disable Register 1
- $20 constant DIDR2_ADC13D \ ADC13 Digital input Disable
- $10 constant DIDR2_ADC12D \ ADC12 Digital input Disable
- $08 constant DIDR2_ADC11D \ ADC11 Digital input Disable
- $04 constant DIDR2_ADC10D \ ADC10 Digital input Disable
- $02 constant DIDR2_ADC9D \ ADC9 Digital input Disable
- $01 constant DIDR2_ADC8D \ ADC8 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&103 constant RCCTRL \ Oscillator Control Register
- $01 constant RCCTRL_RCFREQ \
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-&199 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&198 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&197 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $10 constant PLLCSR_PINDIV \ PLL prescaler Bit 2
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-&82 constant PLLFRQ \ PLL Frequency Control Register
- $80 constant PLLFRQ_PINMUX \
- $40 constant PLLFRQ_PLLUSB \
- $30 constant PLLFRQ_PLLTM \
- $0F constant PLLFRQ_PDIV \
-\ USB_DEVICE
-&244 constant UEINT \
-&243 constant UEBCHX \
-&242 constant UEBCLX \
-&241 constant UEDATX \
- $FF constant UEDATX_DAT \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $7F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_LSM \ USB low speed mode
- $08 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
- $10 constant USBCON_OTGPADE \
- $01 constant USBCON_VBUSTE \
-&218 constant USBINT \
- $01 constant USBINT_VBUSTI \
-&217 constant USBSTA \
- $08 constant USBSTA_SPEED \
- $01 constant USBSTA_VBUS \
-&215 constant UHWCON \
- $01 constant UHWCON_UVREGE \
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant Reserved1Addr \ Reserved1
-&12 constant Reserved2Addr \ Reserved2
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant Reserved3Addr \ Reserved3
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant USB_GENAddr \ USB General Interrupt Request
-&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant Reserved4Addr \ Reserved4
-&28 constant Reserved5Addr \ Reserved5
-&30 constant Reserved6Addr \ Reserved6
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART1__RXAddr \ USART1, Rx Complete
-&52 constant USART1__UDREAddr \ USART1 Data register Empty
-&54 constant USART1__TXAddr \ USART1, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant TWIAddr \ 2-wire Serial Interface
-&74 constant SPM_READYAddr \ Store Program Memory Read
-&76 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&78 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&80 constant TIMER4_COMPDAddr \ Timer/Counter4 Compare Match D
-&82 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&84 constant TIMER4_FPFAddr \ Timer/Counter4 Fault Protection Interrupt
diff --git a/amforth-6.5/avr8/devices/atmega16u4/device.asm b/amforth-6.5/avr8/devices/atmega16u4/device.asm
deleted file mode 100644
index eb03743..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/device.asm
+++ /dev/null
@@ -1,146 +0,0 @@
-; Partname: ATmega16U4
-; generated automatically, do not edit
-
-.nolist
- .include "m16U4def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_WATCHDOG = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_USART1 = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; Reserved1
-.org 12
- rcall isr ; Reserved2
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; Reserved3
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; USB General Interrupt Request
-.org 22
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Reserved4
-.org 28
- rcall isr ; Reserved5
-.org 30
- rcall isr ; Reserved6
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART1, Rx Complete
-.org 52
- rcall isr ; USART1 Data register Empty
-.org 54
- rcall isr ; USART1, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; 2-wire Serial Interface
-.org 74
- rcall isr ; Store Program Memory Read
-.org 76
- rcall isr ; Timer/Counter4 Compare Match A
-.org 78
- rcall isr ; Timer/Counter4 Compare Match B
-.org 80
- rcall isr ; Timer/Counter4 Compare Match D
-.org 82
- rcall isr ; Timer/Counter4 Overflow
-.org 84
- rcall isr ; Timer/Counter4 Fault Protection Interrupt
-.equ INTVECTORS = 43
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1280
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 12288
-mcu_numints:
- .dw 43
-mcu_name:
- .dw 10
- .db "ATmega16U4"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16u4/device.inc b/amforth-6.5/avr8/devices/atmega16u4/device.inc
deleted file mode 100644
index f0de2d7..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/device.inc
+++ /dev/null
@@ -1,1602 +0,0 @@
-; Partname: ATmega16U4
-; generated automatically, no not edit
-
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register D
-VE_TCCR4D:
- .dw $ff06
- .db "TCCR4D"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4D
-XT_TCCR4D:
- .dw PFA_DOVARIABLE
-PFA_TCCR4D:
- .dw 195
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register E
-VE_TCCR4E:
- .dw $ff06
- .db "TCCR4E"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4E
-XT_TCCR4E:
- .dw PFA_DOVARIABLE
-PFA_TCCR4E:
- .dw 196
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Low Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 190
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4
-VE_TC4H:
- .dw $ff04
- .db "TC4H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TC4H
-XT_TC4H:
- .dw PFA_DOVARIABLE
-PFA_TC4H:
- .dw 191
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register C
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register D
-VE_OCR4D:
- .dw $ff05
- .db "OCR4D",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4D
-XT_OCR4D:
- .dw PFA_DOVARIABLE
-PFA_OCR4D:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Dead Time Value
-VE_DT4:
- .dw $ff03
- .db "DT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DT4
-XT_DT4:
- .dw PFA_DOVARIABLE
-PFA_DT4:
- .dw 212
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Control Register
-VE_RCCTRL:
- .dw $ff06
- .db "RCCTRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_RCCTRL
-XT_RCCTRL:
- .dw PFA_DOVARIABLE
-PFA_RCCTRL:
- .dw 103
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 199
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 197
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Frequency Control Register
-VE_PLLFRQ:
- .dw $ff06
- .db "PLLFRQ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLFRQ
-XT_PLLFRQ:
- .dw PFA_DOVARIABLE
-PFA_PLLFRQ:
- .dw 82
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw 215
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega16u4/device.py b/amforth-6.5/avr8/devices/atmega16u4/device.py
deleted file mode 100644
index 2a03486..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/device.py
+++ /dev/null
@@ -1,554 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega16U4
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'Reserved1Addr' : '#10', # Reserved1
- 'Reserved2Addr' : '#12', # Reserved2
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'Reserved3Addr' : '#16', # Reserved3
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'USB_GENAddr' : '#20', # USB General Interrupt Request
- 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'Reserved4Addr' : '#26', # Reserved4
- 'Reserved5Addr' : '#28', # Reserved5
- 'Reserved6Addr' : '#30', # Reserved6
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#50', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
- 'USART1_TXAddr' : '#54', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'TWIAddr' : '#72', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#74', # Store Program Memory Read
- 'TIMER4_COMPAAddr' : '#76', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#78', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPDAddr' : '#80', # Timer/Counter4 Compare Match D
- 'TIMER4_OVFAddr' : '#82', # Timer/Counter4 Overflow
- 'TIMER4_FPFAddr' : '#84', # Timer/Counter4 Fault Protection Interrupt
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$c0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_FOC4A': '$8', # Force Output Compare Match 4A
- 'TCCR4A_FOC4B': '$4', # Force Output Compare Match 4B
- 'TCCR4A_PWM4A': '$2', #
- 'TCCR4A_PWM4B': '$1', #
- 'TCCR4B' : '$c1', # Timer/Counter4 Control Registe
- 'TCCR4B_PWM4X': '$80', # PWM Inversion Mode
- 'TCCR4B_PSR4': '$40', # Prescaler Reset Timer/Counter
- 'TCCR4B_DTPS4': '$30', # Dead Time Prescaler Bits
- 'TCCR4B_CS4': '$f', # Clock Select Bits
- 'TCCR4C' : '$c2', # Timer/Counter 4 Control Regist
- 'TCCR4C_COM4A1S': '$80', # Comparator A Output Mode
- 'TCCR4C_COM4A0S': '$40', # Comparator A Output Mode
- 'TCCR4C_COM4B1S': '$20', # Comparator B Output Mode
- 'TCCR4C_COM4B0S': '$10', # Comparator B Output Mode
- 'TCCR4C_COM4D': '$c', # Comparator D Output Mode
- 'TCCR4C_FOC4D': '$2', # Force Output Compare Match 4D
- 'TCCR4C_PWM4D': '$1', # Pulse Width Modulator D Enable
- 'TCCR4D' : '$c3', # Timer/Counter 4 Control Regist
- 'TCCR4D_FPIE4': '$80', # Fault Protection Interrupt Ena
- 'TCCR4D_FPEN4': '$40', # Fault Protection Mode Enable
- 'TCCR4D_FPNC4': '$20', # Fault Protection Noise Cancele
- 'TCCR4D_FPES4': '$10', # Fault Protection Edge Select
- 'TCCR4D_FPAC4': '$8', # Fault Protection Analog Compar
- 'TCCR4D_FPF4': '$4', # Fault Protection Interrupt Fla
- 'TCCR4D_WGM4': '$3', # Waveform Generation Mode bits
- 'TCCR4E' : '$c4', # Timer/Counter 4 Control Regist
- 'TCCR4E_TLOCK4': '$80', # Register Update Lock
- 'TCCR4E_ENHC4': '$40', # Enhanced Compare/PWM Mode
- 'TCCR4E_OC4OE': '$3f', # Output Compare Override Enable
- 'TCNT4' : '$be', # Timer/Counter4 Low Bytes
- 'TC4H' : '$bf', # Timer/Counter4
- 'OCR4A' : '$cf', # Timer/Counter4 Output Compare
- 'OCR4B' : '$d0', # Timer/Counter4 Output Compare
- 'OCR4C' : '$d1', # Timer/Counter4 Output Compare
- 'OCR4D' : '$d2', # Timer/Counter4 Output Compare
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_OCIE4D': '$80', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$40', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$20', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$4', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_OCF4D': '$80', # Output Compare Flag 4D
- 'TIFR4_OCF4A': '$40', # Output Compare Flag 4A
- 'TIFR4_OCF4B': '$20', # Output Compare Flag 4B
- 'TIFR4_TOV4': '$4', # Timer/Counter4 Overflow Flag
- 'DT4' : '$d4', # Timer/Counter 4 Dead Time Valu
- 'DT4_DT4L': '$ff', # Timer/Counter 4 Dead Time Valu
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_MUX5': '$20', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$17', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC13D': '$20', # ADC13 Digital input Disable
- 'DIDR2_ADC12D': '$10', # ADC12 Digital input Disable
- 'DIDR2_ADC11D': '$8', # ADC11 Digital input Disable
- 'DIDR2_ADC10D': '$4', # ADC10 Digital input Disable
- 'DIDR2_ADC9D': '$2', # ADC9 Digital input Disable
- 'DIDR2_ADC8D': '$1', # ADC8 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'RCCTRL' : '$67', # Oscillator Control Register
- 'RCCTRL_RCFREQ': '$1', #
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
- 'CLKSTA' : '$c7', #
- 'CLKSTA_RCON': '$2', #
- 'CLKSTA_EXTON': '$1', #
- 'CLKSEL1' : '$c6', #
- 'CLKSEL1_RCCKSEL': '$f0', #
- 'CLKSEL1_EXCKSEL': '$f', #
- 'CLKSEL0' : '$c5', #
- 'CLKSEL0_RCSUT': '$c0', #
- 'CLKSEL0_EXSUT': '$30', #
- 'CLKSEL0_RCE': '$8', #
- 'CLKSEL0_EXTE': '$4', #
- 'CLKSEL0_CLKS': '$1', #
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PINDIV': '$10', # PLL prescaler Bit 2
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
- 'PLLFRQ' : '$52', # PLL Frequency Control Register
- 'PLLFRQ_PINMUX': '$80', #
- 'PLLFRQ_PLLUSB': '$40', #
- 'PLLFRQ_PLLTM': '$30', #
- 'PLLFRQ_PDIV': '$f', #
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCHX' : '$f3', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEDATX_DAT': '$ff', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$7f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_LSM': '$4', # USB low speed mode
- 'UDCON_RSTCPU': '$8', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_FRZCLK': '$20', #
- 'USBCON_OTGPADE': '$10', #
- 'USBCON_VBUSTE': '$1', #
- 'USBINT' : '$da', #
- 'USBINT_VBUSTI': '$1', #
- 'USBSTA' : '$d9', #
- 'USBSTA_SPEED': '$8', #
- 'USBSTA_VBUS': '$1', #
- 'UHWCON' : '$d7', #
- 'UHWCON_UVREGE': '$1', #
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega16u4/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16u4/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u4/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16u4/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u4/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16u4/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega16u4/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2560/atmega2560.frt b/amforth-6.5/avr8/devices/atmega2560/atmega2560.frt
deleted file mode 100644
index b73f112..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/atmega2560.frt
+++ /dev/null
@@ -1,580 +0,0 @@
-\ Partname: ATmega2560
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ PORTH
-&258 constant PORTH \ PORT H Data Register
-&257 constant DDRH \ PORT H Data Direction Register
-&256 constant PINH \ PORT H Input Pins
-\ PORTJ
-&261 constant PORTJ \ PORT J Data Register
-&260 constant DDRJ \ PORT J Data Direction Register
-&259 constant PINJ \ PORT J Input Pins
-\ PORTK
-&264 constant PORTK \ PORT K Data Register
-&263 constant DDRK \ PORT K Data Direction Register
-&262 constant PINK \ PORT K Input Pins
-\ PORTL
-&267 constant PORTL \ PORT L Data Register
-&266 constant DDRL \ PORT L Data Direction Register
-&265 constant PINL \ PORT L Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
- $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
- $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
-&290 constant TCCR5C \ Timer/Counter 5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
- $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
- $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
- $20 constant TIFR5_ICF5 \ Input Capture Flag 5
- $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
- $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
- $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
-&162 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
- $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
- $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $20 constant TIFR4_ICF4 \ Input Capture Flag 4
- $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
- $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Power Reduction USART3
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&125 constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \
- $40 constant DIDR2_ADC14D \
- $20 constant DIDR2_ADC13D \
- $10 constant DIDR2_ADC12D \
- $08 constant DIDR2_ADC11D \
- $04 constant DIDR2_ADC10D \
- $02 constant DIDR2_ADC9D \
- $01 constant DIDR2_ADC8D \
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART2
-&214 constant UDR2 \ USART I/O Data Register
-&208 constant UCSR2A \ USART Control and Status Register A
- $80 constant UCSR2A_RXC2 \ USART Receive Complete
- $40 constant UCSR2A_TXC2 \ USART Transmitt Complete
- $20 constant UCSR2A_UDRE2 \ USART Data Register Empty
- $10 constant UCSR2A_FE2 \ Framing Error
- $08 constant UCSR2A_DOR2 \ Data overRun
- $04 constant UCSR2A_UPE2 \ Parity Error
- $02 constant UCSR2A_U2X2 \ Double the USART transmission speed
- $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode
-&209 constant UCSR2B \ USART Control and Status Register B
- $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
- $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
- $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR2B_RXEN2 \ Receiver Enable
- $08 constant UCSR2B_TXEN2 \ Transmitter Enable
- $04 constant UCSR2B_UCSZ22 \ Character Size
- $02 constant UCSR2B_RXB82 \ Receive Data Bit 8
- $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8
-&210 constant UCSR2C \ USART Control and Status Register C
- $C0 constant UCSR2C_UMSEL2 \ USART Mode Select
- $30 constant UCSR2C_UPM2 \ Parity Mode Bits
- $08 constant UCSR2C_USBS2 \ Stop Bit Select
- $06 constant UCSR2C_UCSZ2 \ Character Size
- $01 constant UCSR2C_UCPOL2 \ Clock Polarity
-&212 constant UBRR2 \ USART Baud Rate Register Bytes
-\ USART3
-&310 constant UDR3 \ USART I/O Data Register
-&304 constant UCSR3A \ USART Control and Status Register A
- $80 constant UCSR3A_RXC3 \ USART Receive Complete
- $40 constant UCSR3A_TXC3 \ USART Transmitt Complete
- $20 constant UCSR3A_UDRE3 \ USART Data Register Empty
- $10 constant UCSR3A_FE3 \ Framing Error
- $08 constant UCSR3A_DOR3 \ Data overRun
- $04 constant UCSR3A_UPE3 \ Parity Error
- $02 constant UCSR3A_U2X3 \ Double the USART transmission speed
- $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode
-&305 constant UCSR3B \ USART Control and Status Register B
- $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
- $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
- $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR3B_RXEN3 \ Receiver Enable
- $08 constant UCSR3B_TXEN3 \ Transmitter Enable
- $04 constant UCSR3B_UCSZ32 \ Character Size
- $02 constant UCSR3B_RXB83 \ Receive Data Bit 8
- $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8
-&306 constant UCSR3C \ USART Control and Status Register C
- $C0 constant UCSR3C_UMSEL3 \ USART Mode Select
- $30 constant UCSR3C_UPM3 \ Parity Mode Bits
- $08 constant UCSR3C_USBS3 \ Stop Bit Select
- $06 constant UCSR3C_UCSZ3 \ Character Size
- $01 constant UCSR3C_UCPOL3 \ Clock Polarity
-&308 constant UBRR3 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0__RXAddr \ USART0, Rx Complete
-&52 constant USART0__UDREAddr \ USART0 Data register Empty
-&54 constant USART0__TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1__RXAddr \ USART1, Rx Complete
-&74 constant USART1__UDREAddr \ USART1 Data register Empty
-&76 constant USART1__TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2__RXAddr \ USART2, Rx Complete
-&104 constant USART2__UDREAddr \ USART2 Data register Empty
-&106 constant USART2__TXAddr \ USART2, Tx Complete
-&108 constant USART3__RXAddr \ USART3, Rx Complete
-&110 constant USART3__UDREAddr \ USART3 Data register Empty
-&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega2560/device.asm b/amforth-6.5/avr8/devices/atmega2560/device.asm
deleted file mode 100644
index 7f07ee1..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/device.asm
+++ /dev/null
@@ -1,190 +0,0 @@
-; Partname: ATmega2560
-; generated automatically, do not edit
-
-.nolist
- .include "m2560def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_PORTK = 0
-.set WANT_PORTL = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_USART1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART2 = 0
-.set WANT_USART3 = 0
-.equ intvecsize = 2 ; please verify; flash size: 262144 bytes
-.equ pclen = 3 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.equ INTVECTORS = 57
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 57
-mcu_name:
- .dw 10
- .db "ATmega2560"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega2560/device.inc b/amforth-6.5/avr8/devices/atmega2560/device.inc
deleted file mode 100644
index a683c18..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/device.inc
+++ /dev/null
@@ -1,1980 +0,0 @@
-; Partname: ATmega2560
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 258
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 257
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 256
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 261
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 260
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 259
-
-.endif
-.if WANT_PORTK == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Data Register
-VE_PORTK:
- .dw $ff05
- .db "PORTK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTK
-XT_PORTK:
- .dw PFA_DOVARIABLE
-PFA_PORTK:
- .dw 264
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Data Direction Register
-VE_DDRK:
- .dw $ff04
- .db "DDRK"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRK
-XT_DDRK:
- .dw PFA_DOVARIABLE
-PFA_DDRK:
- .dw 263
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Input Pins
-VE_PINK:
- .dw $ff04
- .db "PINK"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINK
-XT_PINK:
- .dw PFA_DOVARIABLE
-PFA_PINK:
- .dw 262
-
-.endif
-.if WANT_PORTL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Data Register
-VE_PORTL:
- .dw $ff05
- .db "PORTL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTL
-XT_PORTL:
- .dw PFA_DOVARIABLE
-PFA_PORTL:
- .dw 267
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Data Direction Register
-VE_DDRL:
- .dw $ff04
- .db "DDRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRL
-XT_DDRL:
- .dw PFA_DOVARIABLE
-PFA_DDRL:
- .dw 266
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Input Pins
-VE_PINL:
- .dw $ff04
- .db "PINL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINL
-XT_PINL:
- .dw PFA_DOVARIABLE
-PFA_PINL:
- .dw 265
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR2:
- .dw $ff04
- .db "UDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR2
-XT_UDR2:
- .dw PFA_DOVARIABLE
-PFA_UDR2:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR2A:
- .dw $ff06
- .db "UCSR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2A
-XT_UCSR2A:
- .dw PFA_DOVARIABLE
-PFA_UCSR2A:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR2B:
- .dw $ff06
- .db "UCSR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2B
-XT_UCSR2B:
- .dw PFA_DOVARIABLE
-PFA_UCSR2B:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR2C:
- .dw $ff06
- .db "UCSR2C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2C
-XT_UCSR2C:
- .dw PFA_DOVARIABLE
-PFA_UCSR2C:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR2:
- .dw $ff05
- .db "UBRR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR2
-XT_UBRR2:
- .dw PFA_DOVARIABLE
-PFA_UBRR2:
- .dw 212
-
-.endif
-.if WANT_USART3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR3:
- .dw $ff04
- .db "UDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR3
-XT_UDR3:
- .dw PFA_DOVARIABLE
-PFA_UDR3:
- .dw 310
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR3A:
- .dw $ff06
- .db "UCSR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3A
-XT_UCSR3A:
- .dw PFA_DOVARIABLE
-PFA_UCSR3A:
- .dw 304
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR3B:
- .dw $ff06
- .db "UCSR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3B
-XT_UCSR3B:
- .dw PFA_DOVARIABLE
-PFA_UCSR3B:
- .dw 305
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR3C:
- .dw $ff06
- .db "UCSR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3C
-XT_UCSR3C:
- .dw PFA_DOVARIABLE
-PFA_UCSR3C:
- .dw 306
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR3:
- .dw $ff05
- .db "UBRR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR3
-XT_UBRR3:
- .dw PFA_DOVARIABLE
-PFA_UBRR3:
- .dw 308
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega2560/device.py b/amforth-6.5/avr8/devices/atmega2560/device.py
deleted file mode 100644
index fd51a56..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/device.py
+++ /dev/null
@@ -1,633 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega2560
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module PORTH
- 'PORTH' : '$102', # PORT H Data Register
- 'DDRH' : '$101', # PORT H Data Direction Register
- 'PINH' : '$100', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$105', # PORT J Data Register
- 'DDRJ' : '$104', # PORT J Data Direction Register
- 'PINJ' : '$103', # PORT J Input Pins
-
-# Module PORTK
- 'PORTK' : '$108', # PORT K Data Register
- 'DDRK' : '$107', # PORT K Data Direction Register
- 'PINK' : '$106', # PORT K Input Pins
-
-# Module PORTL
- 'PORTL' : '$10b', # PORT L Data Register
- 'DDRL' : '$10a', # PORT L Data Direction Register
- 'PINL' : '$109', # PORT L Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
- 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
- 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
- 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
- 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
- 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_ICF5': '$20', # Input Capture Flag 5
- 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
- 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
- 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
- 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
- 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
- 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
- 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_ICF4': '$20', # Input Capture Flag 4
- 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
- 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
- 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Power Reduction USART3
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', #
- 'DIDR2_ADC14D': '$40', #
- 'DIDR2_ADC13D': '$20', #
- 'DIDR2_ADC12D': '$10', #
- 'DIDR2_ADC11D': '$8', #
- 'DIDR2_ADC10D': '$4', #
- 'DIDR2_ADC9D': '$2', #
- 'DIDR2_ADC8D': '$1', #
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART2
- 'UDR2' : '$d6', # USART I/O Data Register
- 'UCSR2A' : '$d0', # USART Control and Status Regis
- 'UCSR2A_RXC2': '$80', # USART Receive Complete
- 'UCSR2A_TXC2': '$40', # USART Transmitt Complete
- 'UCSR2A_UDRE2': '$20', # USART Data Register Empty
- 'UCSR2A_FE2': '$10', # Framing Error
- 'UCSR2A_DOR2': '$8', # Data overRun
- 'UCSR2A_UPE2': '$4', # Parity Error
- 'UCSR2A_U2X2': '$2', # Double the USART transmission
- 'UCSR2A_MPCM2': '$1', # Multi-processor Communication
- 'UCSR2B' : '$d1', # USART Control and Status Regis
- 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable
- 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable
- 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte
- 'UCSR2B_RXEN2': '$10', # Receiver Enable
- 'UCSR2B_TXEN2': '$8', # Transmitter Enable
- 'UCSR2B_UCSZ22': '$4', # Character Size
- 'UCSR2B_RXB82': '$2', # Receive Data Bit 8
- 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8
- 'UCSR2C' : '$d2', # USART Control and Status Regis
- 'UCSR2C_UMSEL2': '$c0', # USART Mode Select
- 'UCSR2C_UPM2': '$30', # Parity Mode Bits
- 'UCSR2C_USBS2': '$8', # Stop Bit Select
- 'UCSR2C_UCSZ2': '$6', # Character Size
- 'UCSR2C_UCPOL2': '$1', # Clock Polarity
- 'UBRR2' : '$d4', # USART Baud Rate Register Byte
-
-# Module USART3
- 'UDR3' : '$136', # USART I/O Data Register
- 'UCSR3A' : '$130', # USART Control and Status Regis
- 'UCSR3A_RXC3': '$80', # USART Receive Complete
- 'UCSR3A_TXC3': '$40', # USART Transmitt Complete
- 'UCSR3A_UDRE3': '$20', # USART Data Register Empty
- 'UCSR3A_FE3': '$10', # Framing Error
- 'UCSR3A_DOR3': '$8', # Data overRun
- 'UCSR3A_UPE3': '$4', # Parity Error
- 'UCSR3A_U2X3': '$2', # Double the USART transmission
- 'UCSR3A_MPCM3': '$1', # Multi-processor Communication
- 'UCSR3B' : '$131', # USART Control and Status Regis
- 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable
- 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable
- 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte
- 'UCSR3B_RXEN3': '$10', # Receiver Enable
- 'UCSR3B_TXEN3': '$8', # Transmitter Enable
- 'UCSR3B_UCSZ32': '$4', # Character Size
- 'UCSR3B_RXB83': '$2', # Receive Data Bit 8
- 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8
- 'UCSR3C' : '$132', # USART Control and Status Regis
- 'UCSR3C_UMSEL3': '$c0', # USART Mode Select
- 'UCSR3C_UPM3': '$30', # Parity Mode Bits
- 'UCSR3C_USBS3': '$8', # Stop Bit Select
- 'UCSR3C_UCSZ3': '$6', # Character Size
- 'UCSR3C_UCPOL3': '$1', # Clock Polarity
- 'UBRR3' : '$134', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega2560/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega2560/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2560/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega2560/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2560/words/sleep.asm b/amforth-6.5/avr8/devices/atmega2560/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega2560/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2561/atmega2561.frt b/amforth-6.5/avr8/devices/atmega2561/atmega2561.frt
deleted file mode 100644
index ead48f6..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/atmega2561.frt
+++ /dev/null
@@ -1,510 +0,0 @@
-\ Partname: ATmega2561
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
- $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
- $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
-&290 constant TCCR5C \ Timer/Counter 5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
- $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
- $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
- $20 constant TIFR5_ICF5 \ Input Capture Flag 5
- $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
- $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
- $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
-&162 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
- $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
- $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $20 constant TIFR4_ICF4 \ Input Capture Flag 4
- $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
- $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&91 constant RAMPZ \ RAM Page Z Select Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Power Reduction USART3
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&125 constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \
- $40 constant DIDR2_ADC14D \
- $20 constant DIDR2_ADC13D \
- $10 constant DIDR2_ADC12D \
- $08 constant DIDR2_ADC11D \
- $04 constant DIDR2_ADC10D \
- $02 constant DIDR2_ADC9D \
- $01 constant DIDR2_ADC8D \
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0__RXAddr \ USART0, Rx Complete
-&52 constant USART0__UDREAddr \ USART0 Data register Empty
-&54 constant USART0__TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1__RXAddr \ USART1, Rx Complete
-&74 constant USART1__UDREAddr \ USART1 Data register Empty
-&76 constant USART1__TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2__RXAddr \ USART2, Rx Complete
-&104 constant USART2__UDREAddr \ USART2 Data register Empty
-&106 constant USART2__TXAddr \ USART2, Tx Complete
-&108 constant USART3__RXAddr \ USART3, Rx Complete
-&110 constant USART3__UDREAddr \ USART3 Data register Empty
-&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega2561/device.asm b/amforth-6.5/avr8/devices/atmega2561/device.asm
deleted file mode 100644
index e36ccef..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/device.asm
+++ /dev/null
@@ -1,184 +0,0 @@
-; Partname: ATmega2561
-; generated automatically, do not edit
-
-.nolist
- .include "m2561def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_USART1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.equ intvecsize = 2 ; please verify; flash size: 262144 bytes
-.equ pclen = 3 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.equ INTVECTORS = 57
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 57
-mcu_name:
- .dw 10
- .db "ATmega2561"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega2561/device.inc b/amforth-6.5/avr8/devices/atmega2561/device.inc
deleted file mode 100644
index 15ef0ad..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/device.inc
+++ /dev/null
@@ -1,1698 +0,0 @@
-; Partname: ATmega2561
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega2561/device.py b/amforth-6.5/avr8/devices/atmega2561/device.py
deleted file mode 100644
index 90120d0..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/device.py
+++ /dev/null
@@ -1,557 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega2561
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
- 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
- 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
- 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
- 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
- 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_ICF5': '$20', # Input Capture Flag 5
- 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
- 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
- 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
- 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
- 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
- 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
- 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_ICF4': '$20', # Input Capture Flag 4
- 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
- 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
- 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # RAM Page Z Select Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Power Reduction USART3
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', #
- 'DIDR2_ADC14D': '$40', #
- 'DIDR2_ADC13D': '$20', #
- 'DIDR2_ADC12D': '$10', #
- 'DIDR2_ADC11D': '$8', #
- 'DIDR2_ADC10D': '$4', #
- 'DIDR2_ADC9D': '$2', #
- 'DIDR2_ADC8D': '$1', #
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega2561/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega2561/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2561/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega2561/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2561/words/sleep.asm b/amforth-6.5/avr8/devices/atmega2561/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega2561/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/AD_CONVERTER.frt
deleted file mode 100644
index a283d42..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,79 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index 1c3e910..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/BOOT_LOAD.frt
deleted file mode 100644
index fa74497..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/CPU.frt
deleted file mode 100644
index ec40f10..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/CPU.frt
+++ /dev/null
@@ -1,129 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5c constant EIND \ Extended Indirect Register
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fc constant RAMPZ_Res \ Reserved
- 5b $fc bitmask: RAMPZ.Res \ Reserved
- $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
- 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EEPROM.frt
deleted file mode 100644
index ee9efc5..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EEPROM.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 73eb050..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,45 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/FLASH.frt
deleted file mode 100644
index 24391a0..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/FLASH.frt
+++ /dev/null
@@ -1,16 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/JTAG.frt
deleted file mode 100644
index d84e93c..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/JTAG.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTA.frt
deleted file mode 100644
index dcc6084..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTA.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTB.frt
deleted file mode 100644
index c01cc3b..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTC.frt
deleted file mode 100644
index 0915669..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTC.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTD.frt
deleted file mode 100644
index 445c6b9..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTE.frt
deleted file mode 100644
index d985ac0..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTE.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTF.frt
deleted file mode 100644
index f0d7c26..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTF.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTG.frt
deleted file mode 100644
index c90621c..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTG.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PWRCTRL.frt
deleted file mode 100644
index d1a7358..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PWRCTRL.frt
+++ /dev/null
@@ -1,81 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
deleted file mode 100644
index bc4823d..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SYMCNT.frt
deleted file mode 100644
index 7d4663c..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SYMCNT.frt
+++ /dev/null
@@ -1,156 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_0.frt
deleted file mode 100644
index 12e8b21..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_0.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index 34419fd..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_2.frt
deleted file mode 100644
index 9ded205..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_2.frt
+++ /dev/null
@@ -1,67 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_3.frt
deleted file mode 100644
index 9a97103..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_3.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_4.frt
deleted file mode 100644
index 058e1ba..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_4.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_5.frt
deleted file mode 100644
index a8a13c8..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_5.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TRX24.frt
deleted file mode 100644
index eaf1722..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TRX24.frt
+++ /dev/null
@@ -1,495 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TWI.frt
deleted file mode 100644
index f7914e1..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TWI.frt
+++ /dev/null
@@ -1,40 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0.frt
deleted file mode 100644
index 3ea3fd7..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0_SPI.frt
deleted file mode 100644
index 762a5f9..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1.frt
deleted file mode 100644
index 92c957e..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1_SPI.frt
deleted file mode 100644
index 125d4f9..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/WATCHDOG.frt
deleted file mode 100644
index 662a666..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for atmega2564rfr2
-\ #require bitnames.frt
-
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/device.asm b/amforth-6.5/avr8/devices/atmega2564rfr2/device.asm
deleted file mode 100644
index 41c6805..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/device.asm
+++ /dev/null
@@ -1,166 +0,0 @@
-; Generated Automatically
-
-.nolist
- include "m2564RFR2def.inc"
-.list
-FLASHSTART = 0
-FLASHSIZE = 262144
-RAMEND = 33280
-IRAMSTART = 512
-IRAMSIZE = 32768
-EEPROMSIZE = 8192
-; Interrupt Vectors
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.org 114
- rcall isr ; TRX24 - PLL lock interrupt
-.org 116
- rcall isr ; TRX24 - PLL unlock interrupt
-.org 118
- rcall isr ; TRX24 - Receive start interrupt
-.org 120
- rcall isr ; TRX24 - RX_END interrupt
-.org 122
- rcall isr ; TRX24 - CCA/ED done interrupt
-.org 124
- rcall isr ; TRX24 - XAH - AMI
-.org 126
- rcall isr ; TRX24 - TX_END interrupt
-.org 128
- rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-.org 130
- rcall isr ; Symbol counter - compare match 1 interrupt
-.org 132
- rcall isr ; Symbol counter - compare match 2 interrupt
-.org 134
- rcall isr ; Symbol counter - compare match 3 interrupt
-.org 136
- rcall isr ; Symbol counter - overflow interrupt
-.org 138
- rcall isr ; Symbol counter - backoff interrupt
-.org 140
- rcall isr ; AES engine ready interrupt
-.org 142
- rcall isr ; Battery monitor indicates supply voltage below threshold
-.org 144
- rcall isr ; TRX24 TX start interrupt
-.org 146
- rcall isr ; Address match interrupt of address filter 0
-.org 148
- rcall isr ; Address match interrupt of address filter 1
-.org 150
- rcall isr ; Address match interrupt of address filter 2
-.org 152
- rcall isr ; Address match interrupt of address filter 3
-.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/device.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/device.frt
deleted file mode 100644
index 4ff689f..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/device.frt
+++ /dev/null
@@ -1,1753 +0,0 @@
-\ Generated Automatically
-
-\ Interrupt Vectors
-#2 constant INT0Addr \ External Interrupt Request 0
-#4 constant INT1Addr \ External Interrupt Request 1
-#6 constant INT2Addr \ External Interrupt Request 2
-#8 constant INT3Addr \ External Interrupt Request 3
-#10 constant INT4Addr \ External Interrupt Request 4
-#12 constant INT5Addr \ External Interrupt Request 5
-#14 constant INT6Addr \ External Interrupt Request 6
-#16 constant INT7Addr \ External Interrupt Request 7
-#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-#24 constant WDTAddr \ Watchdog Time-out Interrupt
-#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
-#50 constant USART0_RXAddr \ USART0, Rx Complete
-#52 constant USART0_UDREAddr \ USART0 Data register Empty
-#54 constant USART0_TXAddr \ USART0, Tx Complete
-#56 constant ANALOG_COMPAddr \ Analog Comparator
-#58 constant ADCAddr \ ADC Conversion Complete
-#60 constant EE_READYAddr \ EEPROM Ready
-#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-#72 constant USART1_RXAddr \ USART1, Rx Complete
-#74 constant USART1_UDREAddr \ USART1 Data register Empty
-#76 constant USART1_TXAddr \ USART1, Tx Complete
-#78 constant TWIAddr \ 2-wire Serial Interface
-#80 constant SPM_READYAddr \ Store Program Memory Read
-#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-#102 constant USART2_RXAddr \ USART2, Rx Complete
-#104 constant USART2_UDREAddr \ USART2 Data register Empty
-#106 constant USART2_TXAddr \ USART2, Tx Complete
-#108 constant USART3_RXAddr \ USART3, Rx Complete
-#110 constant USART3_UDREAddr \ USART3 Data register Empty
-#112 constant USART3_TXAddr \ USART3, Tx Complete
-#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
-#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
-#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
-#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
-#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
-#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
-#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
-#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
-#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
-#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
-#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
-#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
-#140 constant AES_READYAddr \ AES engine ready interrupt
-#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
-#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
-#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
-#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
-#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
-#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5c constant EIND \ Extended Indirect Register
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fc constant RAMPZ_Res \ Reserved
- 5b $fc bitmask: RAMPZ.Res \ Reserved
- $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
- 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/device.py b/amforth-6.5/avr8/devices/atmega2564rfr2/device.py
deleted file mode 100644
index 92acde5..0000000
--- a/amforth-6.5/avr8/devices/atmega2564rfr2/device.py
+++ /dev/null
@@ -1,1104 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega2564RFR2
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
- 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
- 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
- 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
- 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
- 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
- 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
- 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
- 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
- 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
- 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
- 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
- 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
- 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
- 'AES_READYAddr' : '#140', # AES engine ready interrupt
- 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
- 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
- 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
- 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
- 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
- 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART0 I/O Data Register
- 'UCSR0A' : '$c0', # USART0 Control and Status Regi
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Frame Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART0 Control and Status Regi
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART0 Control and Status Regi
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART1 I/O Data Register
- 'UCSR1A' : '$c8', # USART1 Control and Status Regi
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Frame Error
- 'UCSR1A_DOR1': '$8', # Data OverRun
- 'UCSR1A_UPE1': '$4', # USART Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART Transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART1 Control and Status Regi
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART1 Control and Status Regi
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', # TWI Address Mask
- 'TWAMR_Res': '$1', # Reserved Bit
- 'TWBR' : '$b8', # TWI Bit Rate Register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI START Condition Bit
- 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collision Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_Res': '$2', # Reserved Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_Res': '$4', # Reserved Bit
- 'TWSR_TWPS': '$3', # TWI Prescaler Bits
- 'TWDR' : '$bb', # TWI Data Register
- 'TWAR' : '$ba', # TWI (Slave) Address Register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_Res': '$3e', # Reserved
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins Address
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins Address
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins Address
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins Address
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins Address
-
-# Module PORTF
- 'PORTF' : '$31', # Port F Data Register
- 'DDRF' : '$30', # Port F Data Direction Register
- 'PINF' : '$2f', # Port F Input Pins Address
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins Address
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0 Register
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_Res': '$30', # Reserved Bit
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
- 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
- 'TCCR0A_Res': '$c', # Reserved Bit
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_Res': '$f8', # Reserved
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_Res': '$f8', # Reserved
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_Res': '$7c', # Reserved
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_Res': '$f8', # Reserved Bit
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_Res': '$f8', # Reserved Bit
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
- 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
- 'TCCR2A_Res': '$c', # Reserved
- 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_Res': '$30', # Reserved
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
- 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
- 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
- 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
- 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
- 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_Res': '$20', # Reserved Bit
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Clock Select
- 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
- 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
- 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
- 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
- 'TCCR5C_Res': '$1f', # Reserved
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_Res': '$c0', # Reserved Bit
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_Res': '$10', # Reserved Bit
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_Res': '$c0', # Reserved Bit
- 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
- 'TIFR5_Res': '$10', # Reserved Bit
- 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
- 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
- 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_Res': '$20', # Reserved Bit
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Clock Select
- 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
- 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
- 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
- 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
- 'TCCR4C_Res': '$1f', # Reserved
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_Res': '$c0', # Reserved Bit
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_Res': '$10', # Reserved Bit
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_Res': '$c0', # Reserved Bit
- 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
- 'TIFR4_Res': '$10', # Reserved Bit
- 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
- 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
- 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_Res': '$20', # Reserved Bit
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
- 'TCCR3C_Res': '$1f', # Reserved
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_Res': '$c0', # Reserved Bit
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_Res': '$10', # Reserved Bit
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_Res': '$c0', # Reserved Bit
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_Res': '$10', # Reserved Bit
- 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
- 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
- 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_Res': '$20', # Reserved Bit
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
- 'TCCR1C_Res': '$1f', # Reserved
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_Res': '$c0', # Reserved Bit
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_Res': '$10', # Reserved Bit
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_Res': '$c0', # Reserved Bit
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_Res': '$10', # Reserved Bit
- 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TRX24
- 'PARCR' : '$138', # Power Amplifier Ramp up/down C
- 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
- 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
- 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
- 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
- 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
- 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
- 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
- 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
- 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
- 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA1L' : '$112', # Transceiver MAC Short Address
- 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
- 'MAFSA1H' : '$113', # Transceiver MAC Short Address
- 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
- 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
- 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA2L' : '$116', # Transceiver MAC Short Address
- 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
- 'MAFSA2H' : '$117', # Transceiver MAC Short Address
- 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
- 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
- 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
- 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
- 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
- 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
- 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
- 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
- 'MAFCR0' : '$10c', # Multiple Address Filter Config
- 'MAFCR0_Res': '$f0', # Reserved Bit
- 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
- 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
- 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
- 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
- 'MAFCR1' : '$10d', # Multiple Address Filter Config
- 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
- 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
- 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
- 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
- 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
- 'AES_CTRL' : '$13c', # AES Control Register
- 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
- 'AES_CTRL_Res': '$40', # Reserved Bit
- 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
- 'AES_CTRL_Res': '$10', # Reserved Bit
- 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
- 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
- 'AES_CTRL_Res': '$3', # Reserved Bit
- 'AES_STATUS' : '$13d', # AES Status Register
- 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
- 'AES_STATUS_Res': '$7e', # Reserved
- 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
- 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
- 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
- 'AES_KEY' : '$13f', # AES Encryption and Decryption
- 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
- 'TRX_STATUS' : '$141', # Transceiver Status Register
- 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
- 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
- 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
- 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
- 'TRX_STATE' : '$142', # Transceiver State Control Regi
- 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
- 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
- 'TRX_CTRL_0' : '$143', # Reserved
- 'TRX_CTRL_0_Res7': '$80', # Reserved
- 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
- 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
- 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
- 'TRX_CTRL_0_Res': '$f', # Reserved
- 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
- 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
- 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
- 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
- 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
- 'TRX_CTRL_1_Res': '$f', # Reserved
- 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
- 'PHY_TX_PWR_Res': '$f0', # Reserved
- 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
- 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
- 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
- 'PHY_RSSI_RND_VALUE': '$60', # Random Value
- 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
- 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
- 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
- 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
- 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
- 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
- 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
- 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
- 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
- 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
- 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
- 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
- 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
- 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
- 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
- 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
- 'TRX_CTRL_2_Res': '$7c', # Reserved
- 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
- 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
- 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
- 'ANT_DIV_Res': '$70', # Reserved
- 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
- 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
- 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
- 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
- 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
- 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
- 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
- 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
- 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
- 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
- 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
- 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
- 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
- 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
- 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
- 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
- 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
- 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
- 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
- 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
- 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
- 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
- 'IRQ_MASK1_Res': '$e0', # Reserved Bit
- 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
- 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
- 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
- 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
- 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
- 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
- 'VREG_CTRL' : '$150', # Voltage Regulator Control and
- 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
- 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
- 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
- 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
- 'BATMON' : '$151', # Battery Monitor Control and St
- 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
- 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
- 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
- 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
- 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
- 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
- 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
- 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
- 'CC_CTRL_0' : '$153', # Channel Control Register 0
- 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
- 'CC_CTRL_1' : '$154', # Channel Control Register 1
- 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
- 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
- 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
- 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
- 'RX_SYN_Res': '$30', # Reserved
- 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
- 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
- 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
- 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
- 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
- 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
- 'TRX_RPC_Res0': '$4', # Reserved
- 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
- 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
- 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
- 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
- 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
- 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
- 'XAH_CTRL_1_Res': '$8', # Reserved Bit
- 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
- 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
- 'XAH_CTRL_1_Res': '$1', # Reserved Bit
- 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
- 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
- 'PLL_CF' : '$15a', # Transceiver Center Frequency C
- 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
- 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
- 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
- 'PART_NUM' : '$15c', # Device Identification Register
- 'PART_NUM_PART_NUM': '$ff', # Part Number
- 'VERSION_NUM' : '$15d', # Device Identification Register
- 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
- 'MAN_ID_0' : '$15e', # Device Identification Register
- 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
- 'MAN_ID_1' : '$15f', # Device Identification Register
- 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
- 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
- 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
- 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
- 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
- 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
- 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
- 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
- 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
- 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
- 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
- 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
- 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
- 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
- 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
- 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
- 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
- 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
- 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
- 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
- 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
- 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
- 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
- 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
- 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
- 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
- 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
- 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
- 'TRXFBST' : '$180', # Start of frame buffer
- 'TRXFBEND' : '$1ff', # End of frame buffer
-
-# Module SYMCNT
- 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
- 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
- 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
- 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
- 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
- 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
- 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
- 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
- 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
- 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
- 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
- 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
- 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
- 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
- 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
- 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
- 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
- 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
- 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
- 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
- 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
- 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
- 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
- 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
- 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
- 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
- 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
- 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
- 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
- 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
- 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
- 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
- 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
- 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
- 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
- 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
- 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
- 'SCIRQS_Res': '$e0', # Reserved Bit
- 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
- 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
- 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
- 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
- 'SCIRQM_Res': '$e0', # Reserved Bit
- 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
- 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
- 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
- 'SCSR' : '$de', # Symbol Counter Status Register
- 'SCSR_Res': '$fe', # Reserved Bit
- 'SCSR_SCBSY': '$1', # Symbol Counter busy
- 'SCCR1' : '$dd', # Symbol Counter Control Registe
- 'SCCR1_Res': '$c0', # Reserved Bit
- 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
- 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
- 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
- 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
- 'SCCR0' : '$dc', # Symbol Counter Control Registe
- 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
- 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
- 'SCCR0_SCEN': '$20', # Symbol Counter enable
- 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
- 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
- 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
- 'SCCSR' : '$db', # Symbol Counter Compare Source
- 'SCCSR_Res': '$c0', # Reserved Bit
- 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
- 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
- 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
- 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
- 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
- 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
- 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
- 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_Res': '$c0', # Reserved
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
- 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
- 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
- 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
- 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
- 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
- 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request Ena
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flag
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_Res': '$f8', # Reserved Bit
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_Res': '$f8', # Reserved Bit
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC Multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status Reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status Reg
- 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ADCSRB_REFOK': '$20', # Reference Voltage OK
- 'ADCSRB_ACCH': '$10', # Analog Channel Change
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
- 'ADCSRC' : '$77', # The ADC Control and Status Reg
- 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
- 'ADCSRC_Res0': '$20', # Reserved
- 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', # Reserved Bits
- 'DIDR2_ADC14D': '$40', # Reserved Bits
- 'DIDR2_ADC13D': '$20', # Reserved Bits
- 'DIDR2_ADC12D': '$10', # Reserved Bits
- 'DIDR2_ADC11D': '$8', # Reserved Bits
- 'DIDR2_ADC10D': '$4', # Reserved Bits
- 'DIDR2_ADC9D': '$2', # Reserved Bits
- 'DIDR2_ADC8D': '$1', # Reserved Bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_Res': '$60', # Reserved
- 'MCUCR_PUD': '$10', # Pull-up Disable
- 'MCUCR_Res': '$c', # Reserved
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_Res': '$e0', # Reserved
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on Reset Flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_Res': '$70', # Reserved
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_Res': '$f0', # Reserved
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
- 'RAMPZ_Res': '$fc', # Reserved
- 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
- 'PRR2' : '$63', # Power Reduction Register 2
- 'PRR2_Res': '$f0', # Reserved Bit
- 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
- 'PRR1' : '$65', # Power Reduction Register 1
- 'PRR1_Res': '$80', # Reserved Bit
- 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRPGA': '$10', # Power Reduction PGA
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module FLASH
- 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
- 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
- 'NEMCR_AEAM': '$30', # Address for Extended Address M
- 'BGCR' : '$67', # Reference Voltage Calibration
- 'BGCR_Res': '$80', # Reserved Bit
- 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
- 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
-
-# Module PWRCTRL
- 'TRXPR' : '$139', # Transceiver Pin Register
- 'TRXPR_Res': '$f0', # Reserved
- 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
- 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
- 'DRTRAM0' : '$135', # Data Retention Configuration R
- 'DRTRAM0_Res': '$c0', # Reserved
- 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM1' : '$134', # Data Retention Configuration R
- 'DRTRAM1_Res': '$c0', # Reserved
- 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM2' : '$133', # Data Retention Configuration R
- 'DRTRAM2_Res': '$40', # Reserved Bit
- 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM3' : '$132', # Data Retention Configuration R
- 'DRTRAM3_Res': '$c0', # Reserved
- 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
- 'LLDRL' : '$130', # Low Leakage Voltage Regulator
- 'LLDRL_Res': '$f0', # Reserved
- 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
- 'LLDRH' : '$131', # Low Leakage Voltage Regulator
- 'LLDRH_Res': '$e0', # Reserved
- 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
- 'LLCR' : '$12f', # Low Leakage Voltage Regulator
- 'LLCR_Res': '$c0', # Reserved Bit
- 'LLCR_LLDONE': '$20', # Calibration Done
- 'LLCR_LLCOMP': '$10', # Comparator Output
- 'LLCR_LLCAL': '$8', # Calibration Active
- 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
- 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
- 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
- 'DPDS0' : '$136', # Port Driver Strength Register
- 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
- 'DPDS0_PEDRV': '$30', # Driver Strength Port E
- 'DPDS0_PDDRV': '$c', # Driver Strength Port D
- 'DPDS0_PBDRV': '$3', # Driver Strength Port B
- 'DPDS1' : '$137', # Port Driver Strength Register
- 'DPDS1_Res': '$fc', # Reserved
- 'DPDS1_PGDRV': '$3', # Driver Strength Port G
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up Disable
-
-# Module USART0_SPI
- 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
- 'UCSR0C_UDORD0': '$4', # Data Order
- 'UCSR0C_UCPHA0': '$2', # Clock Phase
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
-
-# Module USART1_SPI
- 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
- 'UCSR1C_UDORD1': '$4', # Data Order
- 'UCSR1C_UCPHA1': '$2', # Clock Phase
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt
deleted file mode 100644
index 17d6c7e..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,79 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index cf9e656..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt
deleted file mode 100644
index d38b796..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt
deleted file mode 100644
index f15f877..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt
+++ /dev/null
@@ -1,129 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5c constant EIND \ Extended Indirect Register
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fc constant RAMPZ_Res \ Reserved
- 5b $fc bitmask: RAMPZ.Res \ Reserved
- $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
- 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt
deleted file mode 100644
index e56ad19..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 4e7c1fc..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,45 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt
deleted file mode 100644
index c219192..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt
+++ /dev/null
@@ -1,16 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt
deleted file mode 100644
index 1960eac..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt
deleted file mode 100644
index 0c4e462..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt
deleted file mode 100644
index 493d57a..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt
deleted file mode 100644
index dfb169b..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt
deleted file mode 100644
index d46daaa..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt
deleted file mode 100644
index feadc5c..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt
deleted file mode 100644
index d4c2e02..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt
deleted file mode 100644
index 53a190c..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt
deleted file mode 100644
index 2ba9d2e..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt
+++ /dev/null
@@ -1,81 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt
deleted file mode 100644
index 53bae0e..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt
deleted file mode 100644
index 26c4758..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt
+++ /dev/null
@@ -1,156 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt
deleted file mode 100644
index 50f60a9..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index d3b8f20..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt
deleted file mode 100644
index 748cd79..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt
+++ /dev/null
@@ -1,67 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt
deleted file mode 100644
index 30d6566..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt
deleted file mode 100644
index 4ed5cb6..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt
deleted file mode 100644
index 434ee3b..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt
deleted file mode 100644
index d8c6290..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt
+++ /dev/null
@@ -1,495 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt
deleted file mode 100644
index 7ac98fa..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt
+++ /dev/null
@@ -1,40 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt
deleted file mode 100644
index 3a4431e..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt
deleted file mode 100644
index 0acd6b4..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt
deleted file mode 100644
index 0852262..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt
deleted file mode 100644
index fa56346..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt
deleted file mode 100644
index c695cba..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for atmega256rfr2
-\ #require bitnames.frt
-
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.asm b/amforth-6.5/avr8/devices/atmega256rfr2/device.asm
deleted file mode 100644
index 9b76f0a..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/device.asm
+++ /dev/null
@@ -1,166 +0,0 @@
-; Generated Automatically
-
-.nolist
- include "m256RFR2def.inc"
-.list
-FLASHSTART = 0
-FLASHSIZE = 262144
-RAMEND = 33280
-IRAMSTART = 512
-IRAMSIZE = 32768
-EEPROMSIZE = 8192
-; Interrupt Vectors
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.org 114
- rcall isr ; TRX24 - PLL lock interrupt
-.org 116
- rcall isr ; TRX24 - PLL unlock interrupt
-.org 118
- rcall isr ; TRX24 - Receive start interrupt
-.org 120
- rcall isr ; TRX24 - RX_END interrupt
-.org 122
- rcall isr ; TRX24 - CCA/ED done interrupt
-.org 124
- rcall isr ; TRX24 - XAH - AMI
-.org 126
- rcall isr ; TRX24 - TX_END interrupt
-.org 128
- rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-.org 130
- rcall isr ; Symbol counter - compare match 1 interrupt
-.org 132
- rcall isr ; Symbol counter - compare match 2 interrupt
-.org 134
- rcall isr ; Symbol counter - compare match 3 interrupt
-.org 136
- rcall isr ; Symbol counter - overflow interrupt
-.org 138
- rcall isr ; Symbol counter - backoff interrupt
-.org 140
- rcall isr ; AES engine ready interrupt
-.org 142
- rcall isr ; Battery monitor indicates supply voltage below threshold
-.org 144
- rcall isr ; TRX24 TX start interrupt
-.org 146
- rcall isr ; Address match interrupt of address filter 0
-.org 148
- rcall isr ; Address match interrupt of address filter 1
-.org 150
- rcall isr ; Address match interrupt of address filter 2
-.org 152
- rcall isr ; Address match interrupt of address filter 3
-.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.frt b/amforth-6.5/avr8/devices/atmega256rfr2/device.frt
deleted file mode 100644
index 4ff689f..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/device.frt
+++ /dev/null
@@ -1,1753 +0,0 @@
-\ Generated Automatically
-
-\ Interrupt Vectors
-#2 constant INT0Addr \ External Interrupt Request 0
-#4 constant INT1Addr \ External Interrupt Request 1
-#6 constant INT2Addr \ External Interrupt Request 2
-#8 constant INT3Addr \ External Interrupt Request 3
-#10 constant INT4Addr \ External Interrupt Request 4
-#12 constant INT5Addr \ External Interrupt Request 5
-#14 constant INT6Addr \ External Interrupt Request 6
-#16 constant INT7Addr \ External Interrupt Request 7
-#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-#24 constant WDTAddr \ Watchdog Time-out Interrupt
-#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
-#50 constant USART0_RXAddr \ USART0, Rx Complete
-#52 constant USART0_UDREAddr \ USART0 Data register Empty
-#54 constant USART0_TXAddr \ USART0, Tx Complete
-#56 constant ANALOG_COMPAddr \ Analog Comparator
-#58 constant ADCAddr \ ADC Conversion Complete
-#60 constant EE_READYAddr \ EEPROM Ready
-#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-#72 constant USART1_RXAddr \ USART1, Rx Complete
-#74 constant USART1_UDREAddr \ USART1 Data register Empty
-#76 constant USART1_TXAddr \ USART1, Tx Complete
-#78 constant TWIAddr \ 2-wire Serial Interface
-#80 constant SPM_READYAddr \ Store Program Memory Read
-#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-#102 constant USART2_RXAddr \ USART2, Rx Complete
-#104 constant USART2_UDREAddr \ USART2 Data register Empty
-#106 constant USART2_TXAddr \ USART2, Tx Complete
-#108 constant USART3_RXAddr \ USART3, Rx Complete
-#110 constant USART3_UDREAddr \ USART3 Data register Empty
-#112 constant USART3_TXAddr \ USART3, Tx Complete
-#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
-#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
-#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
-#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
-#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
-#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
-#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
-#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
-#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
-#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
-#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
-#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
-#140 constant AES_READYAddr \ AES engine ready interrupt
-#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
-#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
-#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
-#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
-#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
-#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
-\ USART0
-$c6 constant UDR0 \ USART0 I/O Data Register
-$c0 constant UCSR0A \ USART0 Control and Status Regi
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
- $8 constant UCSR0A_DOR0 \ Data OverRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
- $4 constant UCSR0A_UPE0 \ USART Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART Transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART0 Control and Status Regi
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART0 Control and Status Regi
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
-\ USART1
-$ce constant UDR1 \ USART1 I/O Data Register
-$c8 constant UCSR1A \ USART1 Control and Status Regi
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
- $8 constant UCSR1A_DOR1 \ Data OverRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
- $4 constant UCSR1A_UPE1 \ USART Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART Transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART1 Control and Status Regi
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART1 Control and Status Regi
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART1 Baud Rate Register Byt
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \ TWI Address Mask
- bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
- $1 constant TWAMR_Res \ Reserved Bit
- bd $1 bitmask: TWAMR.Res \ Reserved Bit
-$b8 constant TWBR \ TWI Bit Rate Register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collision Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $2 constant TWCR_Res \ Reserved Bit
- bc $2 bitmask: TWCR.Res \ Reserved Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $4 constant TWSR_Res \ Reserved Bit
- b9 $4 bitmask: TWSR.Res \ Reserved Bit
- $3 constant TWSR_TWPS \ TWI Prescaler Bits
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
-$bb constant TWDR \ TWI Data Register
-$ba constant TWAR \ TWI (Slave) Address Register
- $fe constant TWAR_TWA \ TWI (Slave) Address
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
-\ SPI
-$4c constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- 4c $40 bitmask: SPCR.SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- 4c $20 bitmask: SPCR.DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
- $8 constant SPCR_CPOL \ Clock polarity
- 4c $8 bitmask: SPCR.CPOL \ Clock polarity
- $4 constant SPCR_CPHA \ Clock Phase
- 4c $4 bitmask: SPCR.CPHA \ Clock Phase
- $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
- 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
-$4d constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
- $3e constant SPSR_Res \ Reserved
- 4d $3e bitmask: SPSR.Res \ Reserved
- $1 constant SPSR_SPI2X \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
-$4e constant SPDR \ SPI Data Register
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins Address
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins Address
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins Address
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins Address
-\ PORTE
-$2e constant PORTE \ Port E Data Register
-$2d constant DDRE \ Port E Data Direction Register
-$2c constant PINE \ Port E Input Pins Address
-\ PORTF
-$31 constant PORTF \ Port F Data Register
-$30 constant DDRF \ Port F Data Direction Register
-$2f constant PINF \ Port F Input Pins Address
-\ PORTG
-$34 constant PORTG \ Port G Data Register
-$33 constant DDRG \ Port G Data Direction Register
-$32 constant PING \ Port G Input Pins Address
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0 Register
-$45 constant TCCR0B \ Timer/Counter0 Control Registe
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter0 Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
- $c constant TCCR0A_Res \ Reserved Bit
- 44 $c bitmask: TCCR0A.Res \ Reserved Bit
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $f8 constant TIMSK0_Res \ Reserved
- 6e $f8 bitmask: TIMSK0.Res \ Reserved
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $f8 constant TIFR0_Res \ Reserved
- 35 $f8 bitmask: TIFR0.Res \ Reserved
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $7c constant GTCCR_Res \ Reserved
- 43 $7c bitmask: GTCCR.Res \ Reserved
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $f8 constant TIMSK2_Res \ Reserved Bit
- 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $f8 constant TIFR2_Res \ Reserved Bit
- 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
- $c constant TCCR2A_Res \ Reserved
- b0 $c bitmask: TCCR2A.Res \ Reserved
- $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- b1 $30 bitmask: TCCR2B.Res \ Reserved
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
- b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
- b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
- b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
- $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
- b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
- $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
- $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-$120 constant TCCR5A \ Timer/Counter5 Control Registe
- $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
- 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
- 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
- $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
- 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
- $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
- 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
-$121 constant TCCR5B \ Timer/Counter5 Control Registe
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
- 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
- $7 constant TCCR5B_CS5 \ Clock Select
- 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
-$122 constant TCCR5C \ Timer/Counter5 Control Registe
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
- 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
- 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
- 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
- $1f constant TCCR5C_Res \ Reserved
- 122 $1f bitmask: TCCR5C.Res \ Reserved
-$124 constant TCNT5 \ Timer/Counter5 Bytes
-$128 constant OCR5A \ Timer/Counter5 Output Compare
-$12a constant OCR5B \ Timer/Counter5 Output Compare
-$12c constant OCR5C \ Timer/Counter5 Output Compare
-$126 constant ICR5 \ Timer/Counter5 Input Capture R
-$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
- $c0 constant TIMSK5_Res \ Reserved Bit
- 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
- 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
- $10 constant TIMSK5_Res \ Reserved Bit
- 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
- $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
- 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
- $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
- 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
- $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
- 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
- $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
- 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
-$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
- $c0 constant TIFR5_Res \ Reserved Bit
- 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
- 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
- $10 constant TIFR5_Res \ Reserved Bit
- 3a $10 bitmask: TIFR5.Res \ Reserved Bit
- $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
- 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
- $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
- 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
- $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
- 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
- $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
- 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-$a0 constant TCCR4A \ Timer/Counter4 Control Registe
- $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
- a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
- a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
- $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
- a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
- $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
- a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
-$a1 constant TCCR4B \ Timer/Counter4 Control Registe
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
- a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
- $7 constant TCCR4B_CS4 \ Clock Select
- a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
-$a2 constant TCCR4C \ Timer/Counter4 Control Registe
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
- a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
- a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
- a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
- $1f constant TCCR4C_Res \ Reserved
- a2 $1f bitmask: TCCR4C.Res \ Reserved
-$a4 constant TCNT4 \ Timer/Counter4 Bytes
-$a8 constant OCR4A \ Timer/Counter4 Output Compare
-$aa constant OCR4B \ Timer/Counter4 Output Compare
-$ac constant OCR4C \ Timer/Counter4 Output Compare
-$a6 constant ICR4 \ Timer/Counter4 Input Capture R
-$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
- $c0 constant TIMSK4_Res \ Reserved Bit
- 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
- 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
- $10 constant TIMSK4_Res \ Reserved Bit
- 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
- $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
- 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
- $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
- 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
- $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
- 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
- $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
- 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
-$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
- $c0 constant TIFR4_Res \ Reserved Bit
- 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
- 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
- $10 constant TIFR4_Res \ Reserved Bit
- 39 $10 bitmask: TIFR4.Res \ Reserved Bit
- $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
- 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
- $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
- 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
- $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
- 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
- $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
- 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-$90 constant TCCR3A \ Timer/Counter3 Control Registe
- $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
- 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
- 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
- $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
- 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
- $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
- 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
-$91 constant TCCR3B \ Timer/Counter3 Control Registe
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
- 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
- $7 constant TCCR3B_CS3 \ Clock Select
- 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
-$92 constant TCCR3C \ Timer/Counter3 Control Registe
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
- 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
- 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
- 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
- $1f constant TCCR3C_Res \ Reserved
- 92 $1f bitmask: TCCR3C.Res \ Reserved
-$94 constant TCNT3 \ Timer/Counter3 Bytes
-$98 constant OCR3A \ Timer/Counter3 Output Compare
-$9a constant OCR3B \ Timer/Counter3 Output Compare
-$9c constant OCR3C \ Timer/Counter3 Output Compare
-$96 constant ICR3 \ Timer/Counter3 Input Capture R
-$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
- $c0 constant TIMSK3_Res \ Reserved Bit
- 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
- 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
- $10 constant TIMSK3_Res \ Reserved Bit
- 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
- $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
- 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
- $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
- 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
- $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
- 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
- $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
- 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
-$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
- $c0 constant TIFR3_Res \ Reserved Bit
- 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
- 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
- $10 constant TIFR3_Res \ Reserved Bit
- 38 $10 bitmask: TIFR3.Res \ Reserved Bit
- $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
- 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
- $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
- 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
- $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
- 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
- $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
- 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
- $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
- 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
- $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
- 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
- $7 constant TCCR1B_CS1 \ Clock Select
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
- 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
- $1f constant TCCR1C_Res \ Reserved
- 82 $1f bitmask: TCCR1C.Res \ Reserved
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$8c constant OCR1C \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $c0 constant TIMSK1_Res \ Reserved Bit
- 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $10 constant TIMSK1_Res \ Reserved Bit
- 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
- $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
- 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
- $c0 constant TIFR1_Res \ Reserved Bit
- 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $10 constant TIFR1_Res \ Reserved Bit
- 36 $10 bitmask: TIFR1.Res \ Reserved Bit
- $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
- 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-\ TRX24
-$138 constant PARCR \ Power Amplifier Ramp up/down C
- $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
- 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
- $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
- 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
- $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
- 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
- $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
- 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
-$10e constant MAFSA0L \ Transceiver MAC Short Address
- $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
- 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
-$10f constant MAFSA0H \ Transceiver MAC Short Address
- $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
- 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
-$110 constant MAFPA0L \ Transceiver Personal Area Netw
- $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
- 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
-$111 constant MAFPA0H \ Transceiver Personal Area Netw
- $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
- 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
-$112 constant MAFSA1L \ Transceiver MAC Short Address
- $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
- 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
-$113 constant MAFSA1H \ Transceiver MAC Short Address
- $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
- 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
-$114 constant MAFPA1L \ Transceiver Personal Area Netw
- $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
- 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
-$115 constant MAFPA1H \ Transceiver Personal Area Netw
- $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
- 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
-$116 constant MAFSA2L \ Transceiver MAC Short Address
- $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
- 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
-$117 constant MAFSA2H \ Transceiver MAC Short Address
- $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
- 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
-$118 constant MAFPA2L \ Transceiver Personal Area Netw
- $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
- 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
-$119 constant MAFPA2H \ Transceiver Personal Area Netw
- $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
- 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
-$11a constant MAFSA3L \ Transceiver MAC Short Address
- $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
- 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
-$11b constant MAFSA3H \ Transceiver MAC Short Address
- $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
- 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
-$11c constant MAFPA3L \ Transceiver Personal Area Netw
- $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
- 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
-$11d constant MAFPA3H \ Transceiver Personal Area Netw
- $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
- 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
-$10c constant MAFCR0 \ Multiple Address Filter Config
- $f0 constant MAFCR0_Res \ Reserved Bit
- 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
- $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
- 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
- $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
- 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
- $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
- 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
- $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
- 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
-$10d constant MAFCR1 \ Multiple Address Filter Config
- $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
- 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
- $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
- $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
- 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
- $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
- $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
- 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
- $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
- $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
- 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
- $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
- 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
-$13c constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
- $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
- $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
- $3 constant AES_CTRL_Res \ Reserved Bit
- 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
-$13d constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
- 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
- $7e constant AES_STATUS_Res \ Reserved
- 13d $7e bitmask: AES_STATUS.Res \ Reserved
- $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
- 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
-$13e constant AES_STATE \ AES Plain and Cipher Text Buff
- $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
- 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
-$13f constant AES_KEY \ AES Encryption and Decryption
- $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
- 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
-$141 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
- $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
- 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
-$142 constant TRX_STATE \ Transceiver State Control Regi
- $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
- $1f constant TRX_STATE_TRX_CMD \ State Control Command
- 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
-$143 constant TRX_CTRL_0 \ Reserved
- $80 constant TRX_CTRL_0_Res7 \ Reserved
- 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
- $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
- 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
- $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
- 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
- $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
- 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
- $f constant TRX_CTRL_0_Res \ Reserved
- 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
-$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
- $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
- 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
- $f constant TRX_CTRL_1_Res \ Reserved
- 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
-$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
- $f0 constant PHY_TX_PWR_Res \ Reserved
- 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
- $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
- 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
-$146 constant PHY_RSSI \ Receiver Signal Strength Indic
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
- $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
- 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
-$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
- $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
- 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
-$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
- $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
- 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
-$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
- $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
- 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
- $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
- 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
-$14a constant RX_CTRL \ Transceiver Receive Control Re
- $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
- 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
-$14b constant SFD_VALUE \ Start of Frame Delimiter Value
- $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
- 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
-$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
- $7c constant TRX_CTRL_2_Res \ Reserved
- 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
- $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
- 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
-$14d constant ANT_DIV \ Antenna Diversity Control Regi
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
- 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
- $70 constant ANT_DIV_Res \ Reserved
- 14d $70 bitmask: ANT_DIV.Res \ Reserved
- $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
- $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
- 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
- $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
- 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
-$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
- 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
- $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
- $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
- $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
- 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
-$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
- 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
- $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
- $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
- $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
- $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
- 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
-$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
- $e0 constant IRQ_MASK1_Res \ Reserved Bit
- be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
- $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
- be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
- $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
- be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
- $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
- be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
- $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
- be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
- $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
- be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
-$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
- $e0 constant IRQ_STATUS1_Res \ Reserved Bit
- bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
- $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
- bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
- $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
- bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
- $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
- bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
- $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
- bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
- $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
- bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
-$150 constant VREG_CTRL \ Voltage Regulator Control and
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
- $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
- $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
- 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
-$151 constant BATMON \ Battery Monitor Control and St
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
- 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
- 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
- $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
- 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
-$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
- $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
- 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
- $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
- 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
-$153 constant CC_CTRL_0 \ Channel Control Register 0
- $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
- 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
-$154 constant CC_CTRL_1 \ Channel Control Register 1
- $f constant CC_CTRL_1_CC_BAND \ Channel Band
- 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
-$155 constant RX_SYN \ Transceiver Receiver Sensitivi
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
- $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
- 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
- $30 constant RX_SYN_Res \ Reserved
- 155 $30 bitmask: RX_SYN.Res \ Reserved
- $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
- 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-$156 constant TRX_RPC \ Transceiver Reduced Power Cons
- $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
- 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
- $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
- 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
- $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
- 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
- $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
- $4 constant TRX_RPC_Res0 \ Reserved
- 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
- $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
- $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
- 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
-$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
- $c0 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
- $8 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
- $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
- $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
- $1 constant XAH_CTRL_1_Res \ Reserved Bit
- 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
-$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
- 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
-$15a constant PLL_CF \ Transceiver Center Frequency C
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
- 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
-$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
- 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
-$15c constant PART_NUM \ Device Identification Register
- $ff constant PART_NUM_PART_NUM \ Part Number
- 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
-$15d constant VERSION_NUM \ Device Identification Register
- $ff constant VERSION_NUM_VERSION_NUM \ Version Number
- 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
-$15e constant MAN_ID_0 \ Device Identification Register
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
- $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
- $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
- $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
- $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
- 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
-$15f constant MAN_ID_1 \ Device Identification Register
- $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
- 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
-$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
- $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
- $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
- $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
- $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
- 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
-$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
- $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
- 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
-$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
- $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
- $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
- $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
- $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
- 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
-$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
- $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
- 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
-$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
- $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
- $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
- $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
- $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
- 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
-$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
- 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
-$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
- 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
-$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
- 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
-$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
- 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
-$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
- 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
-$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
- 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
-$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
- $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
- 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
-$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
- $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
- $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
- $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
- 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
-$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
- 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
- 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
- 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
- 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
- $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
- 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
- $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
- 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
- $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
- 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
- $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
- 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
-$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
- $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
- 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
- $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
- 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
- $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
- 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
-$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
- $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
- $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
- 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
-$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
- $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
- 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
-$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
- $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
- 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
-$180 constant TRXFBST \ Start of frame buffer
-$1ff constant TRXFBEND \ End of frame buffer
-\ SYMCNT
-$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
- fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
-$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
- fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
-$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
- fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
-$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
- $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
- f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
-$f8 constant SCOCR1HH \ Symbol Counter Output Compare
- $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
- f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
-$f7 constant SCOCR1HL \ Symbol Counter Output Compare
- $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
- f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
-$f6 constant SCOCR1LH \ Symbol Counter Output Compare
- $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
- f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
-$f5 constant SCOCR1LL \ Symbol Counter Output Compare
- $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
- f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
-$f4 constant SCOCR2HH \ Symbol Counter Output Compare
- $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
- f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
-$f3 constant SCOCR2HL \ Symbol Counter Output Compare
- $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
- f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
-$f2 constant SCOCR2LH \ Symbol Counter Output Compare
- $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
- f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
-$f1 constant SCOCR2LL \ Symbol Counter Output Compare
- $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
- f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
-$f0 constant SCOCR3HH \ Symbol Counter Output Compare
- $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
- f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
-$ef constant SCOCR3HL \ Symbol Counter Output Compare
- $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
- ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
-$ee constant SCOCR3LH \ Symbol Counter Output Compare
- $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
- ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
-$ed constant SCOCR3LL \ Symbol Counter Output Compare
- $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
- ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
-$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
- ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
-$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
- eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
-$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
- ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
-$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
- $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
- e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
-$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
- e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
-$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
- e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
-$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
- e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
-$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
- $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
- e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
-$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
- $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
- e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
-$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
- $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
- e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
-$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
- $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
- e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
-$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
- $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
- e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
-$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
- $e0 constant SCIRQS_Res \ Reserved Bit
- e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
- $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
- $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
- e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
-$df constant SCIRQM \ Symbol Counter Interrupt Mask
- $e0 constant SCIRQM_Res \ Reserved Bit
- df $e0 bitmask: SCIRQM.Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
- df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
- $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
- df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
- $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
- df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
-$de constant SCSR \ Symbol Counter Status Register
- $fe constant SCSR_Res \ Reserved Bit
- de $fe bitmask: SCSR.Res \ Reserved Bit
- $1 constant SCSR_SCBSY \ Symbol Counter busy
- de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
-$dd constant SCCR1 \ Symbol Counter Control Registe
- $c0 constant SCCR1_Res \ Reserved Bit
- dd $c0 bitmask: SCCR1.Res \ Reserved Bit
- $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
- dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
- $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
- dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
- $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
- dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
- $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
- dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
-$dc constant SCCR0 \ Symbol Counter Control Registe
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
- dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
- $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
- dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
- $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
- dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
-$db constant SCCSR \ Symbol Counter Compare Source
- $c0 constant SCCSR_Res \ Reserved Bit
- db $c0 bitmask: SCCSR.Res \ Reserved Bit
- $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
- db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
- $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
- db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
- $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
- db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
-$da constant SCRSTRHH \ Symbol Counter Received Frame
- $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
- da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
-$d9 constant SCRSTRHL \ Symbol Counter Received Frame
- $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
- d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
-$d8 constant SCRSTRLH \ Symbol Counter Received Frame
- $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
- d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
-$d7 constant SCRSTRLL \ Symbol Counter Received Frame
- $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
- d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Bytes
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $c0 constant EECR_Res \ Reserved
- 3f $c0 bitmask: EECR.Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Programming Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Register
- $ff constant OCDR_OCDR \ On-Chip Debug Register Data
- 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
- 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
- $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
- $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
-$6a constant EICRB \ External Interrupt Control Reg
- $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
- 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
- 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
- $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
- 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
- $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
- 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
-$3d constant EIMSK \ External Interrupt Mask Regist
- $ff constant EIMSK_INT \ External Interrupt Request Ena
- 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
-$3c constant EIFR \ External Interrupt Flag Regist
- $ff constant EIFR_INTF \ External Interrupt Flag
- 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
-$6b constant PCMSK0 \ Pin Change Mask Register 0
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f8 constant PCIFR_Res \ Reserved Bit
- 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
- $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f8 constant PCICR_Res \ Reserved Bit
- 68 $f8 bitmask: PCICR.Res \ Reserved Bit
- $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC Multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status Reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status Reg
- $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
- 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
- $20 constant ADCSRB_REFOK \ Reference Voltage OK
- 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
- $10 constant ADCSRB_ACCH \ Analog Channel Change
- 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
- $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
- 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
-$77 constant ADCSRC \ The ADC Control and Status Reg
- $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- 77 $20 bitmask: ADCSRC.Res0 \ Reserved
- $1f constant ADCSRC_ADSUT \ ADC Start-up Time
- 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
-$7d constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \ Reserved Bits
- 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
- $8 constant DIDR2_ADC11D \ Reserved Bits
- 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
- $4 constant DIDR2_ADC10D \ Reserved Bits
- 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
- $2 constant DIDR2_ADC9D \ Reserved Bits
- 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
- $1 constant DIDR2_ADC8D \ Reserved Bits
- 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
- $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
- $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
- $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
- $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
- 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $60 constant MCUCR_Res \ Reserved
- 55 $60 bitmask: MCUCR.Res \ Reserved
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
- $c constant MCUCR_Res \ Reserved
- 55 $c bitmask: MCUCR.Res \ Reserved
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $e0 constant MCUSR_Res \ Reserved
- 54 $e0 bitmask: MCUSR.Res \ Reserved
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on Reset Flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
-$66 constant OSCCAL \ Oscillator Calibration Value
- $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
- 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
-$61 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- 61 $70 bitmask: CLKPR.Res \ Reserved
- $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
- 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
-$53 constant SMCR \ Sleep Mode Control Register
- $f0 constant SMCR_Res \ Reserved
- 53 $f0 bitmask: SMCR.Res \ Reserved
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$5c constant EIND \ Extended Indirect Register
-$5b constant RAMPZ \ Extended Z-pointer Register fo
- $fc constant RAMPZ_Res \ Reserved
- 5b $fc bitmask: RAMPZ.Res \ Reserved
- $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
- 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
-$4b constant GPIOR2 \ General Purpose I/O Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
-$63 constant PRR2 \ Power Reduction Register 2
- $f0 constant PRR2_Res \ Reserved Bit
- 63 $f0 bitmask: PRR2.Res \ Reserved Bit
- $f constant PRR2_PRRAM \ Power Reduction SRAMs
- 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
-$65 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- 65 $80 bitmask: PRR1.Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
- $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
- $1 constant PRR1_PRUSART1 \ Power Reduction USART1
- 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $2 constant PRR0_PRUSART0 \ Power Reduction USART
- 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
-\ FLASH
-$75 constant NEMCR \ Flash Extended-Mode Control-Re
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
- 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
- $30 constant NEMCR_AEAM \ Address for Extended Address M
- 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
-$67 constant BGCR \ Reference Voltage Calibration
- $80 constant BGCR_Res \ Reserved Bit
- 67 $80 bitmask: BGCR.Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
- $7 constant BGCR_BGCAL \ Coarse Calibration Bits
- 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
-\ PWRCTRL
-$139 constant TRXPR \ Transceiver Pin Register
- $f0 constant TRXPR_Res \ Reserved
- 139 $f0 bitmask: TRXPR.Res \ Reserved
- $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
- 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
- $1 constant TRXPR_TRXRST \ Force Transceiver Reset
- 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
-$135 constant DRTRAM0 \ Data Retention Configuration R
- $c0 constant DRTRAM0_Res \ Reserved
- 135 $c0 bitmask: DRTRAM0.Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
- 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
-$134 constant DRTRAM1 \ Data Retention Configuration R
- $c0 constant DRTRAM1_Res \ Reserved
- 134 $c0 bitmask: DRTRAM1.Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
- 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
-$133 constant DRTRAM2 \ Data Retention Configuration R
- $40 constant DRTRAM2_Res \ Reserved Bit
- 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
- 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
-$132 constant DRTRAM3 \ Data Retention Configuration R
- $c0 constant DRTRAM3_Res \ Reserved
- 132 $c0 bitmask: DRTRAM3.Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
- 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
-$130 constant LLDRL \ Low Leakage Voltage Regulator
- $f0 constant LLDRL_Res \ Reserved
- 130 $f0 bitmask: LLDRL.Res \ Reserved
- $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
- 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
-$131 constant LLDRH \ Low Leakage Voltage Regulator
- $e0 constant LLDRH_Res \ Reserved
- 131 $e0 bitmask: LLDRH.Res \ Reserved
- $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
- 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
-$12f constant LLCR \ Low Leakage Voltage Regulator
- $c0 constant LLCR_Res \ Reserved Bit
- 12f $c0 bitmask: LLCR.Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
- $8 constant LLCR_LLCAL \ Calibration Active
- 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
- $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
- 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
- $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
- 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
- $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
- 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
-$136 constant DPDS0 \ Port Driver Strength Register
- $c0 constant DPDS0_PFDRV \ Driver Strength Port F
- 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
- $c constant DPDS0_PDDRV \ Driver Strength Port D
- 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
- $3 constant DPDS0_PBDRV \ Driver Strength Port B
- 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
-$137 constant DPDS1 \ Port Driver Strength Register
- $fc constant DPDS1_Res \ Reserved
- 137 $fc bitmask: DPDS1.Res \ Reserved
- $3 constant DPDS1_PGDRV \ Driver Strength Port G
- 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
-$55 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up Disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
-\ USART0_SPI
-$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
-$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
-$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
- $4 constant UCSR0C_UDORD0 \ Data Order
- c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
- $2 constant UCSR0C_UCPHA0 \ Clock Phase
- c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-\ USART1_SPI
-$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
-$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
-$ca constant UCSR1C \ USART1 MSPIM Control and Statu
- $4 constant UCSR1C_UDORD1 \ Data Order
- ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
- $2 constant UCSR1C_UCPHA1 \ Clock Phase
- ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.py b/amforth-6.5/avr8/devices/atmega256rfr2/device.py
deleted file mode 100644
index 14b2cdc..0000000
--- a/amforth-6.5/avr8/devices/atmega256rfr2/device.py
+++ /dev/null
@@ -1,1104 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega256RFR2
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
- 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
- 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
- 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
- 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
- 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
- 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
- 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
- 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
- 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
- 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
- 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
- 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
- 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
- 'AES_READYAddr' : '#140', # AES engine ready interrupt
- 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
- 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
- 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
- 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
- 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
- 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART0 I/O Data Register
- 'UCSR0A' : '$c0', # USART0 Control and Status Regi
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Frame Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART0 Control and Status Regi
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART0 Control and Status Regi
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART1 I/O Data Register
- 'UCSR1A' : '$c8', # USART1 Control and Status Regi
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Frame Error
- 'UCSR1A_DOR1': '$8', # Data OverRun
- 'UCSR1A_UPE1': '$4', # USART Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART Transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART1 Control and Status Regi
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART1 Control and Status Regi
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', # TWI Address Mask
- 'TWAMR_Res': '$1', # Reserved Bit
- 'TWBR' : '$b8', # TWI Bit Rate Register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI START Condition Bit
- 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collision Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_Res': '$2', # Reserved Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_Res': '$4', # Reserved Bit
- 'TWSR_TWPS': '$3', # TWI Prescaler Bits
- 'TWDR' : '$bb', # TWI Data Register
- 'TWAR' : '$ba', # TWI (Slave) Address Register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_Res': '$3e', # Reserved
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins Address
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins Address
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins Address
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins Address
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins Address
-
-# Module PORTF
- 'PORTF' : '$31', # Port F Data Register
- 'DDRF' : '$30', # Port F Data Direction Register
- 'PINF' : '$2f', # Port F Input Pins Address
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins Address
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0 Register
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_Res': '$30', # Reserved Bit
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
- 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
- 'TCCR0A_Res': '$c', # Reserved Bit
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_Res': '$f8', # Reserved
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_Res': '$f8', # Reserved
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_Res': '$7c', # Reserved
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_Res': '$f8', # Reserved Bit
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_Res': '$f8', # Reserved Bit
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
- 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
- 'TCCR2A_Res': '$c', # Reserved
- 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_Res': '$30', # Reserved
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
- 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
- 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
- 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
- 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
- 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_Res': '$20', # Reserved Bit
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Clock Select
- 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
- 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
- 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
- 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
- 'TCCR5C_Res': '$1f', # Reserved
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_Res': '$c0', # Reserved Bit
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_Res': '$10', # Reserved Bit
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_Res': '$c0', # Reserved Bit
- 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
- 'TIFR5_Res': '$10', # Reserved Bit
- 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
- 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
- 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_Res': '$20', # Reserved Bit
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Clock Select
- 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
- 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
- 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
- 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
- 'TCCR4C_Res': '$1f', # Reserved
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_Res': '$c0', # Reserved Bit
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_Res': '$10', # Reserved Bit
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_Res': '$c0', # Reserved Bit
- 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
- 'TIFR4_Res': '$10', # Reserved Bit
- 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
- 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
- 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_Res': '$20', # Reserved Bit
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
- 'TCCR3C_Res': '$1f', # Reserved
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_Res': '$c0', # Reserved Bit
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_Res': '$10', # Reserved Bit
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_Res': '$c0', # Reserved Bit
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_Res': '$10', # Reserved Bit
- 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
- 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
- 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_Res': '$20', # Reserved Bit
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
- 'TCCR1C_Res': '$1f', # Reserved
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_Res': '$c0', # Reserved Bit
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_Res': '$10', # Reserved Bit
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_Res': '$c0', # Reserved Bit
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_Res': '$10', # Reserved Bit
- 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TRX24
- 'PARCR' : '$138', # Power Amplifier Ramp up/down C
- 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
- 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
- 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
- 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
- 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
- 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
- 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
- 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
- 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
- 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA1L' : '$112', # Transceiver MAC Short Address
- 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
- 'MAFSA1H' : '$113', # Transceiver MAC Short Address
- 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
- 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
- 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA2L' : '$116', # Transceiver MAC Short Address
- 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
- 'MAFSA2H' : '$117', # Transceiver MAC Short Address
- 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
- 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
- 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
- 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
- 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
- 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
- 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
- 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
- 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
- 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
- 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
- 'MAFCR0' : '$10c', # Multiple Address Filter Config
- 'MAFCR0_Res': '$f0', # Reserved Bit
- 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
- 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
- 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
- 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
- 'MAFCR1' : '$10d', # Multiple Address Filter Config
- 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
- 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
- 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
- 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
- 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
- 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
- 'AES_CTRL' : '$13c', # AES Control Register
- 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
- 'AES_CTRL_Res': '$40', # Reserved Bit
- 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
- 'AES_CTRL_Res': '$10', # Reserved Bit
- 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
- 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
- 'AES_CTRL_Res': '$3', # Reserved Bit
- 'AES_STATUS' : '$13d', # AES Status Register
- 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
- 'AES_STATUS_Res': '$7e', # Reserved
- 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
- 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
- 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
- 'AES_KEY' : '$13f', # AES Encryption and Decryption
- 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
- 'TRX_STATUS' : '$141', # Transceiver Status Register
- 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
- 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
- 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
- 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
- 'TRX_STATE' : '$142', # Transceiver State Control Regi
- 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
- 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
- 'TRX_CTRL_0' : '$143', # Reserved
- 'TRX_CTRL_0_Res7': '$80', # Reserved
- 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
- 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
- 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
- 'TRX_CTRL_0_Res': '$f', # Reserved
- 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
- 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
- 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
- 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
- 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
- 'TRX_CTRL_1_Res': '$f', # Reserved
- 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
- 'PHY_TX_PWR_Res': '$f0', # Reserved
- 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
- 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
- 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
- 'PHY_RSSI_RND_VALUE': '$60', # Random Value
- 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
- 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
- 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
- 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
- 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
- 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
- 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
- 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
- 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
- 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
- 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
- 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
- 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
- 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
- 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
- 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
- 'TRX_CTRL_2_Res': '$7c', # Reserved
- 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
- 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
- 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
- 'ANT_DIV_Res': '$70', # Reserved
- 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
- 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
- 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
- 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
- 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
- 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
- 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
- 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
- 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
- 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
- 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
- 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
- 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
- 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
- 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
- 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
- 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
- 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
- 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
- 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
- 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
- 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
- 'IRQ_MASK1_Res': '$e0', # Reserved Bit
- 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
- 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
- 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
- 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
- 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
- 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
- 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
- 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
- 'VREG_CTRL' : '$150', # Voltage Regulator Control and
- 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
- 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
- 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
- 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
- 'BATMON' : '$151', # Battery Monitor Control and St
- 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
- 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
- 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
- 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
- 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
- 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
- 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
- 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
- 'CC_CTRL_0' : '$153', # Channel Control Register 0
- 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
- 'CC_CTRL_1' : '$154', # Channel Control Register 1
- 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
- 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
- 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
- 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
- 'RX_SYN_Res': '$30', # Reserved
- 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
- 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
- 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
- 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
- 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
- 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
- 'TRX_RPC_Res0': '$4', # Reserved
- 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
- 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
- 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
- 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
- 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
- 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
- 'XAH_CTRL_1_Res': '$8', # Reserved Bit
- 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
- 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
- 'XAH_CTRL_1_Res': '$1', # Reserved Bit
- 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
- 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
- 'PLL_CF' : '$15a', # Transceiver Center Frequency C
- 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
- 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
- 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
- 'PART_NUM' : '$15c', # Device Identification Register
- 'PART_NUM_PART_NUM': '$ff', # Part Number
- 'VERSION_NUM' : '$15d', # Device Identification Register
- 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
- 'MAN_ID_0' : '$15e', # Device Identification Register
- 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
- 'MAN_ID_1' : '$15f', # Device Identification Register
- 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
- 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
- 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
- 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
- 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
- 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
- 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
- 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
- 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
- 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
- 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
- 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
- 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
- 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
- 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
- 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
- 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
- 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
- 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
- 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
- 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
- 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
- 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
- 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
- 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
- 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
- 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
- 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
- 'TRXFBST' : '$180', # Start of frame buffer
- 'TRXFBEND' : '$1ff', # End of frame buffer
-
-# Module SYMCNT
- 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
- 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
- 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
- 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
- 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
- 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
- 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
- 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
- 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
- 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
- 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
- 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
- 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
- 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
- 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
- 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
- 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
- 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
- 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
- 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
- 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
- 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
- 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
- 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
- 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
- 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
- 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
- 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
- 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
- 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
- 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
- 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
- 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
- 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
- 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
- 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
- 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
- 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
- 'SCIRQS_Res': '$e0', # Reserved Bit
- 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
- 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
- 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
- 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
- 'SCIRQM_Res': '$e0', # Reserved Bit
- 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
- 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
- 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
- 'SCSR' : '$de', # Symbol Counter Status Register
- 'SCSR_Res': '$fe', # Reserved Bit
- 'SCSR_SCBSY': '$1', # Symbol Counter busy
- 'SCCR1' : '$dd', # Symbol Counter Control Registe
- 'SCCR1_Res': '$c0', # Reserved Bit
- 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
- 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
- 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
- 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
- 'SCCR0' : '$dc', # Symbol Counter Control Registe
- 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
- 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
- 'SCCR0_SCEN': '$20', # Symbol Counter enable
- 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
- 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
- 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
- 'SCCSR' : '$db', # Symbol Counter Compare Source
- 'SCCSR_Res': '$c0', # Reserved Bit
- 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
- 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
- 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
- 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
- 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
- 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
- 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
- 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
- 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_Res': '$c0', # Reserved
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
- 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
- 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
- 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
- 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
- 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
- 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request Ena
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flag
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_Res': '$f8', # Reserved Bit
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_Res': '$f8', # Reserved Bit
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC Multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status Reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status Reg
- 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ADCSRB_REFOK': '$20', # Reference Voltage OK
- 'ADCSRB_ACCH': '$10', # Analog Channel Change
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
- 'ADCSRC' : '$77', # The ADC Control and Status Reg
- 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
- 'ADCSRC_Res0': '$20', # Reserved
- 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', # Reserved Bits
- 'DIDR2_ADC14D': '$40', # Reserved Bits
- 'DIDR2_ADC13D': '$20', # Reserved Bits
- 'DIDR2_ADC12D': '$10', # Reserved Bits
- 'DIDR2_ADC11D': '$8', # Reserved Bits
- 'DIDR2_ADC10D': '$4', # Reserved Bits
- 'DIDR2_ADC9D': '$2', # Reserved Bits
- 'DIDR2_ADC8D': '$1', # Reserved Bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_Res': '$60', # Reserved
- 'MCUCR_PUD': '$10', # Pull-up Disable
- 'MCUCR_Res': '$c', # Reserved
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_Res': '$e0', # Reserved
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on Reset Flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_Res': '$70', # Reserved
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_Res': '$f0', # Reserved
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
- 'RAMPZ_Res': '$fc', # Reserved
- 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
- 'PRR2' : '$63', # Power Reduction Register 2
- 'PRR2_Res': '$f0', # Reserved Bit
- 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
- 'PRR1' : '$65', # Power Reduction Register 1
- 'PRR1_Res': '$80', # Reserved Bit
- 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRPGA': '$10', # Power Reduction PGA
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module FLASH
- 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
- 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
- 'NEMCR_AEAM': '$30', # Address for Extended Address M
- 'BGCR' : '$67', # Reference Voltage Calibration
- 'BGCR_Res': '$80', # Reserved Bit
- 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
- 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
-
-# Module PWRCTRL
- 'TRXPR' : '$139', # Transceiver Pin Register
- 'TRXPR_Res': '$f0', # Reserved
- 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
- 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
- 'DRTRAM0' : '$135', # Data Retention Configuration R
- 'DRTRAM0_Res': '$c0', # Reserved
- 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM1' : '$134', # Data Retention Configuration R
- 'DRTRAM1_Res': '$c0', # Reserved
- 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM2' : '$133', # Data Retention Configuration R
- 'DRTRAM2_Res': '$40', # Reserved Bit
- 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM3' : '$132', # Data Retention Configuration R
- 'DRTRAM3_Res': '$c0', # Reserved
- 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
- 'LLDRL' : '$130', # Low Leakage Voltage Regulator
- 'LLDRL_Res': '$f0', # Reserved
- 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
- 'LLDRH' : '$131', # Low Leakage Voltage Regulator
- 'LLDRH_Res': '$e0', # Reserved
- 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
- 'LLCR' : '$12f', # Low Leakage Voltage Regulator
- 'LLCR_Res': '$c0', # Reserved Bit
- 'LLCR_LLDONE': '$20', # Calibration Done
- 'LLCR_LLCOMP': '$10', # Comparator Output
- 'LLCR_LLCAL': '$8', # Calibration Active
- 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
- 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
- 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
- 'DPDS0' : '$136', # Port Driver Strength Register
- 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
- 'DPDS0_PEDRV': '$30', # Driver Strength Port E
- 'DPDS0_PDDRV': '$c', # Driver Strength Port D
- 'DPDS0_PBDRV': '$3', # Driver Strength Port B
- 'DPDS1' : '$137', # Port Driver Strength Register
- 'DPDS1_Res': '$fc', # Reserved
- 'DPDS1_PGDRV': '$3', # Driver Strength Port G
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up Disable
-
-# Module USART0_SPI
- 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
- 'UCSR0C_UDORD0': '$4', # Data Order
- 'UCSR0C_UCPHA0': '$2', # Clock Phase
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
-
-# Module USART1_SPI
- 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
- 'UCSR1C_UDORD1': '$4', # Data Order
- 'UCSR1C_UCPHA1': '$2', # Clock Phase
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32/atmega32.frt b/amforth-6.5/avr8/devices/atmega32/atmega32.frt
deleted file mode 100644
index 522ee66..0000000
--- a/amforth-6.5/avr8/devices/atmega32/atmega32.frt
+++ /dev/null
@@ -1,216 +0,0 @@
-\ Partname: ATmega32
-\ generated automatically
-
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDTOE \ RW
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
-&85 constant MCUCR \ General Interrupt Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&92 constant OCR0 \ Output Compare Register
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Pulse Width Modulator Enable
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Clear Timer/Counter2 on Compare Match
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ ANALOG_COMPARATOR
-&80 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&81 constant OSCCAL \ Oscillator Calibration Value
-\ BOOT_LOAD
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read While Write secion read enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler bits
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ Serial Transfer Complete
-&26 constant USART__RXCAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data Register Empty
-&30 constant USART__TXCAddr \ USART, Tx Complete
-&32 constant ADCAddr \ ADC Conversion Complete
-&34 constant EE_RDYAddr \ EEPROM Ready
-&36 constant ANA_COMPAddr \ Analog Comparator
-&38 constant TWIAddr \ 2-wire Serial Interface
-&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega32/device.asm b/amforth-6.5/avr8/devices/atmega32/device.asm
deleted file mode 100644
index 4e25271..0000000
--- a/amforth-6.5/avr8/devices/atmega32/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega32
-; generated automatically, do not edit
-
-.nolist
- .include "m32def.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_EEPROM = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_SPI = 0
-.set WANT_USART = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_TWI = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter1 Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data Register Empty
-.org 30
- rcall isr ; USART, Tx Complete
-.org 32
- rcall isr ; ADC Conversion Complete
-.org 34
- rcall isr ; EEPROM Ready
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; 2-wire Serial Interface
-.org 40
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 21
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 8
- .db "ATmega32"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32/device.inc b/amforth-6.5/avr8/devices/atmega32/device.inc
deleted file mode 100644
index fec57ca..0000000
--- a/amforth-6.5/avr8/devices/atmega32/device.inc
+++ /dev/null
@@ -1,750 +0,0 @@
-; Partname: ATmega32
-; generated automatically, no not edit
-
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32/device.py b/amforth-6.5/avr8/devices/atmega32/device.py
deleted file mode 100644
index 73c9f77..0000000
--- a/amforth-6.5/avr8/devices/atmega32/device.py
+++ /dev/null
@@ -1,268 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # Serial Transfer Complete
- 'USART_RXCAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data Register Empty
- 'USART_TXCAddr' : '#30', # USART, Tx Complete
- 'ADCAddr' : '#32', # ADC Conversion Complete
- 'EE_RDYAddr' : '#34', # EEPROM Ready
- 'ANA_COMPAddr' : '#36', # Analog Comparator
- 'TWIAddr' : '#38', # 2-wire Serial Interface
- 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDTOE': '$10', # RW
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EXTERNAL_INTERRUPT
- 'GICR' : '$5b', # General Interrupt Control Regi
- 'GICR_INT': '$c0', # External Interrupt Request 1 E
- 'GICR_INT2': '$20', # External Interrupt Request 2 E
- 'GICR_IVSEL': '$2', # Interrupt Vector Select
- 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
- 'GIFR' : '$5a', # General Interrupt Flag Registe
- 'GIFR_INTF': '$c0', # External Interrupt Flags
- 'GIFR_INTF2': '$20', # External Interrupt Flag 2
- 'MCUCR' : '$55', # General Interrupt Control Regi
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$5c', # Output Compare Register
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
- 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
- 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TCCR2' : '$45', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Pulse Width Modulator Enable
- 'TCCR2_COM2': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Clear Timer/Counter2 on Compar
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$44', # Timer/Counter2
- 'OCR2' : '$43', # Timer/Counter2 Output Compare
- 'ASSR' : '$42', # Asynchronous Status Register
- 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
- 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
- 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module USART
- 'UDR' : '$2c', # USART I/O Data Register
- 'UCSRA' : '$2b', # USART Control and Status Regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data overRun
- 'UCSRA_UPE': '$4', # Parity Error
- 'UCSRA_U2X': '$2', # Double the USART transmission
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$2a', # USART Control and Status Regis
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$40', # USART Control and Status Regis
- 'UCSRC_URSEL': '$80', # Register Select
- 'UCSRC_UMSEL': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$40', # USART Baud Rate Register Hight
- 'UBRRL' : '$29', # USART Baud Rate Register Low B
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # When this bit is written to on
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$24', # ADC Data Register Bytes
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SE': '$80', # Sleep Enable
- 'MCUCR_SM': '$70', # Sleep Mode Select
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$51', # Oscillator Calibration Value
- 'SFIOR' : '$50', # Special Function IO Register
-
-# Module BOOT_LOAD
- 'SPMCR' : '$57', # Store Program Memory Control R
- 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCR_RWWSRE': '$10', # Read While Write secion read e
- 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCR_PGWRT': '$4', # Page Write
- 'SPMCR_PGERS': '$2', # Page Erase
- 'SPMCR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module TWI
- 'TWBR' : '$20', # TWI Bit Rate register
- 'TWCR' : '$56', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$21', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler bits
- 'TWDR' : '$23', # TWI Data register
- 'TWAR' : '$22', # TWI (Slave) Address register
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega32/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega32/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega323/atmega323.frt b/amforth-6.5/avr8/devices/atmega323/atmega323.frt
deleted file mode 100644
index bb14f0a..0000000
--- a/amforth-6.5/avr8/devices/atmega323/atmega323.frt
+++ /dev/null
@@ -1,123 +0,0 @@
-\ Partname: ATmega323
-\ Built using part description XML file version 203
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-25 constant ADCH \ ADC Data Register High Byte
-24 constant ADCL \ ADC Data Register Low Byte
-26 constant ADCSR \ The ADC Control and Status register
-27 constant ADMUX \ The ADC multiplexer Selection Register
-
-\ ANALOG_COMPARATOR
-28 constant ACSR \ Analog Comparator Control And Status Register
-50 constant SFIOR \ Special Function IO Register
-
-\ CPU
-55 constant MCUCR \ MCU Control Register
-54 constant MCUCSR \ MCU Control And Status Register
-51 constant OSCCAL \ Oscillator Calibration Value
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-57 constant SPMCR \ Store Program Memory Control Register
-5F constant SREG \ Status Register
-
-\ EEPROM
-3F constant EEARH \ EEPROM Read/Write Access High Byte
-3E constant EEARL \ EEPROM Read/Write Access Low Byte
-3C constant EECR \ EEPROM Control Register
-3D constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-5B constant GICR \ General Interrupt Control Register
-5A constant GIFR \ General Interrupt Flag Register
-
-\ PORTA
-3A constant DDRA \ Port A Data Direction Register
-39 constant PINA \ Port A Input Pins
-3B constant PORTA \ Port A Data Register
-
-\ PORTB
-37 constant DDRB \ Port B Data Direction Register
-36 constant PINB \ Port B Input Pins
-38 constant PORTB \ Port B Data Register
-
-\ PORTC
-34 constant DDRC \ Port C Data Direction Register
-33 constant PINC \ Port C Input Pins
-35 constant PORTC \ Port C Data Register
-
-\ PORTD
-31 constant DDRD \ Port D Data Direction Register
-30 constant PIND \ Port D Input Pins
-32 constant PORTD \ Port D Data Register
-
-\ SPI
-2D constant SPCR \ SPI Control Register
-2F constant SPDR \ SPI Data Register
-2E constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-5C constant OCR0 \ Output Compare Register
-53 constant TCCR0 \ Timer/Counter Control Register
-52 constant TCNT0 \ Timer/Counter Register
-58 constant TIFR \ Timer/Counter Interrupt Flag register
-59 constant TIMSK \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-4F constant TCCR1A \ Timer/Counter1 Control Register A
-4E constant TCCR1B \ Timer/Counter1 Control Register B
-4D constant TCNT1H \ Timer/Counter1 High Byte
-4C constant TCNT1L \ Timer/Counter1 Low Byte
-
-\ TIMER_COUNTER_2
-42 constant ASSR \ Asynchronous Status Register
-43 constant OCR2 \ Timer/Counter2 Output Compare Register
-45 constant TCCR2 \ Timer/Counter2 Control Register
-44 constant TCNT2 \ Timer/Counter2
-
-\ TWI
-22 constant TWAR \ TWI (Slave) Address register
-20 constant TWBR \ TWI Bit Rate register
-56 constant TWCR \ TWI Control Register
-23 constant TWDR \ TWI Data register
-21 constant TWSR \ TWI Status Register
-
-\ USART
-40 constant UBRRH \ USART Baud Rate Register Hight Byte
-29 constant UBRRL \ USART Baud Rate Register Low Byte
-2B constant UCSRA \ USART Control and Status Register A
-2A constant UCSRB \ USART Control and Status Register B
-2C constant UDR \ USART I/O Data Register
-
-\ WATCHDOG
-41 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt Request 0
-004 constant INT1Addr \ External Interrupt Request 1
-006 constant INT2Addr \ External Interrupt Request 2
-008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-010 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-018 constant SPI_STCAddr \ Serial Transfer Complete
-01A constant USART_RXCAddr \ USART, Rx Complete
-01C constant USART_UDREAddr \ USART Data Register Empty
-01E constant USART_TXCAddr \ USART, Tx Complete
-020 constant ADCAddr \ ADC Conversion Complete
-022 constant EE_RDYAddr \ EEPROM Ready
-024 constant ANA_COMPAddr \ Analog Comparator
-026 constant TWIAddr \ 2-wire Serial Interface
-28 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega323/device.asm b/amforth-6.5/avr8/devices/atmega323/device.asm
deleted file mode 100644
index bc753f4..0000000
--- a/amforth-6.5/avr8/devices/atmega323/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: ATmega323
-; Built using part description XML file version 203
-; generated automatically, do not edit
-
-.nolist
- .include "m323def.inc"
-.list
-
-.equ ramstart = $60
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TWI = 0
-.set WANT_USART = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 21
-.org $002
- rcall isr ; External Interrupt Request 0
-.org $004
- rcall isr ; External Interrupt Request 1
-.org $006
- rcall isr ; External Interrupt Request 2
-.org $008
- rcall isr ; Timer/Counter2 Compare Match
-.org $00A
- rcall isr ; Timer/Counter2 Overflow
-.org $00C
- rcall isr ; Timer/Counter1 Capture Event
-.org $00E
- rcall isr ; Timer/Counter1 Compare Match A
-.org $010
- rcall isr ; Timer/Counter1 Compare Match B
-.org $012
- rcall isr ; Timer/Counter1 Overflow
-.org $014
- rcall isr ; Timer/Counter0 Compare Match
-.org $016
- rcall isr ; Timer/Counter0 Overflow
-.org $018
- rcall isr ; Serial Transfer Complete
-.org $01A
- rcall isr ; USART, Rx Complete
-.org $01C
- rcall isr ; USART Data Register Empty
-.org $01E
- rcall isr ; USART, Tx Complete
-.org $020
- rcall isr ; ADC Conversion Complete
-.org $022
- rcall isr ; EEPROM Ready
-.org $024
- rcall isr ; Analog Comparator
-.org $026
- rcall isr ; 2-wire Serial Interface
-.org $28
- rcall isr ; Store Program Memory Ready
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 0 ; minimum of 0 (from XML) and 0xffff
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 9
- .db "ATmega323",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega323/device.inc b/amforth-6.5/avr8/devices/atmega323/device.inc
deleted file mode 100644
index 3027d03..0000000
--- a/amforth-6.5/avr8/devices/atmega323/device.inc
+++ /dev/null
@@ -1,867 +0,0 @@
-; Partname: ATmega323
-; Built using part description XML file version 203
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $25
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSR:
- .dw $ff05
- .db "ADCSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSR
-XT_ADCSR:
- .dw PFA_DOVARIABLE
-PFA_ADCSR:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $27
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $28
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw $50
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $51
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw $57
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw $5B
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw $5A
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $3B
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $38
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $34
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $33
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $35
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $31
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $32
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw $5C
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $52
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw $58
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw $59
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $4F
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $4D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $4C
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $44
-
-.endif
-
-; ********
-.if WANT_TWI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw $22
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw $56
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw $21
-
-.endif
-
-; ********
-.if WANT_USART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw $40
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw $2B
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw $2C
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $41
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega323/device.py b/amforth-6.5/avr8/devices/atmega323/device.py
deleted file mode 100644
index b954e83..0000000
--- a/amforth-6.5/avr8/devices/atmega323/device.py
+++ /dev/null
@@ -1,89 +0,0 @@
-# Partname: ATmega323
-# Built using part description XML file version 203
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$25',
- 'ADCL': '$24',
- 'ADCSR': '$26',
- 'ADMUX': '$27',
- 'ACSR': '$28',
- 'SFIOR': '$50',
- 'MCUCR': '$55',
- 'MCUCSR': '$54',
- 'OSCCAL': '$51',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SPMCR': '$57',
- 'SREG': '$5F',
- 'EEARH': '$3F',
- 'EEARL': '$3E',
- 'EECR': '$3C',
- 'EEDR': '$3D',
- 'GICR': '$5B',
- 'GIFR': '$5A',
- 'DDRA': '$3A',
- 'PINA': '$39',
- 'PORTA': '$3B',
- 'DDRB': '$37',
- 'PINB': '$36',
- 'PORTB': '$38',
- 'DDRC': '$34',
- 'PINC': '$33',
- 'PORTC': '$35',
- 'DDRD': '$31',
- 'PIND': '$30',
- 'PORTD': '$32',
- 'SPCR': '$2D',
- 'SPDR': '$2F',
- 'SPSR': '$2E',
- 'OCR0': '$5C',
- 'TCCR0': '$53',
- 'TCNT0': '$52',
- 'TIFR': '$58',
- 'TIMSK': '$59',
- 'ICR1H': '$47',
- 'ICR1L': '$46',
- 'OCR1AH': '$4B',
- 'OCR1AL': '$4A',
- 'OCR1BH': '$49',
- 'OCR1BL': '$48',
- 'TCCR1A': '$4F',
- 'TCCR1B': '$4E',
- 'TCNT1H': '$4D',
- 'TCNT1L': '$4C',
- 'ASSR': '$42',
- 'OCR2': '$43',
- 'TCCR2': '$45',
- 'TCNT2': '$44',
- 'TWAR': '$22',
- 'TWBR': '$20',
- 'TWCR': '$56',
- 'TWDR': '$23',
- 'TWSR': '$21',
- 'UBRRH': '$40',
- 'UBRRL': '$29',
- 'UCSRA': '$2B',
- 'UCSRB': '$2A',
- 'UDR': '$2C',
- 'WDTCR': '$41',
- 'INT0Addr': '$002',
- 'INT1Addr': '$004',
- 'INT2Addr': '$006',
- 'TIMER2_COMPAddr': '$008',
- 'TIMER2_OVFAddr': '$00A',
- 'TIMER1_CAPTAddr': '$00C',
- 'TIMER1_COMPAAddr': '$00E',
- 'TIMER1_COMPBAddr': '$010',
- 'TIMER1_OVFAddr': '$012',
- 'TIMER0_COMPAddr': '$014',
- 'TIMER0_OVFAddr': '$016',
- 'SPI_STCAddr': '$018',
- 'USART_RXCAddr': '$01A',
- 'USART_UDREAddr': '$01C',
- 'USART_TXCAddr': '$01E',
- 'ADCAddr': '$020',
- 'EE_RDYAddr': '$022',
- 'ANA_COMPAddr': '$024',
- 'TWIAddr': '$026',
- 'SPM_RDYAddr': '$28'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega324a/atmega324a.frt b/amforth-6.5/avr8/devices/atmega324a/atmega324a.frt
deleted file mode 100644
index 0299dc2..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/atmega324a.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega324A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega324a/device.asm b/amforth-6.5/avr8/devices/atmega324a/device.asm
deleted file mode 100644
index 2b22c76..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega324A
-; generated automatically, do not edit
-
-.nolist
- .include "m324Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega324A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega324a/device.inc b/amforth-6.5/avr8/devices/atmega324a/device.inc
deleted file mode 100644
index ab2771b..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega324A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega324a/device.py b/amforth-6.5/avr8/devices/atmega324a/device.py
deleted file mode 100644
index 8c0a285..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/device.py
+++ /dev/null
@@ -1,388 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega324A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART1': '$10', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USARTs
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega324a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega324a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega324a/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega324a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega324a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324p/atmega324p.frt b/amforth-6.5/avr8/devices/atmega324p/atmega324p.frt
deleted file mode 100644
index de8d590..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/atmega324p.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega324P
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega324p/device.asm b/amforth-6.5/avr8/devices/atmega324p/device.asm
deleted file mode 100644
index 09eee51..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega324P
-; generated automatically, do not edit
-
-.nolist
- .include "m324Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega324P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega324p/device.inc b/amforth-6.5/avr8/devices/atmega324p/device.inc
deleted file mode 100644
index 15f90e9..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega324P
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega324p/device.py b/amforth-6.5/avr8/devices/atmega324p/device.py
deleted file mode 100644
index 6cdc7eb..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/device.py
+++ /dev/null
@@ -1,390 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega324P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART1': '$10', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USARTs
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega324p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega324p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega324p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega324p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega324p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324pa/atmega324pa.frt b/amforth-6.5/avr8/devices/atmega324pa/atmega324pa.frt
deleted file mode 100644
index db288cd..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/atmega324pa.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega324PA
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega324pa/device.asm b/amforth-6.5/avr8/devices/atmega324pa/device.asm
deleted file mode 100644
index 3651f34..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega324PA
-; generated automatically, do not edit
-
-.nolist
- .include "m324PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 11
- .db "ATmega324PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega324pa/device.inc b/amforth-6.5/avr8/devices/atmega324pa/device.inc
deleted file mode 100644
index 8741996..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega324PA
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega324pa/device.py b/amforth-6.5/avr8/devices/atmega324pa/device.py
deleted file mode 100644
index c1ee97d..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/device.py
+++ /dev/null
@@ -1,389 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega324PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega324pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega324pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega324pa/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega324pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega324pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325/atmega325.frt b/amforth-6.5/avr8/devices/atmega325/atmega325.frt
deleted file mode 100644
index 4030095..0000000
--- a/amforth-6.5/avr8/devices/atmega325/atmega325.frt
+++ /dev/null
@@ -1,278 +0,0 @@
-\ Partname: ATmega325
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325/device.asm b/amforth-6.5/avr8/devices/atmega325/device.asm
deleted file mode 100644
index e7713db..0000000
--- a/amforth-6.5/avr8/devices/atmega325/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega325
-; generated automatically, do not edit
-
-.nolist
- .include "m325def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USI = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 9
- .db "ATmega325",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325/device.inc b/amforth-6.5/avr8/devices/atmega325/device.inc
deleted file mode 100644
index e150e01..0000000
--- a/amforth-6.5/avr8/devices/atmega325/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega325
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega325/device.py b/amforth-6.5/avr8/devices/atmega325/device.py
deleted file mode 100644
index 433c5ca..0000000
--- a/amforth-6.5/avr8/devices/atmega325/device.py
+++ /dev/null
@@ -1,317 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega325
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega325/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega325/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega325/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega325/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250/atmega3250.frt b/amforth-6.5/avr8/devices/atmega3250/atmega3250.frt
deleted file mode 100644
index 93c4b3f..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/atmega3250.frt
+++ /dev/null
@@ -1,292 +0,0 @@
-\ Partname: ATmega3250
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250/device.asm b/amforth-6.5/avr8/devices/atmega3250/device.asm
deleted file mode 100644
index c6c401d..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega3250
-; generated automatically, do not edit
-
-.nolist
- .include "m3250def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 10
- .db "ATmega3250"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250/device.inc b/amforth-6.5/avr8/devices/atmega3250/device.inc
deleted file mode 100644
index 22567c4..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega3250
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250/device.py b/amforth-6.5/avr8/devices/atmega3250/device.py
deleted file mode 100644
index f3dbb9a..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/device.py
+++ /dev/null
@@ -1,333 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3250
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'NOT_USEDAddr' : '#44', # RESERVED
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3250/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3250/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250a/atmega3250a.frt b/amforth-6.5/avr8/devices/atmega3250a/atmega3250a.frt
deleted file mode 100644
index 9d7b26c..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/atmega3250a.frt
+++ /dev/null
@@ -1,292 +0,0 @@
-\ Partname: ATmega3250A
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250a/device.asm b/amforth-6.5/avr8/devices/atmega3250a/device.asm
deleted file mode 100644
index 01060c0..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega3250A
-; generated automatically, do not edit
-
-.nolist
- .include "m3250Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega3250A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250a/device.inc b/amforth-6.5/avr8/devices/atmega3250a/device.inc
deleted file mode 100644
index 5f083a7..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega3250A
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250a/device.py b/amforth-6.5/avr8/devices/atmega3250a/device.py
deleted file mode 100644
index 43b6376..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/device.py
+++ /dev/null
@@ -1,336 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3250PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'NOT_USEDAddr' : '#44', # RESERVED
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3250a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3250a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250p/atmega3250p.frt b/amforth-6.5/avr8/devices/atmega3250p/atmega3250p.frt
deleted file mode 100644
index cf321ee..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/atmega3250p.frt
+++ /dev/null
@@ -1,292 +0,0 @@
-\ Partname: ATmega3250P
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250p/device.asm b/amforth-6.5/avr8/devices/atmega3250p/device.asm
deleted file mode 100644
index 13b7973..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega3250P
-; generated automatically, do not edit
-
-.nolist
- .include "m3250Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega3250P",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250p/device.inc b/amforth-6.5/avr8/devices/atmega3250p/device.inc
deleted file mode 100644
index cd120e1..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega3250P
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250p/device.py b/amforth-6.5/avr8/devices/atmega3250p/device.py
deleted file mode 100644
index 43b6376..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/device.py
+++ /dev/null
@@ -1,336 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3250PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'NOT_USEDAddr' : '#44', # RESERVED
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3250p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3250p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/atmega3250pa.frt b/amforth-6.5/avr8/devices/atmega3250pa/atmega3250pa.frt
deleted file mode 100644
index 2fcaf06..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/atmega3250pa.frt
+++ /dev/null
@@ -1,292 +0,0 @@
-\ Partname: ATmega3250PA
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/device.asm b/amforth-6.5/avr8/devices/atmega3250pa/device.asm
deleted file mode 100644
index 043962e..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega3250PA
-; generated automatically, do not edit
-
-.nolist
- .include "m3250PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 12
- .db "ATmega3250PA"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/device.inc b/amforth-6.5/avr8/devices/atmega3250pa/device.inc
deleted file mode 100644
index b8cd934..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega3250PA
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/device.py b/amforth-6.5/avr8/devices/atmega3250pa/device.py
deleted file mode 100644
index 43db5ea..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/device.py
+++ /dev/null
@@ -1,321 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega325PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250pa/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3250pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325a/atmega325a.frt b/amforth-6.5/avr8/devices/atmega325a/atmega325a.frt
deleted file mode 100644
index df67434..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/atmega325a.frt
+++ /dev/null
@@ -1,279 +0,0 @@
-\ Partname: ATmega325A
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325a/device.asm b/amforth-6.5/avr8/devices/atmega325a/device.asm
deleted file mode 100644
index 75dd6c3..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega325A
-; generated automatically, do not edit
-
-.nolist
- .include "m325Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USI = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 10
- .db "ATmega325A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325a/device.inc b/amforth-6.5/avr8/devices/atmega325a/device.inc
deleted file mode 100644
index 563abd6..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega325A
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega325a/device.py b/amforth-6.5/avr8/devices/atmega325a/device.py
deleted file mode 100644
index 801a088..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/device.py
+++ /dev/null
@@ -1,319 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega325A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega325a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega325a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325p/atmega325p.frt b/amforth-6.5/avr8/devices/atmega325p/atmega325p.frt
deleted file mode 100644
index 36fd302..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/atmega325p.frt
+++ /dev/null
@@ -1,279 +0,0 @@
-\ Partname: ATmega325P
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325p/device.asm b/amforth-6.5/avr8/devices/atmega325p/device.asm
deleted file mode 100644
index 245c2de..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega325P
-; generated automatically, do not edit
-
-.nolist
- .include "m325Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USI = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 10
- .db "ATmega325P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325p/device.inc b/amforth-6.5/avr8/devices/atmega325p/device.inc
deleted file mode 100644
index 84233a9..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega325P
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega325p/device.py b/amforth-6.5/avr8/devices/atmega325p/device.py
deleted file mode 100644
index 1e1ca9c..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/device.py
+++ /dev/null
@@ -1,321 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega325P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega325p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega325p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325pa/atmega325pa.frt b/amforth-6.5/avr8/devices/atmega325pa/atmega325pa.frt
deleted file mode 100644
index a50b001..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/atmega325pa.frt
+++ /dev/null
@@ -1,279 +0,0 @@
-\ Partname: ATmega325PA
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325pa/device.asm b/amforth-6.5/avr8/devices/atmega325pa/device.asm
deleted file mode 100644
index 9a3a3ff..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega325PA
-; generated automatically, do not edit
-
-.nolist
- .include "m325PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USI = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 11
- .db "ATmega325PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325pa/device.inc b/amforth-6.5/avr8/devices/atmega325pa/device.inc
deleted file mode 100644
index c699c12..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega325PA
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega325pa/device.py b/amforth-6.5/avr8/devices/atmega325pa/device.py
deleted file mode 100644
index 43db5ea..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/device.py
+++ /dev/null
@@ -1,321 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega325PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega325pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325pa/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega325pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328/atmega328.frt b/amforth-6.5/avr8/devices/atmega328/atmega328.frt
deleted file mode 100644
index ce047a9..0000000
--- a/amforth-6.5/avr8/devices/atmega328/atmega328.frt
+++ /dev/null
@@ -1,297 +0,0 @@
-\ Partname: ATmega328
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega328/device.asm b/amforth-6.5/avr8/devices/atmega328/device.asm
deleted file mode 100644
index 3ff142d..0000000
--- a/amforth-6.5/avr8/devices/atmega328/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega328
-; generated automatically, do not edit
-
-.nolist
- .include "m328def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 9
- .db "ATmega328",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega328/device.inc b/amforth-6.5/avr8/devices/atmega328/device.inc
deleted file mode 100644
index 8a2b191..0000000
--- a/amforth-6.5/avr8/devices/atmega328/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega328
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega328/device.py b/amforth-6.5/avr8/devices/atmega328/device.py
deleted file mode 100644
index 776a2d7..0000000
--- a/amforth-6.5/avr8/devices/atmega328/device.py
+++ /dev/null
@@ -1,322 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega328
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select Bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega328/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega328/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega328/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega328/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega328/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328/words/sleep.asm b/amforth-6.5/avr8/devices/atmega328/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega328/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328p/atmega328p.frt b/amforth-6.5/avr8/devices/atmega328p/atmega328p.frt
deleted file mode 100644
index 27fb70f..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/atmega328p.frt
+++ /dev/null
@@ -1,299 +0,0 @@
-\ Partname: ATmega328P
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $40 constant MCUCR_BODS \ BOD Sleep
- $20 constant MCUCR_BODSE \ BOD Sleep Enable
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega328p/device.asm b/amforth-6.5/avr8/devices/atmega328p/device.asm
deleted file mode 100644
index a13fda6..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega328P
-; generated automatically, do not edit
-
-.nolist
- .include "m328Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 10
- .db "ATmega328P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega328p/device.inc b/amforth-6.5/avr8/devices/atmega328p/device.inc
deleted file mode 100644
index 4e99429..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega328P
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega328p/device.py b/amforth-6.5/avr8/devices/atmega328p/device.py
deleted file mode 100644
index cd93cb9..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/device.py
+++ /dev/null
@@ -1,324 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega328P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select Bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega328p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega328p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega328p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega328p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega328p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329/atmega329.frt b/amforth-6.5/avr8/devices/atmega329/atmega329.frt
deleted file mode 100644
index 08ccb3e..0000000
--- a/amforth-6.5/avr8/devices/atmega329/atmega329.frt
+++ /dev/null
@@ -1,312 +0,0 @@
-\ Partname: ATmega329
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329/device.asm b/amforth-6.5/avr8/devices/atmega329/device.asm
deleted file mode 100644
index cf02ccb..0000000
--- a/amforth-6.5/avr8/devices/atmega329/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega329
-; generated automatically, do not edit
-
-.nolist
- .include "m329def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 9
- .db "ATmega329",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329/device.inc b/amforth-6.5/avr8/devices/atmega329/device.inc
deleted file mode 100644
index 707042f..0000000
--- a/amforth-6.5/avr8/devices/atmega329/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega329
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega329/device.py b/amforth-6.5/avr8/devices/atmega329/device.py
deleted file mode 100644
index c898aea..0000000
--- a/amforth-6.5/avr8/devices/atmega329/device.py
+++ /dev/null
@@ -1,352 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega329
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega329/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega329/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega329/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega329/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290/atmega3290.frt b/amforth-6.5/avr8/devices/atmega3290/atmega3290.frt
deleted file mode 100644
index 087c43d..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/atmega3290.frt
+++ /dev/null
@@ -1,328 +0,0 @@
-\ Partname: ATmega3290
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290/device.asm b/amforth-6.5/avr8/devices/atmega3290/device.asm
deleted file mode 100644
index 08426f4..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega3290
-; generated automatically, do not edit
-
-.nolist
- .include "m3290def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 10
- .db "ATmega3290"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290/device.inc b/amforth-6.5/avr8/devices/atmega3290/device.inc
deleted file mode 100644
index ac2eebd..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega3290
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290/device.py b/amforth-6.5/avr8/devices/atmega3290/device.py
deleted file mode 100644
index f65657b..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/device.py
+++ /dev/null
@@ -1,370 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3290
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3290/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3290/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290a/atmega3290a.frt b/amforth-6.5/avr8/devices/atmega3290a/atmega3290a.frt
deleted file mode 100644
index e88b4a9..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/atmega3290a.frt
+++ /dev/null
@@ -1,333 +0,0 @@
-\ Partname: ATmega3290A
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \ LCD Display Configurations
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290a/device.asm b/amforth-6.5/avr8/devices/atmega3290a/device.asm
deleted file mode 100644
index 6ffbf86..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega3290A
-; generated automatically, do not edit
-
-.nolist
- .include "m3290Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_LCD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega3290A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290a/device.inc b/amforth-6.5/avr8/devices/atmega3290a/device.inc
deleted file mode 100644
index 3b7f25f..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega3290A
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290a/device.py b/amforth-6.5/avr8/devices/atmega3290a/device.py
deleted file mode 100644
index e02b422..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/device.py
+++ /dev/null
@@ -1,378 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3290A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', # LCD Display Configurations
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3290a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3290a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290p/atmega3290p.frt b/amforth-6.5/avr8/devices/atmega3290p/atmega3290p.frt
deleted file mode 100644
index 09c1c14..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/atmega3290p.frt
+++ /dev/null
@@ -1,333 +0,0 @@
-\ Partname: ATmega3290P
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \ LCD Display Configurations
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290p/device.asm b/amforth-6.5/avr8/devices/atmega3290p/device.asm
deleted file mode 100644
index 7019d09..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega3290P
-; generated automatically, do not edit
-
-.nolist
- .include "m3290Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_LCD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega3290P",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290p/device.inc b/amforth-6.5/avr8/devices/atmega3290p/device.inc
deleted file mode 100644
index 824661b..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega3290P
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290p/device.py b/amforth-6.5/avr8/devices/atmega3290p/device.py
deleted file mode 100644
index 5ebd3d7..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/device.py
+++ /dev/null
@@ -1,378 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3290P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', # LCD Display Configurations
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3290p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3290p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/atmega3290pa.frt b/amforth-6.5/avr8/devices/atmega3290pa/atmega3290pa.frt
deleted file mode 100644
index add7cf2..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/atmega3290pa.frt
+++ /dev/null
@@ -1,333 +0,0 @@
-\ Partname: ATmega3290PA
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \ LCD Display Configurations
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/device.asm b/amforth-6.5/avr8/devices/atmega3290pa/device.asm
deleted file mode 100644
index 06ae50e..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega3290PA
-; generated automatically, do not edit
-
-.nolist
- .include "m3290PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_LCD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 12
- .db "ATmega3290PA"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/device.inc b/amforth-6.5/avr8/devices/atmega3290pa/device.inc
deleted file mode 100644
index 3d403da..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega3290PA
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/device.py b/amforth-6.5/avr8/devices/atmega3290pa/device.py
deleted file mode 100644
index 9604244..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/device.py
+++ /dev/null
@@ -1,378 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega3290PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', # LCD Display Configurations
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290pa/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega3290pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329a/atmega329a.frt b/amforth-6.5/avr8/devices/atmega329a/atmega329a.frt
deleted file mode 100644
index 15882a6..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/atmega329a.frt
+++ /dev/null
@@ -1,461 +0,0 @@
-\ Partname: ATmega329A
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $01 constant PCMSK1_PCINT8 \ Pin Change Mask Register pin 8
- $02 constant PCMSK1_PCINT9 \ Pin Change Mask Register pin 9
- $04 constant PCMSK1_PCINT10 \ Pin Change Mask Register pin 10
- $08 constant PCMSK1_PCINT11 \ Pin Change Mask Register pin 11
- $10 constant PCMSK1_PCINT12 \ Pin Change Mask Register pin 12
- $20 constant PCMSK1_PCINT13 \ Pin Change Mask Register pin 13
- $40 constant PCMSK1_PCINT14 \ Pin Change Mask Register pin 14
- $80 constant PCMSK1_PCINT15 \ Pin Change Mask Register pin 15
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $01 constant PCMSK0_PCINT0 \ Pin Change Mask Register pin 0
- $02 constant PCMSK0_PCINT1 \ Pin Change Mask Register pin 1
- $04 constant PCMSK0_PCINT2 \ Pin Change Mask Register pin 2
- $08 constant PCMSK0_PCINT3 \ Pin Change Mask Register pin 3
- $10 constant PCMSK0_PCINT4 \ Pin Change Mask Register pin 4
- $20 constant PCMSK0_PCINT5 \ Pin Change Mask Register pin 5
- $40 constant PCMSK0_PCINT6 \ Pin Change Mask Register pin 6
- $80 constant PCMSK0_PCINT7 \ Pin Change Mask Register pin 7
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
- $01 constant LCDDR18_SEG324 \ LCD memory bit segment
- $02 constant LCDDR18_SEG325 \ LCD memory bit segment
- $04 constant LCDDR18_SEG326 \ LCD memory bit segment
- $08 constant LCDDR18_SEG327 \ LCD memory bit segment
- $10 constant LCDDR18_SEG328 \ LCD memory bit segment
- $20 constant LCDDR18_SEG329 \ LCD memory bit segment
- $40 constant LCDDR18_SEG330 \ LCD memory bit segment
- $80 constant LCDDR18_SEG331 \ LCD memory bit segment
-&253 constant LCDDR17 \ LCD Data Register 17
- $01 constant LCDDR17_SEG316 \ LCD memory bit segment
- $02 constant LCDDR17_SEG317 \ LCD memory bit segment
- $04 constant LCDDR17_SEG318 \ LCD memory bit segment
- $08 constant LCDDR17_SEG319 \ LCD memory bit segment
- $10 constant LCDDR17_SEG320 \ LCD memory bit segment
- $20 constant LCDDR17_SEG321 \ LCD memory bit segment
- $40 constant LCDDR17_SEG322 \ LCD memory bit segment
- $80 constant LCDDR17_SEG323 \ LCD memory bit segment
-&252 constant LCDDR16 \ LCD Data Register 16
- $01 constant LCDDR16_SEG308 \ LCD memory bit segment
- $02 constant LCDDR16_SEG309 \ LCD memory bit segment
- $04 constant LCDDR16_SEG310 \ LCD memory bit segment
- $08 constant LCDDR16_SEG311 \ LCD memory bit segment
- $10 constant LCDDR16_SEG312 \ LCD memory bit segment
- $20 constant LCDDR16_SEG313 \ LCD memory bit segment
- $40 constant LCDDR16_SEG314 \ LCD memory bit segment
- $80 constant LCDDR16_SEG315 \ LCD memory bit segment
-&251 constant LCDDR15 \ LCD Data Register 15
- $01 constant LCDDR15_SEG300 \ LCD memory bit segment
- $02 constant LCDDR15_SEG301 \ LCD memory bit segment
- $04 constant LCDDR15_SEG302 \ LCD memory bit segment
- $08 constant LCDDR15_SEG302 \ LCD memory bit segment
- $10 constant LCDDR15_SEG304 \ LCD memory bit segment
- $20 constant LCDDR15_SEG305 \ LCD memory bit segment
- $40 constant LCDDR15_SEG306 \ LCD memory bit segment
- $80 constant LCDDR15_SEG307 \ LCD memory bit segment
-&249 constant LCDDR13 \ LCD Data Register 13
- $01 constant LCDDR13_SEG224 \ LCD memory bit segment
- $02 constant LCDDR13_SEG225 \ LCD memory bit segment
- $04 constant LCDDR13_SEG226 \ LCD memory bit segment
- $08 constant LCDDR13_SEG227 \ LCD memory bit segment
- $10 constant LCDDR13_SEG228 \ LCD memory bit segment
- $20 constant LCDDR13_SEG229 \ LCD memory bit segment
- $40 constant LCDDR13_SEG230 \ LCD memory bit segment
- $80 constant LCDDR13_SEG231 \ LCD memory bit segment
-&248 constant LCDDR12 \ LCD Data Register 12
- $01 constant LCDDR12_SEG216 \ LCD memory bit segment
- $02 constant LCDDR12_SEG217 \ LCD memory bit segment
- $04 constant LCDDR12_SEG218 \ LCD memory bit segment
- $08 constant LCDDR12_SEG219 \ LCD memory bit segment
- $10 constant LCDDR12_SEG220 \ LCD memory bit segment
- $20 constant LCDDR12_SEG221 \ LCD memory bit segment
- $40 constant LCDDR12_SEG222 \ LCD memory bit segment
- $80 constant LCDDR12_SEG223 \ LCD memory bit segment
-&247 constant LCDDR11 \ LCD Data Register 11
- $01 constant LCDDR11_SEG208 \ LCD memory bit segment
- $02 constant LCDDR11_SEG209 \ LCD memory bit segment
- $04 constant LCDDR11_SEG210 \ LCD memory bit segment
- $08 constant LCDDR11_SEG211 \ LCD memory bit segment
- $10 constant LCDDR11_SEG212 \ LCD memory bit segment
- $20 constant LCDDR11_SEG213 \ LCD memory bit segment
- $40 constant LCDDR11_SEG214 \ LCD memory bit segment
- $80 constant LCDDR11_SEG215 \ LCD memory bit segment
-&246 constant LCDDR10 \ LCD Data Register 10
- $01 constant LCDDR10_SEG200 \ LCD memory bit segment
- $02 constant LCDDR10_SEG201 \ LCD memory bit segment
- $04 constant LCDDR10_SEG202 \ LCD memory bit segment
- $08 constant LCDDR10_SEG203 \ LCD memory bit segment
- $10 constant LCDDR10_SEG204 \ LCD memory bit segment
- $20 constant LCDDR10_SEG205 \ LCD memory bit segment
- $40 constant LCDDR10_SEG206 \ LCD memory bit segment
- $80 constant LCDDR10_SEG207 \ LCD memory bit segment
-&244 constant LCDDR8 \ LCD Data Register 8
- $01 constant LCDDR8_SEG124 \ LCD memory bit segment
- $02 constant LCDDR8_SEG125 \ LCD memory bit segment
- $04 constant LCDDR8_SEG126 \ LCD memory bit segment
- $08 constant LCDDR8_SEG127 \ LCD memory bit segment
- $10 constant LCDDR8_SEG128 \ LCD memory bit segment
- $20 constant LCDDR8_SEG129 \ LCD memory bit segment
- $40 constant LCDDR8_SEG130 \ LCD memory bit segment
- $80 constant LCDDR8_SEG131 \ LCD memory bit segment
-&243 constant LCDDR7 \ LCD Data Register 7
- $01 constant LCDDR7_SEG116 \ LCD memory bit segment
- $02 constant LCDDR7_SEG117 \ LCD memory bit segment
- $04 constant LCDDR7_SEG118 \ LCD memory bit segment
- $08 constant LCDDR7_SEG119 \ LCD memory bit segment
- $10 constant LCDDR7_SEG120 \ LCD memory bit segment
- $20 constant LCDDR7_SEG121 \ LCD memory bit segment
- $40 constant LCDDR7_SEG122 \ LCD memory bit segment
- $80 constant LCDDR7_SEG123 \ LCD memory bit segment
-&242 constant LCDDR6 \ LCD Data Register 6
- $01 constant LCDDR6_SEG108 \ LCD memory bit segment
- $02 constant LCDDR6_SEG109 \ LCD memory bit segment
- $04 constant LCDDR6_SEG110 \ LCD memory bit segment
- $08 constant LCDDR6_SEG111 \ LCD memory bit segment
- $10 constant LCDDR6_SEG112 \ LCD memory bit segment
- $20 constant LCDDR6_SEG113 \ LCD memory bit segment
- $40 constant LCDDR6_SEG114 \ LCD memory bit segment
- $80 constant LCDDR6_SEG115 \ LCD memory bit segment
-&241 constant LCDDR5 \ LCD Data Register 5
- $01 constant LCDDR5_SEG100 \ LCD memory bit segment
- $02 constant LCDDR5_SEG101 \ LCD memory bit segment
- $04 constant LCDDR5_SEG102 \ LCD memory bit segment
- $08 constant LCDDR5_SEG103 \ LCD memory bit segment
- $10 constant LCDDR5_SEG104 \ LCD memory bit segment
- $20 constant LCDDR5_SEG105 \ LCD memory bit segment
- $40 constant LCDDR5_SEG106 \ LCD memory bit segment
- $80 constant LCDDR5_SEG107 \ LCD memory bit segment
-&239 constant LCDDR3 \ LCD Data Register 3
- $01 constant LCDDR3_SEG024 \ LCD memory bit segment
- $02 constant LCDDR3_SEG025 \ LCD memory bit segment
- $04 constant LCDDR3_SEG026 \ LCD memory bit segment
- $08 constant LCDDR3_SEG027 \ LCD memory bit segment
- $10 constant LCDDR3_SEG028 \ LCD memory bit segment
- $20 constant LCDDR3_SEG029 \ LCD memory bit segment
- $40 constant LCDDR3_SEG030 \ LCD memory bit segment
- $80 constant LCDDR3_SEG031 \ LCD memory bit segment
-&238 constant LCDDR2 \ LCD Data Register 2
- $01 constant LCDDR2_SEG016 \ LCD memory bit segment
- $02 constant LCDDR2_SEG017 \ LCD memory bit segment
- $04 constant LCDDR2_SEG018 \ LCD memory bit segment
- $08 constant LCDDR2_SEG019 \ LCD memory bit segment
- $10 constant LCDDR2_SEG020 \ LCD memory bit segment
- $20 constant LCDDR2_SEG021 \ LCD memory bit segment
- $40 constant LCDDR2_SEG022 \ LCD memory bit segment
- $80 constant LCDDR2_SEG023 \ LCD memory bit segment
-&237 constant LCDDR1 \ LCD Data Register 1
- $01 constant LCDDR1_SEG008 \ LCD memory bit segment
- $02 constant LCDDR1_SEG009 \ LCD memory bit segment
- $04 constant LCDDR1_SEG010 \ LCD memory bit segment
- $08 constant LCDDR1_SEG011 \ LCD memory bit segment
- $10 constant LCDDR1_SEG012 \ LCD memory bit segment
- $20 constant LCDDR1_SEG013 \ LCD memory bit segment
- $40 constant LCDDR1_SEG014 \ LCD memory bit segment
- $80 constant LCDDR1_SEG015 \ LCD memory bit segment
-&236 constant LCDDR0 \ LCD Data Register 0
- $01 constant LCDDR0_SEG000 \ LCD memory bit segment
- $02 constant LCDDR0_SEG001 \ LCD memory bit segment
- $04 constant LCDDR0_SEG002 \ LCD memory bit segment
- $08 constant LCDDR0_SEG003 \ LCD memory bit segment
- $10 constant LCDDR0_SEG004 \ LCD memory bit segment
- $20 constant LCDDR0_SEG005 \ LCD memory bit segment
- $40 constant LCDDR0_SEG006 \ LCD memory bit segment
- $80 constant LCDDR0_SEG007 \ LCD memory bit segment
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329a/device.asm b/amforth-6.5/avr8/devices/atmega329a/device.asm
deleted file mode 100644
index feb1134..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega329A
-; generated automatically, do not edit
-
-.nolist
- .include "m329Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_LCD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 10
- .db "ATmega329A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329a/device.inc b/amforth-6.5/avr8/devices/atmega329a/device.inc
deleted file mode 100644
index ddbcf67..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega329A
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega329a/device.py b/amforth-6.5/avr8/devices/atmega329a/device.py
deleted file mode 100644
index df0c33c..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/device.py
+++ /dev/null
@@ -1,502 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega329A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT8': '$1', # Pin Change Mask Register pin 8
- 'PCMSK1_PCINT9': '$2', # Pin Change Mask Register pin 9
- 'PCMSK1_PCINT10': '$4', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT11': '$8', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT12': '$10', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT13': '$20', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT14': '$40', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT15': '$80', # Pin Change Mask Register pin 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT0': '$1', # Pin Change Mask Register pin 0
- 'PCMSK0_PCINT1': '$2', # Pin Change Mask Register pin 1
- 'PCMSK0_PCINT2': '$4', # Pin Change Mask Register pin 2
- 'PCMSK0_PCINT3': '$8', # Pin Change Mask Register pin 3
- 'PCMSK0_PCINT4': '$10', # Pin Change Mask Register pin 4
- 'PCMSK0_PCINT5': '$20', # Pin Change Mask Register pin 5
- 'PCMSK0_PCINT6': '$40', # Pin Change Mask Register pin 6
- 'PCMSK0_PCINT7': '$80', # Pin Change Mask Register pin 7
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR18_SEG324': '$1', # LCD memory bit segment
- 'LCDDR18_SEG325': '$2', # LCD memory bit segment
- 'LCDDR18_SEG326': '$4', # LCD memory bit segment
- 'LCDDR18_SEG327': '$8', # LCD memory bit segment
- 'LCDDR18_SEG328': '$10', # LCD memory bit segment
- 'LCDDR18_SEG329': '$20', # LCD memory bit segment
- 'LCDDR18_SEG330': '$40', # LCD memory bit segment
- 'LCDDR18_SEG331': '$80', # LCD memory bit segment
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR17_SEG316': '$1', # LCD memory bit segment
- 'LCDDR17_SEG317': '$2', # LCD memory bit segment
- 'LCDDR17_SEG318': '$4', # LCD memory bit segment
- 'LCDDR17_SEG319': '$8', # LCD memory bit segment
- 'LCDDR17_SEG320': '$10', # LCD memory bit segment
- 'LCDDR17_SEG321': '$20', # LCD memory bit segment
- 'LCDDR17_SEG322': '$40', # LCD memory bit segment
- 'LCDDR17_SEG323': '$80', # LCD memory bit segment
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR16_SEG308': '$1', # LCD memory bit segment
- 'LCDDR16_SEG309': '$2', # LCD memory bit segment
- 'LCDDR16_SEG310': '$4', # LCD memory bit segment
- 'LCDDR16_SEG311': '$8', # LCD memory bit segment
- 'LCDDR16_SEG312': '$10', # LCD memory bit segment
- 'LCDDR16_SEG313': '$20', # LCD memory bit segment
- 'LCDDR16_SEG314': '$40', # LCD memory bit segment
- 'LCDDR16_SEG315': '$80', # LCD memory bit segment
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR15_SEG300': '$1', # LCD memory bit segment
- 'LCDDR15_SEG301': '$2', # LCD memory bit segment
- 'LCDDR15_SEG302': '$4', # LCD memory bit segment
- 'LCDDR15_SEG302': '$8', # LCD memory bit segment
- 'LCDDR15_SEG304': '$10', # LCD memory bit segment
- 'LCDDR15_SEG305': '$20', # LCD memory bit segment
- 'LCDDR15_SEG306': '$40', # LCD memory bit segment
- 'LCDDR15_SEG307': '$80', # LCD memory bit segment
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR13_SEG224': '$1', # LCD memory bit segment
- 'LCDDR13_SEG225': '$2', # LCD memory bit segment
- 'LCDDR13_SEG226': '$4', # LCD memory bit segment
- 'LCDDR13_SEG227': '$8', # LCD memory bit segment
- 'LCDDR13_SEG228': '$10', # LCD memory bit segment
- 'LCDDR13_SEG229': '$20', # LCD memory bit segment
- 'LCDDR13_SEG230': '$40', # LCD memory bit segment
- 'LCDDR13_SEG231': '$80', # LCD memory bit segment
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR12_SEG216': '$1', # LCD memory bit segment
- 'LCDDR12_SEG217': '$2', # LCD memory bit segment
- 'LCDDR12_SEG218': '$4', # LCD memory bit segment
- 'LCDDR12_SEG219': '$8', # LCD memory bit segment
- 'LCDDR12_SEG220': '$10', # LCD memory bit segment
- 'LCDDR12_SEG221': '$20', # LCD memory bit segment
- 'LCDDR12_SEG222': '$40', # LCD memory bit segment
- 'LCDDR12_SEG223': '$80', # LCD memory bit segment
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR11_SEG208': '$1', # LCD memory bit segment
- 'LCDDR11_SEG209': '$2', # LCD memory bit segment
- 'LCDDR11_SEG210': '$4', # LCD memory bit segment
- 'LCDDR11_SEG211': '$8', # LCD memory bit segment
- 'LCDDR11_SEG212': '$10', # LCD memory bit segment
- 'LCDDR11_SEG213': '$20', # LCD memory bit segment
- 'LCDDR11_SEG214': '$40', # LCD memory bit segment
- 'LCDDR11_SEG215': '$80', # LCD memory bit segment
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR10_SEG200': '$1', # LCD memory bit segment
- 'LCDDR10_SEG201': '$2', # LCD memory bit segment
- 'LCDDR10_SEG202': '$4', # LCD memory bit segment
- 'LCDDR10_SEG203': '$8', # LCD memory bit segment
- 'LCDDR10_SEG204': '$10', # LCD memory bit segment
- 'LCDDR10_SEG205': '$20', # LCD memory bit segment
- 'LCDDR10_SEG206': '$40', # LCD memory bit segment
- 'LCDDR10_SEG207': '$80', # LCD memory bit segment
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR8_SEG124': '$1', # LCD memory bit segment
- 'LCDDR8_SEG125': '$2', # LCD memory bit segment
- 'LCDDR8_SEG126': '$4', # LCD memory bit segment
- 'LCDDR8_SEG127': '$8', # LCD memory bit segment
- 'LCDDR8_SEG128': '$10', # LCD memory bit segment
- 'LCDDR8_SEG129': '$20', # LCD memory bit segment
- 'LCDDR8_SEG130': '$40', # LCD memory bit segment
- 'LCDDR8_SEG131': '$80', # LCD memory bit segment
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR7_SEG116': '$1', # LCD memory bit segment
- 'LCDDR7_SEG117': '$2', # LCD memory bit segment
- 'LCDDR7_SEG118': '$4', # LCD memory bit segment
- 'LCDDR7_SEG119': '$8', # LCD memory bit segment
- 'LCDDR7_SEG120': '$10', # LCD memory bit segment
- 'LCDDR7_SEG121': '$20', # LCD memory bit segment
- 'LCDDR7_SEG122': '$40', # LCD memory bit segment
- 'LCDDR7_SEG123': '$80', # LCD memory bit segment
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR6_SEG108': '$1', # LCD memory bit segment
- 'LCDDR6_SEG109': '$2', # LCD memory bit segment
- 'LCDDR6_SEG110': '$4', # LCD memory bit segment
- 'LCDDR6_SEG111': '$8', # LCD memory bit segment
- 'LCDDR6_SEG112': '$10', # LCD memory bit segment
- 'LCDDR6_SEG113': '$20', # LCD memory bit segment
- 'LCDDR6_SEG114': '$40', # LCD memory bit segment
- 'LCDDR6_SEG115': '$80', # LCD memory bit segment
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR5_SEG100': '$1', # LCD memory bit segment
- 'LCDDR5_SEG101': '$2', # LCD memory bit segment
- 'LCDDR5_SEG102': '$4', # LCD memory bit segment
- 'LCDDR5_SEG103': '$8', # LCD memory bit segment
- 'LCDDR5_SEG104': '$10', # LCD memory bit segment
- 'LCDDR5_SEG105': '$20', # LCD memory bit segment
- 'LCDDR5_SEG106': '$40', # LCD memory bit segment
- 'LCDDR5_SEG107': '$80', # LCD memory bit segment
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR3_SEG024': '$1', # LCD memory bit segment
- 'LCDDR3_SEG025': '$2', # LCD memory bit segment
- 'LCDDR3_SEG026': '$4', # LCD memory bit segment
- 'LCDDR3_SEG027': '$8', # LCD memory bit segment
- 'LCDDR3_SEG028': '$10', # LCD memory bit segment
- 'LCDDR3_SEG029': '$20', # LCD memory bit segment
- 'LCDDR3_SEG030': '$40', # LCD memory bit segment
- 'LCDDR3_SEG031': '$80', # LCD memory bit segment
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR2_SEG016': '$1', # LCD memory bit segment
- 'LCDDR2_SEG017': '$2', # LCD memory bit segment
- 'LCDDR2_SEG018': '$4', # LCD memory bit segment
- 'LCDDR2_SEG019': '$8', # LCD memory bit segment
- 'LCDDR2_SEG020': '$10', # LCD memory bit segment
- 'LCDDR2_SEG021': '$20', # LCD memory bit segment
- 'LCDDR2_SEG022': '$40', # LCD memory bit segment
- 'LCDDR2_SEG023': '$80', # LCD memory bit segment
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR1_SEG008': '$1', # LCD memory bit segment
- 'LCDDR1_SEG009': '$2', # LCD memory bit segment
- 'LCDDR1_SEG010': '$4', # LCD memory bit segment
- 'LCDDR1_SEG011': '$8', # LCD memory bit segment
- 'LCDDR1_SEG012': '$10', # LCD memory bit segment
- 'LCDDR1_SEG013': '$20', # LCD memory bit segment
- 'LCDDR1_SEG014': '$40', # LCD memory bit segment
- 'LCDDR1_SEG015': '$80', # LCD memory bit segment
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDDR0_SEG000': '$1', # LCD memory bit segment
- 'LCDDR0_SEG001': '$2', # LCD memory bit segment
- 'LCDDR0_SEG002': '$4', # LCD memory bit segment
- 'LCDDR0_SEG003': '$8', # LCD memory bit segment
- 'LCDDR0_SEG004': '$10', # LCD memory bit segment
- 'LCDDR0_SEG005': '$20', # LCD memory bit segment
- 'LCDDR0_SEG006': '$40', # LCD memory bit segment
- 'LCDDR0_SEG007': '$80', # LCD memory bit segment
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', #
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega329a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega329a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329p/atmega329p.frt b/amforth-6.5/avr8/devices/atmega329p/atmega329p.frt
deleted file mode 100644
index b5bdf7d..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/atmega329p.frt
+++ /dev/null
@@ -1,461 +0,0 @@
-\ Partname: ATmega329P
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $01 constant PCMSK1_PCINT8 \ Pin Change Mask Register pin 8
- $02 constant PCMSK1_PCINT9 \ Pin Change Mask Register pin 9
- $04 constant PCMSK1_PCINT10 \ Pin Change Mask Register pin 10
- $08 constant PCMSK1_PCINT11 \ Pin Change Mask Register pin 11
- $10 constant PCMSK1_PCINT12 \ Pin Change Mask Register pin 12
- $20 constant PCMSK1_PCINT13 \ Pin Change Mask Register pin 13
- $40 constant PCMSK1_PCINT14 \ Pin Change Mask Register pin 14
- $80 constant PCMSK1_PCINT15 \ Pin Change Mask Register pin 15
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $01 constant PCMSK0_PCINT0 \ Pin Change Mask Register pin 0
- $02 constant PCMSK0_PCINT1 \ Pin Change Mask Register pin 1
- $04 constant PCMSK0_PCINT2 \ Pin Change Mask Register pin 2
- $08 constant PCMSK0_PCINT3 \ Pin Change Mask Register pin 3
- $10 constant PCMSK0_PCINT4 \ Pin Change Mask Register pin 4
- $20 constant PCMSK0_PCINT5 \ Pin Change Mask Register pin 5
- $40 constant PCMSK0_PCINT6 \ Pin Change Mask Register pin 6
- $80 constant PCMSK0_PCINT7 \ Pin Change Mask Register pin 7
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
- $01 constant LCDDR18_SEG324 \ LCD memory bit segment
- $02 constant LCDDR18_SEG325 \ LCD memory bit segment
- $04 constant LCDDR18_SEG326 \ LCD memory bit segment
- $08 constant LCDDR18_SEG327 \ LCD memory bit segment
- $10 constant LCDDR18_SEG328 \ LCD memory bit segment
- $20 constant LCDDR18_SEG329 \ LCD memory bit segment
- $40 constant LCDDR18_SEG330 \ LCD memory bit segment
- $80 constant LCDDR18_SEG331 \ LCD memory bit segment
-&253 constant LCDDR17 \ LCD Data Register 17
- $01 constant LCDDR17_SEG316 \ LCD memory bit segment
- $02 constant LCDDR17_SEG317 \ LCD memory bit segment
- $04 constant LCDDR17_SEG318 \ LCD memory bit segment
- $08 constant LCDDR17_SEG319 \ LCD memory bit segment
- $10 constant LCDDR17_SEG320 \ LCD memory bit segment
- $20 constant LCDDR17_SEG321 \ LCD memory bit segment
- $40 constant LCDDR17_SEG322 \ LCD memory bit segment
- $80 constant LCDDR17_SEG323 \ LCD memory bit segment
-&252 constant LCDDR16 \ LCD Data Register 16
- $01 constant LCDDR16_SEG308 \ LCD memory bit segment
- $02 constant LCDDR16_SEG309 \ LCD memory bit segment
- $04 constant LCDDR16_SEG310 \ LCD memory bit segment
- $08 constant LCDDR16_SEG311 \ LCD memory bit segment
- $10 constant LCDDR16_SEG312 \ LCD memory bit segment
- $20 constant LCDDR16_SEG313 \ LCD memory bit segment
- $40 constant LCDDR16_SEG314 \ LCD memory bit segment
- $80 constant LCDDR16_SEG315 \ LCD memory bit segment
-&251 constant LCDDR15 \ LCD Data Register 15
- $01 constant LCDDR15_SEG300 \ LCD memory bit segment
- $02 constant LCDDR15_SEG301 \ LCD memory bit segment
- $04 constant LCDDR15_SEG302 \ LCD memory bit segment
- $08 constant LCDDR15_SEG302 \ LCD memory bit segment
- $10 constant LCDDR15_SEG304 \ LCD memory bit segment
- $20 constant LCDDR15_SEG305 \ LCD memory bit segment
- $40 constant LCDDR15_SEG306 \ LCD memory bit segment
- $80 constant LCDDR15_SEG307 \ LCD memory bit segment
-&249 constant LCDDR13 \ LCD Data Register 13
- $01 constant LCDDR13_SEG224 \ LCD memory bit segment
- $02 constant LCDDR13_SEG225 \ LCD memory bit segment
- $04 constant LCDDR13_SEG226 \ LCD memory bit segment
- $08 constant LCDDR13_SEG227 \ LCD memory bit segment
- $10 constant LCDDR13_SEG228 \ LCD memory bit segment
- $20 constant LCDDR13_SEG229 \ LCD memory bit segment
- $40 constant LCDDR13_SEG230 \ LCD memory bit segment
- $80 constant LCDDR13_SEG231 \ LCD memory bit segment
-&248 constant LCDDR12 \ LCD Data Register 12
- $01 constant LCDDR12_SEG216 \ LCD memory bit segment
- $02 constant LCDDR12_SEG217 \ LCD memory bit segment
- $04 constant LCDDR12_SEG218 \ LCD memory bit segment
- $08 constant LCDDR12_SEG219 \ LCD memory bit segment
- $10 constant LCDDR12_SEG220 \ LCD memory bit segment
- $20 constant LCDDR12_SEG221 \ LCD memory bit segment
- $40 constant LCDDR12_SEG222 \ LCD memory bit segment
- $80 constant LCDDR12_SEG223 \ LCD memory bit segment
-&247 constant LCDDR11 \ LCD Data Register 11
- $01 constant LCDDR11_SEG208 \ LCD memory bit segment
- $02 constant LCDDR11_SEG209 \ LCD memory bit segment
- $04 constant LCDDR11_SEG210 \ LCD memory bit segment
- $08 constant LCDDR11_SEG211 \ LCD memory bit segment
- $10 constant LCDDR11_SEG212 \ LCD memory bit segment
- $20 constant LCDDR11_SEG213 \ LCD memory bit segment
- $40 constant LCDDR11_SEG214 \ LCD memory bit segment
- $80 constant LCDDR11_SEG215 \ LCD memory bit segment
-&246 constant LCDDR10 \ LCD Data Register 10
- $01 constant LCDDR10_SEG200 \ LCD memory bit segment
- $02 constant LCDDR10_SEG201 \ LCD memory bit segment
- $04 constant LCDDR10_SEG202 \ LCD memory bit segment
- $08 constant LCDDR10_SEG203 \ LCD memory bit segment
- $10 constant LCDDR10_SEG204 \ LCD memory bit segment
- $20 constant LCDDR10_SEG205 \ LCD memory bit segment
- $40 constant LCDDR10_SEG206 \ LCD memory bit segment
- $80 constant LCDDR10_SEG207 \ LCD memory bit segment
-&244 constant LCDDR8 \ LCD Data Register 8
- $01 constant LCDDR8_SEG124 \ LCD memory bit segment
- $02 constant LCDDR8_SEG125 \ LCD memory bit segment
- $04 constant LCDDR8_SEG126 \ LCD memory bit segment
- $08 constant LCDDR8_SEG127 \ LCD memory bit segment
- $10 constant LCDDR8_SEG128 \ LCD memory bit segment
- $20 constant LCDDR8_SEG129 \ LCD memory bit segment
- $40 constant LCDDR8_SEG130 \ LCD memory bit segment
- $80 constant LCDDR8_SEG131 \ LCD memory bit segment
-&243 constant LCDDR7 \ LCD Data Register 7
- $01 constant LCDDR7_SEG116 \ LCD memory bit segment
- $02 constant LCDDR7_SEG117 \ LCD memory bit segment
- $04 constant LCDDR7_SEG118 \ LCD memory bit segment
- $08 constant LCDDR7_SEG119 \ LCD memory bit segment
- $10 constant LCDDR7_SEG120 \ LCD memory bit segment
- $20 constant LCDDR7_SEG121 \ LCD memory bit segment
- $40 constant LCDDR7_SEG122 \ LCD memory bit segment
- $80 constant LCDDR7_SEG123 \ LCD memory bit segment
-&242 constant LCDDR6 \ LCD Data Register 6
- $01 constant LCDDR6_SEG108 \ LCD memory bit segment
- $02 constant LCDDR6_SEG109 \ LCD memory bit segment
- $04 constant LCDDR6_SEG110 \ LCD memory bit segment
- $08 constant LCDDR6_SEG111 \ LCD memory bit segment
- $10 constant LCDDR6_SEG112 \ LCD memory bit segment
- $20 constant LCDDR6_SEG113 \ LCD memory bit segment
- $40 constant LCDDR6_SEG114 \ LCD memory bit segment
- $80 constant LCDDR6_SEG115 \ LCD memory bit segment
-&241 constant LCDDR5 \ LCD Data Register 5
- $01 constant LCDDR5_SEG100 \ LCD memory bit segment
- $02 constant LCDDR5_SEG101 \ LCD memory bit segment
- $04 constant LCDDR5_SEG102 \ LCD memory bit segment
- $08 constant LCDDR5_SEG103 \ LCD memory bit segment
- $10 constant LCDDR5_SEG104 \ LCD memory bit segment
- $20 constant LCDDR5_SEG105 \ LCD memory bit segment
- $40 constant LCDDR5_SEG106 \ LCD memory bit segment
- $80 constant LCDDR5_SEG107 \ LCD memory bit segment
-&239 constant LCDDR3 \ LCD Data Register 3
- $01 constant LCDDR3_SEG024 \ LCD memory bit segment
- $02 constant LCDDR3_SEG025 \ LCD memory bit segment
- $04 constant LCDDR3_SEG026 \ LCD memory bit segment
- $08 constant LCDDR3_SEG027 \ LCD memory bit segment
- $10 constant LCDDR3_SEG028 \ LCD memory bit segment
- $20 constant LCDDR3_SEG029 \ LCD memory bit segment
- $40 constant LCDDR3_SEG030 \ LCD memory bit segment
- $80 constant LCDDR3_SEG031 \ LCD memory bit segment
-&238 constant LCDDR2 \ LCD Data Register 2
- $01 constant LCDDR2_SEG016 \ LCD memory bit segment
- $02 constant LCDDR2_SEG017 \ LCD memory bit segment
- $04 constant LCDDR2_SEG018 \ LCD memory bit segment
- $08 constant LCDDR2_SEG019 \ LCD memory bit segment
- $10 constant LCDDR2_SEG020 \ LCD memory bit segment
- $20 constant LCDDR2_SEG021 \ LCD memory bit segment
- $40 constant LCDDR2_SEG022 \ LCD memory bit segment
- $80 constant LCDDR2_SEG023 \ LCD memory bit segment
-&237 constant LCDDR1 \ LCD Data Register 1
- $01 constant LCDDR1_SEG008 \ LCD memory bit segment
- $02 constant LCDDR1_SEG009 \ LCD memory bit segment
- $04 constant LCDDR1_SEG010 \ LCD memory bit segment
- $08 constant LCDDR1_SEG011 \ LCD memory bit segment
- $10 constant LCDDR1_SEG012 \ LCD memory bit segment
- $20 constant LCDDR1_SEG013 \ LCD memory bit segment
- $40 constant LCDDR1_SEG014 \ LCD memory bit segment
- $80 constant LCDDR1_SEG015 \ LCD memory bit segment
-&236 constant LCDDR0 \ LCD Data Register 0
- $01 constant LCDDR0_SEG000 \ LCD memory bit segment
- $02 constant LCDDR0_SEG001 \ LCD memory bit segment
- $04 constant LCDDR0_SEG002 \ LCD memory bit segment
- $08 constant LCDDR0_SEG003 \ LCD memory bit segment
- $10 constant LCDDR0_SEG004 \ LCD memory bit segment
- $20 constant LCDDR0_SEG005 \ LCD memory bit segment
- $40 constant LCDDR0_SEG006 \ LCD memory bit segment
- $80 constant LCDDR0_SEG007 \ LCD memory bit segment
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329p/device.asm b/amforth-6.5/avr8/devices/atmega329p/device.asm
deleted file mode 100644
index 30d7f84..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega329P
-; generated automatically, do not edit
-
-.nolist
- .include "m329Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_LCD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 10
- .db "ATmega329P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329p/device.inc b/amforth-6.5/avr8/devices/atmega329p/device.inc
deleted file mode 100644
index 3e941bb..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega329P
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega329p/device.py b/amforth-6.5/avr8/devices/atmega329p/device.py
deleted file mode 100644
index 2fdfee0..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/device.py
+++ /dev/null
@@ -1,504 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega329P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT8': '$1', # Pin Change Mask Register pin 8
- 'PCMSK1_PCINT9': '$2', # Pin Change Mask Register pin 9
- 'PCMSK1_PCINT10': '$4', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT11': '$8', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT12': '$10', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT13': '$20', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT14': '$40', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT15': '$80', # Pin Change Mask Register pin 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT0': '$1', # Pin Change Mask Register pin 0
- 'PCMSK0_PCINT1': '$2', # Pin Change Mask Register pin 1
- 'PCMSK0_PCINT2': '$4', # Pin Change Mask Register pin 2
- 'PCMSK0_PCINT3': '$8', # Pin Change Mask Register pin 3
- 'PCMSK0_PCINT4': '$10', # Pin Change Mask Register pin 4
- 'PCMSK0_PCINT5': '$20', # Pin Change Mask Register pin 5
- 'PCMSK0_PCINT6': '$40', # Pin Change Mask Register pin 6
- 'PCMSK0_PCINT7': '$80', # Pin Change Mask Register pin 7
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR18_SEG324': '$1', # LCD memory bit segment
- 'LCDDR18_SEG325': '$2', # LCD memory bit segment
- 'LCDDR18_SEG326': '$4', # LCD memory bit segment
- 'LCDDR18_SEG327': '$8', # LCD memory bit segment
- 'LCDDR18_SEG328': '$10', # LCD memory bit segment
- 'LCDDR18_SEG329': '$20', # LCD memory bit segment
- 'LCDDR18_SEG330': '$40', # LCD memory bit segment
- 'LCDDR18_SEG331': '$80', # LCD memory bit segment
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR17_SEG316': '$1', # LCD memory bit segment
- 'LCDDR17_SEG317': '$2', # LCD memory bit segment
- 'LCDDR17_SEG318': '$4', # LCD memory bit segment
- 'LCDDR17_SEG319': '$8', # LCD memory bit segment
- 'LCDDR17_SEG320': '$10', # LCD memory bit segment
- 'LCDDR17_SEG321': '$20', # LCD memory bit segment
- 'LCDDR17_SEG322': '$40', # LCD memory bit segment
- 'LCDDR17_SEG323': '$80', # LCD memory bit segment
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR16_SEG308': '$1', # LCD memory bit segment
- 'LCDDR16_SEG309': '$2', # LCD memory bit segment
- 'LCDDR16_SEG310': '$4', # LCD memory bit segment
- 'LCDDR16_SEG311': '$8', # LCD memory bit segment
- 'LCDDR16_SEG312': '$10', # LCD memory bit segment
- 'LCDDR16_SEG313': '$20', # LCD memory bit segment
- 'LCDDR16_SEG314': '$40', # LCD memory bit segment
- 'LCDDR16_SEG315': '$80', # LCD memory bit segment
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR15_SEG300': '$1', # LCD memory bit segment
- 'LCDDR15_SEG301': '$2', # LCD memory bit segment
- 'LCDDR15_SEG302': '$4', # LCD memory bit segment
- 'LCDDR15_SEG302': '$8', # LCD memory bit segment
- 'LCDDR15_SEG304': '$10', # LCD memory bit segment
- 'LCDDR15_SEG305': '$20', # LCD memory bit segment
- 'LCDDR15_SEG306': '$40', # LCD memory bit segment
- 'LCDDR15_SEG307': '$80', # LCD memory bit segment
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR13_SEG224': '$1', # LCD memory bit segment
- 'LCDDR13_SEG225': '$2', # LCD memory bit segment
- 'LCDDR13_SEG226': '$4', # LCD memory bit segment
- 'LCDDR13_SEG227': '$8', # LCD memory bit segment
- 'LCDDR13_SEG228': '$10', # LCD memory bit segment
- 'LCDDR13_SEG229': '$20', # LCD memory bit segment
- 'LCDDR13_SEG230': '$40', # LCD memory bit segment
- 'LCDDR13_SEG231': '$80', # LCD memory bit segment
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR12_SEG216': '$1', # LCD memory bit segment
- 'LCDDR12_SEG217': '$2', # LCD memory bit segment
- 'LCDDR12_SEG218': '$4', # LCD memory bit segment
- 'LCDDR12_SEG219': '$8', # LCD memory bit segment
- 'LCDDR12_SEG220': '$10', # LCD memory bit segment
- 'LCDDR12_SEG221': '$20', # LCD memory bit segment
- 'LCDDR12_SEG222': '$40', # LCD memory bit segment
- 'LCDDR12_SEG223': '$80', # LCD memory bit segment
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR11_SEG208': '$1', # LCD memory bit segment
- 'LCDDR11_SEG209': '$2', # LCD memory bit segment
- 'LCDDR11_SEG210': '$4', # LCD memory bit segment
- 'LCDDR11_SEG211': '$8', # LCD memory bit segment
- 'LCDDR11_SEG212': '$10', # LCD memory bit segment
- 'LCDDR11_SEG213': '$20', # LCD memory bit segment
- 'LCDDR11_SEG214': '$40', # LCD memory bit segment
- 'LCDDR11_SEG215': '$80', # LCD memory bit segment
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR10_SEG200': '$1', # LCD memory bit segment
- 'LCDDR10_SEG201': '$2', # LCD memory bit segment
- 'LCDDR10_SEG202': '$4', # LCD memory bit segment
- 'LCDDR10_SEG203': '$8', # LCD memory bit segment
- 'LCDDR10_SEG204': '$10', # LCD memory bit segment
- 'LCDDR10_SEG205': '$20', # LCD memory bit segment
- 'LCDDR10_SEG206': '$40', # LCD memory bit segment
- 'LCDDR10_SEG207': '$80', # LCD memory bit segment
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR8_SEG124': '$1', # LCD memory bit segment
- 'LCDDR8_SEG125': '$2', # LCD memory bit segment
- 'LCDDR8_SEG126': '$4', # LCD memory bit segment
- 'LCDDR8_SEG127': '$8', # LCD memory bit segment
- 'LCDDR8_SEG128': '$10', # LCD memory bit segment
- 'LCDDR8_SEG129': '$20', # LCD memory bit segment
- 'LCDDR8_SEG130': '$40', # LCD memory bit segment
- 'LCDDR8_SEG131': '$80', # LCD memory bit segment
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR7_SEG116': '$1', # LCD memory bit segment
- 'LCDDR7_SEG117': '$2', # LCD memory bit segment
- 'LCDDR7_SEG118': '$4', # LCD memory bit segment
- 'LCDDR7_SEG119': '$8', # LCD memory bit segment
- 'LCDDR7_SEG120': '$10', # LCD memory bit segment
- 'LCDDR7_SEG121': '$20', # LCD memory bit segment
- 'LCDDR7_SEG122': '$40', # LCD memory bit segment
- 'LCDDR7_SEG123': '$80', # LCD memory bit segment
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR6_SEG108': '$1', # LCD memory bit segment
- 'LCDDR6_SEG109': '$2', # LCD memory bit segment
- 'LCDDR6_SEG110': '$4', # LCD memory bit segment
- 'LCDDR6_SEG111': '$8', # LCD memory bit segment
- 'LCDDR6_SEG112': '$10', # LCD memory bit segment
- 'LCDDR6_SEG113': '$20', # LCD memory bit segment
- 'LCDDR6_SEG114': '$40', # LCD memory bit segment
- 'LCDDR6_SEG115': '$80', # LCD memory bit segment
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR5_SEG100': '$1', # LCD memory bit segment
- 'LCDDR5_SEG101': '$2', # LCD memory bit segment
- 'LCDDR5_SEG102': '$4', # LCD memory bit segment
- 'LCDDR5_SEG103': '$8', # LCD memory bit segment
- 'LCDDR5_SEG104': '$10', # LCD memory bit segment
- 'LCDDR5_SEG105': '$20', # LCD memory bit segment
- 'LCDDR5_SEG106': '$40', # LCD memory bit segment
- 'LCDDR5_SEG107': '$80', # LCD memory bit segment
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR3_SEG024': '$1', # LCD memory bit segment
- 'LCDDR3_SEG025': '$2', # LCD memory bit segment
- 'LCDDR3_SEG026': '$4', # LCD memory bit segment
- 'LCDDR3_SEG027': '$8', # LCD memory bit segment
- 'LCDDR3_SEG028': '$10', # LCD memory bit segment
- 'LCDDR3_SEG029': '$20', # LCD memory bit segment
- 'LCDDR3_SEG030': '$40', # LCD memory bit segment
- 'LCDDR3_SEG031': '$80', # LCD memory bit segment
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR2_SEG016': '$1', # LCD memory bit segment
- 'LCDDR2_SEG017': '$2', # LCD memory bit segment
- 'LCDDR2_SEG018': '$4', # LCD memory bit segment
- 'LCDDR2_SEG019': '$8', # LCD memory bit segment
- 'LCDDR2_SEG020': '$10', # LCD memory bit segment
- 'LCDDR2_SEG021': '$20', # LCD memory bit segment
- 'LCDDR2_SEG022': '$40', # LCD memory bit segment
- 'LCDDR2_SEG023': '$80', # LCD memory bit segment
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR1_SEG008': '$1', # LCD memory bit segment
- 'LCDDR1_SEG009': '$2', # LCD memory bit segment
- 'LCDDR1_SEG010': '$4', # LCD memory bit segment
- 'LCDDR1_SEG011': '$8', # LCD memory bit segment
- 'LCDDR1_SEG012': '$10', # LCD memory bit segment
- 'LCDDR1_SEG013': '$20', # LCD memory bit segment
- 'LCDDR1_SEG014': '$40', # LCD memory bit segment
- 'LCDDR1_SEG015': '$80', # LCD memory bit segment
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDDR0_SEG000': '$1', # LCD memory bit segment
- 'LCDDR0_SEG001': '$2', # LCD memory bit segment
- 'LCDDR0_SEG002': '$4', # LCD memory bit segment
- 'LCDDR0_SEG003': '$8', # LCD memory bit segment
- 'LCDDR0_SEG004': '$10', # LCD memory bit segment
- 'LCDDR0_SEG005': '$20', # LCD memory bit segment
- 'LCDDR0_SEG006': '$40', # LCD memory bit segment
- 'LCDDR0_SEG007': '$80', # LCD memory bit segment
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', #
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega329p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega329p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329pa/atmega329pa.frt b/amforth-6.5/avr8/devices/atmega329pa/atmega329pa.frt
deleted file mode 100644
index e93cfa7..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/atmega329pa.frt
+++ /dev/null
@@ -1,461 +0,0 @@
-\ Partname: ATmega329PA
-\ generated automatically
-
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $01 constant PCMSK1_PCINT8 \ Pin Change Mask Register pin 8
- $02 constant PCMSK1_PCINT9 \ Pin Change Mask Register pin 9
- $04 constant PCMSK1_PCINT10 \ Pin Change Mask Register pin 10
- $08 constant PCMSK1_PCINT11 \ Pin Change Mask Register pin 11
- $10 constant PCMSK1_PCINT12 \ Pin Change Mask Register pin 12
- $20 constant PCMSK1_PCINT13 \ Pin Change Mask Register pin 13
- $40 constant PCMSK1_PCINT14 \ Pin Change Mask Register pin 14
- $80 constant PCMSK1_PCINT15 \ Pin Change Mask Register pin 15
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $01 constant PCMSK0_PCINT0 \ Pin Change Mask Register pin 0
- $02 constant PCMSK0_PCINT1 \ Pin Change Mask Register pin 1
- $04 constant PCMSK0_PCINT2 \ Pin Change Mask Register pin 2
- $08 constant PCMSK0_PCINT3 \ Pin Change Mask Register pin 3
- $10 constant PCMSK0_PCINT4 \ Pin Change Mask Register pin 4
- $20 constant PCMSK0_PCINT5 \ Pin Change Mask Register pin 5
- $40 constant PCMSK0_PCINT6 \ Pin Change Mask Register pin 6
- $80 constant PCMSK0_PCINT7 \ Pin Change Mask Register pin 7
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
- $01 constant LCDDR18_SEG324 \ LCD memory bit segment
- $02 constant LCDDR18_SEG325 \ LCD memory bit segment
- $04 constant LCDDR18_SEG326 \ LCD memory bit segment
- $08 constant LCDDR18_SEG327 \ LCD memory bit segment
- $10 constant LCDDR18_SEG328 \ LCD memory bit segment
- $20 constant LCDDR18_SEG329 \ LCD memory bit segment
- $40 constant LCDDR18_SEG330 \ LCD memory bit segment
- $80 constant LCDDR18_SEG331 \ LCD memory bit segment
-&253 constant LCDDR17 \ LCD Data Register 17
- $01 constant LCDDR17_SEG316 \ LCD memory bit segment
- $02 constant LCDDR17_SEG317 \ LCD memory bit segment
- $04 constant LCDDR17_SEG318 \ LCD memory bit segment
- $08 constant LCDDR17_SEG319 \ LCD memory bit segment
- $10 constant LCDDR17_SEG320 \ LCD memory bit segment
- $20 constant LCDDR17_SEG321 \ LCD memory bit segment
- $40 constant LCDDR17_SEG322 \ LCD memory bit segment
- $80 constant LCDDR17_SEG323 \ LCD memory bit segment
-&252 constant LCDDR16 \ LCD Data Register 16
- $01 constant LCDDR16_SEG308 \ LCD memory bit segment
- $02 constant LCDDR16_SEG309 \ LCD memory bit segment
- $04 constant LCDDR16_SEG310 \ LCD memory bit segment
- $08 constant LCDDR16_SEG311 \ LCD memory bit segment
- $10 constant LCDDR16_SEG312 \ LCD memory bit segment
- $20 constant LCDDR16_SEG313 \ LCD memory bit segment
- $40 constant LCDDR16_SEG314 \ LCD memory bit segment
- $80 constant LCDDR16_SEG315 \ LCD memory bit segment
-&251 constant LCDDR15 \ LCD Data Register 15
- $01 constant LCDDR15_SEG300 \ LCD memory bit segment
- $02 constant LCDDR15_SEG301 \ LCD memory bit segment
- $04 constant LCDDR15_SEG302 \ LCD memory bit segment
- $08 constant LCDDR15_SEG302 \ LCD memory bit segment
- $10 constant LCDDR15_SEG304 \ LCD memory bit segment
- $20 constant LCDDR15_SEG305 \ LCD memory bit segment
- $40 constant LCDDR15_SEG306 \ LCD memory bit segment
- $80 constant LCDDR15_SEG307 \ LCD memory bit segment
-&249 constant LCDDR13 \ LCD Data Register 13
- $01 constant LCDDR13_SEG224 \ LCD memory bit segment
- $02 constant LCDDR13_SEG225 \ LCD memory bit segment
- $04 constant LCDDR13_SEG226 \ LCD memory bit segment
- $08 constant LCDDR13_SEG227 \ LCD memory bit segment
- $10 constant LCDDR13_SEG228 \ LCD memory bit segment
- $20 constant LCDDR13_SEG229 \ LCD memory bit segment
- $40 constant LCDDR13_SEG230 \ LCD memory bit segment
- $80 constant LCDDR13_SEG231 \ LCD memory bit segment
-&248 constant LCDDR12 \ LCD Data Register 12
- $01 constant LCDDR12_SEG216 \ LCD memory bit segment
- $02 constant LCDDR12_SEG217 \ LCD memory bit segment
- $04 constant LCDDR12_SEG218 \ LCD memory bit segment
- $08 constant LCDDR12_SEG219 \ LCD memory bit segment
- $10 constant LCDDR12_SEG220 \ LCD memory bit segment
- $20 constant LCDDR12_SEG221 \ LCD memory bit segment
- $40 constant LCDDR12_SEG222 \ LCD memory bit segment
- $80 constant LCDDR12_SEG223 \ LCD memory bit segment
-&247 constant LCDDR11 \ LCD Data Register 11
- $01 constant LCDDR11_SEG208 \ LCD memory bit segment
- $02 constant LCDDR11_SEG209 \ LCD memory bit segment
- $04 constant LCDDR11_SEG210 \ LCD memory bit segment
- $08 constant LCDDR11_SEG211 \ LCD memory bit segment
- $10 constant LCDDR11_SEG212 \ LCD memory bit segment
- $20 constant LCDDR11_SEG213 \ LCD memory bit segment
- $40 constant LCDDR11_SEG214 \ LCD memory bit segment
- $80 constant LCDDR11_SEG215 \ LCD memory bit segment
-&246 constant LCDDR10 \ LCD Data Register 10
- $01 constant LCDDR10_SEG200 \ LCD memory bit segment
- $02 constant LCDDR10_SEG201 \ LCD memory bit segment
- $04 constant LCDDR10_SEG202 \ LCD memory bit segment
- $08 constant LCDDR10_SEG203 \ LCD memory bit segment
- $10 constant LCDDR10_SEG204 \ LCD memory bit segment
- $20 constant LCDDR10_SEG205 \ LCD memory bit segment
- $40 constant LCDDR10_SEG206 \ LCD memory bit segment
- $80 constant LCDDR10_SEG207 \ LCD memory bit segment
-&244 constant LCDDR8 \ LCD Data Register 8
- $01 constant LCDDR8_SEG124 \ LCD memory bit segment
- $02 constant LCDDR8_SEG125 \ LCD memory bit segment
- $04 constant LCDDR8_SEG126 \ LCD memory bit segment
- $08 constant LCDDR8_SEG127 \ LCD memory bit segment
- $10 constant LCDDR8_SEG128 \ LCD memory bit segment
- $20 constant LCDDR8_SEG129 \ LCD memory bit segment
- $40 constant LCDDR8_SEG130 \ LCD memory bit segment
- $80 constant LCDDR8_SEG131 \ LCD memory bit segment
-&243 constant LCDDR7 \ LCD Data Register 7
- $01 constant LCDDR7_SEG116 \ LCD memory bit segment
- $02 constant LCDDR7_SEG117 \ LCD memory bit segment
- $04 constant LCDDR7_SEG118 \ LCD memory bit segment
- $08 constant LCDDR7_SEG119 \ LCD memory bit segment
- $10 constant LCDDR7_SEG120 \ LCD memory bit segment
- $20 constant LCDDR7_SEG121 \ LCD memory bit segment
- $40 constant LCDDR7_SEG122 \ LCD memory bit segment
- $80 constant LCDDR7_SEG123 \ LCD memory bit segment
-&242 constant LCDDR6 \ LCD Data Register 6
- $01 constant LCDDR6_SEG108 \ LCD memory bit segment
- $02 constant LCDDR6_SEG109 \ LCD memory bit segment
- $04 constant LCDDR6_SEG110 \ LCD memory bit segment
- $08 constant LCDDR6_SEG111 \ LCD memory bit segment
- $10 constant LCDDR6_SEG112 \ LCD memory bit segment
- $20 constant LCDDR6_SEG113 \ LCD memory bit segment
- $40 constant LCDDR6_SEG114 \ LCD memory bit segment
- $80 constant LCDDR6_SEG115 \ LCD memory bit segment
-&241 constant LCDDR5 \ LCD Data Register 5
- $01 constant LCDDR5_SEG100 \ LCD memory bit segment
- $02 constant LCDDR5_SEG101 \ LCD memory bit segment
- $04 constant LCDDR5_SEG102 \ LCD memory bit segment
- $08 constant LCDDR5_SEG103 \ LCD memory bit segment
- $10 constant LCDDR5_SEG104 \ LCD memory bit segment
- $20 constant LCDDR5_SEG105 \ LCD memory bit segment
- $40 constant LCDDR5_SEG106 \ LCD memory bit segment
- $80 constant LCDDR5_SEG107 \ LCD memory bit segment
-&239 constant LCDDR3 \ LCD Data Register 3
- $01 constant LCDDR3_SEG024 \ LCD memory bit segment
- $02 constant LCDDR3_SEG025 \ LCD memory bit segment
- $04 constant LCDDR3_SEG026 \ LCD memory bit segment
- $08 constant LCDDR3_SEG027 \ LCD memory bit segment
- $10 constant LCDDR3_SEG028 \ LCD memory bit segment
- $20 constant LCDDR3_SEG029 \ LCD memory bit segment
- $40 constant LCDDR3_SEG030 \ LCD memory bit segment
- $80 constant LCDDR3_SEG031 \ LCD memory bit segment
-&238 constant LCDDR2 \ LCD Data Register 2
- $01 constant LCDDR2_SEG016 \ LCD memory bit segment
- $02 constant LCDDR2_SEG017 \ LCD memory bit segment
- $04 constant LCDDR2_SEG018 \ LCD memory bit segment
- $08 constant LCDDR2_SEG019 \ LCD memory bit segment
- $10 constant LCDDR2_SEG020 \ LCD memory bit segment
- $20 constant LCDDR2_SEG021 \ LCD memory bit segment
- $40 constant LCDDR2_SEG022 \ LCD memory bit segment
- $80 constant LCDDR2_SEG023 \ LCD memory bit segment
-&237 constant LCDDR1 \ LCD Data Register 1
- $01 constant LCDDR1_SEG008 \ LCD memory bit segment
- $02 constant LCDDR1_SEG009 \ LCD memory bit segment
- $04 constant LCDDR1_SEG010 \ LCD memory bit segment
- $08 constant LCDDR1_SEG011 \ LCD memory bit segment
- $10 constant LCDDR1_SEG012 \ LCD memory bit segment
- $20 constant LCDDR1_SEG013 \ LCD memory bit segment
- $40 constant LCDDR1_SEG014 \ LCD memory bit segment
- $80 constant LCDDR1_SEG015 \ LCD memory bit segment
-&236 constant LCDDR0 \ LCD Data Register 0
- $01 constant LCDDR0_SEG000 \ LCD memory bit segment
- $02 constant LCDDR0_SEG001 \ LCD memory bit segment
- $04 constant LCDDR0_SEG002 \ LCD memory bit segment
- $08 constant LCDDR0_SEG003 \ LCD memory bit segment
- $10 constant LCDDR0_SEG004 \ LCD memory bit segment
- $20 constant LCDDR0_SEG005 \ LCD memory bit segment
- $40 constant LCDDR0_SEG006 \ LCD memory bit segment
- $80 constant LCDDR0_SEG007 \ LCD memory bit segment
-&231 constant LCDCCR \ LCD Contrast Control Register
- $E0 constant LCDCCR_LCDDC \
- $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
- $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
- $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329pa/device.asm b/amforth-6.5/avr8/devices/atmega329pa/device.asm
deleted file mode 100644
index 68258ab..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega329PA
-; generated automatically, do not edit
-
-.nolist
- .include "m329PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USI = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.set WANT_LCD = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 11
- .db "ATmega329PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329pa/device.inc b/amforth-6.5/avr8/devices/atmega329pa/device.inc
deleted file mode 100644
index a37dea9..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega329PA
-; generated automatically, no not edit
-
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega329pa/device.py b/amforth-6.5/avr8/devices/atmega329pa/device.py
deleted file mode 100644
index 2b36098..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/device.py
+++ /dev/null
@@ -1,504 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega329PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT8': '$1', # Pin Change Mask Register pin 8
- 'PCMSK1_PCINT9': '$2', # Pin Change Mask Register pin 9
- 'PCMSK1_PCINT10': '$4', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT11': '$8', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT12': '$10', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT13': '$20', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT14': '$40', # Pin Change Mask Register pin 1
- 'PCMSK1_PCINT15': '$80', # Pin Change Mask Register pin 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT0': '$1', # Pin Change Mask Register pin 0
- 'PCMSK0_PCINT1': '$2', # Pin Change Mask Register pin 1
- 'PCMSK0_PCINT2': '$4', # Pin Change Mask Register pin 2
- 'PCMSK0_PCINT3': '$8', # Pin Change Mask Register pin 3
- 'PCMSK0_PCINT4': '$10', # Pin Change Mask Register pin 4
- 'PCMSK0_PCINT5': '$20', # Pin Change Mask Register pin 5
- 'PCMSK0_PCINT6': '$40', # Pin Change Mask Register pin 6
- 'PCMSK0_PCINT7': '$80', # Pin Change Mask Register pin 7
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR18_SEG324': '$1', # LCD memory bit segment
- 'LCDDR18_SEG325': '$2', # LCD memory bit segment
- 'LCDDR18_SEG326': '$4', # LCD memory bit segment
- 'LCDDR18_SEG327': '$8', # LCD memory bit segment
- 'LCDDR18_SEG328': '$10', # LCD memory bit segment
- 'LCDDR18_SEG329': '$20', # LCD memory bit segment
- 'LCDDR18_SEG330': '$40', # LCD memory bit segment
- 'LCDDR18_SEG331': '$80', # LCD memory bit segment
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR17_SEG316': '$1', # LCD memory bit segment
- 'LCDDR17_SEG317': '$2', # LCD memory bit segment
- 'LCDDR17_SEG318': '$4', # LCD memory bit segment
- 'LCDDR17_SEG319': '$8', # LCD memory bit segment
- 'LCDDR17_SEG320': '$10', # LCD memory bit segment
- 'LCDDR17_SEG321': '$20', # LCD memory bit segment
- 'LCDDR17_SEG322': '$40', # LCD memory bit segment
- 'LCDDR17_SEG323': '$80', # LCD memory bit segment
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR16_SEG308': '$1', # LCD memory bit segment
- 'LCDDR16_SEG309': '$2', # LCD memory bit segment
- 'LCDDR16_SEG310': '$4', # LCD memory bit segment
- 'LCDDR16_SEG311': '$8', # LCD memory bit segment
- 'LCDDR16_SEG312': '$10', # LCD memory bit segment
- 'LCDDR16_SEG313': '$20', # LCD memory bit segment
- 'LCDDR16_SEG314': '$40', # LCD memory bit segment
- 'LCDDR16_SEG315': '$80', # LCD memory bit segment
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR15_SEG300': '$1', # LCD memory bit segment
- 'LCDDR15_SEG301': '$2', # LCD memory bit segment
- 'LCDDR15_SEG302': '$4', # LCD memory bit segment
- 'LCDDR15_SEG302': '$8', # LCD memory bit segment
- 'LCDDR15_SEG304': '$10', # LCD memory bit segment
- 'LCDDR15_SEG305': '$20', # LCD memory bit segment
- 'LCDDR15_SEG306': '$40', # LCD memory bit segment
- 'LCDDR15_SEG307': '$80', # LCD memory bit segment
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR13_SEG224': '$1', # LCD memory bit segment
- 'LCDDR13_SEG225': '$2', # LCD memory bit segment
- 'LCDDR13_SEG226': '$4', # LCD memory bit segment
- 'LCDDR13_SEG227': '$8', # LCD memory bit segment
- 'LCDDR13_SEG228': '$10', # LCD memory bit segment
- 'LCDDR13_SEG229': '$20', # LCD memory bit segment
- 'LCDDR13_SEG230': '$40', # LCD memory bit segment
- 'LCDDR13_SEG231': '$80', # LCD memory bit segment
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR12_SEG216': '$1', # LCD memory bit segment
- 'LCDDR12_SEG217': '$2', # LCD memory bit segment
- 'LCDDR12_SEG218': '$4', # LCD memory bit segment
- 'LCDDR12_SEG219': '$8', # LCD memory bit segment
- 'LCDDR12_SEG220': '$10', # LCD memory bit segment
- 'LCDDR12_SEG221': '$20', # LCD memory bit segment
- 'LCDDR12_SEG222': '$40', # LCD memory bit segment
- 'LCDDR12_SEG223': '$80', # LCD memory bit segment
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR11_SEG208': '$1', # LCD memory bit segment
- 'LCDDR11_SEG209': '$2', # LCD memory bit segment
- 'LCDDR11_SEG210': '$4', # LCD memory bit segment
- 'LCDDR11_SEG211': '$8', # LCD memory bit segment
- 'LCDDR11_SEG212': '$10', # LCD memory bit segment
- 'LCDDR11_SEG213': '$20', # LCD memory bit segment
- 'LCDDR11_SEG214': '$40', # LCD memory bit segment
- 'LCDDR11_SEG215': '$80', # LCD memory bit segment
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR10_SEG200': '$1', # LCD memory bit segment
- 'LCDDR10_SEG201': '$2', # LCD memory bit segment
- 'LCDDR10_SEG202': '$4', # LCD memory bit segment
- 'LCDDR10_SEG203': '$8', # LCD memory bit segment
- 'LCDDR10_SEG204': '$10', # LCD memory bit segment
- 'LCDDR10_SEG205': '$20', # LCD memory bit segment
- 'LCDDR10_SEG206': '$40', # LCD memory bit segment
- 'LCDDR10_SEG207': '$80', # LCD memory bit segment
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR8_SEG124': '$1', # LCD memory bit segment
- 'LCDDR8_SEG125': '$2', # LCD memory bit segment
- 'LCDDR8_SEG126': '$4', # LCD memory bit segment
- 'LCDDR8_SEG127': '$8', # LCD memory bit segment
- 'LCDDR8_SEG128': '$10', # LCD memory bit segment
- 'LCDDR8_SEG129': '$20', # LCD memory bit segment
- 'LCDDR8_SEG130': '$40', # LCD memory bit segment
- 'LCDDR8_SEG131': '$80', # LCD memory bit segment
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR7_SEG116': '$1', # LCD memory bit segment
- 'LCDDR7_SEG117': '$2', # LCD memory bit segment
- 'LCDDR7_SEG118': '$4', # LCD memory bit segment
- 'LCDDR7_SEG119': '$8', # LCD memory bit segment
- 'LCDDR7_SEG120': '$10', # LCD memory bit segment
- 'LCDDR7_SEG121': '$20', # LCD memory bit segment
- 'LCDDR7_SEG122': '$40', # LCD memory bit segment
- 'LCDDR7_SEG123': '$80', # LCD memory bit segment
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR6_SEG108': '$1', # LCD memory bit segment
- 'LCDDR6_SEG109': '$2', # LCD memory bit segment
- 'LCDDR6_SEG110': '$4', # LCD memory bit segment
- 'LCDDR6_SEG111': '$8', # LCD memory bit segment
- 'LCDDR6_SEG112': '$10', # LCD memory bit segment
- 'LCDDR6_SEG113': '$20', # LCD memory bit segment
- 'LCDDR6_SEG114': '$40', # LCD memory bit segment
- 'LCDDR6_SEG115': '$80', # LCD memory bit segment
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR5_SEG100': '$1', # LCD memory bit segment
- 'LCDDR5_SEG101': '$2', # LCD memory bit segment
- 'LCDDR5_SEG102': '$4', # LCD memory bit segment
- 'LCDDR5_SEG103': '$8', # LCD memory bit segment
- 'LCDDR5_SEG104': '$10', # LCD memory bit segment
- 'LCDDR5_SEG105': '$20', # LCD memory bit segment
- 'LCDDR5_SEG106': '$40', # LCD memory bit segment
- 'LCDDR5_SEG107': '$80', # LCD memory bit segment
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR3_SEG024': '$1', # LCD memory bit segment
- 'LCDDR3_SEG025': '$2', # LCD memory bit segment
- 'LCDDR3_SEG026': '$4', # LCD memory bit segment
- 'LCDDR3_SEG027': '$8', # LCD memory bit segment
- 'LCDDR3_SEG028': '$10', # LCD memory bit segment
- 'LCDDR3_SEG029': '$20', # LCD memory bit segment
- 'LCDDR3_SEG030': '$40', # LCD memory bit segment
- 'LCDDR3_SEG031': '$80', # LCD memory bit segment
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR2_SEG016': '$1', # LCD memory bit segment
- 'LCDDR2_SEG017': '$2', # LCD memory bit segment
- 'LCDDR2_SEG018': '$4', # LCD memory bit segment
- 'LCDDR2_SEG019': '$8', # LCD memory bit segment
- 'LCDDR2_SEG020': '$10', # LCD memory bit segment
- 'LCDDR2_SEG021': '$20', # LCD memory bit segment
- 'LCDDR2_SEG022': '$40', # LCD memory bit segment
- 'LCDDR2_SEG023': '$80', # LCD memory bit segment
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR1_SEG008': '$1', # LCD memory bit segment
- 'LCDDR1_SEG009': '$2', # LCD memory bit segment
- 'LCDDR1_SEG010': '$4', # LCD memory bit segment
- 'LCDDR1_SEG011': '$8', # LCD memory bit segment
- 'LCDDR1_SEG012': '$10', # LCD memory bit segment
- 'LCDDR1_SEG013': '$20', # LCD memory bit segment
- 'LCDDR1_SEG014': '$40', # LCD memory bit segment
- 'LCDDR1_SEG015': '$80', # LCD memory bit segment
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDDR0_SEG000': '$1', # LCD memory bit segment
- 'LCDDR0_SEG001': '$2', # LCD memory bit segment
- 'LCDDR0_SEG002': '$4', # LCD memory bit segment
- 'LCDDR0_SEG003': '$8', # LCD memory bit segment
- 'LCDDR0_SEG004': '$10', # LCD memory bit segment
- 'LCDDR0_SEG005': '$20', # LCD memory bit segment
- 'LCDDR0_SEG006': '$40', # LCD memory bit segment
- 'LCDDR0_SEG007': '$80', # LCD memory bit segment
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDCCR_LCDDC': '$e0', #
- 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
- 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
- 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Sleep
- 'MCUCR_BODSE': '$20', # BOD Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega329pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329pa/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega329pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32a/atmega32a.frt b/amforth-6.5/avr8/devices/atmega32a/atmega32a.frt
deleted file mode 100644
index d904f82..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/atmega32a.frt
+++ /dev/null
@@ -1,216 +0,0 @@
-\ Partname: ATmega32A
-\ generated automatically
-
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDTOE \ RW
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
-&85 constant MCUCR \ General Interrupt Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&92 constant OCR0 \ Output Compare Register
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Pulse Width Modulator Enable
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Clear Timer/Counter2 on Compare Match
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ ANALOG_COMPARATOR
-&80 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&81 constant OSCCAL \ Oscillator Calibration Value
-\ BOOT_LOAD
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read While Write secion read enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler bits
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ Serial Transfer Complete
-&26 constant USART__RXCAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data Register Empty
-&30 constant USART__TXCAddr \ USART, Tx Complete
-&32 constant ADCAddr \ ADC Conversion Complete
-&34 constant EE_RDYAddr \ EEPROM Ready
-&36 constant ANA_COMPAddr \ Analog Comparator
-&38 constant TWIAddr \ 2-wire Serial Interface
-&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega32a/device.asm b/amforth-6.5/avr8/devices/atmega32a/device.asm
deleted file mode 100644
index 3b8ea38..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega32A
-; generated automatically, do not edit
-
-.nolist
- .include "m32Adef.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_EEPROM = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_SPI = 0
-.set WANT_USART = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_TWI = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter1 Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data Register Empty
-.org 30
- rcall isr ; USART, Tx Complete
-.org 32
- rcall isr ; ADC Conversion Complete
-.org 34
- rcall isr ; EEPROM Ready
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; 2-wire Serial Interface
-.org 40
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 21
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 9
- .db "ATmega32A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32a/device.inc b/amforth-6.5/avr8/devices/atmega32a/device.inc
deleted file mode 100644
index 2098148..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/device.inc
+++ /dev/null
@@ -1,750 +0,0 @@
-; Partname: ATmega32A
-; generated automatically, no not edit
-
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32a/device.py b/amforth-6.5/avr8/devices/atmega32a/device.py
deleted file mode 100644
index f6913ba..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/device.py
+++ /dev/null
@@ -1,268 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # Serial Transfer Complete
- 'USART_RXCAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data Register Empty
- 'USART_TXCAddr' : '#30', # USART, Tx Complete
- 'ADCAddr' : '#32', # ADC Conversion Complete
- 'EE_RDYAddr' : '#34', # EEPROM Ready
- 'ANA_COMPAddr' : '#36', # Analog Comparator
- 'TWIAddr' : '#38', # 2-wire Serial Interface
- 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDTOE': '$10', # RW
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module EXTERNAL_INTERRUPT
- 'GICR' : '$5b', # General Interrupt Control Regi
- 'GICR_INT': '$c0', # External Interrupt Request 1 E
- 'GICR_INT2': '$20', # External Interrupt Request 2 E
- 'GICR_IVSEL': '$2', # Interrupt Vector Select
- 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
- 'GIFR' : '$5a', # General Interrupt Flag Registe
- 'GIFR_INTF': '$c0', # External Interrupt Flags
- 'GIFR_INTF2': '$20', # External Interrupt Flag 2
- 'MCUCR' : '$55', # General Interrupt Control Regi
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$5c', # Output Compare Register
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
- 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
- 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TCCR2' : '$45', # Timer/Counter2 Control Registe
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Pulse Width Modulator Enable
- 'TCCR2_COM2': '$30', # Compare Output Mode bits
- 'TCCR2_WGM21': '$8', # Clear Timer/Counter2 on Compar
- 'TCCR2_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$44', # Timer/Counter2
- 'OCR2' : '$43', # Timer/Counter2 Output Compare
- 'ASSR' : '$42', # Asynchronous Status Register
- 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
- 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
- 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module USART
- 'UDR' : '$2c', # USART I/O Data Register
- 'UCSRA' : '$2b', # USART Control and Status Regis
- 'UCSRA_RXC': '$80', # USART Receive Complete
- 'UCSRA_TXC': '$40', # USART Transmitt Complete
- 'UCSRA_UDRE': '$20', # USART Data Register Empty
- 'UCSRA_FE': '$10', # Framing Error
- 'UCSRA_DOR': '$8', # Data overRun
- 'UCSRA_UPE': '$4', # Parity Error
- 'UCSRA_U2X': '$2', # Double the USART transmission
- 'UCSRA_MPCM': '$1', # Multi-processor Communication
- 'UCSRB' : '$2a', # USART Control and Status Regis
- 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
- 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
- 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
- 'UCSRB_RXEN': '$10', # Receiver Enable
- 'UCSRB_TXEN': '$8', # Transmitter Enable
- 'UCSRB_UCSZ2': '$4', # Character Size
- 'UCSRB_RXB8': '$2', # Receive Data Bit 8
- 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
- 'UCSRC' : '$40', # USART Control and Status Regis
- 'UCSRC_URSEL': '$80', # Register Select
- 'UCSRC_UMSEL': '$40', # USART Mode Select
- 'UCSRC_UPM': '$30', # Parity Mode Bits
- 'UCSRC_USBS': '$8', # Stop Bit Select
- 'UCSRC_UCSZ': '$6', # Character Size
- 'UCSRC_UCPOL': '$1', # Clock Polarity
- 'UBRRH' : '$40', # USART Baud Rate Register Hight
- 'UBRRL' : '$29', # USART Baud Rate Register Low B
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # When this bit is written to on
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$24', # ADC Data Register Bytes
- 'SFIOR' : '$50', # Special Function IO Register
- 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SE': '$80', # Sleep Enable
- 'MCUCR_SM': '$70', # Sleep Mode Select
- 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
- 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$51', # Oscillator Calibration Value
- 'SFIOR' : '$50', # Special Function IO Register
-
-# Module BOOT_LOAD
- 'SPMCR' : '$57', # Store Program Memory Control R
- 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCR_RWWSRE': '$10', # Read While Write secion read e
- 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCR_PGWRT': '$4', # Page Write
- 'SPMCR_PGERS': '$2', # Page Erase
- 'SPMCR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module TWI
- 'TWBR' : '$20', # TWI Bit Rate register
- 'TWCR' : '$56', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$21', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler bits
- 'TWDR' : '$23', # TWI Data register
- 'TWAR' : '$22', # TWI (Slave) Address register
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32a/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega32a/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt b/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt
deleted file mode 100644
index 118eaba..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt
+++ /dev/null
@@ -1,454 +0,0 @@
-\ Partname: ATmega32C1
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVFG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register Flags
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
- $08 constant CANGIT_SERG \ Stuff Error General Flag
- $04 constant CANGIT_CERG \ CRC Error General Flag
- $02 constant CANGIT_FERG \ Form Error General Flag
- $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register 2
- $3F constant CANEN2_ENMOB \ Enable MObs
-&221 constant CANEN1 \ Enable MOb Register 1(empty)
-&222 constant CANIE2 \ Enable Interrupt MOb Register 2
- $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
-&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
- $3F constant CANSIT2_SIT \ Status of Interrupt MObs
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
-&226 constant CANBT1 \ CAN Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ CAN Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
- $0E constant CANBT2_PRS \ Propagation Time Segment bits
-&228 constant CANBT3 \ CAN Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
- $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
- $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
- $0F constant CANHPMOB_CGP \ CAN General Purpose bits
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
- $07 constant CANPAGE_INDX \ Data Buffer Index bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
- $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
- $20 constant CANSTMOB_RXOK \ Receive OK on MOb
- $10 constant CANSTMOB_BERR \ Bit Error on MOb
- $08 constant CANSTMOB_SERR \ Stuff Error on MOb
- $04 constant CANSTMOB_CERR \ CRC Error on MOb
- $02 constant CANSTMOB_FERR \ Form Error on MOb
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
- $F8 constant CANIDT4_IDT \
- $04 constant CANIDT4_RTRTAG \
- $02 constant CANIDT4_RB1TAG \
- $01 constant CANIDT4_RB0TAG \
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-\ ANALOG_COMPARATOR
-&148 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
- $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&149 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&150 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&151 constant AC3CON \ Analog Comparator 3 Control Register
- $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
- $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&146 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&145 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&144 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $40 constant PRR_PRCAN \ Power Reduction CAN
- $20 constant PRR_PRPSC \ Power Reduction PSC
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRLIN \ Power Reduction LIN UART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ISRCEN \ Current Source Enable
- $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
- $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
- $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
- $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
- $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
- $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
- $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
- $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
-&117 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
- $07 constant AMP0CSR_AMP0TS \
-&118 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
- $07 constant AMP1CSR_AMP1TS \
-&119 constant AMP2CSR \
- $80 constant AMP2CSR_AMP2EN \
- $40 constant AMP2CSR_AMP2IS \
- $30 constant AMP2CSR_AMP2G \
- $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
- $07 constant AMP2CSR_AMP2TS \
-\ LINUART
-&200 constant LINCR \ LIN Control Register
- $80 constant LINCR_LSWRES \ Software Reset
- $40 constant LINCR_LIN13 \ LIN Standard
- $30 constant LINCR_LCONF \ LIN Configuration bits
- $08 constant LINCR_LENA \ LIN or UART Enable
- $07 constant LINCR_LCMD \ LIN Command and Mode bits
-&201 constant LINSIR \ LIN Status and Interrupt Register
- $E0 constant LINSIR_LIDST \ Identifier Status bits
- $10 constant LINSIR_LBUSY \ Busy Signal
- $08 constant LINSIR_LERR \ Error Interrupt
- $04 constant LINSIR_LIDOK \ Identifier Interrupt
- $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
- $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
-&202 constant LINENIR \ LIN Enable Interrupt Register
- $08 constant LINENIR_LENERR \ Enable Error Interrupt
- $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
- $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
- $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
-&203 constant LINERR \ LIN Error Register
- $80 constant LINERR_LABORT \ Abort Flag
- $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
- $20 constant LINERR_LOVERR \ Overrun Error Flag
- $10 constant LINERR_LFERR \ Framing Error Flag
- $08 constant LINERR_LSERR \ Synchronization Error Flag
- $04 constant LINERR_LPERR \ Parity Error Flag
- $02 constant LINERR_LCERR \ Checksum Error Flag
- $01 constant LINERR_LBERR \ Bit Error Flag
-&204 constant LINBTR \ LIN Bit Timing Register
- $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
- $3F constant LINBTR_LBT \ LIN Bit Timing bits
-&205 constant LINBRRL \ LIN Baud Rate Low Register
- $FF constant LINBRRL_LDIV \
-&206 constant LINBRRH \ LIN Baud Rate High Register
- $0F constant LINBRRH_LDIV \
-&207 constant LINDLR \ LIN Data Length Register
- $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
- $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
-&208 constant LINIDR \ LIN Identifier Register
- $C0 constant LINIDR_LP \ Parity bits
- $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
-&209 constant LINSEL \ LIN Data Buffer Selection Register
- $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
- $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
-&210 constant LINDAT \ LIN Data Register
- $FF constant LINDAT_LDATA \
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK3 \ Pin Change Mask Register 3
- $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&106 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \
- $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&2 constant ANACOMP0Addr \ Analog Comparator 0
-&4 constant ANACOMP1Addr \ Analog Comparator 1
-&6 constant ANACOMP2Addr \ Analog Comparator 2
-&8 constant ANACOMP3Addr \ Analog Comparator 3
-&10 constant PSC_FAULTAddr \ PSC Fault
-&12 constant PSC_ECAddr \ PSC End of Cycle
-&14 constant INT0Addr \ External Interrupt Request 0
-&16 constant INT1Addr \ External Interrupt Request 1
-&18 constant INT2Addr \ External Interrupt Request 2
-&20 constant INT3Addr \ External Interrupt Request 3
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
-&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
-&38 constant CAN_TOVFAddr \ CAN Timer Overflow
-&40 constant LIN_TCAddr \ LIN Transfer Complete
-&42 constant LIN_ERRAddr \ LIN Error
-&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&54 constant ADCAddr \ ADC Conversion Complete
-&56 constant WDTAddr \ Watchdog Time-Out Interrupt
-&58 constant EE_READYAddr \ EEPROM Ready
-&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.asm b/amforth-6.5/avr8/devices/atmega32c1/device.asm
deleted file mode 100644
index b43163d..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/device.asm
+++ /dev/null
@@ -1,119 +0,0 @@
-; Partname: ATmega32C1
-; generated automatically, do not edit
-
-.nolist
- .include "m32C1def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CAN = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_LINUART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Analog Comparator 0
-.org 4
- rcall isr ; Analog Comparator 1
-.org 6
- rcall isr ; Analog Comparator 2
-.org 8
- rcall isr ; Analog Comparator 3
-.org 10
- rcall isr ; PSC Fault
-.org 12
- rcall isr ; PSC End of Cycle
-.org 14
- rcall isr ; External Interrupt Request 0
-.org 16
- rcall isr ; External Interrupt Request 1
-.org 18
- rcall isr ; External Interrupt Request 2
-.org 20
- rcall isr ; External Interrupt Request 3
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter1 Compare Match B
-.org 28
- rcall isr ; Timer1/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match A
-.org 32
- rcall isr ; Timer/Counter0 Compare Match B
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN MOB, Burst, General Errors
-.org 38
- rcall isr ; CAN Timer Overflow
-.org 40
- rcall isr ; LIN Transfer Complete
-.org 42
- rcall isr ; LIN Error
-.org 44
- rcall isr ; Pin Change Interrupt Request 0
-.org 46
- rcall isr ; Pin Change Interrupt Request 1
-.org 48
- rcall isr ; Pin Change Interrupt Request 2
-.org 50
- rcall isr ; Pin Change Interrupt Request 3
-.org 52
- rcall isr ; SPI Serial Transfer Complete
-.org 54
- rcall isr ; ADC Conversion Complete
-.org 56
- rcall isr ; Watchdog Time-Out Interrupt
-.org 58
- rcall isr ; EEPROM Ready
-.org 60
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega32C1"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.inc b/amforth-6.5/avr8/devices/atmega32c1/device.inc
deleted file mode 100644
index c2891e4..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/device.inc
+++ /dev/null
@@ -1,1503 +0,0 @@
-; Partname: ATmega32C1
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register Flags
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 2
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 1(empty)
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 2
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 1 (empty)
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 2
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 1 (empty)
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 3 Control Register
-VE_AC3CON:
- .dw $ff06
- .db "AC3CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3CON
-XT_AC3CON:
- .dw PFA_DOVARIABLE
-PFA_AC3CON:
- .dw 151
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 144
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP2CSR:
- .dw $ff07
- .db "AMP2CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP2CSR
-XT_AMP2CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP2CSR:
- .dw 119
-
-.endif
-.if WANT_LINUART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Control Register
-VE_LINCR:
- .dw $ff05
- .db "LINCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINCR
-XT_LINCR:
- .dw PFA_DOVARIABLE
-PFA_LINCR:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Status and Interrupt Register
-VE_LINSIR:
- .dw $ff06
- .db "LINSIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSIR
-XT_LINSIR:
- .dw PFA_DOVARIABLE
-PFA_LINSIR:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Enable Interrupt Register
-VE_LINENIR:
- .dw $ff07
- .db "LINENIR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINENIR
-XT_LINENIR:
- .dw PFA_DOVARIABLE
-PFA_LINENIR:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Error Register
-VE_LINERR:
- .dw $ff06
- .db "LINERR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINERR
-XT_LINERR:
- .dw PFA_DOVARIABLE
-PFA_LINERR:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Bit Timing Register
-VE_LINBTR:
- .dw $ff06
- .db "LINBTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBTR
-XT_LINBTR:
- .dw PFA_DOVARIABLE
-PFA_LINBTR:
- .dw 204
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate Low Register
-VE_LINBRRL:
- .dw $ff07
- .db "LINBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRL
-XT_LINBRRL:
- .dw PFA_DOVARIABLE
-PFA_LINBRRL:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate High Register
-VE_LINBRRH:
- .dw $ff07
- .db "LINBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRH
-XT_LINBRRH:
- .dw PFA_DOVARIABLE
-PFA_LINBRRH:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Length Register
-VE_LINDLR:
- .dw $ff06
- .db "LINDLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDLR
-XT_LINDLR:
- .dw PFA_DOVARIABLE
-PFA_LINDLR:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Identifier Register
-VE_LINIDR:
- .dw $ff06
- .db "LINIDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINIDR
-XT_LINIDR:
- .dw PFA_DOVARIABLE
-PFA_LINIDR:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Buffer Selection Register
-VE_LINSEL:
- .dw $ff06
- .db "LINSEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSEL
-XT_LINSEL:
- .dw PFA_DOVARIABLE
-PFA_LINSEL:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Register
-VE_LINDAT:
- .dw $ff06
- .db "LINDAT"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDAT
-XT_LINDAT:
- .dw PFA_DOVARIABLE
-PFA_LINDAT:
- .dw 210
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.py b/amforth-6.5/avr8/devices/atmega32c1/device.py
deleted file mode 100644
index fe62918..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/device.py
+++ /dev/null
@@ -1,477 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32C1
-
-MCUREGS = {
-# Interrupt Vectors
- 'ANACOMP0Addr' : '#2', # Analog Comparator 0
- 'ANACOMP1Addr' : '#4', # Analog Comparator 1
- 'ANACOMP2Addr' : '#6', # Analog Comparator 2
- 'ANACOMP3Addr' : '#8', # Analog Comparator 3
- 'PSC_FAULTAddr' : '#10', # PSC Fault
- 'PSC_ECAddr' : '#12', # PSC End of Cycle
- 'INT0Addr' : '#14', # External Interrupt Request 0
- 'INT1Addr' : '#16', # External Interrupt Request 1
- 'INT2Addr' : '#18', # External Interrupt Request 2
- 'INT3Addr' : '#20', # External Interrupt Request 3
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
- 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
- 'LIN_TCAddr' : '#40', # LIN Transfer Complete
- 'LIN_ERRAddr' : '#42', # LIN Error
- 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
- 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
- 'ADCAddr' : '#54', # ADC Conversion Complete
- 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
- 'EE_READYAddr' : '#58', # EEPROM Ready
- 'SPM_READYAddr' : '#60', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVFG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
- 'CANGIT_SERG': '$8', # Stuff Error General Flag
- 'CANGIT_CERG': '$4', # CRC Error General Flag
- 'CANGIT_FERG': '$2', # Form Error General Flag
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register 2
- 'CANEN2_ENMOB': '$3f', # Enable MObs
- 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # CAN Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # CAN Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
- 'CANBT2_PRS': '$e', # Propagation Time Segment bits
- 'CANBT3' : '$e4', # CAN Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
- 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
- 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
- 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
- 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
- 'CANSTMOB_BERR': '$10', # Bit Error on MOb
- 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
- 'CANSTMOB_CERR': '$4', # CRC Error on MOb
- 'CANSTMOB_FERR': '$2', # Form Error on MOb
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT4_IDT': '$f8', #
- 'CANIDT4_RTRTAG': '$4', #
- 'CANIDT4_RB1TAG': '$2', #
- 'CANIDT4_RB0TAG': '$1', #
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$94', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$95', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$96', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'AC3CON' : '$97', # Analog Comparator 3 Control Re
- 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
- 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$92', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$91', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$90', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRCAN': '$40', # Power Reduction CAN
- 'PRR_PRPSC': '$20', # Power Reduction PSC
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRLIN': '$2', # Power Reduction LIN UART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ISRCEN': '$40', # Current Source Enable
- 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
- 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
- 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
- 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
- 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
- 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
- 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
- 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
- 'AMP0CSR' : '$75', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
- 'AMP0CSR_AMP0TS': '$7', #
- 'AMP1CSR' : '$76', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
- 'AMP1CSR_AMP1TS': '$7', #
- 'AMP2CSR' : '$77', #
- 'AMP2CSR_AMP2EN': '$80', #
- 'AMP2CSR_AMP2IS': '$40', #
- 'AMP2CSR_AMP2G': '$30', #
- 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
- 'AMP2CSR_AMP2TS': '$7', #
-
-# Module LINUART
- 'LINCR' : '$c8', # LIN Control Register
- 'LINCR_LSWRES': '$80', # Software Reset
- 'LINCR_LIN13': '$40', # LIN Standard
- 'LINCR_LCONF': '$30', # LIN Configuration bits
- 'LINCR_LENA': '$8', # LIN or UART Enable
- 'LINCR_LCMD': '$7', # LIN Command and Mode bits
- 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
- 'LINSIR_LIDST': '$e0', # Identifier Status bits
- 'LINSIR_LBUSY': '$10', # Busy Signal
- 'LINSIR_LERR': '$8', # Error Interrupt
- 'LINSIR_LIDOK': '$4', # Identifier Interrupt
- 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
- 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
- 'LINENIR' : '$ca', # LIN Enable Interrupt Register
- 'LINENIR_LENERR': '$8', # Enable Error Interrupt
- 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
- 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
- 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
- 'LINERR' : '$cb', # LIN Error Register
- 'LINERR_LABORT': '$80', # Abort Flag
- 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
- 'LINERR_LOVERR': '$20', # Overrun Error Flag
- 'LINERR_LFERR': '$10', # Framing Error Flag
- 'LINERR_LSERR': '$8', # Synchronization Error Flag
- 'LINERR_LPERR': '$4', # Parity Error Flag
- 'LINERR_LCERR': '$2', # Checksum Error Flag
- 'LINERR_LBERR': '$1', # Bit Error Flag
- 'LINBTR' : '$cc', # LIN Bit Timing Register
- 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
- 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
- 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
- 'LINBRRL_LDIV': '$ff', #
- 'LINBRRH' : '$ce', # LIN Baud Rate High Register
- 'LINBRRH_LDIV': '$f', #
- 'LINDLR' : '$cf', # LIN Data Length Register
- 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
- 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
- 'LINIDR' : '$d0', # LIN Identifier Register
- 'LINIDR_LP': '$c0', # Parity bits
- 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
- 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
- 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
- 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
- 'LINDAT' : '$d2', # LIN Data Register
- 'LINDAT_LDATA': '$ff', #
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
- 'PCMSK3' : '$6d', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
- 'PCMSK2' : '$6c', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6b', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6a', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/atmega32hvb.frt b/amforth-6.5/avr8/devices/atmega32hvb/atmega32hvb.frt
deleted file mode 100644
index 5a117ed..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/atmega32hvb.frt
+++ /dev/null
@@ -1,33 +0,0 @@
-\ Partname: ATmega32HVB
-\ generated automatically
-
-
-\ Interrupts
-&2 constant BPINTAddr \ Battery Protection Interrupt
-&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
-&6 constant INT0Addr \ External Interrupt Request 0
-&8 constant INT1Addr \ External Interrupt Request 1
-&10 constant INT2Addr \ External Interrupt Request 2
-&12 constant INT3Addr \ External Interrupt Request 3
-&14 constant PCINT0Addr \ Pin Change Interrupt 0
-&16 constant PCINT1Addr \ Pin Change Interrupt 1
-&18 constant WDTAddr \ Watchdog Timeout Interrupt
-&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
-&22 constant CHDETAddr \ Charger Detect
-&24 constant TIMER1_ICAddr \ Timer 1 Input capture
-&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer 1 overflow
-&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
-&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
-&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
-&42 constant TWIAddr \ Two-Wire Serial Interface
-&44 constant SPI_STCAddr \ SPI Serial transfer complete
-&46 constant VADCAddr \ Voltage ADC Conversion Complete
-&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/device.asm b/amforth-6.5/avr8/devices/atmega32hvb/device.asm
deleted file mode 100644
index 310e3e7..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega32HVB
-; generated automatically, do not edit
-
-.nolist
- .include "m32HVBdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Battery Protection Interrupt
-.org 4
- rcall isr ; Voltage regulator monitor interrupt
-.org 6
- rcall isr ; External Interrupt Request 0
-.org 8
- rcall isr ; External Interrupt Request 1
-.org 10
- rcall isr ; External Interrupt Request 2
-.org 12
- rcall isr ; External Interrupt Request 3
-.org 14
- rcall isr ; Pin Change Interrupt 0
-.org 16
- rcall isr ; Pin Change Interrupt 1
-.org 18
- rcall isr ; Watchdog Timeout Interrupt
-.org 20
- rcall isr ; Bandgap Buffer Short Circuit Detected
-.org 22
- rcall isr ; Charger Detect
-.org 24
- rcall isr ; Timer 1 Input capture
-.org 26
- rcall isr ; Timer 1 Compare Match A
-.org 28
- rcall isr ; Timer 1 Compare Match B
-.org 30
- rcall isr ; Timer 1 overflow
-.org 32
- rcall isr ; Timer 0 Input Capture
-.org 34
- rcall isr ; Timer 0 Comapre Match A
-.org 36
- rcall isr ; Timer 0 Compare Match B
-.org 38
- rcall isr ; Timer 0 Overflow
-.org 40
- rcall isr ; Two-Wire Bus Connect/Disconnect
-.org 42
- rcall isr ; Two-Wire Serial Interface
-.org 44
- rcall isr ; SPI Serial transfer complete
-.org 46
- rcall isr ; Voltage ADC Conversion Complete
-.org 48
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org 50
- rcall isr ; Coloumb Counter ADC Regular Current
-.org 52
- rcall isr ; Coloumb Counter ADC Accumulator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; SPM Ready
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 11
- .db "ATmega32HVB",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/device.inc b/amforth-6.5/avr8/devices/atmega32hvb/device.inc
deleted file mode 100644
index 9ea3b65..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/device.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-; Partname: ATmega32HVB
-; generated automatically, no not edit
-
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/device.py b/amforth-6.5/avr8/devices/atmega32hvb/device.py
deleted file mode 100644
index 0c72334..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/device.py
+++ /dev/null
@@ -1,342 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32HVB
-
-MCUREGS = {
-# Interrupt Vectors
- 'BPINTAddr' : '#2', # Battery Protection Interrupt
- 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
- 'INT0Addr' : '#6', # External Interrupt Request 0
- 'INT1Addr' : '#8', # External Interrupt Request 1
- 'INT2Addr' : '#10', # External Interrupt Request 2
- 'INT3Addr' : '#12', # External Interrupt Request 3
- 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
- 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
- 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
- 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
- 'CHDETAddr' : '#22', # Charger Detect
- 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
- 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
- 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
- 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
- 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
- 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
- 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
- 'TWIAddr' : '#42', # Two-Wire Serial Interface
- 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
- 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
- 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
- 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
- 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPMAddr' : '#56', # SPM Ready
-
-# Module AD_CONVERTER
- 'VADMUX' : '$7c', # The VADC multiplexer Selection
- 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
- 'VADC' : '$78', # VADC Data Register Bytes
- 'VADCSR' : '$7a', # The VADC Control and Status re
- 'VADCSR_VADEN': '$8', # VADC Enable
- 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
- 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
- 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module FET
- 'FCSR' : '$f0', # FET Control and Status Registe
- 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
- 'FCSR_CPS': '$4', # Current Protection Status
- 'FCSR_DFE': '$2', # Discharge FET Enable
- 'FCSR_CFE': '$1', # Charge FET Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module COULOMB_COUNTER
- 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
- 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
- 'CADCSRA_CADPOL': '$40', #
- 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
- 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
- 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
- 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
- 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
- 'CADCSRB_CADACIE': '$40', #
- 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
- 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
- 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
- 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
- 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
- 'CADIC' : '$e4', # CC-ADC Instantaneous Current
- 'CADAC3' : '$e3', # ADC Accumulate Current
- 'CADAC2' : '$e2', # ADC Accumulate Current
- 'CADAC1' : '$e1', # ADC Accumulate Current
- 'CADAC0' : '$e0', # ADC Accumulate Current
- 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
- 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
-
-# Module TWI
- 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
- 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
- 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
- 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
-
-# Module TIMER_COUNTER_1
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_CS': '$7', # Clock Select1 bis
- 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
- 'TCCR1A_TCW1': '$80', # Timer/Counter Width
- 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
- 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
- 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
- 'TCCR1A_ICS1': '$8', # Input Capture Select
- 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
- 'TCNT1' : '$84', # Timer Counter 1 Bytes
- 'OCR1A' : '$88', # Output Compare Register 1A
- 'OCR1B' : '$89', # Output Compare Register B
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module CELL_BALANCING
- 'CBCR' : '$f1', # Cell Balancing Control Registe
- 'CBCR_CBE': '$f', # Cell Balancing Enables
-
-# Module BATTERY_PROTECTION
- 'BPPLR' : '$fe', # Battery Protection Parameter L
- 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
- 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
- 'BPCR' : '$fd', # Battery Protection Control Reg
- 'BPCR_EPID': '$20', # External Protection Input Disa
- 'BPCR_SCD': '$10', # Short Circuit Protection Disab
- 'BPCR_DOCD': '$8', # Discharge Over-current Protect
- 'BPCR_COCD': '$4', # Charge Over-current Protection
- 'BPCR_DHCD': '$2', # Discharge High-current Protect
- 'BPCR_CHCD': '$1', # Charge High-current Protection
- 'BPHCTR' : '$fc', # Battery Protection Short-curre
- 'BPOCTR' : '$fb', # Battery Protection Over-curren
- 'BPSCTR' : '$fa', # Battery Protection Short-curre
- 'BPCHCD' : '$f9', # Battery Protection Charge-High
- 'BPDHCD' : '$f8', # Battery Protection Discharge-H
- 'BPCOCD' : '$f7', # Battery Protection Charge-Over
- 'BPDOCD' : '$f6', # Battery Protection Discharge-O
- 'BPSCD' : '$f5', # Battery Protection Short-Circu
- 'BPIFR' : '$f3', # Battery Protection Interrupt F
- 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
- 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
- 'BPIFR_COCIF': '$4', # Charge Over-current Protection
- 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
- 'BPIFR_CHCIF': '$1', # Charge High-current Protection
- 'BPIMSK' : '$f2', # Battery Protection Interrupt M
- 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
- 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
- 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
- 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
- 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
-
-# Module CHARGER_DETECT
- 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
- 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
- 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
- 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
- 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
-
-# Module VOLTAGE_REGULATOR
- 'ROCR' : '$c8', # Regulator Operating Condition
- 'ROCR_ROCS': '$80', # ROC Status
- 'ROCR_ROCD': '$10', # ROC Disable
- 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
- 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
-
-# Module BANDGAP
- 'BGCSR' : '$d2', # Bandgap Control and Status Reg
- 'BGCSR_BGD': '$20', # Bandgap Disable
- 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
- 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
- 'BGCCR' : '$d0', # Bandgap Calibration Register
- 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_CKOE': '$20', # Clock Output Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_OCDRF': '$10', # OCD Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
- 'OSICSR' : '$37', # Oscillator Sampling Interface
- 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
- 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
- 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_PA1DID': '$2', # When this bit is written logic
- 'DIDR0_PA0DID': '$1', # When this bit is written logic
- 'PRR0' : '$64', # Power Reduction Register 0
- 'PRR0_PRTWI': '$40', # Power Reduction TWI
- 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
- 'PRR0_PRSPI': '$8', # Power reduction SPI
- 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
- 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
- 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
- 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
- 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
- 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
- 'TCCR0A_TCW0': '$80', # Timer/Counter Width
- 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
- 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
- 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
- 'TCCR0A_ICS0': '$8', # Input Capture Select
- 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
- 'TCNT0' : '$46', # Timer Counter 0 Bytes
- 'OCR0A' : '$48', # Output Compare Register 0A
- 'OCR0B' : '$49', # Output Compare Register B
- 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
- 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
- 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
- 'SPMCSR_LBSET': '$8', # Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32hvb/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32hvb/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32hvb/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvb/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/atmega32hvbrevb.frt b/amforth-6.5/avr8/devices/atmega32hvbrevb/atmega32hvbrevb.frt
deleted file mode 100644
index ebba295..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/atmega32hvbrevb.frt
+++ /dev/null
@@ -1,33 +0,0 @@
-\ Partname: ATmega32HVBrevB
-\ generated automatically
-
-
-\ Interrupts
-&2 constant BPINTAddr \ Battery Protection Interrupt
-&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
-&6 constant INT0Addr \ External Interrupt Request 0
-&8 constant INT1Addr \ External Interrupt Request 1
-&10 constant INT2Addr \ External Interrupt Request 2
-&12 constant INT3Addr \ External Interrupt Request 3
-&14 constant PCINT0Addr \ Pin Change Interrupt 0
-&16 constant PCINT1Addr \ Pin Change Interrupt 1
-&18 constant WDTAddr \ Watchdog Timeout Interrupt
-&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
-&22 constant CHDETAddr \ Charger Detect
-&24 constant TIMER1_ICAddr \ Timer 1 Input capture
-&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer 1 overflow
-&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
-&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
-&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
-&42 constant TWIAddr \ Two-Wire Serial Interface
-&44 constant SPI_STCAddr \ SPI Serial transfer complete
-&46 constant VADCAddr \ Voltage ADC Conversion Complete
-&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.asm
deleted file mode 100644
index ebf0278..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; Partname: ATmega32HVBrevB
-; generated automatically, do not edit
-
-.nolist
- .include "m32HVBrevBdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Battery Protection Interrupt
-.org 4
- rcall isr ; Voltage regulator monitor interrupt
-.org 6
- rcall isr ; External Interrupt Request 0
-.org 8
- rcall isr ; External Interrupt Request 1
-.org 10
- rcall isr ; External Interrupt Request 2
-.org 12
- rcall isr ; External Interrupt Request 3
-.org 14
- rcall isr ; Pin Change Interrupt 0
-.org 16
- rcall isr ; Pin Change Interrupt 1
-.org 18
- rcall isr ; Watchdog Timeout Interrupt
-.org 20
- rcall isr ; Bandgap Buffer Short Circuit Detected
-.org 22
- rcall isr ; Charger Detect
-.org 24
- rcall isr ; Timer 1 Input capture
-.org 26
- rcall isr ; Timer 1 Compare Match A
-.org 28
- rcall isr ; Timer 1 Compare Match B
-.org 30
- rcall isr ; Timer 1 overflow
-.org 32
- rcall isr ; Timer 0 Input Capture
-.org 34
- rcall isr ; Timer 0 Comapre Match A
-.org 36
- rcall isr ; Timer 0 Compare Match B
-.org 38
- rcall isr ; Timer 0 Overflow
-.org 40
- rcall isr ; Two-Wire Bus Connect/Disconnect
-.org 42
- rcall isr ; Two-Wire Serial Interface
-.org 44
- rcall isr ; SPI Serial transfer complete
-.org 46
- rcall isr ; Voltage ADC Conversion Complete
-.org 48
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org 50
- rcall isr ; Coloumb Counter ADC Regular Current
-.org 52
- rcall isr ; Coloumb Counter ADC Accumulator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; SPM Ready
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 15
- .db "ATmega32HVBrevB",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.inc b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.inc
deleted file mode 100644
index ce47e87..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-; Partname: ATmega32HVBrevB
-; generated automatically, no not edit
-
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.py b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.py
deleted file mode 100644
index f50682a..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.py
+++ /dev/null
@@ -1,342 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32HVBrevB
-
-MCUREGS = {
-# Interrupt Vectors
- 'BPINTAddr' : '#2', # Battery Protection Interrupt
- 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
- 'INT0Addr' : '#6', # External Interrupt Request 0
- 'INT1Addr' : '#8', # External Interrupt Request 1
- 'INT2Addr' : '#10', # External Interrupt Request 2
- 'INT3Addr' : '#12', # External Interrupt Request 3
- 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
- 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
- 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
- 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
- 'CHDETAddr' : '#22', # Charger Detect
- 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
- 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
- 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
- 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
- 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
- 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
- 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
- 'TWIAddr' : '#42', # Two-Wire Serial Interface
- 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
- 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
- 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
- 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
- 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPMAddr' : '#56', # SPM Ready
-
-# Module AD_CONVERTER
- 'VADMUX' : '$7c', # The VADC multiplexer Selection
- 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
- 'VADC' : '$78', # VADC Data Register Bytes
- 'VADCSR' : '$7a', # The VADC Control and Status re
- 'VADCSR_VADEN': '$8', # VADC Enable
- 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
- 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
- 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module FET
- 'FCSR' : '$f0', # FET Control and Status Registe
- 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
- 'FCSR_CPS': '$4', # Current Protection Status
- 'FCSR_DFE': '$2', # Discharge FET Enable
- 'FCSR_CFE': '$1', # Charge FET Enable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module COULOMB_COUNTER
- 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
- 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
- 'CADCSRA_CADPOL': '$40', #
- 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
- 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
- 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
- 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
- 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
- 'CADCSRB_CADACIE': '$40', #
- 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
- 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
- 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
- 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
- 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
- 'CADIC' : '$e4', # CC-ADC Instantaneous Current
- 'CADAC3' : '$e3', # ADC Accumulate Current
- 'CADAC2' : '$e2', # ADC Accumulate Current
- 'CADAC1' : '$e1', # ADC Accumulate Current
- 'CADAC0' : '$e0', # ADC Accumulate Current
- 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
- 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
-
-# Module TWI
- 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
- 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
- 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
- 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
-
-# Module TIMER_COUNTER_1
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_CS': '$7', # Clock Select1 bis
- 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
- 'TCCR1A_TCW1': '$80', # Timer/Counter Width
- 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
- 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
- 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
- 'TCCR1A_ICS1': '$8', # Input Capture Select
- 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
- 'TCNT1' : '$84', # Timer Counter 1 Bytes
- 'OCR1A' : '$88', # Output Compare Register 1A
- 'OCR1B' : '$89', # Output Compare Register B
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module CELL_BALANCING
- 'CBCR' : '$f1', # Cell Balancing Control Registe
- 'CBCR_CBE': '$f', # Cell Balancing Enables
-
-# Module BATTERY_PROTECTION
- 'BPPLR' : '$fe', # Battery Protection Parameter L
- 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
- 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
- 'BPCR' : '$fd', # Battery Protection Control Reg
- 'BPCR_EPID': '$20', # External Protection Input Disa
- 'BPCR_SCD': '$10', # Short Circuit Protection Disab
- 'BPCR_DOCD': '$8', # Discharge Over-current Protect
- 'BPCR_COCD': '$4', # Charge Over-current Protection
- 'BPCR_DHCD': '$2', # Discharge High-current Protect
- 'BPCR_CHCD': '$1', # Charge High-current Protection
- 'BPHCTR' : '$fc', # Battery Protection Short-curre
- 'BPOCTR' : '$fb', # Battery Protection Over-curren
- 'BPSCTR' : '$fa', # Battery Protection Short-curre
- 'BPCHCD' : '$f9', # Battery Protection Charge-High
- 'BPDHCD' : '$f8', # Battery Protection Discharge-H
- 'BPCOCD' : '$f7', # Battery Protection Charge-Over
- 'BPDOCD' : '$f6', # Battery Protection Discharge-O
- 'BPSCD' : '$f5', # Battery Protection Short-Circu
- 'BPIFR' : '$f3', # Battery Protection Interrupt F
- 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
- 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
- 'BPIFR_COCIF': '$4', # Charge Over-current Protection
- 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
- 'BPIFR_CHCIF': '$1', # Charge High-current Protection
- 'BPIMSK' : '$f2', # Battery Protection Interrupt M
- 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
- 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
- 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
- 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
- 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
-
-# Module CHARGER_DETECT
- 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
- 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
- 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
- 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
- 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
-
-# Module VOLTAGE_REGULATOR
- 'ROCR' : '$c8', # Regulator Operating Condition
- 'ROCR_ROCS': '$80', # ROC Status
- 'ROCR_ROCD': '$10', # ROC Disable
- 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
- 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
-
-# Module BANDGAP
- 'BGCSR' : '$d2', # Bandgap Control and Status Reg
- 'BGCSR_BGD': '$20', # Bandgap Disable
- 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
- 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
- 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
- 'BGCCR' : '$d0', # Bandgap Calibration Register
- 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_CKOE': '$20', # Clock Output Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_OCDRF': '$10', # OCD Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
- 'OSICSR' : '$37', # Oscillator Sampling Interface
- 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
- 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
- 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_PA1DID': '$2', # When this bit is written logic
- 'DIDR0_PA0DID': '$1', # When this bit is written logic
- 'PRR0' : '$64', # Power Reduction Register 0
- 'PRR0_PRTWI': '$40', # Power Reduction TWI
- 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
- 'PRR0_PRSPI': '$8', # Power reduction SPI
- 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
- 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
- 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
- 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
- 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
- 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
- 'TCCR0A_TCW0': '$80', # Timer/Counter Width
- 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
- 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
- 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
- 'TCCR0A_ICS0': '$8', # Input Capture Select
- 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
- 'TCNT0' : '$46', # Timer Counter 0 Bytes
- 'OCR0A' : '$48', # Output Compare Register 0A
- 'OCR0B' : '$49', # Output Compare Register B
- 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
- 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
- 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
- 'SPMCSR_LBSET': '$8', # Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32m1/atmega32m1.frt b/amforth-6.5/avr8/devices/atmega32m1/atmega32m1.frt
deleted file mode 100644
index b6c0e2e..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/atmega32m1.frt
+++ /dev/null
@@ -1,513 +0,0 @@
-\ Partname: ATmega32M1
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVFG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register Flags
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
- $08 constant CANGIT_SERG \ Stuff Error General Flag
- $04 constant CANGIT_CERG \ CRC Error General Flag
- $02 constant CANGIT_FERG \ Form Error General Flag
- $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register 2
- $3F constant CANEN2_ENMOB \ Enable MObs
-&221 constant CANEN1 \ Enable MOb Register 1(empty)
-&222 constant CANIE2 \ Enable Interrupt MOb Register 2
- $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
-&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
- $3F constant CANSIT2_SIT \ Status of Interrupt MObs
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
-&226 constant CANBT1 \ CAN Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ CAN Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
- $0E constant CANBT2_PRS \ Propagation Time Segment bits
-&228 constant CANBT3 \ CAN Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
- $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
- $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
- $0F constant CANHPMOB_CGP \ CAN General Purpose bits
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
- $07 constant CANPAGE_INDX \ Data Buffer Index bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
- $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
- $20 constant CANSTMOB_RXOK \ Receive OK on MOb
- $10 constant CANSTMOB_BERR \ Bit Error on MOb
- $08 constant CANSTMOB_SERR \ Stuff Error on MOb
- $04 constant CANSTMOB_CERR \ CRC Error on MOb
- $02 constant CANSTMOB_FERR \ Form Error on MOb
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
- $F8 constant CANIDT4_IDT \
- $04 constant CANIDT4_RTRTAG \
- $02 constant CANIDT4_RB1TAG \
- $01 constant CANIDT4_RB0TAG \
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-\ ANALOG_COMPARATOR
-&148 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
- $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&149 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&150 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&151 constant AC3CON \ Analog Comparator 3 Control Register
- $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
- $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&146 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&145 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&144 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $40 constant PRR_PRCAN \ Power Reduction CAN
- $20 constant PRR_PRPSC \ Power Reduction PSC
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRLIN \ Power Reduction LIN UART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ISRCEN \ Current Source Enable
- $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
- $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
- $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
- $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
- $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
- $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
- $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
- $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
-&117 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
- $07 constant AMP0CSR_AMP0TS \
-&118 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
- $07 constant AMP1CSR_AMP1TS \
-&119 constant AMP2CSR \
- $80 constant AMP2CSR_AMP2EN \
- $40 constant AMP2CSR_AMP2IS \
- $30 constant AMP2CSR_AMP2G \
- $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
- $07 constant AMP2CSR_AMP2TS \
-\ LINUART
-&200 constant LINCR \ LIN Control Register
- $80 constant LINCR_LSWRES \ Software Reset
- $40 constant LINCR_LIN13 \ LIN Standard
- $30 constant LINCR_LCONF \ LIN Configuration bits
- $08 constant LINCR_LENA \ LIN or UART Enable
- $07 constant LINCR_LCMD \ LIN Command and Mode bits
-&201 constant LINSIR \ LIN Status and Interrupt Register
- $E0 constant LINSIR_LIDST \ Identifier Status bits
- $10 constant LINSIR_LBUSY \ Busy Signal
- $08 constant LINSIR_LERR \ Error Interrupt
- $04 constant LINSIR_LIDOK \ Identifier Interrupt
- $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
- $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
-&202 constant LINENIR \ LIN Enable Interrupt Register
- $08 constant LINENIR_LENERR \ Enable Error Interrupt
- $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
- $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
- $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
-&203 constant LINERR \ LIN Error Register
- $80 constant LINERR_LABORT \ Abort Flag
- $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
- $20 constant LINERR_LOVERR \ Overrun Error Flag
- $10 constant LINERR_LFERR \ Framing Error Flag
- $08 constant LINERR_LSERR \ Synchronization Error Flag
- $04 constant LINERR_LPERR \ Parity Error Flag
- $02 constant LINERR_LCERR \ Checksum Error Flag
- $01 constant LINERR_LBERR \ Bit Error Flag
-&204 constant LINBTR \ LIN Bit Timing Register
- $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
- $3F constant LINBTR_LBT \ LIN Bit Timing bits
-&205 constant LINBRRL \ LIN Baud Rate Low Register
- $FF constant LINBRRL_LDIV \
-&206 constant LINBRRH \ LIN Baud Rate High Register
- $0F constant LINBRRH_LDIV \
-&207 constant LINDLR \ LIN Data Length Register
- $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
- $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
-&208 constant LINIDR \ LIN Identifier Register
- $C0 constant LINIDR_LP \ Parity bits
- $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
-&209 constant LINSEL \ LIN Data Buffer Selection Register
- $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
- $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
-&210 constant LINDAT \ LIN Data Register
- $FF constant LINDAT_LDATA \
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK3 \ Pin Change Mask Register 3
- $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&106 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \
- $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC
-&188 constant PIFR \ PSC Interrupt Flag Register
- $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
- $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
-&187 constant PIM \ PSC Interrupt Mask Register
- $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
- $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
-&186 constant PMIC2 \ PSC Module 2 Input Control Register
- $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
- $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
- $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
- $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
- $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
- $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
-&185 constant PMIC1 \ PSC Module 1 Input Control Register
- $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
- $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
- $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
- $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
- $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
- $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
-&184 constant PMIC0 \ PSC Module 0 Input Control Register
- $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
- $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
- $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
- $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
- $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
- $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
-&183 constant PCTL \ PSC Control Register
- $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
- $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
- $02 constant PCTL_PCCYC \ PSC Complete Cycle
- $01 constant PCTL_PRUN \ PSC Run
-&182 constant POC \ PSC Output Configuration
- $20 constant POC_POEN2B \ PSC Output 2B Enable
- $10 constant POC_POEN2A \ PSC Output 2A Enable
- $08 constant POC_POEN1B \ PSC Output 1B Enable
- $04 constant POC_POEN1A \ PSC Output 1A Enable
- $02 constant POC_POEN0B \ PSC Output 0B Enable
- $01 constant POC_POEN0A \ PSC Output 0A Enable
-&181 constant PCNF \ PSC Configuration Register
- $20 constant PCNF_PULOCK \ PSC Update Lock
- $10 constant PCNF_PMODE \ PSC Mode
- $08 constant PCNF_POPB \ PSC Output B Polarity
- $04 constant PCNF_POPA \ PSC Output A Polarity
-&180 constant PSYNC \ PSC Synchro Configuration
- $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
- $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
- $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
-&178 constant POCR_RB \ PSC Output Compare RB Register
-&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
-&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
-&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
-&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
-&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
-&166 constant POCR1SA \ PSC Output Compare SA Register
-&164 constant POCR0SB \ PSC Output Compare SB Register
-&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
-&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
-
-\ Interrupts
-&2 constant ANACOMP0Addr \ Analog Comparator 0
-&4 constant ANACOMP1Addr \ Analog Comparator 1
-&6 constant ANACOMP2Addr \ Analog Comparator 2
-&8 constant ANACOMP3Addr \ Analog Comparator 3
-&10 constant PSC_FAULTAddr \ PSC Fault
-&12 constant PSC_ECAddr \ PSC End of Cycle
-&14 constant INT0Addr \ External Interrupt Request 0
-&16 constant INT1Addr \ External Interrupt Request 1
-&18 constant INT2Addr \ External Interrupt Request 2
-&20 constant INT3Addr \ External Interrupt Request 3
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
-&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
-&38 constant CAN_TOVFAddr \ CAN Timer Overflow
-&40 constant LIN_TCAddr \ LIN Transfer Complete
-&42 constant LIN_ERRAddr \ LIN Error
-&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&54 constant ADCAddr \ ADC Conversion Complete
-&56 constant WDTAddr \ Watchdog Time-Out Interrupt
-&58 constant EE_READYAddr \ EEPROM Ready
-&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32m1/device.asm b/amforth-6.5/avr8/devices/atmega32m1/device.asm
deleted file mode 100644
index cd6365a..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega32M1
-; generated automatically, do not edit
-
-.nolist
- .include "m32M1def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CAN = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_LINUART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Analog Comparator 0
-.org 4
- rcall isr ; Analog Comparator 1
-.org 6
- rcall isr ; Analog Comparator 2
-.org 8
- rcall isr ; Analog Comparator 3
-.org 10
- rcall isr ; PSC Fault
-.org 12
- rcall isr ; PSC End of Cycle
-.org 14
- rcall isr ; External Interrupt Request 0
-.org 16
- rcall isr ; External Interrupt Request 1
-.org 18
- rcall isr ; External Interrupt Request 2
-.org 20
- rcall isr ; External Interrupt Request 3
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter1 Compare Match B
-.org 28
- rcall isr ; Timer1/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match A
-.org 32
- rcall isr ; Timer/Counter0 Compare Match B
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN MOB, Burst, General Errors
-.org 38
- rcall isr ; CAN Timer Overflow
-.org 40
- rcall isr ; LIN Transfer Complete
-.org 42
- rcall isr ; LIN Error
-.org 44
- rcall isr ; Pin Change Interrupt Request 0
-.org 46
- rcall isr ; Pin Change Interrupt Request 1
-.org 48
- rcall isr ; Pin Change Interrupt Request 2
-.org 50
- rcall isr ; Pin Change Interrupt Request 3
-.org 52
- rcall isr ; SPI Serial Transfer Complete
-.org 54
- rcall isr ; ADC Conversion Complete
-.org 56
- rcall isr ; Watchdog Time-Out Interrupt
-.org 58
- rcall isr ; EEPROM Ready
-.org 60
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega32M1"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32m1/device.inc b/amforth-6.5/avr8/devices/atmega32m1/device.inc
deleted file mode 100644
index a2d9764..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/device.inc
+++ /dev/null
@@ -1,1734 +0,0 @@
-; Partname: ATmega32M1
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register Flags
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 2
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 1(empty)
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 2
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 1 (empty)
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 2
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 1 (empty)
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 3 Control Register
-VE_AC3CON:
- .dw $ff06
- .db "AC3CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3CON
-XT_AC3CON:
- .dw PFA_DOVARIABLE
-PFA_AC3CON:
- .dw 151
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 144
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP2CSR:
- .dw $ff07
- .db "AMP2CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP2CSR
-XT_AMP2CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP2CSR:
- .dw 119
-
-.endif
-.if WANT_LINUART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Control Register
-VE_LINCR:
- .dw $ff05
- .db "LINCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINCR
-XT_LINCR:
- .dw PFA_DOVARIABLE
-PFA_LINCR:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Status and Interrupt Register
-VE_LINSIR:
- .dw $ff06
- .db "LINSIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSIR
-XT_LINSIR:
- .dw PFA_DOVARIABLE
-PFA_LINSIR:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Enable Interrupt Register
-VE_LINENIR:
- .dw $ff07
- .db "LINENIR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINENIR
-XT_LINENIR:
- .dw PFA_DOVARIABLE
-PFA_LINENIR:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Error Register
-VE_LINERR:
- .dw $ff06
- .db "LINERR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINERR
-XT_LINERR:
- .dw PFA_DOVARIABLE
-PFA_LINERR:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Bit Timing Register
-VE_LINBTR:
- .dw $ff06
- .db "LINBTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBTR
-XT_LINBTR:
- .dw PFA_DOVARIABLE
-PFA_LINBTR:
- .dw 204
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate Low Register
-VE_LINBRRL:
- .dw $ff07
- .db "LINBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRL
-XT_LINBRRL:
- .dw PFA_DOVARIABLE
-PFA_LINBRRL:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate High Register
-VE_LINBRRH:
- .dw $ff07
- .db "LINBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRH
-XT_LINBRRH:
- .dw PFA_DOVARIABLE
-PFA_LINBRRH:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Length Register
-VE_LINDLR:
- .dw $ff06
- .db "LINDLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDLR
-XT_LINDLR:
- .dw PFA_DOVARIABLE
-PFA_LINDLR:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Identifier Register
-VE_LINIDR:
- .dw $ff06
- .db "LINIDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINIDR
-XT_LINIDR:
- .dw PFA_DOVARIABLE
-PFA_LINIDR:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Buffer Selection Register
-VE_LINSEL:
- .dw $ff06
- .db "LINSEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSEL
-XT_LINSEL:
- .dw PFA_DOVARIABLE
-PFA_LINSEL:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Register
-VE_LINDAT:
- .dw $ff06
- .db "LINDAT"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDAT
-XT_LINDAT:
- .dw PFA_DOVARIABLE
-PFA_LINDAT:
- .dw 210
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Interrupt Flag Register
-VE_PIFR:
- .dw $ff04
- .db "PIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR
-XT_PIFR:
- .dw PFA_DOVARIABLE
-PFA_PIFR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Interrupt Mask Register
-VE_PIM:
- .dw $ff03
- .db "PIM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM
-XT_PIM:
- .dw PFA_DOVARIABLE
-PFA_PIM:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Input Control Register
-VE_PMIC2:
- .dw $ff05
- .db "PMIC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC2
-XT_PMIC2:
- .dw PFA_DOVARIABLE
-PFA_PMIC2:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Input Control Register
-VE_PMIC1:
- .dw $ff05
- .db "PMIC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC1
-XT_PMIC1:
- .dw PFA_DOVARIABLE
-PFA_PMIC1:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Input Control Register
-VE_PMIC0:
- .dw $ff05
- .db "PMIC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC0
-XT_PMIC0:
- .dw PFA_DOVARIABLE
-PFA_PMIC0:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Control Register
-VE_PCTL:
- .dw $ff04
- .db "PCTL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL
-XT_PCTL:
- .dw PFA_DOVARIABLE
-PFA_PCTL:
- .dw 183
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Configuration
-VE_POC:
- .dw $ff03
- .db "POC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POC
-XT_POC:
- .dw PFA_DOVARIABLE
-PFA_POC:
- .dw 182
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Configuration Register
-VE_PCNF:
- .dw $ff04
- .db "PCNF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF
-XT_PCNF:
- .dw PFA_DOVARIABLE
-PFA_PCNF:
- .dw 181
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Synchro Configuration
-VE_PSYNC:
- .dw $ff05
- .db "PSYNC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSYNC
-XT_PSYNC:
- .dw PFA_DOVARIABLE
-PFA_PSYNC:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare RB Register
-VE_POCR_RB:
- .dw $ff07
- .db "POCR_RB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR_RB
-XT_POCR_RB:
- .dw PFA_DOVARIABLE
-PFA_POCR_RB:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare SB Register
-VE_POCR2SB:
- .dw $ff07
- .db "POCR2SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2SB
-XT_POCR2SB:
- .dw PFA_DOVARIABLE
-PFA_POCR2SB:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare RA Register
-VE_POCR2RA:
- .dw $ff07
- .db "POCR2RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2RA
-XT_POCR2RA:
- .dw PFA_DOVARIABLE
-PFA_POCR2RA:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare SA Register
-VE_POCR2SA:
- .dw $ff07
- .db "POCR2SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2SA
-XT_POCR2SA:
- .dw PFA_DOVARIABLE
-PFA_POCR2SA:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Output Compare SB Register
-VE_POCR1SB:
- .dw $ff07
- .db "POCR1SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1SB
-XT_POCR1SB:
- .dw PFA_DOVARIABLE
-PFA_POCR1SB:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Output Compare RA Register
-VE_POCR1RA:
- .dw $ff07
- .db "POCR1RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1RA
-XT_POCR1RA:
- .dw PFA_DOVARIABLE
-PFA_POCR1RA:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare SA Register
-VE_POCR1SA:
- .dw $ff07
- .db "POCR1SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1SA
-XT_POCR1SA:
- .dw PFA_DOVARIABLE
-PFA_POCR1SA:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare SB Register
-VE_POCR0SB:
- .dw $ff07
- .db "POCR0SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0SB
-XT_POCR0SB:
- .dw PFA_DOVARIABLE
-PFA_POCR0SB:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Output Compare RA Register
-VE_POCR0RA:
- .dw $ff07
- .db "POCR0RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0RA
-XT_POCR0RA:
- .dw PFA_DOVARIABLE
-PFA_POCR0RA:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Output Compare SA Register
-VE_POCR0SA:
- .dw $ff07
- .db "POCR0SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0SA
-XT_POCR0SA:
- .dw PFA_DOVARIABLE
-PFA_POCR0SA:
- .dw 160
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32m1/device.py b/amforth-6.5/avr8/devices/atmega32m1/device.py
deleted file mode 100644
index dcee998..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/device.py
+++ /dev/null
@@ -1,537 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32M1
-
-MCUREGS = {
-# Interrupt Vectors
- 'ANACOMP0Addr' : '#2', # Analog Comparator 0
- 'ANACOMP1Addr' : '#4', # Analog Comparator 1
- 'ANACOMP2Addr' : '#6', # Analog Comparator 2
- 'ANACOMP3Addr' : '#8', # Analog Comparator 3
- 'PSC_FAULTAddr' : '#10', # PSC Fault
- 'PSC_ECAddr' : '#12', # PSC End of Cycle
- 'INT0Addr' : '#14', # External Interrupt Request 0
- 'INT1Addr' : '#16', # External Interrupt Request 1
- 'INT2Addr' : '#18', # External Interrupt Request 2
- 'INT3Addr' : '#20', # External Interrupt Request 3
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
- 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
- 'LIN_TCAddr' : '#40', # LIN Transfer Complete
- 'LIN_ERRAddr' : '#42', # LIN Error
- 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
- 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
- 'ADCAddr' : '#54', # ADC Conversion Complete
- 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
- 'EE_READYAddr' : '#58', # EEPROM Ready
- 'SPM_READYAddr' : '#60', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVFG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
- 'CANGIT_SERG': '$8', # Stuff Error General Flag
- 'CANGIT_CERG': '$4', # CRC Error General Flag
- 'CANGIT_FERG': '$2', # Form Error General Flag
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register 2
- 'CANEN2_ENMOB': '$3f', # Enable MObs
- 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # CAN Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # CAN Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
- 'CANBT2_PRS': '$e', # Propagation Time Segment bits
- 'CANBT3' : '$e4', # CAN Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
- 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
- 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
- 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
- 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
- 'CANSTMOB_BERR': '$10', # Bit Error on MOb
- 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
- 'CANSTMOB_CERR': '$4', # CRC Error on MOb
- 'CANSTMOB_FERR': '$2', # Form Error on MOb
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT4_IDT': '$f8', #
- 'CANIDT4_RTRTAG': '$4', #
- 'CANIDT4_RB1TAG': '$2', #
- 'CANIDT4_RB0TAG': '$1', #
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$94', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$95', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$96', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'AC3CON' : '$97', # Analog Comparator 3 Control Re
- 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
- 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$92', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$91', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$90', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRCAN': '$40', # Power Reduction CAN
- 'PRR_PRPSC': '$20', # Power Reduction PSC
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRLIN': '$2', # Power Reduction LIN UART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ISRCEN': '$40', # Current Source Enable
- 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
- 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
- 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
- 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
- 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
- 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
- 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
- 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
- 'AMP0CSR' : '$75', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
- 'AMP0CSR_AMP0TS': '$7', #
- 'AMP1CSR' : '$76', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
- 'AMP1CSR_AMP1TS': '$7', #
- 'AMP2CSR' : '$77', #
- 'AMP2CSR_AMP2EN': '$80', #
- 'AMP2CSR_AMP2IS': '$40', #
- 'AMP2CSR_AMP2G': '$30', #
- 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
- 'AMP2CSR_AMP2TS': '$7', #
-
-# Module LINUART
- 'LINCR' : '$c8', # LIN Control Register
- 'LINCR_LSWRES': '$80', # Software Reset
- 'LINCR_LIN13': '$40', # LIN Standard
- 'LINCR_LCONF': '$30', # LIN Configuration bits
- 'LINCR_LENA': '$8', # LIN or UART Enable
- 'LINCR_LCMD': '$7', # LIN Command and Mode bits
- 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
- 'LINSIR_LIDST': '$e0', # Identifier Status bits
- 'LINSIR_LBUSY': '$10', # Busy Signal
- 'LINSIR_LERR': '$8', # Error Interrupt
- 'LINSIR_LIDOK': '$4', # Identifier Interrupt
- 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
- 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
- 'LINENIR' : '$ca', # LIN Enable Interrupt Register
- 'LINENIR_LENERR': '$8', # Enable Error Interrupt
- 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
- 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
- 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
- 'LINERR' : '$cb', # LIN Error Register
- 'LINERR_LABORT': '$80', # Abort Flag
- 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
- 'LINERR_LOVERR': '$20', # Overrun Error Flag
- 'LINERR_LFERR': '$10', # Framing Error Flag
- 'LINERR_LSERR': '$8', # Synchronization Error Flag
- 'LINERR_LPERR': '$4', # Parity Error Flag
- 'LINERR_LCERR': '$2', # Checksum Error Flag
- 'LINERR_LBERR': '$1', # Bit Error Flag
- 'LINBTR' : '$cc', # LIN Bit Timing Register
- 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
- 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
- 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
- 'LINBRRL_LDIV': '$ff', #
- 'LINBRRH' : '$ce', # LIN Baud Rate High Register
- 'LINBRRH_LDIV': '$f', #
- 'LINDLR' : '$cf', # LIN Data Length Register
- 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
- 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
- 'LINIDR' : '$d0', # LIN Identifier Register
- 'LINIDR_LP': '$c0', # Parity bits
- 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
- 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
- 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
- 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
- 'LINDAT' : '$d2', # LIN Data Register
- 'LINDAT_LDATA': '$ff', #
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
- 'PCMSK3' : '$6d', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
- 'PCMSK2' : '$6c', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6b', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6a', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PSC
- 'PIFR' : '$bc', # PSC Interrupt Flag Register
- 'PIFR_PEV': '$e', # PSC External Event 2 Interrupt
- 'PIFR_PEOP': '$1', # PSC End of Cycle Interrupt
- 'PIM' : '$bb', # PSC Interrupt Mask Register
- 'PIM_PEVE': '$e', # External Event 2 Interrupt Ena
- 'PIM_PEOPE': '$1', # PSC End of Cycle Interrupt Ena
- 'PMIC2' : '$ba', # PSC Module 2 Input Control Reg
- 'PMIC2_POVEN2': '$80', # PSC Module 2 Overlap Enable
- 'PMIC2_PISEL2': '$40', # PSC Module 2 Input Select
- 'PMIC2_PELEV2': '$20', # PSC Module 2 Input Level Selec
- 'PMIC2_PFLTE2': '$10', # PSC Module 2 Input Filter Enab
- 'PMIC2_PAOC2': '$8', # PSC Module 2 Asynchronous Outp
- 'PMIC2_PRFM2': '$7', # PSC Module 2 Input Mode bits
- 'PMIC1' : '$b9', # PSC Module 1 Input Control Reg
- 'PMIC1_POVEN1': '$80', # PSC Module 1 Overlap Enable
- 'PMIC1_PISEL1': '$40', # PSC Module 1 Input Select
- 'PMIC1_PELEV1': '$20', # PSC Module 1 Input Level Selec
- 'PMIC1_PFLTE1': '$10', # PSC Module 1 Input Filter Enab
- 'PMIC1_PAOC1': '$8', # PSC Module 1 Asynchronous Outp
- 'PMIC1_PRFM1': '$7', # PSC Module 1 Input Mode bits
- 'PMIC0' : '$b8', # PSC Module 0 Input Control Reg
- 'PMIC0_POVEN0': '$80', # PSC Module 0 Overlap Enable
- 'PMIC0_PISEL0': '$40', # PSC Module 0 Input Select
- 'PMIC0_PELEV0': '$20', # PSC Module 0 Input Level Selec
- 'PMIC0_PFLTE0': '$10', # PSC Module 0 Input Filter Enab
- 'PMIC0_PAOC0': '$8', # PSC Module 0 Asynchronous Outp
- 'PMIC0_PRFM0': '$7', # PSC Module 0 Input Mode bits
- 'PCTL' : '$b7', # PSC Control Register
- 'PCTL_PPRE': '$c0', # PSC Prescaler Select bits
- 'PCTL_PCLKSEL': '$20', # PSC Input Clock Select
- 'PCTL_PCCYC': '$2', # PSC Complete Cycle
- 'PCTL_PRUN': '$1', # PSC Run
- 'POC' : '$b6', # PSC Output Configuration
- 'POC_POEN2B': '$20', # PSC Output 2B Enable
- 'POC_POEN2A': '$10', # PSC Output 2A Enable
- 'POC_POEN1B': '$8', # PSC Output 1B Enable
- 'POC_POEN1A': '$4', # PSC Output 1A Enable
- 'POC_POEN0B': '$2', # PSC Output 0B Enable
- 'POC_POEN0A': '$1', # PSC Output 0A Enable
- 'PCNF' : '$b5', # PSC Configuration Register
- 'PCNF_PULOCK': '$20', # PSC Update Lock
- 'PCNF_PMODE': '$10', # PSC Mode
- 'PCNF_POPB': '$8', # PSC Output B Polarity
- 'PCNF_POPA': '$4', # PSC Output A Polarity
- 'PSYNC' : '$b4', # PSC Synchro Configuration
- 'PSYNC_PSYNC2': '$30', # Selection of Synchronization O
- 'PSYNC_PSYNC1': '$c', # Selection of Synchronization O
- 'PSYNC_PSYNC0': '$3', # Selection of Synchronization O
- 'POCR_RB' : '$b2', # PSC Output Compare RB Register
- 'POCR2SB' : '$b0', # PSC Module 2 Output Compare SB
- 'POCR2RA' : '$ae', # PSC Module 2 Output Compare RA
- 'POCR2SA' : '$ac', # PSC Module 2 Output Compare SA
- 'POCR1SB' : '$aa', # PSC Module 1 Output Compare SB
- 'POCR1RA' : '$a8', # PSC Module 1 Output Compare RA
- 'POCR1SA' : '$a6', # PSC Output Compare SA Register
- 'POCR0SB' : '$a4', # PSC Output Compare SB Register
- 'POCR0RA' : '$a2', # PSC Module 0 Output Compare RA
- 'POCR0SA' : '$a0', # PSC Module 0 Output Compare SA
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32m1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32m1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32m1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega32m1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u2/atmega32u2.frt b/amforth-6.5/avr8/devices/atmega32u2/atmega32u2.frt
deleted file mode 100644
index 05038dd..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/atmega32u2.frt
+++ /dev/null
@@ -1,367 +0,0 @@
-\ Partname: ATmega32U2
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_DEVICE
-&244 constant UEINT \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $1F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
-&99 constant REGCR \ Regulator Control Register
- $01 constant REGCR_REGDIS \
-\ PS2
-&251 constant UPOE \
- $C0 constant UPOE_UPWE \
- $30 constant UPOE_UPDRV \
- $08 constant UPOE_SCKI \
- $04 constant UPOE_DATAI \
- $02 constant UPOE_DPI \
- $01 constant UPOE_DMI \
-&250 constant PS2CON \ PS2 Pad Enable register
- $01 constant PS2CON_PS2EN \ Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $20 constant MCUSR_USBRF \ USB reset flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
-&210 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&209 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&208 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-&81 constant DWDR \ debugWire communication register
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $1F constant PCMSK1_PCINT \
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&203 constant UCSR1D \ USART Control and Status Register D
- $02 constant UCSR1D_CTSEN \ CTS Enable
- $01 constant UCSR1D_RTSEN \ RTS Enable
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-&98 constant WDTCKD \ Watchdog Timer Clock Divider
- $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
- $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
- $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTC
-&40 constant PORTC \ Port C Data Register
- $F0 constant PORTC_PORTC \ Port C Data Register bits
- $07 constant PORTC_PORTC \ Port C Data Register bits
-&39 constant DDRC \ Port C Data Direction Register
- $F0 constant DDRC_DDC \ Port C Data Direction Register bits
- $07 constant DDRC_DDC \ Port C Data Direction Register bits
-&38 constant PINC \ Port C Input Pins
- $F0 constant PINC_PINC \ Port C Input Pins bits
- $07 constant PINC_PINC \ Port C Input Pins bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant USB_GENAddr \ USB General Interrupt Request
-&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&26 constant WDTAddr \ Watchdog Time-out Interrupt
-&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
-&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
-&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
-&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
-&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&46 constant USART1__RXAddr \ USART1, Rx Complete
-&48 constant USART1__UDREAddr \ USART1 Data register Empty
-&50 constant USART1__TXAddr \ USART1, Tx Complete
-&52 constant ANALOG_COMPAddr \ Analog Comparator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32u2/device.asm b/amforth-6.5/avr8/devices/atmega32u2/device.asm
deleted file mode 100644
index b2164f2..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: ATmega32U2
-; generated automatically, do not edit
-
-.nolist
- .include "m32U2def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_PS2 = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTC = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; USB General Interrupt Request
-.org 24
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 26
- rcall isr ; Watchdog Time-out Interrupt
-.org 28
- rcall isr ; Timer/Counter2 Capture Event
-.org 30
- rcall isr ; Timer/Counter2 Compare Match B
-.org 32
- rcall isr ; Timer/Counter2 Compare Match B
-.org 34
- rcall isr ; Timer/Counter2 Compare Match C
-.org 36
- rcall isr ; Timer/Counter1 Overflow
-.org 38
- rcall isr ; Timer/Counter0 Compare Match A
-.org 40
- rcall isr ; Timer/Counter0 Compare Match B
-.org 42
- rcall isr ; Timer/Counter0 Overflow
-.org 44
- rcall isr ; SPI Serial Transfer Complete
-.org 46
- rcall isr ; USART1, Rx Complete
-.org 48
- rcall isr ; USART1 Data register Empty
-.org 50
- rcall isr ; USART1, Tx Complete
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 10
- .db "ATmega32U2"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32u2/device.inc b/amforth-6.5/avr8/devices/atmega32u2/device.inc
deleted file mode 100644
index a40b3a2..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/device.inc
+++ /dev/null
@@ -1,1155 +0,0 @@
-; Partname: ATmega32U2
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Control Register
-VE_REGCR:
- .dw $ff05
- .db "REGCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_REGCR
-XT_REGCR:
- .dw PFA_DOVARIABLE
-PFA_REGCR:
- .dw 99
-
-.endif
-.if WANT_PS2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UPOE:
- .dw $ff04
- .db "UPOE"
- .dw VE_HEAD
- .set VE_HEAD=VE_UPOE
-XT_UPOE:
- .dw PFA_DOVARIABLE
-PFA_UPOE:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; PS2 Pad Enable register
-VE_PS2CON:
- .dw $ff06
- .db "PS2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_PS2CON
-XT_PS2CON:
- .dw PFA_DOVARIABLE
-PFA_PS2CON:
- .dw 250
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; debugWire communication register
-VE_DWDR:
- .dw $ff04
- .db "DWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_DWDR
-XT_DWDR:
- .dw PFA_DOVARIABLE
-PFA_DWDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register D
-VE_UCSR1D:
- .dw $ff06
- .db "UCSR1D"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1D
-XT_UCSR1D:
- .dw PFA_DOVARIABLE
-PFA_UCSR1D:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Clock Divider
-VE_WDTCKD:
- .dw $ff06
- .db "WDTCKD"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCKD
-XT_WDTCKD:
- .dw PFA_DOVARIABLE
-PFA_WDTCKD:
- .dw 98
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32u2/device.py b/amforth-6.5/avr8/devices/atmega32u2/device.py
deleted file mode 100644
index 20a1998..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/device.py
+++ /dev/null
@@ -1,387 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32U2
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'USB_GENAddr' : '#22', # USB General Interrupt Request
- 'USB_COMAddr' : '#24', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#26', # Watchdog Time-out Interrupt
- 'TIMER1_CAPTAddr' : '#28', # Timer/Counter2 Capture Event
- 'TIMER1_COMPAAddr' : '#30', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPBAddr' : '#32', # Timer/Counter2 Compare Match B
- 'TIMER1_COMPCAddr' : '#34', # Timer/Counter2 Compare Match C
- 'TIMER1_OVFAddr' : '#36', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#38', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#40', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#42', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#44', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#46', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#48', # USART1 Data register Empty
- 'USART1_TXAddr' : '#50', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#52', # Analog Comparator
- 'EE_READYAddr' : '#54', # EEPROM Ready
- 'SPM_READYAddr' : '#56', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$1f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_RSTCPU': '$4', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_FRZCLK': '$20', #
- 'REGCR' : '$63', # Regulator Control Register
- 'REGCR_REGDIS': '$1', #
-
-# Module PS2
- 'UPOE' : '$fb', #
- 'UPOE_UPWE': '$c0', #
- 'UPOE_UPDRV': '$30', #
- 'UPOE_SCKI': '$8', #
- 'UPOE_DATAI': '$4', #
- 'UPOE_DPI': '$2', #
- 'UPOE_DMI': '$1', #
- 'PS2CON' : '$fa', # PS2 Pad Enable register
- 'PS2CON_PS2EN': '$1', # Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_USBRF': '$20', # USB reset flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'CLKSTA' : '$d2', #
- 'CLKSTA_RCON': '$2', #
- 'CLKSTA_EXTON': '$1', #
- 'CLKSEL1' : '$d1', #
- 'CLKSEL1_RCCKSEL': '$f0', #
- 'CLKSEL1_EXCKSEL': '$f', #
- 'CLKSEL0' : '$d0', #
- 'CLKSEL0_RCSUT': '$c0', #
- 'CLKSEL0_EXSUT': '$30', #
- 'CLKSEL0_RCE': '$8', #
- 'CLKSEL0_EXTE': '$4', #
- 'CLKSEL0_CLKS': '$1', #
- 'DWDR' : '$51', # debugWire communication regist
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$1f', #
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UCSR1D' : '$cb', # USART Control and Status Regis
- 'UCSR1D_CTSEN': '$2', # CTS Enable
- 'UCSR1D_RTSEN': '$1', # RTS Enable
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
- 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
- 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
- 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
- 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'PORTC_PORTC': '$f0', # Port C Data Register bits
- 'PORTC_PORTC': '$7', # Port C Data Register bits
- 'DDRC' : '$27', # Port C Data Direction Register
- 'DDRC_DDC': '$f0', # Port C Data Direction Register
- 'DDRC_DDC': '$7', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
- 'PINC_PINC': '$f0', # Port C Input Pins bits
- 'PINC_PINC': '$7', # Port C Input Pins bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32u2/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32u2/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32u2/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega32u2/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u4/atmega32u4.frt b/amforth-6.5/avr8/devices/atmega32u4/atmega32u4.frt
deleted file mode 100644
index 8636a4e..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/atmega32u4.frt
+++ /dev/null
@@ -1,496 +0,0 @@
-\ Partname: ATmega32U4
-\ generated automatically
-
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
-\ TIMER_COUNTER_4
-&192 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $08 constant TCCR4A_FOC4A \ Force Output Compare Match 4A
- $04 constant TCCR4A_FOC4B \ Force Output Compare Match 4B
- $02 constant TCCR4A_PWM4A \
- $01 constant TCCR4A_PWM4B \
-&193 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_PWM4X \ PWM Inversion Mode
- $40 constant TCCR4B_PSR4 \ Prescaler Reset Timer/Counter 4
- $30 constant TCCR4B_DTPS4 \ Dead Time Prescaler Bits
- $0F constant TCCR4B_CS4 \ Clock Select Bits
-&194 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_COM4A1S \ Comparator A Output Mode
- $40 constant TCCR4C_COM4A0S \ Comparator A Output Mode
- $20 constant TCCR4C_COM4B1S \ Comparator B Output Mode
- $10 constant TCCR4C_COM4B0S \ Comparator B Output Mode
- $0C constant TCCR4C_COM4D \ Comparator D Output Mode
- $02 constant TCCR4C_FOC4D \ Force Output Compare Match 4D
- $01 constant TCCR4C_PWM4D \ Pulse Width Modulator D Enable
-&195 constant TCCR4D \ Timer/Counter 4 Control Register D
- $80 constant TCCR4D_FPIE4 \ Fault Protection Interrupt Enable
- $40 constant TCCR4D_FPEN4 \ Fault Protection Mode Enable
- $20 constant TCCR4D_FPNC4 \ Fault Protection Noise Canceler
- $10 constant TCCR4D_FPES4 \ Fault Protection Edge Select
- $08 constant TCCR4D_FPAC4 \ Fault Protection Analog Comparator Enable
- $04 constant TCCR4D_FPF4 \ Fault Protection Interrupt Flag
- $03 constant TCCR4D_WGM4 \ Waveform Generation Mode bits
-&196 constant TCCR4E \ Timer/Counter 4 Control Register E
- $80 constant TCCR4E_TLOCK4 \ Register Update Lock
- $40 constant TCCR4E_ENHC4 \ Enhanced Compare/PWM Mode
- $3F constant TCCR4E_OC4OE \ Output Compare Override Enable bit
-&190 constant TCNT4 \ Timer/Counter4 Low Bytes
-&191 constant TC4H \ Timer/Counter4
-&207 constant OCR4A \ Timer/Counter4 Output Compare Register A
-&208 constant OCR4B \ Timer/Counter4 Output Compare Register B
-&209 constant OCR4C \ Timer/Counter4 Output Compare Register C
-&210 constant OCR4D \ Timer/Counter4 Output Compare Register D
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $80 constant TIMSK4_OCIE4D \ Timer/Counter4 Output Compare D Match Interrupt Enable
- $40 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $20 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $04 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $80 constant TIFR4_OCF4D \ Output Compare Flag 4D
- $40 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $20 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $04 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-&212 constant DT4 \ Timer/Counter 4 Dead Time Value
- $FF constant DT4_DT4L \ Timer/Counter 4 Dead Time Value Bits
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $20 constant ADCSRB_MUX5 \ Analog Channel and Gain Selection Bits
- $17 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 1
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&125 constant DIDR2 \ Digital Input Disable Register 1
- $20 constant DIDR2_ADC13D \ ADC13 Digital input Disable
- $10 constant DIDR2_ADC12D \ ADC12 Digital input Disable
- $08 constant DIDR2_ADC11D \ ADC11 Digital input Disable
- $04 constant DIDR2_ADC10D \ ADC10 Digital input Disable
- $02 constant DIDR2_ADC9D \ ADC9 Digital input Disable
- $01 constant DIDR2_ADC8D \ ADC8 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&103 constant RCCTRL \ Oscillator Control Register
- $01 constant RCCTRL_RCFREQ \
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-&199 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&198 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&197 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $10 constant PLLCSR_PINDIV \ PLL prescaler Bit 2
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-&82 constant PLLFRQ \ PLL Frequency Control Register
- $80 constant PLLFRQ_PINMUX \
- $40 constant PLLFRQ_PLLUSB \
- $30 constant PLLFRQ_PLLTM \
- $0F constant PLLFRQ_PDIV \
-\ USB_DEVICE
-&244 constant UEINT \
-&243 constant UEBCHX \
-&242 constant UEBCLX \
-&241 constant UEDATX \
- $FF constant UEDATX_DAT \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $7F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_LSM \ USB low speed mode
- $08 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
- $10 constant USBCON_OTGPADE \
- $01 constant USBCON_VBUSTE \
-&218 constant USBINT \
- $01 constant USBINT_VBUSTI \
-&217 constant USBSTA \
- $08 constant USBSTA_SPEED \
- $01 constant USBSTA_VBUS \
-&215 constant UHWCON \
- $01 constant UHWCON_UVREGE \
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant Reserved1Addr \ Reserved1
-&12 constant Reserved2Addr \ Reserved2
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant Reserved3Addr \ Reserved3
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant USB_GENAddr \ USB General Interrupt Request
-&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant Reserved4Addr \ Reserved4
-&28 constant Reserved5Addr \ Reserved5
-&30 constant Reserved6Addr \ Reserved6
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART1__RXAddr \ USART1, Rx Complete
-&52 constant USART1__UDREAddr \ USART1 Data register Empty
-&54 constant USART1__TXAddr \ USART1, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant TWIAddr \ 2-wire Serial Interface
-&74 constant SPM_READYAddr \ Store Program Memory Read
-&76 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&78 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&80 constant TIMER4_COMPDAddr \ Timer/Counter4 Compare Match D
-&82 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&84 constant TIMER4_FPFAddr \ Timer/Counter4 Fault Protection Interrupt
diff --git a/amforth-6.5/avr8/devices/atmega32u4/device.asm b/amforth-6.5/avr8/devices/atmega32u4/device.asm
deleted file mode 100644
index f722b8e..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/device.asm
+++ /dev/null
@@ -1,146 +0,0 @@
-; Partname: ATmega32U4
-; generated automatically, do not edit
-
-.nolist
- .include "m32U4def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_WATCHDOG = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_USART1 = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; Reserved1
-.org 12
- rcall isr ; Reserved2
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; Reserved3
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; USB General Interrupt Request
-.org 22
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Reserved4
-.org 28
- rcall isr ; Reserved5
-.org 30
- rcall isr ; Reserved6
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART1, Rx Complete
-.org 52
- rcall isr ; USART1 Data register Empty
-.org 54
- rcall isr ; USART1, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; 2-wire Serial Interface
-.org 74
- rcall isr ; Store Program Memory Read
-.org 76
- rcall isr ; Timer/Counter4 Compare Match A
-.org 78
- rcall isr ; Timer/Counter4 Compare Match B
-.org 80
- rcall isr ; Timer/Counter4 Compare Match D
-.org 82
- rcall isr ; Timer/Counter4 Overflow
-.org 84
- rcall isr ; Timer/Counter4 Fault Protection Interrupt
-.equ INTVECTORS = 43
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2560
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672
-mcu_numints:
- .dw 43
-mcu_name:
- .dw 10
- .db "ATmega32U4"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32u4/device.inc b/amforth-6.5/avr8/devices/atmega32u4/device.inc
deleted file mode 100644
index 4d0f09c..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/device.inc
+++ /dev/null
@@ -1,1602 +0,0 @@
-; Partname: ATmega32U4
-; generated automatically, no not edit
-
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register D
-VE_TCCR4D:
- .dw $ff06
- .db "TCCR4D"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4D
-XT_TCCR4D:
- .dw PFA_DOVARIABLE
-PFA_TCCR4D:
- .dw 195
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register E
-VE_TCCR4E:
- .dw $ff06
- .db "TCCR4E"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4E
-XT_TCCR4E:
- .dw PFA_DOVARIABLE
-PFA_TCCR4E:
- .dw 196
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Low Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 190
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4
-VE_TC4H:
- .dw $ff04
- .db "TC4H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TC4H
-XT_TC4H:
- .dw PFA_DOVARIABLE
-PFA_TC4H:
- .dw 191
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register C
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register D
-VE_OCR4D:
- .dw $ff05
- .db "OCR4D",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4D
-XT_OCR4D:
- .dw PFA_DOVARIABLE
-PFA_OCR4D:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Dead Time Value
-VE_DT4:
- .dw $ff03
- .db "DT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DT4
-XT_DT4:
- .dw PFA_DOVARIABLE
-PFA_DT4:
- .dw 212
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Control Register
-VE_RCCTRL:
- .dw $ff06
- .db "RCCTRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_RCCTRL
-XT_RCCTRL:
- .dw PFA_DOVARIABLE
-PFA_RCCTRL:
- .dw 103
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 199
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 197
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Frequency Control Register
-VE_PLLFRQ:
- .dw $ff06
- .db "PLLFRQ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLFRQ
-XT_PLLFRQ:
- .dw PFA_DOVARIABLE
-PFA_PLLFRQ:
- .dw 82
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw 215
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32u4/device.py b/amforth-6.5/avr8/devices/atmega32u4/device.py
deleted file mode 100644
index ef93719..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/device.py
+++ /dev/null
@@ -1,554 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega32U4
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'Reserved1Addr' : '#10', # Reserved1
- 'Reserved2Addr' : '#12', # Reserved2
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'Reserved3Addr' : '#16', # Reserved3
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'USB_GENAddr' : '#20', # USB General Interrupt Request
- 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'Reserved4Addr' : '#26', # Reserved4
- 'Reserved5Addr' : '#28', # Reserved5
- 'Reserved6Addr' : '#30', # Reserved6
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART1_RXAddr' : '#50', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
- 'USART1_TXAddr' : '#54', # USART1, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'TWIAddr' : '#72', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#74', # Store Program Memory Read
- 'TIMER4_COMPAAddr' : '#76', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#78', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPDAddr' : '#80', # Timer/Counter4 Compare Match D
- 'TIMER4_OVFAddr' : '#82', # Timer/Counter4 Overflow
- 'TIMER4_FPFAddr' : '#84', # Timer/Counter4 Fault Protection Interrupt
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$c0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_FOC4A': '$8', # Force Output Compare Match 4A
- 'TCCR4A_FOC4B': '$4', # Force Output Compare Match 4B
- 'TCCR4A_PWM4A': '$2', #
- 'TCCR4A_PWM4B': '$1', #
- 'TCCR4B' : '$c1', # Timer/Counter4 Control Registe
- 'TCCR4B_PWM4X': '$80', # PWM Inversion Mode
- 'TCCR4B_PSR4': '$40', # Prescaler Reset Timer/Counter
- 'TCCR4B_DTPS4': '$30', # Dead Time Prescaler Bits
- 'TCCR4B_CS4': '$f', # Clock Select Bits
- 'TCCR4C' : '$c2', # Timer/Counter 4 Control Regist
- 'TCCR4C_COM4A1S': '$80', # Comparator A Output Mode
- 'TCCR4C_COM4A0S': '$40', # Comparator A Output Mode
- 'TCCR4C_COM4B1S': '$20', # Comparator B Output Mode
- 'TCCR4C_COM4B0S': '$10', # Comparator B Output Mode
- 'TCCR4C_COM4D': '$c', # Comparator D Output Mode
- 'TCCR4C_FOC4D': '$2', # Force Output Compare Match 4D
- 'TCCR4C_PWM4D': '$1', # Pulse Width Modulator D Enable
- 'TCCR4D' : '$c3', # Timer/Counter 4 Control Regist
- 'TCCR4D_FPIE4': '$80', # Fault Protection Interrupt Ena
- 'TCCR4D_FPEN4': '$40', # Fault Protection Mode Enable
- 'TCCR4D_FPNC4': '$20', # Fault Protection Noise Cancele
- 'TCCR4D_FPES4': '$10', # Fault Protection Edge Select
- 'TCCR4D_FPAC4': '$8', # Fault Protection Analog Compar
- 'TCCR4D_FPF4': '$4', # Fault Protection Interrupt Fla
- 'TCCR4D_WGM4': '$3', # Waveform Generation Mode bits
- 'TCCR4E' : '$c4', # Timer/Counter 4 Control Regist
- 'TCCR4E_TLOCK4': '$80', # Register Update Lock
- 'TCCR4E_ENHC4': '$40', # Enhanced Compare/PWM Mode
- 'TCCR4E_OC4OE': '$3f', # Output Compare Override Enable
- 'TCNT4' : '$be', # Timer/Counter4 Low Bytes
- 'TC4H' : '$bf', # Timer/Counter4
- 'OCR4A' : '$cf', # Timer/Counter4 Output Compare
- 'OCR4B' : '$d0', # Timer/Counter4 Output Compare
- 'OCR4C' : '$d1', # Timer/Counter4 Output Compare
- 'OCR4D' : '$d2', # Timer/Counter4 Output Compare
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_OCIE4D': '$80', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$40', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$20', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$4', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_OCF4D': '$80', # Output Compare Flag 4D
- 'TIFR4_OCF4A': '$40', # Output Compare Flag 4A
- 'TIFR4_OCF4B': '$20', # Output Compare Flag 4B
- 'TIFR4_TOV4': '$4', # Timer/Counter4 Overflow Flag
- 'DT4' : '$d4', # Timer/Counter 4 Dead Time Valu
- 'DT4_DT4L': '$ff', # Timer/Counter 4 Dead Time Valu
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_MUX5': '$20', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$17', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC13D': '$20', # ADC13 Digital input Disable
- 'DIDR2_ADC12D': '$10', # ADC12 Digital input Disable
- 'DIDR2_ADC11D': '$8', # ADC11 Digital input Disable
- 'DIDR2_ADC10D': '$4', # ADC10 Digital input Disable
- 'DIDR2_ADC9D': '$2', # ADC9 Digital input Disable
- 'DIDR2_ADC8D': '$1', # ADC8 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', #
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'RCCTRL' : '$67', # Oscillator Control Register
- 'RCCTRL_RCFREQ': '$1', #
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRUSB': '$80', # Power Reduction USB
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART1': '$1', # Power Reduction USART1
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
- 'CLKSTA' : '$c7', #
- 'CLKSTA_RCON': '$2', #
- 'CLKSTA_EXTON': '$1', #
- 'CLKSEL1' : '$c6', #
- 'CLKSEL1_RCCKSEL': '$f0', #
- 'CLKSEL1_EXCKSEL': '$f', #
- 'CLKSEL0' : '$c5', #
- 'CLKSEL0_RCSUT': '$c0', #
- 'CLKSEL0_EXSUT': '$30', #
- 'CLKSEL0_RCE': '$8', #
- 'CLKSEL0_EXTE': '$4', #
- 'CLKSEL0_CLKS': '$1', #
-
-# Module PLL
- 'PLLCSR' : '$49', # PLL Status and Control registe
- 'PLLCSR_PINDIV': '$10', # PLL prescaler Bit 2
- 'PLLCSR_PLLE': '$2', # PLL Enable Bit
- 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
- 'PLLFRQ' : '$52', # PLL Frequency Control Register
- 'PLLFRQ_PINMUX': '$80', #
- 'PLLFRQ_PLLUSB': '$40', #
- 'PLLFRQ_PLLTM': '$30', #
- 'PLLFRQ_PDIV': '$f', #
-
-# Module USB_DEVICE
- 'UEINT' : '$f4', #
- 'UEBCHX' : '$f3', #
- 'UEBCLX' : '$f2', #
- 'UEDATX' : '$f1', #
- 'UEDATX_DAT': '$ff', #
- 'UEIENX' : '$f0', #
- 'UEIENX_FLERRE': '$80', #
- 'UEIENX_NAKINE': '$40', #
- 'UEIENX_NAKOUTE': '$10', #
- 'UEIENX_RXSTPE': '$8', #
- 'UEIENX_RXOUTE': '$4', #
- 'UEIENX_STALLEDE': '$2', #
- 'UEIENX_TXINE': '$1', #
- 'UESTA1X' : '$ef', #
- 'UESTA1X_CTRLDIR': '$4', #
- 'UESTA1X_CURRBK': '$3', #
- 'UESTA0X' : '$ee', #
- 'UESTA0X_CFGOK': '$80', #
- 'UESTA0X_OVERFI': '$40', #
- 'UESTA0X_UNDERFI': '$20', #
- 'UESTA0X_DTSEQ': '$c', #
- 'UESTA0X_NBUSYBK': '$3', #
- 'UECFG1X' : '$ed', #
- 'UECFG1X_EPSIZE': '$70', #
- 'UECFG1X_EPBK': '$c', #
- 'UECFG1X_ALLOC': '$2', #
- 'UECFG0X' : '$ec', #
- 'UECFG0X_EPTYPE': '$c0', #
- 'UECFG0X_EPDIR': '$1', #
- 'UECONX' : '$eb', #
- 'UECONX_STALLRQ': '$20', #
- 'UECONX_STALLRQC': '$10', #
- 'UECONX_RSTDT': '$8', #
- 'UECONX_EPEN': '$1', #
- 'UERST' : '$ea', #
- 'UERST_EPRST': '$7f', #
- 'UENUM' : '$e9', #
- 'UEINTX' : '$e8', #
- 'UEINTX_FIFOCON': '$80', #
- 'UEINTX_NAKINI': '$40', #
- 'UEINTX_RWAL': '$20', #
- 'UEINTX_NAKOUTI': '$10', #
- 'UEINTX_RXSTPI': '$8', #
- 'UEINTX_RXOUTI': '$4', #
- 'UEINTX_STALLEDI': '$2', #
- 'UEINTX_TXINI': '$1', #
- 'UDMFN' : '$e6', #
- 'UDMFN_FNCERR': '$10', #
- 'UDFNUM' : '$e4', #
- 'UDADDR' : '$e3', #
- 'UDADDR_ADDEN': '$80', #
- 'UDADDR_UADD': '$7f', #
- 'UDIEN' : '$e2', #
- 'UDIEN_UPRSME': '$40', #
- 'UDIEN_EORSME': '$20', #
- 'UDIEN_WAKEUPE': '$10', #
- 'UDIEN_EORSTE': '$8', #
- 'UDIEN_SOFE': '$4', #
- 'UDIEN_SUSPE': '$1', #
- 'UDINT' : '$e1', #
- 'UDINT_UPRSMI': '$40', #
- 'UDINT_EORSMI': '$20', #
- 'UDINT_WAKEUPI': '$10', #
- 'UDINT_EORSTI': '$8', #
- 'UDINT_SOFI': '$4', #
- 'UDINT_SUSPI': '$1', #
- 'UDCON' : '$e0', #
- 'UDCON_LSM': '$4', # USB low speed mode
- 'UDCON_RSTCPU': '$8', #
- 'UDCON_RMWKUP': '$2', #
- 'UDCON_DETACH': '$1', #
- 'USBCON' : '$d8', # USB General Control Register
- 'USBCON_USBE': '$80', #
- 'USBCON_FRZCLK': '$20', #
- 'USBCON_OTGPADE': '$10', #
- 'USBCON_VBUSTE': '$1', #
- 'USBINT' : '$da', #
- 'USBINT_VBUSTI': '$1', #
- 'USBSTA' : '$d9', #
- 'USBSTA_SPEED': '$8', #
- 'USBSTA_VBUS': '$1', #
- 'UHWCON' : '$d7', #
- 'UHWCON_UVREGE': '$1', #
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega32u4/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32u4/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u4/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32u4/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u4/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32u4/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega32u4/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u6/atmega32u6.frt b/amforth-6.5/avr8/devices/atmega32u6/atmega32u6.frt
deleted file mode 100644
index 2040dc3..0000000
--- a/amforth-6.5/avr8/devices/atmega32u6/atmega32u6.frt
+++ /dev/null
@@ -1,233 +0,0 @@
-\ Partname: ATmega32U6
-\ Built using part description XML file version 1
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant ADCH \ ADC Data Register High Byte
-78 constant ADCL \ ADC Data Register Low Byte
-7A constant ADCSRA \ The ADC Control and Status register
-7B constant ADCSRB \ ADC Control and Status Register B
-7C constant ADMUX \ The ADC multiplexer Selection Register
-7E constant DIDR0 \ Digital Input Disable Register 1
-
-\ ANALOG_COMPARATOR
-50 constant ACSR \ Analog Comparator Control And Status Register
-7F constant DIDR1 \
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control Register
-
-\ CPU
-61 constant CLKPR \
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-66 constant OSCCAL \ Oscillator Calibration Value
-64 constant PRR0 \ Power Reduction Register0
-65 constant PRR1 \ Power Reduction Register1
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-74 constant XMCRA \ External Memory Control Register A
-75 constant XMCRB \ External Memory Control Register B
-
-\ EEPROM
-42 constant EEARH \ EEPROM Address Register Low Byte
-41 constant EEARL \ EEPROM Address Register Low Byte
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register A
-6A constant EICRB \ External Interrupt Control Register B
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-68 constant PCICR \ Pin Change Interrupt Control Register
-3B constant PCIFR \ Pin Change Interrupt Flag Register
-6B constant PCMSK0 \ Pin Change Mask Register 0
-
-\ JTAG
-51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-
-\ PLL
-49 constant PLLCSR \ PLL Status and Control register
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Port B Data Direction Register
-23 constant PINB \ Port B Input Pins
-25 constant PORTB \ Port B Data Register
-
-\ PORTC
-27 constant DDRC \ Port C Data Direction Register
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ PORTD
-2A constant DDRD \ Port D Data Direction Register
-29 constant PIND \ Port D Input Pins
-2B constant PORTD \ Port D Data Register
-
-\ PORTE
-2D constant DDRE \ Data Direction Register, Port E
-2C constant PINE \ Input Pins, Port E
-2E constant PORTE \ Data Register, Port E
-
-\ PORTF
-30 constant DDRF \ Data Direction Register, Port F
-2F constant PINF \ Input Pins, Port F
-31 constant PORTF \ Data Register, Port F
-
-\ SPI
-4C constant SPCR \ SPI Control Register
-4E constant SPDR \ SPI Data Register
-4D constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-43 constant GTCCR \ General Timer/Counter Control Register
-47 constant OCR0A \ Timer/Counter0 Output Compare Register
-48 constant OCR0B \ Timer/Counter0 Output Compare Register
-44 constant TCCR0A \ Timer/Counter Control Register A
-45 constant TCCR0B \ Timer/Counter Control Register B
-46 constant TCNT0 \ Timer/Counter0
-35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
-88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
-8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
-8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
-8D constant OCR1CH \ Timer/Counter1 Output Compare Register C High Byte
-8C constant OCR1CL \ Timer/Counter1 Output Compare Register C Low Byte
-80 constant TCCR1A \ Timer/Counter1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-82 constant TCCR1C \ Timer/Counter 1 Control Register C
-85 constant TCNT1H \ Timer/Counter1 High Byte
-84 constant TCNT1L \ Timer/Counter1 Low Byte
-36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
-
-\ TIMER_COUNTER_2
-B6 constant ASSR \ Asynchronous Status Register
-B3 constant OCR2A \ Timer/Counter2 Output Compare Register A
-B4 constant OCR2B \ Timer/Counter2 Output Compare Register B
-B0 constant TCCR2A \ Timer/Counter2 Control Register A
-B1 constant TCCR2B \ Timer/Counter2 Control Register B
-B2 constant TCNT2 \ Timer/Counter2
-37 constant TIFR2 \ Timer/Counter Interrupt Flag Register
-70 constant TIMSK2 \ Timer/Counter Interrupt Mask register
-
-\ TIMER_COUNTER_3
-97 constant ICR3H \ Timer/Counter3 Input Capture Register High Byte
-96 constant ICR3L \ Timer/Counter3 Input Capture Register Low Byte
-99 constant OCR3AH \ Timer/Counter3 Output Compare Register A High Byte
-98 constant OCR3AL \ Timer/Counter3 Output Compare Register A Low Byte
-9B constant OCR3BH \ Timer/Counter3 Output Compare Register B High Byte
-9A constant OCR3BL \ Timer/Counter3 Output Compare Register B Low Byte
-9D constant OCR3CH \ Timer/Counter3 Output Compare Register B High Byte
-9C constant OCR3CL \ Timer/Counter3 Output Compare Register B Low Byte
-90 constant TCCR3A \ Timer/Counter3 Control Register A
-91 constant TCCR3B \ Timer/Counter3 Control Register B
-92 constant TCCR3C \ Timer/Counter 3 Control Register C
-95 constant TCNT3H \ Timer/Counter3 High Byte
-94 constant TCNT3L \ Timer/Counter3 Low Byte
-38 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
-71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
-
-\ TWI
-BD constant TWAMR \ TWI (Slave) Address Mask Register
-BA constant TWAR \ TWI (Slave) Address register
-B8 constant TWBR \ TWI Bit Rate register
-BC constant TWCR \ TWI Control Register
-BB constant TWDR \ TWI Data register
-B9 constant TWSR \ TWI Status Register
-
-\ USART1
-CD constant UBRR1H \ USART Baud Rate Register High Byte
-CC constant UBRR1L \ USART Baud Rate Register Low Byte
-C8 constant UCSR1A \ USART Control and Status Register A
-C9 constant UCSR1B \ USART Control and Status Register B
-CA constant UCSR1C \ USART Control and Status Register C
-CE constant UDR1 \ USART I/O Data Register
-
-\ USB_DEVICE
-E3 constant UDADDR \
-E0 constant UDCON \
-E5 constant UDFNUMH \
-E4 constant UDFNUML \
-E2 constant UDIEN \
-E1 constant UDINT \
-E6 constant UDMFN \
-F3 constant UEBCHX \
-F2 constant UEBCLX \
-EC constant UECFG0X \
-ED constant UECFG1X \
-EB constant UECONX \
-F1 constant UEDATX \
-F0 constant UEIENX \
-F4 constant UEINT \
-E8 constant UEINTX \
-E9 constant UENUM \
-EA constant UERST \
-EE constant UESTA0X \
-EF constant UESTA1X \
-
-\ USB_GLOBAL
-D7 constant UHWCON \ USB Hardware Configuration Register
-D8 constant USBCON \ USB General Control Register
-DA constant USBINT \
-D9 constant USBSTA \
-
-\ WATCHDOG
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt Request 0
-004 constant INT1Addr \ External Interrupt Request 1
-006 constant INT2Addr \ External Interrupt Request 2
-008 constant INT3Addr \ External Interrupt Request 3
-00A constant INT4Addr \ External Interrupt Request 4
-00C constant INT5Addr \ External Interrupt Request 5
-00E constant INT6Addr \ External Interrupt Request 6
-010 constant INT7Addr \ External Interrupt Request 7
-012 constant PCINT0Addr \ Pin Change Interrupt Request 0
-014 constant USB_GENAddr \ USB General Interrupt Request
-016 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-018 constant WDTAddr \ Watchdog Time-out Interrupt
-01A constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-01C constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-01E constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-020 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-022 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-024 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-026 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-028 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-02A constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-02C constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-02E constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-030 constant SPI_STCAddr \ SPI Serial Transfer Complete
-032 constant USART1_RXAddr \ USART1, Rx Complete
-034 constant USART1_UDREAddr \ USART1 Data register Empty
-036 constant USART1_TXAddr \ USART1, Tx Complete
-038 constant ANALOG_COMPAddr \ Analog Comparator
-03A constant ADCAddr \ ADC Conversion Complete
-03C constant EE_READYAddr \ EEPROM Ready
-03E constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-040 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-042 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-044 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-046 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-048 constant TWIAddr \ 2-wire Serial Interface
-04A constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32u6/device.asm b/amforth-6.5/avr8/devices/atmega32u6/device.asm
deleted file mode 100644
index 851ac95..0000000
--- a/amforth-6.5/avr8/devices/atmega32u6/device.asm
+++ /dev/null
@@ -1,155 +0,0 @@
-; Partname: ATmega32U6
-; Built using part description XML file version 1
-; generated automatically, do not edit
-
-.nolist
- .include "m32U6def.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_JTAG = 0
-.set WANT_PLL = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_USB_GLOBAL = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 38
-.org $002
- rcall isr ; External Interrupt Request 0
-.org $004
- rcall isr ; External Interrupt Request 1
-.org $006
- rcall isr ; External Interrupt Request 2
-.org $008
- rcall isr ; External Interrupt Request 3
-.org $00A
- rcall isr ; External Interrupt Request 4
-.org $00C
- rcall isr ; External Interrupt Request 5
-.org $00E
- rcall isr ; External Interrupt Request 6
-.org $010
- rcall isr ; External Interrupt Request 7
-.org $012
- rcall isr ; Pin Change Interrupt Request 0
-.org $014
- rcall isr ; USB General Interrupt Request
-.org $016
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org $018
- rcall isr ; Watchdog Time-out Interrupt
-.org $01A
- rcall isr ; Timer/Counter2 Compare Match A
-.org $01C
- rcall isr ; Timer/Counter2 Compare Match B
-.org $01E
- rcall isr ; Timer/Counter2 Overflow
-.org $020
- rcall isr ; Timer/Counter1 Capture Event
-.org $022
- rcall isr ; Timer/Counter1 Compare Match A
-.org $024
- rcall isr ; Timer/Counter1 Compare Match B
-.org $026
- rcall isr ; Timer/Counter1 Compare Match C
-.org $028
- rcall isr ; Timer/Counter1 Overflow
-.org $02A
- rcall isr ; Timer/Counter0 Compare Match A
-.org $02C
- rcall isr ; Timer/Counter0 Compare Match B
-.org $02E
- rcall isr ; Timer/Counter0 Overflow
-.org $030
- rcall isr ; SPI Serial Transfer Complete
-.org $032
- rcall isr ; USART1, Rx Complete
-.org $034
- rcall isr ; USART1 Data register Empty
-.org $036
- rcall isr ; USART1, Tx Complete
-.org $038
- rcall isr ; Analog Comparator
-.org $03A
- rcall isr ; ADC Conversion Complete
-.org $03C
- rcall isr ; EEPROM Ready
-.org $03E
- rcall isr ; Timer/Counter3 Capture Event
-.org $040
- rcall isr ; Timer/Counter3 Compare Match A
-.org $042
- rcall isr ; Timer/Counter3 Compare Match B
-.org $044
- rcall isr ; Timer/Counter3 Compare Match C
-.org $046
- rcall isr ; Timer/Counter3 Overflow
-.org $048
- rcall isr ; 2-wire Serial Interface
-.org $04A
- rcall isr ; Store Program Memory Read
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 2560
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 14336 ; minimum of 0x3800 (from XML) and 0xffff
-mcu_numints:
- .dw 38
-mcu_name:
- .dw 10
- .db "ATmega32U6"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32u6/device.inc b/amforth-6.5/avr8/devices/atmega32u6/device.inc
deleted file mode 100644
index 3944355..0000000
--- a/amforth-6.5/avr8/devices/atmega32u6/device.inc
+++ /dev/null
@@ -1,1839 +0,0 @@
-; Partname: ATmega32U6
-; Built using part description XML file version 1
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw $7B
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $7C
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $50
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw $7F
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw $65
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw $74
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw $75
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw $6A
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw $68
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw $3B
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw $6B
-
-.endif
-
-; ********
-.if WANT_JTAG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw $51
-
-.endif
-
-; ********
-.if WANT_PLL == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw $49
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw $27
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_PORTF == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw $31
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4C
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4D
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $86
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $8B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $8A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C High Byte
-VE_OCR1CH:
- .dw $ff06
- .db "OCR1CH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1CH
-XT_OCR1CH:
- .dw PFA_DOVARIABLE
-PFA_OCR1CH:
- .dw $8D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Low Byte
-VE_OCR1CL:
- .dw $ff06
- .db "OCR1CL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1CL
-XT_OCR1CL:
- .dw PFA_DOVARIABLE
-PFA_OCR1CL:
- .dw $8C
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw $82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $B6
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw $B3
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw $B4
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw $B0
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw $B1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $B2
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw $70
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_3 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register High Byte
-VE_ICR3H:
- .dw $ff05
- .db "ICR3H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3H
-XT_ICR3H:
- .dw PFA_DOVARIABLE
-PFA_ICR3H:
- .dw $97
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Low Byte
-VE_ICR3L:
- .dw $ff05
- .db "ICR3L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3L
-XT_ICR3L:
- .dw PFA_DOVARIABLE
-PFA_ICR3L:
- .dw $96
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A High Byte
-VE_OCR3AH:
- .dw $ff06
- .db "OCR3AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3AH
-XT_OCR3AH:
- .dw PFA_DOVARIABLE
-PFA_OCR3AH:
- .dw $99
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Low Byte
-VE_OCR3AL:
- .dw $ff06
- .db "OCR3AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3AL
-XT_OCR3AL:
- .dw PFA_DOVARIABLE
-PFA_OCR3AL:
- .dw $98
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B High Byte
-VE_OCR3BH:
- .dw $ff06
- .db "OCR3BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3BH
-XT_OCR3BH:
- .dw PFA_DOVARIABLE
-PFA_OCR3BH:
- .dw $9B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Low Byte
-VE_OCR3BL:
- .dw $ff06
- .db "OCR3BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3BL
-XT_OCR3BL:
- .dw PFA_DOVARIABLE
-PFA_OCR3BL:
- .dw $9A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B High Byte
-VE_OCR3CH:
- .dw $ff06
- .db "OCR3CH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3CH
-XT_OCR3CH:
- .dw PFA_DOVARIABLE
-PFA_OCR3CH:
- .dw $9D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Low Byte
-VE_OCR3CL:
- .dw $ff06
- .db "OCR3CL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3CL
-XT_OCR3CL:
- .dw PFA_DOVARIABLE
-PFA_OCR3CL:
- .dw $9C
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw $90
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw $91
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw $92
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 High Byte
-VE_TCNT3H:
- .dw $ff06
- .db "TCNT3H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3H
-XT_TCNT3H:
- .dw PFA_DOVARIABLE
-PFA_TCNT3H:
- .dw $95
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Low Byte
-VE_TCNT3L:
- .dw $ff06
- .db "TCNT3L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3L
-XT_TCNT3L:
- .dw PFA_DOVARIABLE
-PFA_TCNT3L:
- .dw $94
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw $38
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw $71
-
-.endif
-
-; ********
-.if WANT_TWI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw $BD
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw $BA
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw $B8
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw $BC
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw $BB
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw $B9
-
-.endif
-
-; ********
-.if WANT_USART1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRR1H:
- .dw $ff06
- .db "UBRR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1H
-XT_UBRR1H:
- .dw PFA_DOVARIABLE
-PFA_UBRR1H:
- .dw $CD
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR1L:
- .dw $ff06
- .db "UBRR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1L
-XT_UBRR1L:
- .dw PFA_DOVARIABLE
-PFA_UBRR1L:
- .dw $CC
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw $C8
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw $C9
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw $CA
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw $CE
-
-.endif
-
-; ********
-.if WANT_USB_DEVICE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw $E3
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw $E0
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUMH:
- .dw $ff07
- .db "UDFNUMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUMH
-XT_UDFNUMH:
- .dw PFA_DOVARIABLE
-PFA_UDFNUMH:
- .dw $E5
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUML:
- .dw $ff07
- .db "UDFNUML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUML
-XT_UDFNUML:
- .dw PFA_DOVARIABLE
-PFA_UDFNUML:
- .dw $E4
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw $E2
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw $E1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw $E6
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCHX:
- .dw $ff06
- .db "UEBCHX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCHX
-XT_UEBCHX:
- .dw PFA_DOVARIABLE
-PFA_UEBCHX:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw $EC
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw $ED
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw $EB
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw $F1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw $F0
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw $F4
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw $E8
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw $E9
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw $EA
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw $EE
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw $EF
-
-.endif
-
-; ********
-.if WANT_USB_GLOBAL == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; USB Hardware Configuration Register
-VE_UHWCON:
- .dw $ff06
- .db "UHWCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_UHWCON
-XT_UHWCON:
- .dw PFA_DOVARIABLE
-PFA_UHWCON:
- .dw $D7
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw $D8
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBINT:
- .dw $ff06
- .db "USBINT"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBINT
-XT_USBINT:
- .dw PFA_DOVARIABLE
-PFA_USBINT:
- .dw $DA
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_USBSTA:
- .dw $ff06
- .db "USBSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBSTA
-XT_USBSTA:
- .dw PFA_DOVARIABLE
-PFA_USBSTA:
- .dw $D9
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega32u6/device.py b/amforth-6.5/avr8/devices/atmega32u6/device.py
deleted file mode 100644
index 7a32001..0000000
--- a/amforth-6.5/avr8/devices/atmega32u6/device.py
+++ /dev/null
@@ -1,183 +0,0 @@
-# Partname: ATmega32U6
-# Built using part description XML file version 1
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$79',
- 'ADCL': '$78',
- 'ADCSRA': '$7A',
- 'ADCSRB': '$7B',
- 'ADMUX': '$7C',
- 'DIDR0': '$7E',
- 'ACSR': '$50',
- 'DIDR1': '$7F',
- 'SPMCSR': '$57',
- 'CLKPR': '$61',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$4A',
- 'GPIOR2': '$4B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSCCAL': '$66',
- 'PRR0': '$64',
- 'PRR1': '$65',
- 'SMCR': '$53',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'XMCRA': '$74',
- 'XMCRB': '$75',
- 'EEARH': '$42',
- 'EEARL': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EICRA': '$69',
- 'EICRB': '$6A',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'PCICR': '$68',
- 'PCIFR': '$3B',
- 'PCMSK0': '$6B',
- 'OCDR': '$51',
- 'PLLCSR': '$49',
- 'DDRA': '$21',
- 'PINA': '$20',
- 'PORTA': '$22',
- 'DDRB': '$24',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'DDRC': '$27',
- 'PINC': '$26',
- 'PORTC': '$28',
- 'DDRD': '$2A',
- 'PIND': '$29',
- 'PORTD': '$2B',
- 'DDRE': '$2D',
- 'PINE': '$2C',
- 'PORTE': '$2E',
- 'DDRF': '$30',
- 'PINF': '$2F',
- 'PORTF': '$31',
- 'SPCR': '$4C',
- 'SPDR': '$4E',
- 'SPSR': '$4D',
- 'GTCCR': '$43',
- 'OCR0A': '$47',
- 'OCR0B': '$48',
- 'TCCR0A': '$44',
- 'TCCR0B': '$45',
- 'TCNT0': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'ICR1H': '$87',
- 'ICR1L': '$86',
- 'OCR1AH': '$89',
- 'OCR1AL': '$88',
- 'OCR1BH': '$8B',
- 'OCR1BL': '$8A',
- 'OCR1CH': '$8D',
- 'OCR1CL': '$8C',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCCR1C': '$82',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'ASSR': '$B6',
- 'OCR2A': '$B3',
- 'OCR2B': '$B4',
- 'TCCR2A': '$B0',
- 'TCCR2B': '$B1',
- 'TCNT2': '$B2',
- 'TIFR2': '$37',
- 'TIMSK2': '$70',
- 'ICR3H': '$97',
- 'ICR3L': '$96',
- 'OCR3AH': '$99',
- 'OCR3AL': '$98',
- 'OCR3BH': '$9B',
- 'OCR3BL': '$9A',
- 'OCR3CH': '$9D',
- 'OCR3CL': '$9C',
- 'TCCR3A': '$90',
- 'TCCR3B': '$91',
- 'TCCR3C': '$92',
- 'TCNT3H': '$95',
- 'TCNT3L': '$94',
- 'TIFR3': '$38',
- 'TIMSK3': '$71',
- 'TWAMR': '$BD',
- 'TWAR': '$BA',
- 'TWBR': '$B8',
- 'TWCR': '$BC',
- 'TWDR': '$BB',
- 'TWSR': '$B9',
- 'UBRR1H': '$CD',
- 'UBRR1L': '$CC',
- 'UCSR1A': '$C8',
- 'UCSR1B': '$C9',
- 'UCSR1C': '$CA',
- 'UDR1': '$CE',
- 'UDADDR': '$E3',
- 'UDCON': '$E0',
- 'UDFNUMH': '$E5',
- 'UDFNUML': '$E4',
- 'UDIEN': '$E2',
- 'UDINT': '$E1',
- 'UDMFN': '$E6',
- 'UEBCHX': '$F3',
- 'UEBCLX': '$F2',
- 'UECFG0X': '$EC',
- 'UECFG1X': '$ED',
- 'UECONX': '$EB',
- 'UEDATX': '$F1',
- 'UEIENX': '$F0',
- 'UEINT': '$F4',
- 'UEINTX': '$E8',
- 'UENUM': '$E9',
- 'UERST': '$EA',
- 'UESTA0X': '$EE',
- 'UESTA1X': '$EF',
- 'UHWCON': '$D7',
- 'USBCON': '$D8',
- 'USBINT': '$DA',
- 'USBSTA': '$D9',
- 'WDTCSR': '$60',
- 'INT0Addr': '$002',
- 'INT1Addr': '$004',
- 'INT2Addr': '$006',
- 'INT3Addr': '$008',
- 'INT4Addr': '$00A',
- 'INT5Addr': '$00C',
- 'INT6Addr': '$00E',
- 'INT7Addr': '$010',
- 'PCINT0Addr': '$012',
- 'USB_GENAddr': '$014',
- 'USB_COMAddr': '$016',
- 'WDTAddr': '$018',
- 'TIMER2_COMPAAddr': '$01A',
- 'TIMER2_COMPBAddr': '$01C',
- 'TIMER2_OVFAddr': '$01E',
- 'TIMER1_CAPTAddr': '$020',
- 'TIMER1_COMPAAddr': '$022',
- 'TIMER1_COMPBAddr': '$024',
- 'TIMER1_COMPCAddr': '$026',
- 'TIMER1_OVFAddr': '$028',
- 'TIMER0_COMPAAddr': '$02A',
- 'TIMER0_COMPBAddr': '$02C',
- 'TIMER0_OVFAddr': '$02E',
- 'SPI_STCAddr': '$030',
- 'USART1_RXAddr': '$032',
- 'USART1_UDREAddr': '$034',
- 'USART1_TXAddr': '$036',
- 'ANALOG_COMPAddr': '$038',
- 'ADCAddr': '$03A',
- 'EE_READYAddr': '$03C',
- 'TIMER3_CAPTAddr': '$03E',
- 'TIMER3_COMPAAddr': '$040',
- 'TIMER3_COMPBAddr': '$042',
- 'TIMER3_COMPCAddr': '$044',
- 'TIMER3_OVFAddr': '$046',
- 'TWIAddr': '$048',
- 'SPM_READYAddr': '$04A'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega406/atmega406.frt b/amforth-6.5/avr8/devices/atmega406/atmega406.frt
deleted file mode 100644
index 82320fb..0000000
--- a/amforth-6.5/avr8/devices/atmega406/atmega406.frt
+++ /dev/null
@@ -1,267 +0,0 @@
-\ Partname: ATmega406
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant VADMUX \ The VADC multiplexer Selection Register
- $0F constant VADMUX_VADMUX \ Analog Channel and Gain Selection Bits
-&120 constant VADC \ VADC Data Register Bytes
-&122 constant VADCSR \ The VADC Control and Status register
- $08 constant VADCSR_VADEN \ VADC Enable
- $04 constant VADCSR_VADSC \ VADC Satrt Conversion
- $02 constant VADCSR_VADCCIF \ VADC Conversion Complete Interrupt Flag
- $01 constant VADCSR_VADCCIE \ VADC Conversion Complete Interrupt Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control 3 Bits
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control 2 Bits
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&108 constant PCMSK1 \ Pin Change Enable Mask Register 1
-&107 constant PCMSK0 \ Pin Change Enable Mask Register 0
-\ TIMER_COUNTER_1
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $08 constant TCCR1B_CTC1 \ Clear Timer/Counter on Compare Match
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&132 constant TCNT1 \ Timer Counter 1 Bytes
-&136 constant OCR1AL \ Output Compare Register 1A Low byte
-&137 constant OCR1AH \ Output Compare Register 1A High byte
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare Flag A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset
-\ WAKEUP_TIMER
-&98 constant WUTCSR \ Wake-up Timer Control Register
- $80 constant WUTCSR_WUTIF \ Wake-up Timer Interrupt Flag
- $40 constant WUTCSR_WUTIE \ Wake-up Timer Interrupt Enable
- $20 constant WUTCSR_WUTCF \ Wake-up timer Calibration Flag
- $10 constant WUTCSR_WUTR \ Wake-up Timer Reset
- $08 constant WUTCSR_WUTE \ Wake-up Timer Enable
- $07 constant WUTCSR_WUTP \ Wake-up Timer Prescaler Bits
-\ BATTERY_PROTECTION
-&248 constant BPPLR \ Battery Protection Parameter Lock Register
- $02 constant BPPLR_BPPLE \ Battery Protection Parameter Lock Enable
- $01 constant BPPLR_BPPL \ Battery Protection Parameter Lock
-&247 constant BPCR \ Battery Protection Control Register
- $08 constant BPCR_DUVD \
- $04 constant BPCR_SCD \
- $02 constant BPCR_DCD \
- $01 constant BPCR_CCD \
-&246 constant CBPTR \ Current Battery Protection Timing Register
- $F0 constant CBPTR_SCPT \
- $0F constant CBPTR_OCPT \
-&245 constant BPOCD \ Battery Protection OverCurrent Detection Level Register
- $F0 constant BPOCD_DCDL \
- $0F constant BPOCD_CCDL \
-&244 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
- $0F constant BPSCD_SCDL \
-&243 constant BPDUV \ Battery Protection Deep Under Voltage Register
- $30 constant BPDUV_DUVT \
- $0F constant BPDUV_DUDL \
-&242 constant BPIR \ Battery Protection Interrupt Register
- $80 constant BPIR_DUVIF \ Deep Under-voltage Early Warning Interrupt Flag
- $40 constant BPIR_COCIF \ Charge Over-current Protection Activated Interrupt Flag
- $20 constant BPIR_DOCIF \
- $10 constant BPIR_SCIF \
- $08 constant BPIR_DUVIE \ Deep Under-voltage Early Warning Interrupt Enable
- $04 constant BPIR_COCIE \
- $02 constant BPIR_DOCIE \
- $01 constant BPIR_SCIE \
-\ FET
-&240 constant FCSR \
- $20 constant FCSR_PWMOC \ Pulse Width Modulation of OC output
- $10 constant FCSR_PWMOPC \ Pulse Width Modulation Modulation of OPC output
- $08 constant FCSR_CPS \ Current Protection Status
- $04 constant FCSR_DFE \ Discharge FET Enable
- $02 constant FCSR_CFE \ Charge FET Enable
- $01 constant FCSR_PFD \ Precharge FET disable
-\ COULOMB_COUNTER
-&228 constant CADCSRA \ CC-ADC Control and Status Register A
- $80 constant CADCSRA_CADEN \ When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
- $20 constant CADCSRA_CADUB \ CC_ADC Update Busy
- $18 constant CADCSRA_CADAS \ CC_ADC Accumulate Current Select Bits
- $06 constant CADCSRA_CADSI \ The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
- $01 constant CADCSRA_CADSE \ When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
-&229 constant CADCSRB \ CC-ADC Control and Status Register B
- $40 constant CADCSRB_CADACIE \
- $20 constant CADCSRB_CADRCIE \ Regular Current Interrupt Enable
- $10 constant CADCSRB_CADICIE \ CAD Instantenous Current Interrupt Enable
- $04 constant CADCSRB_CADACIF \ CC-ADC Accumulate Current Interrupt Flag
- $02 constant CADCSRB_CADRCIF \ CC-ADC Accumulate Current Interrupt Flag
- $01 constant CADCSRB_CADICIF \ CC-ADC Instantaneous Current Interrupt Flag
-&232 constant CADIC \ CC-ADC Instantaneous Current
-&227 constant CADAC3 \ ADC Accumulate Current
-&226 constant CADAC2 \ ADC Accumulate Current
-&225 constant CADAC1 \ ADC Accumulate Current
-&224 constant CADAC0 \ ADC Accumulate Current
-&230 constant CADRCC \ CC-ADC Regular Charge Current
-&231 constant CADRDC \ CC-ADC Regular Discharge Current
-\ CELL_BALANCING
-&241 constant CBCR \ Cell Balancing Control Register
- $0F constant CBCR_CBE \ Cell Balancing Enables
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BODRF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant FOSCCAL \ Fast Oscillator Calibration Value
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-&192 constant CCSR \ Clock Control and Status Register
- $02 constant CCSR_XOE \ 32 kHz Crystal Oscillator Enable
- $01 constant CCSR_ACS \ Asynchronous Clock Select
-&126 constant DIDR0 \ Digital Input Disable Register
-&100 constant PRR0 \ Power Reduction Register 0
- $08 constant PRR0_PRTWI \ Power Reduction TWI
- $04 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $02 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $01 constant PRR0_PRVADC \ Power Reduction V-ADC
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $C0 constant TCCR0A_COM0A \ Force Output Compare
- $30 constant TCCR0A_COM0B \
- $03 constant TCCR0A_WGM0 \ Clock Select0 bits
-&69 constant TCCR0B \ Timer/Counter0 Control Register
- $80 constant TCCR0B_FOC0A \ Force Output Compare
- $40 constant TCCR0B_FOC0B \ Waveform Generation Mode
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select0 bits
-&70 constant TCNT0 \ Timer Counter 0
-&71 constant OCR0A \ Output compare Register A
- $FF constant OCR0A_OCR0A \
-&72 constant OCR0B \ Output compare Register B
- $FF constant OCR0B_OCR0B \
-&110 constant TIMSK0 \ Timer/Counter Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Output Compare Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Output Compare Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Output Compare Flag
- $02 constant TIFR0_OCF0A \ Output Compare Flag
- $01 constant TIFR0_TOV0 \ Overflow Flag
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-\ PORTD
-&43 constant PORTD \ Data Register, Port D
-&42 constant DDRD \ Data Direction Register, Port D
-&41 constant PIND \ Input Pins, Port D
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ TWI
-&190 constant TWBCSR \ TWI Bus Control and Status Register
- $80 constant TWBCSR_TWBCIF \ TWI Bus Connect/Disconnect Interrupt Flag
- $40 constant TWBCSR_TWBCIE \ TWI Bus Connect/Disconnect Interrupt Enable
- $06 constant TWBCSR_TWBDT \ TWI Bus Disconnect Time-out Period
- $01 constant TWBCSR_TWBCIP \ TWI Bus Connect/Disconnect Interrupt Polarity
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ BANDGAP
-&209 constant BGCRR \ Bandgap Calibration of Resistor Ladder
-&208 constant BGCCR \ Bandgap Calibration Register
- $80 constant BGCCR_BGD \ Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
- $3F constant BGCCR_BGCC \ BG Calibration of PTAT Current Bits
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Programming Enable
- $02 constant EECR_EEPE \ EEPROM Programming Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&2 constant BPINTAddr \ Battery Protection Interrupt
-&4 constant INT0Addr \ External Interrupt Request 0
-&6 constant INT1Addr \ External Interrupt Request 1
-&8 constant INT2Addr \ External Interrupt Request 2
-&10 constant INT3Addr \ External Interrupt Request 3
-&12 constant PCINT0Addr \ Pin Change Interrupt 0
-&14 constant PCINT1Addr \ Pin Change Interrupt 1
-&16 constant WDTAddr \ Watchdog Timeout Interrupt
-&18 constant WAKE_UPAddr \ Wakeup timer overflow
-&20 constant TIM1_COMPAddr \ Timer/Counter 1 Compare Match
-&22 constant TIM1_OVFAddr \ Timer/Counter 1 Overflow
-&24 constant TIM0_COMPAAddr \ Timer/Counter0 Compare A Match
-&26 constant TIM0_COMPBAddr \ Timer/Counter0 Compare B Match
-&28 constant TIM0_OVFAddr \ Timer/Counter0 Overflow
-&30 constant TWI_BUS_CDAddr \ Two-Wire Bus Connect/Disconnect
-&32 constant TWIAddr \ Two-Wire Serial Interface
-&34 constant VADCAddr \ Voltage ADC Conversion Complete
-&36 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-&38 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-&40 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-&42 constant EE_READYAddr \ EEPROM Ready
-&44 constant SPM_READYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega406/device.asm b/amforth-6.5/avr8/devices/atmega406/device.asm
deleted file mode 100644
index bce90e4..0000000
--- a/amforth-6.5/avr8/devices/atmega406/device.asm
+++ /dev/null
@@ -1,104 +0,0 @@
-; Partname: ATmega406
-; generated automatically, do not edit
-
-.nolist
- .include "m406def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WAKEUP_TIMER = 0
-.set WANT_BATTERY_PROTECTION = 0
-.set WANT_FET = 0
-.set WANT_COULOMB_COUNTER = 0
-.set WANT_CELL_BALANCING = 0
-.set WANT_CPU = 0
-.set WANT_WATCHDOG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_TWI = 0
-.set WANT_BANDGAP = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 2 ; please verify; flash size: 40960 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Battery Protection Interrupt
-.org 4
- rcall isr ; External Interrupt Request 0
-.org 6
- rcall isr ; External Interrupt Request 1
-.org 8
- rcall isr ; External Interrupt Request 2
-.org 10
- rcall isr ; External Interrupt Request 3
-.org 12
- rcall isr ; Pin Change Interrupt 0
-.org 14
- rcall isr ; Pin Change Interrupt 1
-.org 16
- rcall isr ; Watchdog Timeout Interrupt
-.org 18
- rcall isr ; Wakeup timer overflow
-.org 20
- rcall isr ; Timer/Counter 1 Compare Match
-.org 22
- rcall isr ; Timer/Counter 1 Overflow
-.org 24
- rcall isr ; Timer/Counter0 Compare A Match
-.org 26
- rcall isr ; Timer/Counter0 Compare B Match
-.org 28
- rcall isr ; Timer/Counter0 Overflow
-.org 30
- rcall isr ; Two-Wire Bus Connect/Disconnect
-.org 32
- rcall isr ; Two-Wire Serial Interface
-.org 34
- rcall isr ; Voltage ADC Conversion Complete
-.org 36
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org 38
- rcall isr ; Coloumb Counter ADC Regular Current
-.org 40
- rcall isr ; Coloumb Counter ADC Accumulator
-.org 42
- rcall isr ; EEPROM Ready
-.org 44
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 2048
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 36864
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 9
- .db "ATmega406",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega406/device.inc b/amforth-6.5/avr8/devices/atmega406/device.inc
deleted file mode 100644
index aa01e8d..0000000
--- a/amforth-6.5/avr8/devices/atmega406/device.inc
+++ /dev/null
@@ -1,1008 +0,0 @@
-; Partname: ATmega406
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC multiplexer Selection Register
-VE_VADMUX:
- .dw $ff06
- .db "VADMUX"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADMUX
-XT_VADMUX:
- .dw PFA_DOVARIABLE
-PFA_VADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register Bytes
-VE_VADC:
- .dw $ff04
- .db "VADC"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADC
-XT_VADC:
- .dw PFA_DOVARIABLE
-PFA_VADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC Control and Status register
-VE_VADCSR:
- .dw $ff06
- .db "VADCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCSR
-XT_VADCSR:
- .dw PFA_DOVARIABLE
-PFA_VADCSR:
- .dw 122
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Enable Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Enable Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 1A Low byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 1A High byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw 137
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_WAKEUP_TIMER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Wake-up Timer Control Register
-VE_WUTCSR:
- .dw $ff06
- .db "WUTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WUTCSR
-XT_WUTCSR:
- .dw PFA_DOVARIABLE
-PFA_WUTCSR:
- .dw 98
-
-.endif
-.if WANT_BATTERY_PROTECTION == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Parameter Lock Register
-VE_BPPLR:
- .dw $ff05
- .db "BPPLR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPPLR
-XT_BPPLR:
- .dw PFA_DOVARIABLE
-PFA_BPPLR:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Control Register
-VE_BPCR:
- .dw $ff04
- .db "BPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCR
-XT_BPCR:
- .dw PFA_DOVARIABLE
-PFA_BPCR:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Current Battery Protection Timing Register
-VE_CBPTR:
- .dw $ff05
- .db "CBPTR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CBPTR
-XT_CBPTR:
- .dw PFA_DOVARIABLE
-PFA_CBPTR:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection OverCurrent Detection Level Register
-VE_BPOCD:
- .dw $ff05
- .db "BPOCD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPOCD
-XT_BPOCD:
- .dw PFA_DOVARIABLE
-PFA_BPOCD:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-Circuit Detection Level Register
-VE_BPSCD:
- .dw $ff05
- .db "BPSCD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCD
-XT_BPSCD:
- .dw PFA_DOVARIABLE
-PFA_BPSCD:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Deep Under Voltage Register
-VE_BPDUV:
- .dw $ff05
- .db "BPDUV",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDUV
-XT_BPDUV:
- .dw PFA_DOVARIABLE
-PFA_BPDUV:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Register
-VE_BPIR:
- .dw $ff04
- .db "BPIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIR
-XT_BPIR:
- .dw PFA_DOVARIABLE
-PFA_BPIR:
- .dw 242
-
-.endif
-.if WANT_FET == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_FCSR:
- .dw $ff04
- .db "FCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_FCSR
-XT_FCSR:
- .dw PFA_DOVARIABLE
-PFA_FCSR:
- .dw 240
-
-.endif
-.if WANT_COULOMB_COUNTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register A
-VE_CADCSRA:
- .dw $ff07
- .db "CADCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRA
-XT_CADCSRA:
- .dw PFA_DOVARIABLE
-PFA_CADCSRA:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register B
-VE_CADCSRB:
- .dw $ff07
- .db "CADCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRB
-XT_CADCSRB:
- .dw PFA_DOVARIABLE
-PFA_CADCSRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADIC:
- .dw $ff05
- .db "CADIC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADIC
-XT_CADIC:
- .dw PFA_DOVARIABLE
-PFA_CADIC:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC3:
- .dw $ff06
- .db "CADAC3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC3
-XT_CADAC3:
- .dw PFA_DOVARIABLE
-PFA_CADAC3:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC2:
- .dw $ff06
- .db "CADAC2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC2
-XT_CADAC2:
- .dw PFA_DOVARIABLE
-PFA_CADAC2:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC1:
- .dw $ff06
- .db "CADAC1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC1
-XT_CADAC1:
- .dw PFA_DOVARIABLE
-PFA_CADAC1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC0:
- .dw $ff06
- .db "CADAC0"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC0
-XT_CADAC0:
- .dw PFA_DOVARIABLE
-PFA_CADAC0:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regular Charge Current
-VE_CADRCC:
- .dw $ff06
- .db "CADRCC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRCC
-XT_CADRCC:
- .dw PFA_DOVARIABLE
-PFA_CADRCC:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regular Discharge Current
-VE_CADRDC:
- .dw $ff06
- .db "CADRDC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRDC
-XT_CADRDC:
- .dw PFA_DOVARIABLE
-PFA_CADRDC:
- .dw 231
-
-.endif
-.if WANT_CELL_BALANCING == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Cell Balancing Control Register
-VE_CBCR:
- .dw $ff04
- .db "CBCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_CBCR
-XT_CBCR:
- .dw PFA_DOVARIABLE
-PFA_CBCR:
- .dw 241
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Fast Oscillator Calibration Value
-VE_FOSCCAL:
- .dw $ff07
- .db "FOSCCAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_FOSCCAL
-XT_FOSCCAL:
- .dw PFA_DOVARIABLE
-PFA_FOSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Control and Status Register
-VE_CCSR:
- .dw $ff04
- .db "CCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_CCSR
-XT_CCSR:
- .dw PFA_DOVARIABLE
-PFA_CCSR:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register A
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port D
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port D
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port D
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bus Control and Status Register
-VE_TWBCSR:
- .dw $ff06
- .db "TWBCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBCSR
-XT_TWBCSR:
- .dw PFA_DOVARIABLE
-PFA_TWBCSR:
- .dw 190
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_BANDGAP == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration of Resistor Ladder
-VE_BGCRR:
- .dw $ff05
- .db "BGCRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRR
-XT_BGCRR:
- .dw PFA_DOVARIABLE
-PFA_BGCRR:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration Register
-VE_BGCCR:
- .dw $ff05
- .db "BGCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCCR
-XT_BGCCR:
- .dw PFA_DOVARIABLE
-PFA_BGCCR:
- .dw 208
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega406/device.py b/amforth-6.5/avr8/devices/atmega406/device.py
deleted file mode 100644
index 46fb5f3..0000000
--- a/amforth-6.5/avr8/devices/atmega406/device.py
+++ /dev/null
@@ -1,290 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega406
-
-MCUREGS = {
-# Interrupt Vectors
- 'BPINTAddr' : '#2', # Battery Protection Interrupt
- 'INT0Addr' : '#4', # External Interrupt Request 0
- 'INT1Addr' : '#6', # External Interrupt Request 1
- 'INT2Addr' : '#8', # External Interrupt Request 2
- 'INT3Addr' : '#10', # External Interrupt Request 3
- 'PCINT0Addr' : '#12', # Pin Change Interrupt 0
- 'PCINT1Addr' : '#14', # Pin Change Interrupt 1
- 'WDTAddr' : '#16', # Watchdog Timeout Interrupt
- 'WAKE_UPAddr' : '#18', # Wakeup timer overflow
- 'TIM1_COMPAddr' : '#20', # Timer/Counter 1 Compare Match
- 'TIM1_OVFAddr' : '#22', # Timer/Counter 1 Overflow
- 'TIM0_COMPAAddr' : '#24', # Timer/Counter0 Compare A Match
- 'TIM0_COMPBAddr' : '#26', # Timer/Counter0 Compare B Match
- 'TIM0_OVFAddr' : '#28', # Timer/Counter0 Overflow
- 'TWI_BUS_CDAddr' : '#30', # Two-Wire Bus Connect/Disconnect
- 'TWIAddr' : '#32', # Two-Wire Serial Interface
- 'VADCAddr' : '#34', # Voltage ADC Conversion Complete
- 'CCADC_CONVAddr' : '#36', # Coulomb Counter ADC Conversion Complete
- 'CCADC_REG_CURAddr' : '#38', # Coloumb Counter ADC Regular Current
- 'CCADC_ACCAddr' : '#40', # Coloumb Counter ADC Accumulator
- 'EE_READYAddr' : '#42', # EEPROM Ready
- 'SPM_READYAddr' : '#44', # Store Program Memory Ready
-
-# Module AD_CONVERTER
- 'VADMUX' : '$7c', # The VADC multiplexer Selection
- 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
- 'VADC' : '$78', # VADC Data Register Bytes
- 'VADCSR' : '$7a', # The VADC Control and Status re
- 'VADCSR_VADEN': '$8', # VADC Enable
- 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
- 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
- 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
- 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
- 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
-
-# Module TIMER_COUNTER_1
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_CTC1': '$8', # Clear Timer/Counter on Compare
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCNT1' : '$84', # Timer Counter 1 Bytes
- 'OCR1AL' : '$88', # Output Compare Register 1A Low
- 'OCR1AH' : '$89', # Output Compare Register 1A Hig
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
-
-# Module WAKEUP_TIMER
- 'WUTCSR' : '$62', # Wake-up Timer Control Register
- 'WUTCSR_WUTIF': '$80', # Wake-up Timer Interrupt Flag
- 'WUTCSR_WUTIE': '$40', # Wake-up Timer Interrupt Enable
- 'WUTCSR_WUTCF': '$20', # Wake-up timer Calibration Flag
- 'WUTCSR_WUTR': '$10', # Wake-up Timer Reset
- 'WUTCSR_WUTE': '$8', # Wake-up Timer Enable
- 'WUTCSR_WUTP': '$7', # Wake-up Timer Prescaler Bits
-
-# Module BATTERY_PROTECTION
- 'BPPLR' : '$f8', # Battery Protection Parameter L
- 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
- 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
- 'BPCR' : '$f7', # Battery Protection Control Reg
- 'BPCR_DUVD': '$8', #
- 'BPCR_SCD': '$4', #
- 'BPCR_DCD': '$2', #
- 'BPCR_CCD': '$1', #
- 'CBPTR' : '$f6', # Current Battery Protection Tim
- 'CBPTR_SCPT': '$f0', #
- 'CBPTR_OCPT': '$f', #
- 'BPOCD' : '$f5', # Battery Protection OverCurrent
- 'BPOCD_DCDL': '$f0', #
- 'BPOCD_CCDL': '$f', #
- 'BPSCD' : '$f4', # Battery Protection Short-Circu
- 'BPSCD_SCDL': '$f', #
- 'BPDUV' : '$f3', # Battery Protection Deep Under
- 'BPDUV_DUVT': '$30', #
- 'BPDUV_DUDL': '$f', #
- 'BPIR' : '$f2', # Battery Protection Interrupt R
- 'BPIR_DUVIF': '$80', # Deep Under-voltage Early Warni
- 'BPIR_COCIF': '$40', # Charge Over-current Protection
- 'BPIR_DOCIF': '$20', #
- 'BPIR_SCIF': '$10', #
- 'BPIR_DUVIE': '$8', # Deep Under-voltage Early Warni
- 'BPIR_COCIE': '$4', #
- 'BPIR_DOCIE': '$2', #
- 'BPIR_SCIE': '$1', #
-
-# Module FET
- 'FCSR' : '$f0', #
- 'FCSR_PWMOC': '$20', # Pulse Width Modulation of OC o
- 'FCSR_PWMOPC': '$10', # Pulse Width Modulation Modulat
- 'FCSR_CPS': '$8', # Current Protection Status
- 'FCSR_DFE': '$4', # Discharge FET Enable
- 'FCSR_CFE': '$2', # Charge FET Enable
- 'FCSR_PFD': '$1', # Precharge FET disable
-
-# Module COULOMB_COUNTER
- 'CADCSRA' : '$e4', # CC-ADC Control and Status Regi
- 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
- 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
- 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
- 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
- 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
- 'CADCSRB' : '$e5', # CC-ADC Control and Status Regi
- 'CADCSRB_CADACIE': '$40', #
- 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
- 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
- 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
- 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
- 'CADIC' : '$e8', # CC-ADC Instantaneous Current
- 'CADAC3' : '$e3', # ADC Accumulate Current
- 'CADAC2' : '$e2', # ADC Accumulate Current
- 'CADAC1' : '$e1', # ADC Accumulate Current
- 'CADAC0' : '$e0', # ADC Accumulate Current
- 'CADRCC' : '$e6', # CC-ADC Regular Charge Current
- 'CADRDC' : '$e7', # CC-ADC Regular Discharge Curre
-
-# Module CELL_BALANCING
- 'CBCR' : '$f1', # Cell Balancing Control Registe
- 'CBCR_CBE': '$f', # Cell Balancing Enables
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'CCSR' : '$c0', # Clock Control and Status Regis
- 'CCSR_XOE': '$2', # 32 kHz Crystal Oscillator Enab
- 'CCSR_ACS': '$1', # Asynchronous Clock Select
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'PRR0' : '$64', # Power Reduction Register 0
- 'PRR0_PRTWI': '$8', # Power Reduction TWI
- 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
- 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
- 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Force Output Compare
- 'TCCR0A_COM0B': '$30', #
- 'TCCR0A_WGM0': '$3', # Clock Select0 bits
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare
- 'TCCR0B_FOC0B': '$40', # Waveform Generation Mode
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select0 bits
- 'TCNT0' : '$46', # Timer Counter 0
- 'OCR0A' : '$47', # Output compare Register A
- 'OCR0A_OCR0A': '$ff', #
- 'OCR0B' : '$48', # Output compare Register B
- 'OCR0B_OCR0B': '$ff', #
- 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
- 'TIMSK0_OCIE0B': '$4', # Output Compare Interrupt Enabl
- 'TIMSK0_OCIE0A': '$2', # Output Compare Interrupt Enabl
- 'TIMSK0_TOIE0': '$1', # Overflow Interrupt Enable
- 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
- 'TIFR0_OCF0B': '$4', # Output Compare Flag
- 'TIFR0_OCF0A': '$2', # Output Compare Flag
- 'TIFR0_TOV0': '$1', # Overflow Flag
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
-
-# Module PORTD
- 'PORTD' : '$2b', # Data Register, Port D
- 'DDRD' : '$2a', # Data Direction Register, Port
- 'PIND' : '$29', # Input Pins, Port D
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module TWI
- 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
- 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
- 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
- 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module BANDGAP
- 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
- 'BGCCR' : '$d0', # Bandgap Calibration Register
- 'BGCCR_BGD': '$80', # Setting the BGD bit to one wil
- 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Programming Enab
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega406/words/sleep.asm b/amforth-6.5/avr8/devices/atmega406/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega406/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64/atmega64.frt b/amforth-6.5/avr8/devices/atmega64/atmega64.frt
deleted file mode 100644
index 1cc51f1..0000000
--- a/amforth-6.5/avr8/devices/atmega64/atmega64.frt
+++ /dev/null
@@ -1,331 +0,0 @@
-\ Partname: ATmega64
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&64 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&36 constant ADC \ ADC Data Register Bytes
-&38 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&142 constant ADCSRB \ The ADC Control and Status register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ TWI
-&112 constant TWBR \ TWI Bit Rate register
-&116 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&113 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&115 constant TWDR \ TWI Data register
-&114 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&44 constant UDR0 \ USART I/O Data Register
-&43 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&42 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&149 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
-&41 constant UBRR0L \ USART Baud Rate Register Low Byte
-\ USART1
-&156 constant UDR1 \ USART I/O Data Register
-&155 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&154 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&157 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
-&153 constant UBRR1L \ USART Baud Rate Register Low Byte
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SRE \ External SRAM Enable
- $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
- $20 constant MCUCR_SE \ Sleep Enable
- $18 constant MCUCR_SM \ Sleep Mode Select
- $04 constant MCUCR_SM2 \ Sleep Mode Select
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUCSR \ MCU Control And Status Register
- $80 constant MCUCSR_JTD \ JTAG Interface Disable
- $10 constant MCUCSR_JTRF \ JTAG Reset Flag
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&109 constant XMCRA \ External Memory Control Register A
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW0 \ Wait state select bit lower page
- $02 constant XMCRA_SRW11 \ Wait state select bit upper page
-&108 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&111 constant OSCCAL \ Oscillator Calibration Value
-&92 constant XDIV \ XTAL Divide Control Register
- $80 constant XDIV_XDIVEN \ XTAL Divide Enable
- $7F constant XDIV_XDIV \ XTAl Divide Select Bits
-\ BOOT_LOAD
-&104 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ MISC
-\ EXTERNAL_INTERRUPT
-&106 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&90 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&89 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&88 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ PORTE
-&35 constant PORTE \ Data Register, Port E
-&34 constant DDRE \ Data Direction Register, Port E
-&33 constant PINE \ Input Pins, Port E
-\ PORTF
-&98 constant PORTF \ Data Register, Port F
-&97 constant DDRF \ Data Direction Register, Port F
-&32 constant PINF \ Input Pins, Port F
-\ PORTG
-&101 constant PORTG \ Data Register, Port G
-&100 constant DDRG \ Data Direction Register, Port G
-&99 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&81 constant OCR0 \ Output Compare Register
-&80 constant ASSR \ Asynchronus Status Register
- $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
- $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
- $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
- $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
-&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&86 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_1
-&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
- $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
-&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
- $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&122 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
- $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
- $30 constant TCCR2_COM2 \ Compare Match Output Mode
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select
-&68 constant TCNT2 \ Timer/Counter Register
-&67 constant OCR2 \ Output Compare Register
-\ TIMER_COUNTER_3
-&139 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
-&138 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&140 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
- $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
-&136 constant TCNT3 \ Timer/Counter3 Bytes
-&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
-&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART0__RXAddr \ USART0, Rx Complete
-&38 constant USART0__UDREAddr \ USART0 Data Register Empty
-&40 constant USART0__TXAddr \ USART0, Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&60 constant USART1__RXAddr \ USART1, Rx Complete
-&62 constant USART1__UDREAddr \ USART1, Data Register Empty
-&64 constant USART1__TXAddr \ USART1, Tx Complete
-&66 constant TWIAddr \ 2-wire Serial Interface
-&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64/device.asm b/amforth-6.5/avr8/devices/atmega64/device.asm
deleted file mode 100644
index 1bfc5bb..0000000
--- a/amforth-6.5/avr8/devices/atmega64/device.asm
+++ /dev/null
@@ -1,135 +0,0 @@
-; Partname: ATmega64
-; generated automatically, do not edit
-
-.nolist
- .include "m64def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_MISC = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_WATCHDOG = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match
-.org 32
- rcall isr ; Timer/Counter0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART0, Rx Complete
-.org 38
- rcall isr ; USART0 Data Register Empty
-.org 40
- rcall isr ; USART0, Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Timer/Counter1 Compare Match C
-.org 50
- rcall isr ; Timer/Counter3 Capture Event
-.org 52
- rcall isr ; Timer/Counter3 Compare Match A
-.org 54
- rcall isr ; Timer/Counter3 Compare Match B
-.org 56
- rcall isr ; Timer/Counter3 Compare Match C
-.org 58
- rcall isr ; Timer/Counter3 Overflow
-.org 60
- rcall isr ; USART1, Rx Complete
-.org 62
- rcall isr ; USART1, Data Register Empty
-.org 64
- rcall isr ; USART1, Tx Complete
-.org 66
- rcall isr ; 2-wire Serial Interface
-.org 68
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 35
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 35
-mcu_name:
- .dw 8
- .db "ATmega64"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64/device.inc b/amforth-6.5/avr8/devices/atmega64/device.inc
deleted file mode 100644
index ca671b9..0000000
--- a/amforth-6.5/avr8/devices/atmega64/device.inc
+++ /dev/null
@@ -1,1179 +0,0 @@
-; Partname: ATmega64
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 142
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 114
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw 41
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 155
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 157
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR1H:
- .dw $ff06
- .db "UBRR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1H
-XT_UBRR1H:
- .dw PFA_DOVARIABLE
-PFA_UBRR1H:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR1L:
- .dw $ff06
- .db "UBRR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1L
-XT_UBRR1L:
- .dw PFA_DOVARIABLE
-PFA_UBRR1L:
- .dw 153
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; XTAL Divide Control Register
-VE_XDIV:
- .dw $ff04
- .db "XDIV"
- .dw VE_HEAD
- .set VE_HEAD=VE_XDIV
-XT_XDIV:
- .dw PFA_DOVARIABLE
-PFA_XDIV:
- .dw 92
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 104
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 66
-
-.endif
-.if WANT_MISC == 1
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 88
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 33
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 98
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 32
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 99
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronus Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 86
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Mask Register
-VE_ETIMSK:
- .dw $ff06
- .db "ETIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIMSK
-XT_ETIMSK:
- .dw PFA_DOVARIABLE
-PFA_ETIMSK:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Flag register
-VE_ETIFR:
- .dw $ff05
- .db "ETIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIFR
-XT_ETIFR:
- .dw PFA_DOVARIABLE
-PFA_ETIFR:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 139
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output compare Register C Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 128
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega64/device.py b/amforth-6.5/avr8/devices/atmega64/device.py
deleted file mode 100644
index dc1f517..0000000
--- a/amforth-6.5/avr8/devices/atmega64/device.py
+++ /dev/null
@@ -1,405 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega64
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#36', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#40', # USART0, Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
- 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#60', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#64', # USART1, Tx Complete
- 'TWIAddr' : '#66', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#68', # Store Program Memory Read
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$24', # ADC Data Register Bytes
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$8e', # The ADC Control and Status reg
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module TWI
- 'TWBR' : '$70', # TWI Bit Rate register
- 'TWCR' : '$74', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$71', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$73', # TWI Data register
- 'TWAR' : '$72', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$2c', # USART I/O Data Register
- 'UCSR0A' : '$2b', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$2a', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$95', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0H' : '$90', # USART Baud Rate Register Hight
- 'UBRR0L' : '$29', # USART Baud Rate Register Low B
-
-# Module USART1
- 'UDR1' : '$9c', # USART I/O Data Register
- 'UCSR1A' : '$9b', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$9a', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$9d', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1H' : '$98', # USART Baud Rate Register Hight
- 'UBRR1L' : '$99', # USART Baud Rate Register Low B
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SRE': '$80', # External SRAM Enable
- 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
- 'MCUCR_SE': '$20', # Sleep Enable
- 'MCUCR_SM': '$18', # Sleep Mode Select
- 'MCUCR_SM2': '$4', # Sleep Mode Select
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$6d', # External Memory Control Regist
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
- 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
- 'XMCRB' : '$6c', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$6f', # Oscillator Calibration Value
- 'XDIV' : '$5c', # XTAL Divide Control Register
- 'XDIV_XDIVEN': '$80', # XTAL Divide Enable
- 'XDIV_XDIV': '$7f', # XTAl Divide Select Bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$68', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$42', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module MISC
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'SFIOR_PUD': '$4', # Pull Up Disable
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
- 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$6a', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$5a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$59', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$58', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$23', # Data Register, Port E
- 'DDRE' : '$22', # Data Direction Register, Port
- 'PINE' : '$21', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$62', # Data Register, Port F
- 'DDRF' : '$61', # Data Direction Register, Port
- 'PINF' : '$20', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$65', # Data Register, Port G
- 'DDRG' : '$64', # Data Direction Register, Port
- 'PING' : '$63', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$51', # Output Compare Register
- 'ASSR' : '$50', # Asynchronus Status Register
- 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
- 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
- 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
- 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'OCR1C' : '$78', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$45', # Timer/Counter Control Register
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
- 'TCCR2_COM2': '$30', # Compare Match Output Mode
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select
- 'TCNT2' : '$44', # Timer/Counter Register
- 'OCR2' : '$43', # Output Compare Register
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TIMSK' : '$57', #
- 'TIMSK_OCIE2': '$80', #
- 'TIMSK_TOIE2': '$40', #
-
-# Module TIMER_COUNTER_3
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
- 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
- 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
- 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
- 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_ICF3': '$20', # Input Capture Flag 1
- 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
- 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
- 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
- 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
- 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
- 'TCNT3' : '$88', # Timer/Counter3 Bytes
- 'OCR3A' : '$86', # Timer/Counter3 Output Compare
- 'OCR3B' : '$84', # Timer/Counter3 Output Compare
- 'OCR3C' : '$82', # Timer/Counter3 Output compare
- 'ICR3' : '$80', # Timer/Counter3 Input Capture R
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega64/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega64/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega64/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega64/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega640/atmega640.frt b/amforth-6.5/avr8/devices/atmega640/atmega640.frt
deleted file mode 100644
index 2432b5b..0000000
--- a/amforth-6.5/avr8/devices/atmega640/atmega640.frt
+++ /dev/null
@@ -1,579 +0,0 @@
-\ Partname: ATmega640
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Data Register, Port G
-&51 constant DDRG \ Data Direction Register, Port G
-&50 constant PING \ Input Pins, Port G
-\ PORTH
-&258 constant PORTH \ PORT H Data Register
-&257 constant DDRH \ PORT H Data Direction Register
-&256 constant PINH \ PORT H Input Pins
-\ PORTJ
-&261 constant PORTJ \ PORT J Data Register
-&260 constant DDRJ \ PORT J Data Direction Register
-&259 constant PINJ \ PORT J Input Pins
-\ PORTK
-&264 constant PORTK \ PORT K Data Register
-&263 constant DDRK \ PORT K Data Direction Register
-&262 constant PINK \ PORT K Input Pins
-\ PORTL
-&267 constant PORTL \ PORT L Data Register
-&266 constant DDRL \ PORT L Data Direction Register
-&265 constant PINL \ PORT L Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
- $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
- $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
-&290 constant TCCR5C \ Timer/Counter 5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
- $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
- $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
- $20 constant TIFR5_ICF5 \ Input Capture Flag 5
- $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
- $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
- $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
- $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
- $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
-&162 constant TCCR4C \ Timer/Counter 4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
- $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
- $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
- $20 constant TIFR4_ICF4 \ Input Capture Flag 4
- $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
- $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
- $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
-&146 constant TCCR3C \ Timer/Counter 3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
- $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
- $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
- $20 constant TIFR3_ICF3 \ Input Capture Flag 3
- $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
- $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
- $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&116 constant XMCRA \ External Memory Control Register A
- $80 constant XMCRA_SRE \ External SRAM Enable
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW1 \ Wait state select bit upper page
- $03 constant XMCRA_SRW0 \ Wait state select bit lower page
-&117 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Power Reduction USART3
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&125 constant DIDR2 \ Digital Input Disable Register
- $80 constant DIDR2_ADC15D \
- $40 constant DIDR2_ADC14D \
- $20 constant DIDR2_ADC13D \
- $10 constant DIDR2_ADC12D \
- $08 constant DIDR2_ADC11D \
- $04 constant DIDR2_ADC10D \
- $02 constant DIDR2_ADC9D \
- $01 constant DIDR2_ADC8D \
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART2
-&214 constant UDR2 \ USART I/O Data Register
-&208 constant UCSR2A \ USART Control and Status Register A
- $80 constant UCSR2A_RXC2 \ USART Receive Complete
- $40 constant UCSR2A_TXC2 \ USART Transmitt Complete
- $20 constant UCSR2A_UDRE2 \ USART Data Register Empty
- $10 constant UCSR2A_FE2 \ Framing Error
- $08 constant UCSR2A_DOR2 \ Data overRun
- $04 constant UCSR2A_UPE2 \ Parity Error
- $02 constant UCSR2A_U2X2 \ Double the USART transmission speed
- $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode
-&209 constant UCSR2B \ USART Control and Status Register B
- $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
- $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
- $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR2B_RXEN2 \ Receiver Enable
- $08 constant UCSR2B_TXEN2 \ Transmitter Enable
- $04 constant UCSR2B_UCSZ22 \ Character Size
- $02 constant UCSR2B_RXB82 \ Receive Data Bit 8
- $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8
-&210 constant UCSR2C \ USART Control and Status Register C
- $C0 constant UCSR2C_UMSEL2 \ USART Mode Select
- $30 constant UCSR2C_UPM2 \ Parity Mode Bits
- $08 constant UCSR2C_USBS2 \ Stop Bit Select
- $06 constant UCSR2C_UCSZ2 \ Character Size
- $01 constant UCSR2C_UCPOL2 \ Clock Polarity
-&212 constant UBRR2 \ USART Baud Rate Register Bytes
-\ USART3
-&310 constant UDR3 \ USART I/O Data Register
-&304 constant UCSR3A \ USART Control and Status Register A
- $80 constant UCSR3A_RXC3 \ USART Receive Complete
- $40 constant UCSR3A_TXC3 \ USART Transmitt Complete
- $20 constant UCSR3A_UDRE3 \ USART Data Register Empty
- $10 constant UCSR3A_FE3 \ Framing Error
- $08 constant UCSR3A_DOR3 \ Data overRun
- $04 constant UCSR3A_UPE3 \ Parity Error
- $02 constant UCSR3A_U2X3 \ Double the USART transmission speed
- $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode
-&305 constant UCSR3B \ USART Control and Status Register B
- $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
- $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
- $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR3B_RXEN3 \ Receiver Enable
- $08 constant UCSR3B_TXEN3 \ Transmitter Enable
- $04 constant UCSR3B_UCSZ32 \ Character Size
- $02 constant UCSR3B_RXB83 \ Receive Data Bit 8
- $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8
-&306 constant UCSR3C \ USART Control and Status Register C
- $C0 constant UCSR3C_UMSEL3 \ USART Mode Select
- $30 constant UCSR3C_UPM3 \ Parity Mode Bits
- $08 constant UCSR3C_USBS3 \ Stop Bit Select
- $06 constant UCSR3C_UCSZ3 \ Character Size
- $01 constant UCSR3C_UCPOL3 \ Clock Polarity
-&308 constant UBRR3 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0__RXAddr \ USART0, Rx Complete
-&52 constant USART0__UDREAddr \ USART0 Data register Empty
-&54 constant USART0__TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1__RXAddr \ USART1, Rx Complete
-&74 constant USART1__UDREAddr \ USART1 Data register Empty
-&76 constant USART1__TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2__RXAddr \ USART2, Rx Complete
-&104 constant USART2__UDREAddr \ USART2 Data register Empty
-&106 constant USART2__TXAddr \ USART2, Tx Complete
-&108 constant USART3__RXAddr \ USART3, Rx Complete
-&110 constant USART3__UDREAddr \ USART3 Data register Empty
-&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega640/device.asm b/amforth-6.5/avr8/devices/atmega640/device.asm
deleted file mode 100644
index 32d7b10..0000000
--- a/amforth-6.5/avr8/devices/atmega640/device.asm
+++ /dev/null
@@ -1,184 +0,0 @@
-; Partname: ATmega640
-; generated automatically, do not edit
-
-.nolist
- .include "m640def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_PORTK = 0
-.set WANT_PORTL = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_USART1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART2 = 0
-.set WANT_USART3 = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.equ INTVECTORS = 57
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 8192
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 57
-mcu_name:
- .dw 9
- .db "ATmega640",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega640/device.inc b/amforth-6.5/avr8/devices/atmega640/device.inc
deleted file mode 100644
index 5c15876..0000000
--- a/amforth-6.5/avr8/devices/atmega640/device.inc
+++ /dev/null
@@ -1,1968 +0,0 @@
-; Partname: ATmega640
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 258
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 257
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 256
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 261
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 260
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 259
-
-.endif
-.if WANT_PORTK == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Data Register
-VE_PORTK:
- .dw $ff05
- .db "PORTK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTK
-XT_PORTK:
- .dw PFA_DOVARIABLE
-PFA_PORTK:
- .dw 264
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Data Direction Register
-VE_DDRK:
- .dw $ff04
- .db "DDRK"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRK
-XT_DDRK:
- .dw PFA_DOVARIABLE
-PFA_DDRK:
- .dw 263
-; ( -- addr ) System Constant
-; R( -- )
-; PORT K Input Pins
-VE_PINK:
- .dw $ff04
- .db "PINK"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINK
-XT_PINK:
- .dw PFA_DOVARIABLE
-PFA_PINK:
- .dw 262
-
-.endif
-.if WANT_PORTL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Data Register
-VE_PORTL:
- .dw $ff05
- .db "PORTL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTL
-XT_PORTL:
- .dw PFA_DOVARIABLE
-PFA_PORTL:
- .dw 267
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Data Direction Register
-VE_DDRL:
- .dw $ff04
- .db "DDRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRL
-XT_DDRL:
- .dw PFA_DOVARIABLE
-PFA_DDRL:
- .dw 266
-; ( -- addr ) System Constant
-; R( -- )
-; PORT L Input Pins
-VE_PINL:
- .dw $ff04
- .db "PINL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINL
-XT_PINL:
- .dw PFA_DOVARIABLE
-PFA_PINL:
- .dw 265
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR2:
- .dw $ff04
- .db "UDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR2
-XT_UDR2:
- .dw PFA_DOVARIABLE
-PFA_UDR2:
- .dw 214
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR2A:
- .dw $ff06
- .db "UCSR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2A
-XT_UCSR2A:
- .dw PFA_DOVARIABLE
-PFA_UCSR2A:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR2B:
- .dw $ff06
- .db "UCSR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2B
-XT_UCSR2B:
- .dw PFA_DOVARIABLE
-PFA_UCSR2B:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR2C:
- .dw $ff06
- .db "UCSR2C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR2C
-XT_UCSR2C:
- .dw PFA_DOVARIABLE
-PFA_UCSR2C:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR2:
- .dw $ff05
- .db "UBRR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR2
-XT_UBRR2:
- .dw PFA_DOVARIABLE
-PFA_UBRR2:
- .dw 212
-
-.endif
-.if WANT_USART3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR3:
- .dw $ff04
- .db "UDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR3
-XT_UDR3:
- .dw PFA_DOVARIABLE
-PFA_UDR3:
- .dw 310
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR3A:
- .dw $ff06
- .db "UCSR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3A
-XT_UCSR3A:
- .dw PFA_DOVARIABLE
-PFA_UCSR3A:
- .dw 304
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR3B:
- .dw $ff06
- .db "UCSR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3B
-XT_UCSR3B:
- .dw PFA_DOVARIABLE
-PFA_UCSR3B:
- .dw 305
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR3C:
- .dw $ff06
- .db "UCSR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR3C
-XT_UCSR3C:
- .dw PFA_DOVARIABLE
-PFA_UCSR3C:
- .dw 306
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR3:
- .dw $ff05
- .db "UBRR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR3
-XT_UBRR3:
- .dw PFA_DOVARIABLE
-PFA_UBRR3:
- .dw 308
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega640/device.py b/amforth-6.5/avr8/devices/atmega640/device.py
deleted file mode 100644
index 526b8ed..0000000
--- a/amforth-6.5/avr8/devices/atmega640/device.py
+++ /dev/null
@@ -1,632 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega640
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Data Register, Port G
- 'DDRG' : '$33', # Data Direction Register, Port
- 'PING' : '$32', # Input Pins, Port G
-
-# Module PORTH
- 'PORTH' : '$102', # PORT H Data Register
- 'DDRH' : '$101', # PORT H Data Direction Register
- 'PINH' : '$100', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$105', # PORT J Data Register
- 'DDRJ' : '$104', # PORT J Data Direction Register
- 'PINJ' : '$103', # PORT J Input Pins
-
-# Module PORTK
- 'PORTK' : '$108', # PORT K Data Register
- 'DDRK' : '$107', # PORT K Data Direction Register
- 'PINK' : '$106', # PORT K Input Pins
-
-# Module PORTL
- 'PORTL' : '$10b', # PORT L Data Register
- 'DDRL' : '$10a', # PORT L Data Direction Register
- 'PINL' : '$109', # PORT L Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
- 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
- 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
- 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
- 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
- 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_ICF5': '$20', # Input Capture Flag 5
- 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
- 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
- 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
- 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
- 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
- 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
- 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
- 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_ICF4': '$20', # Input Capture Flag 4
- 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
- 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
- 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
- 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
- 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
- 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
- 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_ICF3': '$20', # Input Capture Flag 3
- 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
- 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
- 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$74', # External Memory Control Regist
- 'XMCRA_SRE': '$80', # External SRAM Enable
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
- 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
- 'XMCRB' : '$75', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'EIND' : '$5c', # Extended Indirect Register
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR1' : '$65', # Power Reduction Register1
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Power Reduction USART3
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', #
- 'DIDR2_ADC14D': '$40', #
- 'DIDR2_ADC13D': '$20', #
- 'DIDR2_ADC12D': '$10', #
- 'DIDR2_ADC11D': '$8', #
- 'DIDR2_ADC10D': '$4', #
- 'DIDR2_ADC9D': '$2', #
- 'DIDR2_ADC8D': '$1', #
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART2
- 'UDR2' : '$d6', # USART I/O Data Register
- 'UCSR2A' : '$d0', # USART Control and Status Regis
- 'UCSR2A_RXC2': '$80', # USART Receive Complete
- 'UCSR2A_TXC2': '$40', # USART Transmitt Complete
- 'UCSR2A_UDRE2': '$20', # USART Data Register Empty
- 'UCSR2A_FE2': '$10', # Framing Error
- 'UCSR2A_DOR2': '$8', # Data overRun
- 'UCSR2A_UPE2': '$4', # Parity Error
- 'UCSR2A_U2X2': '$2', # Double the USART transmission
- 'UCSR2A_MPCM2': '$1', # Multi-processor Communication
- 'UCSR2B' : '$d1', # USART Control and Status Regis
- 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable
- 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable
- 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte
- 'UCSR2B_RXEN2': '$10', # Receiver Enable
- 'UCSR2B_TXEN2': '$8', # Transmitter Enable
- 'UCSR2B_UCSZ22': '$4', # Character Size
- 'UCSR2B_RXB82': '$2', # Receive Data Bit 8
- 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8
- 'UCSR2C' : '$d2', # USART Control and Status Regis
- 'UCSR2C_UMSEL2': '$c0', # USART Mode Select
- 'UCSR2C_UPM2': '$30', # Parity Mode Bits
- 'UCSR2C_USBS2': '$8', # Stop Bit Select
- 'UCSR2C_UCSZ2': '$6', # Character Size
- 'UCSR2C_UCPOL2': '$1', # Clock Polarity
- 'UBRR2' : '$d4', # USART Baud Rate Register Byte
-
-# Module USART3
- 'UDR3' : '$136', # USART I/O Data Register
- 'UCSR3A' : '$130', # USART Control and Status Regis
- 'UCSR3A_RXC3': '$80', # USART Receive Complete
- 'UCSR3A_TXC3': '$40', # USART Transmitt Complete
- 'UCSR3A_UDRE3': '$20', # USART Data Register Empty
- 'UCSR3A_FE3': '$10', # Framing Error
- 'UCSR3A_DOR3': '$8', # Data overRun
- 'UCSR3A_UPE3': '$4', # Parity Error
- 'UCSR3A_U2X3': '$2', # Double the USART transmission
- 'UCSR3A_MPCM3': '$1', # Multi-processor Communication
- 'UCSR3B' : '$131', # USART Control and Status Regis
- 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable
- 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable
- 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte
- 'UCSR3B_RXEN3': '$10', # Receiver Enable
- 'UCSR3B_TXEN3': '$8', # Transmitter Enable
- 'UCSR3B_UCSZ32': '$4', # Character Size
- 'UCSR3B_RXB83': '$2', # Receive Data Bit 8
- 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8
- 'UCSR3C' : '$132', # USART Control and Status Regis
- 'UCSR3C_UMSEL3': '$c0', # USART Mode Select
- 'UCSR3C_UPM3': '$30', # Parity Mode Bits
- 'UCSR3C_USBS3': '$8', # Stop Bit Select
- 'UCSR3C_UCSZ3': '$6', # Character Size
- 'UCSR3C_UCPOL3': '$1', # Clock Polarity
- 'UBRR3' : '$134', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega640/words/sleep.asm b/amforth-6.5/avr8/devices/atmega640/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega640/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644/atmega644.frt b/amforth-6.5/avr8/devices/atmega644/atmega644.frt
deleted file mode 100644
index 65858f6..0000000
--- a/amforth-6.5/avr8/devices/atmega644/atmega644.frt
+++ /dev/null
@@ -1,316 +0,0 @@
-\ Partname: ATmega644
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega644/device.asm b/amforth-6.5/avr8/devices/atmega644/device.asm
deleted file mode 100644
index c58fe56..0000000
--- a/amforth-6.5/avr8/devices/atmega644/device.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-; Partname: ATmega644
-; generated automatically, do not edit
-
-.nolist
- .include "m644def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 28
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 28
-mcu_name:
- .dw 9
- .db "ATmega644",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644/device.inc b/amforth-6.5/avr8/devices/atmega644/device.inc
deleted file mode 100644
index d28946f..0000000
--- a/amforth-6.5/avr8/devices/atmega644/device.inc
+++ /dev/null
@@ -1,1065 +0,0 @@
-; Partname: ATmega644
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega644/device.py b/amforth-6.5/avr8/devices/atmega644/device.py
deleted file mode 100644
index 21ccfb1..0000000
--- a/amforth-6.5/avr8/devices/atmega644/device.py
+++ /dev/null
@@ -1,355 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega644
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega644/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega644/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega644/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega644/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644a/atmega644a.frt b/amforth-6.5/avr8/devices/atmega644a/atmega644a.frt
deleted file mode 100644
index ad7a908..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/atmega644a.frt
+++ /dev/null
@@ -1,346 +0,0 @@
-\ Partname: ATmega644A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega644a/device.asm b/amforth-6.5/avr8/devices/atmega644a/device.asm
deleted file mode 100644
index e07e06e..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega644A
-; generated automatically, do not edit
-
-.nolist
- .include "m644Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega644A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644a/device.inc b/amforth-6.5/avr8/devices/atmega644a/device.inc
deleted file mode 100644
index c267ebf..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega644A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega644a/device.py b/amforth-6.5/avr8/devices/atmega644a/device.py
deleted file mode 100644
index 3d2079d..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/device.py
+++ /dev/null
@@ -1,386 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega644A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega644a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644a/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega644a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644p/atmega644p.frt b/amforth-6.5/avr8/devices/atmega644p/atmega644p.frt
deleted file mode 100644
index 8bc29af..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/atmega644p.frt
+++ /dev/null
@@ -1,346 +0,0 @@
-\ Partname: ATmega644P
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega644p/device.asm b/amforth-6.5/avr8/devices/atmega644p/device.asm
deleted file mode 100644
index 0385a8b..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega644P
-; generated automatically, do not edit
-
-.nolist
- .include "m644Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_SPI = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega644P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644p/device.inc b/amforth-6.5/avr8/devices/atmega644p/device.inc
deleted file mode 100644
index 4a3b68a..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega644P
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega644p/device.py b/amforth-6.5/avr8/devices/atmega644p/device.py
deleted file mode 100644
index aee7322..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/device.py
+++ /dev/null
@@ -1,388 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega644P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega644p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega644p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644pa/atmega644pa.frt b/amforth-6.5/avr8/devices/atmega644pa/atmega644pa.frt
deleted file mode 100644
index 8d0ec9c..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/atmega644pa.frt
+++ /dev/null
@@ -1,346 +0,0 @@
-\ Partname: ATmega644PA
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega644pa/device.asm b/amforth-6.5/avr8/devices/atmega644pa/device.asm
deleted file mode 100644
index 7a4bc5f..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega644PA
-; generated automatically, do not edit
-
-.nolist
- .include "m644PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_SPI = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 11
- .db "ATmega644PA",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644pa/device.inc b/amforth-6.5/avr8/devices/atmega644pa/device.inc
deleted file mode 100644
index 3d60f55..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega644PA
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega644pa/device.py b/amforth-6.5/avr8/devices/atmega644pa/device.py
deleted file mode 100644
index f71af9a..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/device.py
+++ /dev/null
@@ -1,388 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega644PA
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
- 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega644pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644pa/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega644pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645/atmega645.frt b/amforth-6.5/avr8/devices/atmega645/atmega645.frt
deleted file mode 100644
index b9d8cbc..0000000
--- a/amforth-6.5/avr8/devices/atmega645/atmega645.frt
+++ /dev/null
@@ -1,285 +0,0 @@
-\ Partname: ATmega645
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega645/device.asm b/amforth-6.5/avr8/devices/atmega645/device.asm
deleted file mode 100644
index 6fa9eb6..0000000
--- a/amforth-6.5/avr8/devices/atmega645/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega645
-; generated automatically, do not edit
-
-.nolist
- .include "m645def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 9
- .db "ATmega645",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega645/device.inc b/amforth-6.5/avr8/devices/atmega645/device.inc
deleted file mode 100644
index 3882309..0000000
--- a/amforth-6.5/avr8/devices/atmega645/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega645
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega645/device.py b/amforth-6.5/avr8/devices/atmega645/device.py
deleted file mode 100644
index e890093..0000000
--- a/amforth-6.5/avr8/devices/atmega645/device.py
+++ /dev/null
@@ -1,318 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega645
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega645/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega645/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega645/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega645/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega645/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645/words/sleep.asm b/amforth-6.5/avr8/devices/atmega645/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega645/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450/atmega6450.frt b/amforth-6.5/avr8/devices/atmega6450/atmega6450.frt
deleted file mode 100644
index 98e3bbb..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/atmega6450.frt
+++ /dev/null
@@ -1,298 +0,0 @@
-\ Partname: ATmega6450
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6450/device.asm b/amforth-6.5/avr8/devices/atmega6450/device.asm
deleted file mode 100644
index 39d52bd..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega6450
-; generated automatically, do not edit
-
-.nolist
- .include "m6450def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 10
- .db "ATmega6450"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6450/device.inc b/amforth-6.5/avr8/devices/atmega6450/device.inc
deleted file mode 100644
index 8b44ba6..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega6450
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega6450/device.py b/amforth-6.5/avr8/devices/atmega6450/device.py
deleted file mode 100644
index b1ca149..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/device.py
+++ /dev/null
@@ -1,333 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega6450
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'NOT_USEDAddr' : '#44', # RESERVED
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega6450/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6450/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega6450/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450a/atmega6450a.frt b/amforth-6.5/avr8/devices/atmega6450a/atmega6450a.frt
deleted file mode 100644
index 23b981b..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/atmega6450a.frt
+++ /dev/null
@@ -1,298 +0,0 @@
-\ Partname: ATmega6450A
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6450a/device.asm b/amforth-6.5/avr8/devices/atmega6450a/device.asm
deleted file mode 100644
index 5d2225b..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega6450A
-; generated automatically, do not edit
-
-.nolist
- .include "m6450Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega6450A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6450a/device.inc b/amforth-6.5/avr8/devices/atmega6450a/device.inc
deleted file mode 100644
index b71ce1b..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega6450A
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega6450a/device.py b/amforth-6.5/avr8/devices/atmega6450a/device.py
deleted file mode 100644
index bea6252..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/device.py
+++ /dev/null
@@ -1,333 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega6450A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'NOT_USEDAddr' : '#44', # RESERVED
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega6450a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6450a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega6450a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt b/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt
deleted file mode 100644
index 6051089..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt
+++ /dev/null
@@ -1,298 +0,0 @@
-\ Partname: ATmega6450P
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant NOT_USEDAddr \ RESERVED
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.asm b/amforth-6.5/avr8/devices/atmega6450p/device.asm
deleted file mode 100644
index 235783e..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega6450P
-; generated automatically, do not edit
-
-.nolist
- .include "m6450Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; RESERVED
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega6450P",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.inc b/amforth-6.5/avr8/devices/atmega6450p/device.inc
deleted file mode 100644
index 1d056aa..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/device.inc
+++ /dev/null
@@ -1,1152 +0,0 @@
-; Partname: ATmega6450P
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.py b/amforth-6.5/avr8/devices/atmega6450p/device.py
deleted file mode 100644
index d034f86..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/device.py
+++ /dev/null
@@ -1,333 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega6450P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'NOT_USEDAddr' : '#44', # RESERVED
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645a/atmega645a.frt b/amforth-6.5/avr8/devices/atmega645a/atmega645a.frt
deleted file mode 100644
index de54e91..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/atmega645a.frt
+++ /dev/null
@@ -1,285 +0,0 @@
-\ Partname: ATmega645A
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega645a/device.asm b/amforth-6.5/avr8/devices/atmega645a/device.asm
deleted file mode 100644
index 687babf..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega645A
-; generated automatically, do not edit
-
-.nolist
- .include "m645Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 10
- .db "ATmega645A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega645a/device.inc b/amforth-6.5/avr8/devices/atmega645a/device.inc
deleted file mode 100644
index f6c0423..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega645A
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega645a/device.py b/amforth-6.5/avr8/devices/atmega645a/device.py
deleted file mode 100644
index e1ba808..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/device.py
+++ /dev/null
@@ -1,318 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega645A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega645a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega645a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega645a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega645a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega645a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645p/atmega645p.frt b/amforth-6.5/avr8/devices/atmega645p/atmega645p.frt
deleted file mode 100644
index bfffd11..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/atmega645p.frt
+++ /dev/null
@@ -1,285 +0,0 @@
-\ Partname: ATmega645P
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega645p/device.asm b/amforth-6.5/avr8/devices/atmega645p/device.asm
deleted file mode 100644
index 781e099..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/device.asm
+++ /dev/null
@@ -1,106 +0,0 @@
-; Partname: ATmega645P
-; generated automatically, do not edit
-
-.nolist
- .include "m645Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_USART0 = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 22
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 22
-mcu_name:
- .dw 10
- .db "ATmega645P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega645p/device.inc b/amforth-6.5/avr8/devices/atmega645p/device.inc
deleted file mode 100644
index 582f84a..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/device.inc
+++ /dev/null
@@ -1,1050 +0,0 @@
-; Partname: ATmega645P
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega645p/device.py b/amforth-6.5/avr8/devices/atmega645p/device.py
deleted file mode 100644
index 30061eb..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/device.py
+++ /dev/null
@@ -1,318 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega645P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega645p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega645p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega645p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega645p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega645p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649/atmega649.frt b/amforth-6.5/avr8/devices/atmega649/atmega649.frt
deleted file mode 100644
index 56b7691..0000000
--- a/amforth-6.5/avr8/devices/atmega649/atmega649.frt
+++ /dev/null
@@ -1,318 +0,0 @@
-\ Partname: ATmega649
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega649/device.asm b/amforth-6.5/avr8/devices/atmega649/device.asm
deleted file mode 100644
index 0fb67ee..0000000
--- a/amforth-6.5/avr8/devices/atmega649/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega649
-; generated automatically, do not edit
-
-.nolist
- .include "m649def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 9
- .db "ATmega649",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega649/device.inc b/amforth-6.5/avr8/devices/atmega649/device.inc
deleted file mode 100644
index 23e59f3..0000000
--- a/amforth-6.5/avr8/devices/atmega649/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega649
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega649/device.py b/amforth-6.5/avr8/devices/atmega649/device.py
deleted file mode 100644
index 07a25b0..0000000
--- a/amforth-6.5/avr8/devices/atmega649/device.py
+++ /dev/null
@@ -1,352 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega649
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega649/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega649/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega649/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega649/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega649/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649/words/sleep.asm b/amforth-6.5/avr8/devices/atmega649/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega649/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490/atmega6490.frt b/amforth-6.5/avr8/devices/atmega6490/atmega6490.frt
deleted file mode 100644
index 33e440a..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/atmega6490.frt
+++ /dev/null
@@ -1,334 +0,0 @@
-\ Partname: ATmega6490
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6490/device.asm b/amforth-6.5/avr8/devices/atmega6490/device.asm
deleted file mode 100644
index 02a743f..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega6490
-; generated automatically, do not edit
-
-.nolist
- .include "m6490def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 10
- .db "ATmega6490"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6490/device.inc b/amforth-6.5/avr8/devices/atmega6490/device.inc
deleted file mode 100644
index 896b218..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega6490
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega6490/device.py b/amforth-6.5/avr8/devices/atmega6490/device.py
deleted file mode 100644
index ba47702..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/device.py
+++ /dev/null
@@ -1,370 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega6490
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega6490/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6490/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6490/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6490/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega6490/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490a/atmega6490a.frt b/amforth-6.5/avr8/devices/atmega6490a/atmega6490a.frt
deleted file mode 100644
index 6522880..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/atmega6490a.frt
+++ /dev/null
@@ -1,334 +0,0 @@
-\ Partname: ATmega6490A
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6490a/device.asm b/amforth-6.5/avr8/devices/atmega6490a/device.asm
deleted file mode 100644
index 9ef601a..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega6490A
-; generated automatically, do not edit
-
-.nolist
- .include "m6490Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega6490A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6490a/device.inc b/amforth-6.5/avr8/devices/atmega6490a/device.inc
deleted file mode 100644
index 0081bb6..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega6490A
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega6490a/device.py b/amforth-6.5/avr8/devices/atmega6490a/device.py
deleted file mode 100644
index de70d9f..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/device.py
+++ /dev/null
@@ -1,370 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega6490A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega6490a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6490a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6490a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6490a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega6490a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490p/atmega6490p.frt b/amforth-6.5/avr8/devices/atmega6490p/atmega6490p.frt
deleted file mode 100644
index 948580b..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/atmega6490p.frt
+++ /dev/null
@@ -1,334 +0,0 @@
-\ Partname: ATmega6490P
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ PORTH
-&218 constant PORTH \ PORT H Data Register
-&217 constant DDRH \ PORT H Data Direction Register
-&216 constant PINH \ PORT H Input Pins
-\ PORTJ
-&221 constant PORTJ \ PORT J Data Register
-&220 constant DDRJ \ PORT J Data Direction Register
-&219 constant PINJ \ PORT J Input Pins
-\ LCD
-&255 constant LCDDR19 \ LCD Data Register 19
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&250 constant LCDDR14 \ LCD Data Register 14
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&245 constant LCDDR9 \ LCD Data Register 9
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&240 constant LCDDR4 \ LCD Data Register 4
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control and Status Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&115 constant PCMSK3 \ Pin Change Mask Register 3
-&109 constant PCMSK2 \ Pin Change Mask Register 2
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART__RXAddr \ USART, Rx Complete
-&28 constant USART__UDREAddr \ USART Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
-&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6490p/device.asm b/amforth-6.5/avr8/devices/atmega6490p/device.asm
deleted file mode 100644
index 3f5cb38..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/device.asm
+++ /dev/null
@@ -1,115 +0,0 @@
-; Partname: ATmega6490P
-; generated automatically, do not edit
-
-.nolist
- .include "m6490Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_PORTH = 0
-.set WANT_PORTJ = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART, Rx Complete
-.org 28
- rcall isr ; USART Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.org 46
- rcall isr ; Pin Change Interrupt Request 2
-.org 48
- rcall isr ; Pin Change Interrupt Request 3
-.equ INTVECTORS = 25
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega6490P",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6490p/device.inc b/amforth-6.5/avr8/devices/atmega6490p/device.inc
deleted file mode 100644
index 9b78b98..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/device.inc
+++ /dev/null
@@ -1,1443 +0,0 @@
-; Partname: ATmega6490P
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_PORTH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Register
-VE_PORTH:
- .dw $ff05
- .db "PORTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTH
-XT_PORTH:
- .dw PFA_DOVARIABLE
-PFA_PORTH:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Data Direction Register
-VE_DDRH:
- .dw $ff04
- .db "DDRH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRH
-XT_DDRH:
- .dw PFA_DOVARIABLE
-PFA_DDRH:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; PORT H Input Pins
-VE_PINH:
- .dw $ff04
- .db "PINH"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINH
-XT_PINH:
- .dw PFA_DOVARIABLE
-PFA_PINH:
- .dw 216
-
-.endif
-.if WANT_PORTJ == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Register
-VE_PORTJ:
- .dw $ff05
- .db "PORTJ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTJ
-XT_PORTJ:
- .dw PFA_DOVARIABLE
-PFA_PORTJ:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Data Direction Register
-VE_DDRJ:
- .dw $ff04
- .db "DDRJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRJ
-XT_DDRJ:
- .dw PFA_DOVARIABLE
-PFA_DDRJ:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; PORT J Input Pins
-VE_PINJ:
- .dw $ff04
- .db "PINJ"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINJ
-XT_PINJ:
- .dw PFA_DOVARIABLE
-PFA_PINJ:
- .dw 219
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 19
-VE_LCDDR19:
- .dw $ff07
- .db "LCDDR19",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR19
-XT_LCDDR19:
- .dw PFA_DOVARIABLE
-PFA_LCDDR19:
- .dw 255
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 14
-VE_LCDDR14:
- .dw $ff07
- .db "LCDDR14",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR14
-XT_LCDDR14:
- .dw PFA_DOVARIABLE
-PFA_LCDDR14:
- .dw 250
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 9
-VE_LCDDR9:
- .dw $ff06
- .db "LCDDR9"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR9
-XT_LCDDR9:
- .dw PFA_DOVARIABLE
-PFA_LCDDR9:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 4
-VE_LCDDR4:
- .dw $ff06
- .db "LCDDR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR4
-XT_LCDDR4:
- .dw PFA_DOVARIABLE
-PFA_LCDDR4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega6490p/device.py b/amforth-6.5/avr8/devices/atmega6490p/device.py
deleted file mode 100644
index 8adff72..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/device.py
+++ /dev/null
@@ -1,370 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega6490P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#26', # USART, Rx Complete
- 'USART_UDREAddr' : '#28', # USART Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
- 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module PORTH
- 'PORTH' : '$da', # PORT H Data Register
- 'DDRH' : '$d9', # PORT H Data Direction Register
- 'PINH' : '$d8', # PORT H Input Pins
-
-# Module PORTJ
- 'PORTJ' : '$dd', # PORT J Data Register
- 'DDRJ' : '$dc', # PORT J Data Direction Register
- 'PINJ' : '$db', # PORT J Input Pins
-
-# Module LCD
- 'LCDDR19' : '$ff', # LCD Data Register 19
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR14' : '$fa', # LCD Data Register 14
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR9' : '$f5', # LCD Data Register 9
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR4' : '$f0', # LCD Data Register 4
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control and Status Registe
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega6490p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6490p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6490p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6490p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega6490p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649a/atmega649a.frt b/amforth-6.5/avr8/devices/atmega649a/atmega649a.frt
deleted file mode 100644
index 43d2d0c..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/atmega649a.frt
+++ /dev/null
@@ -1,318 +0,0 @@
-\ Partname: ATmega649A
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega649a/device.asm b/amforth-6.5/avr8/devices/atmega649a/device.asm
deleted file mode 100644
index dffd7fb..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega649A
-; generated automatically, do not edit
-
-.nolist
- .include "m649Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 10
- .db "ATmega649A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega649a/device.inc b/amforth-6.5/avr8/devices/atmega649a/device.inc
deleted file mode 100644
index dfebd4b..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega649A
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega649a/device.py b/amforth-6.5/avr8/devices/atmega649a/device.py
deleted file mode 100644
index 117cda4..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/device.py
+++ /dev/null
@@ -1,352 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega649A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega649a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega649a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega649a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega649a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega649a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649p/atmega649p.frt b/amforth-6.5/avr8/devices/atmega649p/atmega649p.frt
deleted file mode 100644
index 219388d..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/atmega649p.frt
+++ /dev/null
@@ -1,318 +0,0 @@
-\ Partname: ATmega649P
-\ generated automatically
-
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ USI
-&186 constant USIDR \ USI Data Register
-&185 constant USISR \ USI Status Register
- $80 constant USISR_USISIF \ Start Condition Interrupt Flag
- $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
- $20 constant USISR_USIPF \ Stop Condition Flag
- $10 constant USISR_USIDC \ Data Output Collision
- $0F constant USISR_USICNT \ USI Counter Value Bits
-&184 constant USICR \ USI Control Register
- $80 constant USICR_USISIE \ Start Condition Interrupt Enable
- $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
- $30 constant USICR_USIWM \ USI Wire Mode Bits
- $0C constant USICR_USICS \ USI Clock Source Select Bits
- $02 constant USICR_USICLK \ Clock Strobe
- $01 constant USICR_USITC \ Toggle Clock Port Pin
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&100 constant PRR \ Power Reduction Register
- $10 constant PRR_PRLCD \ Power Reduction LCD
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
-&74 constant GPIOR1 \ General Purpose IO Register 1
-&62 constant GPIOR0 \ General Purpose IO Register 0
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-\ LCD
-&254 constant LCDDR18 \ LCD Data Register 18
-&253 constant LCDDR17 \ LCD Data Register 17
-&252 constant LCDDR16 \ LCD Data Register 16
-&251 constant LCDDR15 \ LCD Data Register 15
-&249 constant LCDDR13 \ LCD Data Register 13
-&248 constant LCDDR12 \ LCD Data Register 12
-&247 constant LCDDR11 \ LCD Data Register 11
-&246 constant LCDDR10 \ LCD Data Register 10
-&244 constant LCDDR8 \ LCD Data Register 8
-&243 constant LCDDR7 \ LCD Data Register 7
-&242 constant LCDDR6 \ LCD Data Register 6
-&241 constant LCDDR5 \ LCD Data Register 5
-&239 constant LCDDR3 \ LCD Data Register 3
-&238 constant LCDDR2 \ LCD Data Register 2
-&237 constant LCDDR1 \ LCD Data Register 1
-&236 constant LCDDR0 \ LCD Data Register 0
-&231 constant LCDCCR \ LCD Contrast Control Register
-&230 constant LCDFRR \ LCD Frame Rate Register
- $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
- $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
-&229 constant LCDCRB \ LCD Control and Status Register B
- $80 constant LCDCRB_LCDCS \ LCD CLock Select
- $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
- $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
- $0F constant LCDCRB_LCDPM \ LCD Port Masks
-&228 constant LCDCRA \ LCD Control Register A
- $80 constant LCDCRA_LCDEN \ LCD Enable
- $40 constant LCDCRA_LCDAB \ LCD A or B waveform
- $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
- $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
- $01 constant LCDCRA_LCDBL \ LCD Blanking
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
- $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
-&61 constant EIMSK \ External Interrupt Mask Register
- $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
- $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
- $01 constant EIFR_INTF0 \ External Interrupt Flag 0
-&108 constant PCMSK1 \ Pin Change Mask Register 1
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ PORTE
-&46 constant PORTE \ Data Register, Port E
-&45 constant DDRE \ Data Direction Register, Port E
-&44 constant PINE \ Input Pins, Port E
-\ PORTF
-&49 constant PORTF \ Data Register, Port F
-&48 constant DDRF \ Data Direction Register, Port F
-&47 constant PINF \ Input Pins, Port F
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins
-\ TIMER_COUNTER_0
-&68 constant TCCR0A \ Timer/Counter0 Control Register
- $80 constant TCCR0A_FOC0A \ Force Output Compare
- $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0A_COM0A \ Compare Match Output Modes
- $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0A_CS0 \ Clock Selects
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TIMER_COUNTER_2
-&176 constant TCCR2A \ Timer/Counter2 Control Register
- $80 constant TCCR2A_FOC2A \ Force Output Compare A
- $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
- $30 constant TCCR2A_COM2A \ Compare Output Mode bits
- $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2A_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register
-&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
- $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&182 constant ASSR \ Asynchronous Status Register
- $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
- $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
- $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&26 constant USART0__RXAddr \ USART0, Rx Complete
-&28 constant USART0__UDREAddr \ USART0 Data register Empty
-&30 constant USART0__TXAddr \ USART0, Tx Complete
-&32 constant USI_STARTAddr \ USI Start Condition
-&34 constant USI_OVERFLOWAddr \ USI Overflow
-&36 constant ANALOG_COMPAddr \ Analog Comparator
-&38 constant ADCAddr \ ADC Conversion Complete
-&40 constant EE_READYAddr \ EEPROM Ready
-&42 constant SPM_READYAddr \ Store Program Memory Read
-&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega649p/device.asm b/amforth-6.5/avr8/devices/atmega649p/device.asm
deleted file mode 100644
index 7abac95..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/device.asm
+++ /dev/null
@@ -1,109 +0,0 @@
-; Partname: ATmega649P
-; generated automatically, do not edit
-
-.nolist
- .include "m649Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_USI = 0
-.set WANT_USART0 = 0
-.set WANT_CPU = 0
-.set WANT_JTAG = 0
-.set WANT_LCD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_BOOT_LOAD = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 6
- rcall isr ; Pin Change Interrupt Request 1
-.org 8
- rcall isr ; Timer/Counter2 Compare Match
-.org 10
- rcall isr ; Timer/Counter2 Overflow
-.org 12
- rcall isr ; Timer/Counter1 Capture Event
-.org 14
- rcall isr ; Timer/Counter1 Compare Match A
-.org 16
- rcall isr ; Timer/Counter Compare Match B
-.org 18
- rcall isr ; Timer/Counter1 Overflow
-.org 20
- rcall isr ; Timer/Counter0 Compare Match
-.org 22
- rcall isr ; Timer/Counter0 Overflow
-.org 24
- rcall isr ; SPI Serial Transfer Complete
-.org 26
- rcall isr ; USART0, Rx Complete
-.org 28
- rcall isr ; USART0 Data register Empty
-.org 30
- rcall isr ; USART0, Tx Complete
-.org 32
- rcall isr ; USI Start Condition
-.org 34
- rcall isr ; USI Overflow
-.org 36
- rcall isr ; Analog Comparator
-.org 38
- rcall isr ; ADC Conversion Complete
-.org 40
- rcall isr ; EEPROM Ready
-.org 42
- rcall isr ; Store Program Memory Read
-.org 44
- rcall isr ; LCD Start of Frame
-.equ INTVECTORS = 23
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 23
-mcu_name:
- .dw 10
- .db "ATmega649P"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega649p/device.inc b/amforth-6.5/avr8/devices/atmega649p/device.inc
deleted file mode 100644
index 630f41a..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/device.inc
+++ /dev/null
@@ -1,1293 +0,0 @@
-; Partname: ATmega649P
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_USI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USI Data Register
-VE_USIDR:
- .dw $ff05
- .db "USIDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USIDR
-XT_USIDR:
- .dw PFA_DOVARIABLE
-PFA_USIDR:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; USI Status Register
-VE_USISR:
- .dw $ff05
- .db "USISR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USISR
-XT_USISR:
- .dw PFA_DOVARIABLE
-PFA_USISR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; USI Control Register
-VE_USICR:
- .dw $ff05
- .db "USICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USICR
-XT_USICR:
- .dw PFA_DOVARIABLE
-PFA_USICR:
- .dw 184
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-
-.endif
-.if WANT_LCD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 18
-VE_LCDDR18:
- .dw $ff07
- .db "LCDDR18",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR18
-XT_LCDDR18:
- .dw PFA_DOVARIABLE
-PFA_LCDDR18:
- .dw 254
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 17
-VE_LCDDR17:
- .dw $ff07
- .db "LCDDR17",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR17
-XT_LCDDR17:
- .dw PFA_DOVARIABLE
-PFA_LCDDR17:
- .dw 253
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 16
-VE_LCDDR16:
- .dw $ff07
- .db "LCDDR16",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR16
-XT_LCDDR16:
- .dw PFA_DOVARIABLE
-PFA_LCDDR16:
- .dw 252
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 15
-VE_LCDDR15:
- .dw $ff07
- .db "LCDDR15",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR15
-XT_LCDDR15:
- .dw PFA_DOVARIABLE
-PFA_LCDDR15:
- .dw 251
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 13
-VE_LCDDR13:
- .dw $ff07
- .db "LCDDR13",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR13
-XT_LCDDR13:
- .dw PFA_DOVARIABLE
-PFA_LCDDR13:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 12
-VE_LCDDR12:
- .dw $ff07
- .db "LCDDR12",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR12
-XT_LCDDR12:
- .dw PFA_DOVARIABLE
-PFA_LCDDR12:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 11
-VE_LCDDR11:
- .dw $ff07
- .db "LCDDR11",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR11
-XT_LCDDR11:
- .dw PFA_DOVARIABLE
-PFA_LCDDR11:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 10
-VE_LCDDR10:
- .dw $ff07
- .db "LCDDR10",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR10
-XT_LCDDR10:
- .dw PFA_DOVARIABLE
-PFA_LCDDR10:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 8
-VE_LCDDR8:
- .dw $ff06
- .db "LCDDR8"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR8
-XT_LCDDR8:
- .dw PFA_DOVARIABLE
-PFA_LCDDR8:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 7
-VE_LCDDR7:
- .dw $ff06
- .db "LCDDR7"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR7
-XT_LCDDR7:
- .dw PFA_DOVARIABLE
-PFA_LCDDR7:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 6
-VE_LCDDR6:
- .dw $ff06
- .db "LCDDR6"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR6
-XT_LCDDR6:
- .dw PFA_DOVARIABLE
-PFA_LCDDR6:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 5
-VE_LCDDR5:
- .dw $ff06
- .db "LCDDR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR5
-XT_LCDDR5:
- .dw PFA_DOVARIABLE
-PFA_LCDDR5:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 3
-VE_LCDDR3:
- .dw $ff06
- .db "LCDDR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR3
-XT_LCDDR3:
- .dw PFA_DOVARIABLE
-PFA_LCDDR3:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 2
-VE_LCDDR2:
- .dw $ff06
- .db "LCDDR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR2
-XT_LCDDR2:
- .dw PFA_DOVARIABLE
-PFA_LCDDR2:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 1
-VE_LCDDR1:
- .dw $ff06
- .db "LCDDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR1
-XT_LCDDR1:
- .dw PFA_DOVARIABLE
-PFA_LCDDR1:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Data Register 0
-VE_LCDDR0:
- .dw $ff06
- .db "LCDDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDDR0
-XT_LCDDR0:
- .dw PFA_DOVARIABLE
-PFA_LCDDR0:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Contrast Control Register
-VE_LCDCCR:
- .dw $ff06
- .db "LCDCCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCCR
-XT_LCDCCR:
- .dw PFA_DOVARIABLE
-PFA_LCDCCR:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Frame Rate Register
-VE_LCDFRR:
- .dw $ff06
- .db "LCDFRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDFRR
-XT_LCDFRR:
- .dw PFA_DOVARIABLE
-PFA_LCDFRR:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control and Status Register B
-VE_LCDCRB:
- .dw $ff06
- .db "LCDCRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRB
-XT_LCDCRB:
- .dw PFA_DOVARIABLE
-PFA_LCDCRB:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; LCD Control Register A
-VE_LCDCRA:
- .dw $ff06
- .db "LCDCRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_LCDCRA
-XT_LCDCRA:
- .dw PFA_DOVARIABLE
-PFA_LCDCRA:
- .dw 228
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 96
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega649p/device.py b/amforth-6.5/avr8/devices/atmega649p/device.py
deleted file mode 100644
index d327b8a..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/device.py
+++ /dev/null
@@ -1,352 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega649P
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
- 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#26', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
- 'USART0_TXAddr' : '#30', # USART0, Tx Complete
- 'USI_STARTAddr' : '#32', # USI Start Condition
- 'USI_OVERFLOWAddr' : '#34', # USI Overflow
- 'ANALOG_COMPAddr' : '#36', # Analog Comparator
- 'ADCAddr' : '#38', # ADC Conversion Complete
- 'EE_READYAddr' : '#40', # EEPROM Ready
- 'SPM_READYAddr' : '#42', # Store Program Memory Read
- 'LCDAddr' : '#44', # LCD Start of Frame
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module USI
- 'USIDR' : '$ba', # USI Data Register
- 'USISR' : '$b9', # USI Status Register
- 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
- 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
- 'USISR_USIPF': '$20', # Stop Condition Flag
- 'USISR_USIDC': '$10', # Data Output Collision
- 'USISR_USICNT': '$f', # USI Counter Value Bits
- 'USICR' : '$b8', # USI Control Register
- 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
- 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
- 'USICR_USIWM': '$30', # USI Wire Mode Bits
- 'USICR_USICS': '$c', # USI Clock Source Select Bits
- 'USICR_USICLK': '$2', # Clock Strobe
- 'USICR_USITC': '$1', # Toggle Clock Port Pin
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRLCD': '$10', # Power Reduction LCD
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module LCD
- 'LCDDR18' : '$fe', # LCD Data Register 18
- 'LCDDR17' : '$fd', # LCD Data Register 17
- 'LCDDR16' : '$fc', # LCD Data Register 16
- 'LCDDR15' : '$fb', # LCD Data Register 15
- 'LCDDR13' : '$f9', # LCD Data Register 13
- 'LCDDR12' : '$f8', # LCD Data Register 12
- 'LCDDR11' : '$f7', # LCD Data Register 11
- 'LCDDR10' : '$f6', # LCD Data Register 10
- 'LCDDR8' : '$f4', # LCD Data Register 8
- 'LCDDR7' : '$f3', # LCD Data Register 7
- 'LCDDR6' : '$f2', # LCD Data Register 6
- 'LCDDR5' : '$f1', # LCD Data Register 5
- 'LCDDR3' : '$ef', # LCD Data Register 3
- 'LCDDR2' : '$ee', # LCD Data Register 2
- 'LCDDR1' : '$ed', # LCD Data Register 1
- 'LCDDR0' : '$ec', # LCD Data Register 0
- 'LCDCCR' : '$e7', # LCD Contrast Control Register
- 'LCDFRR' : '$e6', # LCD Frame Rate Register
- 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
- 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
- 'LCDCRB' : '$e5', # LCD Control and Status Registe
- 'LCDCRB_LCDCS': '$80', # LCD CLock Select
- 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
- 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
- 'LCDCRB_LCDPM': '$f', # LCD Port Masks
- 'LCDCRA' : '$e4', # LCD Control Register A
- 'LCDCRA_LCDEN': '$80', # LCD Enable
- 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
- 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
- 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
- 'LCDCRA_LCDBL': '$1', # LCD Blanking
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
- 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
- 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
- 'EIFR_INTF0': '$1', # External Interrupt Flag 0
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access Byte
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$2e', # Data Register, Port E
- 'DDRE' : '$2d', # Data Direction Register, Port
- 'PINE' : '$2c', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$31', # Data Register, Port F
- 'DDRF' : '$30', # Data Direction Register, Port
- 'PINF' : '$2f', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins
-
-# Module TIMER_COUNTER_0
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_FOC0A': '$80', # Force Output Compare
- 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
- 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0A_CS0': '$7', # Clock Selects
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Control Register
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
- 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
- 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TIMER_COUNTER_2
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_FOC2A': '$80', # Force Output Compare A
- 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
- 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2A_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
- 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
- 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
- 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
- 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
- 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
-
-# Module WATCHDOG
- 'WDTCR' : '$60', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega649p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega649p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega649p/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega649p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega649p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64a/atmega64a.frt b/amforth-6.5/avr8/devices/atmega64a/atmega64a.frt
deleted file mode 100644
index 360771b..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/atmega64a.frt
+++ /dev/null
@@ -1,331 +0,0 @@
-\ Partname: ATmega64A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&64 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&36 constant ADC \ ADC Data Register Bytes
-&38 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&142 constant ADCSRB \ The ADC Control and Status register B
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ TWI
-&112 constant TWBR \ TWI Bit Rate register
-&116 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&113 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&115 constant TWDR \ TWI Data register
-&114 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART0
-&44 constant UDR0 \ USART I/O Data Register
-&43 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&42 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&149 constant UCSR0C \ USART Control and Status Register C
- $40 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
-&41 constant UBRR0L \ USART Baud Rate Register Low Byte
-\ USART1
-&156 constant UDR1 \ USART I/O Data Register
-&155 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&154 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&157 constant UCSR1C \ USART Control and Status Register C
- $40 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
-&153 constant UBRR1L \ USART Baud Rate Register Low Byte
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SRE \ External SRAM Enable
- $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
- $20 constant MCUCR_SE \ Sleep Enable
- $18 constant MCUCR_SM \ Sleep Mode Select
- $04 constant MCUCR_SM2 \ Sleep Mode Select
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUCSR \ MCU Control And Status Register
- $80 constant MCUCSR_JTD \ JTAG Interface Disable
- $10 constant MCUCSR_JTRF \ JTAG Reset Flag
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&109 constant XMCRA \ External Memory Control Register A
- $70 constant XMCRA_SRL \ Wait state page limit
- $0C constant XMCRA_SRW0 \ Wait state select bit lower page
- $02 constant XMCRA_SRW11 \ Wait state select bit upper page
-&108 constant XMCRB \ External Memory Control Register B
- $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
- $07 constant XMCRB_XMM \ External Memory High Mask
-&111 constant OSCCAL \ Oscillator Calibration Value
-&92 constant XDIV \ XTAL Divide Control Register
- $80 constant XDIV_XDIVEN \ XTAL Divide Enable
- $7F constant XDIV_XDIV \ XTAl Divide Select Bits
-\ BOOT_LOAD
-&104 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ JTAG
-&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
- $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
-\ MISC
-\ EXTERNAL_INTERRUPT
-&106 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&90 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&89 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&88 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-\ EEPROM
-&62 constant EEAR \ EEPROM Read/Write Access Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ PORTE
-&35 constant PORTE \ Data Register, Port E
-&34 constant DDRE \ Data Direction Register, Port E
-&33 constant PINE \ Input Pins, Port E
-\ PORTF
-&98 constant PORTF \ Data Register, Port F
-&97 constant DDRF \ Data Direction Register, Port F
-&32 constant PINF \ Input Pins, Port F
-\ PORTG
-&101 constant PORTG \ Data Register, Port G
-&100 constant DDRG \ Data Direction Register, Port G
-&99 constant PING \ Input Pins, Port G
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&81 constant OCR0 \ Output Compare Register
-&80 constant ASSR \ Asynchronus Status Register
- $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
- $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
- $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
- $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
-&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&86 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_1
-&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
- $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
-&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
- $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&122 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
- $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
- $30 constant TCCR2_COM2 \ Compare Match Output Mode
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select
-&68 constant TCNT2 \ Timer/Counter Register
-&67 constant OCR2 \ Output Compare Register
-\ TIMER_COUNTER_3
-&139 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
- $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
- $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
-&138 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Clock Select3 bits
-&140 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
- $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
-&136 constant TCNT3 \ Timer/Counter3 Bytes
-&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
-&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART0__RXAddr \ USART0, Rx Complete
-&38 constant USART0__UDREAddr \ USART0 Data Register Empty
-&40 constant USART0__TXAddr \ USART0, Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&60 constant USART1__RXAddr \ USART1, Rx Complete
-&62 constant USART1__UDREAddr \ USART1, Data Register Empty
-&64 constant USART1__TXAddr \ USART1, Tx Complete
-&66 constant TWIAddr \ 2-wire Serial Interface
-&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64a/device.asm b/amforth-6.5/avr8/devices/atmega64a/device.asm
deleted file mode 100644
index ac325a3..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/device.asm
+++ /dev/null
@@ -1,135 +0,0 @@
-; Partname: ATmega64A
-; generated automatically, do not edit
-
-.nolist
- .include "m64Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_JTAG = 0
-.set WANT_MISC = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_WATCHDOG = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Timer/Counter2 Compare Match
-.org 20
- rcall isr ; Timer/Counter2 Overflow
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter Compare Match B
-.org 28
- rcall isr ; Timer/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match
-.org 32
- rcall isr ; Timer/Counter0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART0, Rx Complete
-.org 38
- rcall isr ; USART0 Data Register Empty
-.org 40
- rcall isr ; USART0, Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Timer/Counter1 Compare Match C
-.org 50
- rcall isr ; Timer/Counter3 Capture Event
-.org 52
- rcall isr ; Timer/Counter3 Compare Match A
-.org 54
- rcall isr ; Timer/Counter3 Compare Match B
-.org 56
- rcall isr ; Timer/Counter3 Compare Match C
-.org 58
- rcall isr ; Timer/Counter3 Overflow
-.org 60
- rcall isr ; USART1, Rx Complete
-.org 62
- rcall isr ; USART1, Data Register Empty
-.org 64
- rcall isr ; USART1, Tx Complete
-.org 66
- rcall isr ; 2-wire Serial Interface
-.org 68
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 35
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 35
-mcu_name:
- .dw 9
- .db "ATmega64A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64a/device.inc b/amforth-6.5/avr8/devices/atmega64a/device.inc
deleted file mode 100644
index c18844e..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/device.inc
+++ /dev/null
@@ -1,1179 +0,0 @@
-; Partname: ATmega64A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 142
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 116
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 114
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR0H:
- .dw $ff06
- .db "UBRR0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0H
-XT_UBRR0H:
- .dw PFA_DOVARIABLE
-PFA_UBRR0H:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR0L:
- .dw $ff06
- .db "UBRR0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0L
-XT_UBRR0L:
- .dw PFA_DOVARIABLE
-PFA_UBRR0L:
- .dw 41
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 155
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 157
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRR1H:
- .dw $ff06
- .db "UBRR1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1H
-XT_UBRR1H:
- .dw PFA_DOVARIABLE
-PFA_UBRR1H:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRR1L:
- .dw $ff06
- .db "UBRR1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1L
-XT_UBRR1L:
- .dw PFA_DOVARIABLE
-PFA_UBRR1L:
- .dw 153
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register A
-VE_XMCRA:
- .dw $ff05
- .db "XMCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRA
-XT_XMCRA:
- .dw PFA_DOVARIABLE
-PFA_XMCRA:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; External Memory Control Register B
-VE_XMCRB:
- .dw $ff05
- .db "XMCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XMCRB
-XT_XMCRB:
- .dw PFA_DOVARIABLE
-PFA_XMCRB:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; XTAL Divide Control Register
-VE_XDIV:
- .dw $ff04
- .db "XDIV"
- .dw VE_HEAD
- .set VE_HEAD=VE_XDIV
-XT_XDIV:
- .dw PFA_DOVARIABLE
-PFA_XDIV:
- .dw 92
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 104
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 66
-
-.endif
-.if WANT_MISC == 1
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 88
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 33
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port F
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 98
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port F
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 32
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port G
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port G
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port G
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 99
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronus Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 86
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Mask Register
-VE_ETIMSK:
- .dw $ff06
- .db "ETIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIMSK
-XT_ETIMSK:
- .dw PFA_DOVARIABLE
-PFA_ETIMSK:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Timer/Counter Interrupt Flag register
-VE_ETIFR:
- .dw $ff05
- .db "ETIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ETIFR
-XT_ETIFR:
- .dw PFA_DOVARIABLE
-PFA_ETIFR:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 139
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output compare Register C Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 128
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega64a/device.py b/amforth-6.5/avr8/devices/atmega64a/device.py
deleted file mode 100644
index b7ab9c9..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/device.py
+++ /dev/null
@@ -1,405 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega64A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
- 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
- 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
- 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#36', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
- 'USART0_TXAddr' : '#40', # USART0, Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
- 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#60', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
- 'USART1_TXAddr' : '#64', # USART1, Tx Complete
- 'TWIAddr' : '#66', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#68', # Store Program Memory Read
-
-# Module ANALOG_COMPARATOR
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'ACSR' : '$28', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
-
-# Module AD_CONVERTER
- 'ADMUX' : '$27', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$24', # ADC Data Register Bytes
- 'ADCSRA' : '$26', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$8e', # The ADC Control and Status reg
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
-
-# Module SPI
- 'SPDR' : '$2f', # SPI Data Register
- 'SPSR' : '$2e', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$2d', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module TWI
- 'TWBR' : '$70', # TWI Bit Rate register
- 'TWCR' : '$74', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$71', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$73', # TWI Data register
- 'TWAR' : '$72', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART0
- 'UDR0' : '$2c', # USART I/O Data Register
- 'UCSR0A' : '$2b', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$2a', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$95', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$40', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0H' : '$90', # USART Baud Rate Register Hight
- 'UBRR0L' : '$29', # USART Baud Rate Register Low B
-
-# Module USART1
- 'UDR1' : '$9c', # USART I/O Data Register
- 'UCSR1A' : '$9b', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$9a', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$9d', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$40', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1H' : '$98', # USART Baud Rate Register Hight
- 'UBRR1L' : '$99', # USART Baud Rate Register Low B
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SRE': '$80', # External SRAM Enable
- 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
- 'MCUCR_SE': '$20', # Sleep Enable
- 'MCUCR_SM': '$18', # Sleep Mode Select
- 'MCUCR_SM2': '$4', # Sleep Mode Select
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUCSR_EXTRF': '$2', # External Reset Flag
- 'MCUCSR_PORF': '$1', # Power-on reset flag
- 'XMCRA' : '$6d', # External Memory Control Regist
- 'XMCRA_SRL': '$70', # Wait state page limit
- 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
- 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
- 'XMCRB' : '$6c', # External Memory Control Regist
- 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
- 'XMCRB_XMM': '$7', # External Memory High Mask
- 'OSCCAL' : '$6f', # Oscillator Calibration Value
- 'XDIV' : '$5c', # XTAL Divide Control Register
- 'XDIV_XDIVEN': '$80', # XTAL Divide Enable
- 'XDIV_XDIV': '$7f', # XTAl Divide Select Bits
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$68', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module JTAG
- 'OCDR' : '$42', # On-Chip Debug Related Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
- 'MCUCSR' : '$54', # MCU Control And Status Registe
- 'MCUCSR_JTD': '$80', # JTAG Interface Disable
- 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module MISC
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
- 'SFIOR_PUD': '$4', # Pull Up Disable
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
- 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$6a', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EICRB' : '$5a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
- 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
- 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
- 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
- 'EIMSK' : '$59', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
- 'EIFR' : '$58', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
- 'EEDR' : '$3d', # EEPROM Data Register
- 'EECR' : '$3c', # EEPROM Control Register
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module PORTA
- 'PORTA' : '$3b', # Port A Data Register
- 'DDRA' : '$3a', # Port A Data Direction Register
- 'PINA' : '$39', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$38', # Port B Data Register
- 'DDRB' : '$37', # Port B Data Direction Register
- 'PINB' : '$36', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$35', # Port C Data Register
- 'DDRC' : '$34', # Port C Data Direction Register
- 'PINC' : '$33', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$32', # Port D Data Register
- 'DDRD' : '$31', # Port D Data Direction Register
- 'PIND' : '$30', # Port D Input Pins
-
-# Module PORTE
- 'PORTE' : '$23', # Data Register, Port E
- 'DDRE' : '$22', # Data Direction Register, Port
- 'PINE' : '$21', # Input Pins, Port E
-
-# Module PORTF
- 'PORTF' : '$62', # Data Register, Port F
- 'DDRF' : '$61', # Data Direction Register, Port
- 'PINF' : '$20', # Input Pins, Port F
-
-# Module PORTG
- 'PORTG' : '$65', # Data Register, Port G
- 'DDRG' : '$64', # Data Direction Register, Port
- 'PING' : '$63', # Input Pins, Port G
-
-# Module TIMER_COUNTER_0
- 'TCCR0' : '$53', # Timer/Counter Control Register
- 'TCCR0_FOC0': '$80', # Force Output Compare
- 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
- 'TCCR0_COM0': '$30', # Compare Match Output Modes
- 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
- 'TCCR0_CS0': '$7', # Clock Selects
- 'TCNT0' : '$52', # Timer/Counter Register
- 'OCR0' : '$51', # Output Compare Register
- 'ASSR' : '$50', # Asynchronus Status Register
- 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
- 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
- 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
- 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
- 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_OCF0': '$2', # Output Compare Flag 0
- 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
-
-# Module TIMER_COUNTER_1
- 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
- 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
- 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
- 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
- 'TIFR_ICF1': '$20', # Input Capture Flag 1
- 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
- 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
- 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
- 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
- 'TCNT1' : '$4c', # Timer/Counter1 Bytes
- 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
- 'OCR1B' : '$48', # Timer/Counter1 Output Compare
- 'OCR1C' : '$78', # Timer/Counter1 Output Compare
- 'ICR1' : '$46', # Timer/Counter1 Input Capture R
-
-# Module TIMER_COUNTER_2
- 'TCCR2' : '$45', # Timer/Counter Control Register
- 'TCCR2_FOC2': '$80', # Force Output Compare
- 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
- 'TCCR2_COM2': '$30', # Compare Match Output Mode
- 'TCCR2_WGM21': '$8', # Waveform Generation Mode
- 'TCCR2_CS2': '$7', # Clock Select
- 'TCNT2' : '$44', # Timer/Counter Register
- 'OCR2' : '$43', # Output Compare Register
- 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
- 'TIFR_OCF2': '$80', # Output Compare Flag 2
- 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
- 'TIMSK' : '$57', #
- 'TIMSK_OCIE2': '$80', #
- 'TIMSK_TOIE2': '$40', #
-
-# Module TIMER_COUNTER_3
- 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
- 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
- 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
- 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
- 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
- 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
- 'ETIFR' : '$7c', # Extended Timer/Counter Interru
- 'ETIFR_ICF3': '$20', # Input Capture Flag 1
- 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
- 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
- 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
- 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
- 'SFIOR' : '$40', # Special Function IO Register
- 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
- 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
- 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
- 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
- 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
- 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select3 bits
- 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
- 'TCNT3' : '$88', # Timer/Counter3 Bytes
- 'OCR3A' : '$86', # Timer/Counter3 Output Compare
- 'OCR3B' : '$84', # Timer/Counter3 Output Compare
- 'OCR3C' : '$82', # Timer/Counter3 Output compare
- 'ICR3' : '$80', # Timer/Counter3 Input Capture R
-
-# Module WATCHDOG
- 'WDTCR' : '$41', # Watchdog Timer Control Registe
- 'WDTCR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCR_WDE': '$8', # Watch Dog Enable
- 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega64a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64a/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega64a/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64c1/atmega64c1.frt b/amforth-6.5/avr8/devices/atmega64c1/atmega64c1.frt
deleted file mode 100644
index e309d02..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/atmega64c1.frt
+++ /dev/null
@@ -1,454 +0,0 @@
-\ Partname: ATmega64C1
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVFG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register Flags
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
- $08 constant CANGIT_SERG \ Stuff Error General Flag
- $04 constant CANGIT_CERG \ CRC Error General Flag
- $02 constant CANGIT_FERG \ Form Error General Flag
- $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register 2
- $3F constant CANEN2_ENMOB \ Enable MObs
-&221 constant CANEN1 \ Enable MOb Register 1(empty)
-&222 constant CANIE2 \ Enable Interrupt MOb Register 2
- $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
-&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
- $3F constant CANSIT2_SIT \ Status of Interrupt MObs
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
-&226 constant CANBT1 \ CAN Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ CAN Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
- $0E constant CANBT2_PRS \ Propagation Time Segment bits
-&228 constant CANBT3 \ CAN Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
- $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
- $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
- $0F constant CANHPMOB_CGP \ CAN General Purpose bits
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
- $07 constant CANPAGE_INDX \ Data Buffer Index bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
- $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
- $20 constant CANSTMOB_RXOK \ Receive OK on MOb
- $10 constant CANSTMOB_BERR \ Bit Error on MOb
- $08 constant CANSTMOB_SERR \ Stuff Error on MOb
- $04 constant CANSTMOB_CERR \ CRC Error on MOb
- $02 constant CANSTMOB_FERR \ Form Error on MOb
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
- $F8 constant CANIDT4_IDT \
- $04 constant CANIDT4_RTRTAG \
- $02 constant CANIDT4_RB1TAG \
- $01 constant CANIDT4_RB0TAG \
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-\ ANALOG_COMPARATOR
-&148 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
- $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&149 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&150 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&151 constant AC3CON \ Analog Comparator 3 Control Register
- $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
- $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&146 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&145 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&144 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $40 constant PRR_PRCAN \ Power Reduction CAN
- $20 constant PRR_PRPSC \ Power Reduction PSC
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRLIN \ Power Reduction LIN UART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ISRCEN \ Current Source Enable
- $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
- $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
- $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
- $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
- $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
- $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
- $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
- $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
-&117 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
- $07 constant AMP0CSR_AMP0TS \
-&118 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
- $07 constant AMP1CSR_AMP1TS \
-&119 constant AMP2CSR \
- $80 constant AMP2CSR_AMP2EN \
- $40 constant AMP2CSR_AMP2IS \
- $30 constant AMP2CSR_AMP2G \
- $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
- $07 constant AMP2CSR_AMP2TS \
-\ LINUART
-&200 constant LINCR \ LIN Control Register
- $80 constant LINCR_LSWRES \ Software Reset
- $40 constant LINCR_LIN13 \ LIN Standard
- $30 constant LINCR_LCONF \ LIN Configuration bits
- $08 constant LINCR_LENA \ LIN or UART Enable
- $07 constant LINCR_LCMD \ LIN Command and Mode bits
-&201 constant LINSIR \ LIN Status and Interrupt Register
- $E0 constant LINSIR_LIDST \ Identifier Status bits
- $10 constant LINSIR_LBUSY \ Busy Signal
- $08 constant LINSIR_LERR \ Error Interrupt
- $04 constant LINSIR_LIDOK \ Identifier Interrupt
- $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
- $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
-&202 constant LINENIR \ LIN Enable Interrupt Register
- $08 constant LINENIR_LENERR \ Enable Error Interrupt
- $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
- $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
- $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
-&203 constant LINERR \ LIN Error Register
- $80 constant LINERR_LABORT \ Abort Flag
- $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
- $20 constant LINERR_LOVERR \ Overrun Error Flag
- $10 constant LINERR_LFERR \ Framing Error Flag
- $08 constant LINERR_LSERR \ Synchronization Error Flag
- $04 constant LINERR_LPERR \ Parity Error Flag
- $02 constant LINERR_LCERR \ Checksum Error Flag
- $01 constant LINERR_LBERR \ Bit Error Flag
-&204 constant LINBTR \ LIN Bit Timing Register
- $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
- $3F constant LINBTR_LBT \ LIN Bit Timing bits
-&205 constant LINBRRL \ LIN Baud Rate Low Register
- $FF constant LINBRRL_LDIV \
-&206 constant LINBRRH \ LIN Baud Rate High Register
- $0F constant LINBRRH_LDIV \
-&207 constant LINDLR \ LIN Data Length Register
- $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
- $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
-&208 constant LINIDR \ LIN Identifier Register
- $C0 constant LINIDR_LP \ Parity bits
- $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
-&209 constant LINSEL \ LIN Data Buffer Selection Register
- $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
- $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
-&210 constant LINDAT \ LIN Data Register
- $FF constant LINDAT_LDATA \
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK3 \ Pin Change Mask Register 3
- $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&106 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \
- $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&2 constant ANACOMP0Addr \ Analog Comparator 0
-&4 constant ANACOMP1Addr \ Analog Comparator 1
-&6 constant ANACOMP2Addr \ Analog Comparator 2
-&8 constant ANACOMP3Addr \ Analog Comparator 3
-&10 constant PSC_FAULTAddr \ PSC Fault
-&12 constant PSC_ECAddr \ PSC End of Cycle
-&14 constant INT0Addr \ External Interrupt Request 0
-&16 constant INT1Addr \ External Interrupt Request 1
-&18 constant INT2Addr \ External Interrupt Request 2
-&20 constant INT3Addr \ External Interrupt Request 3
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
-&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
-&38 constant CAN_TOVFAddr \ CAN Timer Overflow
-&40 constant LIN_TCAddr \ LIN Transfer Complete
-&42 constant LIN_ERRAddr \ LIN Error
-&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&54 constant ADCAddr \ ADC Conversion Complete
-&56 constant WDTAddr \ Watchdog Time-Out Interrupt
-&58 constant EE_READYAddr \ EEPROM Ready
-&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64c1/device.asm b/amforth-6.5/avr8/devices/atmega64c1/device.asm
deleted file mode 100644
index 41f6d97..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/device.asm
+++ /dev/null
@@ -1,119 +0,0 @@
-; Partname: ATmega64C1
-; generated automatically, do not edit
-
-.nolist
- .include "m64C1def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CAN = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_LINUART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Analog Comparator 0
-.org 4
- rcall isr ; Analog Comparator 1
-.org 6
- rcall isr ; Analog Comparator 2
-.org 8
- rcall isr ; Analog Comparator 3
-.org 10
- rcall isr ; PSC Fault
-.org 12
- rcall isr ; PSC End of Cycle
-.org 14
- rcall isr ; External Interrupt Request 0
-.org 16
- rcall isr ; External Interrupt Request 1
-.org 18
- rcall isr ; External Interrupt Request 2
-.org 20
- rcall isr ; External Interrupt Request 3
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter1 Compare Match B
-.org 28
- rcall isr ; Timer1/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match A
-.org 32
- rcall isr ; Timer/Counter0 Compare Match B
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN MOB, Burst, General Errors
-.org 38
- rcall isr ; CAN Timer Overflow
-.org 40
- rcall isr ; LIN Transfer Complete
-.org 42
- rcall isr ; LIN Error
-.org 44
- rcall isr ; Pin Change Interrupt Request 0
-.org 46
- rcall isr ; Pin Change Interrupt Request 1
-.org 48
- rcall isr ; Pin Change Interrupt Request 2
-.org 50
- rcall isr ; Pin Change Interrupt Request 3
-.org 52
- rcall isr ; SPI Serial Transfer Complete
-.org 54
- rcall isr ; ADC Conversion Complete
-.org 56
- rcall isr ; Watchdog Time-Out Interrupt
-.org 58
- rcall isr ; EEPROM Ready
-.org 60
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega64C1"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64c1/device.inc b/amforth-6.5/avr8/devices/atmega64c1/device.inc
deleted file mode 100644
index 09b0293..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/device.inc
+++ /dev/null
@@ -1,1503 +0,0 @@
-; Partname: ATmega64C1
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register Flags
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 2
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 1(empty)
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 2
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 1 (empty)
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 2
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 1 (empty)
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 3 Control Register
-VE_AC3CON:
- .dw $ff06
- .db "AC3CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3CON
-XT_AC3CON:
- .dw PFA_DOVARIABLE
-PFA_AC3CON:
- .dw 151
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 144
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP2CSR:
- .dw $ff07
- .db "AMP2CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP2CSR
-XT_AMP2CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP2CSR:
- .dw 119
-
-.endif
-.if WANT_LINUART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Control Register
-VE_LINCR:
- .dw $ff05
- .db "LINCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINCR
-XT_LINCR:
- .dw PFA_DOVARIABLE
-PFA_LINCR:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Status and Interrupt Register
-VE_LINSIR:
- .dw $ff06
- .db "LINSIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSIR
-XT_LINSIR:
- .dw PFA_DOVARIABLE
-PFA_LINSIR:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Enable Interrupt Register
-VE_LINENIR:
- .dw $ff07
- .db "LINENIR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINENIR
-XT_LINENIR:
- .dw PFA_DOVARIABLE
-PFA_LINENIR:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Error Register
-VE_LINERR:
- .dw $ff06
- .db "LINERR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINERR
-XT_LINERR:
- .dw PFA_DOVARIABLE
-PFA_LINERR:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Bit Timing Register
-VE_LINBTR:
- .dw $ff06
- .db "LINBTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBTR
-XT_LINBTR:
- .dw PFA_DOVARIABLE
-PFA_LINBTR:
- .dw 204
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate Low Register
-VE_LINBRRL:
- .dw $ff07
- .db "LINBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRL
-XT_LINBRRL:
- .dw PFA_DOVARIABLE
-PFA_LINBRRL:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate High Register
-VE_LINBRRH:
- .dw $ff07
- .db "LINBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRH
-XT_LINBRRH:
- .dw PFA_DOVARIABLE
-PFA_LINBRRH:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Length Register
-VE_LINDLR:
- .dw $ff06
- .db "LINDLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDLR
-XT_LINDLR:
- .dw PFA_DOVARIABLE
-PFA_LINDLR:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Identifier Register
-VE_LINIDR:
- .dw $ff06
- .db "LINIDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINIDR
-XT_LINIDR:
- .dw PFA_DOVARIABLE
-PFA_LINIDR:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Buffer Selection Register
-VE_LINSEL:
- .dw $ff06
- .db "LINSEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSEL
-XT_LINSEL:
- .dw PFA_DOVARIABLE
-PFA_LINSEL:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Register
-VE_LINDAT:
- .dw $ff06
- .db "LINDAT"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDAT
-XT_LINDAT:
- .dw PFA_DOVARIABLE
-PFA_LINDAT:
- .dw 210
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega64c1/device.py b/amforth-6.5/avr8/devices/atmega64c1/device.py
deleted file mode 100644
index 198a644..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/device.py
+++ /dev/null
@@ -1,477 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega64C1
-
-MCUREGS = {
-# Interrupt Vectors
- 'ANACOMP0Addr' : '#2', # Analog Comparator 0
- 'ANACOMP1Addr' : '#4', # Analog Comparator 1
- 'ANACOMP2Addr' : '#6', # Analog Comparator 2
- 'ANACOMP3Addr' : '#8', # Analog Comparator 3
- 'PSC_FAULTAddr' : '#10', # PSC Fault
- 'PSC_ECAddr' : '#12', # PSC End of Cycle
- 'INT0Addr' : '#14', # External Interrupt Request 0
- 'INT1Addr' : '#16', # External Interrupt Request 1
- 'INT2Addr' : '#18', # External Interrupt Request 2
- 'INT3Addr' : '#20', # External Interrupt Request 3
- 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
- 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
- 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
- 'LIN_TCAddr' : '#40', # LIN Transfer Complete
- 'LIN_ERRAddr' : '#42', # LIN Error
- 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
- 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
- 'ADCAddr' : '#54', # ADC Conversion Complete
- 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
- 'EE_READYAddr' : '#58', # EEPROM Ready
- 'SPM_READYAddr' : '#60', # Store Program Memory Read
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module CAN
- 'CANGCON' : '$d8', # CAN General Control Register
- 'CANGCON_ABRQ': '$80', # Abort Request
- 'CANGCON_OVRQ': '$40', # Overload Frame Request
- 'CANGCON_TTC': '$20', # Time Trigger Communication
- 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
- 'CANGCON_LISTEN': '$8', # Listening Mode
- 'CANGCON_TEST': '$4', # Test Mode
- 'CANGCON_ENASTB': '$2', # Enable / Standby
- 'CANGCON_SWRES': '$1', # Software Reset Request
- 'CANGSTA' : '$d9', # CAN General Status Register
- 'CANGSTA_OVFG': '$40', # Overload Frame Flag
- 'CANGSTA_TXBSY': '$10', # Transmitter Busy
- 'CANGSTA_RXBSY': '$8', # Receiver Busy
- 'CANGSTA_ENFG': '$4', # Enable Flag
- 'CANGSTA_BOFF': '$2', # Bus Off Mode
- 'CANGSTA_ERRP': '$1', # Error Passive Mode
- 'CANGIT' : '$da', # CAN General Interrupt Register
- 'CANGIT_CANIT': '$80', # General Interrupt Flag
- 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
- 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
- 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
- 'CANGIT_SERG': '$8', # Stuff Error General Flag
- 'CANGIT_CERG': '$4', # CRC Error General Flag
- 'CANGIT_FERG': '$2', # Form Error General Flag
- 'CANGIT_AERG': '$1', # Ackknowledgement Error General
- 'CANGIE' : '$db', # CAN General Interrupt Enable R
- 'CANGIE_ENIT': '$80', # Enable all Interrupts
- 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
- 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
- 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
- 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
- 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
- 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
- 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
- 'CANEN2' : '$dc', # Enable MOb Register 2
- 'CANEN2_ENMOB': '$3f', # Enable MObs
- 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
- 'CANIE2' : '$de', # Enable Interrupt MOb Register
- 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
- 'CANIE1' : '$df', # Enable Interrupt MOb Register
- 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
- 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
- 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
- 'CANBT1' : '$e2', # CAN Bit Timing Register 1
- 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
- 'CANBT2' : '$e3', # CAN Bit Timing Register 2
- 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
- 'CANBT2_PRS': '$e', # Propagation Time Segment bits
- 'CANBT3' : '$e4', # CAN Bit Timing Register 3
- 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
- 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
- 'CANBT3_SMP': '$1', # Sample Type
- 'CANTCON' : '$e5', # Timer Control Register
- 'CANTIML' : '$e6', # Timer Register Low
- 'CANTIMH' : '$e7', # Timer Register High
- 'CANTTCL' : '$e8', # TTC Timer Register Low
- 'CANTTCH' : '$e9', # TTC Timer Register High
- 'CANTEC' : '$ea', # Transmit Error Counter Registe
- 'CANREC' : '$eb', # Receive Error Counter Register
- 'CANHPMOB' : '$ec', # Highest Priority MOb Register
- 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
- 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
- 'CANPAGE' : '$ed', # Page MOb Register
- 'CANPAGE_MOBNB': '$f0', # MOb Number bits
- 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
- 'CANPAGE_INDX': '$7', # Data Buffer Index bits
- 'CANSTMOB' : '$ee', # MOb Status Register
- 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
- 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
- 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
- 'CANSTMOB_BERR': '$10', # Bit Error on MOb
- 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
- 'CANSTMOB_CERR': '$4', # CRC Error on MOb
- 'CANSTMOB_FERR': '$2', # Form Error on MOb
- 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
- 'CANCDMOB' : '$ef', # MOb Control and DLC Register
- 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
- 'CANCDMOB_RPLV': '$20', # Reply Valid
- 'CANCDMOB_IDE': '$10', # Identifier Extension
- 'CANCDMOB_DLC': '$f', # Data Length Code bits
- 'CANIDT4' : '$f0', # Identifier Tag Register 4
- 'CANIDT4_IDT': '$f8', #
- 'CANIDT4_RTRTAG': '$4', #
- 'CANIDT4_RB1TAG': '$2', #
- 'CANIDT4_RB0TAG': '$1', #
- 'CANIDT3' : '$f1', # Identifier Tag Register 3
- 'CANIDT2' : '$f2', # Identifier Tag Register 2
- 'CANIDT1' : '$f3', # Identifier Tag Register 1
- 'CANIDM4' : '$f4', # Identifier Mask Register 4
- 'CANIDM3' : '$f5', # Identifier Mask Register 3
- 'CANIDM2' : '$f6', # Identifier Mask Register 2
- 'CANIDM1' : '$f7', # Identifier Mask Register 1
- 'CANSTML' : '$f8', # Time Stamp Register Low
- 'CANSTMH' : '$f9', # Time Stamp Register High
- 'CANMSG' : '$fa', # Message Data Register
-
-# Module ANALOG_COMPARATOR
- 'AC0CON' : '$94', # Analog Comparator 0 Control Re
- 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
- 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
- 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
- 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
- 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
- 'AC1CON' : '$95', # Analog Comparator 1 Control Re
- 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
- 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
- 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
- 'AC2CON' : '$96', # Analog Comparator 2 Control Re
- 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
- 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
- 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
- 'AC3CON' : '$97', # Analog Comparator 3 Control Re
- 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
- 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
- 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
- 'ACSR' : '$50', # Analog Comparator Status Regis
- 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
- 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
- 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
- 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
- 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
- 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
- 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
- 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
-
-# Module DA_CONVERTER
- 'DACH' : '$92', # DAC Data Register High Byte
- 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
- 'DACL' : '$91', # DAC Data Register Low Byte
- 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
- 'DACON' : '$90', # DAC Control Register
- 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
- 'DACON_DATS': '$70', # DAC Trigger Selection Bits
- 'DACON_DALA': '$4', # DAC Left Adjust
- 'DACON_DAEN': '$1', # DAC Enable Bit
-
-# Module CPU
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_SPIPS': '$80', # SPI Pin Select
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$3a', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$39', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PLLCSR' : '$49', # PLL Control And Status Registe
- 'PLLCSR_PLLF': '$4', # PLL Factor
- 'PLLCSR_PLLE': '$2', # PLL Enable
- 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRCAN': '$40', # Power Reduction CAN
- 'PRR_PRPSC': '$20', # Power Reduction PSC
- 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
- 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRLIN': '$2', # Power Reduction LIN UART
- 'PRR_PRADC': '$1', # Power Reduction ADC
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins
-
-# Module TIMER_COUNTER_0
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCNT0' : '$46', # Timer/Counter0
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
- 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
- 'ADCSRB_ISRCEN': '$40', # Current Source Enable
- 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
- 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
- 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
- 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
- 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
- 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
- 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
- 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
- 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
- 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
- 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
- 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
- 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
- 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
- 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
- 'AMP0CSR' : '$75', #
- 'AMP0CSR_AMP0EN': '$80', #
- 'AMP0CSR_AMP0IS': '$40', #
- 'AMP0CSR_AMP0G': '$30', #
- 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
- 'AMP0CSR_AMP0TS': '$7', #
- 'AMP1CSR' : '$76', #
- 'AMP1CSR_AMP1EN': '$80', #
- 'AMP1CSR_AMP1IS': '$40', #
- 'AMP1CSR_AMP1G': '$30', #
- 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
- 'AMP1CSR_AMP1TS': '$7', #
- 'AMP2CSR' : '$77', #
- 'AMP2CSR_AMP2EN': '$80', #
- 'AMP2CSR_AMP2IS': '$40', #
- 'AMP2CSR_AMP2G': '$30', #
- 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
- 'AMP2CSR_AMP2TS': '$7', #
-
-# Module LINUART
- 'LINCR' : '$c8', # LIN Control Register
- 'LINCR_LSWRES': '$80', # Software Reset
- 'LINCR_LIN13': '$40', # LIN Standard
- 'LINCR_LCONF': '$30', # LIN Configuration bits
- 'LINCR_LENA': '$8', # LIN or UART Enable
- 'LINCR_LCMD': '$7', # LIN Command and Mode bits
- 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
- 'LINSIR_LIDST': '$e0', # Identifier Status bits
- 'LINSIR_LBUSY': '$10', # Busy Signal
- 'LINSIR_LERR': '$8', # Error Interrupt
- 'LINSIR_LIDOK': '$4', # Identifier Interrupt
- 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
- 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
- 'LINENIR' : '$ca', # LIN Enable Interrupt Register
- 'LINENIR_LENERR': '$8', # Enable Error Interrupt
- 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
- 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
- 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
- 'LINERR' : '$cb', # LIN Error Register
- 'LINERR_LABORT': '$80', # Abort Flag
- 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
- 'LINERR_LOVERR': '$20', # Overrun Error Flag
- 'LINERR_LFERR': '$10', # Framing Error Flag
- 'LINERR_LSERR': '$8', # Synchronization Error Flag
- 'LINERR_LPERR': '$4', # Parity Error Flag
- 'LINERR_LCERR': '$2', # Checksum Error Flag
- 'LINERR_LBERR': '$1', # Bit Error Flag
- 'LINBTR' : '$cc', # LIN Bit Timing Register
- 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
- 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
- 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
- 'LINBRRL_LDIV': '$ff', #
- 'LINBRRH' : '$ce', # LIN Baud Rate High Register
- 'LINBRRH_LDIV': '$f', #
- 'LINDLR' : '$cf', # LIN Data Length Register
- 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
- 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
- 'LINIDR' : '$d0', # LIN Identifier Register
- 'LINIDR_LP': '$c0', # Parity bits
- 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
- 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
- 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
- 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
- 'LINDAT' : '$d2', # LIN Data Register
- 'LINDAT_LDATA': '$ff', #
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$f', # External Interrupt Request 3 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$f', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
- 'PCMSK3' : '$6d', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
- 'PCMSK2' : '$6c', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6b', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6a', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Read/Write Access
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', #
- 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
- 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
- 'EECR_EEWE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega64c1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64c1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64c1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64c1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64c1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64c1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega64c1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64hve/atmega64hve.frt b/amforth-6.5/avr8/devices/atmega64hve/atmega64hve.frt
deleted file mode 100644
index 3150df4..0000000
--- a/amforth-6.5/avr8/devices/atmega64hve/atmega64hve.frt
+++ /dev/null
@@ -1,154 +0,0 @@
-\ Partname: ATmega64HVE
-\ Built using part description XML file version 1
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-e2 constant ADCRA \ ADC Control Register A
-e3 constant ADCRB \ ADC Control Register B
-e4 constant ADCRC \ ADC Control Register B
-e5 constant ADCRD \ ADC Control Register D
-e6 constant ADCRE \ ADC Control Register E
-e7 constant ADIFR \ ADC Interrupt Flag Register
-e8 constant ADIMR \ ADC Interrupt Mask Register
-e0 constant ADSCSRA \ ADC Synchronization Control and Status Register
-e1 constant ADSCSRB \ ADC Synchronization Control and Status Register
-ed constant CADAC0 \ C-ADC Accumulated Conversion Result
-ee constant CADAC1 \ C-ADC Accumulated Conversion Result
-ef constant CADAC2 \ C-ADC Accumulated Conversion Result
-f0 constant CADAC3 \ C-ADC Accumulated Conversion Result
-ec constant CADICH \ C-ADC Instantaneous Conversion Result
-eb constant CADICL \ C-ADC Instantaneous Conversion Result
-ea constant CADRCLH \ CC-ADC Regulator Current Comparator Threshold Level
-e9 constant CADRCLL \ CC-ADC Regulator Current Comparator Threshold Level
-f3 constant VADAC0 \ V-ADC Accumulated Conversion Result
-f4 constant VADAC1 \ V-ADC Accumulated Conversion Result
-f5 constant VADAC2 \ V-ADC Accumulated Conversion Result
-f6 constant VADAC3 \ V-ADC Accumulated Conversion Result
-f2 constant VADICH \ V-ADC Instantaneous Conversion Result
-f1 constant VADICL \ V-ADC Instantaneous Conversion Result
-
-\ BANDGAP
-d3 constant BGCRA \ Band Gap Calibration Register A
-d2 constant BGCRB \ Band Gap Calibration Register B
-d1 constant BGCSRA \ Bandgap Control and Status Register A
-d4 constant BGLR \ Band Gap Lock Register
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control and Status Register
-
-\ CPU
-61 constant CLKPR \ Clock Prescale Register
-7E constant DIDR0 \ Digital Input Disable Register
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-d8 constant PLLCSR \ PLL Control and Status Register
-64 constant PRR0 \ Power Reduction Register 0
-53 constant SMCR \ Sleep Mode Control Register
-66 constant SOSCCALA \ Slow Oscillator Calibration Register A
-67 constant SOSCCALB \ Oscillator Calibration Register B
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-42 constant EEARH \ EEPROM Read/Write Access
-41 constant EEARL \ EEPROM Read/Write Access
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-68 constant PCICR \ Pin Change Interrupt Control Register
-3B constant PCIFR \ Pin Change Interrupt Flag Register
-6B constant PCMSK0 \ Pin Change Enable Mask Register 0
-6C constant PCMSK1 \ Pin Change Enable Mask Register 1
-
-\ LINUART
-c6 constant LINBRRH \ LIN Baud Rate High Register
-c5 constant LINBRRL \ LIN Baud Rate Low Register
-c4 constant LINBTR \ LIN Bit Timing Register
-c0 constant LINCR \ LIN Control Register
-cA constant LINDAT \ LIN Data Register
-c7 constant LINDLR \ LIN Data Length Register
-c2 constant LINENIR \ LIN Enable Interrupt Register
-c3 constant LINERR \ LIN Error Register
-c8 constant LINIDR \ LIN Identifier Register
-c9 constant LINSEL \ LIN Data Buffer Selection Register
-c1 constant LINSIR \ LIN Status and Interrupt Register
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Port B Data Direction Register
-dc constant PBOV \ Port B Override
-23 constant PINB \ Port B Input Pins
-25 constant PORTB \ Port B Data Register
-
-\ SPI
-4c constant SPCR \ SPI Control Register
-4e constant SPDR \ SPI Data Register
-4d constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-43 constant GTCCR \ General Timer/Counter Control Register
-48 constant OCR0A \ Output Compare Register 0A
-49 constant OCR0B \ Output Compare Register B
-44 constant TCCR0A \ Timer/Counter 0 Control Register A
-45 constant TCCR0B \ Timer/Counter0 Control Register B
-47 constant TCNT0H \ Timer Counter 0 High Byte
-46 constant TCNT0L \ Timer Counter 0 Low Byte
-35 constant TIFR0 \ Timer/Counter Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-88 constant OCR1A \ Output Compare Register 1A
-89 constant OCR1B \ Output Compare Register B
-80 constant TCCR1A \ Timer/Counter 1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-85 constant TCNT1H \ Timer Counter 1 High Byte
-84 constant TCNT1L \ Timer Counter 1 Low Byte
-36 constant TIFR1 \ Timer/Counter Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
-
-\ WAKEUP_TIMER
-62 constant WUTCSR \ Wake-up Timer Control and Status Register
-
-\ WATCHDOG
-63 constant WDTCLR \ Watchdog Timer Configuration Lock Register
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-0002 constant INT0Addr \ External Interrupt 0
-0004 constant PCINT0Addr \ Pin Change Interrupt 0
-0006 constant PCINT1Addr \ Pin Change Interrupt 1
-0008 constant WDTAddr \ Watchdog Timeout Interrupt
-000a constant WAKEUPAddr \ Wakeup Timer Overflow
-000c constant TIMER1_ICAddr \ Timer 1 Input capture
-000e constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-0010 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-0012 constant TIMER1_OVFAddr \ Timer 1 overflow
-0014 constant TIMER0_ICAddr \ Timer 0 Input Capture
-0016 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-0018 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-001a constant TIMER0_OVFAddr \ Timer 0 Overflow
-001c constant LIN_STATUSAddr \ LIN Status Interrupt
-001e constant LIN_ERRORAddr \ LIN Error Interrupt
-0020 constant SPI_STCAddr \ SPI Serial transfer complete
-0022 constant VADC_CONVAddr \ Voltage ADC Instantaneous Conversion Complet
-0024 constant VADC_ACCAddr \ Voltage ADC Accumulated Conversion Complete
-0026 constant CADC_CONVAddr \ C-ADC Instantaneous Conversion Complete
-0028 constant CADC_REG_CURAddr \ C-ADC Regular Current
-002a constant CADC_ACCAddr \ C-ADC Accumulated Conversion Complete
-02c constant EE_READYAddr \ EEPROM Ready
-02e constant SPMAddr \ SPM Ready
-030 constant PLLAddr \ PLL Lock Change Interrupt
diff --git a/amforth-6.5/avr8/devices/atmega64hve/device.asm b/amforth-6.5/avr8/devices/atmega64hve/device.asm
deleted file mode 100644
index dc9b9ee..0000000
--- a/amforth-6.5/avr8/devices/atmega64hve/device.asm
+++ /dev/null
@@ -1,119 +0,0 @@
-; Partname: ATmega64HVE
-; Built using part description XML file version 1
-; generated automatically, do not edit
-
-.nolist
- .include "m64HVEdef.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_BANDGAP = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_LINUART = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_WAKEUP_TIMER = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 25
-.org $0002
- rcall isr ; External Interrupt 0
-.org $0004
- rcall isr ; Pin Change Interrupt 0
-.org $0006
- rcall isr ; Pin Change Interrupt 1
-.org $0008
- rcall isr ; Watchdog Timeout Interrupt
-.org $000a
- rcall isr ; Wakeup Timer Overflow
-.org $000c
- rcall isr ; Timer 1 Input capture
-.org $000e
- rcall isr ; Timer 1 Compare Match A
-.org $0010
- rcall isr ; Timer 1 Compare Match B
-.org $0012
- rcall isr ; Timer 1 overflow
-.org $0014
- rcall isr ; Timer 0 Input Capture
-.org $0016
- rcall isr ; Timer 0 Comapre Match A
-.org $0018
- rcall isr ; Timer 0 Compare Match B
-.org $001a
- rcall isr ; Timer 0 Overflow
-.org $001c
- rcall isr ; LIN Status Interrupt
-.org $001e
- rcall isr ; LIN Error Interrupt
-.org $0020
- rcall isr ; SPI Serial transfer complete
-.org $0022
- rcall isr ; Voltage ADC Instantaneous Conversion Complete
-.org $0024
- rcall isr ; Voltage ADC Accumulated Conversion Complete
-.org $0026
- rcall isr ; C-ADC Instantaneous Conversion Complete
-.org $0028
- rcall isr ; C-ADC Regular Current
-.org $002a
- rcall isr ; C-ADC Accumulated Conversion Complete
-.org $02c
- rcall isr ; EEPROM Ready
-.org $02e
- rcall isr ; SPM Ready
-.org $030
- rcall isr ; PLL Lock Change Interrupt
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 1024
-mcu_maxdp:
- .dw 28672 ; minimum of 0x7000 (from XML) and 0xffff
-mcu_numints:
- .dw 25
-mcu_name:
- .dw 11
- .db "ATmega64HVE",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64hve/device.inc b/amforth-6.5/avr8/devices/atmega64hve/device.inc
deleted file mode 100644
index 749f94a..0000000
--- a/amforth-6.5/avr8/devices/atmega64hve/device.inc
+++ /dev/null
@@ -1,1227 +0,0 @@
-; Partname: ATmega64HVE
-; Built using part description XML file version 1
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control Register A
-VE_ADCRA:
- .dw $ff05
- .db "ADCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCRA
-XT_ADCRA:
- .dw PFA_DOVARIABLE
-PFA_ADCRA:
- .dw $e2
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control Register B
-VE_ADCRB:
- .dw $ff05
- .db "ADCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCRB
-XT_ADCRB:
- .dw PFA_DOVARIABLE
-PFA_ADCRB:
- .dw $e3
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control Register B
-VE_ADCRC:
- .dw $ff05
- .db "ADCRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCRC
-XT_ADCRC:
- .dw PFA_DOVARIABLE
-PFA_ADCRC:
- .dw $e4
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control Register D
-VE_ADCRD:
- .dw $ff05
- .db "ADCRD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCRD
-XT_ADCRD:
- .dw PFA_DOVARIABLE
-PFA_ADCRD:
- .dw $e5
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control Register E
-VE_ADCRE:
- .dw $ff05
- .db "ADCRE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCRE
-XT_ADCRE:
- .dw PFA_DOVARIABLE
-PFA_ADCRE:
- .dw $e6
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Interrupt Flag Register
-VE_ADIFR:
- .dw $ff05
- .db "ADIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADIFR
-XT_ADIFR:
- .dw PFA_DOVARIABLE
-PFA_ADIFR:
- .dw $e7
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Interrupt Mask Register
-VE_ADIMR:
- .dw $ff05
- .db "ADIMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADIMR
-XT_ADIMR:
- .dw PFA_DOVARIABLE
-PFA_ADIMR:
- .dw $e8
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Synchronization Control and Status Register
-VE_ADSCSRA:
- .dw $ff07
- .db "ADSCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADSCSRA
-XT_ADSCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADSCSRA:
- .dw $e0
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Synchronization Control and Status Register
-VE_ADSCSRB:
- .dw $ff07
- .db "ADSCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADSCSRB
-XT_ADSCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADSCSRB:
- .dw $e1
-; ( -- addr ) System Constant
-; R( -- )
-; C-ADC Accumulated Conversion Result
-VE_CADAC0:
- .dw $ff06
- .db "CADAC0"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC0
-XT_CADAC0:
- .dw PFA_DOVARIABLE
-PFA_CADAC0:
- .dw $ed
-; ( -- addr ) System Constant
-; R( -- )
-; C-ADC Accumulated Conversion Result
-VE_CADAC1:
- .dw $ff06
- .db "CADAC1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC1
-XT_CADAC1:
- .dw PFA_DOVARIABLE
-PFA_CADAC1:
- .dw $ee
-; ( -- addr ) System Constant
-; R( -- )
-; C-ADC Accumulated Conversion Result
-VE_CADAC2:
- .dw $ff06
- .db "CADAC2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC2
-XT_CADAC2:
- .dw PFA_DOVARIABLE
-PFA_CADAC2:
- .dw $ef
-; ( -- addr ) System Constant
-; R( -- )
-; C-ADC Accumulated Conversion Result
-VE_CADAC3:
- .dw $ff06
- .db "CADAC3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC3
-XT_CADAC3:
- .dw PFA_DOVARIABLE
-PFA_CADAC3:
- .dw $f0
-; ( -- addr ) System Constant
-; R( -- )
-; C-ADC Instantaneous Conversion Result
-VE_CADICH:
- .dw $ff06
- .db "CADICH"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICH
-XT_CADICH:
- .dw PFA_DOVARIABLE
-PFA_CADICH:
- .dw $ec
-; ( -- addr ) System Constant
-; R( -- )
-; C-ADC Instantaneous Conversion Result
-VE_CADICL:
- .dw $ff06
- .db "CADICL"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICL
-XT_CADICL:
- .dw PFA_DOVARIABLE
-PFA_CADICL:
- .dw $eb
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regulator Current Comparator Threshold Level
-VE_CADRCLH:
- .dw $ff07
- .db "CADRCLH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRCLH
-XT_CADRCLH:
- .dw PFA_DOVARIABLE
-PFA_CADRCLH:
- .dw $ea
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regulator Current Comparator Threshold Level
-VE_CADRCLL:
- .dw $ff07
- .db "CADRCLL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRCLL
-XT_CADRCLL:
- .dw PFA_DOVARIABLE
-PFA_CADRCLL:
- .dw $e9
-; ( -- addr ) System Constant
-; R( -- )
-; V-ADC Accumulated Conversion Result
-VE_VADAC0:
- .dw $ff06
- .db "VADAC0"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADAC0
-XT_VADAC0:
- .dw PFA_DOVARIABLE
-PFA_VADAC0:
- .dw $f3
-; ( -- addr ) System Constant
-; R( -- )
-; V-ADC Accumulated Conversion Result
-VE_VADAC1:
- .dw $ff06
- .db "VADAC1"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADAC1
-XT_VADAC1:
- .dw PFA_DOVARIABLE
-PFA_VADAC1:
- .dw $f4
-; ( -- addr ) System Constant
-; R( -- )
-; V-ADC Accumulated Conversion Result
-VE_VADAC2:
- .dw $ff06
- .db "VADAC2"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADAC2
-XT_VADAC2:
- .dw PFA_DOVARIABLE
-PFA_VADAC2:
- .dw $f5
-; ( -- addr ) System Constant
-; R( -- )
-; V-ADC Accumulated Conversion Result
-VE_VADAC3:
- .dw $ff06
- .db "VADAC3"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADAC3
-XT_VADAC3:
- .dw PFA_DOVARIABLE
-PFA_VADAC3:
- .dw $f6
-; ( -- addr ) System Constant
-; R( -- )
-; V-ADC Instantaneous Conversion Result
-VE_VADICH:
- .dw $ff06
- .db "VADICH"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADICH
-XT_VADICH:
- .dw PFA_DOVARIABLE
-PFA_VADICH:
- .dw $f2
-; ( -- addr ) System Constant
-; R( -- )
-; V-ADC Instantaneous Conversion Result
-VE_VADICL:
- .dw $ff06
- .db "VADICL"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADICL
-XT_VADICL:
- .dw PFA_DOVARIABLE
-PFA_VADICL:
- .dw $f1
-
-.endif
-
-; ********
-.if WANT_BANDGAP == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Band Gap Calibration Register A
-VE_BGCRA:
- .dw $ff05
- .db "BGCRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRA
-XT_BGCRA:
- .dw PFA_DOVARIABLE
-PFA_BGCRA:
- .dw $d3
-; ( -- addr ) System Constant
-; R( -- )
-; Band Gap Calibration Register B
-VE_BGCRB:
- .dw $ff05
- .db "BGCRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRB
-XT_BGCRB:
- .dw PFA_DOVARIABLE
-PFA_BGCRB:
- .dw $d2
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Control and Status Register A
-VE_BGCSRA:
- .dw $ff06
- .db "BGCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCSRA
-XT_BGCSRA:
- .dw PFA_DOVARIABLE
-PFA_BGCSRA:
- .dw $d1
-; ( -- addr ) System Constant
-; R( -- )
-; Band Gap Lock Register
-VE_BGLR:
- .dw $ff04
- .db "BGLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BGLR
-XT_BGLR:
- .dw PFA_DOVARIABLE
-PFA_BGLR:
- .dw $d4
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control and Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw $d8
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Slow Oscillator Calibration Register A
-VE_SOSCCALA:
- .dw $ff08
- .db "SOSCCALA"
- .dw VE_HEAD
- .set VE_HEAD=VE_SOSCCALA
-XT_SOSCCALA:
- .dw PFA_DOVARIABLE
-PFA_SOSCCALA:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Register B
-VE_SOSCCALB:
- .dw $ff08
- .db "SOSCCALB"
- .dw VE_HEAD
- .set VE_HEAD=VE_SOSCCALB
-XT_SOSCCALB:
- .dw PFA_DOVARIABLE
-PFA_SOSCCALB:
- .dw $67
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $42
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw $68
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw $3B
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Enable Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw $6B
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Enable Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw $6C
-
-.endif
-
-; ********
-.if WANT_LINUART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate High Register
-VE_LINBRRH:
- .dw $ff07
- .db "LINBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRH
-XT_LINBRRH:
- .dw PFA_DOVARIABLE
-PFA_LINBRRH:
- .dw $c6
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate Low Register
-VE_LINBRRL:
- .dw $ff07
- .db "LINBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRL
-XT_LINBRRL:
- .dw PFA_DOVARIABLE
-PFA_LINBRRL:
- .dw $c5
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Bit Timing Register
-VE_LINBTR:
- .dw $ff06
- .db "LINBTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBTR
-XT_LINBTR:
- .dw PFA_DOVARIABLE
-PFA_LINBTR:
- .dw $c4
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Control Register
-VE_LINCR:
- .dw $ff05
- .db "LINCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINCR
-XT_LINCR:
- .dw PFA_DOVARIABLE
-PFA_LINCR:
- .dw $c0
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Register
-VE_LINDAT:
- .dw $ff06
- .db "LINDAT"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDAT
-XT_LINDAT:
- .dw PFA_DOVARIABLE
-PFA_LINDAT:
- .dw $cA
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Length Register
-VE_LINDLR:
- .dw $ff06
- .db "LINDLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDLR
-XT_LINDLR:
- .dw PFA_DOVARIABLE
-PFA_LINDLR:
- .dw $c7
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Enable Interrupt Register
-VE_LINENIR:
- .dw $ff07
- .db "LINENIR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINENIR
-XT_LINENIR:
- .dw PFA_DOVARIABLE
-PFA_LINENIR:
- .dw $c2
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Error Register
-VE_LINERR:
- .dw $ff06
- .db "LINERR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINERR
-XT_LINERR:
- .dw PFA_DOVARIABLE
-PFA_LINERR:
- .dw $c3
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Identifier Register
-VE_LINIDR:
- .dw $ff06
- .db "LINIDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINIDR
-XT_LINIDR:
- .dw PFA_DOVARIABLE
-PFA_LINIDR:
- .dw $c8
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Buffer Selection Register
-VE_LINSEL:
- .dw $ff06
- .db "LINSEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSEL
-XT_LINSEL:
- .dw PFA_DOVARIABLE
-PFA_LINSEL:
- .dw $c9
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Status and Interrupt Register
-VE_LINSIR:
- .dw $ff06
- .db "LINSIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSIR
-XT_LINSIR:
- .dw PFA_DOVARIABLE
-PFA_LINSIR:
- .dw $c1
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Override
-VE_PBOV:
- .dw $ff04
- .db "PBOV"
- .dw VE_HEAD
- .set VE_HEAD=VE_PBOV
-XT_PBOV:
- .dw PFA_DOVARIABLE
-PFA_PBOV:
- .dw $dc
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4c
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4e
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4d
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 0A
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 High Byte
-VE_TCNT0H:
- .dw $ff06
- .db "TCNT0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0H
-XT_TCNT0H:
- .dw PFA_DOVARIABLE
-PFA_TCNT0H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 Low Byte
-VE_TCNT0L:
- .dw $ff06
- .db "TCNT0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0L
-XT_TCNT0L:
- .dw PFA_DOVARIABLE
-PFA_TCNT0L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 1A
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register B
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_WAKEUP_TIMER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Wake-up Timer Control and Status Register
-VE_WUTCSR:
- .dw $ff06
- .db "WUTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WUTCSR
-XT_WUTCSR:
- .dw PFA_DOVARIABLE
-PFA_WUTCSR:
- .dw $62
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Configuration Lock Register
-VE_WDTCLR:
- .dw $ff06
- .db "WDTCLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCLR
-XT_WDTCLR:
- .dw PFA_DOVARIABLE
-PFA_WDTCLR:
- .dw $63
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega64hve/device.py b/amforth-6.5/avr8/devices/atmega64hve/device.py
deleted file mode 100644
index 6bba39c..0000000
--- a/amforth-6.5/avr8/devices/atmega64hve/device.py
+++ /dev/null
@@ -1,124 +0,0 @@
-# Partname: ATmega64HVE
-# Built using part description XML file version 1
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCRA': '$e2',
- 'ADCRB': '$e3',
- 'ADCRC': '$e4',
- 'ADCRD': '$e5',
- 'ADCRE': '$e6',
- 'ADIFR': '$e7',
- 'ADIMR': '$e8',
- 'ADSCSRA': '$e0',
- 'ADSCSRB': '$e1',
- 'CADAC0': '$ed',
- 'CADAC1': '$ee',
- 'CADAC2': '$ef',
- 'CADAC3': '$f0',
- 'CADICH': '$ec',
- 'CADICL': '$eb',
- 'CADRCLH': '$ea',
- 'CADRCLL': '$e9',
- 'VADAC0': '$f3',
- 'VADAC1': '$f4',
- 'VADAC2': '$f5',
- 'VADAC3': '$f6',
- 'VADICH': '$f2',
- 'VADICL': '$f1',
- 'BGCRA': '$d3',
- 'BGCRB': '$d2',
- 'BGCSRA': '$d1',
- 'BGLR': '$d4',
- 'SPMCSR': '$57',
- 'CLKPR': '$61',
- 'DIDR0': '$7E',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$4A',
- 'GPIOR2': '$4B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'PLLCSR': '$d8',
- 'PRR0': '$64',
- 'SMCR': '$53',
- 'SOSCCALA': '$66',
- 'SOSCCALB': '$67',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'EEARH': '$42',
- 'EEARL': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EICRA': '$69',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'PCICR': '$68',
- 'PCIFR': '$3B',
- 'PCMSK0': '$6B',
- 'PCMSK1': '$6C',
- 'LINBRRH': '$c6',
- 'LINBRRL': '$c5',
- 'LINBTR': '$c4',
- 'LINCR': '$c0',
- 'LINDAT': '$cA',
- 'LINDLR': '$c7',
- 'LINENIR': '$c2',
- 'LINERR': '$c3',
- 'LINIDR': '$c8',
- 'LINSEL': '$c9',
- 'LINSIR': '$c1',
- 'DDRA': '$21',
- 'PINA': '$20',
- 'PORTA': '$22',
- 'DDRB': '$24',
- 'PBOV': '$dc',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'SPCR': '$4c',
- 'SPDR': '$4e',
- 'SPSR': '$4d',
- 'GTCCR': '$43',
- 'OCR0A': '$48',
- 'OCR0B': '$49',
- 'TCCR0A': '$44',
- 'TCCR0B': '$45',
- 'TCNT0H': '$47',
- 'TCNT0L': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'OCR1A': '$88',
- 'OCR1B': '$89',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'WUTCSR': '$62',
- 'WDTCLR': '$63',
- 'WDTCSR': '$60',
- 'INT0Addr': '$0002',
- 'PCINT0Addr': '$0004',
- 'PCINT1Addr': '$0006',
- 'WDTAddr': '$0008',
- 'WAKEUPAddr': '$000a',
- 'TIMER1_ICAddr': '$000c',
- 'TIMER1_COMPAAddr': '$000e',
- 'TIMER1_COMPBAddr': '$0010',
- 'TIMER1_OVFAddr': '$0012',
- 'TIMER0_ICAddr': '$0014',
- 'TIMER0_COMPAAddr': '$0016',
- 'TIMER0_COMPBAddr': '$0018',
- 'TIMER0_OVFAddr': '$001a',
- 'LIN_STATUSAddr': '$001c',
- 'LIN_ERRORAddr': '$001e',
- 'SPI_STCAddr': '$0020',
- 'VADC_CONVAddr': '$0022',
- 'VADC_ACCAddr': '$0024',
- 'CADC_CONVAddr': '$0026',
- 'CADC_REG_CURAddr': '$0028',
- 'CADC_ACCAddr': '$002a',
- 'EE_READYAddr': '$02c',
- 'SPMAddr': '$02e',
- 'PLLAddr': '$030'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt b/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt
deleted file mode 100644
index 135e761..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt
+++ /dev/null
@@ -1,513 +0,0 @@
-\ Partname: ATmega64M1
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ CAN
-&216 constant CANGCON \ CAN General Control Register
- $80 constant CANGCON_ABRQ \ Abort Request
- $40 constant CANGCON_OVRQ \ Overload Frame Request
- $20 constant CANGCON_TTC \ Time Trigger Communication
- $10 constant CANGCON_SYNTTC \ Synchronization of TTC
- $08 constant CANGCON_LISTEN \ Listening Mode
- $04 constant CANGCON_TEST \ Test Mode
- $02 constant CANGCON_ENASTB \ Enable / Standby
- $01 constant CANGCON_SWRES \ Software Reset Request
-&217 constant CANGSTA \ CAN General Status Register
- $40 constant CANGSTA_OVFG \ Overload Frame Flag
- $10 constant CANGSTA_TXBSY \ Transmitter Busy
- $08 constant CANGSTA_RXBSY \ Receiver Busy
- $04 constant CANGSTA_ENFG \ Enable Flag
- $02 constant CANGSTA_BOFF \ Bus Off Mode
- $01 constant CANGSTA_ERRP \ Error Passive Mode
-&218 constant CANGIT \ CAN General Interrupt Register Flags
- $80 constant CANGIT_CANIT \ General Interrupt Flag
- $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
- $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
- $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
- $08 constant CANGIT_SERG \ Stuff Error General Flag
- $04 constant CANGIT_CERG \ CRC Error General Flag
- $02 constant CANGIT_FERG \ Form Error General Flag
- $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
-&219 constant CANGIE \ CAN General Interrupt Enable Register
- $80 constant CANGIE_ENIT \ Enable all Interrupts
- $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
- $20 constant CANGIE_ENRX \ Enable Receive Interrupt
- $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
- $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
- $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
- $02 constant CANGIE_ENERG \ Enable General Error Interrupt
- $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
-&220 constant CANEN2 \ Enable MOb Register 2
- $3F constant CANEN2_ENMOB \ Enable MObs
-&221 constant CANEN1 \ Enable MOb Register 1(empty)
-&222 constant CANIE2 \ Enable Interrupt MOb Register 2
- $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
-&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
-&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
- $3F constant CANSIT2_SIT \ Status of Interrupt MObs
-&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
-&226 constant CANBT1 \ CAN Bit Timing Register 1
- $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
-&227 constant CANBT2 \ CAN Bit Timing Register 2
- $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
- $0E constant CANBT2_PRS \ Propagation Time Segment bits
-&228 constant CANBT3 \ CAN Bit Timing Register 3
- $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
- $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
- $01 constant CANBT3_SMP \ Sample Type
-&229 constant CANTCON \ Timer Control Register
-&230 constant CANTIML \ Timer Register Low
-&231 constant CANTIMH \ Timer Register High
-&232 constant CANTTCL \ TTC Timer Register Low
-&233 constant CANTTCH \ TTC Timer Register High
-&234 constant CANTEC \ Transmit Error Counter Register
-&235 constant CANREC \ Receive Error Counter Register
-&236 constant CANHPMOB \ Highest Priority MOb Register
- $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
- $0F constant CANHPMOB_CGP \ CAN General Purpose bits
-&237 constant CANPAGE \ Page MOb Register
- $F0 constant CANPAGE_MOBNB \ MOb Number bits
- $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
- $07 constant CANPAGE_INDX \ Data Buffer Index bits
-&238 constant CANSTMOB \ MOb Status Register
- $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
- $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
- $20 constant CANSTMOB_RXOK \ Receive OK on MOb
- $10 constant CANSTMOB_BERR \ Bit Error on MOb
- $08 constant CANSTMOB_SERR \ Stuff Error on MOb
- $04 constant CANSTMOB_CERR \ CRC Error on MOb
- $02 constant CANSTMOB_FERR \ Form Error on MOb
- $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
-&239 constant CANCDMOB \ MOb Control and DLC Register
- $C0 constant CANCDMOB_CONMOB \ MOb Config bits
- $20 constant CANCDMOB_RPLV \ Reply Valid
- $10 constant CANCDMOB_IDE \ Identifier Extension
- $0F constant CANCDMOB_DLC \ Data Length Code bits
-&240 constant CANIDT4 \ Identifier Tag Register 4
- $F8 constant CANIDT4_IDT \
- $04 constant CANIDT4_RTRTAG \
- $02 constant CANIDT4_RB1TAG \
- $01 constant CANIDT4_RB0TAG \
-&241 constant CANIDT3 \ Identifier Tag Register 3
-&242 constant CANIDT2 \ Identifier Tag Register 2
-&243 constant CANIDT1 \ Identifier Tag Register 1
-&244 constant CANIDM4 \ Identifier Mask Register 4
-&245 constant CANIDM3 \ Identifier Mask Register 3
-&246 constant CANIDM2 \ Identifier Mask Register 2
-&247 constant CANIDM1 \ Identifier Mask Register 1
-&248 constant CANSTML \ Time Stamp Register Low
-&249 constant CANSTMH \ Time Stamp Register High
-&250 constant CANMSG \ Message Data Register
-\ ANALOG_COMPARATOR
-&148 constant AC0CON \ Analog Comparator 0 Control Register
- $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
- $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
- $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
- $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
- $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
-&149 constant AC1CON \ Analog Comparator 1 Control Register
- $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
- $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
- $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
- $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
- $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
-&150 constant AC2CON \ Analog Comparator 2 Control Register
- $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
- $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
- $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
- $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
-&151 constant AC3CON \ Analog Comparator 3 Control Register
- $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
- $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
- $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
- $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
-&80 constant ACSR \ Analog Comparator Status Register
- $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
- $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
- $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
- $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
- $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
- $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
- $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
- $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
-\ DA_CONVERTER
-&146 constant DACH \ DAC Data Register High Byte
- $FF constant DACH_DACH \ DAC Data Register High Byte Bits
-&145 constant DACL \ DAC Data Register Low Byte
- $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
-&144 constant DACON \ DAC Control Register
- $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
- $70 constant DACON_DATS \ DAC Trigger Selection Bits
- $04 constant DACON_DALA \ DAC Left Adjust
- $01 constant DACON_DAEN \ DAC Enable Bit
-\ CPU
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SPIPS \ SPI Pin Select
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&58 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&57 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&73 constant PLLCSR \ PLL Control And Status Register
- $04 constant PLLCSR_PLLF \ PLL Factor
- $02 constant PLLCSR_PLLE \ PLL Enable
- $01 constant PLLCSR_PLOCK \ PLL Lock Detector
-&100 constant PRR \ Power Reduction Register
- $40 constant PRR_PRCAN \ Power Reduction CAN
- $20 constant PRR_PRPSC \ Power Reduction PSC
- $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRLIN \ Power Reduction LIN UART
- $01 constant PRR_PRADC \ Power Reduction ADC
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins
-\ TIMER_COUNTER_0
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&70 constant TCNT0 \ Timer/Counter0
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
- $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&122 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&120 constant ADC \ ADC Data Register Bytes
-&123 constant ADCSRB \ ADC Control and Status Register B
- $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
- $40 constant ADCSRB_ISRCEN \ Current Source Enable
- $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
- $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
- $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
- $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
- $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
- $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
- $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
- $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
- $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
-&127 constant DIDR1 \ Digital Input Disable Register 0
- $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
- $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
- $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
- $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
- $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
- $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
- $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
-&117 constant AMP0CSR \
- $80 constant AMP0CSR_AMP0EN \
- $40 constant AMP0CSR_AMP0IS \
- $30 constant AMP0CSR_AMP0G \
- $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
- $07 constant AMP0CSR_AMP0TS \
-&118 constant AMP1CSR \
- $80 constant AMP1CSR_AMP1EN \
- $40 constant AMP1CSR_AMP1IS \
- $30 constant AMP1CSR_AMP1G \
- $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
- $07 constant AMP1CSR_AMP1TS \
-&119 constant AMP2CSR \
- $80 constant AMP2CSR_AMP2EN \
- $40 constant AMP2CSR_AMP2IS \
- $30 constant AMP2CSR_AMP2G \
- $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
- $07 constant AMP2CSR_AMP2TS \
-\ LINUART
-&200 constant LINCR \ LIN Control Register
- $80 constant LINCR_LSWRES \ Software Reset
- $40 constant LINCR_LIN13 \ LIN Standard
- $30 constant LINCR_LCONF \ LIN Configuration bits
- $08 constant LINCR_LENA \ LIN or UART Enable
- $07 constant LINCR_LCMD \ LIN Command and Mode bits
-&201 constant LINSIR \ LIN Status and Interrupt Register
- $E0 constant LINSIR_LIDST \ Identifier Status bits
- $10 constant LINSIR_LBUSY \ Busy Signal
- $08 constant LINSIR_LERR \ Error Interrupt
- $04 constant LINSIR_LIDOK \ Identifier Interrupt
- $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
- $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
-&202 constant LINENIR \ LIN Enable Interrupt Register
- $08 constant LINENIR_LENERR \ Enable Error Interrupt
- $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
- $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
- $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
-&203 constant LINERR \ LIN Error Register
- $80 constant LINERR_LABORT \ Abort Flag
- $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
- $20 constant LINERR_LOVERR \ Overrun Error Flag
- $10 constant LINERR_LFERR \ Framing Error Flag
- $08 constant LINERR_LSERR \ Synchronization Error Flag
- $04 constant LINERR_LPERR \ Parity Error Flag
- $02 constant LINERR_LCERR \ Checksum Error Flag
- $01 constant LINERR_LBERR \ Bit Error Flag
-&204 constant LINBTR \ LIN Bit Timing Register
- $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
- $3F constant LINBTR_LBT \ LIN Bit Timing bits
-&205 constant LINBRRL \ LIN Baud Rate Low Register
- $FF constant LINBRRL_LDIV \
-&206 constant LINBRRH \ LIN Baud Rate High Register
- $0F constant LINBRRH_LDIV \
-&207 constant LINDLR \ LIN Data Length Register
- $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
- $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
-&208 constant LINIDR \ LIN Identifier Register
- $C0 constant LINIDR_LP \ Parity bits
- $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
-&209 constant LINSEL \ LIN Data Buffer Selection Register
- $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
- $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
-&210 constant LINDAT \ LIN Data Register
- $FF constant LINDAT_LDATA \
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $0F constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK3 \ Pin Change Mask Register 3
- $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&106 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ EEPROM
-&65 constant EEAR \ EEPROM Read/Write Access
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \
- $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ PSC
-&188 constant PIFR \ PSC Interrupt Flag Register
- $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
- $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
-&187 constant PIM \ PSC Interrupt Mask Register
- $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
- $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
-&186 constant PMIC2 \ PSC Module 2 Input Control Register
- $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
- $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
- $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
- $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
- $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
- $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
-&185 constant PMIC1 \ PSC Module 1 Input Control Register
- $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
- $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
- $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
- $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
- $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
- $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
-&184 constant PMIC0 \ PSC Module 0 Input Control Register
- $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
- $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
- $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
- $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
- $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
- $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
-&183 constant PCTL \ PSC Control Register
- $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
- $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
- $02 constant PCTL_PCCYC \ PSC Complete Cycle
- $01 constant PCTL_PRUN \ PSC Run
-&182 constant POC \ PSC Output Configuration
- $20 constant POC_POEN2B \ PSC Output 2B Enable
- $10 constant POC_POEN2A \ PSC Output 2A Enable
- $08 constant POC_POEN1B \ PSC Output 1B Enable
- $04 constant POC_POEN1A \ PSC Output 1A Enable
- $02 constant POC_POEN0B \ PSC Output 0B Enable
- $01 constant POC_POEN0A \ PSC Output 0A Enable
-&181 constant PCNF \ PSC Configuration Register
- $20 constant PCNF_PULOCK \ PSC Update Lock
- $10 constant PCNF_PMODE \ PSC Mode
- $08 constant PCNF_POPB \ PSC Output B Polarity
- $04 constant PCNF_POPA \ PSC Output A Polarity
-&180 constant PSYNC \ PSC Synchro Configuration
- $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
- $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
- $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
-&178 constant POCR_RB \ PSC Output Compare RB Register
-&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
-&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
-&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
-&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
-&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
-&166 constant POCR1SA \ PSC Output Compare SA Register
-&164 constant POCR0SB \ PSC Output Compare SB Register
-&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
-&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
-
-\ Interrupts
-&2 constant ANACOMP0Addr \ Analog Comparator 0
-&4 constant ANACOMP1Addr \ Analog Comparator 1
-&6 constant ANACOMP2Addr \ Analog Comparator 2
-&8 constant ANACOMP3Addr \ Analog Comparator 3
-&10 constant PSC_FAULTAddr \ PSC Fault
-&12 constant PSC_ECAddr \ PSC End of Cycle
-&14 constant INT0Addr \ External Interrupt Request 0
-&16 constant INT1Addr \ External Interrupt Request 1
-&18 constant INT2Addr \ External Interrupt Request 2
-&20 constant INT3Addr \ External Interrupt Request 3
-&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
-&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
-&38 constant CAN_TOVFAddr \ CAN Timer Overflow
-&40 constant LIN_TCAddr \ LIN Transfer Complete
-&42 constant LIN_ERRAddr \ LIN Error
-&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&54 constant ADCAddr \ ADC Conversion Complete
-&56 constant WDTAddr \ Watchdog Time-Out Interrupt
-&58 constant EE_READYAddr \ EEPROM Ready
-&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.asm b/amforth-6.5/avr8/devices/atmega64m1/device.asm
deleted file mode 100644
index 7441fc3..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega64M1
-; generated automatically, do not edit
-
-.nolist
- .include "m64M1def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_CAN = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_DA_CONVERTER = 0
-.set WANT_CPU = 0
-.set WANT_PORTE = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_LINUART = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_EEPROM = 0
-.set WANT_PSC = 0
-.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; Analog Comparator 0
-.org 4
- rcall isr ; Analog Comparator 1
-.org 6
- rcall isr ; Analog Comparator 2
-.org 8
- rcall isr ; Analog Comparator 3
-.org 10
- rcall isr ; PSC Fault
-.org 12
- rcall isr ; PSC End of Cycle
-.org 14
- rcall isr ; External Interrupt Request 0
-.org 16
- rcall isr ; External Interrupt Request 1
-.org 18
- rcall isr ; External Interrupt Request 2
-.org 20
- rcall isr ; External Interrupt Request 3
-.org 22
- rcall isr ; Timer/Counter1 Capture Event
-.org 24
- rcall isr ; Timer/Counter1 Compare Match A
-.org 26
- rcall isr ; Timer/Counter1 Compare Match B
-.org 28
- rcall isr ; Timer1/Counter1 Overflow
-.org 30
- rcall isr ; Timer/Counter0 Compare Match A
-.org 32
- rcall isr ; Timer/Counter0 Compare Match B
-.org 34
- rcall isr ; Timer/Counter0 Overflow
-.org 36
- rcall isr ; CAN MOB, Burst, General Errors
-.org 38
- rcall isr ; CAN Timer Overflow
-.org 40
- rcall isr ; LIN Transfer Complete
-.org 42
- rcall isr ; LIN Error
-.org 44
- rcall isr ; Pin Change Interrupt Request 0
-.org 46
- rcall isr ; Pin Change Interrupt Request 1
-.org 48
- rcall isr ; Pin Change Interrupt Request 2
-.org 50
- rcall isr ; Pin Change Interrupt Request 3
-.org 52
- rcall isr ; SPI Serial Transfer Complete
-.org 54
- rcall isr ; ADC Conversion Complete
-.org 56
- rcall isr ; Watchdog Time-Out Interrupt
-.org 58
- rcall isr ; EEPROM Ready
-.org 60
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 4096
-mcu_eepromsize:
- .dw 2048
-mcu_maxdp:
- .dw 57344
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega64M1"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.inc b/amforth-6.5/avr8/devices/atmega64m1/device.inc
deleted file mode 100644
index fa67589..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/device.inc
+++ /dev/null
@@ -1,1734 +0,0 @@
-; Partname: ATmega64M1
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_CAN == 1
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Control Register
-VE_CANGCON:
- .dw $ff07
- .db "CANGCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGCON
-XT_CANGCON:
- .dw PFA_DOVARIABLE
-PFA_CANGCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Status Register
-VE_CANGSTA:
- .dw $ff07
- .db "CANGSTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGSTA
-XT_CANGSTA:
- .dw PFA_DOVARIABLE
-PFA_CANGSTA:
- .dw 217
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Register Flags
-VE_CANGIT:
- .dw $ff06
- .db "CANGIT"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIT
-XT_CANGIT:
- .dw PFA_DOVARIABLE
-PFA_CANGIT:
- .dw 218
-; ( -- addr ) System Constant
-; R( -- )
-; CAN General Interrupt Enable Register
-VE_CANGIE:
- .dw $ff06
- .db "CANGIE"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANGIE
-XT_CANGIE:
- .dw PFA_DOVARIABLE
-PFA_CANGIE:
- .dw 219
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 2
-VE_CANEN2:
- .dw $ff06
- .db "CANEN2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN2
-XT_CANEN2:
- .dw PFA_DOVARIABLE
-PFA_CANEN2:
- .dw 220
-; ( -- addr ) System Constant
-; R( -- )
-; Enable MOb Register 1(empty)
-VE_CANEN1:
- .dw $ff06
- .db "CANEN1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANEN1
-XT_CANEN1:
- .dw PFA_DOVARIABLE
-PFA_CANEN1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 2
-VE_CANIE2:
- .dw $ff06
- .db "CANIE2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE2
-XT_CANIE2:
- .dw PFA_DOVARIABLE
-PFA_CANIE2:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Enable Interrupt MOb Register 1 (empty)
-VE_CANIE1:
- .dw $ff06
- .db "CANIE1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIE1
-XT_CANIE1:
- .dw PFA_DOVARIABLE
-PFA_CANIE1:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 2
-VE_CANSIT2:
- .dw $ff07
- .db "CANSIT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT2
-XT_CANSIT2:
- .dw PFA_DOVARIABLE
-PFA_CANSIT2:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Status Interrupt MOb Register 1 (empty)
-VE_CANSIT1:
- .dw $ff07
- .db "CANSIT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSIT1
-XT_CANSIT1:
- .dw PFA_DOVARIABLE
-PFA_CANSIT1:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 1
-VE_CANBT1:
- .dw $ff06
- .db "CANBT1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT1
-XT_CANBT1:
- .dw PFA_DOVARIABLE
-PFA_CANBT1:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 2
-VE_CANBT2:
- .dw $ff06
- .db "CANBT2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT2
-XT_CANBT2:
- .dw PFA_DOVARIABLE
-PFA_CANBT2:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; CAN Bit Timing Register 3
-VE_CANBT3:
- .dw $ff06
- .db "CANBT3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANBT3
-XT_CANBT3:
- .dw PFA_DOVARIABLE
-PFA_CANBT3:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Control Register
-VE_CANTCON:
- .dw $ff07
- .db "CANTCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTCON
-XT_CANTCON:
- .dw PFA_DOVARIABLE
-PFA_CANTCON:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register Low
-VE_CANTIML:
- .dw $ff07
- .db "CANTIML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIML
-XT_CANTIML:
- .dw PFA_DOVARIABLE
-PFA_CANTIML:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Register High
-VE_CANTIMH:
- .dw $ff07
- .db "CANTIMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTIMH
-XT_CANTIMH:
- .dw PFA_DOVARIABLE
-PFA_CANTIMH:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register Low
-VE_CANTTCL:
- .dw $ff07
- .db "CANTTCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCL
-XT_CANTTCL:
- .dw PFA_DOVARIABLE
-PFA_CANTTCL:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; TTC Timer Register High
-VE_CANTTCH:
- .dw $ff07
- .db "CANTTCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTTCH
-XT_CANTTCH:
- .dw PFA_DOVARIABLE
-PFA_CANTTCH:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Transmit Error Counter Register
-VE_CANTEC:
- .dw $ff06
- .db "CANTEC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANTEC
-XT_CANTEC:
- .dw PFA_DOVARIABLE
-PFA_CANTEC:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Receive Error Counter Register
-VE_CANREC:
- .dw $ff06
- .db "CANREC"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANREC
-XT_CANREC:
- .dw PFA_DOVARIABLE
-PFA_CANREC:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Highest Priority MOb Register
-VE_CANHPMOB:
- .dw $ff08
- .db "CANHPMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANHPMOB
-XT_CANHPMOB:
- .dw PFA_DOVARIABLE
-PFA_CANHPMOB:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Page MOb Register
-VE_CANPAGE:
- .dw $ff07
- .db "CANPAGE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANPAGE
-XT_CANPAGE:
- .dw PFA_DOVARIABLE
-PFA_CANPAGE:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Status Register
-VE_CANSTMOB:
- .dw $ff08
- .db "CANSTMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMOB
-XT_CANSTMOB:
- .dw PFA_DOVARIABLE
-PFA_CANSTMOB:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; MOb Control and DLC Register
-VE_CANCDMOB:
- .dw $ff08
- .db "CANCDMOB"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANCDMOB
-XT_CANCDMOB:
- .dw PFA_DOVARIABLE
-PFA_CANCDMOB:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 4
-VE_CANIDT4:
- .dw $ff07
- .db "CANIDT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT4
-XT_CANIDT4:
- .dw PFA_DOVARIABLE
-PFA_CANIDT4:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 3
-VE_CANIDT3:
- .dw $ff07
- .db "CANIDT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT3
-XT_CANIDT3:
- .dw PFA_DOVARIABLE
-PFA_CANIDT3:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 2
-VE_CANIDT2:
- .dw $ff07
- .db "CANIDT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT2
-XT_CANIDT2:
- .dw PFA_DOVARIABLE
-PFA_CANIDT2:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Tag Register 1
-VE_CANIDT1:
- .dw $ff07
- .db "CANIDT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDT1
-XT_CANIDT1:
- .dw PFA_DOVARIABLE
-PFA_CANIDT1:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 4
-VE_CANIDM4:
- .dw $ff07
- .db "CANIDM4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM4
-XT_CANIDM4:
- .dw PFA_DOVARIABLE
-PFA_CANIDM4:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 3
-VE_CANIDM3:
- .dw $ff07
- .db "CANIDM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM3
-XT_CANIDM3:
- .dw PFA_DOVARIABLE
-PFA_CANIDM3:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 2
-VE_CANIDM2:
- .dw $ff07
- .db "CANIDM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM2
-XT_CANIDM2:
- .dw PFA_DOVARIABLE
-PFA_CANIDM2:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Identifier Mask Register 1
-VE_CANIDM1:
- .dw $ff07
- .db "CANIDM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANIDM1
-XT_CANIDM1:
- .dw PFA_DOVARIABLE
-PFA_CANIDM1:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register Low
-VE_CANSTML:
- .dw $ff07
- .db "CANSTML",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTML
-XT_CANSTML:
- .dw PFA_DOVARIABLE
-PFA_CANSTML:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Time Stamp Register High
-VE_CANSTMH:
- .dw $ff07
- .db "CANSTMH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CANSTMH
-XT_CANSTMH:
- .dw PFA_DOVARIABLE
-PFA_CANSTMH:
- .dw 249
-; ( -- addr ) System Constant
-; R( -- )
-; Message Data Register
-VE_CANMSG:
- .dw $ff06
- .db "CANMSG"
- .dw VE_HEAD
- .set VE_HEAD=VE_CANMSG
-XT_CANMSG:
- .dw PFA_DOVARIABLE
-PFA_CANMSG:
- .dw 250
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 0 Control Register
-VE_AC0CON:
- .dw $ff06
- .db "AC0CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC0CON
-XT_AC0CON:
- .dw PFA_DOVARIABLE
-PFA_AC0CON:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 1 Control Register
-VE_AC1CON:
- .dw $ff06
- .db "AC1CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC1CON
-XT_AC1CON:
- .dw PFA_DOVARIABLE
-PFA_AC1CON:
- .dw 149
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 2 Control Register
-VE_AC2CON:
- .dw $ff06
- .db "AC2CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC2CON
-XT_AC2CON:
- .dw PFA_DOVARIABLE
-PFA_AC2CON:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator 3 Control Register
-VE_AC3CON:
- .dw $ff06
- .db "AC3CON"
- .dw VE_HEAD
- .set VE_HEAD=VE_AC3CON
-XT_AC3CON:
- .dw PFA_DOVARIABLE
-PFA_AC3CON:
- .dw 151
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-
-.endif
-.if WANT_DA_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register High Byte
-VE_DACH:
- .dw $ff04
- .db "DACH"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACH
-XT_DACH:
- .dw PFA_DOVARIABLE
-PFA_DACH:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Data Register Low Byte
-VE_DACL:
- .dw $ff04
- .db "DACL"
- .dw VE_HEAD
- .set VE_HEAD=VE_DACL
-XT_DACL:
- .dw PFA_DOVARIABLE
-PFA_DACL:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; DAC Control Register
-VE_DACON:
- .dw $ff05
- .db "DACON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DACON
-XT_DACON:
- .dw PFA_DOVARIABLE
-PFA_DACON:
- .dw 144
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 57
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Control And Status Register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP0CSR:
- .dw $ff07
- .db "AMP0CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP0CSR
-XT_AMP0CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP0CSR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP1CSR:
- .dw $ff07
- .db "AMP1CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP1CSR
-XT_AMP1CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP1CSR:
- .dw 118
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_AMP2CSR:
- .dw $ff07
- .db "AMP2CSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AMP2CSR
-XT_AMP2CSR:
- .dw PFA_DOVARIABLE
-PFA_AMP2CSR:
- .dw 119
-
-.endif
-.if WANT_LINUART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Control Register
-VE_LINCR:
- .dw $ff05
- .db "LINCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINCR
-XT_LINCR:
- .dw PFA_DOVARIABLE
-PFA_LINCR:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Status and Interrupt Register
-VE_LINSIR:
- .dw $ff06
- .db "LINSIR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSIR
-XT_LINSIR:
- .dw PFA_DOVARIABLE
-PFA_LINSIR:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Enable Interrupt Register
-VE_LINENIR:
- .dw $ff07
- .db "LINENIR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINENIR
-XT_LINENIR:
- .dw PFA_DOVARIABLE
-PFA_LINENIR:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Error Register
-VE_LINERR:
- .dw $ff06
- .db "LINERR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINERR
-XT_LINERR:
- .dw PFA_DOVARIABLE
-PFA_LINERR:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Bit Timing Register
-VE_LINBTR:
- .dw $ff06
- .db "LINBTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBTR
-XT_LINBTR:
- .dw PFA_DOVARIABLE
-PFA_LINBTR:
- .dw 204
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate Low Register
-VE_LINBRRL:
- .dw $ff07
- .db "LINBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRL
-XT_LINBRRL:
- .dw PFA_DOVARIABLE
-PFA_LINBRRL:
- .dw 205
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Baud Rate High Register
-VE_LINBRRH:
- .dw $ff07
- .db "LINBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LINBRRH
-XT_LINBRRH:
- .dw PFA_DOVARIABLE
-PFA_LINBRRH:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Length Register
-VE_LINDLR:
- .dw $ff06
- .db "LINDLR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDLR
-XT_LINDLR:
- .dw PFA_DOVARIABLE
-PFA_LINDLR:
- .dw 207
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Identifier Register
-VE_LINIDR:
- .dw $ff06
- .db "LINIDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINIDR
-XT_LINIDR:
- .dw PFA_DOVARIABLE
-PFA_LINIDR:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Buffer Selection Register
-VE_LINSEL:
- .dw $ff06
- .db "LINSEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINSEL
-XT_LINSEL:
- .dw PFA_DOVARIABLE
-PFA_LINSEL:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-; LIN Data Register
-VE_LINDAT:
- .dw $ff06
- .db "LINDAT"
- .dw VE_HEAD
- .set VE_HEAD=VE_LINDAT
-XT_LINDAT:
- .dw PFA_DOVARIABLE
-PFA_LINDAT:
- .dw 210
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_PSC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Interrupt Flag Register
-VE_PIFR:
- .dw $ff04
- .db "PIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIFR
-XT_PIFR:
- .dw PFA_DOVARIABLE
-PFA_PIFR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Interrupt Mask Register
-VE_PIM:
- .dw $ff03
- .db "PIM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PIM
-XT_PIM:
- .dw PFA_DOVARIABLE
-PFA_PIM:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Input Control Register
-VE_PMIC2:
- .dw $ff05
- .db "PMIC2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC2
-XT_PMIC2:
- .dw PFA_DOVARIABLE
-PFA_PMIC2:
- .dw 186
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Input Control Register
-VE_PMIC1:
- .dw $ff05
- .db "PMIC1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC1
-XT_PMIC1:
- .dw PFA_DOVARIABLE
-PFA_PMIC1:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Input Control Register
-VE_PMIC0:
- .dw $ff05
- .db "PMIC0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PMIC0
-XT_PMIC0:
- .dw PFA_DOVARIABLE
-PFA_PMIC0:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Control Register
-VE_PCTL:
- .dw $ff04
- .db "PCTL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCTL
-XT_PCTL:
- .dw PFA_DOVARIABLE
-PFA_PCTL:
- .dw 183
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Configuration
-VE_POC:
- .dw $ff03
- .db "POC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POC
-XT_POC:
- .dw PFA_DOVARIABLE
-PFA_POC:
- .dw 182
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Configuration Register
-VE_PCNF:
- .dw $ff04
- .db "PCNF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCNF
-XT_PCNF:
- .dw PFA_DOVARIABLE
-PFA_PCNF:
- .dw 181
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Synchro Configuration
-VE_PSYNC:
- .dw $ff05
- .db "PSYNC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PSYNC
-XT_PSYNC:
- .dw PFA_DOVARIABLE
-PFA_PSYNC:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare RB Register
-VE_POCR_RB:
- .dw $ff07
- .db "POCR_RB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR_RB
-XT_POCR_RB:
- .dw PFA_DOVARIABLE
-PFA_POCR_RB:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare SB Register
-VE_POCR2SB:
- .dw $ff07
- .db "POCR2SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2SB
-XT_POCR2SB:
- .dw PFA_DOVARIABLE
-PFA_POCR2SB:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare RA Register
-VE_POCR2RA:
- .dw $ff07
- .db "POCR2RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2RA
-XT_POCR2RA:
- .dw PFA_DOVARIABLE
-PFA_POCR2RA:
- .dw 174
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 2 Output Compare SA Register
-VE_POCR2SA:
- .dw $ff07
- .db "POCR2SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR2SA
-XT_POCR2SA:
- .dw PFA_DOVARIABLE
-PFA_POCR2SA:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Output Compare SB Register
-VE_POCR1SB:
- .dw $ff07
- .db "POCR1SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1SB
-XT_POCR1SB:
- .dw PFA_DOVARIABLE
-PFA_POCR1SB:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 1 Output Compare RA Register
-VE_POCR1RA:
- .dw $ff07
- .db "POCR1RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1RA
-XT_POCR1RA:
- .dw PFA_DOVARIABLE
-PFA_POCR1RA:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare SA Register
-VE_POCR1SA:
- .dw $ff07
- .db "POCR1SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR1SA
-XT_POCR1SA:
- .dw PFA_DOVARIABLE
-PFA_POCR1SA:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Output Compare SB Register
-VE_POCR0SB:
- .dw $ff07
- .db "POCR0SB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0SB
-XT_POCR0SB:
- .dw PFA_DOVARIABLE
-PFA_POCR0SB:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Output Compare RA Register
-VE_POCR0RA:
- .dw $ff07
- .db "POCR0RA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0RA
-XT_POCR0RA:
- .dw PFA_DOVARIABLE
-PFA_POCR0RA:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; PSC Module 0 Output Compare SA Register
-VE_POCR0SA:
- .dw $ff07
- .db "POCR0SA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_POCR0SA
-XT_POCR0SA:
- .dw PFA_DOVARIABLE
-PFA_POCR0SA:
- .dw 160
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.py b/amforth-6.5/avr8/devices/atmega64m1/device.py
deleted file mode 100644
index c6482be..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/device.py
+++ /dev/null
@@ -1,495 +0,0 @@
-# Partname: ATmega64M1
-# generated automatically, do not edit
-MCUREGS = {
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTC': '&40',
- 'DDRC': '&39',
- 'PINC': '&38',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'CANGCON': '&216',
- 'CANGCON_ABRQ': '$80',
- 'CANGCON_OVRQ': '$40',
- 'CANGCON_TTC': '$20',
- 'CANGCON_SYNTTC': '$10',
- 'CANGCON_LISTEN': '$08',
- 'CANGCON_TEST': '$04',
- 'CANGCON_ENASTB': '$02',
- 'CANGCON_SWRES': '$01',
- 'CANGSTA': '&217',
- 'CANGSTA_OVFG': '$40',
- 'CANGSTA_TXBSY': '$10',
- 'CANGSTA_RXBSY': '$08',
- 'CANGSTA_ENFG': '$04',
- 'CANGSTA_BOFF': '$02',
- 'CANGSTA_ERRP': '$01',
- 'CANGIT': '&218',
- 'CANGIT_CANIT': '$80',
- 'CANGIT_BOFFIT': '$40',
- 'CANGIT_OVRTIM': '$20',
- 'CANGIT_BXOK': '$10',
- 'CANGIT_SERG': '$08',
- 'CANGIT_CERG': '$04',
- 'CANGIT_FERG': '$02',
- 'CANGIT_AERG': '$01',
- 'CANGIE': '&219',
- 'CANGIE_ENIT': '$80',
- 'CANGIE_ENBOFF': '$40',
- 'CANGIE_ENRX': '$20',
- 'CANGIE_ENTX': '$10',
- 'CANGIE_ENERR': '$08',
- 'CANGIE_ENBX': '$04',
- 'CANGIE_ENERG': '$02',
- 'CANGIE_ENOVRT': '$01',
- 'CANEN2': '&220',
- 'CANEN2_ENMOB': '$3F',
- 'CANEN1': '&221',
- 'CANIE2': '&222',
- 'CANIE2_IEMOB': '$3F',
- 'CANIE1': '&223',
- 'CANSIT2': '&224',
- 'CANSIT2_SIT': '$3F',
- 'CANSIT1': '&225',
- 'CANBT1': '&226',
- 'CANBT1_BRP': '$7E',
- 'CANBT2': '&227',
- 'CANBT2_SJW': '$60',
- 'CANBT2_PRS': '$0E',
- 'CANBT3': '&228',
- 'CANBT3_PHS2': '$70',
- 'CANBT3_PHS1': '$0E',
- 'CANBT3_SMP': '$01',
- 'CANTCON': '&229',
- 'CANTIML': '&230',
- 'CANTIMH': '&231',
- 'CANTTCL': '&232',
- 'CANTTCH': '&233',
- 'CANTEC': '&234',
- 'CANREC': '&235',
- 'CANHPMOB': '&236',
- 'CANHPMOB_HPMOB': '$F0',
- 'CANHPMOB_CGP': '$0F',
- 'CANPAGE': '&237',
- 'CANPAGE_MOBNB': '$F0',
- 'CANPAGE_AINC': '$08',
- 'CANPAGE_INDX': '$07',
- 'CANSTMOB': '&238',
- 'CANSTMOB_DLCW': '$80',
- 'CANSTMOB_TXOK': '$40',
- 'CANSTMOB_RXOK': '$20',
- 'CANSTMOB_BERR': '$10',
- 'CANSTMOB_SERR': '$08',
- 'CANSTMOB_CERR': '$04',
- 'CANSTMOB_FERR': '$02',
- 'CANSTMOB_AERR': '$01',
- 'CANCDMOB': '&239',
- 'CANCDMOB_CONMOB': '$C0',
- 'CANCDMOB_RPLV': '$20',
- 'CANCDMOB_IDE': '$10',
- 'CANCDMOB_DLC': '$0F',
- 'CANIDT4': '&240',
- 'CANIDT4_IDT': '$F8',
- 'CANIDT4_RTRTAG': '$04',
- 'CANIDT4_RB1TAG': '$02',
- 'CANIDT4_RB0TAG': '$01',
- 'CANIDT3': '&241',
- 'CANIDT2': '&242',
- 'CANIDT1': '&243',
- 'CANIDM4': '&244',
- 'CANIDM3': '&245',
- 'CANIDM2': '&246',
- 'CANIDM1': '&247',
- 'CANSTML': '&248',
- 'CANSTMH': '&249',
- 'CANMSG': '&250',
- 'AC0CON': '&148',
- 'AC0CON_AC0EN': '$80',
- 'AC0CON_AC0IE': '$40',
- 'AC0CON_AC0IS': '$30',
- 'AC0CON_ACCKSEL': '$08',
- 'AC0CON_AC0M': '$07',
- 'AC1CON': '&149',
- 'AC1CON_AC1EN': '$80',
- 'AC1CON_AC1IE': '$40',
- 'AC1CON_AC1IS': '$30',
- 'AC1CON_AC1ICE': '$08',
- 'AC1CON_AC1M': '$07',
- 'AC2CON': '&150',
- 'AC2CON_AC2EN': '$80',
- 'AC2CON_AC2IE': '$40',
- 'AC2CON_AC2IS': '$30',
- 'AC2CON_AC2M': '$07',
- 'AC3CON': '&151',
- 'AC3CON_AC3EN': '$80',
- 'AC3CON_AC3IE': '$40',
- 'AC3CON_AC3IS': '$30',
- 'AC3CON_AC3M': '$07',
- 'ACSR': '&80',
- 'ACSR_AC3IF': '$80',
- 'ACSR_AC2IF': '$40',
- 'ACSR_AC1IF': '$20',
- 'ACSR_AC0IF': '$10',
- 'ACSR_AC3O': '$08',
- 'ACSR_AC2O': '$04',
- 'ACSR_AC1O': '$02',
- 'ACSR_AC0O': '$01',
- 'DACH': '&146',
- 'DACH_DACH': '$FF',
- 'DACL': '&145',
- 'DACL_DACL': '$FF',
- 'DACON': '&144',
- 'DACON_DAATE': '$80',
- 'DACON_DATS': '$70',
- 'DACON_DALA': '$04',
- 'DACON_DAEN': '$01',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_SIGRD': '$20',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SPMEN': '$01',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'MCUCR': '&85',
- 'MCUCR_SPIPS': '$80',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'GPIOR2': '&58',
- 'GPIOR2_GPIOR': '$FF',
- 'GPIOR1': '&57',
- 'GPIOR1_GPIOR': '$FF',
- 'GPIOR0': '&62',
- 'GPIOR0_GPIOR07': '$80',
- 'GPIOR0_GPIOR06': '$40',
- 'GPIOR0_GPIOR05': '$20',
- 'GPIOR0_GPIOR04': '$10',
- 'GPIOR0_GPIOR03': '$08',
- 'GPIOR0_GPIOR02': '$04',
- 'GPIOR0_GPIOR01': '$02',
- 'GPIOR0_GPIOR00': '$01',
- 'PLLCSR': '&73',
- 'PLLCSR_PLLF': '$04',
- 'PLLCSR_PLLE': '$02',
- 'PLLCSR_PLOCK': '$01',
- 'PRR': '&100',
- 'PRR_PRCAN': '$40',
- 'PRR_PRPSC': '$20',
- 'PRR_PRTIM1': '$10',
- 'PRR_PRTIM0': '$08',
- 'PRR_PRSPI': '$04',
- 'PRR_PRLIN': '$02',
- 'PRR_PRADC': '$01',
- 'PORTE': '&46',
- 'DDRE': '&45',
- 'PINE': '&44',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCNT0': '&70',
- 'OCR0A': '&71',
- 'OCR0B': '&72',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_ICPSEL1': '$40',
- 'GTCCR_PSR10': '$01',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'ICR1': '&134',
- 'ADMUX': '&124',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$1F',
- 'ADCSRA': '&122',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADC': '&120',
- 'ADCSRB': '&123',
- 'ADCSRB_ADHSM': '$80',
- 'ADCSRB_ISRCEN': '$40',
- 'ADCSRB_AREFEN': '$20',
- 'ADCSRB_ADTS': '$0F',
- 'DIDR0': '&126',
- 'DIDR0_ADC7D': '$80',
- 'DIDR0_ADC6D': '$40',
- 'DIDR0_ADC5D': '$20',
- 'DIDR0_ADC4D': '$10',
- 'DIDR0_ADC3D': '$08',
- 'DIDR0_ADC2D': '$04',
- 'DIDR0_ADC1D': '$02',
- 'DIDR0_ADC0D': '$01',
- 'DIDR1': '&127',
- 'DIDR1_AMP2PD': '$40',
- 'DIDR1_ACMP0D': '$20',
- 'DIDR1_AMP0PD': '$10',
- 'DIDR1_AMP0ND': '$08',
- 'DIDR1_ADC10D': '$04',
- 'DIDR1_ADC9D': '$02',
- 'DIDR1_ADC8D': '$01',
- 'AMP0CSR': '&117',
- 'AMP0CSR_AMP0EN': '$80',
- 'AMP0CSR_AMP0IS': '$40',
- 'AMP0CSR_AMP0G': '$30',
- 'AMP0CSR_AMPCMP0': '$08',
- 'AMP0CSR_AMP0TS': '$07',
- 'AMP1CSR': '&118',
- 'AMP1CSR_AMP1EN': '$80',
- 'AMP1CSR_AMP1IS': '$40',
- 'AMP1CSR_AMP1G': '$30',
- 'AMP1CSR_AMPCMP1': '$08',
- 'AMP1CSR_AMP1TS': '$07',
- 'AMP2CSR': '&119',
- 'AMP2CSR_AMP2EN': '$80',
- 'AMP2CSR_AMP2IS': '$40',
- 'AMP2CSR_AMP2G': '$30',
- 'AMP2CSR_AMPCMP2': '$08',
- 'AMP2CSR_AMP2TS': '$07',
- 'LINCR': '&200',
- 'LINCR_LSWRES': '$80',
- 'LINCR_LIN13': '$40',
- 'LINCR_LCONF': '$30',
- 'LINCR_LENA': '$08',
- 'LINCR_LCMD': '$07',
- 'LINSIR': '&201',
- 'LINSIR_LIDST': '$E0',
- 'LINSIR_LBUSY': '$10',
- 'LINSIR_LERR': '$08',
- 'LINSIR_LIDOK': '$04',
- 'LINSIR_LTXOK': '$02',
- 'LINSIR_LRXOK': '$01',
- 'LINENIR': '&202',
- 'LINENIR_LENERR': '$08',
- 'LINENIR_LENIDOK': '$04',
- 'LINENIR_LENTXOK': '$02',
- 'LINENIR_LENRXOK': '$01',
- 'LINERR': '&203',
- 'LINERR_LABORT': '$80',
- 'LINERR_LTOERR': '$40',
- 'LINERR_LOVERR': '$20',
- 'LINERR_LFERR': '$10',
- 'LINERR_LSERR': '$08',
- 'LINERR_LPERR': '$04',
- 'LINERR_LCERR': '$02',
- 'LINERR_LBERR': '$01',
- 'LINBTR': '&204',
- 'LINBTR_LDISR': '$80',
- 'LINBTR_LBT': '$3F',
- 'LINBRRL': '&205',
- 'LINBRRL_LDIV': '$FF',
- 'LINBRRH': '&206',
- 'LINBRRH_LDIV': '$0F',
- 'LINDLR': '&207',
- 'LINDLR_LTXDL': '$F0',
- 'LINDLR_LRXDL': '$0F',
- 'LINIDR': '&208',
- 'LINIDR_LP': '$C0',
- 'LINIDR_LID': '$3F',
- 'LINSEL': '&209',
- 'LINSEL_LAINC': '$08',
- 'LINSEL_LINDX': '$07',
- 'LINDAT': '&210',
- 'LINDAT_LDATA': '$FF',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPDR': '&78',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'EICRA': '&105',
- 'EICRA_ISC3': '$C0',
- 'EICRA_ISC2': '$30',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$0F',
- 'EIFR': '&60',
- 'EIFR_INTF': '$0F',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$0F',
- 'PCMSK3': '&109',
- 'PCMSK3_PCINT': '$07',
- 'PCMSK2': '&108',
- 'PCMSK2_PCINT': '$FF',
- 'PCMSK1': '&107',
- 'PCMSK1_PCINT': '$FF',
- 'PCMSK0': '&106',
- 'PCMSK0_PCINT': '$FF',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$0F',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'PIFR': '&188',
- 'PIFR_PEV': '$0E',
- 'PIFR_PEOP': '$01',
- 'PIM': '&187',
- 'PIM_PEVE': '$0E',
- 'PIM_PEOPE': '$01',
- 'PMIC2': '&186',
- 'PMIC2_POVEN2': '$80',
- 'PMIC2_PISEL2': '$40',
- 'PMIC2_PELEV2': '$20',
- 'PMIC2_PFLTE2': '$10',
- 'PMIC2_PAOC2': '$08',
- 'PMIC2_PRFM2': '$07',
- 'PMIC1': '&185',
- 'PMIC1_POVEN1': '$80',
- 'PMIC1_PISEL1': '$40',
- 'PMIC1_PELEV1': '$20',
- 'PMIC1_PFLTE1': '$10',
- 'PMIC1_PAOC1': '$08',
- 'PMIC1_PRFM1': '$07',
- 'PMIC0': '&184',
- 'PMIC0_POVEN0': '$80',
- 'PMIC0_PISEL0': '$40',
- 'PMIC0_PELEV0': '$20',
- 'PMIC0_PFLTE0': '$10',
- 'PMIC0_PAOC0': '$08',
- 'PMIC0_PRFM0': '$07',
- 'PCTL': '&183',
- 'PCTL_PPRE': '$C0',
- 'PCTL_PCLKSEL': '$20',
- 'PCTL_PCCYC': '$02',
- 'PCTL_PRUN': '$01',
- 'POC': '&182',
- 'POC_POEN2B': '$20',
- 'POC_POEN2A': '$10',
- 'POC_POEN1B': '$08',
- 'POC_POEN1A': '$04',
- 'POC_POEN0B': '$02',
- 'POC_POEN0A': '$01',
- 'PCNF': '&181',
- 'PCNF_PULOCK': '$20',
- 'PCNF_PMODE': '$10',
- 'PCNF_POPB': '$08',
- 'PCNF_POPA': '$04',
- 'PSYNC': '&180',
- 'PSYNC_PSYNC2': '$30',
- 'PSYNC_PSYNC1': '$0C',
- 'PSYNC_PSYNC0': '$03',
- 'POCR_RB': '&178',
- 'POCR2SB': '&176',
- 'POCR2RA': '&174',
- 'POCR2SA': '&172',
- 'POCR1SB': '&170',
- 'POCR1RA': '&168',
- 'POCR1SA': '&166',
- 'POCR0SB': '&164',
- 'POCR0RA': '&162',
- 'POCR0SA': '&160',
- 'ANACOMP0Addr': '2',
- 'ANACOMP1Addr': '4',
- 'ANACOMP2Addr': '6',
- 'ANACOMP3Addr': '8',
- 'PSC_FAULTAddr': '10',
- 'PSC_ECAddr': '12',
- 'INT0Addr': '14',
- 'INT1Addr': '16',
- 'INT2Addr': '18',
- 'INT3Addr': '20',
- 'TIMER1_CAPTAddr': '22',
- 'TIMER1_COMPAAddr': '24',
- 'TIMER1_COMPBAddr': '26',
- 'TIMER1_OVFAddr': '28',
- 'TIMER0_COMPAAddr': '30',
- 'TIMER0_COMPBAddr': '32',
- 'TIMER0_OVFAddr': '34',
- 'CAN_INTAddr': '36',
- 'CAN_TOVFAddr': '38',
- 'LIN_TCAddr': '40',
- 'LIN_ERRAddr': '42',
- 'PCINT0Addr': '44',
- 'PCINT1Addr': '46',
- 'PCINT2Addr': '48',
- 'PCINT3Addr': '50',
- 'SPI__STCAddr': '52',
- 'ADCAddr': '54',
- 'WDTAddr': '56',
- 'EE_READYAddr': '58',
- 'SPM_READYAddr': '60'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/atmega8.frt b/amforth-6.5/avr8/devices/atmega8/atmega8.frt
deleted file mode 100644
index 0149247..0000000
--- a/amforth-6.5/avr8/devices/atmega8/atmega8.frt
+++ /dev/null
@@ -1,207 +0,0 @@
-\ Partname: ATmega8
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&80 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
-&85 constant MCUCR \ MCU Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-\ TIMER_COUNTER_0
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-&83 constant TCCR0 \ Timer/Counter0 Control Register
- $04 constant TCCR0_CS02 \ Clock Select0 bit 2
- $02 constant TCCR0_CS01 \ Clock Select0 bit 1
- $01 constant TCCR0_CS00 \ Clock Select0 bit 0
-&82 constant TCNT0 \ Timer Counter 0
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&84 constant MCUCSR \ MCU Control And Status Register
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&81 constant OSCCAL \ Oscillator Calibration Value
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADFR \ ADC Free Running Select
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&10 constant SPI__STCAddr \ Serial Transfer Complete
-&11 constant USART__RXCAddr \ USART, Rx Complete
-&12 constant USART__UDREAddr \ USART Data Register Empty
-&13 constant USART__TXCAddr \ USART, Tx Complete
-&14 constant ADCAddr \ ADC Conversion Complete
-&15 constant EE_RDYAddr \ EEPROM Ready
-&16 constant ANA_COMPAddr \ Analog Comparator
-&17 constant TWIAddr \ 2-wire Serial Interface
-&18 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8/device.asm b/amforth-6.5/avr8/devices/atmega8/device.asm
deleted file mode 100644
index d822d36..0000000
--- a/amforth-6.5/avr8/devices/atmega8/device.asm
+++ /dev/null
@@ -1,95 +0,0 @@
-; Partname: ATmega8
-; generated automatically, do not edit
-
-.nolist
- .include "m8def.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_USART = 0
-.set WANT_TWI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Timer/Counter2 Compare Match
-.org 4
- rcall isr ; Timer/Counter2 Overflow
-.org 5
- rcall isr ; Timer/Counter1 Capture Event
-.org 6
- rcall isr ; Timer/Counter1 Compare Match A
-.org 7
- rcall isr ; Timer/Counter1 Compare Match B
-.org 8
- rcall isr ; Timer/Counter1 Overflow
-.org 9
- rcall isr ; Timer/Counter0 Overflow
-.org 10
- rcall isr ; Serial Transfer Complete
-.org 11
- rcall isr ; USART, Rx Complete
-.org 12
- rcall isr ; USART Data Register Empty
-.org 13
- rcall isr ; USART, Tx Complete
-.org 14
- rcall isr ; ADC Conversion Complete
-.org 15
- rcall isr ; EEPROM Ready
-.org 16
- rcall isr ; Analog Comparator
-.org 17
- rcall isr ; 2-wire Serial Interface
-.org 18
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 19
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 19
-mcu_name:
- .dw 7
- .db "ATmega8",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8/device.inc b/amforth-6.5/avr8/devices/atmega8/device.inc
deleted file mode 100644
index 733b5ed..0000000
--- a/amforth-6.5/avr8/devices/atmega8/device.inc
+++ /dev/null
@@ -1,696 +0,0 @@
-; Partname: ATmega8
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8/device.py b/amforth-6.5/avr8/devices/atmega8/device.py
deleted file mode 100644
index 9f561f5..0000000
--- a/amforth-6.5/avr8/devices/atmega8/device.py
+++ /dev/null
@@ -1,191 +0,0 @@
-# Partname: ATmega8
-# generated automatically, do not edit
-MCUREGS = {
- 'SFIOR': '&80',
- 'SFIOR_ACME': '$08',
- 'ACSR': '&40',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'SPDR': '&47',
- 'SPSR': '&46',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&45',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'GICR': '&91',
- 'GICR_INT': '$C0',
- 'GICR_IVSEL': '$02',
- 'GICR_IVCE': '$01',
- 'GIFR': '&90',
- 'GIFR_INTF': '$C0',
- 'MCUCR': '&85',
- 'MCUCR_ISC1': '$0C',
- 'MCUCR_ISC0': '$03',
- 'TIMSK': '&89',
- 'TIMSK_TOIE0': '$01',
- 'TIFR': '&88',
- 'TIFR_TOV0': '$01',
- 'TCCR0': '&83',
- 'TCCR0_CS02': '$04',
- 'TCCR0_CS01': '$02',
- 'TCCR0_CS00': '$01',
- 'TCNT0': '&82',
- 'TCCR1A': '&79',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_FOC1A': '$08',
- 'TCCR1A_FOC1B': '$04',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&78',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCNT1': '&76',
- 'OCR1A': '&74',
- 'OCR1B': '&72',
- 'ICR1': '&70',
- 'TCCR2': '&69',
- 'TCCR2_FOC2': '$80',
- 'TCCR2_WGM20': '$40',
- 'TCCR2_COM2': '$30',
- 'TCCR2_WGM21': '$08',
- 'TCCR2_CS2': '$07',
- 'TCNT2': '&68',
- 'OCR2': '&67',
- 'ASSR': '&66',
- 'ASSR_AS2': '$08',
- 'ASSR_TCN2UB': '$04',
- 'ASSR_OCR2UB': '$02',
- 'ASSR_TCR2UB': '$01',
- 'UDR': '&44',
- 'UCSRA': '&43',
- 'UCSRA_RXC': '$80',
- 'UCSRA_TXC': '$40',
- 'UCSRA_UDRE': '$20',
- 'UCSRA_FE': '$10',
- 'UCSRA_DOR': '$08',
- 'UCSRA_UPE': '$04',
- 'UCSRA_U2X': '$02',
- 'UCSRA_MPCM': '$01',
- 'UCSRB': '&42',
- 'UCSRB_RXCIE': '$80',
- 'UCSRB_TXCIE': '$40',
- 'UCSRB_UDRIE': '$20',
- 'UCSRB_RXEN': '$10',
- 'UCSRB_TXEN': '$08',
- 'UCSRB_UCSZ2': '$04',
- 'UCSRB_RXB8': '$02',
- 'UCSRB_TXB8': '$01',
- 'UCSRC': '&64',
- 'UCSRC_URSEL': '$80',
- 'UCSRC_UMSEL': '$40',
- 'UCSRC_UPM': '$30',
- 'UCSRC_USBS': '$08',
- 'UCSRC_UCSZ': '$06',
- 'UCSRC_UCPOL': '$01',
- 'UBRRH': '&64',
- 'UBRRL': '&41',
- 'TWBR': '&32',
- 'TWCR': '&86',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&33',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&35',
- 'TWAR': '&34',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'WDTCR': '&65',
- 'WDTCR_WDCE': '$10',
- 'WDTCR_WDE': '$08',
- 'WDTCR_WDP': '$07',
- 'PORTB': '&56',
- 'DDRB': '&55',
- 'PINB': '&54',
- 'PORTC': '&53',
- 'DDRC': '&52',
- 'PINC': '&51',
- 'PORTD': '&50',
- 'DDRD': '&49',
- 'PIND': '&48',
- 'EEAR': '&62',
- 'EEDR': '&61',
- 'EECR': '&60',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'MCUCSR': '&84',
- 'MCUCSR_WDRF': '$08',
- 'MCUCSR_BORF': '$04',
- 'MCUCSR_EXTRF': '$02',
- 'MCUCSR_PORF': '$01',
- 'OSCCAL': '&81',
- 'SPMCR': '&87',
- 'SPMCR_SPMIE': '$80',
- 'SPMCR_RWWSB': '$40',
- 'SPMCR_RWWSRE': '$10',
- 'SPMCR_BLBSET': '$08',
- 'SPMCR_PGWRT': '$04',
- 'SPMCR_PGERS': '$02',
- 'SPMCR_SPMEN': '$01',
- 'ADMUX': '&39',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADCSRA': '&38',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADFR': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADC': '&36',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'TIMER2_COMPAddr': '3',
- 'TIMER2_OVFAddr': '4',
- 'TIMER1_CAPTAddr': '5',
- 'TIMER1_COMPAAddr': '6',
- 'TIMER1_COMPBAddr': '7',
- 'TIMER1_OVFAddr': '8',
- 'TIMER0_OVFAddr': '9',
- 'SPI__STCAddr': '10',
- 'USART__RXCAddr': '11',
- 'USART__UDREAddr': '12',
- 'USART__TXCAddr': '13',
- 'ADCAddr': '14',
- 'EE_RDYAddr': '15',
- 'ANA_COMPAddr': '16',
- 'TWIAddr': '17',
- 'SPM_RDYAddr': '18'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega8/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt b/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt
deleted file mode 100644
index 576e9e6..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt
+++ /dev/null
@@ -1,193 +0,0 @@
-\ Partname: ATmega8515
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size Bit 2
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size Bits
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register High Byte
- $80 constant UBRRH_URSEL \ Register Select
- $0C constant UBRRH_UBRR1 \ USART Baud Rate Register bit 11
- $03 constant UBRRH_UBRR \ USART Baud Rate Register bits
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&86 constant EMCUCR \ Extended MCU Control Register
- $80 constant EMCUCR_SM0 \ Sleep Mode Select Bit 0
- $70 constant EMCUCR_SRL \ Wait State Selector Limit bits
- $0C constant EMCUCR_SRW0 \ Wait State Select Bits for Lower Sector, bits
- $02 constant EMCUCR_SRW11 \ Wait State Select Bits for Upper Sector, bit 1
- $01 constant EMCUCR_ISC2 \ Interrupt Sense Control 2
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_SRE \ External SRAM/XMEM Enable
- $40 constant MCUCR_SRW10 \ Wait State Select Bits for Upper Sector, bit 0
- $20 constant MCUCR_SE \ Sleep Enable
- $10 constant MCUCR_SM1 \ Sleep Mode Select Bit 1
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $20 constant MCUCSR_SM2 \ Sleep Mode Select Bit 2
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&36 constant OSCCAL \ Oscillator Calibration Value
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-&80 constant SFIOR \ Special Function IO Register
- $40 constant SFIOR_XMBK \ External Memory Bus Keeper Enable
- $38 constant SFIOR_XMM \ External Memory High Mask Bits
- $04 constant SFIOR_PUD \ Pull-up Disable
- $01 constant SFIOR_PSR10 \ Prescaler Reset Timer / Counter 1 and Timer / Counter 0
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter 0 Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter 0 Register
-&81 constant OCR0 \ Timer/Counter 0 Output Compare Register
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
- $01 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
- $01 constant TIFR_OCF0 \ Output Compare Flag 0
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare for Channel A
- $04 constant TCCR1A_FOC1B \ Force Output Compare for Channel B
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Pulse Width Modulator Select Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&68 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ PORTE
-&39 constant PORTE \ Port E Data Register
-&38 constant DDRE \ Port E Data Direction Register
-&37 constant PINE \ Port E Input Pins
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&4 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&5 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare MatchB
-&6 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&7 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&8 constant SPI_STCAddr \ Serial Transfer Complete
-&9 constant USART_RXAddr \ USART, Rx Complete
-&10 constant USART_UDREAddr \ USART Data Register Empty
-&11 constant USART__TXAddr \ USART, Tx Complete
-&12 constant ANA_COMPAddr \ Analog Comparator
-&13 constant INT2Addr \ External Interrupt Request 2
-&14 constant TIMER0_COMPAddr \ Timer 0 Compare Match
-&15 constant EE_RDYAddr \ EEPROM Ready
-&16 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8515/device.asm b/amforth-6.5/avr8/devices/atmega8515/device.asm
deleted file mode 100644
index 801e9dc..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/device.asm
+++ /dev/null
@@ -1,90 +0,0 @@
-; Partname: ATmega8515
-; generated automatically, do not edit
-
-.nolist
- .include "m8515def.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_WATCHDOG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Timer/Counter1 Capture Event
-.org 4
- rcall isr ; Timer/Counter1 Compare Match A
-.org 5
- rcall isr ; Timer/Counter1 Compare MatchB
-.org 6
- rcall isr ; Timer/Counter1 Overflow
-.org 7
- rcall isr ; Timer/Counter0 Overflow
-.org 8
- rcall isr ; Serial Transfer Complete
-.org 9
- rcall isr ; USART, Rx Complete
-.org 10
- rcall isr ; USART Data Register Empty
-.org 11
- rcall isr ; USART, Tx Complete
-.org 12
- rcall isr ; Analog Comparator
-.org 13
- rcall isr ; External Interrupt Request 2
-.org 14
- rcall isr ; Timer 0 Compare Match
-.org 15
- rcall isr ; EEPROM Ready
-.org 16
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 17
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 17
-mcu_name:
- .dw 10
- .db "ATmega8515"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8515/device.inc b/amforth-6.5/avr8/devices/atmega8515/device.inc
deleted file mode 100644
index a8b7e91..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/device.inc
+++ /dev/null
@@ -1,645 +0,0 @@
-; Partname: ATmega8515
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Extended MCU Control Register
-VE_EMCUCR:
- .dw $ff06
- .db "EMCUCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EMCUCR
-XT_EMCUCR:
- .dw PFA_DOVARIABLE
-PFA_EMCUCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 0 Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 68
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 37
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8515/device.py b/amforth-6.5/avr8/devices/atmega8515/device.py
deleted file mode 100644
index 463fdb8..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/device.py
+++ /dev/null
@@ -1,178 +0,0 @@
-# Partname: ATmega8515
-# generated automatically, do not edit
-MCUREGS = {
- 'ACSR': '&40',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'UDR': '&44',
- 'UCSRA': '&43',
- 'UCSRA_RXC': '$80',
- 'UCSRA_TXC': '$40',
- 'UCSRA_UDRE': '$20',
- 'UCSRA_FE': '$10',
- 'UCSRA_DOR': '$08',
- 'UCSRA_UPE': '$04',
- 'UCSRA_U2X': '$02',
- 'UCSRA_MPCM': '$01',
- 'UCSRB': '&42',
- 'UCSRB_RXCIE': '$80',
- 'UCSRB_TXCIE': '$40',
- 'UCSRB_UDRIE': '$20',
- 'UCSRB_RXEN': '$10',
- 'UCSRB_TXEN': '$08',
- 'UCSRB_UCSZ2': '$04',
- 'UCSRB_RXB8': '$02',
- 'UCSRB_TXB8': '$01',
- 'UCSRC': '&64',
- 'UCSRC_URSEL': '$80',
- 'UCSRC_UMSEL': '$40',
- 'UCSRC_UPM': '$30',
- 'UCSRC_USBS': '$08',
- 'UCSRC_UCSZ': '$06',
- 'UCSRC_UCPOL': '$01',
- 'UBRRH': '&64',
- 'UBRRH_URSEL': '$80',
- 'UBRRH_UBRR1': '$0C',
- 'UBRRH_UBRR': '$03',
- 'UBRRL': '&41',
- 'SPDR': '&47',
- 'SPSR': '&46',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&45',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'EMCUCR': '&86',
- 'EMCUCR_SM0': '$80',
- 'EMCUCR_SRL': '$70',
- 'EMCUCR_SRW0': '$0C',
- 'EMCUCR_SRW11': '$02',
- 'EMCUCR_ISC2': '$01',
- 'MCUCR': '&85',
- 'MCUCR_SRE': '$80',
- 'MCUCR_SRW10': '$40',
- 'MCUCR_SE': '$20',
- 'MCUCR_SM1': '$10',
- 'MCUCR_ISC1': '$0C',
- 'MCUCR_ISC0': '$03',
- 'MCUCSR': '&84',
- 'MCUCSR_SM2': '$20',
- 'MCUCSR_WDRF': '$08',
- 'MCUCSR_BORF': '$04',
- 'MCUCSR_EXTRF': '$02',
- 'MCUCSR_PORF': '$01',
- 'OSCCAL': '&36',
- 'SPMCR': '&87',
- 'SPMCR_SPMIE': '$80',
- 'SPMCR_RWWSB': '$40',
- 'SPMCR_RWWSRE': '$10',
- 'SPMCR_BLBSET': '$08',
- 'SPMCR_PGWRT': '$04',
- 'SPMCR_PGERS': '$02',
- 'SPMCR_SPMEN': '$01',
- 'SFIOR': '&80',
- 'SFIOR_XMBK': '$40',
- 'SFIOR_XMM': '$38',
- 'SFIOR_PUD': '$04',
- 'SFIOR_PSR10': '$01',
- 'GICR': '&91',
- 'GICR_INT': '$C0',
- 'GICR_INT2': '$20',
- 'GICR_IVSEL': '$02',
- 'GICR_IVCE': '$01',
- 'GIFR': '&90',
- 'GIFR_INTF': '$C0',
- 'GIFR_INTF2': '$20',
- 'WDTCR': '&65',
- 'WDTCR_WDCE': '$10',
- 'WDTCR_WDE': '$08',
- 'WDTCR_WDP': '$07',
- 'TCCR0': '&83',
- 'TCCR0_FOC0': '$80',
- 'TCCR0_WGM00': '$40',
- 'TCCR0_COM0': '$30',
- 'TCCR0_WGM01': '$08',
- 'TCCR0_CS0': '$07',
- 'TCNT0': '&82',
- 'OCR0': '&81',
- 'TIMSK': '&89',
- 'TIMSK_TOIE0': '$02',
- 'TIMSK_OCIE0': '$01',
- 'TIFR': '&88',
- 'TIFR_TOV0': '$02',
- 'TIFR_OCF0': '$01',
- 'TCCR1A': '&79',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_FOC1A': '$08',
- 'TCCR1A_FOC1B': '$04',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&78',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCNT1': '&76',
- 'OCR1A': '&74',
- 'OCR1B': '&72',
- 'ICR1': '&68',
- 'PORTA': '&59',
- 'DDRA': '&58',
- 'PINA': '&57',
- 'PORTB': '&56',
- 'DDRB': '&55',
- 'PINB': '&54',
- 'PORTC': '&53',
- 'DDRC': '&52',
- 'PINC': '&51',
- 'PORTD': '&50',
- 'DDRD': '&49',
- 'PIND': '&48',
- 'PORTE': '&39',
- 'DDRE': '&38',
- 'PINE': '&37',
- 'EEAR': '&62',
- 'EEDR': '&61',
- 'EECR': '&60',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'TIMER1_CAPTAddr': '3',
- 'TIMER1_COMPAAddr': '4',
- 'TIMER1_COMPBAddr': '5',
- 'TIMER1_OVFAddr': '6',
- 'TIMER0_OVFAddr': '7',
- 'SPI_STCAddr': '8',
- 'USART_RXAddr': '9',
- 'USART_UDREAddr': '10',
- 'USART__TXAddr': '11',
- 'ANA_COMPAddr': '12',
- 'INT2Addr': '13',
- 'TIMER0_COMPAddr': '14',
- 'EE_RDYAddr': '15',
- 'SPM_RDYAddr': '16'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8515/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8515/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega8515/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8535/atmega8535.frt b/amforth-6.5/avr8/devices/atmega8535/atmega8535.frt
deleted file mode 100644
index beda947..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/atmega8535.frt
+++ /dev/null
@@ -1,220 +0,0 @@
-\ Partname: ATmega8535
-\ generated automatically
-
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-&80 constant SFIOR \ Special Function IO Register
- $E0 constant SFIOR_ADTS \ ADC Auto Trigger Sources
-\ ANALOG_COMPARATOR
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size Bit 2
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size Bits
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register High Byte
- $80 constant UBRRH_URSEL \ Register Select
- $0C constant UBRRH_UBRR1 \ USART Baud Rate Register bit 11
- $03 constant UBRRH_UBRR \ USART Baud Rate Register bits
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ PORTA
-&59 constant PORTA \ Port A Data Register
-&58 constant DDRA \ Port A Data Direction Register
-&57 constant PINA \ Port A Input Pins
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&83 constant TCCR0 \ Timer/Counter Control Register
- $80 constant TCCR0_FOC0 \ Force Output Compare
- $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
- $30 constant TCCR0_COM0 \ Compare Match Output Modes
- $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
- $07 constant TCCR0_CS0 \ Clock Selects
-&82 constant TCNT0 \ Timer/Counter Register
-&92 constant OCR0 \ Output Compare Register
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $02 constant TIFR_OCF0 \ Output Compare Flag 0
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
- $20 constant GIFR_INTF2 \ External Interrupt Flag 2
-&85 constant MCUCR \ General Interrupt Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-&84 constant MCUCSR \ MCU Control And Status Register
- $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&81 constant OSCCAL \ Oscillator Calibration Value
-&87 constant SPMCR \
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt 0
-&2 constant INT1Addr \ External Interrupt 1
-&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&10 constant SPI_STCAddr \ SPI Serial Transfer Complete
-&11 constant USART_RXAddr \ USART, RX Complete
-&12 constant USART_UDREAddr \ USART Data Register Empty
-&13 constant USART_TXAddr \ USART, TX Complete
-&14 constant ADCAddr \ ADC Conversion Complete
-&15 constant EE_RDYAddr \ EEPROM Ready
-&16 constant ANA_COMPAddr \ Analog Comparator
-&17 constant TWIAddr \ Two-wire Serial Interface
-&18 constant INT2Addr \ External Interrupt Request 2
-&19 constant TIMER0_COMPAddr \ TimerCounter0 Compare Match
-&20 constant SPM_RDYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega8535/device.asm b/amforth-6.5/avr8/devices/atmega8535/device.asm
deleted file mode 100644
index 6768f1a..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/device.asm
+++ /dev/null
@@ -1,100 +0,0 @@
-; Partname: ATmega8535
-; generated automatically, do not edit
-
-.nolist
- .include "m8535def.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_TWI = 0
-.set WANT_USART = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_WATCHDOG = 0
-.set WANT_CPU = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt 0
-.org 2
- rcall isr ; External Interrupt 1
-.org 3
- rcall isr ; Timer/Counter2 Compare Match
-.org 4
- rcall isr ; Timer/Counter2 Overflow
-.org 5
- rcall isr ; Timer/Counter1 Capture Event
-.org 6
- rcall isr ; Timer/Counter1 Compare Match A
-.org 7
- rcall isr ; Timer/Counter1 Compare Match B
-.org 8
- rcall isr ; Timer/Counter1 Overflow
-.org 9
- rcall isr ; Timer/Counter0 Overflow
-.org 10
- rcall isr ; SPI Serial Transfer Complete
-.org 11
- rcall isr ; USART, RX Complete
-.org 12
- rcall isr ; USART Data Register Empty
-.org 13
- rcall isr ; USART, TX Complete
-.org 14
- rcall isr ; ADC Conversion Complete
-.org 15
- rcall isr ; EEPROM Ready
-.org 16
- rcall isr ; Analog Comparator
-.org 17
- rcall isr ; Two-wire Serial Interface
-.org 18
- rcall isr ; External Interrupt Request 2
-.org 19
- rcall isr ; TimerCounter0 Compare Match
-.org 20
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 21
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 10
- .db "ATmega8535"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8535/device.inc b/amforth-6.5/avr8/devices/atmega8535/device.inc
deleted file mode 100644
index 494fb0b..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/device.inc
+++ /dev/null
@@ -1,747 +0,0 @@
-; Partname: ATmega8535
-; generated automatically, no not edit
-
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register High Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 58
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 57
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8535/device.py b/amforth-6.5/avr8/devices/atmega8535/device.py
deleted file mode 100644
index 413668b..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/device.py
+++ /dev/null
@@ -1,203 +0,0 @@
-# Partname: ATmega8535
-# generated automatically, do not edit
-MCUREGS = {
- 'ADMUX': '&39',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$1F',
- 'ADCSRA': '&38',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADC': '&36',
- 'SFIOR': '&80',
- 'SFIOR_ADTS': '$E0',
- 'ACSR': '&40',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'TWBR': '&32',
- 'TWCR': '&86',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&33',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&35',
- 'TWAR': '&34',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'UDR': '&44',
- 'UCSRA': '&43',
- 'UCSRA_RXC': '$80',
- 'UCSRA_TXC': '$40',
- 'UCSRA_UDRE': '$20',
- 'UCSRA_FE': '$10',
- 'UCSRA_DOR': '$08',
- 'UCSRA_UPE': '$04',
- 'UCSRA_U2X': '$02',
- 'UCSRA_MPCM': '$01',
- 'UCSRB': '&42',
- 'UCSRB_RXCIE': '$80',
- 'UCSRB_TXCIE': '$40',
- 'UCSRB_UDRIE': '$20',
- 'UCSRB_RXEN': '$10',
- 'UCSRB_TXEN': '$08',
- 'UCSRB_UCSZ2': '$04',
- 'UCSRB_RXB8': '$02',
- 'UCSRB_TXB8': '$01',
- 'UCSRC': '&64',
- 'UCSRC_URSEL': '$80',
- 'UCSRC_UMSEL': '$40',
- 'UCSRC_UPM': '$30',
- 'UCSRC_USBS': '$08',
- 'UCSRC_UCSZ': '$06',
- 'UCSRC_UCPOL': '$01',
- 'UBRRH': '&64',
- 'UBRRH_URSEL': '$80',
- 'UBRRH_UBRR1': '$0C',
- 'UBRRH_UBRR': '$03',
- 'UBRRL': '&41',
- 'PORTA': '&59',
- 'DDRA': '&58',
- 'PINA': '&57',
- 'PORTB': '&56',
- 'DDRB': '&55',
- 'PINB': '&54',
- 'PORTC': '&53',
- 'DDRC': '&52',
- 'PINC': '&51',
- 'PORTD': '&50',
- 'DDRD': '&49',
- 'PIND': '&48',
- 'SPDR': '&47',
- 'SPSR': '&46',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&45',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'EEAR': '&62',
- 'EEDR': '&61',
- 'EECR': '&60',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'TCCR0': '&83',
- 'TCCR0_FOC0': '$80',
- 'TCCR0_WGM00': '$40',
- 'TCCR0_COM0': '$30',
- 'TCCR0_WGM01': '$08',
- 'TCCR0_CS0': '$07',
- 'TCNT0': '&82',
- 'OCR0': '&92',
- 'TIMSK': '&89',
- 'TIMSK_OCIE0': '$02',
- 'TIMSK_TOIE0': '$01',
- 'TIFR': '&88',
- 'TIFR_OCF0': '$02',
- 'TIFR_TOV0': '$01',
- 'TCCR1A': '&79',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_FOC1A': '$08',
- 'TCCR1A_FOC1B': '$04',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&78',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCNT1': '&76',
- 'OCR1A': '&74',
- 'OCR1B': '&72',
- 'ICR1': '&70',
- 'TCCR2': '&69',
- 'TCCR2_FOC2': '$80',
- 'TCCR2_WGM20': '$40',
- 'TCCR2_COM2': '$30',
- 'TCCR2_WGM21': '$08',
- 'TCCR2_CS2': '$07',
- 'TCNT2': '&68',
- 'OCR2': '&67',
- 'ASSR': '&66',
- 'ASSR_AS2': '$08',
- 'ASSR_TCN2UB': '$04',
- 'ASSR_OCR2UB': '$02',
- 'ASSR_TCR2UB': '$01',
- 'GICR': '&91',
- 'GICR_INT': '$C0',
- 'GICR_INT2': '$20',
- 'GICR_IVSEL': '$02',
- 'GICR_IVCE': '$01',
- 'GIFR': '&90',
- 'GIFR_INTF': '$C0',
- 'GIFR_INTF2': '$20',
- 'MCUCR': '&85',
- 'MCUCR_ISC1': '$0C',
- 'MCUCR_ISC0': '$03',
- 'MCUCSR': '&84',
- 'MCUCSR_ISC2': '$40',
- 'WDTCR': '&65',
- 'WDTCR_WDCE': '$10',
- 'WDTCR_WDE': '$08',
- 'WDTCR_WDP': '$07',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'OSCCAL': '&81',
- 'SPMCR': '&87',
- 'SPMCR_SPMIE': '$80',
- 'SPMCR_RWWSB': '$40',
- 'SPMCR_RWWSRE': '$10',
- 'SPMCR_BLBSET': '$08',
- 'SPMCR_PGWRT': '$04',
- 'SPMCR_PGERS': '$02',
- 'SPMCR_SPMEN': '$01',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'TIMER2_COMPAddr': '3',
- 'TIMER2_OVFAddr': '4',
- 'TIMER1_CAPTAddr': '5',
- 'TIMER1_COMPAAddr': '6',
- 'TIMER1_COMPBAddr': '7',
- 'TIMER1_OVFAddr': '8',
- 'TIMER0_OVFAddr': '9',
- 'SPI_STCAddr': '10',
- 'USART_RXAddr': '11',
- 'USART_UDREAddr': '12',
- 'USART_TXAddr': '13',
- 'ADCAddr': '14',
- 'EE_RDYAddr': '15',
- 'ANA_COMPAddr': '16',
- 'TWIAddr': '17',
- 'INT2Addr': '18',
- 'TIMER0_COMPAddr': '19',
- 'SPM_RDYAddr': '20'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8535/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8535/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8535/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8535/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8535/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8535/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega8535/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88/atmega88.frt b/amforth-6.5/avr8/devices/atmega88/atmega88.frt
deleted file mode 100644
index 2034063..0000000
--- a/amforth-6.5/avr8/devices/atmega88/atmega88.frt
+++ /dev/null
@@ -1,297 +0,0 @@
-\ Partname: ATmega88
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \
- $0E constant SMCR_SM \
- $01 constant SMCR_SE \
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&6 constant WDTAddr \ Watchdog Time-out Interrupt
-&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&18 constant USART__RXAddr \ USART Rx Complete
-&19 constant USART__UDREAddr \ USART, Data Register Empty
-&20 constant USART__TXAddr \ USART Tx Complete
-&21 constant ADCAddr \ ADC Conversion Complete
-&22 constant EE_READYAddr \ EEPROM Ready
-&23 constant ANALOG_COMPAddr \ Analog Comparator
-&24 constant TWIAddr \ Two-wire Serial Interface
-&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88/device.asm b/amforth-6.5/avr8/devices/atmega88/device.asm
deleted file mode 100644
index fe6d207..0000000
--- a/amforth-6.5/avr8/devices/atmega88/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega88
-; generated automatically, do not edit
-
-.nolist
- .include "m88def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Pin Change Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 5
- rcall isr ; Pin Change Interrupt Request 1
-.org 6
- rcall isr ; Watchdog Time-out Interrupt
-.org 7
- rcall isr ; Timer/Counter2 Compare Match A
-.org 8
- rcall isr ; Timer/Counter2 Compare Match A
-.org 9
- rcall isr ; Timer/Counter2 Overflow
-.org 10
- rcall isr ; Timer/Counter1 Capture Event
-.org 11
- rcall isr ; Timer/Counter1 Compare Match A
-.org 12
- rcall isr ; Timer/Counter1 Compare Match B
-.org 13
- rcall isr ; Timer/Counter1 Overflow
-.org 14
- rcall isr ; TimerCounter0 Compare Match A
-.org 15
- rcall isr ; TimerCounter0 Compare Match B
-.org 16
- rcall isr ; Timer/Couner0 Overflow
-.org 17
- rcall isr ; SPI Serial Transfer Complete
-.org 18
- rcall isr ; USART Rx Complete
-.org 19
- rcall isr ; USART, Data Register Empty
-.org 20
- rcall isr ; USART Tx Complete
-.org 21
- rcall isr ; ADC Conversion Complete
-.org 22
- rcall isr ; EEPROM Ready
-.org 23
- rcall isr ; Analog Comparator
-.org 24
- rcall isr ; Two-wire Serial Interface
-.org 25
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 8
- .db "ATmega88"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88/device.inc b/amforth-6.5/avr8/devices/atmega88/device.inc
deleted file mode 100644
index 32d6fca..0000000
--- a/amforth-6.5/avr8/devices/atmega88/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega88
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega88/device.py b/amforth-6.5/avr8/devices/atmega88/device.py
deleted file mode 100644
index 7849841..0000000
--- a/amforth-6.5/avr8/devices/atmega88/device.py
+++ /dev/null
@@ -1,281 +0,0 @@
-# Partname: ATmega88
-# generated automatically, do not edit
-MCUREGS = {
- 'UDR0': '&198',
- 'UCSR0A': '&192',
- 'UCSR0A_RXC0': '$80',
- 'UCSR0A_TXC0': '$40',
- 'UCSR0A_UDRE0': '$20',
- 'UCSR0A_FE0': '$10',
- 'UCSR0A_DOR0': '$08',
- 'UCSR0A_UPE0': '$04',
- 'UCSR0A_U2X0': '$02',
- 'UCSR0A_MPCM0': '$01',
- 'UCSR0B': '&193',
- 'UCSR0B_RXCIE0': '$80',
- 'UCSR0B_TXCIE0': '$40',
- 'UCSR0B_UDRIE0': '$20',
- 'UCSR0B_RXEN0': '$10',
- 'UCSR0B_TXEN0': '$08',
- 'UCSR0B_UCSZ02': '$04',
- 'UCSR0B_RXB80': '$02',
- 'UCSR0B_TXB80': '$01',
- 'UCSR0C': '&194',
- 'UCSR0C_UMSEL0': '$C0',
- 'UCSR0C_UPM0': '$30',
- 'UCSR0C_USBS0': '$08',
- 'UCSR0C_UCSZ0': '$06',
- 'UCSR0C_UCPOL0': '$01',
- 'UBRR0': '&196',
- 'TWAMR': '&189',
- 'TWAMR_TWAM': '$FE',
- 'TWBR': '&184',
- 'TWCR': '&188',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&185',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&187',
- 'TWAR': '&186',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'ICR1': '&134',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSRSYNC': '$01',
- 'TIMSK2': '&112',
- 'TIMSK2_OCIE2B': '$04',
- 'TIMSK2_OCIE2A': '$02',
- 'TIMSK2_TOIE2': '$01',
- 'TIFR2': '&55',
- 'TIFR2_OCF2B': '$04',
- 'TIFR2_OCF2A': '$02',
- 'TIFR2_TOV2': '$01',
- 'TCCR2A': '&176',
- 'TCCR2A_COM2A': '$C0',
- 'TCCR2A_COM2B': '$30',
- 'TCCR2A_WGM2': '$03',
- 'TCCR2B': '&177',
- 'TCCR2B_FOC2A': '$80',
- 'TCCR2B_FOC2B': '$40',
- 'TCCR2B_WGM22': '$08',
- 'TCCR2B_CS2': '$07',
- 'TCNT2': '&178',
- 'OCR2B': '&180',
- 'OCR2A': '&179',
- 'ASSR': '&182',
- 'ASSR_EXCLK': '$40',
- 'ASSR_AS2': '$20',
- 'ASSR_TCN2UB': '$10',
- 'ASSR_OCR2AUB': '$08',
- 'ASSR_OCR2BUB': '$04',
- 'ASSR_TCR2AUB': '$02',
- 'ASSR_TCR2BUB': '$01',
- 'ADMUX': '&124',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADC': '&120',
- 'ADCSRA': '&122',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADCSRB': '&123',
- 'ADCSRB_ACME': '$40',
- 'ADCSRB_ADTS': '$07',
- 'DIDR0': '&126',
- 'DIDR0_ADC5D': '$20',
- 'DIDR0_ADC4D': '$10',
- 'DIDR0_ADC3D': '$08',
- 'DIDR0_ADC2D': '$04',
- 'DIDR0_ADC1D': '$02',
- 'DIDR0_ADC0D': '$01',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTC': '&40',
- 'DDRC': '&39',
- 'PINC': '&38',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'OCR0B': '&72',
- 'OCR0A': '&71',
- 'TCNT0': '&70',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'EICRA': '&105',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$03',
- 'EIFR': '&60',
- 'EIFR_INTF': '$03',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$07',
- 'PCMSK2': '&109',
- 'PCMSK2_PCINT': '$FF',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$7F',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$07',
- 'SPDR': '&78',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'PRR': '&100',
- 'PRR_PRTWI': '$80',
- 'PRR_PRTIM2': '$40',
- 'PRR_PRTIM0': '$20',
- 'PRR_PRTIM1': '$08',
- 'PRR_PRSPI': '$04',
- 'PRR_PRUSART0': '$02',
- 'PRR_PRADC': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SELFPRGEN': '$01',
- 'MCUCR': '&85',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'GPIOR2': '&75',
- 'GPIOR1': '&74',
- 'GPIOR0': '&62',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMPE': '$04',
- 'EECR_EEPE': '$02',
- 'EECR_EERE': '$01',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'PCINT0Addr': '3',
- 'PCINT1Addr': '4',
- 'PCINT2Addr': '5',
- 'WDTAddr': '6',
- 'TIMER2_COMPAAddr': '7',
- 'TIMER2_COMPBAddr': '8',
- 'TIMER2_OVFAddr': '9',
- 'TIMER1_CAPTAddr': '10',
- 'TIMER1_COMPAAddr': '11',
- 'TIMER1_COMPBAddr': '12',
- 'TIMER1_OVFAddr': '13',
- 'TIMER0_COMPAAddr': '14',
- 'TIMER0_COMPBAddr': '15',
- 'TIMER0_OVFAddr': '16',
- 'SPI__STCAddr': '17',
- 'USART__RXAddr': '18',
- 'USART__UDREAddr': '19',
- 'USART__TXAddr': '20',
- 'ADCAddr': '21',
- 'EE_READYAddr': '22',
- 'ANALOG_COMPAddr': '23',
- 'TWIAddr': '24',
- 'SPM_ReadyAddr': '25'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega88/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega88/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega88/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt b/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt
deleted file mode 100644
index 657734d..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt
+++ /dev/null
@@ -1,297 +0,0 @@
-\ Partname: ATmega88A
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&6 constant WDTAddr \ Watchdog Time-out Interrupt
-&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&18 constant USART__RXAddr \ USART Rx Complete
-&19 constant USART__UDREAddr \ USART, Data Register Empty
-&20 constant USART__TXAddr \ USART Tx Complete
-&21 constant ADCAddr \ ADC Conversion Complete
-&22 constant EE_READYAddr \ EEPROM Ready
-&23 constant ANALOG_COMPAddr \ Analog Comparator
-&24 constant TWIAddr \ Two-wire Serial Interface
-&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88a/device.asm b/amforth-6.5/avr8/devices/atmega88a/device.asm
deleted file mode 100644
index 1195a9c..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega88A
-; generated automatically, do not edit
-
-.nolist
- .include "m88Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Pin Change Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 5
- rcall isr ; Pin Change Interrupt Request 1
-.org 6
- rcall isr ; Watchdog Time-out Interrupt
-.org 7
- rcall isr ; Timer/Counter2 Compare Match A
-.org 8
- rcall isr ; Timer/Counter2 Compare Match A
-.org 9
- rcall isr ; Timer/Counter2 Overflow
-.org 10
- rcall isr ; Timer/Counter1 Capture Event
-.org 11
- rcall isr ; Timer/Counter1 Compare Match A
-.org 12
- rcall isr ; Timer/Counter1 Compare Match B
-.org 13
- rcall isr ; Timer/Counter1 Overflow
-.org 14
- rcall isr ; TimerCounter0 Compare Match A
-.org 15
- rcall isr ; TimerCounter0 Compare Match B
-.org 16
- rcall isr ; Timer/Couner0 Overflow
-.org 17
- rcall isr ; SPI Serial Transfer Complete
-.org 18
- rcall isr ; USART Rx Complete
-.org 19
- rcall isr ; USART, Data Register Empty
-.org 20
- rcall isr ; USART Tx Complete
-.org 21
- rcall isr ; ADC Conversion Complete
-.org 22
- rcall isr ; EEPROM Ready
-.org 23
- rcall isr ; Analog Comparator
-.org 24
- rcall isr ; Two-wire Serial Interface
-.org 25
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 9
- .db "ATmega88A",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88a/device.inc b/amforth-6.5/avr8/devices/atmega88a/device.inc
deleted file mode 100644
index 446e57e..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega88A
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega88a/device.py b/amforth-6.5/avr8/devices/atmega88a/device.py
deleted file mode 100644
index 4c18ee9..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/device.py
+++ /dev/null
@@ -1,281 +0,0 @@
-# Partname: ATmega88A
-# generated automatically, do not edit
-MCUREGS = {
- 'UDR0': '&198',
- 'UCSR0A': '&192',
- 'UCSR0A_RXC0': '$80',
- 'UCSR0A_TXC0': '$40',
- 'UCSR0A_UDRE0': '$20',
- 'UCSR0A_FE0': '$10',
- 'UCSR0A_DOR0': '$08',
- 'UCSR0A_UPE0': '$04',
- 'UCSR0A_U2X0': '$02',
- 'UCSR0A_MPCM0': '$01',
- 'UCSR0B': '&193',
- 'UCSR0B_RXCIE0': '$80',
- 'UCSR0B_TXCIE0': '$40',
- 'UCSR0B_UDRIE0': '$20',
- 'UCSR0B_RXEN0': '$10',
- 'UCSR0B_TXEN0': '$08',
- 'UCSR0B_UCSZ02': '$04',
- 'UCSR0B_RXB80': '$02',
- 'UCSR0B_TXB80': '$01',
- 'UCSR0C': '&194',
- 'UCSR0C_UMSEL0': '$C0',
- 'UCSR0C_UPM0': '$30',
- 'UCSR0C_USBS0': '$08',
- 'UCSR0C_UCSZ0': '$06',
- 'UCSR0C_UCPOL0': '$01',
- 'UBRR0': '&196',
- 'TWAMR': '&189',
- 'TWAMR_TWAM': '$FE',
- 'TWBR': '&184',
- 'TWCR': '&188',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&185',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&187',
- 'TWAR': '&186',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'ICR1': '&134',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSRSYNC': '$01',
- 'TIMSK2': '&112',
- 'TIMSK2_OCIE2B': '$04',
- 'TIMSK2_OCIE2A': '$02',
- 'TIMSK2_TOIE2': '$01',
- 'TIFR2': '&55',
- 'TIFR2_OCF2B': '$04',
- 'TIFR2_OCF2A': '$02',
- 'TIFR2_TOV2': '$01',
- 'TCCR2A': '&176',
- 'TCCR2A_COM2A': '$C0',
- 'TCCR2A_COM2B': '$30',
- 'TCCR2A_WGM2': '$03',
- 'TCCR2B': '&177',
- 'TCCR2B_FOC2A': '$80',
- 'TCCR2B_FOC2B': '$40',
- 'TCCR2B_WGM22': '$08',
- 'TCCR2B_CS2': '$07',
- 'TCNT2': '&178',
- 'OCR2B': '&180',
- 'OCR2A': '&179',
- 'ASSR': '&182',
- 'ASSR_EXCLK': '$40',
- 'ASSR_AS2': '$20',
- 'ASSR_TCN2UB': '$10',
- 'ASSR_OCR2AUB': '$08',
- 'ASSR_OCR2BUB': '$04',
- 'ASSR_TCR2AUB': '$02',
- 'ASSR_TCR2BUB': '$01',
- 'ADMUX': '&124',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADC': '&120',
- 'ADCSRA': '&122',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADCSRB': '&123',
- 'ADCSRB_ACME': '$40',
- 'ADCSRB_ADTS': '$07',
- 'DIDR0': '&126',
- 'DIDR0_ADC5D': '$20',
- 'DIDR0_ADC4D': '$10',
- 'DIDR0_ADC3D': '$08',
- 'DIDR0_ADC2D': '$04',
- 'DIDR0_ADC1D': '$02',
- 'DIDR0_ADC0D': '$01',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTC': '&40',
- 'DDRC': '&39',
- 'PINC': '&38',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'OCR0B': '&72',
- 'OCR0A': '&71',
- 'TCNT0': '&70',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'EICRA': '&105',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$03',
- 'EIFR': '&60',
- 'EIFR_INTF': '$03',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$07',
- 'PCMSK2': '&109',
- 'PCMSK2_PCINT': '$FF',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$7F',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$07',
- 'SPDR': '&78',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMPE': '$04',
- 'EECR_EEPE': '$02',
- 'EECR_EERE': '$01',
- 'PRR': '&100',
- 'PRR_PRTWI': '$80',
- 'PRR_PRTIM2': '$40',
- 'PRR_PRTIM0': '$20',
- 'PRR_PRTIM1': '$08',
- 'PRR_PRSPI': '$04',
- 'PRR_PRUSART0': '$02',
- 'PRR_PRADC': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SELFPRGEN': '$01',
- 'MCUCR': '&85',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'GPIOR2': '&75',
- 'GPIOR1': '&74',
- 'GPIOR0': '&62',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'PCINT0Addr': '3',
- 'PCINT1Addr': '4',
- 'PCINT2Addr': '5',
- 'WDTAddr': '6',
- 'TIMER2_COMPAAddr': '7',
- 'TIMER2_COMPBAddr': '8',
- 'TIMER2_OVFAddr': '9',
- 'TIMER1_CAPTAddr': '10',
- 'TIMER1_COMPAAddr': '11',
- 'TIMER1_COMPBAddr': '12',
- 'TIMER1_OVFAddr': '13',
- 'TIMER0_COMPAAddr': '14',
- 'TIMER0_COMPBAddr': '15',
- 'TIMER0_OVFAddr': '16',
- 'SPI__STCAddr': '17',
- 'USART__RXAddr': '18',
- 'USART__UDREAddr': '19',
- 'USART__TXAddr': '20',
- 'ADCAddr': '21',
- 'EE_READYAddr': '22',
- 'ANALOG_COMPAddr': '23',
- 'TWIAddr': '24',
- 'SPM_ReadyAddr': '25'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega88a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88p/atmega88p.frt b/amforth-6.5/avr8/devices/atmega88p/atmega88p.frt
deleted file mode 100644
index 71d0ca2..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/atmega88p.frt
+++ /dev/null
@@ -1,299 +0,0 @@
-\ Partname: ATmega88P
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $40 constant MCUCR_BODS \ BOD Sleep
- $20 constant MCUCR_BODSE \ BOD Sleep Enable
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&6 constant WDTAddr \ Watchdog Time-out Interrupt
-&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&18 constant USART__RXAddr \ USART Rx Complete
-&19 constant USART__UDREAddr \ USART, Data Register Empty
-&20 constant USART__TXAddr \ USART Tx Complete
-&21 constant ADCAddr \ ADC Conversion Complete
-&22 constant EE_READYAddr \ EEPROM Ready
-&23 constant ANALOG_COMPAddr \ Analog Comparator
-&24 constant TWIAddr \ Two-wire Serial Interface
-&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88p/device.asm b/amforth-6.5/avr8/devices/atmega88p/device.asm
deleted file mode 100644
index 739b20c..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega88P
-; generated automatically, do not edit
-
-.nolist
- .include "m88Pdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Pin Change Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 5
- rcall isr ; Pin Change Interrupt Request 1
-.org 6
- rcall isr ; Watchdog Time-out Interrupt
-.org 7
- rcall isr ; Timer/Counter2 Compare Match A
-.org 8
- rcall isr ; Timer/Counter2 Compare Match A
-.org 9
- rcall isr ; Timer/Counter2 Overflow
-.org 10
- rcall isr ; Timer/Counter1 Capture Event
-.org 11
- rcall isr ; Timer/Counter1 Compare Match A
-.org 12
- rcall isr ; Timer/Counter1 Compare Match B
-.org 13
- rcall isr ; Timer/Counter1 Overflow
-.org 14
- rcall isr ; TimerCounter0 Compare Match A
-.org 15
- rcall isr ; TimerCounter0 Compare Match B
-.org 16
- rcall isr ; Timer/Couner0 Overflow
-.org 17
- rcall isr ; SPI Serial Transfer Complete
-.org 18
- rcall isr ; USART Rx Complete
-.org 19
- rcall isr ; USART, Data Register Empty
-.org 20
- rcall isr ; USART Tx Complete
-.org 21
- rcall isr ; ADC Conversion Complete
-.org 22
- rcall isr ; EEPROM Ready
-.org 23
- rcall isr ; Analog Comparator
-.org 24
- rcall isr ; Two-wire Serial Interface
-.org 25
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 9
- .db "ATmega88P",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88p/device.inc b/amforth-6.5/avr8/devices/atmega88p/device.inc
deleted file mode 100644
index 97494c9..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega88P
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega88p/device.py b/amforth-6.5/avr8/devices/atmega88p/device.py
deleted file mode 100644
index 79aac62..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/device.py
+++ /dev/null
@@ -1,283 +0,0 @@
-# Partname: ATmega88P
-# generated automatically, do not edit
-MCUREGS = {
- 'UDR0': '&198',
- 'UCSR0A': '&192',
- 'UCSR0A_RXC0': '$80',
- 'UCSR0A_TXC0': '$40',
- 'UCSR0A_UDRE0': '$20',
- 'UCSR0A_FE0': '$10',
- 'UCSR0A_DOR0': '$08',
- 'UCSR0A_UPE0': '$04',
- 'UCSR0A_U2X0': '$02',
- 'UCSR0A_MPCM0': '$01',
- 'UCSR0B': '&193',
- 'UCSR0B_RXCIE0': '$80',
- 'UCSR0B_TXCIE0': '$40',
- 'UCSR0B_UDRIE0': '$20',
- 'UCSR0B_RXEN0': '$10',
- 'UCSR0B_TXEN0': '$08',
- 'UCSR0B_UCSZ02': '$04',
- 'UCSR0B_RXB80': '$02',
- 'UCSR0B_TXB80': '$01',
- 'UCSR0C': '&194',
- 'UCSR0C_UMSEL0': '$C0',
- 'UCSR0C_UPM0': '$30',
- 'UCSR0C_USBS0': '$08',
- 'UCSR0C_UCSZ0': '$06',
- 'UCSR0C_UCPOL0': '$01',
- 'UBRR0': '&196',
- 'TWAMR': '&189',
- 'TWAMR_TWAM': '$FE',
- 'TWBR': '&184',
- 'TWCR': '&188',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&185',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&187',
- 'TWAR': '&186',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'ICR1': '&134',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSRSYNC': '$01',
- 'TIMSK2': '&112',
- 'TIMSK2_OCIE2B': '$04',
- 'TIMSK2_OCIE2A': '$02',
- 'TIMSK2_TOIE2': '$01',
- 'TIFR2': '&55',
- 'TIFR2_OCF2B': '$04',
- 'TIFR2_OCF2A': '$02',
- 'TIFR2_TOV2': '$01',
- 'TCCR2A': '&176',
- 'TCCR2A_COM2A': '$C0',
- 'TCCR2A_COM2B': '$30',
- 'TCCR2A_WGM2': '$03',
- 'TCCR2B': '&177',
- 'TCCR2B_FOC2A': '$80',
- 'TCCR2B_FOC2B': '$40',
- 'TCCR2B_WGM22': '$08',
- 'TCCR2B_CS2': '$07',
- 'TCNT2': '&178',
- 'OCR2B': '&180',
- 'OCR2A': '&179',
- 'ASSR': '&182',
- 'ASSR_EXCLK': '$40',
- 'ASSR_AS2': '$20',
- 'ASSR_TCN2UB': '$10',
- 'ASSR_OCR2AUB': '$08',
- 'ASSR_OCR2BUB': '$04',
- 'ASSR_TCR2AUB': '$02',
- 'ASSR_TCR2BUB': '$01',
- 'ADMUX': '&124',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADC': '&120',
- 'ADCSRA': '&122',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADCSRB': '&123',
- 'ADCSRB_ACME': '$40',
- 'ADCSRB_ADTS': '$07',
- 'DIDR0': '&126',
- 'DIDR0_ADC5D': '$20',
- 'DIDR0_ADC4D': '$10',
- 'DIDR0_ADC3D': '$08',
- 'DIDR0_ADC2D': '$04',
- 'DIDR0_ADC1D': '$02',
- 'DIDR0_ADC0D': '$01',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTC': '&40',
- 'DDRC': '&39',
- 'PINC': '&38',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'OCR0B': '&72',
- 'OCR0A': '&71',
- 'TCNT0': '&70',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'EICRA': '&105',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$03',
- 'EIFR': '&60',
- 'EIFR_INTF': '$03',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$07',
- 'PCMSK2': '&109',
- 'PCMSK2_PCINT': '$FF',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$7F',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$07',
- 'SPDR': '&78',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMPE': '$04',
- 'EECR_EEPE': '$02',
- 'EECR_EERE': '$01',
- 'PRR': '&100',
- 'PRR_PRTWI': '$80',
- 'PRR_PRTIM2': '$40',
- 'PRR_PRTIM0': '$20',
- 'PRR_PRTIM1': '$08',
- 'PRR_PRSPI': '$04',
- 'PRR_PRUSART0': '$02',
- 'PRR_PRADC': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SELFPRGEN': '$01',
- 'MCUCR': '&85',
- 'MCUCR_BODS': '$40',
- 'MCUCR_BODSE': '$20',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'GPIOR2': '&75',
- 'GPIOR1': '&74',
- 'GPIOR0': '&62',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'PCINT0Addr': '3',
- 'PCINT1Addr': '4',
- 'PCINT2Addr': '5',
- 'WDTAddr': '6',
- 'TIMER2_COMPAAddr': '7',
- 'TIMER2_COMPBAddr': '8',
- 'TIMER2_OVFAddr': '9',
- 'TIMER1_CAPTAddr': '10',
- 'TIMER1_COMPAAddr': '11',
- 'TIMER1_COMPBAddr': '12',
- 'TIMER1_OVFAddr': '13',
- 'TIMER0_COMPAAddr': '14',
- 'TIMER0_COMPBAddr': '15',
- 'TIMER0_OVFAddr': '16',
- 'SPI__STCAddr': '17',
- 'USART__RXAddr': '18',
- 'USART__UDREAddr': '19',
- 'USART__TXAddr': '20',
- 'ADCAddr': '21',
- 'EE_READYAddr': '22',
- 'ANALOG_COMPAddr': '23',
- 'TWIAddr': '24',
- 'SPM_ReadyAddr': '25'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88p/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88p/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88p/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega88p/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt b/amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt
deleted file mode 100644
index e401789..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt
+++ /dev/null
@@ -1,299 +0,0 @@
-\ Partname: ATmega88PA
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $40 constant MCUCR_BODS \ BOD Sleep
- $20 constant MCUCR_BODSE \ BOD Sleep Enable
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select Bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&6 constant WDTAddr \ Watchdog Time-out Interrupt
-&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&18 constant USART__RXAddr \ USART Rx Complete
-&19 constant USART__UDREAddr \ USART, Data Register Empty
-&20 constant USART__TXAddr \ USART Tx Complete
-&21 constant ADCAddr \ ADC Conversion Complete
-&22 constant EE_READYAddr \ EEPROM Ready
-&23 constant ANALOG_COMPAddr \ Analog Comparator
-&24 constant TWIAddr \ Two-wire Serial Interface
-&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.asm b/amforth-6.5/avr8/devices/atmega88pa/device.asm
deleted file mode 100644
index 5e2d8c3..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega88PA
-; generated automatically, do not edit
-
-.nolist
- .include "m88PAdef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Pin Change Interrupt Request 0
-.org 4
- rcall isr ; Pin Change Interrupt Request 0
-.org 5
- rcall isr ; Pin Change Interrupt Request 1
-.org 6
- rcall isr ; Watchdog Time-out Interrupt
-.org 7
- rcall isr ; Timer/Counter2 Compare Match A
-.org 8
- rcall isr ; Timer/Counter2 Compare Match A
-.org 9
- rcall isr ; Timer/Counter2 Overflow
-.org 10
- rcall isr ; Timer/Counter1 Capture Event
-.org 11
- rcall isr ; Timer/Counter1 Compare Match A
-.org 12
- rcall isr ; Timer/Counter1 Compare Match B
-.org 13
- rcall isr ; Timer/Counter1 Overflow
-.org 14
- rcall isr ; TimerCounter0 Compare Match A
-.org 15
- rcall isr ; TimerCounter0 Compare Match B
-.org 16
- rcall isr ; Timer/Couner0 Overflow
-.org 17
- rcall isr ; SPI Serial Transfer Complete
-.org 18
- rcall isr ; USART Rx Complete
-.org 19
- rcall isr ; USART, Data Register Empty
-.org 20
- rcall isr ; USART Tx Complete
-.org 21
- rcall isr ; ADC Conversion Complete
-.org 22
- rcall isr ; EEPROM Ready
-.org 23
- rcall isr ; Analog Comparator
-.org 24
- rcall isr ; Two-wire Serial Interface
-.org 25
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 10
- .db "ATmega88PA"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.inc b/amforth-6.5/avr8/devices/atmega88pa/device.inc
deleted file mode 100644
index 71a9bf3..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega88PA
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.py b/amforth-6.5/avr8/devices/atmega88pa/device.py
deleted file mode 100644
index d814349..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/device.py
+++ /dev/null
@@ -1,283 +0,0 @@
-# Partname: ATmega88PA
-# generated automatically, do not edit
-MCUREGS = {
- 'UDR0': '&198',
- 'UCSR0A': '&192',
- 'UCSR0A_RXC0': '$80',
- 'UCSR0A_TXC0': '$40',
- 'UCSR0A_UDRE0': '$20',
- 'UCSR0A_FE0': '$10',
- 'UCSR0A_DOR0': '$08',
- 'UCSR0A_UPE0': '$04',
- 'UCSR0A_U2X0': '$02',
- 'UCSR0A_MPCM0': '$01',
- 'UCSR0B': '&193',
- 'UCSR0B_RXCIE0': '$80',
- 'UCSR0B_TXCIE0': '$40',
- 'UCSR0B_UDRIE0': '$20',
- 'UCSR0B_RXEN0': '$10',
- 'UCSR0B_TXEN0': '$08',
- 'UCSR0B_UCSZ02': '$04',
- 'UCSR0B_RXB80': '$02',
- 'UCSR0B_TXB80': '$01',
- 'UCSR0C': '&194',
- 'UCSR0C_UMSEL0': '$C0',
- 'UCSR0C_UPM0': '$30',
- 'UCSR0C_USBS0': '$08',
- 'UCSR0C_UCSZ0': '$06',
- 'UCSR0C_UCPOL0': '$01',
- 'UBRR0': '&196',
- 'TWAMR': '&189',
- 'TWAMR_TWAM': '$FE',
- 'TWBR': '&184',
- 'TWCR': '&188',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&185',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&187',
- 'TWAR': '&186',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'ICR1': '&134',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSRSYNC': '$01',
- 'TIMSK2': '&112',
- 'TIMSK2_OCIE2B': '$04',
- 'TIMSK2_OCIE2A': '$02',
- 'TIMSK2_TOIE2': '$01',
- 'TIFR2': '&55',
- 'TIFR2_OCF2B': '$04',
- 'TIFR2_OCF2A': '$02',
- 'TIFR2_TOV2': '$01',
- 'TCCR2A': '&176',
- 'TCCR2A_COM2A': '$C0',
- 'TCCR2A_COM2B': '$30',
- 'TCCR2A_WGM2': '$03',
- 'TCCR2B': '&177',
- 'TCCR2B_FOC2A': '$80',
- 'TCCR2B_FOC2B': '$40',
- 'TCCR2B_WGM22': '$08',
- 'TCCR2B_CS2': '$07',
- 'TCNT2': '&178',
- 'OCR2B': '&180',
- 'OCR2A': '&179',
- 'ASSR': '&182',
- 'ASSR_EXCLK': '$40',
- 'ASSR_AS2': '$20',
- 'ASSR_TCN2UB': '$10',
- 'ASSR_OCR2AUB': '$08',
- 'ASSR_OCR2BUB': '$04',
- 'ASSR_TCR2AUB': '$02',
- 'ASSR_TCR2BUB': '$01',
- 'ADMUX': '&124',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADC': '&120',
- 'ADCSRA': '&122',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADATE': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADCSRB': '&123',
- 'ADCSRB_ACME': '$40',
- 'ADCSRB_ADTS': '$07',
- 'DIDR0': '&126',
- 'DIDR0_ADC5D': '$20',
- 'DIDR0_ADC4D': '$10',
- 'DIDR0_ADC3D': '$08',
- 'DIDR0_ADC2D': '$04',
- 'DIDR0_ADC1D': '$02',
- 'DIDR0_ADC0D': '$01',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTC': '&40',
- 'DDRC': '&39',
- 'PINC': '&38',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'OCR0B': '&72',
- 'OCR0A': '&71',
- 'TCNT0': '&70',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'EICRA': '&105',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$03',
- 'EIFR': '&60',
- 'EIFR_INTF': '$03',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$07',
- 'PCMSK2': '&109',
- 'PCMSK2_PCINT': '$FF',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$7F',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$07',
- 'SPDR': '&78',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMPE': '$04',
- 'EECR_EEPE': '$02',
- 'EECR_EERE': '$01',
- 'PRR': '&100',
- 'PRR_PRTWI': '$80',
- 'PRR_PRTIM2': '$40',
- 'PRR_PRTIM0': '$20',
- 'PRR_PRTIM1': '$08',
- 'PRR_PRSPI': '$04',
- 'PRR_PRUSART0': '$02',
- 'PRR_PRADC': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SELFPRGEN': '$01',
- 'MCUCR': '&85',
- 'MCUCR_BODS': '$40',
- 'MCUCR_BODSE': '$20',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'GPIOR2': '&75',
- 'GPIOR1': '&74',
- 'GPIOR0': '&62',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'PCINT0Addr': '3',
- 'PCINT1Addr': '4',
- 'PCINT2Addr': '5',
- 'WDTAddr': '6',
- 'TIMER2_COMPAAddr': '7',
- 'TIMER2_COMPBAddr': '8',
- 'TIMER2_OVFAddr': '9',
- 'TIMER1_CAPTAddr': '10',
- 'TIMER1_COMPAAddr': '11',
- 'TIMER1_COMPBAddr': '12',
- 'TIMER1_OVFAddr': '13',
- 'TIMER0_COMPAAddr': '14',
- 'TIMER0_COMPBAddr': '15',
- 'TIMER0_OVFAddr': '16',
- 'SPI__STCAddr': '17',
- 'USART__RXAddr': '18',
- 'USART__UDREAddr': '19',
- 'USART__TXAddr': '20',
- 'ADCAddr': '21',
- 'EE_READYAddr': '22',
- 'ANALOG_COMPAddr': '23',
- 'TWIAddr': '24',
- 'SPM_ReadyAddr': '25'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8a/atmega8a.frt b/amforth-6.5/avr8/devices/atmega8a/atmega8a.frt
deleted file mode 100644
index 842ccd3..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/atmega8a.frt
+++ /dev/null
@@ -1,207 +0,0 @@
-\ Partname: ATmega8A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&80 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
-&85 constant MCUCR \ MCU Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-\ TIMER_COUNTER_0
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-&83 constant TCCR0 \ Timer/Counter0 Control Register
- $04 constant TCCR0_CS02 \ Clock Select0 bit 2
- $02 constant TCCR0_CS01 \ Clock Select0 bit 1
- $01 constant TCCR0_CS00 \ Clock Select0 bit 0
-&82 constant TCNT0 \ Timer Counter 0
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&84 constant MCUCSR \ MCU Control And Status Register
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&81 constant OSCCAL \ Oscillator Calibration Value
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADFR \ ADC Free Running Select
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&10 constant SPI__STCAddr \ Serial Transfer Complete
-&11 constant USART__RXCAddr \ USART, Rx Complete
-&12 constant USART__UDREAddr \ USART Data Register Empty
-&13 constant USART__TXCAddr \ USART, Tx Complete
-&14 constant ADCAddr \ ADC Conversion Complete
-&15 constant EE_RDYAddr \ EEPROM Ready
-&16 constant ANA_COMPAddr \ Analog Comparator
-&17 constant TWIAddr \ 2-wire Serial Interface
-&18 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8a/device.asm b/amforth-6.5/avr8/devices/atmega8a/device.asm
deleted file mode 100644
index 067403d..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/device.asm
+++ /dev/null
@@ -1,95 +0,0 @@
-; Partname: ATmega8A
-; generated automatically, do not edit
-
-.nolist
- .include "m8Adef.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_USART = 0
-.set WANT_TWI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Timer/Counter2 Compare Match
-.org 4
- rcall isr ; Timer/Counter2 Overflow
-.org 5
- rcall isr ; Timer/Counter1 Capture Event
-.org 6
- rcall isr ; Timer/Counter1 Compare Match A
-.org 7
- rcall isr ; Timer/Counter1 Compare Match B
-.org 8
- rcall isr ; Timer/Counter1 Overflow
-.org 9
- rcall isr ; Timer/Counter0 Overflow
-.org 10
- rcall isr ; Serial Transfer Complete
-.org 11
- rcall isr ; USART, Rx Complete
-.org 12
- rcall isr ; USART Data Register Empty
-.org 13
- rcall isr ; USART, Tx Complete
-.org 14
- rcall isr ; ADC Conversion Complete
-.org 15
- rcall isr ; EEPROM Ready
-.org 16
- rcall isr ; Analog Comparator
-.org 17
- rcall isr ; 2-wire Serial Interface
-.org 18
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 19
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 19
-mcu_name:
- .dw 8
- .db "ATmega8A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8a/device.inc b/amforth-6.5/avr8/devices/atmega8a/device.inc
deleted file mode 100644
index ff1f890..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/device.inc
+++ /dev/null
@@ -1,696 +0,0 @@
-; Partname: ATmega8A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8a/device.py b/amforth-6.5/avr8/devices/atmega8a/device.py
deleted file mode 100644
index bcc03ff..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/device.py
+++ /dev/null
@@ -1,191 +0,0 @@
-# Partname: ATmega8A
-# generated automatically, do not edit
-MCUREGS = {
- 'SFIOR': '&80',
- 'SFIOR_ACME': '$08',
- 'ACSR': '&40',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'SPDR': '&47',
- 'SPSR': '&46',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&45',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'GICR': '&91',
- 'GICR_INT': '$C0',
- 'GICR_IVSEL': '$02',
- 'GICR_IVCE': '$01',
- 'GIFR': '&90',
- 'GIFR_INTF': '$C0',
- 'MCUCR': '&85',
- 'MCUCR_ISC1': '$0C',
- 'MCUCR_ISC0': '$03',
- 'TIMSK': '&89',
- 'TIMSK_TOIE0': '$01',
- 'TIFR': '&88',
- 'TIFR_TOV0': '$01',
- 'TCCR0': '&83',
- 'TCCR0_CS02': '$04',
- 'TCCR0_CS01': '$02',
- 'TCCR0_CS00': '$01',
- 'TCNT0': '&82',
- 'TCCR1A': '&79',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_FOC1A': '$08',
- 'TCCR1A_FOC1B': '$04',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&78',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCNT1': '&76',
- 'OCR1A': '&74',
- 'OCR1B': '&72',
- 'ICR1': '&70',
- 'TCCR2': '&69',
- 'TCCR2_FOC2': '$80',
- 'TCCR2_WGM20': '$40',
- 'TCCR2_COM2': '$30',
- 'TCCR2_WGM21': '$08',
- 'TCCR2_CS2': '$07',
- 'TCNT2': '&68',
- 'OCR2': '&67',
- 'ASSR': '&66',
- 'ASSR_AS2': '$08',
- 'ASSR_TCN2UB': '$04',
- 'ASSR_OCR2UB': '$02',
- 'ASSR_TCR2UB': '$01',
- 'UDR': '&44',
- 'UCSRA': '&43',
- 'UCSRA_RXC': '$80',
- 'UCSRA_TXC': '$40',
- 'UCSRA_UDRE': '$20',
- 'UCSRA_FE': '$10',
- 'UCSRA_DOR': '$08',
- 'UCSRA_UPE': '$04',
- 'UCSRA_U2X': '$02',
- 'UCSRA_MPCM': '$01',
- 'UCSRB': '&42',
- 'UCSRB_RXCIE': '$80',
- 'UCSRB_TXCIE': '$40',
- 'UCSRB_UDRIE': '$20',
- 'UCSRB_RXEN': '$10',
- 'UCSRB_TXEN': '$08',
- 'UCSRB_UCSZ2': '$04',
- 'UCSRB_RXB8': '$02',
- 'UCSRB_TXB8': '$01',
- 'UCSRC': '&64',
- 'UCSRC_URSEL': '$80',
- 'UCSRC_UMSEL': '$40',
- 'UCSRC_UPM': '$30',
- 'UCSRC_USBS': '$08',
- 'UCSRC_UCSZ': '$06',
- 'UCSRC_UCPOL': '$01',
- 'UBRRH': '&64',
- 'UBRRL': '&41',
- 'TWBR': '&32',
- 'TWCR': '&86',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&33',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&35',
- 'TWAR': '&34',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'WDTCR': '&65',
- 'WDTCR_WDCE': '$10',
- 'WDTCR_WDE': '$08',
- 'WDTCR_WDP': '$07',
- 'PORTB': '&56',
- 'DDRB': '&55',
- 'PINB': '&54',
- 'PORTC': '&53',
- 'DDRC': '&52',
- 'PINC': '&51',
- 'PORTD': '&50',
- 'DDRD': '&49',
- 'PIND': '&48',
- 'EEAR': '&62',
- 'EEDR': '&61',
- 'EECR': '&60',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'MCUCSR': '&84',
- 'MCUCSR_WDRF': '$08',
- 'MCUCSR_BORF': '$04',
- 'MCUCSR_EXTRF': '$02',
- 'MCUCSR_PORF': '$01',
- 'OSCCAL': '&81',
- 'SPMCR': '&87',
- 'SPMCR_SPMIE': '$80',
- 'SPMCR_RWWSB': '$40',
- 'SPMCR_RWWSRE': '$10',
- 'SPMCR_BLBSET': '$08',
- 'SPMCR_PGWRT': '$04',
- 'SPMCR_PGERS': '$02',
- 'SPMCR_SPMEN': '$01',
- 'ADMUX': '&39',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADCSRA': '&38',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADFR': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADC': '&36',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'TIMER2_COMPAddr': '3',
- 'TIMER2_OVFAddr': '4',
- 'TIMER1_CAPTAddr': '5',
- 'TIMER1_COMPAAddr': '6',
- 'TIMER1_COMPBAddr': '7',
- 'TIMER1_OVFAddr': '8',
- 'TIMER0_OVFAddr': '9',
- 'SPI__STCAddr': '10',
- 'USART__RXCAddr': '11',
- 'USART__UDREAddr': '12',
- 'USART__TXCAddr': '13',
- 'ADCAddr': '14',
- 'EE_RDYAddr': '15',
- 'ANA_COMPAddr': '16',
- 'TWIAddr': '17',
- 'SPM_RDYAddr': '18'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8a/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega8a/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt b/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt
deleted file mode 100644
index a2b741b..0000000
--- a/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt
+++ /dev/null
@@ -1,140 +0,0 @@
-\ Partname: ATmega8HVA
-\ Built using part description XML file version 1
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-79 constant VADCH \ VADC Data Register High Byte
-78 constant VADCL \ VADC Data Register Low Byte
-7A constant VADCSR \ The VADC Control and Status register
-7C constant VADMUX \ The VADC multiplexer Selection Register
-
-\ BANDGAP
-D0 constant BGCCR \ Bandgap Calibration Register
-D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder
-
-\ BATTERY_PROTECTION
-F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register
-F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register
-FD constant BPCR \ Battery Protection Control Register
-F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register
-F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register
-FC constant BPHCTR \ Battery Protection Short-current Timing Register
-F3 constant BPIFR \ Battery Protection Interrupt Flag Register
-F2 constant BPIMSK \ Battery Protection Interrupt Mask Register
-FB constant BPOCTR \ Battery Protection Over-current Timing Register
-FE constant BPPLR \ Battery Protection Parameter Lock Register
-F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
-FA constant BPSCTR \ Battery Protection Short-current Timing Register
-
-\ BOOT_LOAD
-57 constant SPMCSR \ Store Program Memory Control and Status Register
-
-\ COULOMB_COUNTER
-E0 constant CADAC0 \ ADC Accumulate Current
-E1 constant CADAC1 \ ADC Accumulate Current
-E2 constant CADAC2 \ ADC Accumulate Current
-E3 constant CADAC3 \ ADC Accumulate Current
-E4 constant CADCSRA \ CC-ADC Control and Status Register A
-E5 constant CADCSRB \ CC-ADC Control and Status Register B
-E9 constant CADICH \ CC-ADC Instantaneous Current
-E8 constant CADICL \ CC-ADC Instantaneous Current
-E6 constant CADRC \ CC-ADC Regular Current
-
-\ CPU
-61 constant CLKPR \ Clock Prescale Register
-7E constant DIDR0 \ Digital Input Disable Register
-66 constant FOSCCAL \ Fast Oscillator Calibration Value
-3E constant GPIOR0 \ General Purpose IO Register 0
-4A constant GPIOR1 \ General Purpose IO Register 1
-4B constant GPIOR2 \ General Purpose IO Register 2
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register
-64 constant PRR0 \ Power Reduction Register 0
-53 constant SMCR \ Sleep Mode Control Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-
-\ EEPROM
-41 constant EEAR \ EEPROM Read/Write Access
-3F constant EECR \ EEPROM Control Register
-40 constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-69 constant EICRA \ External Interrupt Control Register
-3C constant EIFR \ External Interrupt Flag Register
-3D constant EIMSK \ External Interrupt Mask Register
-
-\ FET
-F0 constant FCSR \ FET Control and Status Register
-
-\ PORTA
-21 constant DDRA \ Port A Data Direction Register
-20 constant PINA \ Port A Input Pins
-22 constant PORTA \ Port A Data Register
-
-\ PORTB
-24 constant DDRB \ Data Direction Register, Port B
-23 constant PINB \ Input Pins, Port B
-25 constant PORTB \ Data Register, Port B
-
-\ PORTC
-26 constant PINC \ Port C Input Pins
-28 constant PORTC \ Port C Data Register
-
-\ SPI
-4c constant SPCR \ SPI Control Register
-4e constant SPDR \ SPI Data Register
-4d constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-48 constant OCR0A \ Output compare Register A
-49 constant OCR0B \ Output compare Register B
-44 constant TCCR0A \ Timer/Counter0 Control Register
-45 constant TCCR0B \ Timer/Counter0 Control Register
-47 constant TCNT0H \ Timer Counter 0 High Byte
-46 constant TCNT0L \ Timer Counter 0 Low Byte
-35 constant TIFR0 \ Timer/Counter Interrupt Flag register
-6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-43 constant GTCCR \ General Timer/Counter Control Register
-88 constant OCR1A \ Output Compare Register 1A
-89 constant OCR1B \ Output Compare Register B
-80 constant TCCR1A \ Timer/Counter 1 Control Register A
-81 constant TCCR1B \ Timer/Counter1 Control Register B
-85 constant TCNT1H \ Timer Counter 1 High Byte
-84 constant TCNT1L \ Timer Counter 1 Low Byte
-36 constant TIFR1 \ Timer/Counter Interrupt Flag register
-6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
-
-\ VOLTAGE_REGULATOR
-C8 constant ROCR \ Regulator Operating Condition Register
-
-\ WATCHDOG
-60 constant WDTCSR \ Watchdog Timer Control Register
-
-\ Interrupts
-0001 constant BPINTAddr \ Battery Protection Interrupt
-0002 constant VREGMONAddr \ Voltage regulator monitor interrupt
-0003 constant INT0Addr \ External Interrupt Request 0
-0004 constant INT1Addr \ External Interrupt Request 1
-0005 constant INT2Addr \ External Interrupt Request 2
-0006 constant WDTAddr \ Watchdog Timeout Interrupt
-0007 constant TIMER1_ICAddr \ Timer 1 Input capture
-0008 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
-0009 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
-000A constant TIMER1_OVFAddr \ Timer 1 overflow
-000B constant TIMER0_ICAddr \ Timer 0 Input Capture
-000C constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
-000D constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
-000E constant TIMER0_OVFAddr \ Timer 0 Overflow
-000F constant SPI;STCAddr \ SPI Serial transfer complete
-0010 constant VADCAddr \ Voltage ADC Conversion Complete
-0011 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
-0012 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
-0013 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
-014 constant EE_READYAddr \ EEPROM Ready
diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.asm b/amforth-6.5/avr8/devices/atmega8hva/device.asm
deleted file mode 100644
index c556dc6..0000000
--- a/amforth-6.5/avr8/devices/atmega8hva/device.asm
+++ /dev/null
@@ -1,114 +0,0 @@
-; Partname: ATmega8HVA
-; Built using part description XML file version 1
-; generated automatically, do not edit
-
-.nolist
- .include "m8HVAdef.inc"
-.list
-
-.equ ramstart = $100
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_BANDGAP = 0
-.set WANT_BATTERY_PROTECTION = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_COULOMB_COUNTER = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_FET = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_VOLTAGE_REGULATOR = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 21
-.org $0001
- rcall isr ; Battery Protection Interrupt
-.org $0002
- rcall isr ; Voltage regulator monitor interrupt
-.org $0003
- rcall isr ; External Interrupt Request 0
-.org $0004
- rcall isr ; External Interrupt Request 1
-.org $0005
- rcall isr ; External Interrupt Request 2
-.org $0006
- rcall isr ; Watchdog Timeout Interrupt
-.org $0007
- rcall isr ; Timer 1 Input capture
-.org $0008
- rcall isr ; Timer 1 Compare Match A
-.org $0009
- rcall isr ; Timer 1 Compare Match B
-.org $000A
- rcall isr ; Timer 1 overflow
-.org $000B
- rcall isr ; Timer 0 Input Capture
-.org $000C
- rcall isr ; Timer 0 Comapre Match A
-.org $000D
- rcall isr ; Timer 0 Compare Match B
-.org $000E
- rcall isr ; Timer 0 Overflow
-.org $000F
- rcall isr ; SPI Serial transfer complete
-.org $0010
- rcall isr ; Voltage ADC Conversion Complete
-.org $0011
- rcall isr ; Coulomb Counter ADC Conversion Complete
-.org $0012
- rcall isr ; Coloumb Counter ADC Regular Current
-.org $0013
- rcall isr ; Coloumb Counter ADC Accumulator
-.org $014
- rcall isr ; EEPROM Ready
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 256
-mcu_maxdp:
- .dw 0 ; minimum of 0 (from XML) and 0xffff
-mcu_numints:
- .dw 21
-mcu_name:
- .dw 10
- .db "ATmega8HVA"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.inc b/amforth-6.5/avr8/devices/atmega8hva/device.inc
deleted file mode 100644
index 0405071..0000000
--- a/amforth-6.5/avr8/devices/atmega8hva/device.inc
+++ /dev/null
@@ -1,1053 +0,0 @@
-; Partname: ATmega8HVA
-; Built using part description XML file version 1
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register High Byte
-VE_VADCH:
- .dw $ff05
- .db "VADCH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCH
-XT_VADCH:
- .dw PFA_DOVARIABLE
-PFA_VADCH:
- .dw $79
-; ( -- addr ) System Constant
-; R( -- )
-; VADC Data Register Low Byte
-VE_VADCL:
- .dw $ff05
- .db "VADCL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCL
-XT_VADCL:
- .dw PFA_DOVARIABLE
-PFA_VADCL:
- .dw $78
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC Control and Status register
-VE_VADCSR:
- .dw $ff06
- .db "VADCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADCSR
-XT_VADCSR:
- .dw PFA_DOVARIABLE
-PFA_VADCSR:
- .dw $7A
-; ( -- addr ) System Constant
-; R( -- )
-; The VADC multiplexer Selection Register
-VE_VADMUX:
- .dw $ff06
- .db "VADMUX"
- .dw VE_HEAD
- .set VE_HEAD=VE_VADMUX
-XT_VADMUX:
- .dw PFA_DOVARIABLE
-PFA_VADMUX:
- .dw $7C
-
-.endif
-
-; ********
-.if WANT_BANDGAP == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration Register
-VE_BGCCR:
- .dw $ff05
- .db "BGCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCCR
-XT_BGCCR:
- .dw PFA_DOVARIABLE
-PFA_BGCCR:
- .dw $D0
-; ( -- addr ) System Constant
-; R( -- )
-; Bandgap Calibration of Resistor Ladder
-VE_BGCRR:
- .dw $ff05
- .db "BGCRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCRR
-XT_BGCRR:
- .dw PFA_DOVARIABLE
-PFA_BGCRR:
- .dw $D1
-
-.endif
-
-; ********
-.if WANT_BATTERY_PROTECTION == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Charge-High-current Detection Level Register
-VE_BPCHCD:
- .dw $ff06
- .db "BPCHCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCHCD
-XT_BPCHCD:
- .dw PFA_DOVARIABLE
-PFA_BPCHCD:
- .dw $F9
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Charge-Over-current Detection Level Register
-VE_BPCOCD:
- .dw $ff06
- .db "BPCOCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCOCD
-XT_BPCOCD:
- .dw PFA_DOVARIABLE
-PFA_BPCOCD:
- .dw $F7
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Control Register
-VE_BPCR:
- .dw $ff04
- .db "BPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPCR
-XT_BPCR:
- .dw PFA_DOVARIABLE
-PFA_BPCR:
- .dw $FD
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Discharge-High-current Detection Level Register
-VE_BPDHCD:
- .dw $ff06
- .db "BPDHCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDHCD
-XT_BPDHCD:
- .dw PFA_DOVARIABLE
-PFA_BPDHCD:
- .dw $F8
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Discharge-Over-current Detection Level Register
-VE_BPDOCD:
- .dw $ff06
- .db "BPDOCD"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPDOCD
-XT_BPDOCD:
- .dw PFA_DOVARIABLE
-PFA_BPDOCD:
- .dw $F6
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-current Timing Register
-VE_BPHCTR:
- .dw $ff06
- .db "BPHCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPHCTR
-XT_BPHCTR:
- .dw PFA_DOVARIABLE
-PFA_BPHCTR:
- .dw $FC
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Flag Register
-VE_BPIFR:
- .dw $ff05
- .db "BPIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIFR
-XT_BPIFR:
- .dw PFA_DOVARIABLE
-PFA_BPIFR:
- .dw $F3
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Interrupt Mask Register
-VE_BPIMSK:
- .dw $ff06
- .db "BPIMSK"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPIMSK
-XT_BPIMSK:
- .dw PFA_DOVARIABLE
-PFA_BPIMSK:
- .dw $F2
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Over-current Timing Register
-VE_BPOCTR:
- .dw $ff06
- .db "BPOCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPOCTR
-XT_BPOCTR:
- .dw PFA_DOVARIABLE
-PFA_BPOCTR:
- .dw $FB
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Parameter Lock Register
-VE_BPPLR:
- .dw $ff05
- .db "BPPLR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPPLR
-XT_BPPLR:
- .dw PFA_DOVARIABLE
-PFA_BPPLR:
- .dw $FE
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-Circuit Detection Level Register
-VE_BPSCD:
- .dw $ff05
- .db "BPSCD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCD
-XT_BPSCD:
- .dw PFA_DOVARIABLE
-PFA_BPSCD:
- .dw $F5
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Protection Short-current Timing Register
-VE_BPSCTR:
- .dw $ff06
- .db "BPSCTR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BPSCTR
-XT_BPSCTR:
- .dw PFA_DOVARIABLE
-PFA_BPSCTR:
- .dw $FA
-
-.endif
-
-; ********
-.if WANT_BOOT_LOAD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_COULOMB_COUNTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC0:
- .dw $ff06
- .db "CADAC0"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC0
-XT_CADAC0:
- .dw PFA_DOVARIABLE
-PFA_CADAC0:
- .dw $E0
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC1:
- .dw $ff06
- .db "CADAC1"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC1
-XT_CADAC1:
- .dw PFA_DOVARIABLE
-PFA_CADAC1:
- .dw $E1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC2:
- .dw $ff06
- .db "CADAC2"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC2
-XT_CADAC2:
- .dw PFA_DOVARIABLE
-PFA_CADAC2:
- .dw $E2
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Accumulate Current
-VE_CADAC3:
- .dw $ff06
- .db "CADAC3"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADAC3
-XT_CADAC3:
- .dw PFA_DOVARIABLE
-PFA_CADAC3:
- .dw $E3
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register A
-VE_CADCSRA:
- .dw $ff07
- .db "CADCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRA
-XT_CADCSRA:
- .dw PFA_DOVARIABLE
-PFA_CADCSRA:
- .dw $E4
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Control and Status Register B
-VE_CADCSRB:
- .dw $ff07
- .db "CADCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADCSRB
-XT_CADCSRB:
- .dw PFA_DOVARIABLE
-PFA_CADCSRB:
- .dw $E5
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADICH:
- .dw $ff06
- .db "CADICH"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICH
-XT_CADICH:
- .dw PFA_DOVARIABLE
-PFA_CADICH:
- .dw $E9
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Instantaneous Current
-VE_CADICL:
- .dw $ff06
- .db "CADICL"
- .dw VE_HEAD
- .set VE_HEAD=VE_CADICL
-XT_CADICL:
- .dw PFA_DOVARIABLE
-PFA_CADICL:
- .dw $E8
-; ( -- addr ) System Constant
-; R( -- )
-; CC-ADC Regular Current
-VE_CADRC:
- .dw $ff05
- .db "CADRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CADRC
-XT_CADRC:
- .dw PFA_DOVARIABLE
-PFA_CADRC:
- .dw $E6
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw $61
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw $7E
-; ( -- addr ) System Constant
-; R( -- )
-; Fast Oscillator Calibration Value
-VE_FOSCCAL:
- .dw $ff07
- .db "FOSCCAL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_FOSCCAL
-XT_FOSCCAL:
- .dw PFA_DOVARIABLE
-PFA_FOSCCAL:
- .dw $66
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Sampling Interface Control and Status Register
-VE_OSICSR:
- .dw $ff06
- .db "OSICSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSICSR
-XT_OSICSR:
- .dw PFA_DOVARIABLE
-PFA_OSICSR:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw $64
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw $41
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $40
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw $69
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_FET == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; FET Control and Status Register
-VE_FCSR:
- .dw $ff04
- .db "FCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_FCSR
-XT_FCSR:
- .dw PFA_DOVARIABLE
-PFA_FCSR:
- .dw $F0
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $20
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $22
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port B
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port B
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $23
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port B
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $25
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $4c
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $4e
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $4d
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register A
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Output compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw $44
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 High Byte
-VE_TCNT0H:
- .dw $ff06
- .db "TCNT0H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0H
-XT_TCNT0H:
- .dw PFA_DOVARIABLE
-PFA_TCNT0H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0 Low Byte
-VE_TCNT0L:
- .dw $ff06
- .db "TCNT0L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0L
-XT_TCNT0L:
- .dw PFA_DOVARIABLE
-PFA_TCNT0L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw $35
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw $6E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register 1A
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw $88
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register B
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw $89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $80
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $81
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $85
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $84
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw $6F
-
-.endif
-
-; ********
-.if WANT_VOLTAGE_REGULATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Operating Condition Register
-VE_ROCR:
- .dw $ff04
- .db "ROCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ROCR
-XT_ROCR:
- .dw PFA_DOVARIABLE
-PFA_ROCR:
- .dw $C8
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw $60
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.py b/amforth-6.5/avr8/devices/atmega8hva/device.py
deleted file mode 100644
index d16cdad..0000000
--- a/amforth-6.5/avr8/devices/atmega8hva/device.py
+++ /dev/null
@@ -1,104 +0,0 @@
-# Partname: ATmega8HVA
-# Built using part description XML file version 1
-# generated automatically, do not edit
-MCUREGS = {
- 'VADCH': '$79',
- 'VADCL': '$78',
- 'VADCSR': '$7A',
- 'VADMUX': '$7C',
- 'BGCCR': '$D0',
- 'BGCRR': '$D1',
- 'BPCHCD': '$F9',
- 'BPCOCD': '$F7',
- 'BPCR': '$FD',
- 'BPDHCD': '$F8',
- 'BPDOCD': '$F6',
- 'BPHCTR': '$FC',
- 'BPIFR': '$F3',
- 'BPIMSK': '$F2',
- 'BPOCTR': '$FB',
- 'BPPLR': '$FE',
- 'BPSCD': '$F5',
- 'BPSCTR': '$FA',
- 'SPMCSR': '$57',
- 'CADAC0': '$E0',
- 'CADAC1': '$E1',
- 'CADAC2': '$E2',
- 'CADAC3': '$E3',
- 'CADCSRA': '$E4',
- 'CADCSRB': '$E5',
- 'CADICH': '$E9',
- 'CADICL': '$E8',
- 'CADRC': '$E6',
- 'CLKPR': '$61',
- 'DIDR0': '$7E',
- 'FOSCCAL': '$66',
- 'GPIOR0': '$3E',
- 'GPIOR1': '$4A',
- 'GPIOR2': '$4B',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'OSICSR': '$37',
- 'PRR0': '$64',
- 'SMCR': '$53',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'EEAR': '$41',
- 'EECR': '$3F',
- 'EEDR': '$40',
- 'EICRA': '$69',
- 'EIFR': '$3C',
- 'EIMSK': '$3D',
- 'FCSR': '$F0',
- 'DDRA': '$21',
- 'PINA': '$20',
- 'PORTA': '$22',
- 'DDRB': '$24',
- 'PINB': '$23',
- 'PORTB': '$25',
- 'PINC': '$26',
- 'PORTC': '$28',
- 'SPCR': '$4c',
- 'SPDR': '$4e',
- 'SPSR': '$4d',
- 'OCR0A': '$48',
- 'OCR0B': '$49',
- 'TCCR0A': '$44',
- 'TCCR0B': '$45',
- 'TCNT0H': '$47',
- 'TCNT0L': '$46',
- 'TIFR0': '$35',
- 'TIMSK0': '$6E',
- 'GTCCR': '$43',
- 'OCR1A': '$88',
- 'OCR1B': '$89',
- 'TCCR1A': '$80',
- 'TCCR1B': '$81',
- 'TCNT1H': '$85',
- 'TCNT1L': '$84',
- 'TIFR1': '$36',
- 'TIMSK1': '$6F',
- 'ROCR': '$C8',
- 'WDTCSR': '$60',
- 'BPINTAddr': '$0001',
- 'VREGMONAddr': '$0002',
- 'INT0Addr': '$0003',
- 'INT1Addr': '$0004',
- 'INT2Addr': '$0005',
- 'WDTAddr': '$0006',
- 'TIMER1_ICAddr': '$0007',
- 'TIMER1_COMPAAddr': '$0008',
- 'TIMER1_COMPBAddr': '$0009',
- 'TIMER1_OVFAddr': '$000A',
- 'TIMER0_ICAddr': '$000B',
- 'TIMER0_COMPAAddr': '$000C',
- 'TIMER0_COMPBAddr': '$000D',
- 'TIMER0_OVFAddr': '$000E',
- 'SPI;STCAddr': '$000F',
- 'VADCAddr': '$0010',
- 'CCADC_CONVAddr': '$0011',
- 'CCADC_REG_CURAddr': '$0012',
- 'CCADC_ACCAddr': '$0013',
- 'EE_READYAddr': '$014'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt b/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt
deleted file mode 100644
index 5c42559..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt
+++ /dev/null
@@ -1,357 +0,0 @@
-\ Partname: ATmega8U2
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_DEVICE
-&244 constant UEINT \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $1F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
-&99 constant REGCR \ Regulator Control Register
- $01 constant REGCR_REGDIS \
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $20 constant MCUSR_USBRF \ USB reset flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
-&210 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&209 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&208 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-&81 constant DWDR \ debugWire communication register
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $1F constant PCMSK1_PCINT \
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&203 constant UCSR1D \ USART Control and Status Register D
- $02 constant UCSR1D_CTSEN \ CTS Enable
- $01 constant UCSR1D_RTSEN \ RTS Enable
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-&98 constant WDTCKD \ Watchdog Timer Clock Divider
- $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
- $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
- $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTC
-&40 constant PORTC \ Port C Data Register
- $F0 constant PORTC_PORTC \ Port C Data Register bits
- $07 constant PORTC_PORTC \ Port C Data Register bits
-&39 constant DDRC \ Port C Data Direction Register
- $F0 constant DDRC_DDC \ Port C Data Direction Register bits
- $07 constant DDRC_DDC \ Port C Data Direction Register bits
-&38 constant PINC \ Port C Input Pins
- $F0 constant PINC_PINC \ Port C Input Pins bits
- $07 constant PINC_PINC \ Port C Input Pins bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant USB_GENAddr \ USB General Interrupt Request
-&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&26 constant WDTAddr \ Watchdog Time-out Interrupt
-&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
-&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
-&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
-&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
-&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&46 constant USART1__RXAddr \ USART1, Rx Complete
-&48 constant USART1__UDREAddr \ USART1 Data register Empty
-&50 constant USART1__TXAddr \ USART1, Tx Complete
-&52 constant ANALOG_COMPAddr \ Analog Comparator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.asm b/amforth-6.5/avr8/devices/atmega8u2/device.asm
deleted file mode 100644
index e8040e5..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/device.asm
+++ /dev/null
@@ -1,112 +0,0 @@
-; Partname: ATmega8U2
-; generated automatically, do not edit
-
-.nolist
- .include "m8U2def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTC = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; USB General Interrupt Request
-.org 24
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 26
- rcall isr ; Watchdog Time-out Interrupt
-.org 28
- rcall isr ; Timer/Counter2 Capture Event
-.org 30
- rcall isr ; Timer/Counter2 Compare Match B
-.org 32
- rcall isr ; Timer/Counter2 Compare Match B
-.org 34
- rcall isr ; Timer/Counter2 Compare Match C
-.org 36
- rcall isr ; Timer/Counter1 Overflow
-.org 38
- rcall isr ; Timer/Counter0 Compare Match A
-.org 40
- rcall isr ; Timer/Counter0 Compare Match B
-.org 42
- rcall isr ; Timer/Counter0 Overflow
-.org 44
- rcall isr ; SPI Serial Transfer Complete
-.org 46
- rcall isr ; USART1, Rx Complete
-.org 48
- rcall isr ; USART1 Data register Empty
-.org 50
- rcall isr ; USART1, Tx Complete
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 4096
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 9
- .db "ATmega8U2",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.inc b/amforth-6.5/avr8/devices/atmega8u2/device.inc
deleted file mode 100644
index bee0007..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega8U2
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Control Register
-VE_REGCR:
- .dw $ff05
- .db "REGCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_REGCR
-XT_REGCR:
- .dw PFA_DOVARIABLE
-PFA_REGCR:
- .dw 99
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; debugWire communication register
-VE_DWDR:
- .dw $ff04
- .db "DWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_DWDR
-XT_DWDR:
- .dw PFA_DOVARIABLE
-PFA_DWDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register D
-VE_UCSR1D:
- .dw $ff06
- .db "UCSR1D"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1D
-XT_UCSR1D:
- .dw PFA_DOVARIABLE
-PFA_UCSR1D:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Clock Divider
-VE_WDTCKD:
- .dw $ff06
- .db "WDTCKD"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCKD
-XT_WDTCKD:
- .dw PFA_DOVARIABLE
-PFA_WDTCKD:
- .dw 98
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.py b/amforth-6.5/avr8/devices/atmega8u2/device.py
deleted file mode 100644
index 34d5823..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/device.py
+++ /dev/null
@@ -1,341 +0,0 @@
-# Partname: ATmega8U2
-# generated automatically, do not edit
-MCUREGS = {
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPDR': '&78',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_SIGRD': '$20',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SPMEN': '$01',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMPE': '$04',
- 'EECR_EEPE': '$02',
- 'EECR_EERE': '$01',
- 'OCR0B': '&72',
- 'OCR0A': '&71',
- 'TCNT0': '&70',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSRSYNC': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_COM1C': '$0C',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCCR1C_FOC1C': '$20',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'OCR1C': '&140',
- 'ICR1': '&134',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1C': '$08',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1C': '$08',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'PLLCSR': '&73',
- 'PLLCSR_PLLP': '$1C',
- 'PLLCSR_PLLE': '$02',
- 'PLLCSR_PLOCK': '$01',
- 'UEINT': '&244',
- 'UEBCLX': '&242',
- 'UEDATX': '&241',
- 'UEIENX': '&240',
- 'UEIENX_FLERRE': '$80',
- 'UEIENX_NAKINE': '$40',
- 'UEIENX_NAKOUTE': '$10',
- 'UEIENX_RXSTPE': '$08',
- 'UEIENX_RXOUTE': '$04',
- 'UEIENX_STALLEDE': '$02',
- 'UEIENX_TXINE': '$01',
- 'UESTA1X': '&239',
- 'UESTA1X_CTRLDIR': '$04',
- 'UESTA1X_CURRBK': '$03',
- 'UESTA0X': '&238',
- 'UESTA0X_CFGOK': '$80',
- 'UESTA0X_OVERFI': '$40',
- 'UESTA0X_UNDERFI': '$20',
- 'UESTA0X_DTSEQ': '$0C',
- 'UESTA0X_NBUSYBK': '$03',
- 'UECFG1X': '&237',
- 'UECFG1X_EPSIZE': '$70',
- 'UECFG1X_EPBK': '$0C',
- 'UECFG1X_ALLOC': '$02',
- 'UECFG0X': '&236',
- 'UECFG0X_EPTYPE': '$C0',
- 'UECFG0X_EPDIR': '$01',
- 'UECONX': '&235',
- 'UECONX_STALLRQ': '$20',
- 'UECONX_STALLRQC': '$10',
- 'UECONX_RSTDT': '$08',
- 'UECONX_EPEN': '$01',
- 'UERST': '&234',
- 'UERST_EPRST': '$1F',
- 'UENUM': '&233',
- 'UEINTX': '&232',
- 'UEINTX_FIFOCON': '$80',
- 'UEINTX_NAKINI': '$40',
- 'UEINTX_RWAL': '$20',
- 'UEINTX_NAKOUTI': '$10',
- 'UEINTX_RXSTPI': '$08',
- 'UEINTX_RXOUTI': '$04',
- 'UEINTX_STALLEDI': '$02',
- 'UEINTX_TXINI': '$01',
- 'UDMFN': '&230',
- 'UDMFN_FNCERR': '$10',
- 'UDFNUM': '&228',
- 'UDADDR': '&227',
- 'UDADDR_ADDEN': '$80',
- 'UDADDR_UADD': '$7F',
- 'UDIEN': '&226',
- 'UDIEN_UPRSME': '$40',
- 'UDIEN_EORSME': '$20',
- 'UDIEN_WAKEUPE': '$10',
- 'UDIEN_EORSTE': '$08',
- 'UDIEN_SOFE': '$04',
- 'UDIEN_SUSPE': '$01',
- 'UDINT': '&225',
- 'UDINT_UPRSMI': '$40',
- 'UDINT_EORSMI': '$20',
- 'UDINT_WAKEUPI': '$10',
- 'UDINT_EORSTI': '$08',
- 'UDINT_SOFI': '$04',
- 'UDINT_SUSPI': '$01',
- 'UDCON': '&224',
- 'UDCON_RSTCPU': '$04',
- 'UDCON_RMWKUP': '$02',
- 'UDCON_DETACH': '$01',
- 'USBCON': '&216',
- 'USBCON_USBE': '$80',
- 'USBCON_FRZCLK': '$20',
- 'REGCR': '&99',
- 'REGCR_REGDIS': '$01',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'MCUCR': '&85',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_USBRF': '$20',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'EIND': '&92',
- 'GPIOR2': '&75',
- 'GPIOR2_GPIOR': '$FF',
- 'GPIOR1': '&74',
- 'GPIOR1_GPIOR': '$FF',
- 'GPIOR0': '&62',
- 'GPIOR0_GPIOR07': '$80',
- 'GPIOR0_GPIOR06': '$40',
- 'GPIOR0_GPIOR05': '$20',
- 'GPIOR0_GPIOR04': '$10',
- 'GPIOR0_GPIOR03': '$08',
- 'GPIOR0_GPIOR02': '$04',
- 'GPIOR0_GPIOR01': '$02',
- 'GPIOR0_GPIOR00': '$01',
- 'PRR1': '&101',
- 'PRR1_PRUSB': '$80',
- 'PRR1_PRUSART1': '$01',
- 'PRR0': '&100',
- 'PRR0_PRTIM0': '$20',
- 'PRR0_PRTIM1': '$08',
- 'PRR0_PRSPI': '$04',
- 'CLKSTA': '&210',
- 'CLKSTA_RCON': '$02',
- 'CLKSTA_EXTON': '$01',
- 'CLKSEL1': '&209',
- 'CLKSEL1_RCCKSEL': '$F0',
- 'CLKSEL1_EXCKSEL': '$0F',
- 'CLKSEL0': '&208',
- 'CLKSEL0_RCSUT': '$C0',
- 'CLKSEL0_EXSUT': '$30',
- 'CLKSEL0_RCE': '$08',
- 'CLKSEL0_EXTE': '$04',
- 'CLKSEL0_CLKS': '$01',
- 'DWDR': '&81',
- 'EICRA': '&105',
- 'EICRA_ISC3': '$C0',
- 'EICRA_ISC2': '$30',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EICRB': '&106',
- 'EICRB_ISC7': '$C0',
- 'EICRB_ISC6': '$30',
- 'EICRB_ISC5': '$0C',
- 'EICRB_ISC4': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$FF',
- 'EIFR': '&60',
- 'EIFR_INTF': '$FF',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$1F',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$03',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$03',
- 'UDR1': '&206',
- 'UCSR1A': '&200',
- 'UCSR1A_RXC1': '$80',
- 'UCSR1A_TXC1': '$40',
- 'UCSR1A_UDRE1': '$20',
- 'UCSR1A_FE1': '$10',
- 'UCSR1A_DOR1': '$08',
- 'UCSR1A_UPE1': '$04',
- 'UCSR1A_U2X1': '$02',
- 'UCSR1A_MPCM1': '$01',
- 'UCSR1B': '&201',
- 'UCSR1B_RXCIE1': '$80',
- 'UCSR1B_TXCIE1': '$40',
- 'UCSR1B_UDRIE1': '$20',
- 'UCSR1B_RXEN1': '$10',
- 'UCSR1B_TXEN1': '$08',
- 'UCSR1B_UCSZ12': '$04',
- 'UCSR1B_RXB81': '$02',
- 'UCSR1B_TXB81': '$01',
- 'UCSR1C': '&202',
- 'UCSR1C_UMSEL1': '$C0',
- 'UCSR1C_UPM1': '$30',
- 'UCSR1C_USBS1': '$08',
- 'UCSR1C_UCSZ1': '$06',
- 'UCSR1C_UCPOL1': '$01',
- 'UCSR1D': '&203',
- 'UCSR1D_CTSEN': '$02',
- 'UCSR1D_RTSEN': '$01',
- 'UBRR1': '&204',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'WDTCKD': '&98',
- 'WDTCKD_WDEWIF': '$08',
- 'WDTCKD_WDEWIE': '$04',
- 'WDTCKD_WCLKD': '$03',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTC': '&40',
- 'PORTC_PORTC': '$F0',
- 'PORTC_PORTC': '$07',
- 'DDRC': '&39',
- 'DDRC_DDC': '$F0',
- 'DDRC_DDC': '$07',
- 'PINC': '&38',
- 'PINC_PINC': '$F0',
- 'PINC_PINC': '$07',
- 'INT0Addr': '2',
- 'INT1Addr': '4',
- 'INT2Addr': '6',
- 'INT3Addr': '8',
- 'INT4Addr': '10',
- 'INT5Addr': '12',
- 'INT6Addr': '14',
- 'INT7Addr': '16',
- 'PCINT0Addr': '18',
- 'PCINT1Addr': '20',
- 'USB_GENAddr': '22',
- 'USB_COMAddr': '24',
- 'WDTAddr': '26',
- 'TIMER1_CAPTAddr': '28',
- 'TIMER1_COMPAAddr': '30',
- 'TIMER1_COMPBAddr': '32',
- 'TIMER1_COMPCAddr': '34',
- 'TIMER1_OVFAddr': '36',
- 'TIMER0_COMPAAddr': '38',
- 'TIMER0_COMPBAddr': '40',
- 'TIMER0_OVFAddr': '42',
- 'SPI__STCAddr': '44',
- 'USART1__RXAddr': '46',
- 'USART1__UDREAddr': '48',
- 'USART1__TXAddr': '50',
- 'ANALOG_COMPAddr': '52',
- 'EE_READYAddr': '54',
- 'SPM_READYAddr': '56'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/dict/appl_2k.inc b/amforth-6.5/avr8/dict/appl_2k.inc
deleted file mode 100644
index 40f6ec3..0000000
--- a/amforth-6.5/avr8/dict/appl_2k.inc
+++ /dev/null
@@ -1,175 +0,0 @@
-.include "words/d-2star.asm"
-.include "words/d-2slash.asm"
-.include "words/d-plus.asm"
-.include "words/d-minus.asm"
-.include "words/d-invert.asm"
-.include "words/u-dot.asm"
-.include "words/u-dot-r.asm"
-
-.include "words/show-wordlist.asm"
-.include "words/words.asm"
-.include "dict/interrupt.inc"
-
-.include "words/pick.asm"
-.include "words/dot-quote.asm"
-.include "words/squote.asm"
-
-.include "words/fill.asm"
-.include "dict/compiler1.inc"
-
-.include "words/environment.asm"
-.include "words/env-wordlists.asm"
-.include "words/env-slashpad.asm"
-.include "words/env-slashhold.asm"
-.include "words/env-forthname.asm"
-.include "words/env-forthversion.asm"
-.include "words/env-cpu.asm"
-.include "words/env-mcuinfo.asm"
-.include "words/env-usersize.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/f_cpu.asm"
-.include "words/state.asm"
-.include "words/base.asm"
-
-.include "words/cells.asm"
-.include "words/cellplus.asm"
-
-.include "words/2dup.asm"
-.include "words/2drop.asm"
-
-.include "words/tuck.asm"
-
-.include "words/to-in.asm"
-.include "words/pad.asm"
-.include "words/emit.asm"
-.include "words/emitq.asm"
-.include "words/key.asm"
-.include "words/keyq.asm"
-
-.include "words/dp.asm"
-.include "words/ehere.asm"
-.include "words/here.asm"
-.include "words/allot.asm"
-
-.include "words/bin.asm"
-.include "words/decimal.asm"
-.include "words/hex.asm"
-.include "words/bl.asm"
-
-.include "words/turnkey.asm"
-
-.include "words/slashmod.asm"
-.include "words/uslashmod.asm"
-.include "words/negate.asm"
-.include "words/slash.asm"
-.include "words/mod.asm"
-.include "words/abs.asm"
-.include "words/min.asm"
-.include "words/max.asm"
-.include "words/within.asm"
-
-.include "words/to-upper.asm"
-.include "words/to-lower.asm"
-;;;;;;;;;;;;;;;;;;;;;;
-.include "words/hld.asm"
-.include "words/hold.asm"
-.include "words/less-sharp.asm" ; <#
-.include "words/sharp.asm"
-.include "words/sharp-s.asm"
-.include "words/sharp-greater.asm" ; #>
-.include "words/sign.asm"
-.include "words/d-dot-r.asm"
-.include "words/dot-r.asm"
-.include "words/d-dot.asm"
-.include "words/dot.asm"
-.include "words/ud-dot.asm"
-.include "words/ud-dot-r.asm"
-.include "words/ud-slash-mod.asm"
-.include "words/digit-q.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/do-sliteral.asm"
-.include "words/scomma.asm"
-.include "words/itype.asm"
-.include "words/icount.asm"
-.include "words/cr.asm"
-.include "words/space.asm"
-.include "words/spaces.asm"
-.include "words/type.asm"
-.include "words/tick.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/handler.asm"
-.include "words/catch.asm"
-.include "words/throw.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/cskip.asm"
-.include "words/cscan.asm"
-.include "words/accept.asm"
-.include "words/refill.asm"
-.include "words/char.asm"
-.include "words/number.asm"
-.include "words/q-sign.asm"
-.include "words/set-base.asm"
-.include "words/to-number.asm"
-.include "words/parse.asm"
-.include "words/source.asm"
-.include "words/slash-string.asm"
-.include "words/parse-name.asm"
-.include "words/find-xt.asm"
-
-.include "words/quit.asm"
-.include "words/prompt-ok.asm"
-.include "words/prompt-ready.asm"
-.include "words/prompt-error.asm"
-.include "words/pause.asm"
-.include "words/cold.asm"
-.include "words/warm.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/sp0.asm"
-.include "words/rp0.asm"
-.include "words/depth.asm"
-.include "words/recognize.asm"
-.include "words/forth-recognizer.asm"
-.include "words/interpret.asm"
-.include "words/rec-intnum.asm"
-.include "words/rec-find.asm"
-.include "words/dt-null.asm"
-
-.include "words/q-stack.asm"
-.include "words/ver.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/noop.asm"
-.include "words/unused.asm"
-
-.include "words/to.asm"
-.include "words/i-cellplus.asm"
-
-.include "words/edefer-fetch.asm"
-.include "words/edefer-store.asm"
-.include "words/rdefer-fetch.asm"
-.include "words/rdefer-store.asm"
-.include "words/udefer-fetch.asm"
-.include "words/udefer-store.asm"
-.include "words/defer-store.asm"
-.include "words/defer-fetch.asm"
-.include "words/do-defer.asm"
-
-.include "words/search-wordlist.asm"
-.include "words/traverse-wordlist.asm"
-.include "words/name2string.asm"
-.include "words/nfa2cfa.asm"
-.include "words/icompare.asm"
-
-.include "words/star.asm"
-.include "words/j.asm"
-
-.include "words/dabs.asm"
-.include "words/dnegate.asm"
-.include "words/cmove.asm"
-.include "words/2swap.asm"
-
-.include "words/tib.asm"
-
-.include "words/init-ram.asm"
-.include "words/bounds.asm"
-.include "words/s-to-d.asm"
-.include "words/to-body.asm"
diff --git a/amforth-6.5/avr8/dict/appl_4k.inc b/amforth-6.5/avr8/dict/appl_4k.inc
deleted file mode 100644
index 8cc8451..0000000
--- a/amforth-6.5/avr8/dict/appl_4k.inc
+++ /dev/null
@@ -1,81 +0,0 @@
-.include "words/ver.asm"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/noop.asm"
-.include "words/unused.asm"
-.include "words/to.asm"
-.include "words/i-cellplus.asm"
-.include "words/icompare.asm"
-.include "words/star.asm"
-.include "words/j.asm"
-.include "words/dabs.asm"
-.include "words/dnegate.asm"
-.include "words/cmove.asm"
-.include "words/2swap.asm"
-.include "words/tib.asm"
-.include "words/init-ram.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-
-.include "words/environment.asm"
-.include "words/env-wordlists.asm"
-.include "words/env-slashpad.asm"
-.include "words/env-slashhold.asm"
-.include "words/env-forthname.asm"
-.include "words/env-forthversion.asm"
-.include "words/env-cpu.asm"
-.include "words/env-mcuinfo.asm"
-.include "words/env-usersize.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/hld.asm"
-.include "words/hold.asm"
-.include "words/less-sharp.asm" ; <#
-.include "words/sharp.asm"
-.include "words/sharp-s.asm"
-.include "words/sharp-greater.asm" ; #>
-.include "words/sign.asm"
-.include "words/d-dot-r.asm"
-.include "words/dot-r.asm"
-.include "words/d-dot.asm"
-.include "words/dot.asm"
-.include "words/ud-dot.asm"
-.include "words/ud-dot-r.asm"
-.include "words/ud-slash-mod.asm"
-.include "words/digit-q.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/do-sliteral.asm"
-.include "words/scomma.asm"
-.include "words/itype.asm"
-.include "words/icount.asm"
-.include "words/type.asm"
-.include "words/tick.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/cskip.asm"
-.include "words/cscan.asm"
-.include "words/accept.asm"
-.include "words/refill.asm"
-.include "words/char.asm"
-.include "words/number.asm"
-.include "words/q-sign.asm"
-.include "words/set-base.asm"
-.include "words/to-number.asm"
-.include "words/parse.asm"
-.include "words/source.asm"
-.include "words/slash-string.asm"
-.include "words/parse-name.asm"
-.include "words/sp0.asm"
-.include "words/rp0.asm"
-.include "words/depth.asm"
-.include "words/forth-recognizer.asm"
-.include "words/recognize.asm"
-.include "words/interpret.asm"
-.include "words/rec-intnum.asm"
-.include "words/rec-find.asm"
-.include "words/dt-null.asm"
-.include "words/search-wordlist.asm"
-.include "words/traverse-wordlist.asm"
-.include "words/name2string.asm"
-.include "words/nfa2cfa.asm"
-.include "words/find-xt.asm"
-
-.include "dict/compiler1.inc"
diff --git a/amforth-6.5/avr8/dict/appl_8k.inc b/amforth-6.5/avr8/dict/appl_8k.inc
deleted file mode 100644
index bfedb0a..0000000
--- a/amforth-6.5/avr8/dict/appl_8k.inc
+++ /dev/null
@@ -1 +0,0 @@
-.include "dict/compiler1.inc"
diff --git a/amforth-6.5/avr8/dict/compiler1.inc b/amforth-6.5/avr8/dict/compiler1.inc
deleted file mode 100644
index 7baa432..0000000
--- a/amforth-6.5/avr8/dict/compiler1.inc
+++ /dev/null
@@ -1,70 +0,0 @@
-
-.include "words/newest.asm"
-.include "words/latest.asm"
-.include "words/do-create.asm"
-.include "words/backslash.asm"
-.include "words/l-paren.asm"
-
-.include "words/compile.asm"
-.include "words/comma.asm"
-.include "words/brackettick.asm"
-
-
-.include "words/literal.asm"
-.include "words/sliteral.asm"
-.include "words/g-mark.asm"
-.include "words/g-resolve.asm"
-.include "words/l_mark.asm"
-.include "words/l_resolve.asm"
-
-.include "words/ahead.asm"
-.include "words/if.asm"
-.include "words/else.asm"
-.include "words/then.asm"
-.include "words/begin.asm"
-.include "words/while.asm"
-.include "words/repeat.asm"
-.include "words/until.asm"
-.include "words/again.asm"
-.include "words/do.asm"
-.include "words/loop.asm"
-.include "words/plusloop.asm"
-.include "words/leave.asm"
-.include "words/qdo.asm"
-.include "words/endloop.asm"
-; leave address stack
-.include "words/l-from.asm"
-.include "words/to-l.asm"
-.include "words/lp0.asm"
-.include "words/lp.asm"
-
-.include "words/create.asm"
-.include "words/header.asm"
-.include "words/wlscope.asm"
-.include "words/reveal.asm"
-.include "words/does.asm"
-.include "words/colon.asm"
-.include "words/colon-noname.asm"
-.include "words/semicolon.asm"
-.include "words/right-bracket.asm"
-.include "words/left-bracket.asm"
-.include "words/variable.asm"
-.include "words/constant.asm"
-.include "words/user.asm"
-
-.include "words/recurse.asm"
-.include "words/immediate.asm"
-
-.include "words/bracketchar.asm"
-.include "words/abort-string.asm"
-.include "words/abort.asm"
-.include "words/q-abort.asm"
-
-.include "words/get-stack.asm"
-.include "words/set-stack.asm"
-.include "words/map-stack.asm"
-.include "words/get-current.asm"
-.include "words/get-order.asm"
-.include "words/cfg-order.asm"
-.include "words/compare.asm"
-.include "words/nfa2lfa.asm"
diff --git a/amforth-6.5/avr8/dict/compiler2.inc b/amforth-6.5/avr8/dict/compiler2.inc
deleted file mode 100644
index 5d06a55..0000000
--- a/amforth-6.5/avr8/dict/compiler2.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-; words from this file are optional. They can be
-; included almost independently from each other
-; on a include-per-use basis
-;
-.if DICT_COMPILER2 == 0
-.set DICT_COMPILER2 = 1
-
-.include "words/set-current.asm"
-.include "words/wordlist.asm"
-
-.include "words/forth-wordlist.asm"
-.include "words/set-order.asm"
-.include "words/set-recognizer.asm"
-.include "words/get-recognizer.asm"
-.include "words/code.asm"
-.include "words/end-code.asm"
-.include "words/marker.asm"
-.include "words/postpone.asm"
-.endif
diff --git a/amforth-6.5/avr8/dict/core_2k.inc b/amforth-6.5/avr8/dict/core_2k.inc
deleted file mode 100644
index 5ac1e93..0000000
--- a/amforth-6.5/avr8/dict/core_2k.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-; this file contains nothing
-; \ No newline at end of file
diff --git a/amforth-6.5/avr8/dict/core_4k.inc b/amforth-6.5/avr8/dict/core_4k.inc
deleted file mode 100644
index 6e083d5..0000000
--- a/amforth-6.5/avr8/dict/core_4k.inc
+++ /dev/null
@@ -1,98 +0,0 @@
-; first the assembly words to keep them
-; in a short distance to DO_NEXT
-.include "words/n_to_r.asm"
-.include "words/n_r_from.asm"
-.include "words/d-2star.asm"
-.include "words/d-2slash.asm"
-.include "words/d-plus.asm"
-.include "words/d-minus.asm"
-.include "words/d-invert.asm"
-.include "words/slashmod.asm"
-.include "words/abs.asm"
-.include "words/pick.asm"
-.include "words/cellplus.asm"
-.include "dict/interrupt.inc"
-
-; now the relocatable colon words
-.include "words/prompt-ok.asm"
-.include "words/prompt-ready.asm"
-.include "words/prompt-error.asm"
-
-.include "words/quit.asm"
-.include "words/pause.asm"
-.include "words/cold.asm"
-.include "words/warm.asm"
-
-.include "words/handler.asm"
-.include "words/catch.asm"
-.include "words/throw.asm"
-
-
-.include "words/edefer-fetch.asm"
-.include "words/edefer-store.asm"
-.include "words/rdefer-fetch.asm"
-.include "words/rdefer-store.asm"
-.include "words/udefer-fetch.asm"
-.include "words/udefer-store.asm"
-.include "words/defer-store.asm"
-.include "words/defer-fetch.asm"
-.include "words/do-defer.asm"
-
-.include "words/u-dot.asm"
-.include "words/u-dot-r.asm"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/uslashmod.asm"
-.include "words/negate.asm"
-.include "words/slash.asm"
-.include "words/mod.asm"
-
-.include "words/min.asm"
-.include "words/max.asm"
-.include "words/within.asm"
-
-.include "words/show-wordlist.asm"
-.include "words/words.asm"
-
-.include "words/dot-quote.asm"
-.include "words/squote.asm"
-.include "words/fill.asm"
-
-.include "words/f_cpu.asm"
-.include "words/state.asm"
-.include "words/base.asm"
-
-.include "words/cells.asm"
-
-.include "words/2dup.asm"
-.include "words/2drop.asm"
-.include "words/tuck.asm"
-
-.include "words/to-in.asm"
-.include "words/pad.asm"
-.include "words/emit.asm"
-.include "words/emitq.asm"
-.include "words/key.asm"
-.include "words/keyq.asm"
-
-.include "words/dp.asm"
-.include "words/ehere.asm"
-.include "words/here.asm"
-.include "words/allot.asm"
-
-.include "words/bin.asm"
-.include "words/decimal.asm"
-.include "words/hex.asm"
-.include "words/bl.asm"
-
-.include "words/turnkey.asm"
-.include "words/to-upper.asm"
-.include "words/to-lower.asm"
-
-.include "words/q-stack.asm"
-.include "words/bounds.asm"
-.include "words/cr.asm"
-.include "words/space.asm"
-.include "words/spaces.asm"
-.include "words/s-to-d.asm"
-.include "words/to-body.asm"
diff --git a/amforth-6.5/avr8/dict/core_8k.inc b/amforth-6.5/avr8/dict/core_8k.inc
deleted file mode 100644
index ed5b805..0000000
--- a/amforth-6.5/avr8/dict/core_8k.inc
+++ /dev/null
@@ -1,180 +0,0 @@
-
-.include "words/n_to_r.asm"
-.include "words/n_r_from.asm"
-
-.include "words/d-2star.asm"
-.include "words/d-2slash.asm"
-.include "words/d-plus.asm"
-.include "words/d-minus.asm"
-.include "words/d-invert.asm"
-.include "words/u-dot.asm"
-.include "words/u-dot-r.asm"
-
-.include "words/show-wordlist.asm"
-.include "words/words.asm"
-.include "dict/interrupt.inc"
-
-.include "words/pick.asm"
-.include "words/dot-quote.asm"
-.include "words/squote.asm"
-
-.include "words/fill.asm"
-
-.include "words/environment.asm"
-.include "words/env-wordlists.asm"
-.include "words/env-slashpad.asm"
-.include "words/env-slashhold.asm"
-.include "words/env-forthname.asm"
-.include "words/env-forthversion.asm"
-.include "words/env-cpu.asm"
-.include "words/env-mcuinfo.asm"
-.include "words/env-usersize.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/f_cpu.asm"
-.include "words/state.asm"
-.include "words/base.asm"
-
-.include "words/cells.asm"
-.include "words/cellplus.asm"
-
-.include "words/2dup.asm"
-.include "words/2drop.asm"
-
-.include "words/tuck.asm"
-
-.include "words/to-in.asm"
-.include "words/pad.asm"
-.include "words/emit.asm"
-.include "words/emitq.asm"
-.include "words/key.asm"
-.include "words/keyq.asm"
-
-.include "words/dp.asm"
-.include "words/ehere.asm"
-.include "words/here.asm"
-.include "words/allot.asm"
-
-.include "words/bin.asm"
-.include "words/decimal.asm"
-.include "words/hex.asm"
-.include "words/bl.asm"
-
-.include "words/turnkey.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/slashmod.asm"
-.include "words/uslashmod.asm"
-.include "words/negate.asm"
-.include "words/slash.asm"
-.include "words/mod.asm"
-.include "words/abs.asm"
-.include "words/min.asm"
-.include "words/max.asm"
-.include "words/within.asm"
-
-.include "words/to-upper.asm"
-.include "words/to-lower.asm"
-;;;;;;;;;;;;;;;;;;;;;;
-.include "words/hld.asm"
-.include "words/hold.asm"
-.include "words/less-sharp.asm" ; <#
-.include "words/sharp.asm"
-.include "words/sharp-s.asm"
-.include "words/sharp-greater.asm" ; #>
-.include "words/sign.asm"
-.include "words/d-dot-r.asm"
-.include "words/dot-r.asm"
-.include "words/d-dot.asm"
-.include "words/dot.asm"
-.include "words/ud-dot.asm"
-.include "words/ud-dot-r.asm"
-.include "words/ud-slash-mod.asm"
-.include "words/digit-q.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/do-sliteral.asm"
-.include "words/scomma.asm"
-.include "words/itype.asm"
-.include "words/icount.asm"
-.include "words/cr.asm"
-.include "words/space.asm"
-.include "words/spaces.asm"
-.include "words/type.asm"
-.include "words/tick.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/handler.asm"
-.include "words/catch.asm"
-.include "words/throw.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/cskip.asm"
-.include "words/cscan.asm"
-.include "words/accept.asm"
-.include "words/refill.asm"
-.include "words/char.asm"
-.include "words/number.asm"
-.include "words/q-sign.asm"
-.include "words/set-base.asm"
-.include "words/to-number.asm"
-.include "words/parse.asm"
-.include "words/source.asm"
-.include "words/slash-string.asm"
-.include "words/parse-name.asm"
-.include "words/find-xt.asm"
-
-.include "words/prompt-ok.asm"
-.include "words/prompt-ready.asm"
-.include "words/prompt-error.asm"
-
-.include "words/quit.asm"
-.include "words/pause.asm"
-.include "words/cold.asm"
-.include "words/warm.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/sp0.asm"
-.include "words/rp0.asm"
-.include "words/depth.asm"
-.include "words/interpret.asm"
-.include "words/forth-recognizer.asm"
-.include "words/recognize.asm"
-.include "words/rec-intnum.asm"
-.include "words/rec-find.asm"
-.include "words/dt-null.asm"
-
-.include "words/q-stack.asm"
-.include "words/ver.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/noop.asm"
-.include "words/unused.asm"
-
-.include "words/to.asm"
-.include "words/i-cellplus.asm"
-
-.include "words/edefer-fetch.asm"
-.include "words/edefer-store.asm"
-.include "words/rdefer-fetch.asm"
-.include "words/rdefer-store.asm"
-.include "words/udefer-fetch.asm"
-.include "words/udefer-store.asm"
-.include "words/defer-store.asm"
-.include "words/defer-fetch.asm"
-.include "words/do-defer.asm"
-
-.include "words/search-wordlist.asm"
-.include "words/traverse-wordlist.asm"
-.include "words/name2string.asm"
-.include "words/nfa2cfa.asm"
-.include "words/icompare.asm"
-
-.include "words/star.asm"
-.include "words/j.asm"
-
-.include "words/dabs.asm"
-.include "words/dnegate.asm"
-.include "words/cmove.asm"
-.include "words/2swap.asm"
-
-.include "words/tib.asm"
-
-.include "words/init-ram.asm"
-.include "dict/compiler2.inc"
-.include "words/bounds.asm"
-.include "words/s-to-d.asm"
-.include "words/to-body.asm"
diff --git a/amforth-6.5/avr8/dict/interrupt.inc b/amforth-6.5/avr8/dict/interrupt.inc
deleted file mode 100644
index a22c9b5..0000000
--- a/amforth-6.5/avr8/dict/interrupt.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-
-.if WANT_INTERRUPTS == 1
-
-.if WANT_INTERRUPT_COUNTERS == 1
- .include "words/irqcnt.asm"
-.endif
-
-.include "words/int-on.asm"
-.include "words/int-off.asm"
-.include "words/int-store.asm"
-.include "words/int-fetch.asm"
-.include "words/int-trap.asm"
-
-.include "words/isr-exec.asm"
-.include "words/isr-end.asm"
-.endif
diff --git a/amforth-6.5/avr8/dict/nrww.inc b/amforth-6.5/avr8/dict/nrww.inc
deleted file mode 100644
index b46c307..0000000
--- a/amforth-6.5/avr8/dict/nrww.inc
+++ /dev/null
@@ -1,114 +0,0 @@
-; this part of the dictionay has to fit into the nrww flash
-; section together with the forth inner interpreter
-
-.include "words/exit.asm"
-.include "words/execute.asm"
-.include "words/dobranch.asm"
-.include "words/docondbranch.asm"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/doliteral.asm"
-.include "words/dovariable.asm"
-.include "words/doconstant.asm"
-.include "words/douser.asm"
-.include "words/do-value.asm"
-.include "words/fetch.asm"
-.include "words/store.asm"
-.include "words/cstore.asm"
-.include "words/cfetch.asm"
-.include "words/fetch-u.asm"
-.include "words/store-u.asm"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/dup.asm"
-.include "words/qdup.asm"
-.include "words/swap.asm"
-.include "words/over.asm"
-.include "words/drop.asm"
-.include "words/rot.asm"
-.include "words/nip.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/r_from.asm"
-.include "words/to_r.asm"
-.include "words/r_fetch.asm"
-
-
-.include "words/not-equal.asm"
-.include "words/equalzero.asm"
-.include "words/lesszero.asm"
-.include "words/greaterzero.asm"
-.include "words/d-greaterzero.asm"
-.include "words/d-lesszero.asm"
-
-.include "words/true.asm"
-.include "words/zero.asm"
-.include "words/uless.asm"
-.include "words/u-greater.asm"
-.include "words/less.asm"
-.include "words/greater.asm"
-
-.include "words/log2.asm"
-.include "words/minus.asm"
-.include "words/plus.asm"
-.include "words/mstar.asm"
-.include "words/umslashmod.asm"
-.include "words/umstar.asm"
-
-.include "words/invert.asm"
-.include "words/2slash.asm"
-.include "words/2star.asm"
-.include "words/and.asm"
-.include "words/or.asm"
-.include "words/xor.asm"
-
-.include "words/1plus.asm"
-.include "words/1minus.asm"
-.include "words/q-negate.asm"
-.include "words/lshift.asm"
-.include "words/rshift.asm"
-.include "words/plusstore.asm"
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/rpfetch.asm"
-.include "words/rpstore.asm"
-.include "words/spfetch.asm"
-.include "words/spstore.asm"
-
-.include "words/dodo.asm"
-.include "words/i.asm"
-.include "words/doplusloop.asm"
-.include "words/doloop.asm"
-.include "words/unloop.asm"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-.include "words/cmove_g.asm"
-.include "words/byteswap.asm"
-.include "words/up.asm"
-.include "words/1ms.asm"
-.include "words/2to_r.asm"
-.include "words/2r_from.asm"
-
-.include "words/store-e.asm"
-.include "words/fetch-e.asm"
-.include "words/store-i.asm"
-.if FLASHEND > $10000
- .include "words/store-i_big.asm"
-.else
- .include "words/store-i_nrww.asm"
-.endif
-.include "words/fetch-i.asm"
-
-.if AMFORTH_NRWW_SIZE>8000
-.include "dict/core_8k.inc"
-.elif AMFORTH_NRWW_SIZE>4000
-.include "dict/core_4k.inc"
-.elif AMFORTH_NRWW_SIZE>2000
-.include "dict/core_2k.inc"
-.else
-.error "AMFORTH_NRWW_SIZE too small, cannot continue"
-.endif
-; now colon words
-;;;;;;;;;;;;;;;;;;;;;;;;
-.include "words/2literal.asm"
-.include "words/equal.asm"
-.include "words/num-constants.asm"
diff --git a/amforth-6.5/avr8/dict/rww.inc b/amforth-6.5/avr8/dict/rww.inc
deleted file mode 100644
index a9ab0df..0000000
--- a/amforth-6.5/avr8/dict/rww.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-.include "words/mplus.asm"
-.include "words/ud-star.asm"
-.include "words/umax.asm"
-.include "words/umin.asm"
-.include "words/immediate-q.asm"
-.include "words/name2flags.asm"
-
-.if AMFORTH_NRWW_SIZE > 8000
-.include "dict/appl_8k.inc"
-.elif AMFORTH_NRWW_SIZE > 4000
-.include "dict/appl_4k.inc"
-.elif AMFORTH_NRWW_SIZE > 2000
-.include "dict/appl_2k.inc"
-.else
-.error "AMFORTH_NRWW_SIZE too small. Cannot continue"
-.endif
diff --git a/amforth-6.5/avr8/drivers/1wire.asm b/amforth-6.5/avr8/drivers/1wire.asm
deleted file mode 100644
index ab5c9f4..0000000
--- a/amforth-6.5/avr8/drivers/1wire.asm
+++ /dev/null
@@ -1,165 +0,0 @@
-;; AUTHORs
-; B. J. Rodriguez (MSP 430)
-; Matthias Trute (AVR Atmega)
-; COPYRIGHT
-; (c) 2012 Bradford J. Rodriguez for the 430 code and API
-
-; adapted 430 assembly code to AVR
-; wishlist:
-; use a configurable pin at runtime, compatible with bitnames.frt
-; no external pull up, no external power supply for devices
-; ???
-;
-;.EQU OW_BIT=4
-;.equ OW_PORT=PORTE
-.set OW_DDR=(OW_PORT-1)
-.set OW_PIN=(OW_DDR-1)
-
-;****f* 1W.RESET
-; NAME
-; 1W.RESET
-; SYNOPSIS
-; 1W.RESET ( -- f ) Initialize 1-wire devices; return true if present
-; DESCRIPTION
-; This configures the port pin used by the 1-wire interface, and then
-; sends an "initialize" sequence to the 1-wire devices. If any device
-; is present, it will be detected.
-;
-; Timing, per DS18B20 data sheet:
-; a) Output "0" (drive output low) for >480 usec.
-; b) Output "1" (let output float).
-; c) After 15 to 60 usec, device will drive pin low for 60 to 240 usec.
-; So, wait 75 usec and sample input.
-; d) Leave output high (floating) for at least 480 usec.
-;******
-; ( -- f )
-; Hardware
-; Initialize 1-wire devices; return true if present
-VE_OW_RESET:
- .dw $ff08
- .db "1w.reset"
- .dw VE_HEAD
- .set VE_HEAD = VE_OW_RESET
-XT_OW_RESET:
- .dw PFA_OW_RESET
-PFA_OW_RESET:
- savetos
- ; setup to output
- sbi OW_DDR, OW_BIT
- ; Pull output low
- cbi OW_PORT, OW_BIT
- ; Delay >480 usec
- DELAY 480
- ; Critical timing period, disable interrupts.
- in temp1, SREG
- cli
- ; Pull output high
- sbi OW_PORT, OW_BIT
- ; make pin input, sends "1"
- cbi OW_DDR, OW_BIT
- DELAY 64 ; delayB
- ; Sample input pin, set TOS if input is zero
- in tosl, OW_PIN
- sbrs tosl, OW_BIT
- ser tosh
- ; End critical timing period, enable interrupts
- out SREG, temp1
- ; release bus
- cbi OW_DDR, OW_BIT
- cbi OW_PORT, OW_BIT
-
- ; Delay rest of 480 usec
- DELAY 416
- ; we now have the result flag in TOS
- mov tosl, tosh
- jmp_ DO_NEXT
-
-;****f* 1W.SLOT
-; NAME
-; 1W.SLOT
-; SYNOPSIS
-; 1W.SLOT ( c -- c' ) Write and read one bit to/from 1-wire.
-; DESCRIPTION
-; The "touch byte" function is described in Dallas App Note 74.
-; It outputs a byte to the 1-wire pin, LSB first, and reads back
-; the state of the 1-wire pin after a suitable delay.
-; To read a byte, output $FF and read the reply data.
-; To write a byte, output that byte and discard the reply.
-;
-; This function performs one bit of the "touch" operation --
-; one read/write "slot" in Dallas jargon. Perform this eight
-; times in a row to get the "touch byte" function.
-;
-; PARAMETERS
-; The input parameter is xxxxxxxxbbbbbbbo where
-; 'xxxxxxxx' are don't cares,
-; 'bbbbbbb' are bits to be shifted down, and
-; 'o' is the bit to be output in the slot. This must be 1
-; to create a read slot.
-;
-; The returned value is xxxxxxxxibbbbbbb where
-; 'xxxxxxxx' are not known (the input shifted down 1 position),
-; 'i' is the bit read during the slot. This has no meaning
-; if it was a write slot.
-; 'bbbbbbb' are the 7 input bits, shifted down one position.
-;
-; This peculiar parameter usage allows OWTOUCH to be written as
-; OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT OWSLOT
-;
-; NOTES
-; Interrupts are disabled during each bit.
-
-; Timing, per DS18B20 data sheet:
-; a) Output "0" for start period. (> 1 us, < 15 us, typ. 6 us*)
-; b) Output data bit (0 or 1), open drain
-; c) After MS from start of cycle, sample input (15 to 60 us, typ. 25 us*)
-; d) After write-0 period from start of cycle, output "1" (>60 us)
-; e) After recovery period, loop or return. (> 1 us)
-; For writes, DS18B20 samples input 15 to 60 usec from start of cycle.
-; * "Typical" values are per App Note 132 for a 300m cable length.
-
-; --------- -------------------------------
-; \ / /
-; -------------------------------
-; a b c d e
-; | 6us | 19us | 35us | 2us |
-;******
-; ( c -- c' )
-; Hardware
-; Write and read one bit to/from 1-wire.
-VE_OW_SLOT:
- .dw $ff07
- .db "1w.slot",0
- .dw VE_HEAD
- .set VE_HEAD = VE_OW_SLOT
-XT_OW_SLOT:
- .dw PFA_OW_SLOT
-PFA_OW_SLOT:
- ; pull low
- cbi OW_PORT, OW_BIT
- sbi OW_DDR, OW_BIT
- ; disable interrupts
- in temp1, SREG
- cli
- DELAY 6 ; DELAY A
- ; check bit
- clc
- ror tosl
- brcc PFA_OW_SLOT0 ; a 0 keeps the bus low
- ; release bus, a 1 is written
- sbi OW_PORT, OW_BIT
- cbi OW_DDR, OW_BIT
-PFA_OW_SLOT0:
- ; sample the input (no action required if zero)
- DELAY 9 ; wait DELAY E to sample
- in temp0, OW_PIN
- sbrc temp0, OW_BIT
- ori tosl, $80
-
- DELAY 51 ; DELAY B
- sbi OW_PORT, OW_BIT ; release bus
- cbi OW_DDR, OW_BIT
- delay 2
- ; re-enable interrupts
- out SREG, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/drivers/generic-isr.asm b/amforth-6.5/avr8/drivers/generic-isr.asm
deleted file mode 100644
index e0aeaed..0000000
--- a/amforth-6.5/avr8/drivers/generic-isr.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-; ISR routines
-.eseg
-intvec: .byte INTVECTORS * CELLSIZE
-.dseg
-intcnt: .byte INTVECTORS
-.cseg
-
-; interrupt routine gets called (again) by rcall! This gives the
-; address of the int-vector on the stack.
-isr:
- st -Y, r0
- in r0, SREG
- st -Y, r0
-.if (pclen==3)
- pop r0 ; some 128+K Flash devices use 3 cells for call/ret
-.endif
- pop r0
- pop r0 ; = intnum * intvectorsize + 1 (address following the rcall)
- dec r0
-.if intvecsize == 1 ;
- lsl r0
-.endif
- mov isrflag, r0
- push zh
- push zl
- ldi zl, low(intcnt)
- ldi zh, high(intcnt)
- lsr r0 ; we use byte addresses in the counter array, not words
- add zl, r0
- adc zh, zeroh
- ld r0, Z
- inc r0
- st Z, r0
- pop zl
- pop zh
-
- ld r0, Y+
- out SREG, r0
- ld r0, Y+
- ret ; returns the interrupt, the rcall stack frame is removed!
- ; no reti here, see words/isr-end.asm
diff --git a/amforth-6.5/avr8/drivers/usart-rx-buffer.asm b/amforth-6.5/avr8/drivers/usart-rx-buffer.asm
deleted file mode 100644
index b6a64b8..0000000
--- a/amforth-6.5/avr8/drivers/usart-rx-buffer.asm
+++ /dev/null
@@ -1,132 +0,0 @@
-;;; usart driver, receiving
-
-; sizes have to be powers of 2!
-.equ usart_rx_size = $10
-.equ usart_rx_mask = usart_rx_size - 1
-.dseg
- usart_rx_data: .byte usart_rx_size
- usart_rx_in: .byte 1
- usart_rx_out: .byte 1
-.cseg
-
-VE_TO_RXBUF:
- .dw $ff07
- .db ">rx-buf",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_RXBUF
-XT_TO_RXBUF:
- .dw PFA_rx_tobuf
-PFA_rx_tobuf:
- mov temp0, tosl
- lds temp1, usart_rx_in
- ldi zl, low(usart_rx_data)
- ldi zh, high(usart_rx_data)
- add zl, temp1
- adc zh, zeroh
- st Z, temp0
- inc temp1
- andi temp1,usart_rx_mask
- sts usart_rx_in, temp1
- loadtos
- jmp_ DO_NEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; setup with
-; ' isr-rx URXCaddr int!
-VE_ISR_RX:
- .dw $ff06
- .db "isr-rx"
- .dw VE_HEAD
- .set VE_HEAD = VE_ISR_RX
-XT_ISR_RX:
- .dw DO_COLON
-usart_rx_isr:
- .dw XT_DOLITERAL
- .dw usart_data
- .dw XT_CFETCH
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw 3
- .dw XT_EQUAL
- .dw XT_DOCONDBRANCH
- .dw usart_rx_isr1
- .dw XT_COLD
-usart_rx_isr1:
- .dw XT_TO_RXBUF
- .dw XT_EXIT
-
-; ( -- ) Hardware Access
-; R( --)
-; initialize usart
-;VE_USART_INIT_RXBUFFER:
-; .dw $ff0x
-; .db "+usart-buffer"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_USART_INIT_RXBUFFER
-XT_USART_INIT_RX_BUFFER:
- .dw DO_COLON
-PFA_USART_INIT_RX_BUFFER: ; ( -- )
- .dw XT_DOLITERAL, XT_ISR_RX
- .dw XT_DOLITERAL, URXCaddr
- .dw XT_INTSTORE
-
- .dw XT_DOLITERAL
- .dw usart_rx_data
- .dw XT_DOLITERAL
- .dw usart_rx_size + 6
- .dw XT_ZERO
- .dw XT_FILL
- .dw XT_EXIT
-
-; ( -- c)
-; MCU
-; get 1 character from input queue, wait if needed using interrupt driver
-VE_RX_BUFFER:
- .dw $ff06
- .db "rx-buf"
- .dw VE_HEAD
- .set VE_HEAD = VE_RX_BUFFER
-XT_RX_BUFFER:
- .dw DO_COLON
-PFA_RX_BUFFER:
- .dw XT_RXQ_BUFFER
- .dw XT_DOCONDBRANCH
- .dw PFA_RX_BUFFER
- .dw XT_DOLITERAL
- .dw usart_rx_out
- .dw XT_CFETCH
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw usart_rx_data
- .dw XT_PLUS
- .dw XT_CFETCH
- .dw XT_SWAP
- .dw XT_1PLUS
- .dw XT_DOLITERAL
- .dw usart_rx_mask
- .dw XT_AND
- .dw XT_DOLITERAL
- .dw usart_rx_out
- .dw XT_CSTORE
- .dw XT_EXIT
-
-; ( -- f)
-; MCU
-; check if unread characters are in the input queue
-VE_RXQ_BUFFER:
- .dw $ff07
- .db "rx?-buf",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_BUFFER
-XT_RXQ_BUFFER:
- .dw DO_COLON
-PFA_RXQ_BUFFER:
- .dw XT_PAUSE
- .dw XT_DOLITERAL
- .dw usart_rx_out
- .dw XT_CFETCH
- .dw XT_DOLITERAL
- .dw usart_rx_in
- .dw XT_CFETCH
- .dw XT_NOTEQUAL
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/drivers/usart.asm b/amforth-6.5/avr8/drivers/usart.asm
deleted file mode 100644
index 7274789..0000000
--- a/amforth-6.5/avr8/drivers/usart.asm
+++ /dev/null
@@ -1,30 +0,0 @@
-
-.equ BAUDRATE_LOW = UBRRL+$20
-.equ BAUDRATE_HIGH = UBRRH+$20
-.equ USART_C = UCSRC+$20
-.equ USART_B = UCSRB+$20
-.equ USART_A = UCSRA+$20
-.equ USART_DATA = UDR+$20
-.equ bm_USARTC_en = 1 << 7
-
-; some generic constants
-.equ bm_USART_RXRD = 1 << RXC
-.equ bm_USART_TXRD = 1 << UDRE
-.equ bm_ENABLE_TX = 1 << TXEN
-.equ bm_ENABLE_RX = 1 << RXEN
-.equ bm_ENABLE_INT_RX = 1<<RXCIE
-.equ bm_ENABLE_INT_TX = 1<<UDRE
-
-.equ bm_ASYNC = 0 << 6
-.equ bm_SYNC = 1 << 6
-.equ bm_NO_PARITY = 0 << 4
-.equ bm_EVEN_PARITY = 2 << 4
-.equ bm_ODD_PARITY = 3 << 4
-.equ bm_1STOPBIT = 0 << 3
-.equ bm_2STOPBIT = 1 << 3
-.equ bm_5BIT = 0 << 1
-.equ bm_6BIT = 1 << 1
-.equ bm_7BIT = 2 << 1
-.equ bm_8BIT = 3 << 1
-
-.include "drivers/usart_common.asm"
diff --git a/amforth-6.5/avr8/drivers/usart_0.asm b/amforth-6.5/avr8/drivers/usart_0.asm
deleted file mode 100644
index 107c462..0000000
--- a/amforth-6.5/avr8/drivers/usart_0.asm
+++ /dev/null
@@ -1,32 +0,0 @@
- .equ BAUDRATE_LOW = UBRR0L
- .equ BAUDRATE_HIGH = UBRR0H
- .equ USART_C = UCSR0C
- .equ USART_B = UCSR0B
- .equ USART_A = UCSR0A
- .equ USART_DATA = UDR0
- .ifndef URXCaddr
- .equ URXCaddr = URXC0addr
- .equ UDREaddr = UDRE0addr
- .endif
-
-.equ bm_USART_RXRD = 1 << RXC0
-.equ bm_USART_TXRD = 1 << UDRE0
-.equ bm_ENABLE_TX = 1 << TXEN0
-.equ bm_ENABLE_RX = 1 << RXEN0
-.equ bm_ENABLE_INT_RX = 1<<RXCIE0
-.equ bm_ENABLE_INT_TX = 1<<UDRIE0
-
-.equ bm_USARTC_en = 0
-.equ bm_ASYNC = 0 << 6
-.equ bm_SYNC = 1 << 6
-.equ bm_NO_PARITY = 0 << 4
-.equ bm_EVEN_PARITY = 2 << 4
-.equ bm_ODD_PARITY = 3 << 4
-.equ bm_1STOPBIT = 0 << 3
-.equ bm_2STOPBIT = 1 << 3
-.equ bm_5BIT = 0 << 1
-.equ bm_6BIT = 1 << 1
-.equ bm_7BIT = 2 << 1
-.equ bm_8BIT = 3 << 1
-
-.include "drivers/usart_common.asm"
diff --git a/amforth-6.5/avr8/drivers/usart_1.asm b/amforth-6.5/avr8/drivers/usart_1.asm
deleted file mode 100644
index 2ee44ae..0000000
--- a/amforth-6.5/avr8/drivers/usart_1.asm
+++ /dev/null
@@ -1,31 +0,0 @@
- .equ BAUDRATE_LOW = UBRR1L
- .equ BAUDRATE_HIGH = UBRR1H
- .equ USART_C = UCSR1C
- .equ USART_B = UCSR1B
- .equ USART_A = UCSR1A
- .equ USART_DATA = UDR1
-
-.equ URXCaddr = URXC1addr
-.equ UDREaddr = UDRE1addr
-
-.equ bm_USART_RXRD = 1 << RXC1
-.equ bm_USART_TXRD = 1 << UDRE1
-.equ bm_ENABLE_TX = 1 << TXEN1
-.equ bm_ENABLE_RX = 1 << RXEN1
-.equ bm_ENABLE_INT_RX = 1<<RXCIE1
-.equ bm_ENABLE_INT_TX = 1<<UDRIE1
-
-.equ bm_USARTC_en = 0
-.equ bm_ASYNC = 0 << 6
-.equ bm_SYNC = 1 << 6
-.equ bm_NO_PARITY = 0 << 4
-.equ bm_EVEN_PARITY = 2 << 4
-.equ bm_ODD_PARITY = 3 << 4
-.equ bm_1STOPBIT = 0 << 3
-.equ bm_2STOPBIT = 1 << 3
-.equ bm_5BIT = 0 << 1
-.equ bm_6BIT = 1 << 1
-.equ bm_7BIT = 2 << 1
-.equ bm_8BIT = 3 << 1
-
-.include "drivers/usart_common.asm"
diff --git a/amforth-6.5/avr8/drivers/usart_2.asm b/amforth-6.5/avr8/drivers/usart_2.asm
deleted file mode 100644
index 71fefe2..0000000
--- a/amforth-6.5/avr8/drivers/usart_2.asm
+++ /dev/null
@@ -1,34 +0,0 @@
- .equ BAUDRATE_LOW = UBRR2L
- .equ BAUDRATE_HIGH = UBRR2H
- .equ USART_C = UCSR2C
- .equ USART_B = UCSR2B
- .equ USART_A = UCSR2A
- .equ USART_DATA = UDR2
-
- .equ URXCaddr = URXC2addr
- .equ UDREaddr = UDRE2addr
-
-.equ bm_USART_RXRD = 1 << RXC2
-.equ bm_USART_TXRD = 1 << UDRE2
-.equ bm_ENABLE_TX = 1 << TXEN2
-.equ bm_ENABLE_RX = 1 << RXEN2
-.equ bm_ENABLE_INT_RX = 1<<RXCIE2
-.equ bm_ENABLE_INT_TX = 1<<UDRIE2
-
-.equ bm_USART_RXRD = 1 << RXC2
-.equ bm_USART_TXRD = 1 << UDRE2
-
-.equ bm_USARTC_en = 0
-.equ bm_ASYNC = 0 << 6
-.equ bm_SYNC = 1 << 6
-.equ bm_NO_PARITY = 0 << 4
-.equ bm_EVEN_PARITY = 2 << 4
-.equ bm_ODD_PARITY = 3 << 4
-.equ bm_1STOPBIT = 0 << 3
-.equ bm_2STOPBIT = 1 << 3
-.equ bm_5BIT = 0 << 1
-.equ bm_6BIT = 1 << 1
-.equ bm_7BIT = 2 << 1
-.equ bm_8BIT = 3 << 1
-
-.include "drivers/usart_common.asm"
diff --git a/amforth-6.5/avr8/drivers/usart_3.asm b/amforth-6.5/avr8/drivers/usart_3.asm
deleted file mode 100644
index 1745b31..0000000
--- a/amforth-6.5/avr8/drivers/usart_3.asm
+++ /dev/null
@@ -1,31 +0,0 @@
- .equ BAUDRATE_LOW = UBRR3L
- .equ BAUDRATE_HIGH = UBRR3H
- .equ USART_C = UCSR3C
- .equ USART_B = UCSR3B
- .equ USART_A = UCSR3A
- .equ USART_DATA = UDR3
-
-.equ URXCaddr = URXC3addr
-.equ UDREaddr = UDRE3addr
-
-.equ bm_USART_RXRD = 1 << RXC3
-.equ bm_USART_TXRD = 1 << UDRE3
-.equ bm_ENABLE_TX = 1 << TXEN3
-.equ bm_ENABLE_RX = 1 << RXEN3
-.equ bm_ENABLE_INT_RX = 1<<RXCIE3
-.equ bm_ENABLE_INT_TX = 1<<UDRIE3
-
-.equ bm_USARTC_en = 0
-.equ bm_ASYNC = 0 << 6
-.equ bm_SYNC = 1 << 6
-.equ bm_NO_PARITY = 0 << 4
-.equ bm_EVEN_PARITY = 2 << 4
-.equ bm_ODD_PARITY = 3 << 4
-.equ bm_1STOPBIT = 0 << 3
-.equ bm_2STOPBIT = 1 << 3
-.equ bm_5BIT = 0 << 1
-.equ bm_6BIT = 1 << 1
-.equ bm_7BIT = 2 << 1
-.equ bm_8BIT = 3 << 1
-
-.include "drivers/usart_common.asm"
diff --git a/amforth-6.5/avr8/drivers/usart_common.asm b/amforth-6.5/avr8/drivers/usart_common.asm
deleted file mode 100644
index e6238ec..0000000
--- a/amforth-6.5/avr8/drivers/usart_common.asm
+++ /dev/null
@@ -1,30 +0,0 @@
-
-.set USART_C_VALUE = bm_ASYNC | bm_NO_PARITY | bm_1STOPBIT | bm_8BIT
-.if WANT_INTERRUPTS == 0
- .if WANT_ISR_RX == 1
- .error "*** Config error. set WANT_ISR_RX to 0 too if you disable interrupts (WANT_INTERRUPTS is set to 0)"
- .endif
-.endif
-
-.if WANT_ISR_RX == 1
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX | bm_ENABLE_INT_RX
- .include "drivers/usart-rx-buffer.asm"
-; .include "drivers/timer-usart-isr.asm"
- .set XT_RX = XT_RX_BUFFER
- .set XT_RXQ = XT_RXQ_BUFFER
- .set XT_USART_INIT_RX = XT_USART_INIT_RX_BUFFER
-.else
- .set USART_B_VALUE = bm_ENABLE_TX | bm_ENABLE_RX
- .include "words/usart-rx-poll.asm"
- .set XT_RX = XT_RX_POLL
- .set XT_RXQ = XT_RXQ_POLL
- .set XT_USART_INIT_RX = 0
-.endif
-
-.include "words/usart-tx-poll.asm"
-.set XT_TX = XT_TX_POLL
-.set XT_TXQ = XT_TXQ_POLL
-.set XT_USART_INIT_TX = 0
-
-.include "words/ubrr.asm"
-.include "words/usart.asm"
diff --git a/amforth-6.5/avr8/lib/2evalue.frt b/amforth-6.5/avr8/lib/2evalue.frt
deleted file mode 100644
index 6a1d3aa..0000000
--- a/amforth-6.5/avr8/lib/2evalue.frt
+++ /dev/null
@@ -1,30 +0,0 @@
-\ use 2 cells of EEPROM
-\ Author: Erich Wälde
-\ Date: oct 2015
-
-\ #require quotations.frt
-\ #require eallot.frt
-
-: 2@e ( eaddr -- n2 n1 )
- dup \ -- addr addr
- cell+ \ -- addr addr+2
- @e \ -- addr n2
- swap \ -- n2 addr
- @e \ -- n2 n1
-;
-: 2!e ( n1 n2 eaddr -- )
- rot \ -- n2 eaddr n1
- over \ -- n2 eaddr n1 eaddr
- cell+ \ -- n2 eaddr n1 eaddr+2
- !e \ -- n2 eaddr
- !e \ --
-;
-
-: 2Evalue ( d -- )
- (value)
- ehere ,
- [: @i 2@e ;] ,
- [: @i 2!e ;] ,
- ehere 2!e 2 cells eallot
-;
-
diff --git a/amforth-6.5/avr8/lib/assembler-test.frt b/amforth-6.5/avr8/lib/assembler-test.frt
deleted file mode 100644
index b769f3d..0000000
--- a/amforth-6.5/avr8/lib/assembler-test.frt
+++ /dev/null
@@ -1,58 +0,0 @@
-\ ----- Test AvrAsm -----
-
-only forth also assembler
-
-: loadtos, 24 Y+ ld, 25 Y+ ld, ; \ define macro
-: savetos, -Y 25 st, -Y 24 st, ; \ from macros.asm
-
-code dup_ savetos, end-code \ insert asm code
-code drop_ loadtos, end-code
-
-code ++_ \ ( x1 x2 x3 -- x4 )
- R14 2 ldi, \ + +
- label>
- R16 Y+ ld,
- R17 Y+ ld,
- R24 R16 add,
- R25 R17 adc,
- R14 1 subi,
- <radr brne,
-end-code
-
-previous
-
-\ code demojmp \ demo jump + dup
-\ adr> 0 jmp, \ -+
-\ label> \ | +>-+
-\ clc, \ | | |
-\ adr> rjmp, \ | | +-+
-\ nop, \ | | |
-\ <labelr \ | | +<+
-\ adr> brcc, \ | | +-+
-\ nop, \ | | |
-\ rot <labell \ +> | |
-\ swap <radr rjmp, \ '-+ |
-\ <labelb \ <-+
-\ savetos,
-\ end-code
-
-\ code demojmp \ version with vector
-\ adr> 0 jmp, 0 >lbl \ addr->lbl[0]
-\ label> 1 >lbl
-\ clc,
-\ adr> rjmp, 2 >lbl
-\ nop,
-\ 2 <lbl <labelr
-\ adr> brcc, 3 >lbl
-\ nop,
-\ 0 <lbl <labell \ lbl[0]->tos
-\ 1 <lbl <radr rjmp,
-\ 3 <lbl <labelb
-\ savetos,
-\ end-code
-
-
-2 3 4 ++_ . \ 9
-5 6 drop_ dup_ . . \ 5 5
-
-\ end of file
diff --git a/amforth-6.5/avr8/lib/assembler.frt b/amforth-6.5/avr8/lib/assembler.frt
deleted file mode 100644
index d8ed6b5..0000000
--- a/amforth-6.5/avr8/lib/assembler.frt
+++ /dev/null
@@ -1,325 +0,0 @@
-\ AvrAsm - assembler Atmega chips, Lubos Pekny, www.forth.cz
-\ Library for amforth 3.0 mFC 1.0
-
-\ V.1.1v, 29.01.2009, add vocabulary only
-
-\ V.1.1, 15.05.2008, tested on atmega32, amforth 2.7
-\ - change reg tosl,tosh in Test AvrAsm (loadtos, savetos)
-\ - change <label to <labelr
-\ - vector of labels, 20 bytes in RAM, example
-
-\ V.1.0, 07.02.2008, tested on atmega168, amforth 2.6
-\ Size 3554B (opcode: 2980B, labels: 158B, constants Rx: 416B)
-
-hex
-
-vocabulary assembler
-only forth also assembler definitions \ vocabulary
-
- \ Store src to dest thru mask, FF00 0551 0333 mask! u. FD11
-: mask! ( dest1 src mask -- dest2 )
- rot over invert and rot rot and or ; \ dest1&!mask src&mask or
-
-
- \ Operands Rd,Rr
-: Rd,Rr, ( Rd Rr opcode mask -- xxxz.xxrd.dddd.rrrr )
- >r >r \ -- Rd Rr | -- mask opcode
- 1F and dup 5 lshift or 20F and \ -- Rd r00000rrrr
- swap 4 lshift 1F0 and \ -- rr 0ddddd0000
- or r> r> mask! \ -- ddrr opcode mask mask!
- dup FC07 and 9000 = if EFFF and then , ; \ if Z or Y then z=0
-
-
- \ Operand Rd
-: Rd, ( Rd opcode mask -- xxxx.xxxd.dddd.xxxx )
- >r >r \ -- Rd | -- mask opcode
- 4 lshift 1F0 and \ -- 0ddddd0000
- r> r> mask! , ; \ dd opcode mask mask! to flash
-
-
- \ Operands Rd,constant 8bit
-: Rd,k, ( Rd k8 opcode mask -- xxxx.kkkk.dddd.kkkk )
- >r >r \ -- Rd k8 | -- mask opcode
- FF and dup 4 lshift or F0F and \ -- Rd kkkk0000kkkk
- swap 4 lshift F0 and \ -- kk dddd0000
- or r> r> mask! , ; \ kkdd opcode mask mask! to flash
-
-
- \ Operands Rd,Rr,constant 6bit
-: Rd,Rr+q, ( Rd Rr k6 opcode mask -- xxkx.kkxd.dddd.rkkk )
- >r >r \ -- Rd Rr k6 | -- mask opcode
- 3F and dup 7 lshift \ -- Rd Rr k6 xkkkkkkxxxxxxx
- dup 1000 and 1 lshift or or 2C07 and \ -- Rd Rr kxkkxxxxxxxkkk
- rot 4 lshift 1F0 and \ -- Rr kk ddddd0000
- or swap 8 and \ -- kkdd rxxx
- or r> r> mask! , ; \ kkddrr opcode mask mask! to flash
-
-
- \ Operands Rw pair,constant 6bit
-: Rw,k, ( Rw k6 opcode mask -- xxxx.xxxx.kkww.kkkk )
- >r >r \ -- Rw k6 | -- mask opcode
- 3F and dup 2 lshift C0 and \ -- Rw k6 kk000000
- swap F and or \ -- Rw kk00kkkk
- swap 4 lshift 30 and \ -- kk ww0000
- or r> r> mask! , ; \ kkww opcode mask mask! to flash
-
-
- \ Operands P-port,bit
-: P,b, ( P b opcode mask -- xxxx.xxxx.PPPP.Pbbb )
- >r >r \ -- P b | -- mask opcode
- 7 and swap 3 lshift \ -- 0bbb PPPPP000
- or r> r> mask! , ; \ PPbb opcode mask mask! to flash
-
-
- \ Operands Rd,P-port
-: Rd,P, ( Rd P opcode mask -- xxxx.xPPd.dddd.PPPP )
- >r >r \ -- Rd P | -- mask opcode
- 3F and dup 5 lshift or 60F and \ -- Rd PP00000PPPP
- swap 4 lshift 1F0 and \ -- PP 00ddddd0000
- or r> r> mask! , ; \ ddPP opcode mask mask! to flash
-
-
- \ Operand k16 k6
-: k22, ( k16 k6 opcode mask -- k16 xxxx.xxxk.kkkk.xxxk )
- >r >r \ -- k16 k6 | -- mask opcode
- dup 1 and swap 3 lshift \ -- 000k kkkkkk000
- or r> r> mask! , , ; \ k16 kk opcode mask mask! to flash
-
-
-00 constant Z
-01 constant Z+
-02 constant -Z
-08 constant Y
-09 constant Y+
-0A constant -Y
-0C constant X
-0D constant X+
-0E constant -X
-
-
-: movw, 1 rshift swap \ R0:1,R2:3,R4:5,..R30:31
- 1 rshift swap \ 0 2 movw, R0:1<--R2:3
- 0100 FF00 Rd,Rr, ; ( Rd Rr -- )
-: mul, 9C00 FC00 Rd,Rr, ; \ 2 3 mul,
-: muls, 0200 FF00 Rd,Rr, ;
-: mulsu, 0300 FF88 Rd,Rr, ;
-: fmul, 0308 FF88 Rd,Rr, ;
-: fmuls, 0380 FF88 Rd,Rr, ;
-: fmulsu, 0388 FF88 Rd,Rr, ;
-: cpc, 0400 FC00 Rd,Rr, ;
-: sbc, 0800 FC00 Rd,Rr, ;
-: add, 0C00 FC00 Rd,Rr, ;
-: cpse, 1000 FC00 Rd,Rr, ;
-: cp, 1400 FC00 Rd,Rr, ;
-: sub, 1800 FC00 Rd,Rr, ;
-: adc, 1C00 FC00 Rd,Rr, ;
-: and, 2000 FC00 Rd,Rr, ;
-: eor, 2400 FC00 Rd,Rr, ;
-: or, 2800 FC00 Rd,Rr, ;
-: mov, 2C00 FC00 Rd,Rr, ; \ 2 3 mov, R2<--R3
-
-: cpi, 3000 F000 Rd,k, ; ( Rd k8 -- )
-: sbci, 4000 F000 Rd,k, ;
-: subi, 5000 F000 Rd,k, ;
-: ori, 6000 F000 Rd,k, ;
-: sbr, ori, ;
-: andi, 7000 F000 Rd,k, ;
-: cbr, invert andi, ;
-: ldi, E000 F000 Rd,k, ; \ 2 FF ldi, R2<--#FF
-
-: ldd, 8000 D200 Rd,Rr+q, ; ( Rd Rr q -- ) \ Rr={Z+,Y+}, 2 Y+ 3F ldd,
-: std, rot rot
- 8200 D200 Rd,Rr+q, ; ( Rd q Rr -- ) \ Rd={Z+,Y+}, Y+ 3F 2 std,
-
-: ld, 9000 FE00 Rd,Rr, ; ( Rd Rr -- ) \ Rr={Z+,-Z,Y+,-Y,X+,-X,X,Y,Z}
-: lds, swap
- 9000 FE0F Rd, , ; ( Rd k16 -- )
-: lpm_, 9004 FE0E Rd,Rr, ; ( Rd Rr -- ) \ Rr={Z,Z+}, 2 Z+ lpm_
-: elpm_, 9006 FE0E Rd,Rr, ; ( Rd Rr -- ) \ Rr={Z,Z+}
-: st, swap
- 9200 FE00 Rd,Rr, ; ( Rd Rr -- ) \ Rd={Z+,-Z,Y+,-Y,X+,-X,X,Y,Z}
-: sts, 9200 FE0F Rd, , ; ( k16 Rd -- ) \ FFFF 2 sts, adr(FFFF)<--R2
-
-: lsl, dup add, ; ( Rd -- )
-: rol, dup adc, ;
-: tst, dup and, ;
-: clr, dup eor, ;
-: ser, FF ldi, ;
-
-: pop, 900F FE0F Rd, ; ( Rd -- ) \ 2 pop,
-: push, 920F FE0F Rd, ;
-: com, 9400 FE0F Rd, ;
-: neg, 9401 FE0F Rd, ;
-: swap, 9402 FE0F Rd, ;
-: inc, 9403 FE0F Rd, ;
-: asr, 9405 FE0F Rd, ;
-: lsr, 9406 FE0F Rd, ;
-: ror, 9407 FE0F Rd, ;
-: bset, 9408 FF8F Rd, ;
-: bclr, 9488 FF8F Rd, ;
-: dec, 940A FE0F Rd, ;
-
-: nop, 0000 , ; ( -- )
-: ret, 9508 , ;
-: reti, 9518 , ;
-: sleep, 9588 , ;
-: break, 9598 , ;
-: wdr, 95A8 , ;
-: lpm, 95C8 , ;
-: elpm, 95D8 , ;
-: spm, 95E8 , ;
-: espm, 95F8 , ;
-: ijmp, 9409 , ;
-: eijmp, 9419 , ;
-: icall, 9509 , ;
-: eicall, 9519 , ;
-
-: clc, 9488 , ;
-: clh, 94D8 , ;
-: cli, 94F8 , ;
-: cln, 94A8 , ;
-: cls, 94C8 , ;
-: clt, 94E8 , ;
-: clv, 94B8 , ;
-: clz, 9498 , ;
-: sec, 9408 , ;
-: seh, 9458 , ;
-: sei, 9478 , ;
-: sen, 9428 , ;
-: ses, 9448 , ;
-: set, 9468 , ;
-: sev, 9438 , ;
-: sez, 9418 , ;
-
-: adiw, 9600 FF00 Rw,k, ; ( Rw k6 -- ) \ 3 3F adiw, ZLH=ZLH+#3F
-: sbiw, 9700 FF00 Rw,k, ;
-: cbi, 9800 FF00 P,b, ; ( P b -- )
-: sbic, 9900 FF00 P,b, ;
-: sbi, 9A00 FF00 P,b, ;
-: sbis, 9B00 FF00 P,b, ;
-
-: in, B000 F800 Rd,P, ; ( Rd P -- )
-: out, swap
- B800 F800 Rd,P, ; ( P Rr -- )
-
-: bld, F800 FE08 Rd,Rr, ; ( Rd b -- )
-: bst, FA00 FE08 Rd,Rr, ;
-: sbrc, FC00 FE08 Rd,Rr, ;
-: sbrs, FE00 FE08 Rd,Rr, ;
-
-: jmp, 940C FE0E k22, ; ( k16 k6 -- ) \ k6=0 for 16b addr
-: call, 940E FE0E k22, ;
-: rjmp, C000 F000 mask! , ; ( k12 -- )
-: rcall, D000 F000 mask! , ;
-
-: brbc, F400 FC00 P,b, ; ( k7 b -- )
-: brbs, F000 FC00 P,b, ;
-: brcc, 0 brbc, ; ( k7 )
-: brcs, 0 brbs, ;
-: brsh, 0 brbc, ;
-: brlo, 0 brbs, ;
-: brne, 1 brbc, ;
-: breq, 1 brbs, ;
-: brpl, 2 brbc, ;
-: brmi, 2 brbs, ;
-: brvc, 3 brbc, ;
-: brvs, 3 brbs, ;
-: brge, 4 brbc, ;
-: brlt, 4 brbs, ;
-: brhc, 5 brbc, ;
-: brhs, 5 brbs, ;
-: brtc, 6 brbc, ;
-: brts, 6 brbs, ;
-: brid, 7 brbc, ;
-: brie, 7 brbs, ;
-
-
- \ Relative addr, for jump back, <radr brne
-: <radr ( adr -- k )
- dp 1+ - ;
-
-
- \ Label for jump back, label> ......... <radr brne,
-: label> ( -- adr ) \ label> ......... <radr rjmp,
- dp ; \ label> ......... 0 jmp,
-
-
- \ Addr, for jump forward, adr> brne, adr> 0 jmp,
-: adr> ( -- adr k )
- dp 0 ;
-
-
- \ Label for branch forward, adr> brne, ......... <labelb
-: <labelb ( adr -- )
- dup 1+ dp swap -
- 7F and 3 lshift \ -- adr k7
- over @i or \ -- adr opcode
- swap !i ; \ overwrite branch
-
-
- \ Label for jump forward, adr> rjmp, ......... <labelr
-: <labelr ( adr -- )
- dup 1+ dp swap -
- 0FFF and \ -- adr k12
- over @i or \ -- adr opcode
- swap !i ; \ overwrite rjmp, rcall
-
-
- \ Label for long jump forward, adr> 0 jmp, ......... <labell
-: <labell ( adr -- )
- 1+ dp swap !i ; \ overwrite k16
-
-
-00 constant R0
-01 constant R1
-02 constant R2
-03 constant R3
-04 constant R4
-05 constant R5
-06 constant R6
-07 constant R7
-08 constant R8
-09 constant R9
-0A constant R10
-0B constant R11
-0C constant R12
-0D constant R13
-0E constant R14
-0F constant R15
-10 constant R16
-11 constant R17
-12 constant R18
-13 constant R19
-14 constant R20
-15 constant R21
-16 constant R22
-17 constant R23
-18 constant R24
-19 constant R25
-1A constant R26
-1B constant R27
-1C constant R28
-1D constant R29
-1E constant R30
-1F constant R31
-1A constant XL
-1B constant XH
-1C constant YL
-1D constant YH
-1E constant ZL
-1F constant ZH
-01 constant XH:XL \ XH:XL 3F adiw, sbiw,
-02 constant YH:YL
-03 constant ZH:ZL
-
-variable (lbl) 12 allot \ RAM for 10 labels
-
- \ store addr to vector of labels
-: >lbl ( addr c -- ) \ index c=0..9
- 2* (lbl) + ! ;
-
- \ read addr from vector of labels
-: <lbl ( c -- addr ) \ index c=0..9
- 2* (lbl) + @ ;
-
-previous definitions
diff --git a/amforth-6.5/avr8/lib/bitnames-code.frt b/amforth-6.5/avr8/lib/bitnames-code.frt
deleted file mode 100644
index 897bae3..0000000
--- a/amforth-6.5/avr8/lib/bitnames-code.frt
+++ /dev/null
@@ -1,351 +0,0 @@
-\ V 1.3, 02.11.2007
-\ V 1.3a, 15.07.2009, assembler version, L.Pekny
-
-\ Code: Matthias Trute
-\ Text: M.Kalus
-
-\ A named port pin puts a bitmask on stack, wherin the set bit indicates which
-\ bit of the port register corresponds to the pin.
-\ And then puts the address of its port on stack too.
-
-\ Use it this way:
-\ PORTD 7 portpin: PD.7 ( define portD pin #7)
-\ PD.7 high ( turn portD pin #7 on, i.e. set it high-level)
-\ PD.7 low ( turn portD pin #7 off, i.e. set it low-level)
-\ PD.7 <ms> pulse ( turn portD pin #7 for <ms> high and low)
-\ the following words are for "real" IO pins only
-\ PD.7 pin_output ( set DDRD so that portD pin #7 is output)
-\ PD.7 pin_input ( set DDRD so that portD pin #7 is input)
-\ PD.7 pin_high? ( true if pinD pin #7 is high)
-\ PD.7 pin_low? ( true if pinD pin #7 is low)
-\
-\ multi bit operation
-\ PORTD F portpin PD.F ( define the lower nibble of port d )
-\ PD.F pin@ ( get the lower nibble bits )
-\ 5 PD.F pin! ( put the lower nibble bits, do not change the others )
-
-hex
-
-\ At compiletime:
-\ Store combination of portaddress and bit number in a cell and give it a name.
-\ At runtime:
-\ Get pinmask and portaddress on stack.
-: portpin: create ( C: "ccc" portadr n -- ) ( R: -- pinmask portadr )
- 1 swap lshift
- 8 lshift or , \ packed value
- does> @i \ get packed value
- dup 8 rshift swap ff and \
-;
-
-: bitmask: create ( C: "ccc" portadr n -- ) ( R: -- pinmask portadr )
- 8 lshift or , \ packed value
- does> @i \ get packed value
- dup 8 rshift swap ff and \
-;
-
-
-\ Turn a port pin on, dont change the others.
-: high ( pinmask portadr -- )
- dup ( -- pinmask portadr portadr )
- c@ ( -- pinmask portadr value )
- rot ( -- portadr value pinmask )
- or ( -- portadr new-value)
- swap ( -- new-value portadr)
- c!
-;
-
-\ Turn a port pin off, dont change the others.
-: low ( pinmask portadr -- )
- dup ( -- pinmask portadr portadr )
- c@ ( -- pinmask portadr value )
- rot ( -- portadr value pinmask )
- invert and ( -- portadr new-value)
- swap ( -- new-value port)
- c!
-;
-
-\ pulse the pin
-: pulse ( pinmask portaddr time -- )
- >r
- over over high
- r> 0 ?do 1ms loop
- low
-;
-
-: is_low? ( pinmask portaddr -- f )
- c@ invert and
-;
-
-: is_high? ( pinmask portaddr -- f )
- c@ and
-;
-
-\ write the pins masked as output
-\ read the current value, mask all but
-\ the desired bits and set the new
-\ bits. write back the resulting byte
-: pin! ( c pinmask portaddr -- )
- dup ( -- c pm pa pa )
- >r
- c@ ( -- c pm c' )
- over invert and ( -- c pm c'' )
- >r ( -- c pm )
- and
- r> ( -- c c'' )
- or r>
- c!
-;
-
-
-\ Only for PORTx bits,
-\ because address of DDRx is one less than address of PORTx.
-
-\ Set DDRx so its corresponding pin is output.
-: pin_output ( pinmask portadr -- )
- 1- high
-;
-
-\ Set DDRx so its corresponding pin is input.
-: pin_input ( pinmask portadr -- )
- 1- low
-;
-
-\ PINx is two less of PORTx
-: pin_high? ( pinmask portaddr -- f )
- 1- 1- c@ and
-;
-
-: pin_low? ( pinmask portaddr -- f )
- 1- 1- c@ invert and
-;
-
-\ read the pins masked as input
-: pin@ ( pinmask portaddr -- c )
- 1- 1- c@ and
-;
-
-\ toggle the pin
-: toggle ( pinmask portaddr -- )
- over over pin_high? if
- low
- else
- high
- then
-;
-
-
-\ ----- assembler version -----
-\ assembler library: loadtos, savetos, TOSL,TOSH, readflashcell
-
-\ macros definitions
-: loadtos, 16 Y+ ld, 17 Y+ ld, ; \ define macro
-: savetos, -Y 17 st, -Y 16 st, ; \ tosl=r22, tosh=r23
-: TOSL 16 ;
-: TOSH 17 ;
-
- \ read flash cell to tos
-: readflashcell,
- assembler
- ZL lsl, \ addr in ZH:ZL
- ZH rol,
- TOSL Z+ lpm_,
- TOSH Z+ lpm_, ; \ @i to tos
-
-\ ---------------------------------------------
-\ macros definitions
-
- \ convert mask+addr to port+bit for cbi, sbi,
-: ma2pbi ( mask addr -- port bit )
- 20 - swap log2 ;
-
-
- \ set pin high
-: high, ( pinmask portadr -- )
- assembler
- R16 over lds, \ @portadr
- R16 rot ori, \ or pinmask
- R16 sts, ; \ c!
-
-
- \ set pin low
-: low, ( pinmask portadr -- )
- assembler
- R16 over lds, \ @portadr
- R16 rot invert andi, \ and not(pinmask)
- R16 sts, ; \ c!
-
-
- \ c@ and
-: is_high?, ( pinmask portadr -- f )
- assembler
- R16 swap lds, \ @portadr
- R16 swap andi, \ c@ and m
- savetos,
- TOSL R16 mov,
- TOSH clr, ;
-
-
- \ c@ invert and
-: is_low?, ( pinmask portadr -- f )
- assembler
- R16 swap lds, \ @portadr
- R16 com, \ invert
- R16 swap andi, \ and m
- savetos,
- TOSL R16 mov,
- TOSH clr, ;
-
-
- \ 1- 1- c@ and
-: pin@, ( pinmask portadr -- c )
- 1- 1- is_high?, ;
-
-\ macros are for high speed words
-\ pin,addr,mask is directly in asm instruction
-\ example for use macros
-\ PORTB 04 portpin: SPI_SS \ PB.4 - SPI select
-\ : setoutSS SPI_SS pin_output ;
-\ code setoutSS SPI_SS 1- high, end-code
-\ code setoutSS SPI_SS 1- ma2pbi sbi, end-code
-\ : +mmc SPI_SS low ; \ forth speed
-\ code +mmc SPI_SS low, end-code \ asm speed
-\ code +mmc SPI_SS ma2pbi cbi, end-code \ asm high speed
-\ code SPI_SS_clk
-\ SPI_SS low,
-\ SPI_SS high,
-\ end-code
-
-
-\ code definitions
-\ pin,addr,mask is read from tos
-
-code (portpin:) ( addr -- pinmask portadr )
- ZL TOSL movw, \ tos->z, addr @i
- readflashcell, \ TOSH pinmask, TOSL portadr
- R16 TOSL mov, \ temp0
- TOSL TOSH mov,
- TOSH clr,
- savetos, \ -- pinmask
- TOSL R16 mov, \ -- pinmask portadr
-end-code
-
-: portpin: create ( C: "ccc" portadr n -- ) ( R: -- pinmask portadr )
- 1 swap lshift
- 8 lshift or , \ packed value
- does> (portpin:) \ get packed value
- \ @i dup 8 rshift swap ff and \ replaced by (portpin:)
-;
-
-
-code high ( pinmask portadr -- )
- \ dup c@ rot or swap c! \ replaced by assembler
- ZL TOSL movw, \ tos->z
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- R16 TOSL or, \ or pinmask
- Z R16 st, \ c!
- loadtos, \ delete pinmask
-end-code
-
-
-code low ( pinmask portadr -- )
- \ dup c@ rot invert and swap c! \ replaced by assembler
- ZL TOSL movw, \ tos->z
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- TOSL com, \ not(pinmask)
- R16 TOSL and, \ and pinmask
- Z R16 st, \ c!
- loadtos, \ delete pinmask
-end-code
-
-
-: pin_output ( pinmask portadr -- )
- 1- high ;
-
-
-: pin_input ( pinmask portadr -- )
- 1- low ;
-
-
-code pin! ( c pinmask portadr -- )
- \ (c and m) or (@port and not(m))
- ZL TOSL movw, \ tos->z
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- R17 TOSL mov, \ pinmask
- TOSL com, \ not(pinmask)
- R16 TOSL and, \ and pinmask
- loadtos, \ delete pinmask
- R17 TOSL and, \ m and c
- R16 R17 or, \ () or ()
- Z R16 st, \ c!
- loadtos, \ delete c
-end-code
-
-
-code pin@ ( pinmask portadr -- c )
- \ 1- 1- c@ and
- ZL TOSL movw, \ tos->z
- ZH:ZL 2 sbiw, \ 1- 1-
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- TOSL R16 and, \ and pinmask
- TOSH clr,
-end-code
-
-
-code is_low? ( pinmask portaddr -- c )
- \ c@ invert and
- ZL TOSL movw, \ tos->z
- R16 Z ld, \ addr c@
- R16 com, \ invert
- loadtos, \ delete portadr
- TOSL R16 and, \ and pinmask
- TOSH clr,
-end-code
-
-
-code is_high? ( pinmask portaddr -- c )
- \ c@ and
- ZL TOSL movw, \ tos->z
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- TOSL R16 and, \ and pinmask
- TOSH clr,
-end-code
-
-
-code pin_low? ( pinmask portadr -- c )
- \ 1- 1- c@ invert and
- ZL TOSL movw, \ tos->z
- ZH:ZL 2 sbiw, \ 1- 1-
- R16 Z ld, \ addr c@
- R16 com, \ invert
- loadtos, \ delete portadr
- TOSL R16 and, \ and pinmask
- TOSH clr,
-end-code
-
-
-code pin_high? ( pinmask portadr -- c )
- \ 1- 1- c@ and
- ZL TOSL movw, \ tos->z
- ZH:ZL 2 sbiw, \ 1- 1-
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- TOSL R16 and, \ and pinmask
- TOSH clr,
-end-code
-
-
-code toggle ( pinmask portaddr -- )
- ZL TOSL movw, \ tos->z
- R16 Z ld, \ addr c@
- loadtos, \ delete portadr
- R16 TOSL eor, \ xor pinmask
- Z R16 st, \ c!
- loadtos, \ delete pinmask
-end-code
-
-\ end of file
diff --git a/amforth-6.5/avr8/lib/bitnames.frt b/amforth-6.5/avr8/lib/bitnames.frt
deleted file mode 100644
index fdda840..0000000
--- a/amforth-6.5/avr8/lib/bitnames.frt
+++ /dev/null
@@ -1,155 +0,0 @@
-\ Code: Matthias Trute
-\ Text: M.Kalus
-
-\ A named port pin puts a bitmask on stack, wherin the set bit indicates which
-\ bit of the port register corresponds to the pin.
-\ And then puts the address of its port on stack too.
-
-\ Use it this way:
-\ PORTD 7 portpin: PD.7 ( define portD pin #7)
-\ PD.7 high ( turn portD pin #7 on, i.e. set it high-level)
-\ PD.7 low ( turn portD pin #7 off, i.e. set it low-level)
-\ PD.7 <ms> pulse ( turn portD pin #7 for <ms> high and low)
-\ the following words are for "real" IO pins only
-\ PD.7 pin_output ( set DDRD so that portD pin #7 is output)
-\ PD.7 pin_input ( set DDRD so that portD pin #7 is input)
-\ PD.7 pin_high? ( true if pinD pin #7 is high)
-\ PD.7 pin_low? ( true if pinD pin #7 is low)
-\
-\ multi bit operation
-\ PORTD F bitmask: PD.F ( define the lower nibble of port d )
-\ PD.F pin@ ( get the lower nibble bits )
-\ 5 PD.F pin! ( put the lower nibble bits, do not change the others )
-
-\ #require builds.frt
-
-: bitmask: ( C: "ccc" portadr bmask -- ) ( R: -- pinmask portadr )
- <builds
- , ,
- does>
- dup @i swap i-cell+ @i
-;
-
-: portpin: ( C: "ccc" portadr n -- ) ( R: -- pinmask portadr )
- 1 over 7 and lshift >r \ bit position
- 3 rshift + \ byte address
- r> bitmask: \ portaddr may have changed
-;
-
-
-
-\ Turn a port pin on, dont change the others.
-: high ( pinmask portadr -- )
- dup ( -- pinmask portadr portadr )
- c@ ( -- pinmask portadr value )
- rot ( -- portadr value pinmask )
- or ( -- portadr new-value)
- swap ( -- new-value portadr)
- c!
-;
-
-\ Turn a port pin off, dont change the others.
-: low ( pinmask portadr -- )
- dup ( -- pinmask portadr portadr )
- c@ ( -- pinmask portadr value )
- rot ( -- portadr value pinmask )
- invert and ( -- portadr new-value)
- swap ( -- new-value port)
- c!
-;
-
-
-\ synonym off low
-\ synonym on high
-
-\ pulse the pin
-: pulse ( pinmask portaddr time -- )
- >r
- 2dup high
- r> 0 ?do 1ms loop
- low
-;
-
-: is_low? ( pinmask portaddr -- f)
- c@ and 0=
-;
-
-: is_high? ( pinmask portaddr -- f)
- c@ over and =
-;
-
-: wait_low ( pinmask portaddr -- )
- begin
- 2dup is_low?
- until 2drop
-;
-
-: wait_high_all ( pinmask portaddr -- )
- begin
- 2dup is_high?
- until 2drop
-;
-
-\ write the pins masked as output
-\ read the current value, mask all but
-\ the desired bits and set the new
-\ bits. write back the resulting byte
-: pin! ( c pinmask portaddr -- )
- dup ( -- c pm pa pa )
- >r
- c@ ( -- c pm c' )
- over invert and ( -- c pm c'' )
- >r ( -- c pm )
- and
- r> ( -- c c'' )
- or r>
- c!
-;
-
-
-\ Only for PORTx bits,
-\ because address of DDRx is one less than address of PORTx.
-
-\ Set DDRx so its corresponding pin is output.
-: pin_output ( pinmask portadr -- )
- 1- high
-;
-
-\ Set DDRx so its corresponding pin is input.
-: pin_input ( pinmask portadr -- )
- 1- low
-;
-
-\ PINx is two less of PORTx
-: pin_high? ( pinmask portaddr -- f)
- 1- 1- c@ and
-;
-
-: pin_low? ( pinmask portaddr -- f)
- 1- 1- c@ invert and
-;
-
-\ read the pins masked as input
-: pin@ ( pinmask portaddr -- c )
- 1- 1- c@ and
-;
-
-\ toggle the pin
-: toggle ( pinmask portaddr -- )
- 2dup pin_high? if
- low
- else
- high
- then
-;
-
-\ disable the pull up resistor
-: pin_pullup_off ( pinmask portaddr -- )
- 2dup pin_input low
-;
-
-
-\ enable the pull up resistor
-: pin_pullup_on ( pinmask portaddr -- )
- 2dup pin_input high
-;
diff --git a/amforth-6.5/avr8/lib/calc-baudrate.frt b/amforth-6.5/avr8/lib/calc-baudrate.frt
deleted file mode 100644
index 015eb10..0000000
--- a/amforth-6.5/avr8/lib/calc-baudrate.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-
-\ calculates the baudrate register values
-\ the two bytes of the result should be
-\ transferred in high - low order
-
-\ ( baudrate -- baud-rate-register)
-: calc-baudrate
- f_cpu
- d2/ d2/ d2/ d2/
- rot um/mod
- swap drop 1-
-;
diff --git a/amforth-6.5/avr8/lib/dot-res.frt b/amforth-6.5/avr8/lib/dot-res.frt
deleted file mode 100644
index 398bd88..0000000
--- a/amforth-6.5/avr8/lib/dot-res.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-
-\ dump free ressources
-: .res ( -- )
- base @ >r
- decimal
- ver ." running at " f_cpu #1000 um/mod . drop ." kHz " cr
- s" mcu-info" environment? if
- 2 + @i 2/ dp -
- ." free FLASH cells " u. cr
- else
- ." no flash size information available " cr
- then
- ." free RAM bytes " unused u. cr
- ." used EEPROM bytes " ehere u. cr
- ." used data stack cells " depth u. cr
- ." used return stack cells " rp0 rp@ - 1- 1- 2/ u. cr
- ." free return stack cells " rp@ sp0 - 1+ 1+ 2/ u. cr
- r> base !
-;
diff --git a/amforth-6.5/avr8/lib/eallot.frt b/amforth-6.5/avr8/lib/eallot.frt
deleted file mode 100644
index 73939cc..0000000
--- a/amforth-6.5/avr8/lib/eallot.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-\ allocate n bytes in EEPROM
-
-: eallot ( n -- )
- ehere + to ehere
-;
diff --git a/amforth-6.5/avr8/lib/forth2012/core-ext.frt b/amforth-6.5/avr8/lib/forth2012/core-ext.frt
deleted file mode 100644
index 7e16121..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core-ext.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ 'core-ext.frt' generated automatically, do not edit
-#require case.frt
-\ #require case-test.frt
-#require compile-comma.frt
-\ #require exceptions.frt
-#require marker.frt
-\ #require marker-test.frt
-
-\ update the environment
-\ get-current environment set-current
-\ : core-ext 0 ;
-\ reset the definition word list
-\ set-current
diff --git a/amforth-6.5/avr8/lib/forth2012/core-ext/avr-defers.frt b/amforth-6.5/avr8/lib/forth2012/core-ext/avr-defers.frt
deleted file mode 100644
index 0421ab3..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core-ext/avr-defers.frt
+++ /dev/null
@@ -1,20 +0,0 @@
-\ the following code works in the AVR only
-
-\ use the eeprom to keep the XT. Unlike the RAM/USER
-\ based locations, the EEPROM vector is available without
-\ initialization.
-: Edefer ( "name" -- )
- (defer)
- ehere dup ,
- ['] Edefer@ ,
- ['] Edefer! ,
- cell+ to ehere
-;
-
-\ the flash is writable, not that often, but it is
-: Idefer ( "name" -- )
- (defer)
- ['] noop , \ a dummy action as place holder
- [: @i execute ;] , \ XT is directly in the dictionary.
- [: !i ;] ,
-;
diff --git a/amforth-6.5/avr8/lib/forth2012/core-ext/marker-test.frt b/amforth-6.5/avr8/lib/forth2012/core-ext/marker-test.frt
deleted file mode 100644
index 3a7c9b0..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core-ext/marker-test.frt
+++ /dev/null
@@ -1,18 +0,0 @@
-#include dumper.frt
-#include order.frt
-#include marker.frt
-
-wordlist constant test-wl
-get-order test-wl swap 1+ set-order
-order
-marker empty
-
-' empty 4 - 10 idump
-
-: hallo ." Hallo " ;
-
-order
-words
-empty
-words
-order
diff --git a/amforth-6.5/avr8/lib/forth2012/core-ext/marker.frt b/amforth-6.5/avr8/lib/forth2012/core-ext/marker.frt
deleted file mode 100644
index 8d5756b..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core-ext/marker.frt
+++ /dev/null
@@ -1,23 +0,0 @@
-\ Defines a word which resets the dictionary and removes itself
-\ when called.
-\ Better then forget but still has limitations.
-
-\ all information is in the first few EEPROM cells.
-\ (marker) is a value that holds the max eeprom address
-
-: marker
- \ get information to remove the marker itself
- get-current @e dp
- \ create the wordlist entry
- create
- \ save all data
- (marker) 0 do i @e , 2 +loop
- \ save the marker-remove data
- , ,
- does>
- \ restore data from saved state
- (marker) 0 do dup @i i !e 1+ 2 +loop
- \ purge the marker itself
- dup @i to dp
- 1+ @i get-current !e
-;
diff --git a/amforth-6.5/avr8/lib/forth2012/core.frt b/amforth-6.5/avr8/lib/forth2012/core.frt
deleted file mode 100644
index 5db1994..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core.frt
+++ /dev/null
@@ -1,26 +0,0 @@
-\ 'core.frt' generated automatically, do not edit
-#require 2over.frt
-#require 2swap.frt
-#require aligned.frt
-#require align.frt
-#require blank.frt
-#require c-comma.frt
-#require char-plus.frt
-#require chars.frt
-#require dot-paren.frt
-#require environment-q.frt
-#require erase.frt
-#require evaluate.frt
-#require fm-slash-mod.frt
-#require star-slash.frt
-#require move.frt
-
-#require sm-slash-rem.frt
-#require source-id.frt
-#require find.frt
-
-\ update the environment
-get-current environment set-current
-: core -1 ;
-\ reset the definition word list
-set-current
diff --git a/amforth-6.5/avr8/lib/forth2012/core/align.frt b/amforth-6.5/avr8/lib/forth2012/core/align.frt
deleted file mode 100644
index e68f679..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/align.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ atmega's are always aligned
-: align ;
-
diff --git a/amforth-6.5/avr8/lib/forth2012/core/aligned.frt b/amforth-6.5/avr8/lib/forth2012/core/aligned.frt
deleted file mode 100644
index f2b942a..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/aligned.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ atmega's are always aligned
-: aligned ;
-
diff --git a/amforth-6.5/avr8/lib/forth2012/core/avr-values.frt b/amforth-6.5/avr8/lib/forth2012/core/avr-values.frt
deleted file mode 100644
index a23d0be..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/avr-values.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-\ EEPROM based values
-
-: Evalue ( n -- )
- (value)
- ehere ,
- ['] Edefer@ ,
- ['] Edefer! ,
- ehere dup cell+ to ehere !e
-;
diff --git a/amforth-6.5/avr8/lib/forth2012/core/c-comma.frt b/amforth-6.5/avr8/lib/forth2012/core/c-comma.frt
deleted file mode 100644
index 2c4e678..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/c-comma.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ a character occupies a full flash cell
-: c, , ;
-
diff --git a/amforth-6.5/avr8/lib/forth2012/core/eeprom-buffer.frt b/amforth-6.5/avr8/lib/forth2012/core/eeprom-buffer.frt
deleted file mode 100644
index 5cb2ceb..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/eeprom-buffer.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ internal EEPROM routines. They do not operate on external
-\ storage
-
-\ Ebuffer: is the EEPROM pendant to buffer: from forth200x
-\ it takes the number of bytes to allocate in RAM and parses
-\ SOURCE for the name to give to the buffer
-
-\ Eallot is the EEPROM pendant for allot from the core word set
-\ it allocates n bytes of EEPROM storage and return the starting
-\ address.
-
-: Eallot ehere + to ehere ;
-: Ebuffer: ehere constant Eallot ;
-
-\ for usage see http://amforth.sourceforge.net/TG/recipes/EEPROM.html
diff --git a/amforth-6.5/avr8/lib/forth2012/core/environment-q.frt b/amforth-6.5/avr8/lib/forth2012/core/environment-q.frt
deleted file mode 100644
index e16428d..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/environment-q.frt
+++ /dev/null
@@ -1,53 +0,0 @@
-\ environment queries are placed in a
-\ separate wordlist.
-
-\ #require imove.frt
-
-\ we have to distinguish between interpreted (RAM)
-\ and compiled (Flash) strings. First the RAM
-\ strings
-
-: (environment?) \ addr len -- 0|x*i -1
- environment search-wordlist dup
- if >r execute r> then
-;
-
-
-\ the compiled (Flash) strings are transferred
-\ to RAM and this copy processed afterwards.
-: [environment?]
- ( iaddr len -- )
- dup >r
- here imove
- here r> (environment?)
-;
-
-\ a state smart word to decide what to do.
-: environment?
- state @ if
- postpone [environment?]
- else
- (environment?)
- then
-; immediate
-
-\ some environment queries
-
-\ save the definitions word list for this file
-\ and switch to the environment queries wordlist
-get-current environment set-current
-
-: /counted-strings &60 ;
-: floored 0 ;
-: address-unit-bits $10 ;
-: max-char $ff ;
-: max-d $7fffffff. ;
-: max-ud $ffffffff. ;
-: max-n $7fff ;
-: max-u $ffff ;
-
-: return-stack-cells &10 ;
-: stack-cells &10 ;
-
-\ reset the definition word list
-set-current
diff --git a/amforth-6.5/avr8/lib/forth2012/core/evaluate.frt b/amforth-6.5/avr8/lib/forth2012/core/evaluate.frt
deleted file mode 100644
index 80659bc..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/evaluate.frt
+++ /dev/null
@@ -1,46 +0,0 @@
-\ evaluate
-\ temporarily redirect the input source
-\ to string buffer. Return the the previous
-\ input source afterwards and continue
-
-\ #require imove.frt
-
-\ some helper words
-variable strlen
-variable str
-: source-string str @ strlen @ ;
-
-\ we have to distinguish between interpreted (RAM)
-\ and compiled (Flash) strings. First the RAM
-\ strings
-
-: (evaluate) \ i*x addr len -- j*y
- ['] source defer@ >r
- >in @ >r
- 0 >in !
- strlen !
- str !
- ['] source-string is source
- ['] interpret catch
- r> >in !
- r> is source
- throw
-;
-
-\ the compiled (Flash) strings are transferred
-\ to RAM and processed there.
-: [evaluate]
- ( iaddr len -- )
- dup >r
- here imove
- here r> (evaluate)
-;
-
-\ a state smart word to decide what to do.
-: evaluate
- state @ if
- postpone [evaluate]
- else
- (evaluate)
- then
-; immediate
diff --git a/amforth-6.5/avr8/lib/forth2012/core/fm-slash-mod.frt b/amforth-6.5/avr8/lib/forth2012/core/fm-slash-mod.frt
deleted file mode 100644
index dfb10e9..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/fm-slash-mod.frt
+++ /dev/null
@@ -1,22 +0,0 @@
-
-
-: fm/mod ( d1 n1 -- n2 n3 )
- dup >r
- 2dup xor >r
- >r
- dabs r@ abs um/mod
- swap r> ?negate swap
- r> 0< if
- negate
- over if
- r@ rot - swap 1-
- then
- then
- r> drop
-;
-
-\ alternative solution
-\
-\ : FM/MOD \ ( d m -- r q ) signed floored division
-\ DUP >R SM/REM 2DUP 0< AND IF 1- SWAP R> + SWAP ELSE R> DROP THEN ;
-\ \ No newline at end of file
diff --git a/amforth-6.5/avr8/lib/forth2012/core/sm-slash-rem.frt b/amforth-6.5/avr8/lib/forth2012/core/sm-slash-rem.frt
deleted file mode 100644
index baf07cf..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/sm-slash-rem.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-
-: sm/rem ( d1 n1 -- n2 n3 )
- 2dup xor >r
- over >r
- abs >r dabs r> um/mod
- swap r> ?negate
- swap r> ?negate
-;
diff --git a/amforth-6.5/avr8/lib/forth2012/core/star-slash-mod.frt b/amforth-6.5/avr8/lib/forth2012/core/star-slash-mod.frt
deleted file mode 100644
index 9d47a61..0000000
--- a/amforth-6.5/avr8/lib/forth2012/core/star-slash-mod.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-\ #require sm-slash-rem.frt
-
-: */mod >r m* r> sm/rem ;
diff --git a/amforth-6.5/avr8/lib/hardware/25xxx.frt b/amforth-6.5/avr8/lib/hardware/25xxx.frt
deleted file mode 100644
index 2951810..0000000
--- a/amforth-6.5/avr8/lib/hardware/25xxx.frt
+++ /dev/null
@@ -1,131 +0,0 @@
-
- 6 constant SEE_WREN
- 4 constant SEE_WRDI
- 5 constant SEE_RDSR
- 1 constant SEE_WRSR
- 3 constant SEE_READ
- 2 constant SEE_WRITE
-$AB constant SEE_RDID \ Microchip 25LCxxx only; remove from deep power-down
-
- : 25xxx_disable \ raise serial EEPROM chip-select line high
- 25XXX_CS_A_MASK
- 25XXX_CS_A_PORT c@
- or
- 25XXX_CS_A_PORT c!
- ;
-
- : 25xxx_enable ( -- ) \ pull serial EEPROM chip-select line low
- 25XXX_CS_A_MASK invert
- 25XXX_CS_A_PORT c@
- and
- 25XXX_CS_A_PORT c!
- ;
-
- : 25xxx_c! ( c addr -- ) \ writes char in NOS to serial EEPROM, address in TOS
- 25xxx_enable
- 25XXX_WREN spi_send \ send enable-write command, ignore response
- 25xxx_disable
-
- 25xxx_enable
- 25XXX_WRITE spi_send \ send write command, ignore response
- 25xxx_sendaddr \ send addr (16 or 24 bits)
- spi_send \ write byte
- 25xxx_disable
- 25xxx_wait_rdy
- ;
-
- : 25xxx_! ( w seeaddrl seeaddrh -- ) \ write word in NOS to serial EEPROM at addr in TOS
- 2>r dup >< 2r> \ fast way to prep data in stack ( wl wh seeaddrl seeaddrh )
- over over 1 0 d+ \ precalc addr of second byte in data
- 2>r \ save for later ( wl wh seeaddrl seeaddrh )
- 25xxx_c! \ write MSB of word ( wl )
- 2r> \ recover addr of next byte ( wl seeaddrl+1 seeaddrh )
- 25xxx_c! \ write LSB
- ;
-
- : 25xxx_wait_rdy ( -- ) \ busy-wait until serial EEPROM finishes writing
- begin
- 25xxx_enable
- 25XXX_RDSR spi_xchg drop \ send read-status command, ignore response
- 0 spi_xchg \ send null byte, response is on TOS
- 25xxx_disable
- 1 and \ isolate the WIP (write-in-progress) bit
- 1 xor \ reverse state of WIP bit
- until \ loop until WIP = 0
- ;
-
- : see_c@ ( addrl addrh -- c ) \ returns byte at 32-bit address in TOS
- 25xxx_enable
- 25XXX_READ spi_send \ send READ command, ignore response
- 25xxx_sendaddr \ send address (16 or 24 bits)
- 0 spi_xchg \ send null byte, response is in TOS
- 25xxx_disable
- ;
-
- : 25xxx_c@_blk ( addr n eeaddrl eeaddrh -- )
- 25xxx_enable
- 25XXX_READ spi_send \ send READ command, ignore response
- 25xxx_sendaddr \ send address (16 or 24 bits)
- 0 \ ( -- addr n 0 )
- do \ for all requested bytes...
- 0 spi_xchg \ get byte from serial EEPROM
- over \ get addr to use
- c! \ save the byte
- 1+ \ bump pointer
- loop
- drop \ done with address
- 25xxx_disable
- ;
-
-
- : 25xxx_c!blk ( addr n seeaddrl seeaddrh -- ) \ copies N bytes from addr to EEPROM address in TOS/NOS
- 25xxx_enable
- 25XXX_WREN spisend \ need to enable serial EEPROM for writing
- 25xxx_disable
-
- 25xxx_enable
- 25XXX_WRITE spi_send \ send WRITE command, ignore response
- over over \ copy of 32-bit serial EEPROM addr
- 25xxx_sendaddr \ send addr to serial EEPROM ( -- addr n seeaddrl seeaddrh )
- rot \ ( -- addr seeaddrl seeaddrh n )
- 0 \ ( -- addr seeaddrl seeaddrh n 0 )
- do \ for all requested bytes ( -- addr seeaddrl seeaddrh )
- rot dup i + \ addr of byte to fetch ( -- seeaddrl seeaddrh addr addr+i )
- c@ spi_send \ write to serial EEPROM ( -- seeaddrl seeaddrh addr )
- rot dup i + \ calc addr within serial EEPROM ( -- seeaddrh addr seeaddrl seeaddrl+i )
- 7f and 7f = \ last addr in page?; use 7f for 25LC256/512, 3f for AT25128/256
- if
- 25xxx_disable \ done with this page
- 25xxx_wait_rdy
- 25xxx_enable
- 25XXX_WREN spi_send \ need to enable serial EEPROM for writing
- 25xxx_disable
- 25xxx_enable
- 25XXX_WRITE spi_send \ send WRITE command ( -- seeaddrh addr seeaddrl )
- rot \ set up EEPROM addr ( -- addr seeaddrl seeaddrh )
- over over \ get a copy
- i 1+ 0 d+ \ calc addr of next page ( -- addr seeaddrl seeaddrh seeaddrl seeaddrh )
- 25xxx_sendaddr \ send addr to serial EEPROM ( -- addr seeaddrl seeaddrh)
- else \ not start of new page ( -- seeaddrh addr seeaddrl )
- rot \ rearrange ( -- addr seeaddrl seeaddrh )
- then
- loop
- drop
- drop drop
- 25xxx_disable
- 25xxx_wait_rdy
- ;
-
-
- : 25xxx_init ( -- ) \ initialize SPI and I/O ports for accessing serial EEPROM
- spi_init
- 25XXX_CS_A_DDR c@
- 25XXX_CS_A_MASK or \ need to make CS an output
- 25XXX_CS_A_DDR c!
- 25xxx_enable
- 25XXX_RDID spi_xchg drop \ Microchip 25LCxxx only; take chip out of deep power-down
- 0 spi_xchg drop \ need to send dummy 16-bit addr, ignore response
- 0 spi_xchg drop
- 0 spi_xchg drop \ one last null byte, Microchip devices will send ID, ignore it
- 25xxx_disable
- ;
diff --git a/amforth-6.5/avr8/lib/hardware/flash-block.frt b/amforth-6.5/avr8/lib/hardware/flash-block.frt
deleted file mode 100644
index 661e3b4..0000000
--- a/amforth-6.5/avr8/lib/hardware/flash-block.frt
+++ /dev/null
@@ -1,37 +0,0 @@
-\
-\ flash-block
-\ contiguous flash region used a block storage
-\
-\ requires blocks.frt (for init and blocksize)
-\
-
-\ start address for blocks.
-\ the block data starts at
-\ flash.base-addr + (blocknum*blocksize)
-\ it could be beyond the 128K limit, if the
-\ !i and @i are replaced by words which take a
-\ doube cell address or handle the block at once
-\ (preferred)
-\
-variable flash.base-addr
-
-\ remember a flash cell contains 2 bytes
-
-: flash.load-buffer ( a-addr u -- )
- 1- blocksize 2/ * flash.base-addr @ +
- blocksize 2/ bounds ?do i @i over ! cell+ loop drop
-;
-
-: flash.save-buffer ( a-addr u -- )
- 1- blocksize 2/ * flash.base-addr @ +
- ." still debugging. no actual flash write!"
- blocksize 2/ bounds ?do dup @ i 2drop ( !i) cell+ loop drop
-;
-
-\ for turnkey
-: flash.init ( -- )
- ['] flash.load-buffer is load-buffer
- ['] flash.save-buffer is save-buffer
- 0 flash.base-addr !
- block:init
-;
diff --git a/amforth-6.5/avr8/lib/hardware/i2c-twi-master.frt b/amforth-6.5/avr8/lib/hardware/i2c-twi-master.frt
deleted file mode 100644
index 3bd2190..0000000
--- a/amforth-6.5/avr8/lib/hardware/i2c-twi-master.frt
+++ /dev/null
@@ -1,136 +0,0 @@
-\ basic I2C operations, uses 7bit bus addresses
-\ uses the TWI module of the Atmega's.
-
-#require bitnames.frt
-#require avr-values.frt
-
-\ provides public commands
-\ i2c.ping? -- checks if addr is active
-\ i2c.init -- flexible configuration setup. see below
-\ i2c.init.default -- generic slow speed setup
-\ i2c.off -- turns off I2C
-
-\ and more internal commands
-\ i2c.wait -- wait for the current i2c transaction
-\ i2c.start -- send start condition
-\ i2c.stop -- send stop condition
-\ i2c.tx -- send one byte, wait for ACK
-\ i2c.rx -- receive one byte with ACK
-\ i2c.rxn .. receive one byte with NACK
-\ i2c.status -- get the last i2c status
-
-\
-\ i2c (SCL) clock speed = CPU_clock/(16 + 2*bitrateregister*(4^prescaler))
-\ following the SCL clock speed in Hz for an 8Mhz device
-\ bitrate register (may be any value between 0 and 255)
-\ 4 8 16 32 64 128 255
-\ prescaler
-\ /1 333.333 250.000 166.667 100.000 55.556 29.412 15.209
-\ /4 166.667 100.000 55.556 29.412 15.152 7.692 3.891
-\ /16 55.556 29.412 15.152 7.692 3.876 1.946 978
-\ /64 15.152 7.692 3.876 1.946 975 488 245
-\
-\
-
--#4000 constant i2c.timeout \ exception number for timeout
-#10000 Evalue i2c.maxticks \ # of checks until timeout is reached
-variable i2c.loop \ timeout counter
-variable i2c.current \ current hwid if <> 0
-
-: i2c.timeout?
- i2c.loop @ 1- dup i2c.loop ! 0=
-;
-
-\ turn off i2c
-: i2c.off ( -- )
- 0 TWCR c!
- 0 i2c.current !
-;
-
-#0 constant i2c.prescaler/1
-#1 constant i2c.prescaler/4
-#2 constant i2c.prescaler/16
-#3 constant i2c.prescaler/64
-TWSR $3 bitmask: i2c.conf.prescaler
-
-TWCR #7 portpin: i2c.int
-TWCR #6 portpin: i2c.ea
-TWCR #5 portpin: i2c.sta
-
-\ enable i2c
-: i2c.init ( prescaler bitrate -- )
- i2c.off \ stop i2c, just to be sure
- TWBR c! \ set bitrate register
- i2c.conf.prescaler pin! \ the prescaler has only 2 bits
-;
-
-\ a very low speed initialization.
-: i2c.init.default
- i2c.prescaler/64 #3 i2c.init
-;
-
-\ wait for i2c finish
-: i2c.wait ( -- )
- i2c.maxticks i2c.loop !
- begin
- pause \ or 1ms?
- i2c.int is_high?
- i2c.timeout? if i2c.timeout throw then
- until
-;
-
-\ send start condition
-: i2c.start ( -- )
- %10100100 TWCR c!
- i2c.wait
-;
-
-\ send stop condition
-: i2c.stop ( -- )
- %10010100 TWCR c!
- \ no wait for completion.
-;
-
-\ send the restart condition (AVR simply sends start again)
-: i2c.restart ( -- )
- i2c.start
-;
-
-\ process the data, waits for completion
-: i2c.action
- %10000100 or TWCR c! \ _BV(i2cNT)|_BV(TWEN)
- i2c.wait
-;
-
-\ send 1 byte
-: i2c.tx ( c -- )
- TWDR c!
- 0 i2c.action
-;
-
-\ receive 1 byte, send ACK
-: i2c.rx ( -- c )
- %01000000 \ TWEA
- i2c.action
- TWDR c@
-;
-
-\ receive 1 byte, send NACK
-: i2c.rxn ( -- c )
- 0 i2c.action
- TWDR c@
-;
-
-\ get i2c status
-: i2c.status ( -- n )
- TWSR c@
- $f8 and
-;
-
-\ detect presence of a device on the bus
-: i2c.ping? ( addr -- f )
- i2c.start
- 2* i2c.tx
- i2c.status $18 =
- i2c.stop
-;
diff --git a/amforth-6.5/avr8/lib/hardware/i2c-twi-slave.frt b/amforth-6.5/avr8/lib/hardware/i2c-twi-slave.frt
deleted file mode 100644
index c045433..0000000
--- a/amforth-6.5/avr8/lib/hardware/i2c-twi-slave.frt
+++ /dev/null
@@ -1,89 +0,0 @@
-\ the following code is work in progress.
-\ debug output and other oddities are possible
-
-\ The slave provides a circular buffer of
-\ $10 bytes size. The variables i2c-in
-\ and i2c-out are pointers to the next
-\ byte in this buffer.
-\
-
-\ #require buffer.frt
-
-$10 constant i2c-bufsize
-
-i2c-bufsize buffer: i2c-buffer
-variable i2c-in
-variable i2c-out
-
-: ++wrap ( addr -- n )
- dup @ ( -- addr n )
- dup 0 [ i2c-bufsize 1- ] literal within
- if 1+ else drop 0 then
- dup rot !
-;
-
-: >i2c-buffer ( c -- )
- i2c-buffer i2c-in ++wrap + c!
-;
-
-: i2c-buffer> ( -- c )
- i2c-buffer i2c-out ++wrap + c@
-;
-
-
-TWCR_TWEN TWCR_TWIE TWCR_TWINT or or constant TWCR_TWENALL
-
-\ set the hw address and start the receiver
-: i2c.slave.init ( hwid -- )
- 2* \ see datasheet
- TWAR c!
- [ TWCR_TWENALL TWCR_TWEA or ] literal TWCR c!
-;
-
-: i2c.slave.twcr.ack
- [ TWCR_TWENALL TWCR_TWEA or ] literal TWCR c!
-;
-: i2c.slave.twcr.nack
- [ TWCR_TWENALL ] literal TWCR c!
-;
-
-: i2c.slave.twcr.reset
- [ TWCR_TWENALL TWCR_TWEA TWCR_TWSTO or or ] literal TWCR c!
-;
-
-\ own address received with ACK
-: i2c.addr.ack ( -- )
- \ well, nothing to do
- i2c.slave.twcr.ack
-;
-
-\ data received with NACK, probably the last one
-: i2c.data.nack ( -- )
- TWDR c@ >i2c-buffer
- i2c.slave.twcr.nack
-;
-\ data received with ACK, more to follow
-: i2c.data.ack ( -- )
- TWDR c@ >i2c-buffer
- i2c.slave.twcr.ack
-;
-
-: i2c.data.send ( -- )
- i2c-buffer> TWDR c!
- i2c.slave.twcr.ack
-;
-
-: i2c.slave.isr ( -- )
- TWSR c@ $f8 and
- \ receiving data
- dup $60 = if drop i2c.addr.ack exit then \ TW_SR_SLA_ACK
- dup $80 = if drop i2c.data.ack exit then \ TW_SR_SLA_ACK
- dup $88 = if drop i2c.data.nack exit then \ TW_SR_SLA_NACK
- \ sending data
- dup $a8 = if drop i2c.data.send exit then \ TW_ST_SLA_ACK
- dup $b8 = if drop i2c.data.send exit then \ TW_ST_DATA_ACK
- drop i2c.slave.twcr.reset
-;
-
-' i2c.slave.isr decimal TWIAddr int!
-$42 i2c.slave.init
diff --git a/amforth-6.5/avr8/lib/hardware/int-q.frt b/amforth-6.5/avr8/lib/hardware/int-q.frt
deleted file mode 100644
index 923e000..0000000
--- a/amforth-6.5/avr8/lib/hardware/int-q.frt
+++ /dev/null
@@ -1,2 +0,0 @@
-
-: int? SREG c@ SREG_I and 0> ; \ AVR
diff --git a/amforth-6.5/avr8/lib/hardware/interrupts.frt b/amforth-6.5/avr8/lib/hardware/interrupts.frt
deleted file mode 100644
index d6eae22..0000000
--- a/amforth-6.5/avr8/lib/hardware/interrupts.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ initialize interrupt vectors
-
-: initIntVectors
- #int 0 do
- ['] noop i int!
- loop
-;
diff --git a/amforth-6.5/avr8/lib/hardware/key2char.frt b/amforth-6.5/avr8/lib/hardware/key2char.frt
deleted file mode 100644
index 37e3d45..0000000
--- a/amforth-6.5/avr8/lib/hardware/key2char.frt
+++ /dev/null
@@ -1,135 +0,0 @@
-\ Convert tab for Keyboard.frt - Lubos Pekny, www.forth.cz
-\ V.1.0, 26.05.2008
-\ keyboard scan code->ascii char, 128 words, Hi:Lo byte (Hi is with shift)
-
-create kbd_CHARTAB
-\ ascii key char char^
-0000 , \ 00
-0000 , \ 01 F9
-0000 , \ 02
-0000 , \ 03 F5
-0000 , \ 04 F3
-0000 , \ 05 F1
-0000 , \ 06 F2
-0000 , \ 07 F12
-0000 , \ 08
-0000 , \ 09 F10
-0000 , \ 0A F8
-0000 , \ 0B F6
-0000 , \ 0C F4
-0909 , \ 0D TAB
-7E60 , \ 0E ` ~
-0000 , \ 0F
-0000 , \ 10
-0000 , \ 11 ALT
-0000 , \ 12 Left SHIFT
-0000 , \ 13
-0000 , \ 14 Ctrl
-5171 , \ 15 q Q
-2131 , \ 16 1 !
-0000 , \ 17
-0000 , \ 18
-0000 , \ 19
-5A7A , \ 1A z Z
-5373 , \ 1B s S
-4161 , \ 1C a A
-5777 , \ 1D w W
-4032 , \ 1E 2 @
-0000 , \ 1F
-0000 , \ 20
-4363 , \ 21 c C
-5878 , \ 22 x X
-4464 , \ 23 d D
-4565 , \ 24 e E
-2434 , \ 25 4 $
-2333 , \ 26 3 #
-0000 , \ 27
-0000 , \ 28
-2020 , \ 29 Space
-5676 , \ 2A v V
-4666 , \ 2B f F
-5474 , \ 2C t T
-5272 , \ 2D r R
-2535 , \ 2E 5 %
-0000 , \ 2F
-0000 , \ 30
-4E6E , \ 31 n N
-4262 , \ 32 b B
-4868 , \ 33 h H
-4767 , \ 34 g G
-5979 , \ 35 y Y
-5E36 , \ 36 6 ^
-0000 , \ 37
-0000 , \ 38
-0000 , \ 39
-4D6D , \ 3A m M
-4A6A , \ 3B j J
-5575 , \ 3C u U
-2637 , \ 3D 7 &
-2A38 , \ 3E 8 *
-0000 , \ 3F
-0000 , \ 40
-3C2C , \ 41 , <
-4B6B , \ 42 k K
-4969 , \ 43 i I
-4F6F , \ 44 o O
-2930 , \ 45 0 )
-2839 , \ 46 9 (
-0000 , \ 47
-0000 , \ 48
-3E2E , \ 49 . >
-3F2F , \ 4A / ?
-4C6C , \ 4B l L
-3A3B , \ 4C ; :
-5070 , \ 4D p P
-5F2D , \ 4E - _
-0000 , \ 4F
-0000 , \ 50
-0000 , \ 51
-2227 , \ 52 ' "
-0000 , \ 53
-7B5B , \ 54 [ {
-2B3D , \ 55 = +
-0000 , \ 56
-0000 , \ 57
-0000 , \ 58 Caps Lock
-0000 , \ 59 Right Shift
-0D0D , \ 5A Enter
-7D5D , \ 5B ] }
-0000 , \ 5C
-7C5C , \ 5D \ |
-0000 , \ 5E
-0000 , \ 5F
-0000 , \ 60
-0000 , \ 61
-0000 , \ 62
-0000 , \ 63
-0000 , \ 64
-0000 , \ 65
-0808 , \ 66 Backspace
-0000 , \ 67
-0000 , \ 68
-3100 , \ 69 END, NUM 1
-0000 , \ 6A
-3400 , \ 6B LEFT, NUM 4
-3700 , \ 6C HOME, NUM 7
-0000 , \ 6D
-0000 , \ 6E
-0000 , \ 6F
-3000 , \ 70 INS, NUM 0
-2E00 , \ 71 DEL, NUM .
-3200 , \ 72 DOWN, NUM 2
-3500 , \ 73 , NUM 5
-3600 , \ 74 RIGHT,NUM 6
-3800 , \ 75 UP, NUM 8
-1B1B , \ 76 ESC
-0000 , \ 77 NUM LOCK
-0000 , \ 78 F11
-2B2B , \ 79 NUM +
-3300 , \ 7A PgDwn,NUM 3
-2D2D , \ 7B NUM -
-2A2A , \ 7C NUM *
-3900 , \ 7D PgUp, NUM 9
-0000 , \ 7E SCROLL LOCK
-0000 , \ 7F
-\ 83 F7
diff --git a/amforth-6.5/avr8/lib/hardware/keyboard.frt b/amforth-6.5/avr8/lib/hardware/keyboard.frt
deleted file mode 100644
index 7182f26..0000000
--- a/amforth-6.5/avr8/lib/hardware/keyboard.frt
+++ /dev/null
@@ -1,486 +0,0 @@
-\ Keyboard PS/2 - Lubos Pekny, www.forth.cz
-\ Library for amforth 3.0 mFC 1.0
-
-\ V.1.2v, 29.01.2009, add vocabulary
-
-\ V.1.2, 14.01.2009, tested on atmega32, amforth 3.0
-\ - add err bit in kbd_FLGR
-\ - add sync to kbd_ekey?
-
-\ V.1.1, 06.07.2008, tested on atmega32, amforth 2.7
-\ - changes in key->ps2, kbd_ascii, kbd_sync, appl_kbdlcd
-\ - optimalized restart and clk-sync
-
-\ V.1.0, 03.07.2008, tested on atmega32, amforth 2.7
-\ - used INT2 + 1 pin
-\ - kbd_init kbd_char kbd_ekey? kbd_ekey
-\ - ekey? ekey ekey>char ekey>fkey key? key
-
-\ a = char a $61
-\ shift+a = char A $41
-\ ctrl+a = no char, events $401C
-\ ctrl+shift+a = char $01
-\ alt+char = $80+char
-\ alt+ctrl+shift+a = char $81
-
-#include key2char.frt \ V 1.0, 26.05.2008
-
-hex
-
-forth
-<bit> definitions \ into vocabulary <bit>
-
-38 constant PORTB \ Atmega32, PB.2 (INT2)<-clk, PB.1 (in)<-data out
-
-forth
-<kbd> definitions \ into vocabulary <kbd>
-
-variable PENDING-CHAR \ for key?, key
-variable kbd_CNTR \ r4:w4:b8, 8bit+2x4b circular buf counters
-variable kbd_ROTR \ received bits from keyboard
-variable kbd_FLGR \ flags, final hi=|alt|ctrl|shift|num|releas|extend|0|err|
- \ work lo=|altL|altR|ctrlL|ctrlR|shiftL|shiftR|caps|num|
-variable kbd_SKEY \ keyboard scan code+flags
- 8 cells allot \ 8 events buf
-
-8000 constant K-ALT-MASK
-4000 constant K-CTRL-MASK
-2000 constant K-SHIFT-MASK
-1000 constant K-NUM-MASK
-0800 constant K-RELEAS-MASK
-0400 constant K-EXTEND-MASK
-0100 constant K-EVENTS-MASK
-
-
- \ interrupt, keyboard clock
-code kbd_clk
- R18 push,
- R18 3F in, \ SREG 0x3F(0x5F)
- R18 push,
- R17 push, R16 push,
- ZH push, ZL push,
-
-\ --- Receive bits --
- R16 kbd_ROTR lds, \ received bits reg
- R17 kbd_ROTR 1+ lds,
- clc, \ CY=0
- <bit> PORTB assembler
- 22 - 1 sbic, \ PinB.1=1 then CY=1
- sec,
- R17 ror, R16 ror, \ CY->R17.7->R16, rotate
- kbd_ROTR 1+ R17 sts,
- kbd_ROTR R16 sts, \ update variable kbd_ROTR
-
- R18 kbd_CNTR lds, \ bit counter reg
- R18 0F andi,
- R18 00 cpi, \ =0 then 0B
- adr> brne,
- R18 0B ldi,
- <labelb
- R18 0B cpi, \ >=0B then 0B
- adr> brcs,
- R18 0B ldi,
- <labelb
- R18 dec, \ dec bit counter, 0A..00
- kbd_CNTR R18 sts, \ update variable kbd_CNTR
- adr> brne, 0 >lbl \ all 8+3 bits? else end
-
- R16 rol,
- R17 rol, \ CY=stopbit
- adr> brcc, 1 >lbl \ CY=0 then error end
- R16 rol,
- R17 rol, \ CY=parity, data
- R16 rol, \ CY=startbit
- adr> brcs, 2 >lbl \ CY=1? then error end
-
-\ --- Entry point, R17-scan code
-
- ZL kbd_FLGR lds, \ work flags
- ZH kbd_FLGR 1+ lds, \ final flags
-
- R18 kbd_CNTR 1+ lds, \ buf counters
- R16 R18 mov, \ read:write counter
- R16 swap,
- R18 inc, \ wr+1, next position
- R18 07 andi, \ 3b counters
- R16 0F andi,
- R16 R18 cp, \ rd=wr+1? ->no overwrite buf
- adr> breq, 3 >lbl \ end
-
- R16 swap,
- R16 R18 or, \ rd:wr+1, update counter
-
- R17 E0 cpi, \ data>=E0 then no update
- adr> brcc, 4 >lbl \ skip for EXTEND or RELEAS
-
- kbd_CNTR 1+ R16 sts, \ update position
-
-\ --- Flags ---
- adr> rcall, 5 >lbl \ make work flags
- adr> rcall, 6 >lbl \ make final flags
-
-\ --- Write to the buf ---
- R16 clr, \ write to the kbd_SKEY buf
- R18 lsl, \ 2*(wr+1)
- ZL kbd_SKEY ldi, \ addr buf
- ZH kbd_SKEY >< ldi,
- ZL R18 add,
- ZH R16 adc, \ ZH:ZL+0:R18
- Z+ R17 st, \ scan code->lo(kbd_SKEY+wr)
- R17 kbd_FLGR 1+ lds,
- Z+ R17 st, \ flags->hi(kbd_SKEY+wr)
- kbd_FLGR 1+ R16 sts, \ clear final flags
- R16 R16 cpse, \ end
-
-\ --- EXTEND or RELEAS ---
- 4 <lbl <labelb
- adr> rcall, 7 >lbl \ set flag EXTEND or RELEAS
-
-\ --- End ---
- 3 <lbl <labelb \ from No everwrite
- 0 <lbl <labelb \ from No all bits
- label> \ from Set err
- ZL pop, ZH pop,
- R16 pop, R17 pop,
- R18 pop, 3F R18 out,
- R18 pop,
- reti,
-
-\ --- Set err ---
- 2 <lbl <labelb
- 1 <lbl <labelb
- R17 kbd_FLGR 1+ lds,
- R17 1 ori,
- kbd_FLGR 1+ R17 sts, \ set err in final flags
- <radr rjmp, \ jump to end
-
-
-\ --- Subroutines ---
-
-\ Set flag EXTEND or RELEAS (E0 or F0)
- 7 <lbl <labelr \ ZH-final flags
- R17 F0 cpi, \ R17-scan code
- adr> brcc, \ >=F0
- ZH K-EXTEND-MASK >< ori,
- ZH ZH cpse,
- <labelb
- ZH K-RELEAS-MASK >< ori,
- kbd_FLGR 1+ ZH sts, \ update final flags
- ret,
-
-
-\ Make work flags, Caps, LShift, RShift, etc.
- 5 <lbl <labelr \ R17-scan code, ZL-work flags
- R16 clr,
- R17 77 cpi, \ num
- 1 brne,
- R16 01 ldi,
- R17 58 cpi, \ caps
- 1 brne,
- R16 02 ldi,
- R17 59 cpi, \ Rshift
- 1 brne,
- R16 04 ldi,
- R17 12 cpi, \ Lshift
- 1 brne,
- R16 08 ldi,
-
- ZH 02 sbrc, \ E0?
- adr> rjmp, \ jmp EXTEND
-
- R17 14 cpi, \ ctrl no EXTEND
- 1 brne,
- R16 10 ldi,
- R17 11 cpi, \ alt
- 1 brne,
- R16 40 ldi,
- adr> rjmp, \ jmp test F0
-
- swap <labelr \ yes EXTEND
- R17 14 cpi, \ ctrl
- 1 brne,
- R16 20 ldi,
- R17 11 cpi, \ alt
- 1 brne,
- R16 80 ldi,
-
- <labelr \ test F0
- R16 4 cpi, \ <4
- adr> brcs, \ jmp num or caps
- ZH 03 sbrs, \ F0?
- adr> rjmp, \ jmp no RELEAS
- R16 com,
- ZL R16 and, \ clear flag
- ZL ZL cpse, \ skip
- <labelr \ no RELEAS
- ZL R16 or, \ set flag
- kbd_FLGR ZL sts, \ update work flags
- ret,
-
- <labelb \ num or caps
- ZH 03 sbrc, \ F0?
- ret, \ yes F0
- ZL R16 eor, \ no F0, then flip
- kbd_FLGR ZL sts, \ update work flags
- ret,
-
-
-\ Make final flags, SHIFT=CAPS xor (LShift or RShift)
- 6 <lbl <labelr
- R16 K-SHIFT-MASK >< ldi,
- ZL 7 sbrc, \ test work flags
- ZH K-ALT-MASK >< ori, \ set final flags
- ZL 6 sbrc,
- ZH K-ALT-MASK >< ori,
- ZL 5 sbrc,
- ZH K-CTRL-MASK >< ori,
- ZL 4 sbrc,
- ZH K-CTRL-MASK >< ori,
- ZL 3 sbrc,
- ZH K-SHIFT-MASK >< ori,
- ZL 2 sbrc,
- ZH K-SHIFT-MASK >< ori,
- ZL 1 sbrc,
- ZH R16 eor,
- ZL 0 sbrc,
- ZH K-NUM-MASK >< ori,
- kbd_FLGR 1+ ZH sts, \ update final flags
- ret,
-end-code
-
-
-940C 0006 i! ' kbd_clk i@ 0007 i! \ Set INT2 vector
-
- \ INT2 enabled, clear buf
-: kbd_init ( -- )
- <bit>
- -int drop
- PORTB c@ 06 or PORTB c! \ pull-up
- PORTB 1- c@ F9 and PORTB 1- c! \ DDRB, PB.1,2 in
- 54 c@ BF and 54 c! \ MCUCSR.ISC2=0, 0x34(0x54).6, fall
- 5B c@ 20 or 5B c! \ GICR.INT2=1, 0x3B(0x5B).5, enable
- +int
- 0 kbd_CNTR ! 0 kbd_ROTR ! 1 kbd_FLGR ! \ all reset, set num
- 10 0 do 0 kbd_SKEY i + c! loop \ clear buffer
- -1 PENDING-CHAR ! ;
-
-
- \ convert scan code to visible char
-: kbd_char ( u -- char ) \ u=|alt|ctrl|shift|num|releas|extend|0|0|:|8b code|
- dup 7F and dup \ -- u c c
- kbd_CHARTAB + i@ \ -- u c 2char
- swap \ -- u 2char c
- dup 68 > swap 7E < and \ c=69..7D then num else shift
- if \ -- u 2char
- swap K-NUM-MASK and \ num?
- else
- swap K-SHIFT-MASK and \ shift?
- then
- if >< then \ swap byte in 2char, Hi->Lo
- FF and ; \ -- char
-
-
- \ convert scan code to ascii,+ctrl+alt
-: kbd_ascii ( u -- char )
- dup 0C00 and \ releas,extend?
- if drop 00 exit then \ event, char 00
- dup kbd_char \ -- u char
- dup 0=
- if swap drop exit then \ -- 00, isn't visible char
- over K-CTRL-MASK and \ -- u char, ctrl?
- if
- dup 3F > over 60 < and \ 64<=char<96
- if
- 40 - \ -- char-64
- else
- drop drop 00 exit \ event, char 00
- then
- then
- swap K-ALT-MASK and \ alt?
- if 80 + then ; \ -- char+128
-
-
- \ int-, set b7 in kbd_CNTR, int+
-code kbd_b7set
- R18 push,
- R18 3F in, \ SREG 0x3F(0x5F)
- R18 push,
- cli,
- R18 kbd_CNTR lds, \ bit counter reg
- R18 80 ori, \ set b7
- kbd_CNTR R18 sts,
- sei,
- R18 pop, 3F R18 out,
- R18 pop,
-end-code
-
-
- \ int-, b7=1? then clear kbd_CNTR, int+
-code kbd_b7tst
- R18 push,
- R18 3F in, \ SREG 0x3F(0x5F)
- R18 push,
- cli,
-
- R18 kbd_CNTR lds, \ bit counter reg
- R18 rol,
- adr> brcc, \ b7=0? then end
- R18 clr,
- kbd_CNTR R18 sts, \ clear bits counter
-
- <labelb
- sei,
- R18 pop, 3F R18 out,
- R18 pop,
-end-code
-
-
- \ sync clk - set bit, wait, int2 clear this bit
-: kbd_sync ( -- ) \ v.1.1 15ms->3ms, int-, int+
- kbd_b7set \ set b7 in kbd_CNTR
- 3 ms
- kbd_b7tst ; \ b7=1? then clear bits counter
-
-
- \ keyboard events?, rd<>wr counter
-: kbd_ekey? ( -- flag )
- kbd_FLGR 1+ c@ 1 and \ flag err is set in kbd_clk
- if
- kbd_FLGR 1+ dup c@ \ -- addr c
- FE and swap c! \ clear err
- 3 ms 0 kbd_CNTR c! \ if err then sync
- then
- kbd_CNTR 1+ c@ \ -- rd:wr, 3b counters
- dup 4 lshift F0 and \ -- rd:wr wr:0
- swap F0 and xor ; \ wr=rd?, 0 is false
-
-
- \ Read event, scan code from buffer
-: kbd_ekey ( -- u ) \ |alt|ctrl|shift|num|releas|extend|0|0|:|8b code|
- begin kbd_ekey? until \ events?
- kbd_CNTR 1+ dup c@ dup \ -- addr addr rd:wr rd:wr
- 4 rshift 1+ 07 and \ -- addr addr rd:wr 0:rd+1
- >r 0F and r@ 4 lshift or \ -- addr addr rd+1:wr
- swap c! \ -- addr, update counter rd
- r> 2* kbd_SKEY + @ \ kbd_SKEY+2*(rd+1) @
- kbd_sync ; \ sync after stopbit
-
-
- \ convert num '/','enter' to char
-: kbd_numchar ( u -- u|char )
- dup 0FFF and dup \ -- u1 u2 u2
- 054A = swap 55A = or \ -- u1 flag
- if
- F0FF and kbd_ascii \ num '/','enter'
- then ;
-
-
-: ekey? ( -- flag )
- kbd_ekey? ;
-
-
- \ Ascii char or u scan code
-: ekey ( -- char|u )
- kbd_ekey dup kbd_ascii \ -- u char
- ?dup 0=
- if
- K-EVENTS-MASK or \ -- u+256
- K-NUM-MASK invert and \ clear num
- else
- swap drop \ -- char
- then
- kbd_numchar ; \ '/','enter'
-
-
-: ekey>char ( u -- u false|char true)
- dup FF u>
- if false else true then ;
-
-
-: ekey>fkey ( u1 -- u2 flag )
- dup ekey>char swap drop 0= ;
-
-
-: ps2key? ( -- flag )
- PENDING-CHAR @ 0<
- if
- begin
- ekey?
- while
- ekey ekey>char
- if
- PENDING-CHAR ! true exit
- then drop
- repeat false exit
- then true ;
-
-
-: ps2key ( -- char )
- PENDING-CHAR @ 0<
- if
- begin
- ekey ekey>char 0=
- while
- drop
- repeat exit
- then
- PENDING-CHAR @ -1 PENDING-CHAR ! ;
-
-
- \ Switch key to ps2 keyboard
-: key->ps2 ( -- )
- ['] ps2key ['] key defer!
- ['] ps2key? ['] key? defer!
- ['] noop ['] /key defer! ; \ v.1.1 add /key
-
-
- \ Switch key to serial port
-: key->rx0 ( -- )
- ['] rx0 ['] key defer!
- ['] rx0? ['] key? defer! ;
-
-
- \ Alone system PS2-keyboard+LCD20x4
- \ PS2 keyboard started slowly. To delay amforth abouth 0.5s
- \ +echo or set eeprom $14.0=H if you need view keyboard char
-: appl_kbdlcd
- 200 ms \ v.1.1, to delay amforth or app restart
- <lcd>
- applturnkey
- kbd_init scr_init
- key->ps2 emit->scr
- ver ;
-
-
-\ Write to the eeprom appl started after switch on.
-\ ' appl_kbdlcd 0A e! \ PS2+LCD
-\ ' applturnkey 0A e! \ UART0
-\ ' appl_mpc 0A e! \ applturnkey+slave detect
-
-
-\ ----- Test key -----
-
- \ info about pressed key, 'Ctrl+c' end loop
-: kbd_info ( -- )
- begin
- ekey \ get char|event
- dup 21 \ 'c'
- K-EVENTS-MASK or \ event, no ascii
- K-CTRL-MASK or <> \ ctrl+c?
- while
- dup u. space \ code
- dup FF u> \ char
- if drop else emit then
- cr
- repeat drop ;
-
- \ write text, 'Esc' end loop
-: kbd_writer ( -- )
- begin
- ps2key \ get char
- dup 1B <> \ Esc?
- while
- emit \ view char
- repeat drop ;
-
-\ end of file
diff --git a/amforth-6.5/avr8/lib/hardware/mmc.frt b/amforth-6.5/avr8/lib/hardware/mmc.frt
deleted file mode 100644
index f213c9b..0000000
--- a/amforth-6.5/avr8/lib/hardware/mmc.frt
+++ /dev/null
@@ -1,371 +0,0 @@
-\ MMC+SD card - Lubos Pekny, www.forth.cz
-\ Library for amforth 3.0, mFC modification
-\ Max. 4GB no SDHC, access thru buffer 512B or short block or direct
-
-\ V.1.0, 16.07.2009, tested on atmega32, amforth30mFC12.zip
-\ - used SPI (MOSI, MISO, SCK, SS)
-\ mmc_init, mmc_CID, mmc_CSD, mmc_read, mmc_mread, mmc_write,
-\ mmc_blk@, mmc_blk!, mmc_c@, mmc_c!, mmc_end?, mmc_end!
-
-\ needs +/-spi for pin configuration
-\ needs +/-mmc for slave select action
-
-hex
-
-variable mmc_#buf \ position in buf
-variable mmc_buf 1FE allot \ 512B RAM
-
-
- \ enable spi for mmc, set I/O
-: mmc_+spi ( -- )
- +spi
- -spi2x
- SPCR_SPE SPCR_MSTR or
- spi.f/128 or
- spi.mode0 or SPCR c! ;
-
- \ send dummy byte x-times
-: mmc_dummy ( x -- )
- 0 ?do $ff c!spi loop ;
-
-
-\ convert 32b block to byte addr, double 9 lshift
-: mmc_blk2addr ( L H -- L H )
- swap dup 9 lshift \ -- H L L<<9
- swap 7 rshift \ -- H L<<9 L>>7
- rot 9 lshift or ; \ -- L<<9 H<<9
-
-
- \ waiting for cmd response
-: mmc_cresp ( -- c|-1 )
- FF 0 do
- c@spi dup 80 and 0= \ bit7=0?
- if unloop exit then \ -- c, 0=ok
- drop \ --
- loop -1 ; \ -- -1, timeout
-
-
- \ waiting for data response
-: mmc_dresp ( -- c|-1 )
- FF 0 do
- c@spi dup 11 and 1 = \ xxx0ccc1
- if
- 0F and unloop exit \ -- c, 5=ok
- then
- drop \ --
- loop -1 ; \ -- -1, timeout
-
-
- \ waiting for token
-: mmc_token ( -- c|-1 )
- FF 0 do
- c@spi dup FF - \ <>FF?
- if unloop exit then \ -- c, FC,FE=ok
- drop \ --
- loop -1 ; \ -- -1, timeout
-
-
- \ waiting while busy, after write
-: mmc_busy ( -- 0|-1 )
- FF 0 do
- c@spi FF = \ =FF?
- if 0 unloop exit then \ -- 0, ok
- loop -1 ; \ -- -1, timeout
-
-
- \ send command cmd, data xl, xh
-: mmc_cmd ( xl xh cmd -- c|-1 )
- FF c!spi \ flush spi register
- 40 or c!spi \ send command cmd
- dup >< c!spi c!spi \ send xhh, xhl
- dup >< c!spi c!spi \ send xlh, xll
- 95 c!spi \ no crc
- mmc_cresp ; \ -- c|-1, c=0 no errors
-
-
- \ set block length
-: mmc_length ( n -- c|-1 )
- 0 10 mmc_cmd ; \ CMD16
-
-
- \ stop multiread
-: mmc_rstop ( -- c|-1 )
- 0 0 C mmc_cmd \ CMD12
- mmc_busy or -mmc ; \ -- c|-1, c=0 no errors
-
-
- \ stop multiwrite
-: mmc_wstop ( -- c|-1 )
- FD c!spi \ Stop tran for CMD25
- FF c!spi \ 1B wait
- mmc_busy -mmc ; \ -- c|-1, c=0 no errors
-
-
- \ reset card, idle
-: mmc_reset ( -- c|-1 )
- -mmc 10 mmc_dummy \ 74< clk to reset mmc
- +mmc
- 0 0 0 mmc_cmd ; \ CMD0, -- 1, reset ok
-
-
- \ detect sd card, 0=SD, -1=timeout
-: mmc_sd? ( -- c|-1 )
- 0 0 37 mmc_cmd drop \ CMD55
- 0 0 29 mmc_cmd \ ACMD41, -- c
- dup 1+ \ -- -1 0, timeout
- if 4 and then ; \ SD(R1.2=0) / MMC(R1.2=1)
-
-
- \ wait for init MMC card
-: mmc_waitmmc ( -- 0|-1 )
- FF \ -- cnt
- begin
- 0 0 1 mmc_cmd 0= \ CMD1, -- cnt f
- if drop 0 exit then \ -- 0, ok
- 1- dup 0= \ -- cnt-1 f
- until 1- ; \ -- -1, timeout
-
-
- \ wait for init SD card
-: mmc_waitsd ( -- 0|-1 )
- FF \ -- cnt
- begin
- 0 0 37 mmc_cmd drop \ CMD55
- 0 0 29 mmc_cmd 0= \ ACMD41, -- cnt f
- if drop 0 exit then \ -- 0, ok
- 1- dup 0= \ -- cnt-1 f
- until 1- ; \ -- -1, timeout
-
-
-
-
- \ check end of sector, for mmc read
-: mmc_end? ( -- flag )
- 200 mmc_#buf @
- > 0= dup \ -- c c, -1=end
- if \ size<=#buf then
- 2 mmc_dummy \ dummy crc
- then ;
-
-
-\ check end of sector, wait for no busy, for mmc write
-: mmc_end! ( -- 0|-1 )
- mmc_end? \ -- flag, crc dummy for end
- if
- mmc_dresp 5 <> \ -- 0, 0=ok, response
- mmc_busy or \ -- c, 0=ok, writed
- else 0 then ; \ -- c, 0=ok, -1=timeout
-
-
-: mmc_buf> ( addr n -- 0|-1 )
- dup mmc_#buf +! \ +n, update buf position
- 0 ?do \ addr n -- send n bytes from addr
- dup c@ c!spi 1+ \ -- addr+1
- loop drop
- \ n!spi
- mmc_end! ; \ -- c, 0=ok, -1=timeout
-
-
- \ copy spi to buf
-: mmc_>buf ( addr n -- )
- dup mmc_#buf +! \ +n, update buf position
- 0 ?do \ write n bytes to addr
- c@spi over c! 1+ \ -- addr+1
- loop drop
-\ n@spi
- mmc_end? drop ; \ crc dummy for end
-
-
- \ wait for token, copy first n bytes to buf
-: mmc_(read) ( n 0 -- c|-1 )
- 0 mmc_#buf ! \ reset buf position
- dup 0= \ 0 -- , cmd ok
- if
- drop mmc_token dup \ c -- c c
- FE =
- if
- drop mmc_buf swap \ -- addr n
- mmc_>buf 0 \ -- 0, ok
- else
- swap drop \ n c -- c
- then
- else
- swap drop \ n c -- c
- then ; \ 0=ok, -1=timeout
-
-
- \ copy first n bytes to card, response, busy
-: mmc_(write) ( n 0 -- c|-1 )
- 0 mmc_#buf ! \ reset buf position
- dup 0= \ 0 -- , cmd ok
- if
- drop FF c!spi \ wait 1B
- FE c!spi \ send start byte
- mmc_buf swap \ -- addr n
- mmc_buf> \ -- c, 0=ok, -1=timeout
- else
- swap drop \ n c -- c
- then ; \ 0=ok, -1=timeout
-
-
- \ copy first n bytes to card, multiwrite, busy
-: mmc_(mwrite) ( n 0 -- c|-1 )
- 0 mmc_#buf ! \ reset buf position
- dup 0= \ 0 -- , cmd ok
- if
- drop FF c!spi \ wait 1B
- FC c!spi \ send start byte
- mmc_buf swap \ -- addr n
- mmc_buf> \ -- c, 0=ok, -1=timeout
- else
- swap drop \ n c -- c
- then ; \ 0=ok, -1=timeout
-
-
-\ ----- final words -----
-
- \ initialize card MMC or SD v.1.x
-: mmc_init ( -- x|-1 )
- 0 mmc_#buf !
- mmc_+spi \ init spi, I/O
- mmc_reset \ -- c, 1=ok
- dup 1-
- if -mmc 100 xor exit then \ <>1 then exit
- drop \ --
-
- mmc_sd? \ detect SD
- dup 0< \ -- 0, SD
- if -mmc 200 xor exit then \ -1 --, timeout
- if
- mmc_waitmmc \ MMC init
- else
- mmc_waitsd \ SD init
- then
- 200 mmc_length \ set sector length
- or -mmc ; \ -- 0|-1, 0=ok, -1=timeout
-
-
- \ read CID register 16B
-: mmc_CID ( -- c|-1 )
- +mmc 10 \ length 16B
- 0 0 A mmc_cmd \ CMD10,
- mmc_(read) \ 10 c -- c, 0=ok, -1=timeout
- 2 mmc_dummy \ dummy CRC
- -mmc ;
-
-
- \ read CSD register 16B
-: mmc_CSD ( -- c|-1 )
- +mmc 10 \ length 16B
- 0 0 9 mmc_cmd \ CMD9
- mmc_(read) \ 10 c -- c, 0=ok, -1=timeout
- 2 mmc_dummy \ dummy CRC
- -mmc ;
-
-
- \ open sector for read, copy n bytes to buf
- \ 200 ABCD 7F mmc_read \ open,copy 512B from sector
- \ 0 ABCD 7F mmc_read \ only open sector 7FABCD
-: mmc_read ( n xl xh -- c|-1 ) \ length, sector addr
- +mmc
- mmc_blk2addr \ addr*512, block->byte
- 11 mmc_cmd \ addrL addrH 11 --, CMD17
- mmc_(read) \ n c -- c, 0=ok, -1=timeout
- -mmc ;
-
-
- \ open sector for multi read, copy n bytes to buf
-: mmc_mread ( n xl xh -- c|-1 ) \ length, sector addr
- +mmc
- mmc_blk2addr \ addr*512, block->byte
- 12 mmc_cmd \ addrL addrH 12 --, CMD18
- mmc_(read) \ n c -- c, 0=ok, -1=timeout
- -mmc ;
-
-
- \ open sector for write, copy n bytes from buf to card
-: mmc_write ( n xl xh -- c|-1 ) \ length, sector addr
- +mmc
- mmc_blk2addr \ addr*512, block->byte
- 18 mmc_cmd \ addrL addrH 18 --, CMD24
- mmc_(write) \ n c -- c, 0=ok, -1=timeout
- -mmc ;
-
-
- \ open sector for multi write, copy n bytes from buf to card
-: mmc_mwrite ( n xl xh -- c|-1 ) \ length, sector addr
- +mmc
- mmc_blk2addr \ addr*512, block->byte
- 19 mmc_cmd \ addrL addrH 19 --, CMD25
- mmc_(mwrite) \ n c -- c, 0=ok, -1=timeout
- -mmc ;
-
-
- \ read short block from opened sector to buf
- \ use mmc_read or mmc_(read) first
-: mmc_blk@ ( addr n -- ) \ addr, length of blk
- +mmc
- mmc_>buf \ addr n -- ,copy spi to buf
- -mmc ;
-
-
- \ write short block to opened sector from buf
- \ use mmc_write or mmc_(write) first
-: mmc_blk! ( addr n -- 0|-1 ) \ addr, length of blk
- +mmc
- mmc_buf> \ addr n -- 0|-1, from buf
- -mmc ; \ 0=ok, -1=timeout
-
-
- \ direct read byte from opened sector
- \ note: +mmc, if end of sector then dummy crc, -mmc
-: mmc_c@ ( -- c )
- c@spi \ read byte from card
- 1 mmc_#buf +! ; \ increment position
-
-
- \ direct write byte to opened sector
- \ note: +mmc, if end of sector then mmc_end!, -mmc
-: mmc_c! ( c -- )
- c!spi \ write byte to card
- 1 mmc_#buf +! ; \ increment position
-
-
- \ view n bytes from mmc_buf+offset
-: mmc. ( n offset -- )
- mmc_buf + swap
- 0 ?do \ addr n -- view n bytes from addr
- dup c@ . 1+ \ -- addr+1
- loop drop ;
-
-
-\ sptx Stop transmit
-
-: mmc_tstmread ( n -- ) \ read n x 1MB
- 0 .
- 200 0 0 mmc_mread . \ open for multiread
- +mmc
- 0 ?do
- 800 1 do \ 1MB
- 200 0 mmc_(read) \ 512B
- drop
- loop
- i .
- loop 0 .
- mmc_rstop drop ;
-
-
-: mmc_tstread ( n -- ) \ read n x 1MB
- 0 .
- 200 0 0 mmc_read .
- 0 ?do
- 800 1 do \ 1MB
- 200 0 0 mmc_read \ 512B
- drop
- loop
- i .
- loop 0 . ;
-
-
-\ sptx Stop transmit
-
diff --git a/amforth-6.5/avr8/lib/hardware/mpc485.frt b/amforth-6.5/avr8/lib/hardware/mpc485.frt
deleted file mode 100644
index 811b9b3..0000000
--- a/amforth-6.5/avr8/lib/hardware/mpc485.frt
+++ /dev/null
@@ -1,156 +0,0 @@
-\ Multi-processor communication RS485 - Lubos Pekny, www.forth.cz
-\ Library for amforth 3.0, mFC modification
-
-\ V.1.0, 30.01.2009, tested on atmega32, amforth30mFC10.zip
-\ - used PD.7 for switch RX/TX RS485
-
-hex
-
-forth
-<bit> definitions \ into vocabulary <bit>
-
-\ usart i/o atmega32
-32 constant PORTD
-2B constant UCSRA
-2A constant UCSRB
-40 constant UCSRC
-
-forth
-<mpc> definitions \ into vocabulary <mpc>
-
-06 constant ACK
-15 constant NAK
-
- \ wait for tx complete, rx ready
-: txc ( -- )
- <bit>
- begin PORTD @ 80 and 0= until ; \ wait for PD.7=0
-
-
- \ initialize multi-processor communication 7-bit
- \ modul is waiting for address, b7=1
-: +mpc7 ( -- )
- <bit>
- txc \ wait for tx complete
- UCSRA c@ 01 or UCSRA c! \ MPCM=1, multiprocessor
- 8C UCSRC c! ; \ UCSZ=10, no parity, 2 Stopbits
-
-
- \ initialize no MPC communication 8-bit
- \ modul receive/transmit 8-bit data, b7=0
-: -mpc7 ( -- )
- <bit>
- UCSRA c@ FE and UCSRA c! \ MPCM=0, no multiprocessor
- 86 UCSRC c! ; \ UCSZ=11, no parity, 1 Stopbit
-
-
- \ write ID to mpc_ID and eeprom 000C
-: mpc_ID! ( x -- )
- dup 12 e! \ 16b to $0012:0013
- mpc_ID c! ; \ 8b ID to RAM
-
-
- \ send buffer+CR+crc if enabled
- \ if n=0 then send CR only
-: mpc_sendbuf ( addr n -- )
- dup 0= \ n=0?
- if
- drop drop 0D tx0 exit
- then
- begin
- over over 0 \ -- addr n addr n 0
- do
- dup i + c@ tx0 \ send buffer
- loop over \ -- addr n addr n
- 0D tx0 \ send CR
- crc \ -- c1 c2 c3 c4 flag
- if
- 4 0 do tx0 loop \ send crc4-1
- rx0 \ wait for ack/nak
- else
- ACK
- then
- ACK =
- until drop drop ; \ ACK or crc disabled
-
-
- \ send ID, slave initialized for communication
-: mpc_call ( c -- ) \ ID
- 0 tx0 \ delay
- 80 or tx0 \ set 7.bit+ID, for slave
- +mpc7 ; \ modul off, wait for ID
-
-
- \ send command line for ID.slave
-: mpc_line ( c -- ) \ ID
- mpc_call \ ID.slave
- tib >in @ \ -- addr offs
- swap over + \ -- offs addr+
- #tib @ rot - \ -- addr+ n
- -mpc7
- mpc_sendbuf
- 0 #tib ! ; \ stop interpret
-
-
- \ terminal-char, text commands for slave
- \ send char, until ESC
-: mpc_termc ( -- )
- begin
- rx0?
- if rx0 emit then \ answer
- key?
- if
- key dup tx0 \ send char
- 1B =
- else
- 0
- then
- until ; \ until ESC pressed
-
-
-: ~end +mpc7 ;
-: ~call mpc_call ;
-: ~line mpc_line ;
-: ~id mpc_ID c@ ;
-
-
- \ init mpc after restart, $14.7=1 then slave
-: appl_mpc ( -- )
- applturnkey \ init vocabulary, ID, echo, antic
- 14 e@ 80 and \ default echo b7=1 then slave, wait
- if +mpc7 then ; \ ~end
-
-' appl_mpc 0A e! \ write appl_mpc to eeprom APPLTURNKEY
-
-\ echo c@ 80 or 14 e! \ set slave after restart
-\ echo c@ 7F and 14 e! \ set master, no wait
-
-\ ditx Disable transmit
-
-\ ----- Test -----
-\ master: PC, 8-bits data, bit 7 cleared
-\ two slaves: ID=2, ID=5
-\ slave ID5: 4 3 + 5
-\ slave ID2: +
-\ result: C
-\ +antic ~end modules are waiting
-\ alt+0133 send 128+5, select slave ID5
-\ !! wait line by line
-\ Forfiter: TestOK=Off, CRdelay=1000 or TestOK=On, F8-step by step
-\ if loop created then try backspace, enter or +crc ~end from editor
-
-~id . \ 5, view selected slave
-2 ~call \ switch to slave ID2
-~id . \ 2, this run on slave ID2
-5 ~line 4 3 + . cr ~end \ send line from slave ID2 to ID5
- \ "5 ~line" run on slave ID2
- \ "4 3 + . cr ~end" run on slave ID5
- \ 7, store to slave ID2 TOS
-5 ~line ~id . cr ~end \ " ~id . cr ~end" run on slave ID5
- \ 5, store to slave ID2 TOS
-+ . \ C, run on slave ID2
-5 ~call \ switch to slave ID5, run on slave ID2
-~id . \ 5, run on slave ID5
-
-\ entx Enable transmit
-\ end of file
diff --git a/amforth-6.5/avr8/lib/hardware/spi.frt b/amforth-6.5/avr8/lib/hardware/spi.frt
deleted file mode 100644
index 49dbd19..0000000
--- a/amforth-6.5/avr8/lib/hardware/spi.frt
+++ /dev/null
@@ -1,110 +0,0 @@
-\ SPI routines
-
-\ requires: 2rvalue (with further deps)
-\ bitnames
-
-#require 2rvalue.frt
-#require bitnames.frt
-
-\ definitions from application, matching the
-\ SPI hardware pins
-\ PORTB 1 portpin: spi.clk
-\ PORTB 2 portpin: spi.mosi
-\ PORTB 3 portpin: spi.miso
-
-\ usage
-
-\ specific slave select pin
-\ PORTX PINY portpin: appl.ss_line
-\ appl.ss_line to spi.ss
-
-0. 2rvalue spi.ss
-
-\ update spi.ss to the actual setup
-\ +spi -- turn on SPI module, sets up the pins as well
-\ spi.modeX spi.setmode -- switch clock polarity/clock phase
-\ spi.f/X spi.setspeed -- select spi clock rate relative to f_cpu
-\ +spi.2x -- double speed
-\ -spi.2x -- normal speed
-\ -spi -- turn off SPI
-\
-
-\ following definitions are the same for all atmegas
-
-SPSR 0 portpin: spi.2x
-
-SPCR 6 portpin: spi.enable
-SPCR 5 portpin: spi.dord
-SPCR 4 portpin: spi.master
-SPCR %00001100 bitmask: spi.mode
-SPCR %00000011 bitmask: spi.speed
-
-$0 constant spi.mode0 \ sample rising/--
-$4 constant spi.mode1 \ --/sample falling
-$8 constant spi.mode2 \ sample falling/--
-$c constant spi.mode3 \ --/sample rising
-
-0 constant spi.f/4
-1 constant spi.f/16
-2 constant spi.f/64
-3 constant spi.f/128
-
-: +spi
- \ Slave select *must* be *always* at a controlled level when SPI is activated.
- \ Changing a pin into output mode change its level to low. that makes a SPI think
- \ a communication has started which is not the case when this word is called.
- spi.ss high \ deselect slave
- spi.ss pin_output \ possibly short low pulse
- spi.ss high \
-
- \ now its save to turn on the SPI module
- spi.master high
- spi.enable high
-
- \ since spi.ss is HIGH, nobody will be confused
- spi.clk pin_output
- spi.mosi pin_output
- \ miso is controlled by SPI module internally
-;
-
-: -spi 0 SPCR c! ;
-
-\ check SPI device datasheet for mode settings
-: spi.setmode ( spi-mode -- )
- spi.mode pin!
-;
-
-\ speed relative to f_cpu, constants see above
-: spi.setspeed ( spi.speed -- )
- spi.speed pin!
-;
-
-\ double speed mode
-: +spi2x
- spi.2x high
-;
-
-
-: -spi2x
- spi.2x low
-;
-
-\ send a byte, ignore recieved byte
-: c!spi ( c -- )
- c!@spi drop
-;
-
- \ receive a byte, send a dummy one
-: c@spi ( -- c)
- 0 c!@spi
-;
-
-\ send a cell, check data order for MSB/LSB
-\ untested so far
-: !@spi
- dup >< ( -- low high )
- spi.dord is_high? if swap then \ LSB first
- c!@spi swap c!@spi
- spi.dord is_low? if swap then \ MSB was first
- >< or \ upper nibble is set to 0 automatically
-;
diff --git a/amforth-6.5/avr8/lib/hardware/timer0.frt b/amforth-6.5/avr8/lib/hardware/timer0.frt
deleted file mode 100644
index 29670e6..0000000
--- a/amforth-6.5/avr8/lib/hardware/timer0.frt
+++ /dev/null
@@ -1,43 +0,0 @@
-\ TIMER_0 example
-\
-\ requires
-\ in application master file
-\ .set WANT_TIMER_COUNTER_0 = 1
-\ from device.frt
-\ TIMER0_OVFAddr
-\ provides
-\ timer0.tick -- increasing ticker
-\
-\ older mcu's may need
-TCCR0 constant TCCR0B
-TIMSK constant TIMSK0
-
-variable timer0.tick
-
-: timer0.isr
- 1 timer0.tick +!
-;
-
-\ preload for overflow interrupt every 1ms
-\ preload = 256 - (f_cpu / (prescaler * 1000))
-
-: timer0.preload
- f_cpu #1000 um/mod nip 64 / 256 - negate
-;
-
-: timer0.init ( -- )
- timer0.preload TCNT0 c!
- 0 timer0.tick !
- ['] timer0.isr TIMER0_OVFAddr int!
-;
-
-: timer0.start
- timer0.init
- %00000011 TCCR0B c! \ prescaler 64
- %00000001 TIMSK0 c! \ enable overflow interrupt
-;
-
-: timer0.stop
- %00000000 TCCR0B c! \ stop timer
- %00000000 TIMSK0 c! \ stop interrupt
-;
diff --git a/amforth-6.5/avr8/lib/hardware/timer1.frt b/amforth-6.5/avr8/lib/hardware/timer1.frt
deleted file mode 100644
index 7ab9061..0000000
--- a/amforth-6.5/avr8/lib/hardware/timer1.frt
+++ /dev/null
@@ -1,44 +0,0 @@
-\ TIMER_1 example
-\
-\ requires
-\ in application master file
-\ .set WANT_TIMER_COUNTER_1 = 1
-\ from device.frt
-\ TIMER1_OVFAddr
-\ provides
-\ timer1.tick -- increasing ticker
-\
-\ older mcu's may need
-\ TCCR1 constant TCCR1B
-\ TIMSK constant TIMSK1
-
-variable timer1.tick
-
-: timer1.isr
- 1 timer1.tick +!
-;
-
-\ preload for overflow interrupt every 1 ms
-\ preload = 65536 - (f_cpu / (prescaler * 1000))
-
-: timer1.preload
- f_cpu #1000 um/mod nip 8 / negate
-;
-
-: timer1.init ( -- )
- timer1.preload TCNT1 !
- 0 timer1.tick !
- ['] timer1.isr TIMER1_OVFAddr int!
-;
-
-: timer1.start
- timer1.init
- 0 timer1.tick !
- %00000010 TCCR1B c! \ prescaler 8
- %00000001 TIMSK1 c! \ enable overflow interrupt
-;
-
-: timer1.stop
- %00000000 TCCR1B c! \ stop timer
- %00000000 TIMSK1 c! \ stop interrupt
-;
diff --git a/amforth-6.5/avr8/lib/hardware/timer2.frt b/amforth-6.5/avr8/lib/hardware/timer2.frt
deleted file mode 100644
index ed0472f..0000000
--- a/amforth-6.5/avr8/lib/hardware/timer2.frt
+++ /dev/null
@@ -1,42 +0,0 @@
-\ TIMER_2 example
-\ uses an external 32kHz clock quartz
-\ 32kHz / 256 => 128 ticks per second
-\ 7.8125 ms per tick (gets approximated)
-\ --> less accurate than the other timers, but...
-\
-\ 16 ticks are 125ms
-\ 125 = 15*8+5: 15x 8-tock and a short step
-\ or 125 = 15*7+20:15x 7-tock and a huge step
-\ -> we choose the 1st variant
-\ provides
-\ timer2.tick -- increasing ticker
-\
-
-variable timer2.tick
-variable timer2.tock \ used internally
-
-: timer2.isr ( -- )
- timer2.tock @ 1+ 15 = if
- 0 timer2.tock !
- 5 timer2.tick +!
- else
- 8 timer2.tick +!
- 1 timer2.tock +!
- then
-;
-
-: timer2.init ( -- )
- 1 TCCR2 c!
- 8 ASSR c!
- ['] timer2.isr TIMER2_OVFAddr int!
-;
-
-: timer2.start
- 0 timer2.tick !
- 0 timer2.tock !
- TIMSK c@ $40 or TIMSK c! ( enable timer2 interupt )
-;
-
-: timer2.stop
- TIMSK c@ [ $40 invert ] literal and TIMSK c! \ stop timer2 interrupt
-;
diff --git a/amforth-6.5/avr8/lib/imove.frt b/amforth-6.5/avr8/lib/imove.frt
deleted file mode 100644
index bf33697..0000000
--- a/amforth-6.5/avr8/lib/imove.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-\ copy a string from flash to RAM
-\
-\ i->d on the msp430, and the same stack as cmove
-\
-: imove ( i-addr len ram -- )
- rot rot dup 1 and >r \ ( ram i-addr len ) ( r: odd )
- 2/ over + dup >r \ ( ram i-addr i-addr' ) ( r: odd i-addr' )
- swap \ ( ram i-addr' i-addr )
- ?do i @i over ! cell+ loop \ ( ram' )
- r> r> \ ( ram' i-addr' odd )
- if @i swap c! else 2drop then
-;
diff --git a/amforth-6.5/avr8/lib/portio.frt b/amforth-6.5/avr8/lib/portio.frt
deleted file mode 100644
index 4d40c46..0000000
--- a/amforth-6.5/avr8/lib/portio.frt
+++ /dev/null
@@ -1,46 +0,0 @@
-\ Only for PORTx bits,
-\ because address of DDRx is one less than address of PORTx.
-
-\ Set DDRx so its corresponding pin is output.
-: pin_output ( pinmask portadr -- )
- 1- bm:high
-;
-
-\ Set DDRx so its corresponding pin is input.
-: pin_input ( pinmask portadr -- )
- 1- bm:low
-;
-
-\ PINx is two less of PORTx
-: pin_high? ( pinmask portaddr -- f)
- 1- 1- c@ and
-;
-
-: pin_low? ( pinmask portaddr -- f)
- 1- 1- c@ invert and
-;
-
-\ read the pins masked as input
-: pin@ ( pinmask portaddr -- c )
- 1- 1- c@ and
-;
-
-\ toggle the pin
-: toggle ( pinmask portaddr -- )
- 2dup bm:high? if
- bm:low
- else
- bm:high
- then
-;
-
-\ disable the pull up resistor
-: pin_pullup_off ( pinmask portaddr -- )
- 2dup pin_input low
-;
-
-
-\ enable the pull up resistor
-: pin_pullup_on ( pinmask portaddr -- )
- 2dup pin_input high
-;
diff --git a/amforth-6.5/avr8/lib/ram.frt b/amforth-6.5/avr8/lib/ram.frt
deleted file mode 100644
index fb37ab7..0000000
--- a/amforth-6.5/avr8/lib/ram.frt
+++ /dev/null
@@ -1,225 +0,0 @@
-\ RAM - 512kB sram memory, Lubos Pekny, www.forth.cz
-\ Library for amforth 3.0, mFC modification
-\ ram_init, ram_addr, ram_addr+, ram_read, ram_write, ram_off
-\ ram_c@, ram_c!, ram_c@+, ram_c!+
-
-\ V.1.1, 28.07.2009, asm optimalization, amforth30mFC12.zip
-\ V.1.0, 20.03.2009, tested on atmega32, amforth30mFC11.zip
-\ - used bitnames.frt
-\ - used PA0-7, PB0-2, PC2-7
-
-hex
-
-forth
-<bit> definitions \ into vocabulary <bit>
-
-3B constant PORTA \ ATmega32
-\ 38 constant PORTB
-\ 35 constant PORTC
-
-
-forth
-<ram> definitions \ into vocabulary <ram>
-
-<bit>
-PORTC 02 portpin: ram_WRL \ PC.2 set low 8b addr
-PORTC 03 portpin: ram_WRH \ PC.3 set high 8b addr
-PORTC 04 portpin: ram_INC \ PC.4 increment addr
-PORTC 05 portpin: ram_WR \ PC.5 write to sram
-PORTC 06 portpin: ram_OE \ PC.6 output enable
-PORTC 07 portpin: ram_CS \ PC.7 chip select
-PORTA constant ram_DATA \ PA data 8b, in/out
-: ram_PAGE <bit> 07 PORTB ; \ PB.0-2 out
-: ram_CTRL <bit> FC PORTC ; \ PC.2-7 out
-
- \ define macros
-: ram_din,
- assembler
- R16 0 ldi,
- ram_DATA 1- R16 sts, ;
-
-: ram_dout,
- assembler
- R16 FF ldi,
- ram_DATA 1- R16 sts, ;
-
-
- \ data port direction - input
-code ram_din ( -- )
- ram_din,
-end-code
-
-
- \ data port direction - output
-code ram_dout ( -- )
- ram_dout,
-end-code
-
-
- \ set I/O
-: ram_init ( -- )
- <bit>
- -jtag \ port C i/o
- ram_din \ port in
- ram_PAGE pin_output \ out
- ram_CTRL pin_output \ out
- ram_PAGE high \ last page
- ram_CTRL high ; \ sram disabled
-
-
- \ set low 8b addr
-code ram_addrl ( c -- )
- ram_DATA TOSL sts, \ data
- loadtos, \ delete c
- <bit>
- ram_WRL low,
- ram_WRL high, \ set counter
-end-code
-
-
- \ set high 8b addr
-code ram_addrh ( c -- )
- ram_DATA TOSL sts, \ data
- loadtos, \ delete c
- <bit>
- ram_WRH low,
- ram_WRH high, \ set counter
-end-code
-
-
- \ set addr, sram off, port input
-: ram_addr ( addr page -- )
- <bit>
- ram_CS high \ sram disabled
- ram_PAGE pin! \ set page
- ram_dout \ port out
- dup ram_addrl \ addr low
- >< ram_addrh \ addr high
- ram_din ; \ port in
-
-
- \ increment addr
-code ram_addr+ ( -- )
- <bit>
- ram_INC low,
- ram_INC high, \ increment addr
-end-code
-
-
- \ set pins for read from sram
-code ram_read ( -- )
- <bit>
- ram_din, \ port in
- ram_OE low,
- ram_CS low, \ out and chip enabled
-end-code
-
-
- \ set pins for write to sram
-code ram_write ( -- )
- <bit>
- ram_OE high,
- ram_CS low, \ chip enabled
- ram_dout, \ port out
-end-code
-
-
- \ set pins for disable sram
-code ram_off ( -- )
- <bit>
- ram_CS high,
- ram_OE high, \ sram disabled
- ram_din, \ port in
-end-code
-
-
- \ write pulse
-code ram_clk ( -- )
- <bit>
- ram_WR low,
- ram_WR high, \ write to sram
-end-code
-
-
- \ read from sram
-: ram_c@ ( -- c )
- ram_read \ sram enabled, out
- [ ram_DATA 1- 1- ] \ convert to literal
- literal c@ \ read byte from sram
- ram_off ;
-
-
- \ write to sram
-: ram_c! ( c -- )
- ram_write \ sram enabled, in
- ram_DATA c! \ write byte to sram
- ram_clk \ write pulse
- ram_off ;
-
-
- \ read from sram, increment addr, page 64kB
- \ use ram_read ram_c@+ .... ram_off
-code ram_c@+ ( -- c )
- \ ram_DATA 1- 1- c@
- savetos, \ add item
- TOSL ram_DATA 1- 1- lds, \ port -> tosl
- TOSH 0 ldi, \ 0 -> tosh
-
- \ ram_addr+
- ram_INC <bit> ma2pbi \ mask addr -- port bit
- over over \ 2dup
- assembler
- cbi, nop, sbi, \ pulse INC
-end-code
-
-
- \ write to sram, increment addr, page 64kB
- \ use ram_write ram_c!+ .... ram_off
-code ram_c!+ ( c -- )
- \ ram_DATA c!
- ram_DATA TOSL sts, \ c!, tosl -> port
- loadtos, \ delete item
-
- \ ram_clk
- ram_WR <bit> ma2pbi \ mask addr -- port bit
- over over \ 2dup
- assembler
- cbi, nop, sbi, \ pulse WR
-
- \ ram_addr+
- ram_INC <bit> ma2pbi \ mask addr -- port bit
- over over \ 2dup
- assembler
- cbi, nop, sbi, \ pulse INC
-end-code
-
-
-\ sptx Stop transmit
-
-\ ----- Test -----
-forth
-<ram>
-ram_init
-13 3 0 ram_addr ram_c! \ 13 write at addr 0003, page 0
-14 4 0 ram_addr ram_c! \ 14 write at addr 0004, page 0
-
-0 0 ram_addr \ set addr to 0:0000
-ram_write \ mode write
-31 ram_c!+
-32 ram_c!+
-33 ram_c!+ \ write 31,32,33 from addr 0:0000
-
-0 0 ram_addr \ set addr to 0:0000
-ram_read \ mode read
-ram_c@+ .
-ram_c@+ .
-ram_c@+ . \ read 31,32,33 from addr 0:0000
-ram_c@+ .
-ram_c@+ . \ read 13,14
-ram_off
-
-4 0 ram_addr ram_c@ . \ read 14 at addr 0:0004
-2 0 ram_addr ram_c@ . \ read 33 at addr 0:0002
-3 0 ram_addr ram_c@ . \ read 13 at addr 0:0003
-
-\ end of file
diff --git a/amforth-6.5/avr8/lib/recognizer-arch.frt b/amforth-6.5/avr8/lib/recognizer-arch.frt
deleted file mode 100644
index 9f8cb52..0000000
--- a/amforth-6.5/avr8/lib/recognizer-arch.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-\ platform specific core
-
-\ #require eallot.frt
-
-: recognizer ( size -- stack-id )
- \ allocate size + 1 cells in config space (eeprom, info flash)
- 1+ cells ehere swap eallot dup 0 !e
-;
diff --git a/amforth-6.5/avr8/lib/run-hayes.frt b/amforth-6.5/avr8/lib/run-hayes.frt
deleted file mode 100644
index 20442a5..0000000
--- a/amforth-6.5/avr8/lib/run-hayes.frt
+++ /dev/null
@@ -1,28 +0,0 @@
-\
-\ process this file with amforth-upload.py and
-\ the proper setting of $AMFORTH_LIB (basedir of
-\ you amforth file tree)
-\ WIN (untested, DOS Box)
-\ cd c:\amforth-x.y
-\ set AMFORTH_LIB=c:\amforth-x.y
-\ python tools\amforth-upload.py -t com1: examples\run-hayes.frt
-\ UNIX / MAC (Terminal)
-\ cd $HOME/amforth-x.y
-\ export AMFORTH_LIB=$HOME/amforth-x.y
-\ tools/amforth-upload.py -t /dev/ttyUSB0 examples/run-hayes.frt
-\ enjoy!
-\
-\ it is meant to be run on a newly flashed
-\ controller, e.g. all the dict_* are included
-\
-
-#require is.frt
-
-\ include all sources
-#include core.frt
-#include double.frt
-#include marker.frt
-#include tester-amforth.frt
-\ and finally run all the tests
-
-#include core.fr
diff --git a/amforth-6.5/avr8/macros.asm b/amforth-6.5/avr8/macros.asm
deleted file mode 100644
index 6ee20a5..0000000
--- a/amforth-6.5/avr8/macros.asm
+++ /dev/null
@@ -1,158 +0,0 @@
-; conditional assembly needs preparation
-.set DICT_COMPILER2 = 0 ;
-.set cpu_msp430 = 0
-.set cpu_avr8 = 1
-
-.include "user.inc"
-
- .def zerol = r2
- .def zeroh = r3
- .def upl = r4
- .def uph = r5
-
- .def al = r6
- .def ah = r7
- .def bl = r8
- .def bh = r9
-
-; internal
- .def mcu_boot = r10
- .def isrflag = r11
-
- .def temp4 = r14
- .def temp5 = r15
-
- .def temp0 = r16
- .def temp1 = r17
- .def temp2 = r18
- .def temp3 = r19
-
- .def temp6 = r20
- .def temp7 = r21
-
- .def tosl = r24
- .def tosh = r25
-
- .def wl = r22
- .def wh = r23
-
-.macro loadtos
- ld tosl, Y+
- ld tosh, Y+
-.endmacro
-
-.macro savetos
- st -Y, tosh
- st -Y, tosl
-.endmacro
-
-.macro in_
-.if (@1 < $40)
- in @0,@1
-.else
- lds @0,@1
-.endif
-.endmacro
-
-.macro out_
-.if (@0 < $40)
- out @0,@1
-.else
- sts @0,@1
-.endif
-.endmacro
-
-.macro sbi_
-.if (@0 < $40)
- sbi @0,@1
-.else
- in_ @2,@0
- ori @2,exp2(@1)
- out_ @0,@2
-.endif
-.endmacro
-
-.macro cbi_
-.if (@0 < $40)
- cbi @0,@1
-.else
- in_ @2,@0
- andi @2,~(exp2(@1))
- out_ @0,@2
-.endif
-.endmacro
-
-.macro jmp_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- jmp @0
- .else
- rjmp @0
- .endif
- .else
- jmp @0
- .endif
-.endmacro
-.macro call_
- ; a more flexible macro
- .ifdef @0
- .if (@0-pc > 2040) || (pc-@0>2040)
- call @0
- .else
- rcall @0
- .endif
- .else
- call @0
- .endif
-.endmacro
-
-; F_CPU
-; µsec 16000000 14745600 8000000 1000000
-; 1 16 14,74 8 1
-; 10 160 147,45 80 10
-; 100 1600 1474,56 800 100
-; 1000 16000 14745,6 8000 1000
-;
-; cycles = µsec * f_cpu / 1e6
-; n_loops=cycles/5
-;
-; cycles already used will be subtracted from the delay
-; the waittime resolution is 1 cycle (delay from exact to +1 cycle)
-; the maximum delay at 20MHz (50ns/clock) is 38350ns
-; waitcount register must specify an immediate register
-;
-; busy waits a specfied amount of microseconds
-.macro delay
- .set cycles = ( ( @0 * F_CPU ) / 1000000 )
- .if (cycles > ( 256 * 255 * 4 + 2))
- .error "MACRO delay - too many cycles to burn"
- .else
- .if (cycles > 6)
- .set loop_cycles = (cycles / 4)
- ldi zl,low(loop_cycles)
- ldi zh,high(loop_cycles)
- sbiw Z, 1
- brne pc-1
- .set cycles = (cycles - (loop_cycles * 4))
- .endif
- .if (cycles > 0)
- .if (cycles & 4)
- rjmp pc+1
- rjmp pc+1
- .endif
- .if (cycles & 2)
- rjmp pc+1
- .endif
- .if (cycles & 1)
- nop
- .endif
- .endif
- .endif
-.endmacro
-
-; portability macros, they come from the msp430 branches
-
-.macro DEST
- .dw @0
-.endm
diff --git a/amforth-6.5/avr8/preamble.inc b/amforth-6.5/avr8/preamble.inc
deleted file mode 100644
index 8f141dc..0000000
--- a/amforth-6.5/avr8/preamble.inc
+++ /dev/null
@@ -1,50 +0,0 @@
-; generic macros and register definitions
-.include "macros.asm"
-
-; controller specific file selected via include
-; directory definition when calling the assembler (-I)
-.include "device.asm"
-
-; some defaults, change them in your application master file
-; see template.asm for an example
-
-; enabling Interrupts, disabling them affects
-; other settings as well.
-.set WANT_INTERRUPTS = 1
-
-; count the number of interrupts individually.
-; requires a lot of RAM (one byte per interrupt)
-; disabled by default.
-.set WANT_INTERRUPT_COUNTERS = 0
-
-; receiving is asynchronously, so an interrupt queue is useful.
-.set WANT_ISR_RX = 1
-
-; case insensitve dictionary lookup.
-.set WANT_IGNORECASE = 0
-
-; map all memories to one address space. Details in the
-; technical guide
-.set WANT_UNIFIED = 0
-
-; terminal input buffer
-.set TIB_SIZE = 90 ; ANS94 needs at least 80 characters per line
-
-; USER variables *in addition* to system ones
-.set APPUSERSIZE = 10 ; size of application specific user area in bytes
-
-; addresses of various data segments
-.set rstackstart = RAMEND ; start address of return stack, grows downward
-.set stackstart = RAMEND - 80 ; start address of data stack, grows downward
-; change only if you know what to you do
-.set NUMWORDLISTS = 8 ; number of word lists in the searh order, at least 8
-.set NUMRECOGNIZERS = 4 ; total number of recognizers, two are always used.
-
-; 10 per mille (1 per cent) is ok.
-.set BAUD = 38400
-.set BAUD_MAXERROR = 10
-
-; Dictionary setup
-.set VE_HEAD = $0000
-.set VE_ENVHEAD = $0000
-.set AMFORTH_RO_SEG = NRWW_START_ADDR \ No newline at end of file
diff --git a/amforth-6.5/avr8/tools/99-avr.rules b/amforth-6.5/avr8/tools/99-avr.rules
deleted file mode 100644
index 4dc9da4..0000000
--- a/amforth-6.5/avr8/tools/99-avr.rules
+++ /dev/null
@@ -1,10 +0,0 @@
-
-# Atmel Corp.JTAG ICE mkII
-ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2103", MODE="660", GROUP="plugdev"
-
-# Atmel Corp. AVRISP mkII
-ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2104", MODE="660", GROUP="plugdev"
-
-# Atmel Corp. Dragon
-ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2107", MODE="660", GROUP="plugdev"
-
diff --git a/amforth-6.5/avr8/user.inc b/amforth-6.5/avr8/user.inc
deleted file mode 100644
index ff7bbcd..0000000
--- a/amforth-6.5/avr8/user.inc
+++ /dev/null
@@ -1,34 +0,0 @@
-; Layout of the user area
-;
-
-; used by the multitasker
-.set USER_STATE = 0
-.set USER_FOLLOWER = 2
-
-; stackpointer, used by mulitasker
-.set USER_RP = 4
-.set USER_SP0 = 6
-.set USER_SP = 8
-
-; excpection handling
-.set USER_HANDLER = 10
-
-; numeric IO
-.set USER_BASE = 12
-
-; character IO
-.set USER_EMIT = 14
-.set USER_EMITQ = 16
-.set USER_KEY = 18
-.set USER_KEYQ = 20
-
-.set USER_SOURCE = 22
-.set USER_TO_IN = 24
-.set USER_REFILL = 26
-
-.set USER_P_OK = 28
-.set USER_P_ERR = 30
-.set USER_P_RDY = 32
-
-.set SYSUSERSIZE = 34
-;
diff --git a/amforth-6.5/avr8/words/1minus.asm b/amforth-6.5/avr8/words/1minus.asm
deleted file mode 100644
index ca70fed..0000000
--- a/amforth-6.5/avr8/words/1minus.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; (S: n1 -- n2 )
-; Arithmetics
-; optimized decrement
-VE_1MINUS:
- .dw $ff02
- .db "1-"
- .dw VE_HEAD
- .set VE_HEAD = VE_1MINUS
-XT_1MINUS:
- .dw PFA_1MINUS
-PFA_1MINUS:
- sbiw tosl, 1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/1ms.asm b/amforth-6.5/avr8/words/1ms.asm
deleted file mode 100644
index f23951d..0000000
--- a/amforth-6.5/avr8/words/1ms.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( -- )
-; Time
-; busy waits (almost) exactly 1 millisecond
-VE_1MS:
- .dw $ff03
- .db "1ms",0
- .dw VE_HEAD
- .set VE_HEAD = VE_1MS
-XT_1MS:
- .dw PFA_1MS
-PFA_1MS:
- delay 1000
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/1plus.asm b/amforth-6.5/avr8/words/1plus.asm
deleted file mode 100644
index ffaaec2..0000000
--- a/amforth-6.5/avr8/words/1plus.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( n1|u1 -- n2|u2 )
-; Arithmetics
-; optimized increment
-VE_1PLUS:
- .dw $ff02
- .db "1+"
- .dw VE_HEAD
- .set VE_HEAD = VE_1PLUS
-XT_1PLUS:
- .dw PFA_1PLUS
-PFA_1PLUS:
- adiw tosl,1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/2r_fetch.asm b/amforth-6.5/avr8/words/2r_fetch.asm
deleted file mode 100644
index 8d0060b..0000000
--- a/amforth-6.5/avr8/words/2r_fetch.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- d) (R: d -- d )
-; Stack
-; fetch content of TOR
-VE_2R_FETCH:
- .dw $ff03
- .db "2r@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_2R_FETCH
-XT_2R_FETCH:
- .dw PFA_2R_FETCH
-PFA_2R_FETCH:
- savetos
- pop zl
- pop zh
- pop tosl
- pop tosh
- push tosh
- push tosl
- push zh
- push zl
- savetos
- movw tosl, zl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/2r_from.asm b/amforth-6.5/avr8/words/2r_from.asm
deleted file mode 100644
index ffb5a34..0000000
--- a/amforth-6.5/avr8/words/2r_from.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- x1 x2 ) (R: x1 x2 --)
-; Stack
-; move DTOR to TOS
-VE_2R_FROM:
- .dw $ff03
- .db "2r>",0
- .dw VE_HEAD
- .set VE_HEAD = VE_2R_FROM
-XT_2R_FROM:
- .dw PFA_2R_FROM
-PFA_2R_FROM:
- savetos
- pop zl
- pop zh
- pop tosl
- pop tosh
- savetos
- movw tosl, zl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/2slash.asm b/amforth-6.5/avr8/words/2slash.asm
deleted file mode 100644
index 5d4ada2..0000000
--- a/amforth-6.5/avr8/words/2slash.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n1 -- n2 )
-; Arithmetics
-; arithmetic shift right
-VE_2SLASH:
- .dw $ff02
- .db "2/"
- .dw VE_HEAD
- .set VE_HEAD = VE_2SLASH
-XT_2SLASH:
- .dw PFA_2SLASH
-PFA_2SLASH:
- asr tosh
- ror tosl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/2spirw.asm b/amforth-6.5/avr8/words/2spirw.asm
deleted file mode 100644
index a7064da..0000000
--- a/amforth-6.5/avr8/words/2spirw.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( n1 -- n2 )
-; MCU
-; SPI exchange of 2 bytes, high byte first
-VE_2SPIRW:
- .dw $ff05
- .db "!@spi",0
- .dw VE_HEAD
- .set VE_HEAD = VE_2SPIRW
-XT_2SPIRW:
- .dw PFA_2SPIRW
-PFA_2SPIRW:
- push tosl
- mov tosl, tosh
- call_ do_spirw
- mov tosh, tosl
- pop tosl
- call_ do_spirw
- jmp_ DO_NEXT
-
diff --git a/amforth-6.5/avr8/words/2star.asm b/amforth-6.5/avr8/words/2star.asm
deleted file mode 100644
index ef307e3..0000000
--- a/amforth-6.5/avr8/words/2star.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n1 -- n2 )
-; Arithmetics
-; arithmetic shift left, filling with zero
-VE_2STAR:
- .dw $ff02
- .db "2*"
- .dw VE_HEAD
- .set VE_HEAD = VE_2STAR
-XT_2STAR:
- .dw PFA_2STAR
-PFA_2STAR:
- lsl tosl
- rol tosh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/2to_r.asm b/amforth-6.5/avr8/words/2to_r.asm
deleted file mode 100644
index 0e70f18..0000000
--- a/amforth-6.5/avr8/words/2to_r.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( x1 x2 -- ) (R: -- x1 x2)
-; Stack
-; move DTOS to TOR
-VE_2TO_R:
- .dw $ff03
- .db "2>r",0
- .dw VE_HEAD
- .set VE_HEAD = VE_2TO_R
-XT_2TO_R:
- .dw PFA_2TO_R
-PFA_2TO_R:
- movw zl, tosl
- loadtos
- push tosh
- push tosl
- push zh
- push zl
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/allot.asm b/amforth-6.5/avr8/words/allot.asm
deleted file mode 100644
index 0356fa4..0000000
--- a/amforth-6.5/avr8/words/allot.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( n -- )
-; System
-; allocate or release memory in RAM
-VE_ALLOT:
- .dw $ff05
- .db "allot",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ALLOT
-XT_ALLOT:
- .dw DO_COLON
-PFA_ALLOT:
- .dw XT_HERE
- .dw XT_PLUS
- .dw XT_DOTO
- .dw PFA_HERE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/and.asm b/amforth-6.5/avr8/words/and.asm
deleted file mode 100644
index ed31668..0000000
--- a/amforth-6.5/avr8/words/and.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( n1 n2 -- n3 )
-; Logic
-; bitwise and
-VE_AND:
- .dw $ff03
- .db "and",0
- .dw VE_HEAD
- .set VE_HEAD = VE_AND
-XT_AND:
- .dw PFA_AND
-PFA_AND:
- ld temp0, Y+
- ld temp1, Y+
- and tosl, temp0
- and tosh, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/bm-clear.asm b/amforth-6.5/avr8/words/bm-clear.asm
deleted file mode 100644
index 6c47517..0000000
--- a/amforth-6.5/avr8/words/bm-clear.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( bitmask byte-addr -- )
-; MCU
-; clear bits set in bitmask on byte at addr
-VE_BM_CLEAR:
- .dw $ff08
- .db "bm-clear"
- .dw VE_HEAD
- .set VE_HEAD = VE_BM_CLEAR
-XT_BM_CLEAR:
- .dw PFA_BM_CLEAR
-PFA_BM_CLEAR:
- movw zl, tosl
- loadtos
- com tosl
- ld temp0, Z
- and temp0, tosl
- st Z, temp0
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/bm-set.asm b/amforth-6.5/avr8/words/bm-set.asm
deleted file mode 100644
index 1ba5faa..0000000
--- a/amforth-6.5/avr8/words/bm-set.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( bitmask byte-addr -- )
-; MCU
-; set bits from bitmask on byte at addr
-VE_BM_SET:
- .dw $ff06
- .db "bm-set"
- .dw VE_HEAD
- .set VE_HEAD = VE_BM_SET
-XT_BM_SET:
- .dw PFA_BM_SET
-PFA_BM_SET:
- movw zl, tosl
- loadtos
- ld temp0, Z
- or temp0, tosl
- st Z, temp0
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/bm-toggle.asm b/amforth-6.5/avr8/words/bm-toggle.asm
deleted file mode 100644
index fbbdc21..0000000
--- a/amforth-6.5/avr8/words/bm-toggle.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( bitmask byte-addr -- )
-; MCU
-; toggle bits set in bitmask on byte at addr
-VE_BM_TOGGLE:
- .dw $ff09
- .db "bm-toggle",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BM_TOGGLE
-XT_BM_TOGGLE:
- .dw PFA_BM_TOGGLE
-PFA_BM_TOGGLE:
- movw zl, tosl
- loadtos
- ld temp0, Z
- eor temp0, tosl
- st Z, temp0
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/byteswap.asm b/amforth-6.5/avr8/words/byteswap.asm
deleted file mode 100644
index b49cd2f..0000000
--- a/amforth-6.5/avr8/words/byteswap.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( n1 -- n2 )
-; Arithmetics
-; exchange the bytes of the TOS
-VE_BYTESWAP:
- .dw $ff02
- .db "><"
- .dw VE_HEAD
- .set VE_HEAD = VE_BYTESWAP
-XT_BYTESWAP:
- .dw PFA_BYTESWAP
-PFA_BYTESWAP:
- mov temp0, tosh
- mov tosh, tosl
- mov tosl, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/cas.asm b/amforth-6.5/avr8/words/cas.asm
deleted file mode 100644
index f59ae26..0000000
--- a/amforth-6.5/avr8/words/cas.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-; ( new old addr -- f )
-; Multitasking
-; Atomic Compare and Swap: store new at addr and set f to true if contents of addr is equal to old.
-VE_CAS:
- .dw $ff03
- .db "cas",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CAS
-XT_CAS:
- .dw PFA_CAS
-PFA_CAS:
- movw zl, tosl
- loadtos
- ldd temp0, Z+0
- ldd temp1, Z+1
- cp tosl, temp0
- cpc tosh, temp1
- loadtos
- brne PFA_CAS1
- std Z+0, tosl
- std Z+1, tosh
- ser tosl
- rjmp PFA_CAS2
-PFA_CAS1:
- clr tosl
-PFA_CAS2:
- mov tosh, tosl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/cellplus.asm b/amforth-6.5/avr8/words/cellplus.asm
deleted file mode 100644
index e75de15..0000000
--- a/amforth-6.5/avr8/words/cellplus.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( a-addr1 -- a-addr2 )
-; Arithmetics
-; add the size of an address-unit to a-addr1
-VE_CELLPLUS:
- .dw $ff05
- .db "cell+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CELLPLUS
-XT_CELLPLUS:
- .dw PFA_CELLPLUS
-PFA_CELLPLUS:
- adiw tosl, CELLSIZE
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/cells.asm b/amforth-6.5/avr8/words/cells.asm
deleted file mode 100644
index 2876c2d..0000000
--- a/amforth-6.5/avr8/words/cells.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-; ( n1 -- n2 )
-; Arithmetics
-; n2 is the size in address units of n1 cells
-VE_CELLS:
- .dw $ff05
- .db "cells",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CELLS
-XT_CELLS:
- .dw PFA_2STAR
diff --git a/amforth-6.5/avr8/words/cfetch.asm b/amforth-6.5/avr8/words/cfetch.asm
deleted file mode 100644
index 97ff7dc..0000000
--- a/amforth-6.5/avr8/words/cfetch.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( a-addr - c1 )
-; Memory
-; fetch a single byte from memory mapped locations
-VE_CFETCH:
- .dw $ff02
- .db "c@"
- .dw VE_HEAD
- .set VE_HEAD = VE_CFETCH
-XT_CFETCH:
- .dw PFA_CFETCH
-PFA_CFETCH:
- movw zl, tosl
- clr tosh
- ld tosl, Z
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/cmove.asm b/amforth-6.5/avr8/words/cmove.asm
deleted file mode 100644
index f7a1134..0000000
--- a/amforth-6.5/avr8/words/cmove.asm
+++ /dev/null
@@ -1,30 +0,0 @@
-; (addr-from addr-to n -- )
-; Memory
-; copy data in RAM, from lower to higher addresses
-VE_CMOVE:
- .dw $ff05
- .db "cmove",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE
-XT_CMOVE:
- .dw PFA_CMOVE
-PFA_CMOVE:
- push xh
- push xl
- ld zl, Y+
- ld zh, Y+ ; addr-to
- ld xl, Y+
- ld xh, Y+ ; addr-from
- mov temp0, tosh
- or temp0, tosl
- brbs 1, PFA_CMOVE1
-PFA_CMOVE2:
- ld temp1, X+
- st Z+, temp1
- sbiw tosl, 1
- brbc 1, PFA_CMOVE2
-PFA_CMOVE1:
- pop xl
- pop xh
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/cmove_g.asm b/amforth-6.5/avr8/words/cmove_g.asm
deleted file mode 100644
index 3bcbb4e..0000000
--- a/amforth-6.5/avr8/words/cmove_g.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; (addr-from addr-to n -- )
-; Memory
-; copy data in RAM from higher to lower addresses.
-VE_CMOVE_G:
- .dw $ff06
- .db "cmove>"
- .dw VE_HEAD
- .set VE_HEAD = VE_CMOVE_G
-XT_CMOVE_G:
- .dw PFA_CMOVE_G
-PFA_CMOVE_G:
- push xh
- push xl
- ld zl, Y+
- ld zh, Y+ ; addr-to
- ld xl, Y+
- ld xh, Y+ ; addr-from
- mov temp0, tosh
- or temp0, tosl
- brbs 1, PFA_CMOVE_G1
- add zl, tosl
- adc zh, tosh
- add xl, tosl
- adc xh, tosh
-PFA_CMOVE_G2:
- ld temp1, -X
- st -Z, temp1
- sbiw tosl, 1
- brbc 1, PFA_CMOVE_G2
-PFA_CMOVE_G1:
- pop xl
- pop xh
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/code.asm b/amforth-6.5/avr8/words/code.asm
deleted file mode 100644
index ecbb6d5..0000000
--- a/amforth-6.5/avr8/words/code.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( -- ) (C: cchar -- )
-; Compiler
-; create named entry in the dictionary, XT is the data field
-VE_CODE:
- .dw $ff04
- .db "code"
- .dw VE_HEAD
- .set VE_HEAD = VE_CODE
-XT_CODE:
- .dw DO_COLON
-PFA_CODE:
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_DP
- .dw XT_ICELLPLUS
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/cold.asm b/amforth-6.5/avr8/words/cold.asm
deleted file mode 100644
index 4547f55..0000000
--- a/amforth-6.5/avr8/words/cold.asm
+++ /dev/null
@@ -1,52 +0,0 @@
-; ( i*x -- ) (R: j*y -- )
-; System
-; start up amforth.
-VE_COLD:
- .dw $ff04
- .db "cold"
- .dw VE_HEAD
- .set VE_HEAD = VE_COLD
-XT_COLD:
- .dw PFA_COLD
-PFA_COLD:
- in_ mcu_boot, MCUSR
- clr zerol
- clr zeroh
- clr isrflag
- out_ MCUSR, zerol
- ; clear RAM
- ldi zl, low(ramstart)
- ldi zh, high(ramstart)
-clearloop:
- st Z+, zerol
- cpi zl, low(sram_size+ramstart)
- brne clearloop
- cpi zh, high(sram_size+ramstart)
- brne clearloop
- ; init first user data area
- ; allocate space for User Area
-.dseg
-ram_user1: .byte SYSUSERSIZE + APPUSERSIZE
-.cseg
- ldi zl, low(ram_user1)
- ldi zh, high(ram_user1)
- movw upl, zl
- ; init return stack pointer
- ldi temp0,low(rstackstart)
- out_ SPL,temp0
- std Z+4, temp0
- ldi temp1,high(rstackstart)
- out_ SPH,temp1
- std Z+5, temp1
-
- ; init parameter stack pointer
- ldi yl,low(stackstart)
- std Z+6, yl
- ldi yh,high(stackstart)
- std Z+7, yh
-
- ; load Forth IP with starting word
- ldi XL, low(PFA_WARM)
- ldi XH, high(PFA_WARM)
- ; its a far jump...
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/colon-noname.asm b/amforth-6.5/avr8/words/colon-noname.asm
deleted file mode 100644
index 8c47fb3..0000000
--- a/amforth-6.5/avr8/words/colon-noname.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- xt )
-; Compiler
-; create an unnamed entry in the dictionary, XT is DO_COLON
-VE_COLONNONAME:
- .dw $ff07
- .db ":noname",0
- .dw VE_HEAD
- .set VE_HEAD = VE_COLONNONAME
-XT_COLONNONAME:
- .dw DO_COLON
-PFA_COLONNONAME:
- .dw XT_DP
- .dw XT_DUP
- .dw XT_LATEST
- .dw XT_STORE
-
- .dw XT_COMPILE
- .dw DO_COLON
-
- .dw XT_RBRACKET
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/comma.asm b/amforth-6.5/avr8/words/comma.asm
deleted file mode 100644
index a9a903b..0000000
--- a/amforth-6.5/avr8/words/comma.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( n -- )
-; Dictionary
-; compile 16 bit into flash at DP
-VE_COMMA:
- .dw $ff01
- .db ',',0 ; ,
- .dw VE_HEAD
- .set VE_HEAD = VE_COMMA
-XT_COMMA:
- .dw DO_COLON
-PFA_COMMA:
- .dw XT_DP
- .dw XT_STOREI
- .dw XT_DP
- .dw XT_1PLUS
- .dw XT_DOTO
- .dw PFA_DP
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/compare.asm b/amforth-6.5/avr8/words/compare.asm
deleted file mode 100644
index 0a33f47..0000000
--- a/amforth-6.5/avr8/words/compare.asm
+++ /dev/null
@@ -1,47 +0,0 @@
-; ( r-addr r-len f-addr f-len -- f)
-; String
-; compares two strings in RAM
-VE_COMPARE:
- .dw $ff07
- .db "compare",0
- .dw VE_HEAD
- .set VE_HEAD = VE_COMPARE
-XT_COMPARE:
- .dw PFA_COMPARE
-PFA_COMPARE:
- push xh
- push xl
- movw temp0, tosl
- loadtos
- movw xl, tosl
- loadtos
- movw temp2, tosl
- loadtos
- movw zl, tosl
-PFA_COMPARE_LOOP:
- ld temp4, X+
- ld temp5, Z+
- cp temp4, temp5
- brne PFA_COMPARE_NOTEQUAL
- dec temp0
- breq PFA_COMPARE_ENDREACHED2
- dec temp2
- brne PFA_COMPARE_LOOP
- rjmp PFA_COMPARE_ENDREACHED
-PFA_COMPARE_ENDREACHED2:
- dec temp2
-PFA_COMPARE_ENDREACHED:
- or temp0, temp2
- brne PFA_COMPARE_CHECKLASTCHAR
- clr tosl
- rjmp PFA_COMPARE_DONE
-PFA_COMPARE_CHECKLASTCHAR:
-PFA_COMPARE_NOTEQUAL:
- ser tosl
- rjmp PFA_COMPARE_DONE
-
-PFA_COMPARE_DONE:
- mov tosh, tosl
- pop xl
- pop xh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/const-fold-depth.asm b/amforth-6.5/avr8/words/const-fold-depth.asm
deleted file mode 100644
index 40b80eb..0000000
--- a/amforth-6.5/avr8/words/const-fold-depth.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( flagset -- n )
-; Tools
-; constant fold depth
-VE_CONSTFOLDDEPTH:
- .dw $ff0a
- .db "cfolddepth"
- .dw VE_HEAD
- .set VE_HEAD = VE_CONSTFOLDDEPTH
-XT_CONSTFOLDDEPTH:
- .dw DO_COLON
-PFA_CONSTFOLDDEPTH:
- .dw XT_DOLITERAL
- .dw $7000
- .dw XT_AND
- .dw XT_DOLITERAL
- .dw 12
- .dw XT_RSHIFT
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/cstore.asm b/amforth-6.5/avr8/words/cstore.asm
deleted file mode 100644
index f953f8f..0000000
--- a/amforth-6.5/avr8/words/cstore.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( c a-addr -- )
-; Memory
-; store a single byte to RAM address
-VE_CSTORE:
- .dw $ff02
- .db "c!"
- .dw VE_HEAD
- .set VE_HEAD = VE_CSTORE
-XT_CSTORE:
- .dw PFA_CSTORE
-PFA_CSTORE:
- movw zl, tosl
- loadtos
- st Z, tosl
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/d-2slash.asm b/amforth-6.5/avr8/words/d-2slash.asm
deleted file mode 100644
index e9a67ea..0000000
--- a/amforth-6.5/avr8/words/d-2slash.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( d1 -- d2 )
-; Arithmetics
-; shift a double cell value right
-VE_D2SLASH:
- .dw $ff03
- .db "d2/",0
- .dw VE_HEAD
- .set VE_HEAD = VE_D2SLASH
-XT_D2SLASH:
- .dw PFA_D2SLASH
-PFA_D2SLASH:
- ld temp0, Y+
- ld temp1, Y+
- asr tosh
- ror tosl
- ror temp1
- ror temp0
- st -Y, temp1
- st -Y, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/d-2star.asm b/amforth-6.5/avr8/words/d-2star.asm
deleted file mode 100644
index f0ca099..0000000
--- a/amforth-6.5/avr8/words/d-2star.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( d1 -- d2 )
-; Arithmetics
-; shift a double cell left
-VE_D2STAR:
- .dw $ff03
- .db "d2*",0
- .dw VE_HEAD
- .set VE_HEAD = VE_D2STAR
-XT_D2STAR:
- .dw PFA_D2STAR
-PFA_D2STAR:
- ld temp0, Y+
- ld temp1, Y+
- lsl temp0
- rol temp1
- rol tosl
- rol tosh
- st -Y, temp1
- st -Y, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/d-greaterzero.asm b/amforth-6.5/avr8/words/d-greaterzero.asm
deleted file mode 100644
index 30fad34..0000000
--- a/amforth-6.5/avr8/words/d-greaterzero.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( d -- flag )
-; Compare
-; compares if a double double cell number is greater 0
-VE_DGREATERZERO:
- .dw $ff03
- .db "d0>",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DGREATERZERO
-XT_DGREATERZERO:
- .dw PFA_DGREATERZERO
-PFA_DGREATERZERO:
- cp tosl, zerol
- cpc tosh, zeroh
- loadtos
- cpc tosl, zerol
- cpc tosh, zeroh
- brlt PFA_ZERO1
- brbs 1, PFA_ZERO1
- rjmp PFA_TRUE1
diff --git a/amforth-6.5/avr8/words/d-invert.asm b/amforth-6.5/avr8/words/d-invert.asm
deleted file mode 100644
index c87ae05..0000000
--- a/amforth-6.5/avr8/words/d-invert.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( d1 -- d2)
-; Arithmetics
-; invert all bits in the double cell value
-VE_DINVERT:
- .dw $ff07
- .db "dinvert",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DINVERT
-XT_DINVERT:
- .dw PFA_DINVERT
-PFA_DINVERT:
- ld temp0, Y+
- ld temp1, Y+
- com tosl
- com tosh
- com temp0
- com temp1
- st -Y, temp1
- st -Y, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/d-lesszero.asm b/amforth-6.5/avr8/words/d-lesszero.asm
deleted file mode 100644
index afa70c7..0000000
--- a/amforth-6.5/avr8/words/d-lesszero.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( d -- flag )
-; Compare
-; compares if a double double cell number is less than 0
-VE_DXT_ZEROLESS:
- .dw $ff03
- .db "d0<",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DXT_ZEROLESS
-XT_DXT_ZEROLESS:
- .dw PFA_DXT_ZEROLESS
-PFA_DXT_ZEROLESS:
- adiw Y,2
- sbrc tosh,7
- jmp PFA_TRUE1
- jmp PFA_ZERO1
diff --git a/amforth-6.5/avr8/words/d-minus.asm b/amforth-6.5/avr8/words/d-minus.asm
deleted file mode 100644
index a458851..0000000
--- a/amforth-6.5/avr8/words/d-minus.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-; ( d1 d2 -- d3 )
-; Arithmetics
-; subtract d2 from d1
-VE_DMINUS:
- .dw $ff02
- .db "d-"
- .dw VE_HEAD
- .set VE_HEAD = VE_DMINUS
-XT_DMINUS:
- .dw PFA_DMINUS
-PFA_DMINUS:
- ld temp2, Y+
- ld temp3, Y+
-
- ld temp4, Y+
- ld temp5, Y+
- ld temp6, Y+
- ld temp7, Y+
-
- sub temp6, temp2
- sbc temp7, temp3
- sbc temp4, tosl
- sbc temp5, tosh
-
- st -Y, temp7
- st -Y, temp6
- movw tosl, temp4
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/d-plus.asm b/amforth-6.5/avr8/words/d-plus.asm
deleted file mode 100644
index 60286dd..0000000
--- a/amforth-6.5/avr8/words/d-plus.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( d1 d2 -- d3)
-; Arithmetics
-; add 2 double cell values
-VE_DPLUS:
- .dw $ff02
- .db "d+"
- .dw VE_HEAD
- .set VE_HEAD = VE_DPLUS
-XT_DPLUS:
- .dw PFA_DPLUS
-PFA_DPLUS:
- ld temp2, Y+
- ld temp3, Y+
-
- ld temp4, Y+
- ld temp5, Y+
- ld temp6, Y+
- ld temp7, Y+
-
- add temp2, temp6
- adc temp3, temp7
- adc tosl, temp4
- adc tosh, temp5
-
- st -Y, temp3
- st -Y, temp2
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/dabs.asm b/amforth-6.5/avr8/words/dabs.asm
deleted file mode 100644
index 43b372d..0000000
--- a/amforth-6.5/avr8/words/dabs.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( d -- ud )
-; Arithmetics
-; double cell absolute value
-VE_DABS:
- .dw $ff04
- .db "dabs"
- .dw VE_HEAD
- .set VE_HEAD = VE_DABS
-XT_DABS:
- .dw DO_COLON
-PFA_DABS:
- .dw XT_DUP
- .dw XT_ZEROLESS
- .dw XT_DOCONDBRANCH
- .dw PFA_DABS1
- .dw XT_DNEGATE
-PFA_DABS1:
- .dw XT_EXIT
-; : dabs ( ud1 -- +d2 ) dup 0< if dnegate then ;
diff --git a/amforth-6.5/avr8/words/dnegate.asm b/amforth-6.5/avr8/words/dnegate.asm
deleted file mode 100644
index cfa45ca..0000000
--- a/amforth-6.5/avr8/words/dnegate.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( d1 -- d2 )
-; Arithmetics
-; double cell negation
-VE_DNEGATE:
- .dw $ff07
- .db "dnegate",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DNEGATE
-XT_DNEGATE:
- .dw DO_COLON
-PFA_DNEGATE:
- .dw XT_DINVERT
- .dw XT_ONE
- .dw XT_ZERO
- .dw XT_DPLUS
- .dw XT_EXIT
-; : dnegate ( ud1 -- ud2 ) dinvert 1. d+ ;
diff --git a/amforth-6.5/avr8/words/do-defer.asm b/amforth-6.5/avr8/words/do-defer.asm
deleted file mode 100644
index dbd190e..0000000
--- a/amforth-6.5/avr8/words/do-defer.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( i*x -- j*x )
-; System
-; runtime of defer
-VE_DODEFER:
- .dw $ff07
- .db "(defer)", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_DODEFER
-XT_DODEFER:
- .dw DO_COLON
-PFA_DODEFER:
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_COMPILE
- .dw PFA_DODEFER1
- .dw XT_EXIT
-PFA_DODEFER1:
- call_ DO_DODOES
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXECUTE
- .dw XT_EXIT
-
-; : (defer) <builds does> dup i-cell+ @i execute execute ;
-
diff --git a/amforth-6.5/avr8/words/do-sliteral.asm b/amforth-6.5/avr8/words/do-sliteral.asm
deleted file mode 100644
index 41ddb15..0000000
--- a/amforth-6.5/avr8/words/do-sliteral.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- addr len )
-; String
-; runtime portion of sliteral
-;VE_DOSLITERAL:
-; .dw $ff0a
-; .db "(sliteral)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOSLITERAL
-XT_DOSLITERAL:
- .dw DO_COLON
-PFA_DOSLITERAL:
- .dw XT_R_FETCH ; ( -- addr )
- .dw XT_ICOUNT
- .dw XT_R_FROM
- .dw XT_OVER ; ( -- addr' n addr n)
- .dw XT_1PLUS
- .dw XT_2SLASH ; ( -- addr' n addr k )
- .dw XT_PLUS ; ( -- addr' n addr'' )
- .dw XT_1PLUS
- .dw XT_TO_R ; ( -- )
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/do-value.asm b/amforth-6.5/avr8/words/do-value.asm
deleted file mode 100644
index 65182f5..0000000
--- a/amforth-6.5/avr8/words/do-value.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- n )
-; System
-; runtime of value
-VE_DOVALUE:
- .dw $ff07
- .db "(value)", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_DOVALUE
-XT_DOVALUE:
- .dw DO_COLON
-PFA_DOVALUE:
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_COMPILE
- .dw PFA_DOVALUE1
- .dw XT_EXIT
-PFA_DOVALUE1:
- call_ DO_DODOES
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXIT
-
-; : (value) <builds does> dup icell+ @i execute ;
diff --git a/amforth-6.5/avr8/words/dobranch.asm b/amforth-6.5/avr8/words/dobranch.asm
deleted file mode 100644
index 7ff018f..0000000
--- a/amforth-6.5/avr8/words/dobranch.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; System
-; runtime of branch
-;VE_DOBRANCH:
-; .dw $ff08
-; .db "(branch)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOBRANCH
-XT_DOBRANCH:
- .dw PFA_DOBRANCH
-PFA_DOBRANCH:
- movw zl, XL
- readflashcell XL,XH
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/docondbranch.asm b/amforth-6.5/avr8/words/docondbranch.asm
deleted file mode 100644
index 64b2e5e..0000000
--- a/amforth-6.5/avr8/words/docondbranch.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( f -- )
-; System
-; runtime of ?branch
-;VE_DOCONDBRANCH:
-; .dw $ff09
-; .db "(?branch)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOCONDBRANCH
-XT_DOCONDBRANCH:
- .dw PFA_DOCONDBRANCH
-PFA_DOCONDBRANCH:
- or tosh, tosl
- loadtos
- brbs 1, PFA_DOBRANCH ; 1 is z flag; if tos is zero (false), do the branch
- adiw XL, 1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/doconstant.asm b/amforth-6.5/avr8/words/doconstant.asm
deleted file mode 100644
index 0ecdf27..0000000
--- a/amforth-6.5/avr8/words/doconstant.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- addr )
-; System
-; place data field address on TOS
-;VE_DOCONSTANT:
-; .dw $ff0a
-; .db "(constant)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOCONSTANT
-XT_DOCONSTANT:
- .dw PFA_DOCONSTANT
-PFA_DOCONSTANT:
- savetos
- movw tosl, wl
- adiw tosl, 1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/dodo.asm b/amforth-6.5/avr8/words/dodo.asm
deleted file mode 100644
index 3b88694..0000000
--- a/amforth-6.5/avr8/words/dodo.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( limit start -- ) (R: -- loop-sys )
-; System
-; runtime of do
-;VE_DODO:
-; .dw $ff04
-; .db "(do)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DODO
-XT_DODO:
- .dw PFA_DODO
-PFA_DODO:
- ld temp2, Y+
- ld temp3, Y+ ; limit
-PFA_DODO1:
- ldi zl, $80
- add temp3, zl
- sub tosl, temp2
- sbc tosh, temp3
-
- push temp3
- push temp2 ; limit ( --> limit + $8000)
- push tosh
- push tosl ; start -> index ( --> index - (limit - $8000)
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/does.asm b/amforth-6.5/avr8/words/does.asm
deleted file mode 100644
index 6e3e71b..0000000
--- a/amforth-6.5/avr8/words/does.asm
+++ /dev/null
@@ -1,53 +0,0 @@
-; ( i*x -- j*y ) (R: nest-sys1 -- ) (C: colon-sys1 -- colon-sys2 )
-; Compiler
-; organize the XT replacement to call other colon code
-VE_DOES:
- .dw $0005
- .db "does>",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DOES
-XT_DOES:
- .dw DO_COLON
-PFA_DOES:
- .dw XT_COMPILE
- .dw XT_DODOES
- .dw XT_COMPILE ; create a code snippet to be used in an embedded XT
- .dw $940e ; the address of this compiled
- .dw XT_COMPILE ; code will replace the XT of the
- .dw DO_DODOES ; word that CREATE created
- .dw XT_EXIT ;
-
-DO_DODOES: ; ( -- PFA )
- savetos
- movw tosl, wl
- adiw tosl, 1
- ; the following takes the address from a real uC-call
-.if (pclen==3)
- pop wh ; some 128K Flash devices use 3 cells for call/ret
-.endif
- pop wh
- pop wl
-
- push XH
- push XL
- movw XL, wl
- jmp_ DO_NEXT
-
-; ( -- )
-; System
-; replace the XT written by CREATE to call the code that follows does>
-;VE_DODOES:
-; .dw $ff07
-; .db "(does>)"
-; .set VE_HEAD = VE_DODOES
-XT_DODOES:
- .dw DO_COLON
-PFA_DODOES:
- .dw XT_R_FROM
- .dw XT_NEWEST
- .dw XT_CELLPLUS
- .dw XT_FETCH
- .dw XT_FETCHE
- .dw XT_NFA2CFA
- .dw XT_STOREI
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/doliteral.asm b/amforth-6.5/avr8/words/doliteral.asm
deleted file mode 100644
index 31da4b3..0000000
--- a/amforth-6.5/avr8/words/doliteral.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( -- n1 )
-; System
-; runtime of literal
-;VE_DOLITERAL:
-; .dw $ff09
-; .db "(literal)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOLITERAL
-XT_DOLITERAL:
- .dw PFA_DOLITERAL
-PFA_DOLITERAL:
- savetos
- movw zl, xl
- readflashcell tosl,tosh
- adiw xl, 1
- jmp_ DO_NEXT
-
diff --git a/amforth-6.5/avr8/words/doloop.asm b/amforth-6.5/avr8/words/doloop.asm
deleted file mode 100644
index b5e0a26..0000000
--- a/amforth-6.5/avr8/words/doloop.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- ) (R: loop-sys1 -- loop-sys2| )
-; System
-; runtime of loop
-;VE_DOLOOP:
-; .dw $ff06
-; .db "(loop)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOLOOP
-XT_DOLOOP:
- .dw PFA_DOLOOP
-PFA_DOLOOP:
- pop zl
- pop zh
- adiw zl,1
- brvs PFA_DOPLUSLOOP_LEAVE
- jmp_ PFA_DOPLUSLOOP_NEXT
diff --git a/amforth-6.5/avr8/words/doplusloop.asm b/amforth-6.5/avr8/words/doplusloop.asm
deleted file mode 100644
index c34cae5..0000000
--- a/amforth-6.5/avr8/words/doplusloop.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-; ( n1 -- ) (R: loop-sys1 -- loop-sys2| )
-; System
-; runtime of +loop
-;VE_DOPLUSLOOP:
-; .dw $ff07
-; .db "(+loop)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOPLUSLOOP
-XT_DOPLUSLOOP:
- .dw PFA_DOPLUSLOOP
-PFA_DOPLUSLOOP:
- pop zl
- pop zh
- add zl, tosl
- adc zh, tosh
- loadtos
- brvs PFA_DOPLUSLOOP_LEAVE
- ; next cycle
-PFA_DOPLUSLOOP_NEXT:
- ; next iteration
- push zh
- push zl
- rjmp PFA_DOBRANCH ; read next cell from dictionary and jump to its destination
-PFA_DOPLUSLOOP_LEAVE:
- pop temp0
- pop temp1 ; remove limit
- adiw xl, 1 ; skip branch-back address
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/douser.asm b/amforth-6.5/avr8/words/douser.asm
deleted file mode 100644
index 1347651..0000000
--- a/amforth-6.5/avr8/words/douser.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( -- addr )
-; System
-; runtime part of user
-;VE_DOUSER:
-; .dw $ff06
-; .db "(user)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOUSER
-XT_DOUSER:
- .dw PFA_DOUSER
-PFA_DOUSER:
- savetos
- movw zl, wl
- adiw zl, 1
- readflashcell tosl,tosh
- add tosl, upl
- adc tosh, uph
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/dovariable.asm b/amforth-6.5/avr8/words/dovariable.asm
deleted file mode 100644
index 6866ef4..0000000
--- a/amforth-6.5/avr8/words/dovariable.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- addr )
-; System
-; puts content of parameter field (1 cell) to TOS
-;VE_DOVARIABLE:
-; .dw $ff0a
-; .db "(variable)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOVARIABLE
-XT_DOVARIABLE:
- .dw PFA_DOVARIABLE
-PFA_DOVARIABLE:
- savetos
- movw zl, wl
- adiw zl,1
- readflashcell tosl,tosh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/dp.asm b/amforth-6.5/avr8/words/dp.asm
deleted file mode 100644
index c9507f7..0000000
--- a/amforth-6.5/avr8/words/dp.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- f-addr )
-; System Value
-; address of the next free dictionary cell
-VE_DP:
- .dw $ff02
- .db "dp"
- .dw VE_HEAD
- .set VE_HEAD = VE_DP
-XT_DP:
- .dw PFA_DOVALUE1
-PFA_DP:
- .dw CFG_DP
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/drop.asm b/amforth-6.5/avr8/words/drop.asm
deleted file mode 100644
index baee84b..0000000
--- a/amforth-6.5/avr8/words/drop.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( n -- )
-; Stack
-; drop TOS
-VE_DROP:
- .dw $ff04
- .db "drop"
- .dw VE_HEAD
- .set VE_HEAD = VE_DROP
-XT_DROP:
- .dw PFA_DROP
-PFA_DROP:
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/dup.asm b/amforth-6.5/avr8/words/dup.asm
deleted file mode 100644
index 0b5fa27..0000000
--- a/amforth-6.5/avr8/words/dup.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( n -- n n )
-; Stack
-; duplicate TOS
-VE_DUP:
- .dw $ff03
- .db "dup",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DUP
-XT_DUP:
- .dw PFA_DUP
-PFA_DUP:
- savetos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/edefer-fetch.asm b/amforth-6.5/avr8/words/edefer-fetch.asm
deleted file mode 100644
index 651bb53..0000000
--- a/amforth-6.5/avr8/words/edefer-fetch.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( xt1 -- xt2 )
-; System
-; does the real defer@ for eeprom defers
-VE_EDEFERFETCH:
- .dw $ff07
- .db "Edefer@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERFETCH
-XT_EDEFERFETCH:
- .dw DO_COLON
-PFA_EDEFERFETCH:
- .dw XT_FETCHI
- .dw XT_FETCHE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/edefer-store.asm b/amforth-6.5/avr8/words/edefer-store.asm
deleted file mode 100644
index 1c0011b..0000000
--- a/amforth-6.5/avr8/words/edefer-store.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( xt1 xt2 -- )
-; System
-; does the real defer! for eeprom defers
-VE_EDEFERSTORE:
- .dw $ff07
- .db "Edefer!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_EDEFERSTORE
-XT_EDEFERSTORE:
- .dw DO_COLON
-PFA_EDEFERSTORE:
- .dw XT_FETCHI
- .dw XT_STOREE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/ehere.asm b/amforth-6.5/avr8/words/ehere.asm
deleted file mode 100644
index e416c0e..0000000
--- a/amforth-6.5/avr8/words/ehere.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- e-addr )
-; System Value
-; address of the next free address in eeprom
-VE_EHERE:
- .dw $ff05
- .db "ehere",0
- .dw VE_HEAD
- .set VE_HEAD = VE_EHERE
-XT_EHERE:
- .dw PFA_DOVALUE1
-PFA_EHERE:
- .dw EE_EHERE
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/end-code.asm b/amforth-6.5/avr8/words/end-code.asm
deleted file mode 100644
index bf161eb..0000000
--- a/amforth-6.5/avr8/words/end-code.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- )
-; Compiler
-; finish a code definition
-VE_ENDCODE:
- .dw $ff08
- .db "end-code"
- .dw VE_HEAD
- .set VE_HEAD = VE_ENDCODE
-XT_ENDCODE:
- .dw DO_COLON
-PFA_ENDCODE:
- .dw XT_COMPILE
- .dw $940c
- .dw XT_COMPILE
- .dw DO_NEXT
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/env-mcuinfo.asm b/amforth-6.5/avr8/words/env-mcuinfo.asm
deleted file mode 100644
index ef7240a..0000000
--- a/amforth-6.5/avr8/words/env-mcuinfo.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- faddr len )
-; Environment
-; flash address of some CPU specific parameters
-VE_ENV_MCUINFO:
- .dw $ff08
- .db "mcu-info"
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_MCUINFO
-XT_ENV_MCUINFO:
- .dw DO_COLON
-PFA_EN_MCUINFO:
- .dw XT_DOLITERAL
- .dw mcu_info
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/env-slashpad.asm b/amforth-6.5/avr8/words/env-slashpad.asm
deleted file mode 100644
index 1cb7dbb..0000000
--- a/amforth-6.5/avr8/words/env-slashpad.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- padsize )
-; Environment
-; Size of the PAD buffer in bytes
-VE_ENVSLASHPAD:
- .dw $ff04
- .db "/pad"
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHPAD
-XT_ENVSLASHPAD:
- .dw DO_COLON
-PFA_ENVSLASHPAD:
- .dw XT_SP_FETCH
- .dw XT_PAD
- .dw XT_MINUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/env-wordlists.asm b/amforth-6.5/avr8/words/env-wordlists.asm
deleted file mode 100644
index 643cfb7..0000000
--- a/amforth-6.5/avr8/words/env-wordlists.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- n )
-; Environment
-; maximum number of wordlists in the dictionary search order
-VE_ENVWORDLISTS:
- .dw $ff09
- .db "wordlists",0
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVWORDLISTS
-XT_ENVWORDLISTS:
- .dw DO_COLON
-PFA_ENVWORDLISTS:
- .dw XT_DOLITERAL
- .dw NUMWORDLISTS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/environment.asm b/amforth-6.5/avr8/words/environment.asm
deleted file mode 100644
index 8e39c08..0000000
--- a/amforth-6.5/avr8/words/environment.asm
+++ /dev/null
@@ -1,12 +0,0 @@
-; ( -- wid)
-; System Value
-; word list identifier of the environmental search list
-VE_ENVIRONMENT:
- .dw $ff0b
- .db "environment",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ENVIRONMENT
-XT_ENVIRONMENT:
- .dw PFA_DOVARIABLE
-PFA_ENVIRONMENT:
- .dw CFG_ENVIRONMENT
diff --git a/amforth-6.5/avr8/words/equal.asm b/amforth-6.5/avr8/words/equal.asm
deleted file mode 100644
index 1cd3e57..0000000
--- a/amforth-6.5/avr8/words/equal.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n1 n2 -- flag )
-; Compare
-; compares two values for equality
-VE_EQUAL:
- .dw $ff01
- .db "=",0
- .dw VE_HEAD
- .set VE_HEAD = VE_EQUAL
-XT_EQUAL:
- .dw DO_COLON
-PFA_EQUAL:
- .dw XT_MINUS
- .dw XT_ZEROEQUAL
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/equalzero.asm b/amforth-6.5/avr8/words/equalzero.asm
deleted file mode 100644
index d33cedd..0000000
--- a/amforth-6.5/avr8/words/equalzero.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n -- flag )
-; Compare
-; compare with 0 (zero)
-VE_ZEROEQUAL:
- .dw $ff02
- .db "0="
- .dw VE_HEAD
- .set VE_HEAD = VE_ZEROEQUAL
-XT_ZEROEQUAL:
- .dw PFA_ZEROEQUAL
-PFA_ZEROEQUAL:
- or tosh, tosl
- brne PFA_ZERO1
- rjmp PFA_TRUE1
diff --git a/amforth-6.5/avr8/words/execute.asm b/amforth-6.5/avr8/words/execute.asm
deleted file mode 100644
index 4a2308d..0000000
--- a/amforth-6.5/avr8/words/execute.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( xt -- )
-; System
-; execute XT
-VE_EXECUTE:
- .dw $ff07
- .db "execute",0
- .dw VE_HEAD
- .set VE_HEAD = VE_EXECUTE
-XT_EXECUTE:
- .dw PFA_EXECUTE
-PFA_EXECUTE:
- movw wl, tosl
- loadtos
- jmp_ DO_EXECUTE
diff --git a/amforth-6.5/avr8/words/exit.asm b/amforth-6.5/avr8/words/exit.asm
deleted file mode 100644
index 89e19b9..0000000
--- a/amforth-6.5/avr8/words/exit.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- ) (R: nest-sys -- )
-; Compiler
-; end of current colon word
-VE_EXIT:
- .dw $ff04
- .db "exit"
- .dw VE_HEAD
- .set VE_HEAD = VE_EXIT
-XT_EXIT:
- .dw PFA_EXIT
-PFA_EXIT:
- pop XL
- pop XH
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/fetch-e.asm b/amforth-6.5/avr8/words/fetch-e.asm
deleted file mode 100644
index fb0dee5..0000000
--- a/amforth-6.5/avr8/words/fetch-e.asm
+++ /dev/null
@@ -1,51 +0,0 @@
-; ( e-addr - n)
-; Memory
-; read 1 cell from eeprom
-VE_FETCHE:
- .dw $ff02
- .db "@e"
- .dw VE_HEAD
- .set VE_HEAD = VE_FETCHE
-XT_FETCHE:
- .dw PFA_FETCHE
-PFA_FETCHE:
-.if WANT_UNIFIED == 1
- ldi zh, high(EEPROMEND)
- ldi zl, low(EEPROMEND)
- cp tosl, zl
- cpc tosh, zh
- brlt PFA_FETCHE1
- brbs 1, PFA_FETCHE1
- rjmp PFA_FETCHE_OTHER
-.endif
-PFA_FETCHE1:
- in_ temp2, SREG
- cli
- movw zl, tosl
- rcall PFA_FETCHE2
- in_ tosl, EEDR
-
- adiw zl,1
-
- rcall PFA_FETCHE2
- in_ tosh, EEDR
- out_ SREG, temp2
- jmp_ DO_NEXT
-
-PFA_FETCHE2:
- sbic EECR, EEPE
- rjmp PFA_FETCHE2
-
- out_ EEARH,zh
- out_ EEARL,zl
-
- sbi EECR,EERE
- ret
-
-.if WANT_UNIFIED == 1
-PFA_FETCHE_OTHER:
- adiw zl, 1
- sub tosl, zl
- sbc tosh, zh
- jmp_ PFA_FETCHI
-.endif
diff --git a/amforth-6.5/avr8/words/fetch-i.asm b/amforth-6.5/avr8/words/fetch-i.asm
deleted file mode 100644
index 5cdcc37..0000000
--- a/amforth-6.5/avr8/words/fetch-i.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( f-addr -- n1 )
-; Memory
-; read 1 cell from flash
-VE_FETCHI:
- .dw $ff02
- .db "@i"
- .dw VE_HEAD
- .set VE_HEAD = VE_FETCHI
-XT_FETCHI:
- .dw PFA_FETCHI
-PFA_FETCHI:
- movw zl, tosl
- readflashcell tosl,tosh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/fetch-u.asm b/amforth-6.5/avr8/words/fetch-u.asm
deleted file mode 100644
index 6e94616..0000000
--- a/amforth-6.5/avr8/words/fetch-u.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( offset -- n )
-; Memory
-; read 1 cell from USER area
-VE_FETCHU:
- .dw $ff02
- .db "@u"
- .dw VE_HEAD
- .set VE_HEAD = VE_FETCHU
-XT_FETCHU:
- .dw DO_COLON
-PFA_FETCHU:
- .dw XT_UP_FETCH
- .dw XT_PLUS
- .dw XT_FETCH
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/fetch.asm b/amforth-6.5/avr8/words/fetch.asm
deleted file mode 100644
index 6cd2f2b..0000000
--- a/amforth-6.5/avr8/words/fetch.asm
+++ /dev/null
@@ -1,33 +0,0 @@
-; ( a-addr -- n )
-; Memory
-; read 1 cell from RAM address
-VE_FETCH:
- .dw $ff01
- .db "@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_FETCH
-XT_FETCH:
- .dw PFA_FETCH
-PFA_FETCH:
-.if WANT_UNIFIED == 1
- ldi zh, high(RAMEND)
- ldi zl, low(RAMEND)
- cp tosl, zl
- cpc tosh, zh
- brlt PFA_FETCHRAM
- brbs 1, PFA_FETCHRAM
- rjmp PFA_FETCHOTHER
-.endif
-PFA_FETCHRAM:
- movw zl, tosl
- ; low byte is read before the high byte
- ld tosl, z+
- ld tosh, z+
- jmp_ DO_NEXT
-.if WANT_UNIFIED == 1
-PFA_FETCHOTHER:
- adiw zl, 1
- sub tosl, zl
- sbc tosh, zh
- jmp_ PFA_FETCHE
-.endif
diff --git a/amforth-6.5/avr8/words/fill.asm b/amforth-6.5/avr8/words/fill.asm
deleted file mode 100644
index e8bcacc..0000000
--- a/amforth-6.5/avr8/words/fill.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( a-addr u c -- )
-; Memory
-; fill u bytes memory beginning at a-addr with character c
-VE_FILL:
- .dw $ff04
- .db "fill"
- .dw VE_HEAD
- .set VE_HEAD = VE_FILL
-XT_FILL:
- .dw DO_COLON
-PFA_FILL:
- .dw XT_ROT
- .dw XT_ROT
- .dw XT_QDUP,XT_DOCONDBRANCH
- DEST(PFA_FILL2)
- .dw XT_BOUNDS
- .dw XT_DODO
-PFA_FILL1:
- .dw XT_DUP
- .dw XT_I
- .dw XT_CSTORE ; ( -- c c-addr)
- .dw XT_DOLOOP
- .dw PFA_FILL1
-PFA_FILL2:
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/forth-recognizer.asm b/amforth-6.5/avr8/words/forth-recognizer.asm
deleted file mode 100644
index 5b50820..0000000
--- a/amforth-6.5/avr8/words/forth-recognizer.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- addr )
-; System Value
-; address of the next free data space (RAM) cell
-VE_FORTHRECOGNIZER:
- .dw $ff10
- .db "forth-recognizer"
- .dw VE_HEAD
- .set VE_HEAD = VE_FORTHRECOGNIZER
-XT_FORTHRECOGNIZER:
- .dw PFA_DOVALUE1
-PFA_FORTHRECOGNIZER:
- .dw CFG_FORTHRECOGNIZER
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/forth-wordlist.asm b/amforth-6.5/avr8/words/forth-wordlist.asm
deleted file mode 100644
index 4147aea..0000000
--- a/amforth-6.5/avr8/words/forth-wordlist.asm
+++ /dev/null
@@ -1,12 +0,0 @@
-; ( -- wid )
-; Search Order
-; get the system default word list
-VE_FORTHWORDLIST:
- .dw $ff0e
- .db "forth-wordlist"
- .dw VE_HEAD
- .set VE_HEAD = VE_FORTHWORDLIST
-XT_FORTHWORDLIST:
- .dw PFA_DOVARIABLE
-PFA_FORTHWORDLIST:
- .dw CFG_FORTHWORDLIST
diff --git a/amforth-6.5/avr8/words/g-mark.asm b/amforth-6.5/avr8/words/g-mark.asm
deleted file mode 100644
index 7f7fa36..0000000
--- a/amforth-6.5/avr8/words/g-mark.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- dest )
-; Compiler
-; places current dictionary position for backward resolves
-;VE_GMARK:
-; .dw $ff05
-; .db ">mark"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_GMARK
-XT_GMARK:
- .dw DO_COLON
-PFA_GMARK:
- .dw XT_DP
- .dw XT_COMPILE
- .dw -1 ; ffff does not erase flash
- .dw XT_EXIT
- \ No newline at end of file
diff --git a/amforth-6.5/avr8/words/g-resolve.asm b/amforth-6.5/avr8/words/g-resolve.asm
deleted file mode 100644
index 0566b37..0000000
--- a/amforth-6.5/avr8/words/g-resolve.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( dest -- )
-; Compiler
-; resolve backward jumps
-;VE_GRESOLVE:
-; .dw $ff08
-; .db ">resolve"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_GRESOLVE
-XT_GRESOLVE:
- .dw DO_COLON
-PFA_GRESOLVE:
- .dw XT_QSTACK
- .dw XT_DP
- .dw XT_SWAP
- .dw XT_STOREI
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/get-current.asm b/amforth-6.5/avr8/words/get-current.asm
deleted file mode 100644
index a016a95..0000000
--- a/amforth-6.5/avr8/words/get-current.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- wid)
-; Search Order
-; get the wid of the current compilation word list
-VE_GET_CURRENT:
- .dw $ff0b
- .db "get-current",0
- .dw VE_HEAD
- .set VE_HEAD = VE_GET_CURRENT
-XT_GET_CURRENT:
- .dw DO_COLON
-PFA_GET_CURRENT:
- .dw XT_DOLITERAL
- .dw CFG_CURRENT
- .dw XT_FETCHE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/greater.asm b/amforth-6.5/avr8/words/greater.asm
deleted file mode 100644
index b4a9731..0000000
--- a/amforth-6.5/avr8/words/greater.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( n1 n2 -- flag )
-; Compare
-; flag is true if n1 is greater than n2
-VE_GREATER:
- .dw $ff01
- .db ">",0
- .dw VE_HEAD
- .set VE_HEAD = VE_GREATER
-XT_GREATER:
- .dw PFA_GREATER
-PFA_GREATER:
- ld temp2, Y+
- ld temp3, Y+
- cp temp2, tosl
- cpc temp3, tosh
-PFA_GREATERDONE:
- brlt PFA_ZERO1
- brbs 1, PFA_ZERO1
- rjmp PFA_TRUE1
diff --git a/amforth-6.5/avr8/words/greaterzero.asm b/amforth-6.5/avr8/words/greaterzero.asm
deleted file mode 100644
index 61cca0e..0000000
--- a/amforth-6.5/avr8/words/greaterzero.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( n1 -- flag )
-; Compare
-; true if n1 is greater than 0
-VE_GREATERZERO:
- .dw $ff02
- .db "0>"
- .dw VE_HEAD
- .set VE_HEAD = VE_GREATERZERO
-XT_GREATERZERO:
- .dw PFA_GREATERZERO
-PFA_GREATERZERO:
- cp tosl, zerol
- cpc tosh, zeroh
- brlt PFA_ZERO1
- brbs 1, PFA_ZERO1
- rjmp PFA_TRUE1
diff --git a/amforth-6.5/avr8/words/header.asm b/amforth-6.5/avr8/words/header.asm
deleted file mode 100644
index 4a1e6e9..0000000
--- a/amforth-6.5/avr8/words/header.asm
+++ /dev/null
@@ -1,36 +0,0 @@
-; ( addr len wid -- nfa )
-; Compiler
-; creates the vocabulary header without XT and data field (PF) in the wordlist wid
-VE_HEADER:
- .dw $ff06
- .db "header"
- .dw VE_HEAD
- .set VE_HEAD = VE_HEADER
-XT_HEADER:
- .dw DO_COLON
-PFA_HEADER:
- .dw XT_DP ; the new Name Field
- .dw XT_TO_R
- .dw XT_TO_R ; ( R: NFA WID )
- .dw XT_DUP
- .dw XT_GREATERZERO
- .dw XT_DOCONDBRANCH
- .dw PFA_HEADER1
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw $ff00 ; all flags are off (e.g. immediate)
- .dw XT_OR
- .dw XT_DOSCOMMA
- ; make the link to the previous entry in this wordlist
- .dw XT_R_FROM
- .dw XT_FETCHE
- .dw XT_COMMA
- .dw XT_R_FROM
- .dw XT_EXIT
-
-PFA_HEADER1:
- ; -16: attempt to use zero length string as a name
- .dw XT_DOLITERAL
- .dw -16
- .dw XT_THROW
-
diff --git a/amforth-6.5/avr8/words/here.asm b/amforth-6.5/avr8/words/here.asm
deleted file mode 100644
index c3fc5cb..0000000
--- a/amforth-6.5/avr8/words/here.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- addr )
-; System Value
-; address of the next free data space (RAM) cell
-VE_HERE:
- .dw $ff04
- .db "here"
- .dw VE_HEAD
- .set VE_HEAD = VE_HERE
-XT_HERE:
- .dw PFA_DOVALUE1
-PFA_HERE:
- .dw EE_HERE
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/hld.asm b/amforth-6.5/avr8/words/hld.asm
deleted file mode 100644
index d31590c..0000000
--- a/amforth-6.5/avr8/words/hld.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- addr )
-; Numeric IO
-; pointer to current write position in the Pictured Numeric Output buffer
-VE_HLD:
- .dw $ff03
- .db "hld",0
- .dw VE_HEAD
- .set VE_HEAD = VE_HLD
-XT_HLD:
- .dw PFA_DOVARIABLE
-PFA_HLD:
- .dw ram_hld
-
-.dseg
-ram_hld: .byte 2
-.cseg
diff --git a/amforth-6.5/avr8/words/i-cellplus.asm b/amforth-6.5/avr8/words/i-cellplus.asm
deleted file mode 100644
index 08cbb14..0000000
--- a/amforth-6.5/avr8/words/i-cellplus.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( addr -- addr' )
-; Compiler
-; skip to the next cell in flash
-VE_ICELLPLUS:
- .dw $FF07
- .db "i-cell+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ICELLPLUS
-XT_ICELLPLUS:
- .dw DO_COLON
-PFA_ICELLPLUS:
- .dw XT_1PLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/i.asm b/amforth-6.5/avr8/words/i.asm
deleted file mode 100644
index 4943073..0000000
--- a/amforth-6.5/avr8/words/i.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- n ) (R: loop-sys -- loop-sys)
-; Compiler
-; current loop counter
-VE_I:
- .dw $FF01
- .db "i",0
- .dw VE_HEAD
- .set VE_HEAD = VE_I
-XT_I:
- .dw PFA_I
-PFA_I:
- savetos
- pop tosl
- pop tosh ; index
- pop zl
- pop zh ; limit
- push zh
- push zl
- push tosh
- push tosl
- add tosl, zl
- adc tosh, zh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/icompare.asm b/amforth-6.5/avr8/words/icompare.asm
deleted file mode 100644
index f0fbab5..0000000
--- a/amforth-6.5/avr8/words/icompare.asm
+++ /dev/null
@@ -1,103 +0,0 @@
-; ( r-addr r-len f-addr f-len -- f)
-; Tools
-; compares string in RAM with string in flash. f is zero if equal like COMPARE
-VE_ICOMPARE:
- .dw $ff08
- .db "icompare"
- .dw VE_HEAD
- .set VE_HEAD = VE_ICOMPARE
-XT_ICOMPARE:
- .dw DO_COLON
-PFA_ICOMPARE:
- .dw XT_TO_R ; ( -- r-addr r-len f-addr)
- .dw XT_OVER ; ( -- r-addr r-len f-addr r-len)
- .dw XT_R_FROM ; ( -- r-addr r-len f-addr r-len f-len )
- .dw XT_NOTEQUAL ; ( -- r-addr r-len f-addr flag )
- .dw XT_DOCONDBRANCH
- .dw PFA_ICOMPARE_SAMELEN
- .dw XT_2DROP
- .dw XT_DROP
- .dw XT_TRUE
- .dw XT_EXIT
-PFA_ICOMPARE_SAMELEN:
- .dw XT_SWAP ; ( -- r-addr f-addr len )
- .dw XT_ZERO
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- .dw PFA_ICOMPARE_DONE
- .dw XT_DODO
-PFA_ICOMPARE_LOOP:
- ; ( r-addr f-addr --)
- .dw XT_OVER
- .dw XT_FETCH
-.if WANT_IGNORECASE == 1
- .dw XT_ICOMPARE_LC
-.endif
- .dw XT_OVER
- .dw XT_FETCHI ; ( -- r-addr f-addr r-cc f- cc)
-.if WANT_IGNORECASE == 1
- .dw XT_ICOMPARE_LC
-.endif
- ; flash strings are zero-padded at the last cell
- ; that means: if the flash cell is less $0100, than mask the
- ; high byte in the ram cell
- .dw XT_DUP
- ;.dw XT_BYTESWAP
- .dw XT_DOLITERAL
- .dw $100
- .dw XT_ULESS
- .dw XT_DOCONDBRANCH
- .dw PFA_ICOMPARE_LASTCELL
- .dw XT_SWAP
- .dw XT_DOLITERAL
- .dw $00FF
- .dw XT_AND ; the final swap can be omitted
-PFA_ICOMPARE_LASTCELL:
- .dw XT_NOTEQUAL
- .dw XT_DOCONDBRANCH
- .dw PFA_ICOMPARE_NEXTLOOP
- .dw XT_2DROP
- .dw XT_TRUE
- .dw XT_UNLOOP
- .dw XT_EXIT
-PFA_ICOMPARE_NEXTLOOP:
- .dw XT_1PLUS
- .dw XT_SWAP
- .dw XT_CELLPLUS
- .dw XT_SWAP
- .dw XT_DOLITERAL
- .dw 2
- .dw XT_DOPLUSLOOP
- .dw PFA_ICOMPARE_LOOP
-PFA_ICOMPARE_DONE:
- .dw XT_2DROP
- .dw XT_ZERO
- .dw XT_EXIT
-
-.if WANT_IGNORECASE == 1
-; ( cc1 cc2 -- f)
-; Tools
-; compares two packed characters
-;VE_ICOMPARELC:
-; .dw $ff08
-; .db "icompare-lower"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_ICOMPARELC
-XT_ICOMPARE_LC:
- .dw DO_COLON
-PFA_ICOMPARE_LC:
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw $00ff
- .dw XT_AND
- .dw XT_TOLOWER
- .dw XT_SWAP
- .dw XT_BYTESWAP
- .dw XT_DOLITERAL
- .dw $00ff
- .dw XT_AND
- .dw XT_TOLOWER
- .dw XT_BYTESWAP
- .dw XT_OR
- .dw XT_EXIT
-.endif
diff --git a/amforth-6.5/avr8/words/icount.asm b/amforth-6.5/avr8/words/icount.asm
deleted file mode 100644
index d71ef13..0000000
--- a/amforth-6.5/avr8/words/icount.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( addr -- addr+1 n )
-; Tools
-; get count information out of a counted string in flash
-VE_ICOUNT:
- .dw $ff06
- .db "icount"
- .dw VE_HEAD
- .set VE_HEAD = VE_ICOUNT
-XT_ICOUNT:
- .dw DO_COLON
-PFA_ICOUNT:
- .dw XT_DUP
- .dw XT_1PLUS
- .dw XT_SWAP
- .dw XT_FETCHI
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/immediate-q.asm b/amforth-6.5/avr8/words/immediate-q.asm
deleted file mode 100644
index 36fb29a..0000000
--- a/amforth-6.5/avr8/words/immediate-q.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( flagset -- +/-1 )
-; Tools
-; return +1 if immediate, -1 otherwise, flag from name>flags
-;VE_IMMEDIATEQ:
-; .dw $ff06
-; .db "immediate?"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_IMMEDIATEQ
-XT_IMMEDIATEQ:
- .dw DO_COLON
-PFA_IMMEDIATEQ:
- .dw XT_DOLITERAL
- .dw $8000
- .dw XT_AND
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(IMMEDIATEQ1)
- .dw XT_ONE
- .dw XT_EXIT
-IMMEDIATEQ1:
- ; not immediate
- .dw XT_TRUE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/immediate.asm b/amforth-6.5/avr8/words/immediate.asm
deleted file mode 100644
index 6a2370d..0000000
--- a/amforth-6.5/avr8/words/immediate.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- )
-; Compiler
-; set immediate flag for the most recent word definition
-VE_IMMEDIATE:
- .dw $ff09
- .db "immediate",0
- .dw VE_HEAD
- .set VE_HEAD = VE_IMMEDIATE
-XT_IMMEDIATE:
- .dw DO_COLON
-PFA_IMMEDIATE:
- .dw XT_GET_CURRENT
- .dw XT_FETCHE
- .dw XT_DUP
- .dw XT_FETCHI
- .dw XT_DOLITERAL
- .dw $7fff
- .dw XT_AND
- .dw XT_SWAP
- .dw XT_STOREI
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/init-ram.asm b/amforth-6.5/avr8/words/init-ram.asm
deleted file mode 100644
index cd672bd..0000000
--- a/amforth-6.5/avr8/words/init-ram.asm
+++ /dev/null
@@ -1,48 +0,0 @@
-; ( e-addr r-addr len -- )
-; Tools
-; copy len cells from eeprom to ram
-VE_EE2RAM:
- .dw $ff06
- .db "ee>ram"
- .dw VE_HEAD
- .set VE_HEAD = VE_EE2RAM
-XT_EE2RAM:
- .dw DO_COLON
-PFA_EE2RAM: ; ( -- )
- .dw XT_ZERO
- .dw XT_DODO
-PFA_EE2RAM_1:
- ; ( -- e-addr r-addr )
- .dw XT_OVER
- .dw XT_FETCHE
- .dw XT_OVER
- .dw XT_STORE
- .dw XT_CELLPLUS
- .dw XT_SWAP
- .dw XT_CELLPLUS
- .dw XT_SWAP
- .dw XT_DOLOOP
- .dw PFA_EE2RAM_1
-PFA_EE2RAM_2:
- .dw XT_2DROP
- .dw XT_EXIT
-
-; ( -- )
-; Tools
-; setup the default user area from eeprom
-VE_INIT_RAM:
- .dw $ff08
- .db "init-ram"
- .dw VE_HEAD
- .set VE_HEAD = VE_INIT_RAM
-XT_INIT_RAM:
- .dw DO_COLON
-PFA_INI_RAM: ; ( -- )
- .dw XT_DOLITERAL
- .dw EE_INITUSER
- .dw XT_UP_FETCH
- .dw XT_DOLITERAL
- .dw SYSUSERSIZE
- .dw XT_2SLASH
- .dw XT_EE2RAM
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/int-fetch.asm b/amforth-6.5/avr8/words/int-fetch.asm
deleted file mode 100644
index f0c713a..0000000
--- a/amforth-6.5/avr8/words/int-fetch.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( i -- xt )
-; Interrupt
-; fetches XT from interrupt vector i
-VE_INTFETCH:
- .dw $ff04
- .db "int@"
- .dw VE_HEAD
- .set VE_HEAD = VE_INTFETCH
-XT_INTFETCH:
- .dw DO_COLON
-PFA_INTFETCH:
- .dw XT_DOLITERAL
- .dw intvec
- .dw XT_PLUS
- .dw XT_FETCHE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/int-num.asm b/amforth-6.5/avr8/words/int-num.asm
deleted file mode 100644
index 31f51df..0000000
--- a/amforth-6.5/avr8/words/int-num.asm
+++ /dev/null
@@ -1,12 +0,0 @@
-; ( -- n )
-; Interrupt
-; number of interrupt vectors (0 based)
-VE_NUMINT:
- .dw $ff04
- .db "#int"
- .dw VE_HEAD
- .set VE_HEAD = VE_NUMINT
-XT_NUMINT:
- .dw PFA_DOVARIABLE
-PFA_NUMINT:
- .dw INTVECTORS
diff --git a/amforth-6.5/avr8/words/int-off.asm b/amforth-6.5/avr8/words/int-off.asm
deleted file mode 100644
index 4301404..0000000
--- a/amforth-6.5/avr8/words/int-off.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( -- )
-; Interrupt
-; turns off all interrupts
-VE_INTOFF:
- .dw $ff04
- .db "-int"
- .dw VE_HEAD
- .set VE_HEAD = VE_INTOFF
-XT_INTOFF:
- .dw PFA_INTOFF
-PFA_INTOFF:
- cli
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/int-on.asm b/amforth-6.5/avr8/words/int-on.asm
deleted file mode 100644
index 8b909da..0000000
--- a/amforth-6.5/avr8/words/int-on.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( -- )
-; Interrupt
-; turns on all interrupts
-VE_INTON:
- .dw $ff04
- .db "+int"
- .dw VE_HEAD
- .set VE_HEAD = VE_INTON
-XT_INTON:
- .dw PFA_INTON
-PFA_INTON:
- sei
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/int-store.asm b/amforth-6.5/avr8/words/int-store.asm
deleted file mode 100644
index 9189ba0..0000000
--- a/amforth-6.5/avr8/words/int-store.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( xt i -- )
-; Interrupt
-; stores XT as interrupt vector i
-VE_INTSTORE:
- .dw $ff04
- .db "int!"
- .dw VE_HEAD
- .set VE_HEAD = VE_INTSTORE
-XT_INTSTORE:
- .dw DO_COLON
-PFA_INTSTORE:
- .dw XT_DOLITERAL
- .dw intvec
- .dw XT_PLUS
- .dw XT_STOREE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/int-trap.asm b/amforth-6.5/avr8/words/int-trap.asm
deleted file mode 100644
index dd3170f..0000000
--- a/amforth-6.5/avr8/words/int-trap.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( i -- )
-; Interrupt
-; trigger an interrupt
-VE_INTTRAP:
- .dw $ff08
- .db "int-trap"
- .dw VE_HEAD
- .set VE_HEAD = VE_INTTRAP
-XT_INTTRAP:
- .dw PFA_INTTRAP
-PFA_INTTRAP:
- mov isrflag, tosl
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/invert.asm b/amforth-6.5/avr8/words/invert.asm
deleted file mode 100644
index 84d7a1d..0000000
--- a/amforth-6.5/avr8/words/invert.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n1 -- n2)
-; Arithmetics
-; 1-complement of TOS
-VE_INVERT:
- .dw $ff06
- .db "invert"
- .dw VE_HEAD
- .set VE_HEAD = VE_INVERT
-XT_INVERT:
- .dw PFA_INVERT
-PFA_INVERT:
- com tosl
- com tosh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/irqcnt.asm b/amforth-6.5/avr8/words/irqcnt.asm
deleted file mode 100644
index edb8a39..0000000
--- a/amforth-6.5/avr8/words/irqcnt.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( i -- xt )
-; Interrupt
-; fetches XT from interrupt vector i
-VE_IRQCNTADDR:
- .dw $ff06
- .db "irq[]#"
- .dw VE_HEAD
- .set VE_HEAD = VE_IRQCNTADDR
-XT_IRQCNTADDR:
- .dw DO_COLON
-PFA_IRQCNTADDR:
- .dw XT_DOLITERAL
- .dw intcnt
- .dw XT_PLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/isr-end.asm b/amforth-6.5/avr8/words/isr-end.asm
deleted file mode 100644
index 7fe6132..0000000
--- a/amforth-6.5/avr8/words/isr-end.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- )
-; Interrupt
-; re-enables interrupts in an ISR
-;VE_ISREND:
-; .dw $ff07
-; .db "isr-end",0
-; .dw VE_HEAD
-; .set VE_HEAD = VE_ISREND
-XT_ISREND:
- .dw PFA_ISREND
-PFA_ISREND:
- rcall PFA_ISREND1 ; clear the interrupt flag for the controller
- jmp_ DO_NEXT
-PFA_ISREND1:
- reti
diff --git a/amforth-6.5/avr8/words/isr-exec.asm b/amforth-6.5/avr8/words/isr-exec.asm
deleted file mode 100644
index 6c1a379..0000000
--- a/amforth-6.5/avr8/words/isr-exec.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( n -- )
-; Interrupt
-; executes an interrupt service routine
-;VE_ISREXEC:
-; .dw $ff08
-; .db "isr-exec"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_ISREXEC
-XT_ISREXEC:
- .dw DO_COLON
-PFA_ISREXEC:
- .dw XT_INTFETCH
- .dw XT_EXECUTE
- .dw XT_ISREND
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/itype.asm b/amforth-6.5/avr8/words/itype.asm
deleted file mode 100644
index 7831344..0000000
--- a/amforth-6.5/avr8/words/itype.asm
+++ /dev/null
@@ -1,74 +0,0 @@
-; ( addr n -- )
-; Tools
-; reads string from flash and prints it
-VE_ITYPE:
- .dw $ff05
- .db "itype",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ITYPE
-XT_ITYPE:
- .dw DO_COLON
-PFA_ITYPE:
- .dw XT_DUP ; ( --addr len len)
- .dw XT_2SLASH ; ( -- addr len len/2
- .dw XT_TUCK ; ( -- addr len/2 len len/2
- .dw XT_2STAR ; ( -- addr len/2 len len'
- .dw XT_MINUS ; ( -- addr len/2 rem
- .dw XT_TO_R
- .dw XT_ZERO
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- .dw PFA_ITYPE2
- .dw XT_DODO
-PFA_ITYPE1:
- .dw XT_DUP ; ( -- addr addr )
- .dw XT_FETCHI ; ( -- addr c1c2 )
- .dw XT_DUP
- .dw XT_LOWEMIT
- .dw XT_HIEMIT
- .dw XT_1PLUS ; ( -- addr+cell )
- .dw XT_DOLOOP
- .dw PFA_ITYPE1
-PFA_ITYPE2:
- .dw XT_R_FROM
- .dw XT_GREATERZERO
- .dw XT_DOCONDBRANCH
- .dw PFA_ITYPE3
- .dw XT_DUP ; make sure the drop below has always something to do
- .dw XT_FETCHI
- .dw XT_LOWEMIT
-PFA_ITYPE3:
- .dw XT_DROP
- .dw XT_EXIT
-
-; ( w -- )
-; R( -- )
-; content of cell fetched on stack.
-;VE_HIEMIT:
-; .dw $ff06
-; .db "hiemit"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_HIEMIT
-XT_HIEMIT:
- .dw DO_COLON
-PFA_HIEMIT:
- .dw XT_BYTESWAP
- .dw XT_LOWEMIT
- .dw XT_EXIT
-
-; ( w -- )
-; R( -- )
-; content of cell fetched on stack.
-;VE_LOWEMIT:
-; .dw $ff07
-; .db "lowemit"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_LOWEMIT
-XT_LOWEMIT:
- .dw DO_COLON
-PFA_LOWEMIT:
- .dw XT_DOLITERAL
- .dw $00ff
- .dw XT_AND
- .dw XT_EMIT
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/j.asm b/amforth-6.5/avr8/words/j.asm
deleted file mode 100644
index 30ba24b..0000000
--- a/amforth-6.5/avr8/words/j.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- n ) (R: loop-sys1 loop-sys2 -- loop-sys1 loop-sys2)
-; Compiler
-; loop counter of outer loop
-VE_J:
- .dw $FF01
- .db "j",0
- .dw VE_HEAD
- .set VE_HEAD = VE_J
-XT_J:
- .dw DO_COLON
-PFA_J:
- .dw XT_RP_FETCH
- .dw XT_DOLITERAL
- .dw 7
- .dw XT_PLUS
- .dw XT_FETCH
- .dw XT_RP_FETCH
- .dw XT_DOLITERAL
- .dw 9
- .dw XT_PLUS
- .dw XT_FETCH
- .dw XT_PLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/l_mark.asm b/amforth-6.5/avr8/words/l_mark.asm
deleted file mode 100644
index 9d5c5ae..0000000
--- a/amforth-6.5/avr8/words/l_mark.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( -- dest )
-; Compiler
-; place destination for backward branch
-;VE_LMARK:
-; .dw $ff05
-; .db "<mark"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_LMARK
-XT_LMARK:
- .dw DO_COLON
-PFA_LMARK:
- .dw XT_DP
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/l_resolve.asm b/amforth-6.5/avr8/words/l_resolve.asm
deleted file mode 100644
index 4e7e472..0000000
--- a/amforth-6.5/avr8/words/l_resolve.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( dest -- )
-; Compiler
-; resolve backward branch
-;VE_LRESOLVE:
-; .dw $ff08
-; .db "<resolve"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_LRESOLVE
-XT_LRESOLVE:
- .dw DO_COLON
-PFA_LRESOLVE:
- .dw XT_QSTACK
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/latest.asm b/amforth-6.5/avr8/words/latest.asm
deleted file mode 100644
index 33088e6..0000000
--- a/amforth-6.5/avr8/words/latest.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- addr )
-; System Variable
-; system state
-VE_LATEST:
- .dw $ff06
- .db "latest"
- .dw VE_HEAD
- .set VE_HEAD = VE_LATEST
-XT_LATEST:
- .dw PFA_DOVARIABLE
-PFA_LATEST:
- .dw ram_latest
-
-.dseg
-ram_latest: .byte 2
-.cseg \ No newline at end of file
diff --git a/amforth-6.5/avr8/words/less.asm b/amforth-6.5/avr8/words/less.asm
deleted file mode 100644
index 8426acd..0000000
--- a/amforth-6.5/avr8/words/less.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( n1 n2 -- flag)
-; Compare
-; true if n1 is less than n2
- VE_LESS:
- .dw $ff01
- .db "<",0
- .dw VE_HEAD
- .set VE_HEAD = VE_LESS
-XT_LESS:
- .dw PFA_LESS
-PFA_LESS:
- ld temp2, Y+
- ld temp3, Y+
- cp temp2, tosl
- cpc temp3, tosh
-PFA_LESSDONE:
- brge PFA_ZERO1
- rjmp PFA_TRUE1
diff --git a/amforth-6.5/avr8/words/lesszero.asm b/amforth-6.5/avr8/words/lesszero.asm
deleted file mode 100644
index 7a5d291..0000000
--- a/amforth-6.5/avr8/words/lesszero.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n1 -- flag)
-; Compare
-; compare with zero
-VE_ZEROLESS:
- .dw $ff02
- .db "0<"
- .dw VE_HEAD
- .set VE_HEAD = VE_ZEROLESS
-XT_ZEROLESS:
- .dw PFA_ZEROLESS
-PFA_ZEROLESS:
- sbrc tosh,7
- rjmp PFA_TRUE1
- rjmp PFA_ZERO1
diff --git a/amforth-6.5/avr8/words/log2.asm b/amforth-6.5/avr8/words/log2.asm
deleted file mode 100644
index 0dcc511..0000000
--- a/amforth-6.5/avr8/words/log2.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( n1 -- n2 )
-; Arithmetics
-; logarithm to base 2 or highest set bitnumber
-VE_LOG2:
- .dw $ff04
- .db "log2"
- .dw VE_HEAD
- .set VE_HEAD = VE_LOG2
-XT_LOG2:
- .dw PFA_LOG2
-PFA_LOG2:
- movw zl, tosl
- clr tosh
- ldi tosl, 16
-PFA_LOG2_1:
- dec tosl
- brmi PFA_LOG2_2 ; wrong data
- lsl zl
- rol zh
- brcc PFA_LOG2_1
- jmp_ DO_NEXT
-
-PFA_LOG2_2:
- dec tosh
- jmp_ DO_NEXT
- \ No newline at end of file
diff --git a/amforth-6.5/avr8/words/lp.asm b/amforth-6.5/avr8/words/lp.asm
deleted file mode 100644
index 34fb85a..0000000
--- a/amforth-6.5/avr8/words/lp.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( -- addr )
-; System Variable
-; leave stack pointer
-VE_LP:
- .dw $ff02
- .db "lp"
- .dw VE_HEAD
- .set VE_HEAD = VE_LP
-XT_LP:
- .dw PFA_DOVARIABLE
-PFA_LP:
- .dw ram_lp
-
-.dseg
-ram_lp: .byte 2
-.cseg
-
diff --git a/amforth-6.5/avr8/words/lp0.asm b/amforth-6.5/avr8/words/lp0.asm
deleted file mode 100644
index 919c9e0..0000000
--- a/amforth-6.5/avr8/words/lp0.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- addr)
-; Stack
-; start address of leave stack
-VE_LP0:
- .dw $ff03
- .db "lp0",0
- .dw VE_HEAD
- .set VE_HEAD = VE_LP0
-XT_LP0:
- .dw PFA_DOVALUE1
-PFA_LP0:
- .dw CFG_LP0
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/lshift.asm b/amforth-6.5/avr8/words/lshift.asm
deleted file mode 100644
index 2016525..0000000
--- a/amforth-6.5/avr8/words/lshift.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( n1 n2 -- n3)
-; Arithmetics
-; logically shift n1 left n2 times
-VE_LSHIFT:
- .dw $ff06
- .db "lshift"
- .dw VE_HEAD
- .set VE_HEAD = VE_LSHIFT
-XT_LSHIFT:
- .dw PFA_LSHIFT
-PFA_LSHIFT:
- movw zl, tosl
- loadtos
-PFA_LSHIFT1:
- sbiw zl, 1
- brmi PFA_LSHIFT2
- lsl tosl
- rol tosh
- rjmp PFA_LSHIFT1
-PFA_LSHIFT2:
- jmp_ DO_NEXT
-
diff --git a/amforth-6.5/avr8/words/marker.asm b/amforth-6.5/avr8/words/marker.asm
deleted file mode 100644
index 3210fff..0000000
--- a/amforth-6.5/avr8/words/marker.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- e-addr )
-; System Value
-; The eeprom address until which MARKER saves and restores the eeprom data.
-VE_MARKER:
- .dw $ff08
- .db "(marker)"
- .dw VE_HEAD
- .set VE_HEAD = VE_MARKER
-XT_MARKER:
- .dw PFA_DOVALUE1
-PFA_MARKER:
- .dw EE_MARKER
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/minus.asm b/amforth-6.5/avr8/words/minus.asm
deleted file mode 100644
index e1922ce..0000000
--- a/amforth-6.5/avr8/words/minus.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( n1|u1 n2|u2 -- n3|u3 )
-; Arithmetics
-; subtract n2 from n1
-VE_MINUS:
- .dw $ff01
- .db "-",0
- .dw VE_HEAD
- .set VE_HEAD = VE_MINUS
-XT_MINUS:
- .dw PFA_MINUS
-PFA_MINUS:
- ld temp0, Y+
- ld temp1, Y+
- sub temp0, tosl
- sbc temp1, tosh
- movw tosl, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/mplus.asm b/amforth-6.5/avr8/words/mplus.asm
deleted file mode 100644
index 28f76bd..0000000
--- a/amforth-6.5/avr8/words/mplus.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( d1 n1 -- d2)
-; Arithmetics
-; add a number to a double cell
-VE_MPLUS:
- .dw $ff02
- .db "m+"
- .dw VE_HEAD
- .set VE_HEAD = VE_MPLUS
-XT_MPLUS:
- .dw DO_COLON
-PFA_MPLUS:
- .dw XT_S2D
- .dw XT_DPLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/mstar.asm b/amforth-6.5/avr8/words/mstar.asm
deleted file mode 100644
index a25d4a1..0000000
--- a/amforth-6.5/avr8/words/mstar.asm
+++ /dev/null
@@ -1,37 +0,0 @@
-; ( n1 n2 -- d)
-; Arithmetics
-; multiply 2 cells to a double cell
-VE_MSTAR:
- .dw $ff02
- .db "m*"
- .dw VE_HEAD
- .set VE_HEAD = VE_MSTAR
-XT_MSTAR:
- .dw PFA_MSTAR
-PFA_MSTAR:
- movw temp0, tosl
- loadtos
- movw temp2, tosl
- ; high cell ah*bh
- muls temp3, temp1
- movw temp4, r0
- ; low cell al*bl
- mul temp2, temp0
- movw tosl, r0
- ; signed ah*bl
- mulsu temp3, temp0
- sbc temp5, zeroh
- add tosh, r0
- adc temp4, r1
- adc temp5, zeroh
-
- ; signed al*bh
- mulsu temp1, temp2
- sbc temp5, zeroh
- add tosh, r0
- adc temp4, r1
- adc temp5, zeroh
-
- savetos
- movw tosl, temp4
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/n-spi.asm b/amforth-6.5/avr8/words/n-spi.asm
deleted file mode 100644
index 45f6cdc..0000000
--- a/amforth-6.5/avr8/words/n-spi.asm
+++ /dev/null
@@ -1,55 +0,0 @@
-; ( addr len -- )
-; MCU
-; read len bytes from SPI to addr
-VE_N_SPIR:
- .dw $ff05
- .db "n@spi",0
- .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIR
-XT_N_SPIR:
- .dw PFA_N_SPIR
-PFA_N_SPIR:
- movw temp0, tosl
- loadtos
- movw zl, tosl
- movw tosl, temp0
-PFA_N_SPIR_LOOP:
- out_ SPDR, zerol
-PFA_N_SPIR_LOOP1:
- in_ temp2, SPSR
- sbrs temp2, SPIF
- rjmp PFA_N_SPIR_LOOP1
- in_ temp2, SPDR
- st Z+, temp2
- sbiw tosl, 1
- brne PFA_N_SPIR_LOOP
- loadtos
- jmp_ DO_NEXT
-
-; ( addr len -- )
-; MCU
-; write len bytes to SPI from addr
-VE_N_SPIW:
- .dw $ff05
- .db "n!spi",0
- .dw VE_HEAD
- .set VE_HEAD = VE_N_SPIW
-XT_N_SPIW:
- .dw PFA_N_SPIW
-PFA_N_SPIW:
- movw temp0, tosl
- loadtos
- movw zl, tosl
- movw tosl, temp0
-PFA_N_SPIW_LOOP:
- ld temp2, Z+
- out_ SPDR, temp2
-PFA_N_SPIW_LOOP1:
- in_ temp2, SPSR
- sbrs temp2, SPIF
- rjmp PFA_N_SPIW_LOOP1
- in_ temp2, SPDR ; ignore the data
- sbiw tosl, 1
- brne PFA_N_SPIW_LOOP
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/n_r_from.asm b/amforth-6.5/avr8/words/n_r_from.asm
deleted file mode 100644
index d69dc1b..0000000
--- a/amforth-6.5/avr8/words/n_r_from.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- x-n .. x-1 n ) (R: x-n .. x-1 n -- )
-; Stack
-; move n items from return stack to data stack
-VE_N_R_FROM:
- .dw $ff03
- .db "nr>",0
- .dw VE_HEAD
- .set VE_HEAD = VE_N_R_FROM
-XT_N_R_FROM:
- .dw PFA_N_R_FROM
-PFA_N_R_FROM:
- savetos
- pop zh
- pop zl
- mov temp0, zl
-PFA_N_R_FROM1:
- pop tosl
- pop tosh
- savetos
- dec temp0
- brne PFA_N_R_FROM1
- movw tosl, zl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/n_to_r.asm b/amforth-6.5/avr8/words/n_to_r.asm
deleted file mode 100644
index 9efdaa6..0000000
--- a/amforth-6.5/avr8/words/n_to_r.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( x-n .. x-1 n -- ) (R: -- x-n .. x-1 n)
-; Stack
-; move n items from data stack to return stack
-VE_N_TO_R:
- .dw $ff03
- .db "n>r",0
- .dw VE_HEAD
- .set VE_HEAD = VE_N_TO_R
-XT_N_TO_R:
- .dw PFA_N_TO_R
-PFA_N_TO_R:
- movw zl, tosl
- mov temp0, tosl
-PFA_N_TO_R1:
- loadtos
- push tosh
- push tosl
- dec temp0
- brne PFA_N_TO_R1
- push zl
- push zh
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/name2flags.asm b/amforth-6.5/avr8/words/name2flags.asm
deleted file mode 100644
index 12f618e..0000000
--- a/amforth-6.5/avr8/words/name2flags.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( nt -- f )
-; Tools
-; get the flags from a name token
-VE_NAME2FLAGS:
- .dw $ff0a
- .db "name>flags"
- .dw VE_HEAD
- .set VE_HEAD = VE_NAME2FLAGS
-XT_NAME2FLAGS:
- .dw DO_COLON
-PFA_NAME2FLAGS:
- .dw XT_FETCHI ; skip to link field
- .dw XT_DOLITERAL
- .dw $ff00
- .dw XT_AND
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/negate.asm b/amforth-6.5/avr8/words/negate.asm
deleted file mode 100644
index 6a88d58..0000000
--- a/amforth-6.5/avr8/words/negate.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n1 -- n2 )
-; Logic
-; 2-complement
-VE_NEGATE:
- .dw $ff06
- .db "negate"
- .dw VE_HEAD
- .set VE_HEAD = VE_NEGATE
-XT_NEGATE:
- .dw DO_COLON
-PFA_NEGATE:
- .dw XT_INVERT
- .dw XT_1PLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/newest.asm b/amforth-6.5/avr8/words/newest.asm
deleted file mode 100644
index 62839fc..0000000
--- a/amforth-6.5/avr8/words/newest.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- addr )
-; System Variable
-; system state
-VE_NEWEST:
- .dw $ff06
- .db "newest"
- .dw VE_HEAD
- .set VE_HEAD = VE_NEWEST
-XT_NEWEST:
- .dw PFA_DOVARIABLE
-PFA_NEWEST:
- .dw ram_newest
-
-.dseg
-ram_newest: .byte 4
-.cseg \ No newline at end of file
diff --git a/amforth-6.5/avr8/words/nfa2cfa.asm b/amforth-6.5/avr8/words/nfa2cfa.asm
deleted file mode 100644
index ab1b230..0000000
--- a/amforth-6.5/avr8/words/nfa2cfa.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( nt -- xt )
-; Tools
-; get the XT from a name token
-VE_NFA2CFA:
- .dw $ff07
- .db "nfa>cfa"
- .dw VE_HEAD
- .set VE_HEAD = VE_NFA2CFA
-XT_NFA2CFA:
- .dw DO_COLON
-PFA_NFA2CFA:
- .dw XT_NFA2LFA ; skip to link field
- .dw XT_1PLUS ; next is the execution token
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/nfa2lfa.asm b/amforth-6.5/avr8/words/nfa2lfa.asm
deleted file mode 100644
index 945fb64..0000000
--- a/amforth-6.5/avr8/words/nfa2lfa.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( nfa -- lfa )
-; System
-; get the link field address from the name field address
-VE_NFA2LFA:
- .dw $ff07
- .db "nfa>lfa",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NFA2LFA
-XT_NFA2LFA:
- .dw DO_COLON
-PFA_NFA2LFA:
- .dw XT_NAME2STRING
- .dw XT_1PLUS
- .dw XT_2SLASH
- .dw XT_PLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/nip.asm b/amforth-6.5/avr8/words/nip.asm
deleted file mode 100644
index cfa1d1a..0000000
--- a/amforth-6.5/avr8/words/nip.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( n1 n2 -- n2 )
-; Stack
-; Remove Second of Stack
-VE_NIP:
- .dw $ff03
- .db "nip",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NIP
-XT_NIP:
- .dw PFA_NIP
-PFA_NIP:
- adiw yl, 2
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/not.asm b/amforth-6.5/avr8/words/not.asm
deleted file mode 100644
index 26aa5c4..0000000
--- a/amforth-6.5/avr8/words/not.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( flag -- flag' )
-; Logic
-; identical to 0=
-VE_NOT:
- .dw $ff03
- .db "not",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOT
-XT_NOT:
- .dw DO_COLON
-PFA_NOT:
- .dw XT_ZEROEQUAL
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/notequalzero.asm b/amforth-6.5/avr8/words/notequalzero.asm
deleted file mode 100644
index 5088bf3..0000000
--- a/amforth-6.5/avr8/words/notequalzero.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n -- flag )
-; Compare
-; true if n is not zero
-VE_NOTZEROEQUAL:
- .dw $ff03
- .db "0<>",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOTZEROEQUAL
-XT_NOTZEROEQUAL:
- .dw DO_COLON
-PFA_NOTZEROEQUAL:
- .dw XT_ZEROEQUAL
- .dw XT_ZEROEQUAL
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/or.asm b/amforth-6.5/avr8/words/or.asm
deleted file mode 100644
index 24bc268..0000000
--- a/amforth-6.5/avr8/words/or.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( n1 n2 -- n3 )
-; Logic
-; logical or
-VE_OR:
- .dw $ff02
- .db "or"
- .dw VE_HEAD
- .set VE_HEAD = VE_OR
-XT_OR:
- .dw PFA_OR
-PFA_OR:
- ld temp0, Y+
- ld temp1, Y+
- or tosl, temp0
- or tosh, temp1
- jmp_ DO_NEXT
-
diff --git a/amforth-6.5/avr8/words/over.asm b/amforth-6.5/avr8/words/over.asm
deleted file mode 100644
index 97ca242..0000000
--- a/amforth-6.5/avr8/words/over.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( x1 x2 -- x1 x2 x1 )
-; Stack
-; Place a copy of x1 on top of the stack
-VE_OVER:
- .dw $ff04
- .db "over"
- .dw VE_HEAD
- .set VE_HEAD = VE_OVER
-XT_OVER:
- .dw PFA_OVER
-PFA_OVER:
- savetos
- ldd tosl, Y+2
- ldd tosh, Y+3
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/pause.asm b/amforth-6.5/avr8/words/pause.asm
deleted file mode 100644
index 747fde4..0000000
--- a/amforth-6.5/avr8/words/pause.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( -- )
-; Multitasking
-; Fetch pause vector and execute it. may make a context/task switch
-VE_PAUSE:
- .dw $ff05
- .db "pause",0
- .dw VE_HEAD
- .set VE_HEAD = VE_PAUSE
-XT_PAUSE:
- .dw PFA_DODEFER1
-PFA_PAUSE:
- .dw ram_pause
- .dw XT_RDEFERFETCH
- .dw XT_RDEFERSTORE
-
-.dseg
-ram_pause: .byte 2
-.cseg
diff --git a/amforth-6.5/avr8/words/plus.asm b/amforth-6.5/avr8/words/plus.asm
deleted file mode 100644
index 1b2a6c4..0000000
--- a/amforth-6.5/avr8/words/plus.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( n1 n2 -- n3)
-; Arithmetics
-; add n1 and n2
-VE_PLUS:
- .dw $ff01
- .db "+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_PLUS
-XT_PLUS:
- .dw PFA_PLUS
-PFA_PLUS:
- ld temp0, Y+
- ld temp1, Y+
- add tosl, temp0
- adc tosh, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/plusstore.asm b/amforth-6.5/avr8/words/plusstore.asm
deleted file mode 100644
index 344670b..0000000
--- a/amforth-6.5/avr8/words/plusstore.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( n a-addr -- )
-; Arithmetics
-; add n to content of RAM address a-addr
-VE_PLUSSTORE:
- .dw $ff02
- .db "+!"
- .dw VE_HEAD
- .set VE_HEAD = VE_PLUSSTORE
-XT_PLUSSTORE:
- .dw PFA_PLUSSTORE
-PFA_PLUSSTORE:
- movw zl, tosl
- loadtos
- ldd temp2, Z+0
- ldd temp3, Z+1
- add tosl, temp2
- adc tosh, temp3
- std Z+0, tosl
- std Z+1, tosh
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/popcnt.asm b/amforth-6.5/avr8/words/popcnt.asm
deleted file mode 100644
index 66f8f47..0000000
--- a/amforth-6.5/avr8/words/popcnt.asm
+++ /dev/null
@@ -1,29 +0,0 @@
-; ( n1 -- n2 )
-; Arithmetics
-; count the Number of 1 bits (population count)
-VE_POPCNT:
- .dw $ff06
- .db "popcnt"
- .dw VE_HEAD
- .set VE_HEAD = VE_POPCNT
-XT_POPCNT:
- .dw PFA_POPCNT
-PFA_POPCNT:
- movw zl, tosl
- clr tosl
- rcall PFA_POPCNT1
- mov zl, zh
- rcall PFA_POPCNT1
- clr tosh
- jmp_ DO_NEXT
-
-PFA_POPCNT1:
- ldi tosh, 8
-PFA_POPCNT2:
- ror zl
- ;breq PFA_POPCNT3
- adc tosl, zeroh
- dec tosh
- brne PFA_POPCNT2
-POPCNT3:
- ret \ No newline at end of file
diff --git a/amforth-6.5/avr8/words/qdup.asm b/amforth-6.5/avr8/words/qdup.asm
deleted file mode 100644
index e65640b..0000000
--- a/amforth-6.5/avr8/words/qdup.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( n1 -- [ n1 n1 ] | 0)
-; Stack
-; duplicate TOS if non-zero
-VE_QDUP:
- .dw $ff04
- .db "?dup"
- .dw VE_HEAD
- .set VE_HEAD = VE_QDUP
-XT_QDUP:
- .dw PFA_QDUP
-PFA_QDUP:
- mov temp0, tosl
- or temp0, tosh
- breq PFA_QDUP1
- savetos
-PFA_QDUP1:
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/r_fetch.asm b/amforth-6.5/avr8/words/r_fetch.asm
deleted file mode 100644
index 06d8ab0..0000000
--- a/amforth-6.5/avr8/words/r_fetch.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( -- n) (R: n -- n )
-; Stack
-; fetch content of TOR
-VE_R_FETCH:
- .dw $ff02
- .db "r@"
- .dw VE_HEAD
- .set VE_HEAD = VE_R_FETCH
-XT_R_FETCH:
- .dw PFA_R_FETCH
-PFA_R_FETCH:
- savetos
- pop tosl
- pop tosh
- push tosh
- push tosl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/r_from.asm b/amforth-6.5/avr8/words/r_from.asm
deleted file mode 100644
index 66c1ebc..0000000
--- a/amforth-6.5/avr8/words/r_from.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- n ) (R: n --)
-; Stack
-; move TOR to TOS
-VE_R_FROM:
- .dw $ff02
- .db "r>"
- .dw VE_HEAD
- .set VE_HEAD = VE_R_FROM
-XT_R_FROM:
- .dw PFA_R_FROM
-PFA_R_FROM:
- savetos
- pop tosl
- pop tosh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/reg-a.asm b/amforth-6.5/avr8/words/reg-a.asm
deleted file mode 100644
index 196ca3c..0000000
--- a/amforth-6.5/avr8/words/reg-a.asm
+++ /dev/null
@@ -1,180 +0,0 @@
-; ( -- n2 )
-; Extended VM
-; Read memory pointed to by register A (Extended VM)
-VE_AFETCH:
- .dw $ff02
- .db "a@"
- .dw VE_HEAD
- .set VE_HEAD = VE_AFETCH
-XT_AFETCH:
- .dw PFA_AFETCH
-PFA_AFETCH:
- savetos
- movw zl, al
- ld tosl, Z+
- ld tosh, Z+
- jmp_ DO_NEXT
-
-; ( n1 -- n2 )
-; Extended VM
-; Read memory pointed to by register A plus offset (Extended VM)
-VE_NAFETCH:
- .dw $ff03
- .db "na@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NAFETCH
-XT_NAFETCH:
- .dw PFA_NAFETCH
-PFA_NAFETCH:
- movw zl, al
- add zl, tosl
- adc zh, tosh
- ld tosl, Z+
- ld tosh, Z+
- jmp_ DO_NEXT
-
-; ( -- n )
-; Extended VM
-; Read memory pointed to by register A, increment A by 1 cell (Extended VM)
-VE_AFETCHPLUS:
- .dw $ff03
- .db "a@+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_AFETCHPLUS
-XT_AFETCHPLUS:
- .dw PFA_AFETCHPLUS
-PFA_AFETCHPLUS:
- savetos
- movw zl, al
- ld tosl, Z+
- ld tosh, Z+
- movw al, zl
- jmp_ DO_NEXT
-
-; ( -- n )
-; Extended VM
-; Read memory pointed to by register A, decrement A by 1 cell (Extended VM)
-VE_AFETCHMINUS:
- .dw $ff03
- .db "a@-",0
- .dw VE_HEAD
- .set VE_HEAD = VE_AFETCHMINUS
-XT_AFETCHMINUS:
- .dw PFA_AFETCHMINUS
-PFA_AFETCHMINUS:
- savetos
- movw zl, al
- ld tosh, -Z ; TODO: check byte order!!
- ld tosl, -Z
- movw al, zl
- jmp_ DO_NEXT
-
-; ( n -- )
-; Extended VM
-; Write memory pointed to by register A (Extended VM)
-VE_ASTORE:
- .dw $ff02
- .db "a!"
- .dw VE_HEAD
- .set VE_HEAD = VE_ASTORE
-XT_ASTORE:
- .dw PFA_ASTORE
-PFA_ASTORE:
- movw zl, al
- st Z+, tosl
- st Z+, tosh
- loadtos
- jmp_ DO_NEXT
-
-; ( n offs -- )
-; Extended VM
-; Write memory pointed to by register A plus offset (Extended VM)
-VE_NASTORE:
- .dw $ff03
- .db "na!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NASTORE
-XT_NASTORE:
- .dw PFA_NASTORE
-PFA_NASTORE:
- movw zl, al
- add zl, tosl
- adc zh, tosh
- loadtos
- st Z+, tosl
- st Z+, tosh
- loadtos
- jmp_ DO_NEXT
-
-; ( -- n2 )
-; Extended VM
-; Write memory pointed to by register A, increment A by 1 cell (Extended VM)
-VE_ASTOREPLUS:
- .dw $ff03
- .db "a!+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ASTOREPLUS
-XT_ASTOREPLUS:
- .dw PFA_ASTOREPLUS
-PFA_ASTOREPLUS:
- movw zl, al
- st Z+, tosl
- st Z+, tosh
- loadtos
- movw al, zl
- jmp_ DO_NEXT
-
-; ( -- n2 )
-; Extended VM
-; Write memory pointed to by register A, decrement A by 1 cell (Extended VM)
-VE_ASTOREMINUS:
- .dw $ff03
- .db "a!-",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ASTOREMINUS
-XT_ASTOREMINUS:
- .dw PFA_ASTOREMINUS
-PFA_ASTOREMINUS:
- movw zl, al
- st -Z, tosh
- st -Z, tosl
- loadtos
- movw al, zl
- jmp_ DO_NEXT
-
-
-
-; ( n -- )
-; Extended VM
-; Write to A register (Extended VM)
-VE_TO_A:
- .dw $ff02
- .db ">a"
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_A
-XT_TO_A:
- .dw PFA_TO_A
-PFA_TO_A:
- movw al, tosl
- loadtos
- jmp_ DO_NEXT
-
-; ( n1 -- n2 )
-; Extended VM
-; read the A register (Extended VM)
-VE_A_FROM:
- .dw $ff02
- .db "a>"
- .dw VE_HEAD
- .set VE_HEAD = VE_A_FROM
-XT_A_FROM:
- .dw PFA_A_FROM
-PFA_A_FROM:
- savetos
- movw tosl, al
- jmp_ DO_NEXT
-
-; for more information read
-; http://www.complang.tuwien.ac.at/anton/euroforth/ef08/papers/pelc.pdf
-; adapted index based access from X/Y registers
-; note: offset is byte address, not cell!
diff --git a/amforth-6.5/avr8/words/reg-b.asm b/amforth-6.5/avr8/words/reg-b.asm
deleted file mode 100644
index 4b77e99..0000000
--- a/amforth-6.5/avr8/words/reg-b.asm
+++ /dev/null
@@ -1,180 +0,0 @@
-; ( -- n2 )
-; Extended VM
-; Read memory pointed to by register B (Extended VM)
-VE_BFETCH:
- .dw $ff02
- .db "b@"
- .dw VE_HEAD
- .set VE_HEAD = VE_BFETCH
-XT_BFETCH:
- .dw PFA_BFETCH
-PFA_BFETCH:
- savetos
- movw zl, bl
- ld tosl, Z+
- ld tosh, Z+
- jmp_ DO_NEXT
-
-; ( n1 -- n2 )
-; Extended VM
-; Read memory pointed to by register B plus offset (Extended VM)
-VE_NBFETCH:
- .dw $ff03
- .db "nb@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NBFETCH
-XT_NBFETCH:
- .dw PFA_NBFETCH
-PFA_NBFETCH:
- movw zl, bl
- add zl, tosl
- adc zh, tosh
- ld tosl, Z+
- ld tosh, Z+
- jmp_ DO_NEXT
-
-; ( -- n )
-; Extended VM
-; Read memory pointed to by register B, increment B by 1 cell (Extended VM)
-VE_BFETCHPLUS:
- .dw $ff03
- .db "b@+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BFETCHPLUS
-XT_BFETCHPLUS:
- .dw PFA_BFETCHPLUS
-PFA_BFETCHPLUS:
- savetos
- movw zl, bl
- ld tosl, Z+
- ld tosh, Z+
- movw bl, zl
- jmp_ DO_NEXT
-
-; ( -- n )
-; Extended VM
-; Read memory pointed to by register B, decrement B by 1 cell (Extended VM)
-VE_BFETCHMINUS:
- .dw $ff03
- .db "b@-",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BFETCHMINUS
-XT_BFETCHMINUS:
- .dw PFA_BFETCHMINUS
-PFA_BFETCHMINUS:
- savetos
- movw zl, bl
- ld tosh, -Z
- ld tosl, -Z
- movw bl, zl
- jmp_ DO_NEXT
-
-; ( n -- )
-; Extended VM
-; Write memory pointed to by register B (Extended VM)
-VE_BSTORE:
- .dw $ff02
- .db "b!"
- .dw VE_HEAD
- .set VE_HEAD = VE_BSTORE
-XT_BSTORE:
- .dw PFA_BSTORE
-PFA_BSTORE:
- movw zl, bl
- st Z+, tosl
- st Z+, tosh
- loadtos
- jmp_ DO_NEXT
-
-; ( n offs -- )
-; Extended VM
-; Write memory pointed to by register B plus offset (Extended VM)
-VE_NBSTORE:
- .dw $ff03
- .db "nb!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NBSTORE
-XT_NBSTORE:
- .dw PFA_NBSTORE
-PFA_NBSTORE:
- movw zl, bl
- add zl, tosl
- adc zh, tosh
- loadtos
- st Z+, tosl
- st Z+, tosh
- loadtos
- jmp_ DO_NEXT
-
-; ( -- n2 )
-; Extended VM
-; Write memory pointed to by register B, increment B by 1 cell (Extended VM)
-VE_BSTOREPLUS:
- .dw $ff03
- .db "b!+",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BSTOREPLUS
-XT_BSTOREPLUS:
- .dw PFA_BSTOREPLUS
-PFA_BSTOREPLUS:
- movw zl, bl
- st Z+, tosl
- st Z+, tosh
- loadtos
- movw bl, zl
- jmp_ DO_NEXT
-
-; ( -- n2 )
-; Extended VM
-; Write memory pointed to by register B, decrement B by 1 cell (Extended VM)
-VE_BSTOREMINUS:
- .dw $ff03
- .db "b!-",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BSTOREMINUS
-XT_BSTOREMINUS:
- .dw PFA_BSTOREMINUS
-PFA_BSTOREMINUS:
- movw zl, bl
- st -Z, tosh
- st -Z, tosl
- loadtos
- movw bl, zl
- jmp_ DO_NEXT
-
-
-
-; ( n -- )
-; Extended VM
-; Write to B register (Extended VM)
-VE_TO_B:
- .dw $ff02
- .db ">b"
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_B
-XT_TO_B:
- .dw PFA_TO_B
-PFA_TO_B:
- movw bl, tosl
- loadtos
- jmp_ DO_NEXT
-
-; ( n1 -- n2 )
-; Extended VM
-; read the B register (Extended VM)
-VE_B_FROM:
- .dw $ff02
- .db "b>"
- .dw VE_HEAD
- .set VE_HEAD = VE_B_FROM
-XT_B_FROM:
- .dw PFA_B_FROM
-PFA_B_FROM:
- savetos
- movw tosl, bl
- jmp_ DO_NEXT
-
-; for more information read
-; http://www.complang.tuwien.ac.at/anton/euroforth/ef08/papers/pelc.pdf
-; adapted index based access from X/Y registers
-; note: offset is byte address, not cell!
diff --git a/amforth-6.5/avr8/words/rot.asm b/amforth-6.5/avr8/words/rot.asm
deleted file mode 100644
index 298b79c..0000000
--- a/amforth-6.5/avr8/words/rot.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( n1 n2 n3 -- n2 n3 n1)
-; Stack
-; rotate the three top level cells
-VE_ROT:
- .dw $ff03
- .db "rot",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ROT
-XT_ROT:
- .dw PFA_ROT
-PFA_ROT:
- movw temp0, tosl
- ld temp2, Y+
- ld temp3, Y+
- loadtos
-
- st -Y, temp3
- st -Y, temp2
- st -Y, temp1
- st -Y, temp0
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/rp0.asm b/amforth-6.5/avr8/words/rp0.asm
deleted file mode 100644
index 1909f1c..0000000
--- a/amforth-6.5/avr8/words/rp0.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( -- addr)
-; Stack
-; start address of return stack
-VE_RP0:
- .dw $ff03
- .db "rp0",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RP0
-XT_RP0:
- .dw DO_COLON
-PFA_RP0:
- .dw XT_DORP0
- .dw XT_FETCH
- .dw XT_EXIT
-
-; ( -- addr)
-; Stack
-; user variable of the address of the initial return stack
-;VE_DORP0:
-; .dw $ff05
-; .db "(rp0)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DORP0
-XT_DORP0:
- .dw PFA_DOUSER
-PFA_DORP0:
- .dw USER_RP
diff --git a/amforth-6.5/avr8/words/rpfetch.asm b/amforth-6.5/avr8/words/rpfetch.asm
deleted file mode 100644
index 8d1cdb6..0000000
--- a/amforth-6.5/avr8/words/rpfetch.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- n)
-; Stack
-; current return stack pointer address
-VE_RP_FETCH:
- .dw $ff03
- .db "rp@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RP_FETCH
-XT_RP_FETCH:
- .dw PFA_RP_FETCH
-PFA_RP_FETCH:
- savetos
- in tosl, SPL
- in tosh, SPH
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/rpstore.asm b/amforth-6.5/avr8/words/rpstore.asm
deleted file mode 100644
index 2a3d778..0000000
--- a/amforth-6.5/avr8/words/rpstore.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( addr -- ) (R: -- x*y)
-; Stack
-; set return stack pointer
-VE_RP_STORE:
- .dw $ff03
- .db "rp!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RP_STORE
-XT_RP_STORE:
- .dw PFA_RP_STORE
-PFA_RP_STORE:
- in temp2, SREG
- cli
- out SPL, tosl
- out SPH, tosh
- out SREG, temp2
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/rshift.asm b/amforth-6.5/avr8/words/rshift.asm
deleted file mode 100644
index e0e2231..0000000
--- a/amforth-6.5/avr8/words/rshift.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( n1 n2 -- n3 )
-; Arithmetics
-; shift n1 n2-times logically right
-VE_RSHIFT:
- .dw $ff06
- .db "rshift"
- .dw VE_HEAD
- .set VE_HEAD = VE_RSHIFT
-XT_RSHIFT:
- .dw PFA_RSHIFT
-PFA_RSHIFT:
- movw zl, tosl
- loadtos
-PFA_RSHIFT1:
- sbiw zl, 1
- brmi PFA_RSHIFT2
- lsr tosh
- ror tosl
- rjmp PFA_RSHIFT1
-PFA_RSHIFT2:
- jmp_ DO_NEXT
-
diff --git a/amforth-6.5/avr8/words/scomma.asm b/amforth-6.5/avr8/words/scomma.asm
deleted file mode 100644
index a5be0ca..0000000
--- a/amforth-6.5/avr8/words/scomma.asm
+++ /dev/null
@@ -1,56 +0,0 @@
-; ( addr len -- )
-; Compiler
-; compiles a string from RAM to Flash
-VE_SCOMMA:
- .dw $ff02
- .db "s",$2c
- .dw VE_HEAD
- .set VE_HEAD = VE_SCOMMA
-XT_SCOMMA:
- .dw DO_COLON
-PFA_SCOMMA:
- .dw XT_DUP
- .dw XT_DOSCOMMA
- .dw XT_EXIT
-
-; ( addr len len' -- )
-; Compiler
-; compiles a string from RAM to Flash
-;VE_DOSCOMMA:
-; .dw $ff04
-; .db "(s",$2c,")"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOSCOMMA
-XT_DOSCOMMA:
- .dw DO_COLON
-PFA_DOSCOMMA:
- .dw XT_COMMA
- .dw XT_DUP ; ( --addr len len)
- .dw XT_2SLASH ; ( -- addr len len/2
- .dw XT_TUCK ; ( -- addr len/2 len len/2
- .dw XT_2STAR ; ( -- addr len/2 len len'
- .dw XT_MINUS ; ( -- addr len/2 rem
- .dw XT_TO_R
- .dw XT_ZERO
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- .dw PFA_SCOMMA2
- .dw XT_DODO
-PFA_SCOMMA1:
- .dw XT_DUP ; ( -- addr addr )
- .dw XT_FETCH ; ( -- addr c1c2 )
- .dw XT_COMMA ; ( -- addr )
- .dw XT_CELLPLUS ; ( -- addr+cell )
- .dw XT_DOLOOP
- .dw PFA_SCOMMA1
-PFA_SCOMMA2:
- .dw XT_R_FROM
- .dw XT_GREATERZERO
- .dw XT_DOCONDBRANCH
- .dw PFA_SCOMMA3
- .dw XT_DUP ; well, tricky
- .dw XT_CFETCH
- .dw XT_COMMA
-PFA_SCOMMA3:
- .dw XT_DROP ; ( -- )
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/set-current.asm b/amforth-6.5/avr8/words/set-current.asm
deleted file mode 100644
index 334e167..0000000
--- a/amforth-6.5/avr8/words/set-current.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( wid -- )
-; Search Order
-; set current word list to the given word list wid
-VE_SET_CURRENT:
- .dw $ff0b
- .db "set-current",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SET_CURRENT
-XT_SET_CURRENT:
- .dw DO_COLON
-PFA_SET_CURRENT:
- .dw XT_DOLITERAL
- .dw CFG_CURRENT
- .dw XT_STOREE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/slashmod.asm b/amforth-6.5/avr8/words/slashmod.asm
deleted file mode 100644
index 2772651..0000000
--- a/amforth-6.5/avr8/words/slashmod.asm
+++ /dev/null
@@ -1,66 +0,0 @@
-; ( n1 n2 -- rem quot)
-; Arithmetics
-; signed division n1/n2 with remainder and quotient
-VE_SLASHMOD:
- .dw $ff04
- .db "/mod"
- .dw VE_HEAD
- .set VE_HEAD = VE_SLASHMOD
-XT_SLASHMOD:
- .dw PFA_SLASHMOD
-PFA_SLASHMOD:
- movw temp2, tosl
-
- ld temp0, Y+
- ld temp1, Y+
-
- mov temp6,temp1 ;move dividend High to sign register
- eor temp6,temp3 ;xor divisor High with sign register
- sbrs temp1,7 ;if MSB in dividend set
- rjmp PFA_SLASHMOD_1
- com temp1 ; change sign of dividend
- com temp0
- subi temp0,low(-1)
- sbci temp1,high(-1)
-PFA_SLASHMOD_1:
- sbrs temp3,7 ;if MSB in divisor set
- rjmp PFA_SLASHMOD_2
- com temp3 ; change sign of divisor
- com temp2
- subi temp2,low(-1)
- sbci temp3,high(-1)
-PFA_SLASHMOD_2: clr temp4 ;clear remainder Low byte
- sub temp5,temp5;clear remainder High byte and carry
- ldi temp7,17 ;init loop counter
-
-PFA_SLASHMOD_3: rol temp0 ;shift left dividend
- rol temp1
- dec temp7 ;decrement counter
- brne PFA_SLASHMOD_5 ;if done
- sbrs temp6,7 ; if MSB in sign register set
- rjmp PFA_SLASHMOD_4
- com temp1 ; change sign of result
- com temp0
- subi temp0,low(-1)
- sbci temp1,high(-1)
-PFA_SLASHMOD_4: rjmp PFA_SLASHMODmod_done ; return
-PFA_SLASHMOD_5: rol temp4 ;shift dividend into remainder
- rol temp5
- sub temp4,temp2 ;remainder = remainder - divisor
- sbc temp5,temp3 ;
- brcc PFA_SLASHMOD_6 ;if result negative
- add temp4,temp2 ; restore remainder
- adc temp5,temp3
- clc ; clear carry to be shifted into result
- rjmp PFA_SLASHMOD_3 ;else
-PFA_SLASHMOD_6: sec ; set carry to be shifted into result
- rjmp PFA_SLASHMOD_3
-
-PFA_SLASHMODmod_done:
- ; put remainder on stack
- st -Y,temp5
- st -Y,temp4
-
- ; put quotient on stack
- movw tosl, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/sp0.asm b/amforth-6.5/avr8/words/sp0.asm
deleted file mode 100644
index 324c1cf..0000000
--- a/amforth-6.5/avr8/words/sp0.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( -- addr)
-; Stack
-; start address of the data stack
-VE_SP0:
- .dw $ff03
- .db "sp0",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SP0
-XT_SP0:
- .dw PFA_DOVALUE1
-PFA_SP0:
- .dw USER_SP0
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
-
-; ( -- addr)
-; Stack
-; address of user variable to store top-of-stack for inactive tasks
-VE_SP:
- .dw $ff02
- .db "sp"
- .dw VE_HEAD
- .set VE_HEAD = VE_SP
-XT_SP:
- .dw PFA_DOUSER
-PFA_SP:
- .dw USER_SP
diff --git a/amforth-6.5/avr8/words/spfetch.asm b/amforth-6.5/avr8/words/spfetch.asm
deleted file mode 100644
index 69a0709..0000000
--- a/amforth-6.5/avr8/words/spfetch.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- addr )
-; Stack
-; current data stack pointer
-VE_SP_FETCH:
- .dw $ff03
- .db "sp@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SP_FETCH
-XT_SP_FETCH:
- .dw PFA_SP_FETCH
-PFA_SP_FETCH:
- savetos
- movw tosl, yl
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/spirw.asm b/amforth-6.5/avr8/words/spirw.asm
deleted file mode 100644
index bd6616a..0000000
--- a/amforth-6.5/avr8/words/spirw.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( txbyte -- rxbyte)
-; MCU
-; SPI exchange of 1 byte
-VE_SPIRW:
- .dw $ff06
- .db "c!@spi"
- .dw VE_HEAD
- .set VE_HEAD = VE_SPIRW
-XT_SPIRW:
- .dw PFA_SPIRW
-PFA_SPIRW:
- rcall do_spirw
- clr tosh
- jmp_ DO_NEXT
-
-do_spirw:
- out_ SPDR, tosl
-do_spirw1:
- in_ temp0, SPSR
- cbr temp0,7
- out_ SPSR, temp0
- in_ temp0, SPSR
- sbrs temp0, 7
- rjmp do_spirw1 ; wait until complete
- in_ tosl, SPDR
- ret
diff --git a/amforth-6.5/avr8/words/spstore.asm b/amforth-6.5/avr8/words/spstore.asm
deleted file mode 100644
index 004d348..0000000
--- a/amforth-6.5/avr8/words/spstore.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( addr -- i*x)
-; Stack
-; set data stack pointer to addr
-VE_SP_STORE:
- .dw $ff03
- .db "sp!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SP_STORE
-XT_SP_STORE:
- .dw PFA_SP_STORE
-PFA_SP_STORE:
- movw yl, tosl
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/state.asm b/amforth-6.5/avr8/words/state.asm
deleted file mode 100644
index 31895fd..0000000
--- a/amforth-6.5/avr8/words/state.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- addr )
-; System Variable
-; system state
-VE_STATE:
- .dw $ff05
- .db "state",0
- .dw VE_HEAD
- .set VE_HEAD = VE_STATE
-XT_STATE:
- .dw PFA_DOVARIABLE
-PFA_STATE:
- .dw ram_state
-
-.dseg
-ram_state: .byte 2
-.cseg \ No newline at end of file
diff --git a/amforth-6.5/avr8/words/store-e.asm b/amforth-6.5/avr8/words/store-e.asm
deleted file mode 100644
index 45fff2a..0000000
--- a/amforth-6.5/avr8/words/store-e.asm
+++ /dev/null
@@ -1,66 +0,0 @@
-; ( n e-addr -- )
-; Memory
-; write n (2bytes) to eeprom address
-VE_STOREE:
- .dw $ff02
- .db "!e"
- .dw VE_HEAD
- .set VE_HEAD = VE_STOREE
-XT_STOREE:
- .dw PFA_STOREE
-PFA_STOREE:
-.if WANT_UNIFIED == 1
- ldi zh, high(EEPROMEND)
- ldi zl, low(EEPROMEND)
- cp tosl, zl
- cpc tosh, zh
- brlt PFA_STOREE0
- brbs 1, PFA_STOREE0
- rjmp PFA_STOREE_OTHER
-.endif
-PFA_STOREE0:
- movw zl, tosl
- loadtos
- in_ temp2, SREG
- cli
- rcall PFA_FETCHE2
- in_ temp0, EEDR
- cp temp0,tosl
- breq PFA_STOREE3
- rcall PFA_STOREE1
-PFA_STOREE3:
- adiw zl,1
- rcall PFA_FETCHE2
- in_ temp0, EEDR
- cp temp0,tosh
- breq PFA_STOREE4
- mov tosl, tosh
- rcall PFA_STOREE1
-PFA_STOREE4:
- out_ SREG, temp2
- loadtos
- jmp_ DO_NEXT
-
-PFA_STOREE1:
- sbic EECR, EEPE
- rjmp PFA_STOREE1
-
-PFA_STOREE2: ; estore_wait_low_spm:
- in_ temp0, SPMCSR
- sbrc temp0,SPMEN
- rjmp PFA_STOREE2
-
- out_ EEARH,zh
- out_ EEARL,zl
- out_ EEDR, tosl
- sbi EECR,EEMPE
- sbi EECR,EEPE
-
- ret
-.if WANT_UNIFIED == 1
-PFA_STOREE_OTHER:
- adiw zl, 1
- sub tosl, zl
- sbc tosh, zh
- jmp_ PFA_STOREI
-.endif
diff --git a/amforth-6.5/avr8/words/store-i.asm b/amforth-6.5/avr8/words/store-i.asm
deleted file mode 100644
index a56fce2..0000000
--- a/amforth-6.5/avr8/words/store-i.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( n addr -- )
-; System Value
-; Deferred action to write a single 16bit cell to flash
-VE_STOREI:
- .dw $ff02
- .db "!i"
- .dw VE_HEAD
- .set VE_HEAD = VE_STOREI
-XT_STOREI:
- .dw PFA_DODEFER1
-PFA_STOREI:
- .dw EE_STOREI
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/store-i_big.asm b/amforth-6.5/avr8/words/store-i_big.asm
deleted file mode 100644
index 422da39..0000000
--- a/amforth-6.5/avr8/words/store-i_big.asm
+++ /dev/null
@@ -1,129 +0,0 @@
-; ( n addr -- ) Memory
-; R( -- )
-; writes a cell in flash
-VE_DO_STOREI_BIG:
- .dw $ff04
- .db "(i!)"
- .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_BIG
-XT_DO_STOREI:
- .dw PFA_DO_STOREI_BIG
-PFA_DO_STOREI_BIG:
- movw temp2, tosl ; save the (word) address
- loadtos ; get the new value for the flash cell
- push xl
- push xh
- push yl
- push yh
- ldi zl, byte3(DO_STOREI_atmega)
- out_ rampz, zl
- ldi zh, byte2(DO_STOREI_atmega)
- ldi zl, byte1(DO_STOREI_atmega)
- eicall
- pop yh
- pop yl
- pop xh
- pop xl
- ; finally clear the stack
- loadtos
- jmp_ DO_NEXT
-
-;
-.set _pc = pc
-.org NRWW_START_ADDR
-DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
- rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
- com temp4
- com temp5
- and tosl, temp4
- and tosh, temp5
- or tosh, tosl
- breq DO_STOREI_writepage
-
- movw zl, temp2
- ldi temp0,(1<<PGERS|1<<SPMEN)
- rcall dospm
-
-DO_STOREI_writepage:
- ; write page
- movw zl, temp2
- ldi temp0,(1<<PGWRT|1<<SPMEN)
- rcall dospm
-
- ; reenable RWW section
- movw zl, temp2
- ldi temp0,(1<<RWWSRE|1<<SPMEN)
- rcall dospm
- ret
-
-; load the desired page
-.equ pagemask = ~ ( PAGESIZE - 1 )
-pageload:
- movw zl, temp2
- ; get the beginning of page
- andi zl,low(pagemask)
- andi zh,high(pagemask)
- movw y, z
- ; loop counter (in words)
- ldi xl,low(pagesize)
- ldi xh,high(pagesize)
-pageload_loop:
- ; we need the current flash value anyways
- movw z, y
- readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
- movw z, y
- cp zl, temp2
- cpc zh, temp3
- breq pageload_newdata
- movw r0, temp6
- rjmp pageload_cont
-pageload_newdata:
- movw temp4, temp6
- movw r0, tosl
-pageload_cont:
- ldi temp0,(1<<SPMEN)
- rcall dospm
- adiw y, 1
- sbiw x, 1
- brne pageload_loop
-
-pageload_done:
- ret
-
-
-;; dospm
-;;
-;; execute spm instruction
-;; temp0 holds the value for SPMCR
-
-dospm:
- ; store status register
- in temp1,SREG
- push temp1
- cli
-Wait_ee:
- sbic EECR, EEPE
- rjmp Wait_ee
-wait_spm:
- in temp1, SPMCSR
- sbrc temp1, SPMEN
- rjmp Wait_spm
-
- ; turn the word addres into a byte address
- writeflashcell
- ; execute spm
- out SPMCSR,temp0
- spm
- pop temp1
- ; restore status register
- out SREG,temp1
- ret
-
-.org _pc
diff --git a/amforth-6.5/avr8/words/store-i_nrww.asm b/amforth-6.5/avr8/words/store-i_nrww.asm
deleted file mode 100644
index 85be220..0000000
--- a/amforth-6.5/avr8/words/store-i_nrww.asm
+++ /dev/null
@@ -1,123 +0,0 @@
-; ( n f-addr -- )
-; Memory
-; writes n to flash memory using assembly code (code to be placed in boot loader section)
-VE_DO_STOREI_NRWW:
- .dw $ff09
- .db "(!i-nrww)",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DO_STOREI_NRWW
-XT_DO_STOREI:
- .dw PFA_DO_STOREI_NRWW
-PFA_DO_STOREI_NRWW:
- ; store status register
- in temp1,SREG
- push temp1
- cli
-
- movw temp2, tosl ; save the (word) address
- loadtos ; get the new value for the flash cell
- push xl
- push xh
- push yl
- push yh
- rcall DO_STOREI_atmega
- pop yh
- pop yl
- pop xh
- pop xl
- ; finally clear the stack
- loadtos
- pop temp1
- ; restore status register (and interrupt enable flag)
- out SREG,temp1
-
- jmp_ DO_NEXT
-
-;
-DO_STOREI_atmega:
- ; write data to temp page buffer
- ; use the values in tosl/tosh at the
- ; appropiate place
- rcall pageload
-
- ; erase page if needed
- ; it is needed if a bit goes from 0 to 1
- com temp4
- com temp5
- and tosl, temp4
- and tosh, temp5
- or tosh, tosl
- breq DO_STOREI_writepage
- movw zl, temp2
- ldi temp0,(1<<PGERS)
- rcall dospm
-
-DO_STOREI_writepage:
- ; write page
- movw zl, temp2
- ldi temp0,(1<<PGWRT)
- rcall dospm
-
- ; reenable RWW section
- movw zl, temp2
- ldi temp0,(1<<RWWSRE)
- rcall dospm
- ret
-
-; load the desired page
-.equ pagemask = ~ ( PAGESIZE - 1 )
-pageload:
- movw zl, temp2
- ; get the beginning of page
- andi zl,low(pagemask)
- andi zh,high(pagemask)
- movw y, z
- ; loop counter (in words)
- ldi xl,low(pagesize)
- ldi xh,high(pagesize)
-pageload_loop:
- ; we need the current flash value anyways
- movw z, y
- readflashcell temp6, temp7 ; destroys Z
- ; now check: if Z points to the same cell as temp2/3, we want the new data
- movw z, y
- cp zl, temp2
- cpc zh, temp3
- breq pageload_newdata
- movw r0, temp6
- rjmp pageload_cont
-pageload_newdata:
- movw temp4, temp6
- movw r0, tosl
-pageload_cont:
- clr temp0
- rcall dospm
- adiw y, 1
- sbiw x, 1
- brne pageload_loop
-
-pageload_done:
- ret
-
-
-;; dospm
-;;
-;; execute spm instruction
-;; temp0 holds the value for SPMCR
-
-dospm:
-dospm_wait_ee:
- sbic EECR, EEPE
- rjmp dospm_wait_ee
-dospm_wait_spm:
- in_ temp1, SPMCSR
- sbrc temp1, SPMEN
- rjmp dospm_wait_spm
-
- ; turn the word addres into a byte address
- writeflashcell
- ; execute spm
- ori temp0, (1<<SPMEN)
- out_ SPMCSR,temp0
- spm
- ret
diff --git a/amforth-6.5/avr8/words/store-u.asm b/amforth-6.5/avr8/words/store-u.asm
deleted file mode 100644
index df73ee9..0000000
--- a/amforth-6.5/avr8/words/store-u.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( n offset -- )
-; Memory
-; write n to USER area at offset
-VE_STOREU:
- .dw $ff02
- .db "!u"
- .dw VE_HEAD
- .set VE_HEAD = VE_STOREU
-XT_STOREU:
- .dw DO_COLON
-PFA_STOREU:
- .dw XT_UP_FETCH
- .dw XT_PLUS
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/store.asm b/amforth-6.5/avr8/words/store.asm
deleted file mode 100644
index a71dd4b..0000000
--- a/amforth-6.5/avr8/words/store.asm
+++ /dev/null
@@ -1,35 +0,0 @@
-; ( n addr -- )
-; Memory
-; write n to RAM memory at addr, low byte first
-VE_STORE:
- .dw $ff01
- .db "!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_STORE
-XT_STORE:
- .dw PFA_STORE
-PFA_STORE:
-.if WANT_UNIFIED == 1
- ldi zh, high(RAMEND)
- ldi zl, low(RAMEND)
- cp tosl, zl
- cpc tosh, zh
- brlt PFA_STORERAM
- brbs 1, PFA_STORERAM
- rjmp PFA_STOREOTHER
-.endif
-PFA_STORERAM:
- movw zl, tosl
- loadtos
- ; the high byte is written before the low byte
- std Z+1, tosh
- std Z+0, tosl
- loadtos
- jmp_ DO_NEXT
-.if WANT_UNIFIED == 1
-PFA_STOREOTHER:
- adiw zl, 1
- sub tosl, zl
- sbc tosh, zh
- jmp_ PFA_STOREE
-.endif
diff --git a/amforth-6.5/avr8/words/swap.asm b/amforth-6.5/avr8/words/swap.asm
deleted file mode 100644
index c54cdcd..0000000
--- a/amforth-6.5/avr8/words/swap.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( n1 n2 -- n2 n1)
-; Stack
-; swaps the two top level stack cells
-VE_SWAP:
- .dw $ff04
- .db "swap"
- .dw VE_HEAD
- .set VE_HEAD = VE_SWAP
-XT_SWAP:
- .dw PFA_SWAP
-PFA_SWAP:
- movw temp0, tosl
- loadtos
- st -Y, temp1
- st -Y, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/to-body.asm b/amforth-6.5/avr8/words/to-body.asm
deleted file mode 100644
index 34e9e9d..0000000
--- a/amforth-6.5/avr8/words/to-body.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-; ( XT -- PFA )
-; Core
-; get body from XT
-VE_TO_BODY:
- .dw $ff05
- .db ">body",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_BODY
-XT_TO_BODY:
- .dw PFA_1PLUS
diff --git a/amforth-6.5/avr8/words/to_r.asm b/amforth-6.5/avr8/words/to_r.asm
deleted file mode 100644
index 3e038de..0000000
--- a/amforth-6.5/avr8/words/to_r.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( n -- ) (R: -- n)
-; Stack
-; move TOS to TOR
-VE_TO_R:
- .dw $ff02
- .db ">r"
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_R
-XT_TO_R:
- .dw PFA_TO_R
-PFA_TO_R:
- push tosh
- push tosl
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/true.asm b/amforth-6.5/avr8/words/true.asm
deleted file mode 100644
index 9b64014..0000000
--- a/amforth-6.5/avr8/words/true.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- -1 )
-; Arithmetics
-; leaves the value -1 (true) on TOS
-VE_TRUE:
- .dw $ff04
- .db "true"
- .dw VE_HEAD
- .set VE_HEAD = VE_TRUE
-XT_TRUE:
- .dw PFA_TRUE
-PFA_TRUE:
- savetos
-PFA_TRUE1:
- ser tosl
- ser tosh
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/turnkey.asm b/amforth-6.5/avr8/words/turnkey.asm
deleted file mode 100644
index 6f8e0c4..0000000
--- a/amforth-6.5/avr8/words/turnkey.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- n*y )
-; System Value
-; Deferred action during startup/reset
-VE_TURNKEY:
- .dw $ff07
- .db "turnkey",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TURNKEY
-XT_TURNKEY:
- .dw PFA_DODEFER1
-PFA_TURNKEY:
- .dw CFG_TURNKEY
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/ubrr.asm b/amforth-6.5/avr8/words/ubrr.asm
deleted file mode 100644
index 40f4304..0000000
--- a/amforth-6.5/avr8/words/ubrr.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- v)
-; MCU
-; returns usart UBRR settings
-VE_UBRR:
- .dw $ff04
- .db "ubrr"
- .dw VE_HEAD
- .set VE_HEAD = VE_UBRR
-XT_UBRR:
- .dw PFA_DOVALUE1
-PFA_UBRR: ; ( -- )
- .dw EE_UBRRVAL
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
diff --git a/amforth-6.5/avr8/words/uless.asm b/amforth-6.5/avr8/words/uless.asm
deleted file mode 100644
index 69d5a6b..0000000
--- a/amforth-6.5/avr8/words/uless.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( u1 u2 -- flasg)
-; Compare
-; true if u1 < u2 (unsigned)
-VE_ULESS:
- .dw $ff02
- .db "u<"
- .dw VE_HEAD
- .set VE_HEAD = VE_ULESS
-XT_ULESS:
- .dw PFA_ULESS
-PFA_ULESS:
- ld temp2, Y+
- ld temp3, Y+
- cp tosl, temp2
- cpc tosh, temp3
- brlo PFA_ZERO1
- brbs 1, PFA_ZERO1
- jmp_ PFA_TRUE1
diff --git a/amforth-6.5/avr8/words/umslashmod.asm b/amforth-6.5/avr8/words/umslashmod.asm
deleted file mode 100644
index 6adfbb1..0000000
--- a/amforth-6.5/avr8/words/umslashmod.asm
+++ /dev/null
@@ -1,62 +0,0 @@
-; ( ud u2 -- rem quot)
-; Arithmetics
-; unsigned division ud / u2 with remainder
-VE_UMSLASHMOD:
- .dw $ff06
- .db "um/mod"
- .dw VE_HEAD
- .set VE_HEAD = VE_UMSLASHMOD
-XT_UMSLASHMOD:
- .dw PFA_UMSLASHMOD
-PFA_UMSLASHMOD:
- movw temp4, tosl
-
- ld temp2, Y+
- ld temp3, Y+
-
- ld temp0, Y+
- ld temp1, Y+
-
-;; unsigned 32/16 -> 16r16 divide
-
-PFA_UMSLASHMODmod:
-
- ; set loop counter
- ldi temp6,$10
-
-PFA_UMSLASHMODmod_loop:
- ; shift left, saving high bit
- clr temp7
- lsl temp0
- rol temp1
- rol temp2
- rol temp3
- rol temp7
-
- ; try subtracting divisor
- cp temp2, temp4
- cpc temp3, temp5
- cpc temp7,zerol
-
- brcs PFA_UMSLASHMODmod_loop_control
-
-PFA_UMSLASHMODmod_subtract:
- ; dividend is large enough
- ; do the subtraction for real
- ; and set lowest bit
- inc temp0
- sub temp2, temp4
- sbc temp3, temp5
-
-PFA_UMSLASHMODmod_loop_control:
- dec temp6
- brne PFA_UMSLASHMODmod_loop
-
-PFA_UMSLASHMODmod_done:
- ; put remainder on stack
- st -Y,temp3
- st -Y,temp2
-
- ; put quotient on stack
- movw tosl, temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/umstar.asm b/amforth-6.5/avr8/words/umstar.asm
deleted file mode 100644
index ee53c87..0000000
--- a/amforth-6.5/avr8/words/umstar.asm
+++ /dev/null
@@ -1,37 +0,0 @@
-; ( u1 u2 -- d)
-; Arithmetics
-; multiply 2 unsigned cells to a double cell
-VE_UMSTAR:
- .dw $ff03
- .db "um*",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UMSTAR
-XT_UMSTAR:
- .dw PFA_UMSTAR
-PFA_UMSTAR:
- movw temp0, tosl
- loadtos
- ; result: (temp3*temp1)* 65536 + (temp3*temp0 + temp1*temp2) * 256 + (temp0 * temp2)
- ; low bytes
- mul tosl,temp0
- movw zl, r0
- clr temp2
- clr temp3
- ; middle bytes
- mul tosh, temp0
- add zh, r0
- adc temp2, r1
- adc temp3, zeroh
-
- mul tosl, temp1
- add zh, r0
- adc temp2, r1
- adc temp3, zeroh
-
- mul tosh, temp1
- add temp2, r0
- adc temp3, r1
- movw tosl, zl
- savetos
- movw tosl, temp2
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/unloop.asm b/amforth-6.5/avr8/words/unloop.asm
deleted file mode 100644
index f4fb4bc..0000000
--- a/amforth-6.5/avr8/words/unloop.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( -- ) (R: loop-sys -- )
-; Compiler
-; remove loop-sys, exit the loop and continue execution after it
-VE_UNLOOP:
- .dw $ff06
- .db "unloop"
- .dw VE_HEAD
- .set VE_HEAD = VE_UNLOOP
-XT_UNLOOP:
- .dw PFA_UNLOOP
-PFA_UNLOOP:
- pop temp1
- pop temp0
- pop temp1
- pop temp0
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/unused.asm b/amforth-6.5/avr8/words/unused.asm
deleted file mode 100644
index 16566d4..0000000
--- a/amforth-6.5/avr8/words/unused.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- n )
-; Tools
-; Amount of available RAM (incl. PAD)
-VE_UNUSED:
- .dw $ff06
- .db "unused"
- .dw VE_HEAD
- .set VE_HEAD = VE_UNUSED
-XT_UNUSED:
- .dw DO_COLON
-PFA_UNUSED:
- .dw XT_SP_FETCH
- .dw XT_HERE
- .dw XT_MINUS
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/up.asm b/amforth-6.5/avr8/words/up.asm
deleted file mode 100644
index 0edfc01..0000000
--- a/amforth-6.5/avr8/words/up.asm
+++ /dev/null
@@ -1,29 +0,0 @@
-; ( -- addr )
-; System Variable
-; get user area pointer
-VE_UP_FETCH:
- .dw $ff03
- .db "up@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UP_FETCH
-XT_UP_FETCH:
- .dw PFA_UP_FETCH
-PFA_UP_FETCH:
- savetos
- movw tosl, upl
- jmp_ DO_NEXT
-
-; ( addr -- )
-; System Variable
-; set user area pointer
-VE_UP_STORE:
- .dw $ff03
- .db "up!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UP_STORE
-XT_UP_STORE:
- .dw PFA_UP_STORE
-PFA_UP_STORE:
- movw upl, tosl
- loadtos
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/usart-rx-poll.asm b/amforth-6.5/avr8/words/usart-rx-poll.asm
deleted file mode 100644
index 9896175..0000000
--- a/amforth-6.5/avr8/words/usart-rx-poll.asm
+++ /dev/null
@@ -1,42 +0,0 @@
-; (c -- )
-; MCU
-; wait for one character and read it from the terminal connection using register poll
-VE_RX_POLL:
- .dw $ff07
- .db "rx-poll",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RX_POLL
-XT_RX_POLL:
- .dw DO_COLON
-PFA_RX_POLL:
- ; wait for data ready
- .dw XT_RXQ_POLL
- .dw XT_DOCONDBRANCH
- .dw PFA_RX_POLL
- ; send to usart
- .dw XT_DOLITERAL
- .dw USART_DATA
- .dw XT_CFETCH
- .dw XT_EXIT
-
-; ( -- f)
-; MCU
-; check if a unread character in the input device is available
-VE_RXQ_POLL:
- .dw $ff08
- .db "rx?-poll"
- .dw VE_HEAD
- .set VE_HEAD = VE_RXQ_POLL
-XT_RXQ_POLL:
- .dw DO_COLON
-PFA_RXQ_POLL:
- .dw XT_PAUSE
- .dw XT_DOLITERAL
- .dw bm_USART_RXRD
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw USART_A
- .dw XT_CFETCH
- .dw XT_AND
- .dw XT_EQUAL
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/usart-tx-poll.asm b/amforth-6.5/avr8/words/usart-tx-poll.asm
deleted file mode 100644
index a33e8fb..0000000
--- a/amforth-6.5/avr8/words/usart-tx-poll.asm
+++ /dev/null
@@ -1,40 +0,0 @@
-; (c -- )
-; MCU
-; check availability and send one character to the terminal using register poll
-VE_TX_POLL:
- .dw $ff07
- .db "tx-poll",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TX_POLL
-XT_TX_POLL:
- .dw DO_COLON
-PFA_TX_POLL:
- ; wait for data ready
- .dw XT_TXQ_POLL
- .dw XT_DOCONDBRANCH
- .dw PFA_TX_POLL
- ; send to usart
- .dw XT_DOLITERAL
- .dw USART_DATA
- .dw XT_CSTORE
- .dw XT_EXIT
-
-; ( -- f) MCU
-; MCU
-; check if a character can be send using register poll
-VE_TXQ_POLL:
- .dw $ff08
- .db "tx?-poll"
- .dw VE_HEAD
- .set VE_HEAD = VE_TXQ_POLL
-XT_TXQ_POLL:
- .dw DO_COLON
-PFA_TXQ_POLL:
- .dw XT_PAUSE
- .dw XT_DOLITERAL
- .dw USART_A
- .dw XT_CFETCH
- .dw XT_DOLITERAL
- .dw bm_USART_TXRD
- .dw XT_AND
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/usart.asm b/amforth-6.5/avr8/words/usart.asm
deleted file mode 100644
index f14e62f..0000000
--- a/amforth-6.5/avr8/words/usart.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-; ( -- )
-; MCU
-; initialize usart
-VE_USART:
- .dw $ff06
- .db "+usart"
- .dw VE_HEAD
- .set VE_HEAD = VE_USART
-XT_USART:
- .dw DO_COLON
-PFA_USART: ; ( -- )
-
- .dw XT_DOLITERAL
- .dw USART_B_VALUE
- .dw XT_DOLITERAL
- .dw USART_B
- .dw XT_CSTORE
-
- .dw XT_DOLITERAL
- .dw USART_C_VALUE
- .dw XT_DOLITERAL
- .dw USART_C | bm_USARTC_en
- .dw XT_CSTORE
-
- .dw XT_UBRR
- .dw XT_DUP
- .dw XT_BYTESWAP
- .dw XT_DOLITERAL
- .dw BAUDRATE_HIGH
- .dw XT_CSTORE
- .dw XT_DOLITERAL
- .dw BAUDRATE_LOW
- .dw XT_CSTORE
-.if XT_USART_INIT_RX!=0
- .dw XT_USART_INIT_RX
-.endif
-.if XT_USART_INIT_TX!=0
- .dw XT_USART_INIT_TX
-.endif
-
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/user.asm b/amforth-6.5/avr8/words/user.asm
deleted file mode 100644
index c11f600..0000000
--- a/amforth-6.5/avr8/words/user.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-; ( n cchar -- )
-; Compiler
-; create a dictionary entry for a user variable at offset n
-VE_USER:
- .dw $ff04
- .db "user"
- .dw VE_HEAD
- .set VE_HEAD = VE_USER
-XT_USER:
- .dw DO_COLON
-PFA_USER:
- .dw XT_DOCREATE
- .dw XT_REVEAL
-
- .dw XT_COMPILE
- .dw PFA_DOUSER
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/uslashmod.asm b/amforth-6.5/avr8/words/uslashmod.asm
deleted file mode 100644
index 0d9b5aa..0000000
--- a/amforth-6.5/avr8/words/uslashmod.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; (u1 u2 -- rem quot)
-; Arithmetics
-; unsigned division with remainder
-VE_USLASHMOD:
- .dw $ff05
- .db "u/mod",0
- .dw VE_HEAD
- .set VE_HEAD = VE_USLASHMOD
-XT_USLASHMOD:
- .dw DO_COLON
-PFA_USLASHMOD:
- .dw XT_TO_R
- .dw XT_ZERO
- .dw XT_R_FROM
- .dw XT_UMSLASHMOD
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/wdr.asm b/amforth-6.5/avr8/words/wdr.asm
deleted file mode 100644
index b2c78f6..0000000
--- a/amforth-6.5/avr8/words/wdr.asm
+++ /dev/null
@@ -1,13 +0,0 @@
-; ( -- )
-; MCU
-; calls the MCU watch dog reset instruction
-VE_WDR:
- .dw $ff03
- .db "wdr",0
- .dw VE_HEAD
- .set VE_HEAD = VE_WDR
-XT_WDR:
- .dw PFA_WDR
-PFA_WDR:
- wdr
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/wlscope.asm b/amforth-6.5/avr8/words/wlscope.asm
deleted file mode 100644
index cbef8c2..0000000
--- a/amforth-6.5/avr8/words/wlscope.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( addr len -- addr' len' wid )
-; Compiler
-; dynamically place a word in a wordlist. The word name may be changed.
-VE_WLSCOPE:
- .dw $ff07
- .db "wlscope",0
- .dw VE_HEAD
- .set VE_HEAD = VE_WLSCOPE
-XT_WLSCOPE:
- .dw PFA_DODEFER1
-PFA_WLSCOPE:
- .dw CFG_WLSCOPE
- .dw XT_EDEFERFETCH
- .dw XT_EDEFERSTORE
-
-; wlscope, "wordlist scope" ( addr len -- addr' len' wid ), is a deferred word
-; which enables the AmForth application to choose the wordlist ( wid ) for the
-; new voc entry based on the input ( addr len ) string. The name of the new voc
-; entry ( addr' len' ) may be different from the input string. Note that all
-; created voc entry types pass through the wlscope mechanism. The default
-; wlscope action passes the input string to the output without modification and
-; uses get-current to select the wid.
diff --git a/amforth-6.5/avr8/words/wordlist.asm b/amforth-6.5/avr8/words/wordlist.asm
deleted file mode 100644
index d5d2980..0000000
--- a/amforth-6.5/avr8/words/wordlist.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( -- wid )
-; Search Order
-; create a new, empty wordlist
-VE_WORDLIST:
- .dw $ff08
- .db "wordlist"
- .dw VE_HEAD
- .set VE_HEAD = VE_WORDLIST
-XT_WORDLIST:
- .dw DO_COLON
-PFA_WORDLIST:
- .dw XT_EHERE
- .dw XT_ZERO
- .dw XT_OVER
- .dw XT_STOREE
- .dw XT_DUP
- .dw XT_CELLPLUS
- .dw XT_DOTO
- .dw PFA_EHERE
- .dw XT_EXIT
diff --git a/amforth-6.5/avr8/words/xor.asm b/amforth-6.5/avr8/words/xor.asm
deleted file mode 100644
index 337259c..0000000
--- a/amforth-6.5/avr8/words/xor.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; ( n1 n2 -- n3)
-; Logic
-; exclusive or
-VE_XOR:
- .dw $ff03
- .db "xor",0
- .dw VE_HEAD
- .set VE_HEAD = VE_XOR
-XT_XOR:
- .dw PFA_XOR
-PFA_XOR:
- ld temp0, Y+
- ld temp1, Y+
- eor tosl, temp0
- eor tosh, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/words/zero.asm b/amforth-6.5/avr8/words/zero.asm
deleted file mode 100644
index a03942c..0000000
--- a/amforth-6.5/avr8/words/zero.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( -- 0 )
-; Arithmetics
-; place a value 0 on TOS
-VE_ZERO:
- .dw $ff01
- .db "0",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ZERO
-XT_ZERO:
- .dw PFA_ZERO
-PFA_ZERO:
- savetos
-PFA_ZERO1:
- movw tosl, zerol
- jmp_ DO_NEXT
diff --git a/amforth-6.5/common/lib/2rvalue.frt b/amforth-6.5/common/lib/2rvalue.frt
deleted file mode 100644
index 2c46d01..0000000
--- a/amforth-6.5/common/lib/2rvalue.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-
-\ a value in RAM with 2 cells data storage
-\ requires quotations and 2@/2! from double wordset
-
-#require quotations.frt
-#require 2-fetch.frt
-#require 2-store.frt
-
-: 2rvalue ( d -- )
- (value)
- here ,
- [: @i 2@ ;] ,
- [: @i 2! ;] ,
- here 2! 2 cells allot
-;
diff --git a/amforth-6.5/common/lib/anew.frt b/amforth-6.5/common/lib/anew.frt
deleted file mode 100644
index a7e9330..0000000
--- a/amforth-6.5/common/lib/anew.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ POSSIBLY ( "name" -- )
-\ Execute _name_ if it exists; otherwise, do nothing.
-\ Useful implementation factor of `ANEW`.
-
-\ ANEW ( "name" -- )
-\ Compiler directive used in the form: `ANEW _name_`.
-\ If the word _name_ already exists, it and all
-\ subsequent words are forgotten from the current
-\ dictionary, and then a `MARKER` word _name_ is
-\ created that does nothing. This is usually placed
-\ at the start of a file. When the code is reloaded,
-\ any prior version is automatically pruned from the
-\ dictionary.
-\
-\ Executing _name_ will also cause it to be forgotten,
-\ since it is a `MARKER` word.
-\
-\ Useful implementation factor of `EMPTY`.
-
-\ meta comment for amforth-shell.
-\ #require marker.frt
-
-: possibly ( "name" -- )
- parse-name find-xt if execute then ;
-
-: anew ( "name" -- ) >in @ possibly >in ! marker ;
-
diff --git a/amforth-6.5/common/lib/base-execute.frt b/amforth-6.5/common/lib/base-execute.frt
deleted file mode 100644
index 44eaff8..0000000
--- a/amforth-6.5/common/lib/base-execute.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ execute xt with the content of BASE being u, and
-\ restoring the original BASE afterwards.
-: base-execute ( i*x xt u -- j*x ) \ gforth
- base @ >r
- base ! execute
- r> base !
-; \ No newline at end of file
diff --git a/amforth-6.5/common/lib/bounds.frt b/amforth-6.5/common/lib/bounds.frt
deleted file mode 100644
index 85e0c20..0000000
--- a/amforth-6.5/common/lib/bounds.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-
-: bounds \ addr len -- addr+len addr
- over + swap
-;
-
diff --git a/amforth-6.5/common/lib/builds.frt b/amforth-6.5/common/lib/builds.frt
deleted file mode 100644
index 377728d..0000000
--- a/amforth-6.5/common/lib/builds.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-\ pre ANS94 Forth. <builds .. does> instead of create does>
-\
-: <builds (create) reveal -1 , ;
diff --git a/amforth-6.5/common/lib/chain-stack-test.frt b/amforth-6.5/common/lib/chain-stack-test.frt
deleted file mode 100644
index 5a0f250..0000000
--- a/amforth-6.5/common/lib/chain-stack-test.frt
+++ /dev/null
@@ -1,17 +0,0 @@
-\ demonstate the chains with a configuration stack
-
-\ first create and allocate a chain storage
-4 chain: kette
-
-\ now populate the chain with some execution
-\ tokens.
-' ver ' cr ' ver 3 chain>id kette set-stack
-
-\ there is no easy way to show the content of
-\ a stack
-
-\ now execute the stack. The TOS element is
-\ called first
-
-kette \ emits the version string twice and a newline between them
-
diff --git a/amforth-6.5/common/lib/chain-stack.frt b/amforth-6.5/common/lib/chain-stack.frt
deleted file mode 100644
index 0ea3959..0000000
--- a/amforth-6.5/common/lib/chain-stack.frt
+++ /dev/null
@@ -1,31 +0,0 @@
-\ chains: execute a list of XT when calling the
-\ anchor. Elements can be pre- and ap-pended.
-\ no particular stack effect enforcment
-
-\ chain.run ( chainid -- i*x )
-\ chain ( -- chainid ) \ allocate an unnamed chain
-\ chain: ( "name" -- ) create a named chain
-
-\ implementation uses configuration stacks
-
-\ #require quotations.frt
-\ #require builds.frt
-
-\ #require eallot.frt
-: chain ( n -- ) ehere swap 1+ cells eallot ; \ n cells for n XT's
-\ for the MSP use the following line instead of the two above
-\ : chain ( n -- ) here swap 1+ cells allot ; \ n cells for n XT's
-
-: chain.run ( chainid -- i*x )
- [: ( i*x XT -- j*y 0 ) execute 0 ;] swap map-stack ( -- 0 ) drop
-;
-
-\ create a named chain with an action
-: chain: <builds 0 chain dup , !e does> @i chain.run ;
-\ for the MSP430 use the following line instead
-\ : chain: <builds 0 chain dup , ! does> @i chain.run ;
-
-\ get the chainid from its name
-: chain>id ( "name" -- chainid )
- ' >body @i
-;
diff --git a/amforth-6.5/common/lib/chains-wordlist-test.frt b/amforth-6.5/common/lib/chains-wordlist-test.frt
deleted file mode 100644
index 95a36a6..0000000
--- a/amforth-6.5/common/lib/chains-wordlist-test.frt
+++ /dev/null
@@ -1,22 +0,0 @@
-\ test the chains with wordlist backend
-
-\ first create a named chain, identified by kette
-chain: kette
-
-\ now populate the chain with words, save the
-\ existing definition word list on stack
-get-current
-
-\ chain>id is a parsing word
-chain>id kette set-current
-: s1 ." one " ;
-: s2 ." two " ;
-
-\ restore the previously used definition wordlist
-set-current
-
-\ show the content of the chain
-chain>id kette show-wordlist
-
-\ and finally execute the words in it.
-kette \ prints "two one"
diff --git a/amforth-6.5/common/lib/chains-wordlist.frt b/amforth-6.5/common/lib/chains-wordlist.frt
deleted file mode 100644
index f79f117..0000000
--- a/amforth-6.5/common/lib/chains-wordlist.frt
+++ /dev/null
@@ -1,31 +0,0 @@
-\ chains: execute a list of XT when calling the
-\ anchor. Elements can be pre- and ap-pended.
-\ no particular stack effect enforcment
-
-\ chain.run ( chainid -- i*x )
-\ chain ( -- chainid ) \ create an unnamed chain
-\ chain: ( "name" -- ) \ create a named chain
-
-\ implementation uses wordlists
-
-\ #require name2interpret.frt
-\ #require quotations.frt
-\ #require builds.frt
-
-\ create an unnamed chain
-: chain wordlist ; \ trivial
-
-: chain.run ( chainid -- i*x )
- [: name>interpret execute true ;]
- swap traverse-wordlist
-;
-
-\ create a named chain with an action
-: chain: <builds 0 chain dup , !e does> @i chain.run ;
-\ for MSP430 use instead
-\ : chain: <builds 0 chain dup , ! does> @i chain.run ;
-
-\ get the chainid from its name
-: chain>id ( "name" -- chainid )
- ' >body @i
-;
diff --git a/amforth-6.5/common/lib/clip.frt b/amforth-6.5/common/lib/clip.frt
deleted file mode 100644
index 95c4654..0000000
--- a/amforth-6.5/common/lib/clip.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-
-: clip ( n lo hi -- n)
- rot min max
-;
-
-\ usage:
-\ input @ minval maxval clip ...
-\ source: CLF, Brian Fox, 21.4.1997 \ No newline at end of file
diff --git a/amforth-6.5/common/lib/crc8.frt b/amforth-6.5/common/lib/crc8.frt
deleted file mode 100644
index f2d4e17..0000000
--- a/amforth-6.5/common/lib/crc8.frt
+++ /dev/null
@@ -1,94 +0,0 @@
-\ -*- Mode: Forth; Coding: utf-8 -*-
-
-\ Copyright (c) 2013 Energy Measurement & Control, NJ, USA.
-\ Software license: AmForth compliant, see http://amforth.sourceforge.net/
-\
-\ (crc8) is a configurable 8-bit table-driven CRC generator/checker. For usage
-\ see below (*). (crc8) was adapted from Linux/lib/crc8.c, See:
-\ http://lxr.free-electrons.com/source/include/linux/crc8.h
-\
-\ fabtab: is a factory function for arbitrary-length byte-wide Flash look-up
-\ tables. Data is read from the pad.
-
-\ #error-on-output
-
-decimal
-
-\ IMPORTANT:
-\ amforth-shell needs the following constants defined in appl_defs.frt
-\ msb-first poly: (1)11010101 = 0xD5
-\ lsb-first poly: 10101011(1) = 0xAB
-\ bit-order: true = msb-first, false = lsb-first
-(
-$d5 constant CRC8MSB
-$ab constant CRC8LSB
-true constant CRC8REV
-)
-
-\ verify having 256 pad bytes to form the crc table
-\ #expect-output-next ^-1 0 $
-s" /pad" environment? . 256 < .
-
-\ pad bytes → flash table factory function
-: fabtab: create ( "table-name" table-byte-count -- )
- dup , \ table byte count
- 1+ 2/ 0 do pad i 2* + @ , loop \ table words
- does> ( table-byte-index -- table-byte )
- 2dup @i U< if
- over 2/ + 1+ @i \ ( table-byte-index table-word )
- swap 1 and \ ( table-word high-byte? )
- if >< then 255 and \ AVR is little endian
- else
- -9 throw \ index out of range
- then
-;
-
-marker ->crc8
-
-\ populate pad with crc table for CRC8MSB poly in reverse bit order
-: crc8_msb_pad ( -- )
- 0 pad c! \ "table[0] = 0"
- 1 $80 begin \ ( 2ˣ "t" ) x: 0→7
- dup $80 and if CRC8MSB else 0 then
- swap 2* xor \ update "t"
- swap dup 0 do \ ( "t" 2ˣ )
- over pad i + c@ xor \ ( "t" 2ˣ "table[j] ^ t" )
- over pad + i + c! \ "table[i+j] = ..."
- loop
- 2* dup 256 < \ ( "t" 2ˣ⁺¹ flag )
- while swap \ ( 2ˣ⁺¹ "t" )
- repeat
- 2drop
-;
-
-\ populate pad with crc table for CRC8LSB poly in regular bit order
-: crc8_lsb_pad ( -- )
- 0 pad c! \ "table[0] = 0"
- 128 $01 begin \ ( 2ˣ "t") x: 7→0
- dup 1 and if CRC8LSB else 0 then
- swap 2/ xor \ update "t"
- swap 256 0 do \ ( "t" 2ˣ )
- over pad i + c@ xor \ ( "t" 2ˣ "table[j] ^ t" )
- over pad + i + c! \ "table[i+j] = ..."
- dup 2* +loop
- 2/ dup \ ( "t" 2ˣ⁻¹ flag )
- while swap \ ( 2ˣ⁻¹ "t" )
- repeat
- 2drop
-;
-
-\ CRC8REV [if] crc8_msb_pad [else] crc8_lsb_pad [then]
-: crc8_pad CRC8REV if crc8_msb_pad else crc8_lsb_pad then ; crc8_pad
-
-->crc8 \ pad data is preserved
-
-256 fabtab: crc8tb@ \ 256B pad → flash lookup table
-
-\ (*) Using (crc8):
-\ The initial crc-byte should be 255
-\ To the outgoing message append the byte-complement of crc-byte'
-\ The final crc-byte' of a valid incoming message+crc is: 255 crc8tb@
-
-: (crc8) ( crc-byte data-byte -- crc-byte' )
- xor crc8tb@
-;
diff --git a/amforth-6.5/common/lib/debug.frt b/amforth-6.5/common/lib/debug.frt
deleted file mode 100644
index 3fc07ce..0000000
--- a/amforth-6.5/common/lib/debug.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-\ Gerry dlf 31.8.2012 "Single Step Debugging.."
-\ modified: prints a debug prompt. Exits the
-\ debug mode when entering an empty line
-
-\ more usage examples can be found at the cookbook
-\ http://amforth.sf.net/recipes
-
-82 buffer: debugbuf
-: (?) cr ." debug> " debugbuf dup 80 accept ;
-: ?? begin (?) dup while (evaluate) repeat 2drop ;
-\ maybe add a special debug wordlist
diff --git a/amforth-6.5/common/lib/defer-seal.frt b/amforth-6.5/common/lib/defer-seal.frt
deleted file mode 100644
index 9c50a84..0000000
--- a/amforth-6.5/common/lib/defer-seal.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-
-\ ' turnkey defer:seal
-
-: defer:seal ( XT -- )
- dup defer@ ( -- XT' XT )
- swap ( -- XT XT')
- dup ['] quit @i ( get DO_COLON) swap !i
- 1+ dup rot swap !i
- 1+ ['] exit swap !i
-;
-
diff --git a/amforth-6.5/common/lib/dot-base.frt b/amforth-6.5/common/lib/dot-base.frt
deleted file mode 100644
index f3d293c..0000000
--- a/amforth-6.5/common/lib/dot-base.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-
-\ print current BASE in decimal, keep BASE intact
-: .base ( -- )
- base @ dup decimal . base !
-;
diff --git a/amforth-6.5/common/lib/dot-recs.frt b/amforth-6.5/common/lib/dot-recs.frt
deleted file mode 100644
index a14dce0..0000000
--- a/amforth-6.5/common/lib/dot-recs.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-
-\ print the names of the current recognizer stack
-
-#require to-name.frt
-
-: .recs
- get-recognizers 0 ?do
- >name icount $ff and itype space
- loop
-;
diff --git a/amforth-6.5/common/lib/dot-ver.frt b/amforth-6.5/common/lib/dot-ver.frt
deleted file mode 100644
index 9ca17ca..0000000
--- a/amforth-6.5/common/lib/dot-ver.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-
-: .ver
- s" version" environment? if
- s>d <# # [char] . hold #s #> type
- then
-;
diff --git a/amforth-6.5/common/lib/exception.frt b/amforth-6.5/common/lib/exception.frt
deleted file mode 100644
index d9f7a87..0000000
--- a/amforth-6.5/common/lib/exception.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-
-
-\ allocate an exception number
-\ is less than -4096, keeps track in EEPROM
-
--4096 Evalue exception
-: exception ( -- n ) exception dup 1- to exception ;
-
-\ usage
-\ the code sequence
-\ exception constant !!foo
-\ ... if !!foo throw then ...
-\ prints
-\ ?? -4096
-\ and returns to the command prompt if not catched \ No newline at end of file
diff --git a/amforth-6.5/common/lib/execute-parsing.frt b/amforth-6.5/common/lib/execute-parsing.frt
deleted file mode 100644
index a5dc9bc..0000000
--- a/amforth-6.5/common/lib/execute-parsing.frt
+++ /dev/null
@@ -1,25 +0,0 @@
-
-\ execute-parsing
-\ ( addr len XT -- )
-\ execute XT with addr/len as SOURCE
-\
-
-variable xp-addr
-variable xp-len
-
-: xp-source xp-addr @ xp-len @ ;
-
-: execute-parsing ( addr len XT -- )
- xp-addr @ xp-len @ 2>r \ make it nestable
- >r \ save XT temporarily
- xp-len ! xp-addr ! \ prepare new source
- r> \ get back the XT
- ['] source defer@ >in @ 2>r \ save and switch source
- ['] xp-source is SOURCE
- 0 >IN !
- catch \ DO IT
- 2r> >in ! is source \ restore old source
- 2r> xp-len ! xp-addr ! \ restore nested information
- throw \ re-throw exception, if any
-;
-
diff --git a/amforth-6.5/common/lib/find-name.frt b/amforth-6.5/common/lib/find-name.frt
deleted file mode 100644
index df40185..0000000
--- a/amforth-6.5/common/lib/find-name.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-
-\ #require search-name.frt
-
-: (find-name) ( addr len wid -- addr len 0 | nt -1 )
- >r 2dup r> search-name dup if nip nip then ;
-
-: find-name ( addr len -- nt|0 )
- ['] (find-name) cfg-order map-stack
- dup 0= if nip nip then
-;
diff --git a/amforth-6.5/common/lib/flags.frt b/amforth-6.5/common/lib/flags.frt
deleted file mode 100644
index 43fb38b..0000000
--- a/amforth-6.5/common/lib/flags.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ 2008-01-01 EW w4_flags.fs
-
-\ die bits einer Variablen als "flags" benutzen
-
-\ flag@ ( var bitnum -- f ) und flag! ( flag var bitnum -- )
-
-\ variable mainFlags
-\ mainFlags 0 flag: Fdebug
-\ Fdebug fset ( set bit 0 in Variable mainFlags )
-\ Fdebug fclr ( clear bit )
-\ Fdebug fset? ( true if bit is set )
-\ Fdebug fclr? ( true if bit is NOT set )
-
-\ compile time: store address and bitmask into pfa
-\ run time: fetch bitmask and address to stack
-: flag: create ( addr bit -- )
- 1 swap lshift , ,
-does> ( -- bitmask addr )
- dup @i swap 1+ @i
-;
-
-\ bitvalue, convert number of bit [0..7] to mask
-: bv ( bitnumber -- bitmask )
- 1 swap lshift
-;
-
-: fset ( bitmask addr -- )
- dup @ ( mask addr value )
- rot ( addr value mask )
- or ( addr new-value )
- swap !
-;
-
-: fclr ( bitmask addr -- )
- dup @ ( mask addr value )
- rot ( addr value mask )
- invert and ( addr new-value )
- swap !
-;
-
-
-: fset? ( bitmask addr -- t/f )
- @ and 0<>
-;
-
-: fclr? ( bitmask addr -- t/f )
- @ and 0=
-;
-
-: ftgl ( bitmask addr -- )
- over over ( mask addr mask addr )
- fset?
- if fclr else fset then
-;
diff --git a/amforth-6.5/common/lib/for-next.frt b/amforth-6.5/common/lib/for-next.frt
deleted file mode 100644
index 8a29ebf..0000000
--- a/amforth-6.5/common/lib/for-next.frt
+++ /dev/null
@@ -1,18 +0,0 @@
-\ for/next is from colorforth
-\ note that 0 and -1 are executable words, not numbers!
-\
-: for postpone 0
- postpone swap
- postpone do
-; immediate
-
-: next
- postpone -1
- postpone +loop
-; immediate
-
-\ test case
-\ : test 10 for i . next ;
-\ prints
-\ 10 9 8 7 6 5 4 3 2 1 0
-\ \ No newline at end of file
diff --git a/amforth-6.5/common/lib/forth2012/blocks/blocks.frt b/amforth-6.5/common/lib/forth2012/blocks/blocks.frt
deleted file mode 100644
index c11be70..0000000
--- a/amforth-6.5/common/lib/forth2012/blocks/blocks.frt
+++ /dev/null
@@ -1,68 +0,0 @@
-\
-\ simple block wordset
-\ single buffer management.
-\ non-standard block size (to save RAM).
-\ only basic routines. No hardware access
-\
-
-#require defer.frt
-#require buffer.frt
-
-\ high level blocksize, ANS94 says 1024 bytes, SD Cards have 512
-#512 constant blocksize
-variable scr
-
-\ API for low level drivers. They get the
-\ buffer address in RAM and the block number.
-Rdefer load-buffer ( buf-addr u -- )
-Rdefer save-buffer ( buf-addr u -- )
-
-\ single buffer blocks.
-variable blk1
-variable blk1-dirty
-blocksize buffer: blk1-buffer
-
-\ for turnkey
-: block:init
- -1 blk1 !
- 0 blk1-dirty !
-;
-
-: update -1 blk1-dirty ! ;
-: updated? ( u -- f )
- blk1 @ = if
- blk1-dirty @
- else
- 0
- then
-;
-
-\ reloads the block only if the blocknumber differs
-: block ( u -- a-addr )
- dup blk1 @ = if drop else
- blk1 @ updated? if
- blk1-buffer blk1 @ save-buffer
- then
- blk1-buffer swap dup blk1 ! load-buffer
- 0 blk1-dirty !
- then
- blk1-buffer
-;
-
-\ a buffer is an un-initialized block.
-: buffer ( u -- a-addr ) block ;
-
-: save-buffers
- blk1 @ updated? if
- blk1-buffer blk1 @ save-buffer
- then
- 0 blk1-dirty !
-;
-
-: empty-buffers
- -1 blk1 !
- 0 blk1-dirty !
-;
-
-: flush save-buffers empty-buffers ;
-
diff --git a/amforth-6.5/common/lib/forth2012/blocks/list-dump.frt b/amforth-6.5/common/lib/forth2012/blocks/list-dump.frt
deleted file mode 100644
index 28a0df7..0000000
--- a/amforth-6.5/common/lib/forth2012/blocks/list-dump.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-
-\ a trivial list in hexdump format
-#require dump.frt
-
-: list
- dup scr !
- buffer blocksize dump
- scr @ updated? 0= if ." not " then ." modified" cr
-;
-
diff --git a/amforth-6.5/common/lib/forth2012/blocks/list.frt b/amforth-6.5/common/lib/forth2012/blocks/list.frt
deleted file mode 100644
index 2520aeb..0000000
--- a/amforth-6.5/common/lib/forth2012/blocks/list.frt
+++ /dev/null
@@ -1,24 +0,0 @@
-
-\ a list in text format. not suitable
-\ for binary data!
-
-\ #16 constant #lines
-\ #64 constant #cols
-
- #8 constant #lines
-#64 constant #cols
-
-: list ( blk -- ) \ list selected screen
- dup scr !
- dup cr ." Listing of screen (" .
- dup updated? if ." not " then ." modified)" cr
- buffer
- #lines 0
- do
- cr i 0 <# [char] : hold # # #> type space
- dup i #cols * +
- #cols type
- [char] | emit
- loop
- cr
- ;
diff --git a/amforth-6.5/common/lib/forth2012/blocks/load.frt b/amforth-6.5/common/lib/forth2012/blocks/load.frt
deleted file mode 100644
index 55cd14b..0000000
--- a/amforth-6.5/common/lib/forth2012/blocks/load.frt
+++ /dev/null
@@ -1,20 +0,0 @@
-\ load a block and evaluate its content
-\
-: source-block1
- blk1-buffer blocksize
-;
-
-: load ( i*x n -- j*y )
- ['] source defer@ >r >in @ >r
- 0 >in !
- buffer drop
- ['] source-block1 is source
- ['] interpret catch
- r> >in ! r> is source
- throw
-;
-
-
-: thru ( i*x n1 n2 -- j*y )
- 1+ swap ?do i load loop
-;
diff --git a/amforth-6.5/common/lib/forth2012/core-ext/case-test.frt b/amforth-6.5/common/lib/forth2012/core-ext/case-test.frt
deleted file mode 100644
index ad9b1f1..0000000
--- a/amforth-6.5/common/lib/forth2012/core-ext/case-test.frt
+++ /dev/null
@@ -1,7 +0,0 @@
- : foo ( selector -- )
- case
- 3 of ." three" endof
- 5 9 range of ." between" endof
- 1 of ." one" endof
- endcase
- ;
diff --git a/amforth-6.5/common/lib/forth2012/core-ext/case.frt b/amforth-6.5/common/lib/forth2012/core-ext/case.frt
deleted file mode 100644
index 02e73f1..0000000
--- a/amforth-6.5/common/lib/forth2012/core-ext/case.frt
+++ /dev/null
@@ -1,35 +0,0 @@
-\ From: eaker@ukulele.crd.ge.com (Chuck Eaker)
-\ Subject: Re: Wanted .. CASE,OF,ENDOF,ENDCASE
-\ Message-ID: <1992Nov25.164255.23225@crd.ge.com>
-\ Date: 25 Nov 92 16:42:55 GMT
-
-: case 0 ; immediate
-: of ( #of -- orig #of+1 / x -- )
- 1+ ( count OFs )
- >r ( move off the stack in case the control-flow )
- ( stack is the data stack. )
- postpone over postpone = ( copy and test case value )
- postpone if ( add orig to control flow stack )
- postpone drop ( discards case value if = )
- r> ; ( we can bring count back now )
- immediate
-
-: endof ( orig1 #of -- orig2 #of )
- >r ( move off the stack in case the control-flow )
- ( stack is the data stack. )
- postpone else
- r> ; ( we can bring count back now )
- immediate
-
-: endcase ( orig 1..orign #of -- )
- postpone drop ( discard case value )
- 0 ?do
- postpone then
- loop ;
- immediate
-
-
- \ from Message-ID: <ggo2up$67k$1@news-01.bur.connect.com.au>
-: range ( selector low high -- selector x )
- 2>r dup dup 2r> within
- 0= if invert then ;
diff --git a/amforth-6.5/common/lib/forth2012/core-ext/compile-comma.frt b/amforth-6.5/common/lib/forth2012/core-ext/compile-comma.frt
deleted file mode 100644
index 3845e6c..0000000
--- a/amforth-6.5/common/lib/forth2012/core-ext/compile-comma.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ append the XT to the dictionary
-( xt -- )
-: compile, , ;
diff --git a/amforth-6.5/common/lib/forth2012/core-ext/defers.frt b/amforth-6.5/common/lib/forth2012/core-ext/defers.frt
deleted file mode 100644
index 25b9505..0000000
--- a/amforth-6.5/common/lib/forth2012/core-ext/defers.frt
+++ /dev/null
@@ -1,23 +0,0 @@
-
-\ various defer definitions
-\ platform specific examples are available !
-
-\ place the XT in RAM, suitable for frequent changes
-\ but needs to be initialized at startup
-
-: Rdefer ( "name" -- )
- (defer)
- here ,
- ['] Rdefer@ ,
- ['] Rdefer! ,
- 2 allot
-;
-
-\ use the user area to hold the XT. Similiar to
-\ Rdefer but task lokal in multitasking applications
-: Udefer ( u "name" -- )
- (defer)
- , \
- ['] Udefer@ ,
- ['] Udefer! ,
-;
diff --git a/amforth-6.5/common/lib/forth2012/core-ext/exceptions.frt b/amforth-6.5/common/lib/forth2012/core-ext/exceptions.frt
deleted file mode 100644
index ec175a0..0000000
--- a/amforth-6.5/common/lib/forth2012/core-ext/exceptions.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ ******************************************
-\ some exceptions
-\ ******************************************
-
-: ?throw ( f exc -- )
- swap if throw then drop
-;
-
-: ?comp ( -- )
- state @ 0= -&14 ?throw
-;
-
-: ?pairs ( n1 n2 -- )
- - -&22 ?throw
-;
diff --git a/amforth-6.5/common/lib/forth2012/core-ext/roll.frt b/amforth-6.5/common/lib/forth2012/core-ext/roll.frt
deleted file mode 100644
index 385c14a..0000000
--- a/amforth-6.5/common/lib/forth2012/core-ext/roll.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-
-: roll ( x0 x1 .. xn n -- x1 .. xn x0 ) \ core-ext
- dup 0> 0= if
- drop
- else
- swap >r 1- recurse r> swap
- then ;
diff --git a/amforth-6.5/common/lib/forth2012/core/2over.frt b/amforth-6.5/common/lib/forth2012/core/2over.frt
deleted file mode 100644
index cf614ca..0000000
--- a/amforth-6.5/common/lib/forth2012/core/2over.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-\ 2over ( w1 w2 w3 w4 -- w1 w2 w3 w4 w1 w2 ) core two_over
-: 2over
- >r >r
- over over
- r>
- rot rot
- r>
- rot rot ;
diff --git a/amforth-6.5/common/lib/forth2012/core/2swap.frt b/amforth-6.5/common/lib/forth2012/core/2swap.frt
deleted file mode 100644
index 773228e..0000000
--- a/amforth-6.5/common/lib/forth2012/core/2swap.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ 2swap ( w1 w2 w3 w4 -- w3 w4 w1 w2 ) core two_swap
-: 2swap
- rot >r rot r> ;
diff --git a/amforth-6.5/common/lib/forth2012/core/action-of.frt b/amforth-6.5/common/lib/forth2012/core/action-of.frt
deleted file mode 100644
index 894b399..0000000
--- a/amforth-6.5/common/lib/forth2012/core/action-of.frt
+++ /dev/null
@@ -1,14 +0,0 @@
-\ *******************************************
-\ action-of depends on defer@
-\ *******************************************
-
-\ #requires postpone.frt
-
-: action-of
- state @
- if
- postpone ['] postpone defer@
- else
- ' defer@
- then
-; immediate
diff --git a/amforth-6.5/common/lib/forth2012/core/blank.frt b/amforth-6.5/common/lib/forth2012/core/blank.frt
deleted file mode 100644
index a99ae5f..0000000
--- a/amforth-6.5/common/lib/forth2012/core/blank.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-\ fill with blanks
-: blank ( addr n -- )
- bl fill
-;
diff --git a/amforth-6.5/common/lib/forth2012/core/buffer.frt b/amforth-6.5/common/lib/forth2012/core/buffer.frt
deleted file mode 100644
index 10db671..0000000
--- a/amforth-6.5/common/lib/forth2012/core/buffer.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-\ allocate a buffer and give it a name in the dictionary
-\ see http://www.forth200x.org/buffer.html
-
-: buffer: ( n "<spaces>name" )
- \ variable already allocates 1 cell
- variable 1 cells - allot ;
diff --git a/amforth-6.5/common/lib/forth2012/core/char-plus.frt b/amforth-6.5/common/lib/forth2012/core/char-plus.frt
deleted file mode 100644
index c71230e..0000000
--- a/amforth-6.5/common/lib/forth2012/core/char-plus.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ a character has 1 bytes
-: char+ 1+ ;
-
diff --git a/amforth-6.5/common/lib/forth2012/core/chars.frt b/amforth-6.5/common/lib/forth2012/core/chars.frt
deleted file mode 100644
index 254b3dc..0000000
--- a/amforth-6.5/common/lib/forth2012/core/chars.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ a character has 1 byte, multiply by 1 is easy
-: chars ; immediate \ does nothing at all
-
diff --git a/amforth-6.5/common/lib/forth2012/core/count.frt b/amforth-6.5/common/lib/forth2012/core/count.frt
deleted file mode 100644
index 339da65..0000000
--- a/amforth-6.5/common/lib/forth2012/core/count.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-\ ( addr -- addr+1 len )
-: count dup 1+ swap c@ ;
diff --git a/amforth-6.5/common/lib/forth2012/core/dot-paren.frt b/amforth-6.5/common/lib/forth2012/core/dot-paren.frt
deleted file mode 100644
index 6266725..0000000
--- a/amforth-6.5/common/lib/forth2012/core/dot-paren.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-
-: .( \ (s -- )
- [char] ) parse type
-; immediate
-
diff --git a/amforth-6.5/common/lib/forth2012/core/erase.frt b/amforth-6.5/common/lib/forth2012/core/erase.frt
deleted file mode 100644
index eb23f3b..0000000
--- a/amforth-6.5/common/lib/forth2012/core/erase.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-\ fill a memory area with zeros
-
-: erase ( addr n -- )
- 0 fill
-;
-
diff --git a/amforth-6.5/common/lib/forth2012/core/find.frt b/amforth-6.5/common/lib/forth2012/core/find.frt
deleted file mode 100644
index a289cc8..0000000
--- a/amforth-6.5/common/lib/forth2012/core/find.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ #require count.frt
-
-: find ( addr -- addr 0 | xt -1 | xt 1 )
- dup count find-xt dup
- if rot drop then
-;
-
-\ \ find-xt is using the order stack
-\ \ with map-stack as iterator.
-\ : (find-xt) ( addr len wid -- addr len 0 | xt +/-1 -1 )
-\ >r 2dup r> search-wordlist
-\ dup if
-\ >r nip nip r> -1
-\ then
-\ ;
-\
-\ : find-xt
-\ ['] (find-xt) 'ORDER map-stack
-\ 0= if 2drop 0 then
-\ ;
-
diff --git a/amforth-6.5/common/lib/forth2012/core/is.frt b/amforth-6.5/common/lib/forth2012/core/is.frt
deleted file mode 100644
index 9ac18ea..0000000
--- a/amforth-6.5/common/lib/forth2012/core/is.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-
-\ *******************************************
-\ IS depends on defer!
-\ *******************************************
-
-: is
- state @ if
- postpone ['] postpone defer!
- else
- ' defer!
- then
-; immediate
diff --git a/amforth-6.5/common/lib/forth2012/core/move.frt b/amforth-6.5/common/lib/forth2012/core/move.frt
deleted file mode 100644
index 795a8ef..0000000
--- a/amforth-6.5/common/lib/forth2012/core/move.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-\ respect overlapping memory regions a choose
-\ the proper cmove
-: move
- >r 2dup u< if r> cmove> else r> cmove then
-;
diff --git a/amforth-6.5/common/lib/forth2012/core/source-id.frt b/amforth-6.5/common/lib/forth2012/core/source-id.frt
deleted file mode 100644
index aeea963..0000000
--- a/amforth-6.5/common/lib/forth2012/core/source-id.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-
-\ source-id is currently not used
-: source-id ( -- f )
- 0 \ always user input device
-;
diff --git a/amforth-6.5/common/lib/forth2012/core/star-slash.frt b/amforth-6.5/common/lib/forth2012/core/star-slash.frt
deleted file mode 100644
index 4a47ed9..0000000
--- a/amforth-6.5/common/lib/forth2012/core/star-slash.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-\ #require star-slash-mod.frt
-
-: */ */mod nip ;
diff --git a/amforth-6.5/common/lib/forth2012/core/values.frt b/amforth-6.5/common/lib/forth2012/core/values.frt
deleted file mode 100644
index 08bf0a1..0000000
--- a/amforth-6.5/common/lib/forth2012/core/values.frt
+++ /dev/null
@@ -1,16 +0,0 @@
-
-: Uvalue ( n offs -- )
- (value)
- dup ,
- ['] Udefer@ ,
- ['] Udefer! ,
- up@ + !
-;
-
-: Rvalue ( n -- )
- (value)
- here ,
- ['] Rdefer@ ,
- ['] Rdefer! ,
- here ! 2 allot
-;
diff --git a/amforth-6.5/common/lib/forth2012/double.frt b/amforth-6.5/common/lib/forth2012/double.frt
deleted file mode 100644
index 5cd2e14..0000000
--- a/amforth-6.5/common/lib/forth2012/double.frt
+++ /dev/null
@@ -1,9 +0,0 @@
-\ 'double.frt' generated automatically, do not edit
-#include 2constant.frt
-#include 2-fetch.frt
-#include 2nip.frt
-#include 2rot.frt
-#include 2tuck.frt
-#include 2-store.frt
-#include 2variable.frt
-#include m-star-slash.frt
diff --git a/amforth-6.5/common/lib/forth2012/double/2-fetch.frt b/amforth-6.5/common/lib/forth2012/double/2-fetch.frt
deleted file mode 100644
index 9b3a76a..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2-fetch.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ 2@ ( addr -- n1 n2 )
-: 2@
- dup ( -- addr addr )
- cell+ ( -- addr addr+2 )
- @ ( -- addr n2 )
- swap ( -- n2 addr )
- @ ; ( -- n2 n1 )
diff --git a/amforth-6.5/common/lib/forth2012/double/2-store.frt b/amforth-6.5/common/lib/forth2012/double/2-store.frt
deleted file mode 100644
index 93d2402..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2-store.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ 2! ( n1 n2 addr -- )
-: 2!
- swap ( -- n1 addr n2 )
- over ( -- n1 addr n2 addr )
- ! ( -- n1 addr )
- cell+ ( -- n1 addr+2 )
- ! ;
diff --git a/amforth-6.5/common/lib/forth2012/double/2constant.frt b/amforth-6.5/common/lib/forth2012/double/2constant.frt
deleted file mode 100644
index 4f012d3..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2constant.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-
-: 2constant
- create , ,
- does>
- dup 1+ @i swap @i
-;
diff --git a/amforth-6.5/common/lib/forth2012/double/2nip.frt b/amforth-6.5/common/lib/forth2012/double/2nip.frt
deleted file mode 100644
index 04c5599..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2nip.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-\ 2nip ( w1 w2 w3 w4 -- w3 w4 ) gforth two_nip
-: 2nip
- 2swap 2drop ;
-
diff --git a/amforth-6.5/common/lib/forth2012/double/2rot.frt b/amforth-6.5/common/lib/forth2012/double/2rot.frt
deleted file mode 100644
index 4befd64..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2rot.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ 2rot ( w1 w2 w3 w4 w5 w6 -- w3 w4 w5 w6 w1 w2 ) double-ext two_rote
-: 2rot
- >r >r 2swap r> r> 2swap ;
diff --git a/amforth-6.5/common/lib/forth2012/double/2tuck.frt b/amforth-6.5/common/lib/forth2012/double/2tuck.frt
deleted file mode 100644
index 9ad9781..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2tuck.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ 2tuck ( w1 w2 w3 w4 -- w3 w4 w1 w2 w3 w4 ) gforth two_tuck
-: 2tuck
- 2swap 2over ;
diff --git a/amforth-6.5/common/lib/forth2012/double/2variable.frt b/amforth-6.5/common/lib/forth2012/double/2variable.frt
deleted file mode 100644
index f6b63fb..0000000
--- a/amforth-6.5/common/lib/forth2012/double/2variable.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-: 2variable
- here 2 cells allot constant
-;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-equal.frt b/amforth-6.5/common/lib/forth2012/double/d-equal.frt
deleted file mode 100644
index db5a9c6..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-equal.frt
+++ /dev/null
@@ -1,2 +0,0 @@
- ( d1 d2 -- f )
-: d= d- or 0= ;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-greater-zero.frt b/amforth-6.5/common/lib/forth2012/double/d-greater-zero.frt
deleted file mode 100644
index 3628320..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-greater-zero.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-
-\ #require d-less-zero.frt
-
-: d0> ( d -- f)
- 2dup or >r \ not equal zero
- d0< 0= r> and \ and not less zero
- 0= 0= \ normalize to 0/-1 flag
-;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-greater.frt b/amforth-6.5/common/lib/forth2012/double/d-greater.frt
deleted file mode 100644
index 133cdcd..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-greater.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-( d1 d2 -- f )
-: d> d- d0> ;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-less-zero.frt b/amforth-6.5/common/lib/forth2012/double/d-less-zero.frt
deleted file mode 100644
index 973b9da..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-less-zero.frt
+++ /dev/null
@@ -1,2 +0,0 @@
-
-: d0< nip 0< ;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-less.frt b/amforth-6.5/common/lib/forth2012/double/d-less.frt
deleted file mode 100644
index b85cbb8..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-less.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-
-\ #require d-less-zero.frt
-
-( d1 d2 -- f )
-: d< d- d0< ;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-max.frt b/amforth-6.5/common/lib/forth2012/double/d-max.frt
deleted file mode 100644
index fcf979a..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-max.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-: dmax ( d1 d2 -- d ) \ double d-max
- 2over 2over d< if 2swap then 2drop ;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-min.frt b/amforth-6.5/common/lib/forth2012/double/d-min.frt
deleted file mode 100644
index beca796..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-min.frt
+++ /dev/null
@@ -1,2 +0,0 @@
-: dmin ( d1 d2 -- d ) \ double d-min
- 2over 2over d> if 2swap then 2drop ;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-plusstore.frt b/amforth-6.5/common/lib/forth2012/double/d-plusstore.frt
deleted file mode 100644
index c7405b5..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-plusstore.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-: d+! ( d addr -- ) \ same as +! but for double cell numbers
- dup >r 2@ d+ r> 2!
-;
diff --git a/amforth-6.5/common/lib/forth2012/double/d-zero-equal.frt b/amforth-6.5/common/lib/forth2012/double/d-zero-equal.frt
deleted file mode 100644
index a853671..0000000
--- a/amforth-6.5/common/lib/forth2012/double/d-zero-equal.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-( d -- f )
-: d0= or 0= ;
diff --git a/amforth-6.5/common/lib/forth2012/double/m-plus.frt b/amforth-6.5/common/lib/forth2012/double/m-plus.frt
deleted file mode 100644
index f716566..0000000
--- a/amforth-6.5/common/lib/forth2012/double/m-plus.frt
+++ /dev/null
@@ -1,2 +0,0 @@
-
-: m+ s>d d+ ;
diff --git a/amforth-6.5/common/lib/forth2012/double/m-star-slash.frt b/amforth-6.5/common/lib/forth2012/double/m-star-slash.frt
deleted file mode 100644
index 94959d4..0000000
--- a/amforth-6.5/common/lib/forth2012/double/m-star-slash.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-
-: m*/ ( d1 n2 u3 -- dquot ) \ double m-star-slash
- >r s>d >r abs rot rot
- s>d r> xor r> swap >r >r dabs rot tuck um* 2swap um*
- swap >r 0 d+ r> rot rot r@ um/mod rot rot r> um/mod
- nip swap r> if dnegate then
-;
diff --git a/amforth-6.5/common/lib/forth2012/facility.frt b/amforth-6.5/common/lib/forth2012/facility.frt
deleted file mode 100644
index 1be4601..0000000
--- a/amforth-6.5/common/lib/forth2012/facility.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ 'facility.frt' generated automatically, do not edit
-#include ms.frt
-#include time-and-date.frt
diff --git a/amforth-6.5/common/lib/forth2012/facility/ms.frt b/amforth-6.5/common/lib/forth2012/facility/ms.frt
deleted file mode 100644
index 7dfcd5d..0000000
--- a/amforth-6.5/common/lib/forth2012/facility/ms.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-\ a trivial multitasking friendly ms
-: ms 0 ?do pause 1ms loop ;
diff --git a/amforth-6.5/common/lib/forth2012/facility/structures-array.frt b/amforth-6.5/common/lib/forth2012/facility/structures-array.frt
deleted file mode 100644
index 14e62df..0000000
--- a/amforth-6.5/common/lib/forth2012/facility/structures-array.frt
+++ /dev/null
@@ -1,24 +0,0 @@
-
-begin-structure hash
- field: hash.key
- field: hash.value
-end-structure
-
-\ inspired by CELLS
-: hash-cells hash * ;
-
-\ define a hash-array
-: hash:
- hash-cells buffer:
- does>
- swap hash-cells +
-;
-
-\ define an array of some elements hash'es
-4 hash: my-hash
-cr 0 my-hash .
-cr 1 my-hash .
-
-\ store a key/value pair
-42 3 my-hash hash.key !
-4711 3 my-hash hash.value !
diff --git a/amforth-6.5/common/lib/forth2012/facility/structures-test.frt b/amforth-6.5/common/lib/forth2012/facility/structures-test.frt
deleted file mode 100644
index c4e810c..0000000
--- a/amforth-6.5/common/lib/forth2012/facility/structures-test.frt
+++ /dev/null
@@ -1,16 +0,0 @@
-\ simple test example for forth200x structures
-\ define a new data structure named list.
-
-begin-structure list
- field: l.p \ previous
- field: l.n \ next
- field: l.d \ data
-end-structure
-
-\ create an instance of the datastructure list
-\ named listroot
-
-list buffer: listroot
-
-\ access an element from the instance
-$55aa listroot l.d !
diff --git a/amforth-6.5/common/lib/forth2012/facility/structures.frt b/amforth-6.5/common/lib/forth2012/facility/structures.frt
deleted file mode 100644
index 65f8e5e..0000000
--- a/amforth-6.5/common/lib/forth2012/facility/structures.frt
+++ /dev/null
@@ -1,24 +0,0 @@
-\ structures according to http://www.forth200x.org/structures.html
-\ and http://www.forth200x.org/structures2.html
-\ the reference implementation does not work since amforth uses
-\ not the unified memory model for dictionary and data
-
-: +field: ( n1 "<spaces>name" -- n2 )
- create over , +
- does> @i +
-;
-
-: begin-structure
- create dp 0 -1 , \ -1 saves a flash erase when end-structure is executed
- does>
- @i
-;
-
-: end-structure
- swap !i
-;
-
-: cfield: 1 +field: ;
-: field: 2 +field: ;
-\ 2field is not standard, but why not?
-: 2field: 4 +field: ;
diff --git a/amforth-6.5/common/lib/forth2012/facility/time-and-date.frt b/amforth-6.5/common/lib/forth2012/facility/time-and-date.frt
deleted file mode 100644
index aecbeff..0000000
--- a/amforth-6.5/common/lib/forth2012/facility/time-and-date.frt
+++ /dev/null
@@ -1,33 +0,0 @@
-
-
-\ common words for date&time
-
-\ uses timer interrrupt module to call
-\ a background task every second.
-
-\ holds the ever increasing time ticks
-\ unfortunatly, a day has more seconds
-\ a 16bit variable can store.
-2variable time \ the seconds of the current day
-2variable date \ a day number
-
-\ a background task
-: next-second
- time 2@ 1. d+ 2dup
- 86399. d> if
- 2drop 0.
- 1. date d+!
- then
- time 2!
-;
-
-: dateinit
- 0. time 2!
- 0. date 2!
-;
-
-\ simple world. Every month has 30 days
-: time&date ( -- sec min hour day month year )
- date 2@ 365 um/mod 30 /mod ( -- day month year )
- time 2@ 24 um/mod 60 /mod ( -- sec min hour )
-;
diff --git a/amforth-6.5/common/lib/forth2012/file/paren.frt b/amforth-6.5/common/lib/forth2012/file/paren.frt
deleted file mode 100644
index 24c8460..0000000
--- a/amforth-6.5/common/lib/forth2012/file/paren.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-\ redefine (, still buggy
-: (
- begin
- >in @ [char] ) parse nip
- >in @ rot - = \ something found?
- while
- refill 0=
- if
- abort" refill while searching ) failed"
- then
- repeat ; immediate
diff --git a/amforth-6.5/common/lib/forth2012/memory.frt b/amforth-6.5/common/lib/forth2012/memory.frt
deleted file mode 100644
index 82debbf..0000000
--- a/amforth-6.5/common/lib/forth2012/memory.frt
+++ /dev/null
@@ -1,2 +0,0 @@
-\ 'memory.frt' generated automatically, do not edit
-#include memory.frt
diff --git a/amforth-6.5/common/lib/forth2012/search-order.frt b/amforth-6.5/common/lib/forth2012/search-order.frt
deleted file mode 100644
index db7f92a..0000000
--- a/amforth-6.5/common/lib/forth2012/search-order.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-\ include words from the search order wordset
-
-\ from search order
-\ #require set-order.frt
-\ #require get-order.frt
-\ #require also.frt
-\ #require definitions.frt
-\ #require forth.frt
-\ #require previous.frt
-\ #require order.frt
diff --git a/amforth-6.5/common/lib/forth2012/search/also.frt b/amforth-6.5/common/lib/forth2012/search/also.frt
deleted file mode 100644
index 8934ce4..0000000
--- a/amforth-6.5/common/lib/forth2012/search/also.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-\ duplicate first wordlist entry
-
-\ #require get-order.frt
-\ #require set-order.frt
-
-: also ( -- )
- get-order over swap 1+ set-order
-;
diff --git a/amforth-6.5/common/lib/forth2012/search/definitions.frt b/amforth-6.5/common/lib/forth2012/search/definitions.frt
deleted file mode 100644
index 7ab89f0..0000000
--- a/amforth-6.5/common/lib/forth2012/search/definitions.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-\ Make the compilation word list the same as the current first word list in the search order.
-
-\ #require get-order.frt
-
-: definitions ( -- )
- get-order over set-current
- 0 ?do drop loop \ clean up
-;
diff --git a/amforth-6.5/common/lib/forth2012/search/forth.frt b/amforth-6.5/common/lib/forth2012/search/forth.frt
deleted file mode 100644
index 77d6e6f..0000000
--- a/amforth-6.5/common/lib/forth2012/search/forth.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-\ replace the first search order entry
-\ with forth-wordlist
-
-\ #require get-order.frt
-\ #require set-order.frt
-
-: forth
- get-order nip
- forth-wordlist swap set-order
-;
diff --git a/amforth-6.5/common/lib/forth2012/search/get-order.frt b/amforth-6.5/common/lib/forth2012/search/get-order.frt
deleted file mode 100644
index 958df7a..0000000
--- a/amforth-6.5/common/lib/forth2012/search/get-order.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-\ get the ORDER stack
-
-: get-order
- cfg-order get-stack
-; \ No newline at end of file
diff --git a/amforth-6.5/common/lib/forth2012/search/only.frt b/amforth-6.5/common/lib/forth2012/search/only.frt
deleted file mode 100644
index 11d1a22..0000000
--- a/amforth-6.5/common/lib/forth2012/search/only.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ sets the system specific forth wordlist
-
-\ #require set-order.frt
-
-: only
- forth-wordlist 1 set-order
-;
diff --git a/amforth-6.5/common/lib/forth2012/search/order.frt b/amforth-6.5/common/lib/forth2012/search/order.frt
deleted file mode 100644
index b0c4057..0000000
--- a/amforth-6.5/common/lib/forth2012/search/order.frt
+++ /dev/null
@@ -1,9 +0,0 @@
-\ print the wids of the current word list and the search order
-
-\ #require get-order.frt
-
-: order ( -- )
- get-current u. cr
- get-order dup u.
- 0 ?do u. space loop
-;
diff --git a/amforth-6.5/common/lib/forth2012/search/previous.frt b/amforth-6.5/common/lib/forth2012/search/previous.frt
deleted file mode 100644
index 8d78394..0000000
--- a/amforth-6.5/common/lib/forth2012/search/previous.frt
+++ /dev/null
@@ -1,8 +0,0 @@
-\ remove the first entry in the search order list
-
-\ #require get-order.frt
-\ #require set-order.frt
-
-: previous
- get-order nip 1- set-order
-;
diff --git a/amforth-6.5/common/lib/forth2012/search/set-order.frt b/amforth-6.5/common/lib/forth2012/search/set-order.frt
deleted file mode 100644
index 5969ea3..0000000
--- a/amforth-6.5/common/lib/forth2012/search/set-order.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ set a new ORDER stack
-
-: set-order
- dup 0= if -50 throw then \ no empty search order stack
- cfg-order set-stack
-;
-
-\ A better check would be
-\ : set-order
-\ dup 0 [ s" wordlists" environment search-wordlist drop execute ] literal
-\ within if cfg-order set-stack else -50 throw then
-\ ;
-\ \ No newline at end of file
diff --git a/amforth-6.5/common/lib/forth2012/string/search.frt b/amforth-6.5/common/lib/forth2012/string/search.frt
deleted file mode 100644
index 36c0339..0000000
--- a/amforth-6.5/common/lib/forth2012/string/search.frt
+++ /dev/null
@@ -1,23 +0,0 @@
-
-\ mostly from gforth. Minor modifications however..
-
-: str= ( c-addr1 u1 c-addr2 u2 -- f ) \ gforth
- compare 0= ;
-
-: string-prefix? ( c-addr1 u1 c-addr2 u2 -- f ) \ gforth
- \ Is c-addr2 u2 a prefix of c-addr1 u1 ?
- tuck 2>r min 2r> str= ;
-
-: >= < 0= ;
-
-: search ( c-addr1 u1 c-addr2 u2 -- c-addr3 u3 flag ) \ string
- 2>r 2dup
- begin
- dup r@ >= \ 2r@ nip >=
- while
- 2dup 2r@ string-prefix? if
- 2swap 2drop 2r> 2drop true exit
- then
- 1 /string
- repeat
- 2drop 2r> 2drop 0 ;
diff --git a/amforth-6.5/common/lib/forth2012/string/split.frt b/amforth-6.5/common/lib/forth2012/string/split.frt
deleted file mode 100644
index c627ed3..0000000
--- a/amforth-6.5/common/lib/forth2012/string/split.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Newsgroups: comp.lang.forth
-\ Date: Sat, 21 Jun 2014 13:48:57 -0700 (PDT)
-\ From: Julian Fondren <julian....@gmail.com>
-\ slightly modified for amforth (rdrop, false)
-
-\ split a string at the first occurance
-
-\ #require 2over.frt
-\ #require search.frt
-
-: split ( 'string' 'separator' -- 'before' 'after' -1 | 0 )
- dup >r 2over 2swap search 0= if 2drop 2drop r> drop 0 exit then
- 2>r r@ - 2r> r> /string true
-;
-
diff --git a/amforth-6.5/common/lib/forth2012/string/trailing.frt b/amforth-6.5/common/lib/forth2012/string/trailing.frt
deleted file mode 100644
index 51e709d..0000000
--- a/amforth-6.5/common/lib/forth2012/string/trailing.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-: -trailing ( c_addr u1 -- c_addr u2 ) \ string dash-trailing
-\ Adjust the string specified by {c-addr, u1} to remove all
-\ trailing spaces. {u2} is the length of the modified string.
- begin
- dup
- while
- 1- 2dup + c@ bl <>
- until 1+ then ;
diff --git a/amforth-6.5/common/lib/forth2012/tester.frt b/amforth-6.5/common/lib/forth2012/tester.frt
deleted file mode 100644
index cb73a41..0000000
--- a/amforth-6.5/common/lib/forth2012/tester.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-\ 'tester.frt' generated automatically, do not edit
-#include anstests.zip
-#include core.fr
-#include doubletest.fth
-#include searchordertest.txt
-#include tester-amforth.frt
diff --git a/amforth-6.5/common/lib/forth2012/tester/anstests.zip b/amforth-6.5/common/lib/forth2012/tester/anstests.zip
deleted file mode 100644
index 34dc1bd..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/anstests.zip
+++ /dev/null
Binary files differ
diff --git a/amforth-6.5/common/lib/forth2012/tester/anstests0.9.zip b/amforth-6.5/common/lib/forth2012/tester/anstests0.9.zip
deleted file mode 100644
index 89ad461..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/anstests0.9.zip
+++ /dev/null
Binary files differ
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-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-\ T{ : GT3 GT2 LITERAL ; -> }T
-\ T{ GT3 -> ' GT1 }T
-\ T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-
-
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
diff --git a/amforth-6.5/common/lib/forth2012/tester/coreexttest.fth b/amforth-6.5/common/lib/forth2012/tester/coreexttest.fth
deleted file mode 100644
index a7de63d..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/coreexttest.fth
+++ /dev/null
@@ -1,322 +0,0 @@
-\ To test some of the ANS Forth Core Extension word set
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.6 1 April 2012 Tests placed in the public domain.
-\ SAVE-INPUT & RESTORE-INPUT tests, position
-\ of T{ moved so that tests work with ttester.fs
-\ CONVERT test deleted - obsolete word removed from Forth 200X
-\ IMMEDIATE VALUEs tested
-\ RECURSE with :NONAME tested
-\ PARSE and .( tested
-\ Parsing behaviour of C" added
-\ 0.5 14 September 2011 Removed the double [ELSE] from the
-\ initial SAVE-INPUT & RESTORE-INPUT test
-\ 0.4 30 November 2009 max-int replaced with max-intx to
-\ avoid redefinition warnings.
-\ 0.3 6 March 2009 { and } replaced with T{ and }T
-\ CONVERT test now independent of cell size
-\ 0.2 20 April 2007 ANS Forth words changed to upper case
-\ Tests qd3 to qd6 by Reinhold Straub
-\ 0.1 Oct 2006 First version released
-\ ------------------------------------------------------------------------------
-\ This is only a partial test of the core extension words.
-\ The tests are based on John Hayes test program for the core word set
-
-\ Words tested in this file are:
-\ TRUE FALSE :NONAME ?DO VALUE TO CASE OF ENDOF ENDCASE PARSE
-\ C" CONVERT COMPILE, [COMPILE] SAVE-INPUT RESTORE-INPUT .(
-\ ------------------------------------------------------------------------------
-\ Assumptions:
-\ - tester.fr or ttester.fs has been included prior to this file
-\ ------------------------------------------------------------------------------
-TESTING Core Extension words
-
-DECIMAL
-
-0 INVERT 1 RSHIFT CONSTANT max-intx \ 01...1
-
-
-TESTING TRUE FALSE
-
-T{ TRUE -> 0 INVERT }T
-T{ FALSE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING :NONAME with and without RECURSEs
-
-VARIABLE nn1
-VARIABLE nn2
-:NONAME 1234 ; nn1 !
-:NONAME 9876 ; nn2 !
-T{ nn1 @ EXECUTE -> 1234 }T
-T{ nn2 @ EXECUTE -> 9876 }T
-
-T{ :NONAME ( n -- 0,1,..n ) DUP IF DUP >R 1- RECURSE R> THEN ;
- CONSTANT rn1 -> }T
-T{ 0 rn1 EXECUTE -> 0 }T
-T{ 4 rn1 EXECUTE -> 0 1 2 3 4 }T
-
-:NONAME ( n -- n1 ) \ Multiple RECURSEs in one definition
- 1- DUP
- CASE 0 OF EXIT ENDOF
- 1 OF 11 SWAP RECURSE ENDOF
- 2 OF 22 SWAP RECURSE ENDOF
- 3 OF 33 SWAP RECURSE ENDOF
- DROP ABS RECURSE EXIT
- ENDCASE
-; CONSTANT rn2
-
-T{ 1 rn2 EXECUTE -> 0 }T
-T{ 2 rn2 EXECUTE -> 11 0 }T
-T{ 4 rn2 EXECUTE -> 33 22 11 0 }T
-T{ 25 rn2 EXECUTE -> 33 22 11 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING ?DO
-
-: qd ?DO I LOOP ;
-T{ 789 789 qd -> }T
-T{ -9876 -9876 qd -> }T
-T{ 5 0 qd -> 0 1 2 3 4 }T
-
-: qd1 ?DO I 10 +LOOP ;
-T{ 50 1 qd1 -> 1 11 21 31 41 }T
-T{ 50 0 qd1 -> 0 10 20 30 40 }T
-
-: qd2 ?DO I 3 > IF LEAVE ELSE I THEN LOOP ;
-T{ 5 -1 qd2 -> -1 0 1 2 3 }T
-
-: qd3 ?DO I 1 +LOOP ;
-T{ 4 4 qd3 -> }T
-T{ 4 1 qd3 -> 1 2 3 }T
-T{ 2 -1 qd3 -> -1 0 1 }T
-
-: qd4 ?DO I -1 +LOOP ;
-T{ 4 4 qd4 -> }T
-T{ 1 4 qd4 -> 4 3 2 1 }T
-T{ -1 2 qd4 -> 2 1 0 -1 }T
-
-: qd5 ?DO I -10 +LOOP ;
-T{ 1 50 qd5 -> 50 40 30 20 10 }T
-T{ 0 50 qd5 -> 50 40 30 20 10 0 }T
-T{ -25 10 qd5 -> 10 0 -10 -20 }T
-
-VARIABLE iters
-VARIABLE incrmnt
-
-: qd6 ( limit start increment -- )
- incrmnt !
- 0 iters !
- ?DO
- 1 iters +!
- I
- iters @ 6 = IF LEAVE THEN
- incrmnt @
- +LOOP iters @
-;
-
-T{ 4 4 -1 qd6 -> 0 }T
-T{ 1 4 -1 qd6 -> 4 3 2 1 4 }T
-T{ 4 1 -1 qd6 -> 1 0 -1 -2 -3 -4 6 }T
-T{ 4 1 0 qd6 -> 1 1 1 1 1 1 6 }T
-T{ 0 0 0 qd6 -> 0 }T
-T{ 1 4 0 qd6 -> 4 4 4 4 4 4 6 }T
-T{ 1 4 1 qd6 -> 4 5 6 7 8 9 6 }T
-T{ 4 1 1 qd6 -> 1 2 3 3 }T
-T{ 4 4 1 qd6 -> 0 }T
-T{ 2 -1 -1 qd6 -> -1 -2 -3 -4 -5 -6 6 }T
-T{ -1 2 -1 qd6 -> 2 1 0 -1 4 }T
-T{ 2 -1 0 qd6 -> -1 -1 -1 -1 -1 -1 6 }T
-T{ -1 2 0 qd6 -> 2 2 2 2 2 2 6 }T
-T{ -1 2 1 qd6 -> 2 3 4 5 6 7 6 }T
-T{ 2 -1 1 qd6 -> -1 0 1 3 }T
-
-\ ------------------------------------------------------------------------------
-TESTING VALUE TO
-
-T{ 111 VALUE val1 -999 VALUE val2 -> }T
-T{ val1 -> 111 }T
-T{ val2 -> -999 }T
-T{ 222 TO val1 -> }T
-T{ val1 -> 222 }T
-T{ : vd1 val1 ; -> }T
-T{ vd1 -> 222 }T
-T{ : vd2 TO val2 ; -> }T
-T{ val2 -> -999 }T
-T{ -333 vd2 -> }T
-T{ val2 -> -333 }T
-T{ val1 -> 222 }T
-T{ 123 VALUE val3 IMMEDIATE val3 -> 123 }T
-T{ : vd3 val3 LITERAL ; vd3 -> 123 }T
-
-\ ------------------------------------------------------------------------------
-TESTING CASE OF ENDOF ENDCASE
-
-: cs1 CASE 1 OF 111 ENDOF
- 2 OF 222 ENDOF
- 3 OF 333 ENDOF
- >R 999 R>
- ENDCASE
-;
-
-T{ 1 cs1 -> 111 }T
-T{ 2 cs1 -> 222 }T
-T{ 3 cs1 -> 333 }T
-T{ 4 cs1 -> 999 }T
-
-: cs2 >R CASE -1 OF CASE R@ 1 OF 100 ENDOF
- 2 OF 200 ENDOF
- >R -300 R>
- ENDCASE
- ENDOF
- -2 OF CASE R@ 1 OF -99 ENDOF
- >R -199 R>
- ENDCASE
- ENDOF
- >R 299 R>
- ENDCASE R> DROP
-;
-
-T{ -1 1 cs2 -> 100 }T
-T{ -1 2 cs2 -> 200 }T
-T{ -1 3 cs2 -> -300 }T
-T{ -2 1 cs2 -> -99 }T
-T{ -2 2 cs2 -> -199 }T
-T{ 0 2 cs2 -> 299 }T
-
-\ ------------------------------------------------------------------------------
-TESTING C"
-
-T{ : cq1 C" 123" ; -> }T
-T{ cq1 COUNT EVALUATE -> 123 }T
-T{ : cq2 C" " ; -> }T
-T{ cq2 COUNT EVALUATE -> }T
-T{ : cq3 C" 2345"COUNT EVALUATE ; cq3 -> 2345 }T
-
-\ ------------------------------------------------------------------------------
-TESTING COMPILE, [COMPILE]
-
-:NONAME DUP + ; CONSTANT dup+
-T{ : q dup+ COMPILE, ; -> }T
-T{ : as1 [ q ] ; -> }T
-T{ 123 as1 -> 246 }T
-
-T{ : [c1] [COMPILE] DUP ; IMMEDIATE -> }T
-T{ 123 [c1] -> 123 123 }T \ With default compilation semantics
-T{ : [c2] [COMPILE] [c1] ; -> }T
-T{ 234 [c2] -> 234 234 }T \ With an immediate word
-T{ : [cif] [COMPILE] IF ; IMMEDIATE -> }T
-T{ : [c3] [cif] 111 ELSE 222 THEN ; -> }T \ With special compilation semantics
-T{ -1 [c3] -> 111 }T
-T{ 0 [c3] -> 222 }T
-
-\ ------------------------------------------------------------------------------
-\ Cannot automatically test SAVE-INPUT and RESTORE-INPUT from a console source
-
-TESTING SAVE-INPUT and RESTORE-INPUT with a file source
-
-VARIABLE siv -1 siv !
-
-: NeverExecuted
- ." This should never be executed" ABORT
-;
-
-T{ 11111 SAVE-INPUT
-
-siv @
-
-[IF]
- 0 siv !
- RESTORE-INPUT
- NeverExecuted
-[ELSE]
-
-TESTING the -[ELSE]- part is executed
-22222
-
-[THEN]
-
- -> 11111 0 22222 }T \ 0 comes from RESTORE-INPUT
-
-TESTING SAVE-INPUT and RESTORE-INPUT with a string source
-
-VARIABLE si_inc 0 si_inc !
-
-: si1
- si_inc @ >IN +!
- 15 si_inc !
-;
-
-: s$ S" SAVE-INPUT si1 RESTORE-INPUT 12345" ;
-
-T{ s$ EVALUATE si_inc @ -> 0 2345 15 }T
-
-TESTING nested SAVE-INPUT and RESTORE-INPUT
-
-: read_a_line
- REFILL 0=
- ABORT" REFILL failed"
-;
-
-0 si_inc !
-
-2VARIABLE 2res -1. 2res 2!
-
-: si2
- read_a_line
- read_a_line
- SAVE-INPUT
- read_a_line
- read_a_line
- s$ EVALUATE 2res 2!
- RESTORE-INPUT
-;
-
-\ WARNING: do not delete or insert lines of text after si2 is called
-\ otherwise the next test will fail
-
-T{ si2
-33333 \ This line should be ignored
-2res 2@ 44444 \ RESTORE-INPUT should return to this line
-
-55555
-TESTING the nested results
- -> 0 0 2345 44444 55555 }T
-
-\ End of warning
-
-\ ------------------------------------------------------------------------------
-TESTING .(
-
-T{ S" A string"2DROP -> }T
-T{ CR .( You should see -9876: ) -9876 . -> }T
-T{ CR .( Repeated: ).( -9876)CR -> }T
-
-\ ------------------------------------------------------------------------------
-TESTING PARSE
-
-T{ CHAR | PARSE 1234| DUP ROT ROT EVALUATE -> 4 1234 }T
-T{ CHAR ^ PARSE 23 45 ^ DUP ROT ROT EVALUATE -> 7 23 45 }T
-: pa1 [CHAR] $ PARSE DUP >R PAD SWAP CHARS MOVE PAD R> ;
-T{ pa1 3456
- DUP ROT ROT EVALUATE -> 4 3456 }T
-T{ CHAR a PARSE a SWAP DROP -> 0 }T
-T{ CHAR z PARSE
- SWAP DROP -> 0 }T
-T{ CHAR " PARSE 4567 "DUP ROT ROT EVALUATE -> 5 4567 }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of Core Extension word tests) CR
-
-
diff --git a/amforth-6.5/common/lib/forth2012/tester/coreplustest.fth b/amforth-6.5/common/lib/forth2012/tester/coreplustest.fth
deleted file mode 100644
index ff165d4..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/coreplustest.fth
+++ /dev/null
@@ -1,190 +0,0 @@
-\ Additional tests on the the ANS Forth Core word set
-
-\ This program was written by Gerry Jackson in 2007, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.3 1 April 2012 Tests placed in the public domain.
-\ Testing multiple ELSE's.
-\ Further tests on DO +LOOPs.
-\ Ackermann function added to test RECURSE.
-\ >IN manipulation in interpreter mode
-\ Immediate CONSTANTs, VARIABLEs and CREATEd words tests.
-\ :NONAME with RECURSE moved to core extension tests.
-\ Parsing behaviour of S" ." and ( tested
-\ 0.2 6 March 2009 { and } replaced with T{ and }T
-\ Added extra RECURSE tests
-\ 0.1 20 April 2007 Created
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\
-\ This file provides some more tests on Core words where the original Hayes
-\ tests are thought to be incomplete
-\
-\ Words tested in this file are:
-\ DO +LOOP RECURSE ELSE >IN IMMEDIATE
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ - core.fr has been loaded so that constants MAX-INT, MIN-INT and
-\ MAX-UINT are defined
-\ ------------------------------------------------------------------------------
-
-DECIMAL
-
-TESTING DO +LOOP with run-time increment, negative increment, infinite loop
-\ Contributed by Reinhold Straub
-
-VARIABLE iterations
-VARIABLE increment
-: gd7 ( limit start increment -- )
- increment !
- 0 iterations !
- DO
- 1 iterations +!
- I
- iterations @ 6 = IF LEAVE THEN
- increment @
- +LOOP iterations @
-;
-
-T{ 4 4 -1 gd7 -> 4 1 }T
-T{ 1 4 -1 gd7 -> 4 3 2 1 4 }T
-T{ 4 1 -1 gd7 -> 1 0 -1 -2 -3 -4 6 }T
-T{ 4 1 0 gd7 -> 1 1 1 1 1 1 6 }T
-T{ 0 0 0 gd7 -> 0 0 0 0 0 0 6 }T
-T{ 1 4 0 gd7 -> 4 4 4 4 4 4 6 }T
-T{ 1 4 1 gd7 -> 4 5 6 7 8 9 6 }T
-T{ 4 1 1 gd7 -> 1 2 3 3 }T
-T{ 4 4 1 gd7 -> 4 5 6 7 8 9 6 }T
-T{ 2 -1 -1 gd7 -> -1 -2 -3 -4 -5 -6 6 }T
-T{ -1 2 -1 gd7 -> 2 1 0 -1 4 }T
-T{ 2 -1 0 gd7 -> -1 -1 -1 -1 -1 -1 6 }T
-T{ -1 2 0 gd7 -> 2 2 2 2 2 2 6 }T
-T{ -1 2 1 gd7 -> 2 3 4 5 6 7 6 }T
-T{ 2 -1 1 gd7 -> -1 0 1 3 }T
-T{ -20 30 -10 gd7 -> 30 20 10 0 -10 -20 6 }T
-T{ -20 31 -10 gd7 -> 31 21 11 1 -9 -19 6 }T
-T{ -20 29 -10 gd7 -> 29 19 9 -1 -11 5 }T
-
-\ ------------------------------------------------------------------------------
-TESTING DO +LOOP with large and small increments
-
-\ Contributed by Andrew Haley
-
-MAX-UINT 8 RSHIFT 1+ CONSTANT ustep
-ustep NEGATE CONSTANT -ustep
-MAX-INT 7 RSHIFT 1+ CONSTANT step
-step NEGATE CONSTANT -step
-
-VARIABLE bump
-
-T{ : gd8 bump ! DO 1+ bump @ +LOOP ; -> }T
-
-T{ 0 MAX-UINT 0 ustep gd8 -> 256 }T
-T{ 0 0 MAX-UINT -ustep gd8 -> 256 }T
-
-T{ 0 MAX-INT MIN-INT step gd8 -> 256 }T
-T{ 0 MIN-INT MAX-INT -step gd8 -> 256 }T
-
-\ Two's complement arithmetic, wraps around modulo wordsize
-\ Only tested if the Forth system does wrap around, use of conditional
-\ compilation deliberately avoided
-
-MAX-INT 1+ MIN-INT = CONSTANT +wrap?
-MIN-INT 1- MAX-INT = CONSTANT -wrap?
-MAX-UINT 1+ 0= CONSTANT +uwrap?
-0 1- MAX-UINT = CONSTANT -uwrap?
-
-: gd9 ( n limit start step f result -- )
- >R IF gd8 ELSE 2DROP 2DROP R@ THEN -> R> }T
-;
-
-T{ 0 0 0 ustep +uwrap? 256 gd9
-T{ 0 0 0 -ustep -uwrap? 1 gd9
-T{ 0 MIN-INT MAX-INT step +wrap? 1 gd9
-T{ 0 MAX-INT MIN-INT -step -wrap? 1 gd9
-
-\ ------------------------------------------------------------------------------
-TESTING DO +LOOP with maximum and minimum increments
-
-: (-mi) MAX-INT DUP NEGATE + 0= IF MAX-INT NEGATE ELSE -32767 THEN ;
-(-mi) CONSTANT -max-int
-
-T{ 0 1 0 MAX-INT gd8 -> 1 }T
-T{ 0 -max-int NEGATE -max-int OVER gd8 -> 2 }T
-
-T{ 0 MAX-INT 0 MAX-INT gd8 -> 1 }T
-T{ 0 MAX-INT 1 MAX-INT gd8 -> 1 }T
-T{ 0 MAX-INT -1 MAX-INT gd8 -> 2 }T
-T{ 0 MAX-INT dup 1- MAX-INT gd8 -> 1 }T
-
-T{ 0 MIN-INT 1+ 0 MIN-INT gd8 -> 1 }T
-T{ 0 MIN-INT 1+ -1 MIN-INT gd8 -> 1 }T
-T{ 0 MIN-INT 1+ 1 MIN-INT gd8 -> 2 }T
-T{ 0 MIN-INT 1+ DUP MIN-INT gd8 -> 1 }T
-
-\ ------------------------------------------------------------------------------
-TESTING multiple RECURSEs in one colon definition
-
-: ack ( m n -- u ) \ Ackermann function, from Rosetta Code
- OVER 0= IF NIP 1+ EXIT THEN \ ack(0, n) = n+1
- SWAP 1- SWAP ( -- m-1 n )
- DUP 0= IF 1+ RECURSE EXIT THEN \ ack(m, 0) = ack(m-1, 1)
- 1- OVER 1+ SWAP RECURSE RECURSE \ ack(m, n) = ack(m-1, ack(m,n-1))
-;
-
-T{ 0 0 ack -> 1 }T
-T{ 3 0 ack -> 5 }T
-T{ 2 4 ack -> 11 }T
-
-\ ------------------------------------------------------------------------------
-TESTING multiple ELSE's in an IF statement
-\ Discussed on comp.lang.forth and accepted as valid ANS Forth
-
-: melse IF 1 ELSE 2 ELSE 3 ELSE 4 ELSE 5 THEN ;
-T{ 0 melse -> 2 4 }T
-T{ -1 melse -> 1 3 5 }T
-
-\ ------------------------------------------------------------------------------
-TESTING manipulation of >IN in interpreter mode
-
-T{ 123456 depth over 9 < 35 and + 3 + >in ! -> 123456 23456 3456 456 56 6 }T
-T{ 14145 8115 ?dup 0= 34 and >in +! tuck mod 14 >in ! GCD calculation -> 15 }T
-
-\ ------------------------------------------------------------------------------
-TESTING IMMEDIATE with CONSTANT VARIABLE and CREATE [ ... DOES> ]
-
-T{ 123 CONSTANT iw1 IMMEDIATE iw1 -> 123 }T
-T{ : iw2 iw1 LITERAL ; iw2 -> 123 }T
-T{ VARIABLE iw3 IMMEDIATE 234 iw3 ! iw3 @ -> 234 }T
-T{ : iw4 iw3 [ @ ] LITERAL ; iw4 -> 234 }T
-T{ :noname [ 345 ] iw3 [ ! ] ; DROP iw3 @ -> 345 }T
-T{ CREATE iw5 456 , IMMEDIATE -> }T
-T{ :noname iw5 [ @ iw3 ! ] ; DROP iw3 @ -> 456 }T
-T{ : iw6 CREATE , IMMEDIATE DOES> @ 1+ ; -> }T
-T{ 111 iw6 iw7 iw7 -> 112 }T
-T{ : iw8 iw7 LITERAL 1+ ; iw8 -> 113 }T
-T{ : iw9 CREATE , DOES> @ 2 + IMMEDIATE ; -> }T
-: find-iw bl word find nip ; ( -- 0 | 1 | -1 )
-T{ 222 iw9 iw10 find-iw iw10 -> -1 }T \ iw10 is not immediate
-T{ iw10 find-iw iw10 -> 224 1 }T \ iw10 becomes immediate
-
-\ ------------------------------------------------------------------------------
-TESTING parsing behaviour of S" ." and (
-\ which should parse to just beyond the terminating character no space needed
-
-T{ S" A string"2DROP -> }T
-T{ ( A comment)1234 -> 1234 }T
-T{ : pb1 cr ." You should see 2345: "." 2345"( A comment); pb1 -> }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of additional Core tests) CR
diff --git a/amforth-6.5/common/lib/forth2012/tester/doubletest.fth b/amforth-6.5/common/lib/forth2012/tester/doubletest.fth
deleted file mode 100644
index 523b110..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/doubletest.fth
+++ /dev/null
@@ -1,386 +0,0 @@
-\ To test the ANS Forth Double-Number word set and double number extensions
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-\ ------------------------------------------------------------------------------
-\ Version 0.6 1 April 2012 Tests placed in the public domain.
-\ Immediate 2CONSTANTs and 2VARIABLEs tested
-\ 0.5 20 November 2009 Various constants renamed to avoid
-\ redefinition warnings. <true> and <false> replaced
-\ with TRUE and FALSE
-\ 0.4 6 March 2009 { and } replaced with T{ and }T
-\ Tests rewritten to be independent of word size and
-\ tests re-ordered
-\ 0.3 20 April 2007 ANS Forth words changed to upper case
-\ 0.2 30 Oct 2006 Updated following GForth test to include
-\ various constants from core.fr
-\ 0.1 Oct 2006 First version released
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-
-\ Words tested in this file are:
-\ 2CONSTANT 2LITERAL 2VARIABLE D+ D- D. D.R D0< D0= D2* D2/
-\ D< D= D>S DABS DMAX DMIN DNEGATE M*/ M+ 2ROT DU<
-\ Also tests the interpreter and compiler reading a double number
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - tester.fr or ttester.fs has been included prior to this file
-\ - core words and core extension words have been tested
-\ ------------------------------------------------------------------------------
-\ Constant definitions
-
-DECIMAL
-0 INVERT CONSTANT 1sd
-1sd 1 RSHIFT CONSTANT max-intd \ 01...1
-max-intd INVERT CONSTANT min-intd \ 10...0
-max-intd 2/ CONSTANT hi-int \ 001...1
-min-intd 2/ CONSTANT lo-int \ 110...1
-
-\ ------------------------------------------------------------------------------
-TESTING interpreter and compiler reading a double number
-
-T{ 1. -> 1 0 }T
-T{ -2. -> -2 -1 }T
-T{ : rdl1 3. ; rdl1 -> 3 0 }T
-T{ : rdl2 -4. ; rdl2 -> -4 -1 }T
-
-\ ------------------------------------------------------------------------------
-TESTING 2CONSTANT
-
-T{ 1 2 2CONSTANT 2c1 -> }T
-T{ 2c1 -> 1 2 }T
-T{ : cd1 2c1 ; -> }T
-T{ cd1 -> 1 2 }T
-T{ : cd2 2CONSTANT ; -> }T
-T{ -1 -2 cd2 2c2 -> }T
-T{ 2c2 -> -1 -2 }T
-T{ 4 5 2CONSTANT 2c3 IMMEDIATE 2c3 -> 4 5 }T
-T{ : cd6 2c3 2LITERAL ; cd6 -> 4 5 }T
-
-\ ------------------------------------------------------------------------------
-\ Some 2CONSTANTs for the following tests
-
-1sd max-intd 2CONSTANT max-2int \ 01...1
-0 min-intd 2CONSTANT min-2int \ 10...0
-max-2int 2/ 2CONSTANT hi-2int \ 001...1
-min-2int 2/ 2CONSTANT lo-2int \ 110...0
-
-\ ------------------------------------------------------------------------------
-TESTING DNEGATE
-
-T{ 0. DNEGATE -> 0. }T
-T{ 1. DNEGATE -> -1. }T
-T{ -1. DNEGATE -> 1. }T
-T{ max-2int DNEGATE -> min-2int SWAP 1+ SWAP }T
-T{ min-2int SWAP 1+ SWAP DNEGATE -> max-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING D+ with small integers
-
-T{ 0. 5. D+ -> 5. }T
-T{ -5. 0. D+ -> -5. }T
-T{ 1. 2. D+ -> 3. }T
-T{ 1. -2. D+ -> -1. }T
-T{ -1. 2. D+ -> 1. }T
-T{ -1. -2. D+ -> -3. }T
-T{ -1. 1. D+ -> 0. }T
-
-TESTING D+ with mid range integers
-
-T{ 0 0 0 5 D+ -> 0 5 }T
-T{ -1 5 0 0 D+ -> -1 5 }T
-T{ 0 0 0 -5 D+ -> 0 -5 }T
-T{ 0 -5 -1 0 D+ -> -1 -5 }T
-T{ 0 1 0 2 D+ -> 0 3 }T
-T{ -1 1 0 -2 D+ -> -1 -1 }T
-T{ 0 -1 0 2 D+ -> 0 1 }T
-T{ 0 -1 -1 -2 D+ -> -1 -3 }T
-T{ -1 -1 0 1 D+ -> -1 0 }T
-T{ min-intd 0 2DUP D+ -> 0 1 }T
-T{ min-intd S>D min-intd 0 D+ -> 0 0 }T
-
-TESTING D+ with large double integers
-
-T{ hi-2int 1. D+ -> 0 hi-int 1+ }T
-T{ hi-2int 2DUP D+ -> 1sd 1- max-intd }T
-T{ max-2int min-2int D+ -> -1. }T
-T{ max-2int lo-2int D+ -> hi-2int }T
-T{ hi-2int min-2int D+ 1. D+ -> lo-2int }T
-T{ lo-2int 2DUP D+ -> min-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING D- with small integers
-
-T{ 0. 5. D- -> -5. }T
-T{ 5. 0. D- -> 5. }T
-T{ 0. -5. D- -> 5. }T
-T{ 1. 2. D- -> -1. }T
-T{ 1. -2. D- -> 3. }T
-T{ -1. 2. D- -> -3. }T
-T{ -1. -2. D- -> 1. }T
-T{ -1. -1. D- -> 0. }T
-
-TESTING D- with mid-range integers
-
-T{ 0 0 0 5 D- -> 0 -5 }T
-T{ -1 5 0 0 D- -> -1 5 }T
-T{ 0 0 -1 -5 D- -> 1 4 }T
-T{ 0 -5 0 0 D- -> 0 -5 }T
-T{ -1 1 0 2 D- -> -1 -1 }T
-T{ 0 1 -1 -2 D- -> 1 2 }T
-T{ 0 -1 0 2 D- -> 0 -3 }T
-T{ 0 -1 0 -2 D- -> 0 1 }T
-T{ 0 0 0 1 D- -> 0 -1 }T
-T{ min-intd 0 2DUP D- -> 0. }T
-T{ min-intd S>D max-intd 0 D- -> 1 1sd }T
-
-TESTING D- with large integers
-
-T{ max-2int max-2int D- -> 0. }T
-T{ min-2int min-2int D- -> 0. }T
-T{ max-2int hi-2int D- -> lo-2int DNEGATE }T
-T{ hi-2int lo-2int D- -> max-2int }T
-T{ lo-2int hi-2int D- -> min-2int 1. D+ }T
-T{ min-2int min-2int D- -> 0. }T
-T{ min-2int lo-2int D- -> lo-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING D0< D0=
-
-T{ 0. D0< -> FALSE }T
-T{ 1. D0< -> FALSE }T
-T{ min-intd 0 D0< -> FALSE }T
-T{ 0 max-intd D0< -> FALSE }T
-T{ max-2int D0< -> FALSE }T
-T{ -1. D0< -> TRUE }T
-T{ min-2int D0< -> TRUE }T
-
-T{ 1. D0= -> FALSE }T
-T{ min-intd 0 D0= -> FALSE }T
-T{ max-2int D0= -> FALSE }T
-T{ -1 max-intd D0= -> FALSE }T
-T{ 0. D0= -> TRUE }T
-T{ -1. D0= -> FALSE }T
-T{ 0 min-intd D0= -> FALSE }T
-
-\ ------------------------------------------------------------------------------
-TESTING D2* D2/
-
-T{ 0. D2* -> 0. D2* }T
-T{ min-intd 0 D2* -> 0 1 }T
-T{ hi-2int D2* -> max-2int 1. D- }T
-T{ lo-2int D2* -> min-2int }T
-
-T{ 0. D2/ -> 0. }T
-T{ 1. D2/ -> 0. }T
-T{ 0 1 D2/ -> min-intd 0 }T
-T{ max-2int D2/ -> hi-2int }T
-T{ -1. D2/ -> -1. }T
-T{ min-2int D2/ -> lo-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING D< D=
-
-T{ 0. 1. D< -> TRUE }T
-T{ 0. 0. D< -> FALSE }T
-T{ 1. 0. D< -> FALSE }T
-T{ -1. 1. D< -> TRUE }T
-T{ -1. 0. D< -> TRUE }T
-T{ -2. -1. D< -> TRUE }T
-T{ -1. -2. D< -> FALSE }T
-T{ -1. max-2int D< -> TRUE }T
-T{ min-2int max-2int D< -> TRUE }T
-T{ max-2int -1. D< -> FALSE }T
-T{ max-2int min-2int D< -> FALSE }T
-T{ max-2int 2DUP -1. D+ D< -> FALSE }T
-T{ min-2int 2DUP 1. D+ D< -> TRUE }T
-
-T{ -1. -1. D= -> TRUE }T
-T{ -1. 0. D= -> FALSE }T
-T{ -1. 1. D= -> FALSE }T
-T{ 0. -1. D= -> FALSE }T
-T{ 0. 0. D= -> TRUE }T
-T{ 0. 1. D= -> FALSE }T
-T{ 1. -1. D= -> FALSE }T
-T{ 1. 0. D= -> FALSE }T
-T{ 1. 1. D= -> TRUE }T
-
-T{ 0 -1 0 -1 D= -> TRUE }T
-T{ 0 -1 0 0 D= -> FALSE }T
-T{ 0 -1 0 1 D= -> FALSE }T
-T{ 0 0 0 -1 D= -> FALSE }T
-T{ 0 0 0 0 D= -> TRUE }T
-T{ 0 0 0 1 D= -> FALSE }T
-T{ 0 1 0 -1 D= -> FALSE }T
-T{ 0 1 0 0 D= -> FALSE }T
-T{ 0 1 0 1 D= -> TRUE }T
-
-T{ max-2int min-2int D= -> FALSE }T
-T{ max-2int 0. D= -> FALSE }T
-T{ max-2int max-2int D= -> TRUE }T
-T{ max-2int hi-2int D= -> FALSE }T
-T{ max-2int min-2int D= -> FALSE }T
-T{ min-2int min-2int D= -> TRUE }T
-T{ min-2int lo-2int D= -> FALSE }T
-T{ min-2int max-2int D= -> FALSE }T
-
-\ ------------------------------------------------------------------------------
-TESTING 2LITERAL 2VARIABLE
-
-T{ : cd3 [ max-2int ] 2LITERAL ; -> }T
-T{ cd3 -> max-2int }T
-T{ 2VARIABLE 2v1 -> }T
-T{ 0. 2v1 2! -> }T
-T{ 2v1 2@ -> 0. }T
-T{ -1 -2 2v1 2! -> }T
-T{ 2v1 2@ -> -1 -2 }T
-T{ : cd4 2VARIABLE ; -> }T
-T{ cd4 2v2 -> }T
-T{ : cd5 2v2 2! ; -> }T
-T{ -2 -1 cd5 -> }T
-T{ 2v2 2@ -> -2 -1 }T
-T{ 2VARIABLE 2v3 IMMEDIATE 5 6 2v3 2! -> }T
-T{ 2v3 2@ -> 5 6 }T
-T{ : cd7 2v3 [ 2@ ] 2LITERAL ; cd7 -> 5 6 }T
-T{ : cd8 [ 6 7 ] 2v3 [ 2! ] ; 2v3 2@ -> 6 7 }T
-
-\ ------------------------------------------------------------------------------
-TESTING DMAX DMIN
-
-T{ 1. 2. DMAX -> 2. }T
-T{ 1. 0. DMAX -> 1. }T
-T{ 1. -1. DMAX -> 1. }T
-T{ 1. 1. DMAX -> 1. }T
-T{ 0. 1. DMAX -> 1. }T
-T{ 0. -1. DMAX -> 0. }T
-T{ -1. 1. DMAX -> 1. }T
-T{ -1. -2. DMAX -> -1. }T
-
-T{ max-2int hi-2int DMAX -> max-2int }T
-T{ max-2int min-2int DMAX -> max-2int }T
-T{ min-2int max-2int DMAX -> max-2int }T
-T{ min-2int lo-2int DMAX -> lo-2int }T
-
-T{ max-2int 1. DMAX -> max-2int }T
-T{ max-2int -1. DMAX -> max-2int }T
-T{ min-2int 1. DMAX -> 1. }T
-T{ min-2int -1. DMAX -> -1. }T
-
-
-T{ 1. 2. DMIN -> 1. }T
-T{ 1. 0. DMIN -> 0. }T
-T{ 1. -1. DMIN -> -1. }T
-T{ 1. 1. DMIN -> 1. }T
-T{ 0. 1. DMIN -> 0. }T
-T{ 0. -1. DMIN -> -1. }T
-T{ -1. 1. DMIN -> -1. }T
-T{ -1. -2. DMIN -> -2. }T
-
-T{ max-2int hi-2int DMIN -> hi-2int }T
-T{ max-2int min-2int DMIN -> min-2int }T
-T{ min-2int max-2int DMIN -> min-2int }T
-T{ min-2int lo-2int DMIN -> min-2int }T
-
-T{ max-2int 1. DMIN -> 1. }T
-T{ max-2int -1. DMIN -> -1. }T
-T{ min-2int 1. DMIN -> min-2int }T
-T{ min-2int -1. DMIN -> min-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING D>S DABS
-
-T{ 1234 0 D>S -> 1234 }T
-T{ -1234 -1 D>S -> -1234 }T
-T{ max-intd 0 D>S -> max-intd }T
-T{ min-intd -1 D>S -> min-intd }T
-
-T{ 1. DABS -> 1. }T
-T{ -1. DABS -> 1. }T
-T{ max-2int DABS -> max-2int }T
-T{ min-2int 1. D+ DABS -> max-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING M+ M*/
-
-T{ hi-2int 1 M+ -> hi-2int 1. D+ }T
-T{ max-2int -1 M+ -> max-2int -1. D+ }T
-T{ min-2int 1 M+ -> min-2int 1. D+ }T
-T{ lo-2int -1 M+ -> lo-2int -1. D+ }T
-
-\ To correct the result if the division is floored, only used when
-\ necessary i.e. negative quotient and remainder <> 0
-
-: ?floored [ -3 2 / -2 = ] LITERAL IF 1. D- THEN ;
-
-T{ 5. 7 11 M*/ -> 3. }T
-T{ 5. -7 11 M*/ -> -3. ?floored }T \ floored -4.
-T{ -5. 7 11 M*/ -> -3. ?floored }T \ floored -4.
-T{ -5. -7 11 M*/ -> 3. }T
-T{ max-2int 8 16 M*/ -> hi-2int }T
-T{ max-2int -8 16 M*/ -> hi-2int DNEGATE ?floored }T \ floored subtract 1
-T{ min-2int 8 16 M*/ -> lo-2int }T
-T{ min-2int -8 16 M*/ -> lo-2int DNEGATE }T
-T{ max-2int max-intd max-intd M*/ -> max-2int }T
-T{ max-2int max-intd 2/ max-intd M*/ -> max-intd 1- hi-2int NIP }T
-T{ min-2int lo-2int NIP DUP NEGATE M*/ -> min-2int }T
-T{ min-2int lo-2int NIP 1- max-intd M*/ -> min-intd 3 + hi-2int NIP 2 + }T
-T{ max-2int lo-2int NIP DUP NEGATE M*/ -> max-2int DNEGATE }T
-T{ min-2int max-intd DUP M*/ -> min-2int }T
-
-\ ------------------------------------------------------------------------------
-TESTING D. D.R
-
-\ Create some large double numbers
-max-2int 71 73 M*/ 2CONSTANT dbl1
-min-2int 73 79 M*/ 2CONSTANT dbl2
-
-: d>ascii ( d -- caddr u )
- DUP >R <# DABS #S R> SIGN #> ( -- caddr1 u )
- HERE SWAP 2DUP 2>R CHARS DUP ALLOT MOVE 2R>
-;
-
-dbl1 d>ascii 2CONSTANT "dbl1"
-dbl2 d>ascii 2CONSTANT "dbl2"
-
-: DoubleOutput
- CR ." You should see lines duplicated:" CR
- 5 SPACES "dbl1" TYPE CR
- 5 SPACES dbl1 D. CR
- 8 SPACES "dbl1" DUP >R TYPE CR
- 5 SPACES dbl1 R> 3 + D.R CR
- 5 SPACES "dbl2" TYPE CR
- 5 SPACES dbl2 D. CR
- 10 SPACES "dbl2" DUP >R TYPE CR
- 5 SPACES dbl2 R> 5 + D.R CR
-;
-
-T{ DoubleOutput -> }T
-
-\ ------------------------------------------------------------------------------
-TESTING 2ROT DU< (Double Number extension words)
-
-T{ 1. 2. 3. 2ROT -> 2. 3. 1. }T
-T{ max-2int min-2int 1. 2ROT -> min-2int 1. max-2int }T
-
-T{ 1. 1. DU< -> FALSE }T
-T{ 1. -1. DU< -> TRUE }T
-T{ -1. 1. DU< -> FALSE }T
-T{ -1. -2. DU< -> FALSE }T
-
-T{ max-2int hi-2int DU< -> FALSE }T
-T{ hi-2int max-2int DU< -> TRUE }T
-T{ max-2int min-2int DU< -> TRUE }T
-T{ min-2int max-2int DU< -> FALSE }T
-T{ min-2int lo-2int DU< -> TRUE }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of Double-Number word tests) CR
-
diff --git a/amforth-6.5/common/lib/forth2012/tester/exceptiontest.fth b/amforth-6.5/common/lib/forth2012/tester/exceptiontest.fth
deleted file mode 100644
index 7b612bf..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/exceptiontest.fth
+++ /dev/null
@@ -1,96 +0,0 @@
-\ To test the ANS Forth Exception word set and extension words
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.4 1 April 2012 Tests placed in the public domain.
-\ 0.3 6 March 2009 { and } replaced with T{ and }T
-\ 0.2 20 April 2007 ANS Forth words changed to upper case
-\ 0.1 Oct 2006 First version released
-
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\
-\ Words tested in this file are:
-\ CATCH THROW ABORT ABORT"
-\
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - the forth system under test throws an exception with throw
-\ code -13 for a word not found by the text interpreter. The
-\ undefined word used is $$qweqweqwert$$, if this happens to be
-\ a valid word in your system change the definition of t7 below
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ - CASE, OF, ENDOF and ENDCASE from the core extension wordset
-\ are present and work correctly
-\ ------------------------------------------------------------------------------
-TESTING CATCH THROW
-
-DECIMAL
-
-: t1 9 ;
-: c1 1 2 3 ['] t1 CATCH ;
-T{ c1 -> 1 2 3 9 0 }T \ No THROW executed
-
-: t2 8 0 THROW ;
-: c2 1 2 ['] t2 CATCH ;
-T{ c2 -> 1 2 8 0 }T \ 0 THROW does nothing
-
-: t3 7 8 9 99 THROW ;
-: c3 1 2 ['] t3 CATCH ;
-T{ c3 -> 1 2 99 }T \ Restores stack to CATCH depth
-
-: t4 1- DUP 0> IF RECURSE ELSE 999 THROW -222 THEN ;
-: c4 3 4 5 10 ['] t4 CATCH -111 ;
-T{ c4 -> 3 4 5 0 999 -111 }T \ Test return stack unwinding
-
-: t5 2DROP 2DROP 9999 THROW ;
-: c5 1 2 3 4 ['] t5 CATCH \ Test depth restored correctly
- DEPTH >R DROP 2DROP 2DROP R> ; \ after stack has been emptied
-T{ c5 -> 5 }T
-
-\ ------------------------------------------------------------------------------
-TESTING ABORT ABORT"
-
--1 CONSTANT exc_abort
--2 CONSTANT exc_abort"
--13 CONSTANT exc_undef
-: t6 ABORT ;
-
-\ The 77 in t10 is necessary for the second ABORT" test as the data stack
-\ is restored to a depth of 2 when THROW is executed. The 77 ensures the top
-\ of stack value is known for the results check
-
-: t10 77 SWAP ABORT" This should not be displayed" ;
-: c6 CATCH
- CASE exc_abort OF 11 ENDOF
- exc_abort" OF 12 ENDOF
- exc_undef OF 13 ENDOF
- ENDCASE
-;
-
-T{ 1 2 ' t6 c6 -> 1 2 11 }T \ Test that ABORT is caught
-T{ 3 0 ' t10 c6 -> 3 77 }T \ ABORT" does nothing
-T{ 4 5 ' t10 c6 -> 4 77 12 }T \ ABORT" caught, no message
-
-\ ------------------------------------------------------------------------------
-TESTING a system generated exception
-
-: t7 S" 333 $$qweqweqwert$$ 334" EVALUATE 335 ;
-: t8 S" 222 t7 223" EVALUATE 224 ;
-: t9 S" 111 112 t8 113" EVALUATE 114 ;
-
-T{ 6 7 ' t9 c6 3 -> 6 7 13 3 }T \ Test unlinking of sources
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of Exception word tests) CR
-
diff --git a/amforth-6.5/common/lib/forth2012/tester/filetest.fth b/amforth-6.5/common/lib/forth2012/tester/filetest.fth
deleted file mode 100644
index 0364360..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/filetest.fth
+++ /dev/null
@@ -1,193 +0,0 @@
-\ To test the ANS File Access word set and extension words
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.5 1 April 2012 Tests placed in the public domain.
-\ 0.4 22 March 2009 { and } replaced with T{ and }T
-\ 0.3 20 April 2007 ANS Forth words changed to upper case.
-\ Removed directory test from the filenames.
-\ 0.2 30 Oct 2006 updated following GForth tests to remove
-\ system dependency on file size, to allow for file
-\ buffering and to allow for PAD moving around.
-\ 0.1 Oct 2006 First version released.
-
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\ and requires those files to have been loaded
-
-\ Words tested in this file are:
-\ ( BIN CLOSE-FILE CREATE-FILE DELETE-FILE FILE-POSITION FILE-SIZE
-\ OPEN-FILE R/O R/W READ-FILE READ-LINE REPOSITION-FILE RESIZE-FILE
-\ S" SOURCE-ID W/O WRITE-FILE WRITE-LINE
-\ FILE-STATUS FLUSH-FILE RENAME-FILE
-
-\ Words not tested:
-\ REFILL INCLUDED INCLUDE-FILE (as these will likely have been
-\ tested in the execution of the test files)
-\ ------------------------------------------------------------------------------
-\ Assumptions, dependencies and notes:
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ - These tests create files in the current directory, if all goes
-\ well these will be deleted. If something fails they may not be
-\ deleted. If this is a problem ensure you set a suitable
-\ directory before running this test. There is no ANS standard
-\ way of doing this. Also be aware of the file names used below
-\ which are: fatest1.txt, fatest2.txt and fatest3.txt
-\ - TRUE and FALSE are present from the Core extension word set
-\ ------------------------------------------------------------------------------
-
-TESTING File Access word set
-
-DECIMAL
-
-\ ------------------------------------------------------------------------------
-TESTING CREATE-FILE CLOSE-FILE
-
-: fn1 S" fatest1.txt" ;
-VARIABLE fid1
-
-T{ fn1 R/W CREATE-FILE SWAP fid1 ! -> 0 }T
-T{ fid1 @ CLOSE-FILE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING OPEN-FILE W/O WRITE-LINE
-
-: line1 S" Line 1" ;
-
-T{ fn1 W/O OPEN-FILE SWAP fid1 ! -> 0 }T
-T{ line1 fid1 @ WRITE-LINE -> 0 }T
-T{ fid1 @ CLOSE-FILE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING R/O FILE-POSITION (simple) READ-LINE
-
-200 CONSTANT bsize
-CREATE buf bsize ALLOT
-VARIABLE #chars
-
-T{ fn1 R/O OPEN-FILE SWAP fid1 ! -> 0 }T
-T{ fid1 @ FILE-POSITION -> 0. 0 }T
-T{ buf 100 fid1 @ READ-LINE ROT DUP #chars ! -> TRUE 0 line1 SWAP DROP }T
-T{ buf #chars @ line1 COMPARE -> 0 }T
-T{ fid1 @ CLOSE-FILE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING R/W WRITE-FILE REPOSITION-FILE READ-FILE FILE-POSITION S"
-
-: line2 S" Line 2 blah blah blah" ;
-: rl1 buf 100 fid1 @ READ-LINE ;
-2VARIABLE fp
-
-T{ fn1 R/W OPEN-FILE SWAP fid1 ! -> 0 }T
-T{ fid1 @ FILE-SIZE DROP fid1 @ REPOSITION-FILE -> 0 }T
-T{ fid1 @ FILE-SIZE -> fid1 @ FILE-POSITION }T
-T{ line2 fid1 @ WRITE-FILE -> 0 }T
-T{ 10. fid1 @ REPOSITION-FILE -> 0 }T
-T{ fid1 @ FILE-POSITION -> 10. 0 }T
-T{ 0. fid1 @ REPOSITION-FILE -> 0 }T
-T{ rl1 -> line1 SWAP DROP TRUE 0 }T
-T{ rl1 ROT DUP #chars ! -> TRUE 0 line2 SWAP DROP }T
-T{ buf #chars @ line2 COMPARE -> 0 }T
-T{ rl1 -> 0 FALSE 0 }T
-T{ fid1 @ FILE-POSITION ROT ROT fp 2! -> 0 }T
-T{ fp 2@ fid1 @ FILE-SIZE DROP D= -> TRUE }T
-T{ S" " fid1 @ WRITE-LINE -> 0 }T
-T{ S" " fid1 @ WRITE-LINE -> 0 }T
-T{ fp 2@ fid1 @ REPOSITION-FILE -> 0 }T
-T{ rl1 -> 0 TRUE 0 }T
-T{ rl1 -> 0 TRUE 0 }T
-T{ rl1 -> 0 FALSE 0 }T
-T{ fid1 @ CLOSE-FILE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING BIN READ-FILE FILE-SIZE
-
-: cbuf buf bsize 0 FILL ;
-: fn2 S" fatest2.txt" ;
-VARIABLE fid2
-: setpad PAD 50 0 DO I OVER C! CHAR+ LOOP DROP ;
-
-setpad \ If anything else is defined setpad must be called again
- \ as pad may move
-
-T{ fn2 R/W BIN CREATE-FILE SWAP fid2 ! -> 0 }T
-T{ PAD 50 fid2 @ WRITE-FILE fid2 @ FLUSH-FILE -> 0 0 }T
-T{ fid2 @ FILE-SIZE -> 50. 0 }T
-T{ 0. fid2 @ REPOSITION-FILE -> 0 }T
-T{ cbuf buf 29 fid2 @ READ-FILE -> 29 0 }T
-T{ PAD 29 buf 29 COMPARE -> 0 }T
-T{ PAD 30 buf 30 COMPARE -> 1 }T
-T{ cbuf buf 29 fid2 @ READ-FILE -> 21 0 }T
-T{ PAD 29 + 21 buf 21 COMPARE -> 0 }T
-T{ fid2 @ FILE-SIZE DROP fid2 @ FILE-POSITION DROP D= -> TRUE }T
-T{ buf 10 fid2 @ READ-FILE -> 0 0 }T
-T{ fid2 @ CLOSE-FILE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING RESIZE-FILE
-
-T{ fn2 R/W BIN OPEN-FILE SWAP fid2 ! -> 0 }T
-T{ 37. fid2 @ RESIZE-FILE -> 0 }T
-T{ fid2 @ FILE-SIZE -> 37. 0 }T
-T{ 0. fid2 @ REPOSITION-FILE -> 0 }T
-T{ cbuf buf 100 fid2 @ READ-FILE -> 37 0 }T
-T{ PAD 37 buf 37 COMPARE -> 0 }T
-T{ PAD 38 buf 38 COMPARE -> 1 }T
-T{ 500. fid2 @ RESIZE-FILE -> 0 }T
-T{ fid2 @ FILE-SIZE -> 500. 0 }T
-T{ 0. fid2 @ REPOSITION-FILE -> 0 }T
-T{ cbuf buf 100 fid2 @ READ-FILE -> 100 0 }T
-T{ PAD 37 buf 37 COMPARE -> 0 }T
-T{ fid2 @ CLOSE-FILE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING DELETE-FILE
-
-T{ fn2 DELETE-FILE -> 0 }T
-T{ fn2 R/W BIN OPEN-FILE SWAP DROP 0= -> FALSE }T
-T{ fn2 DELETE-FILE 0= -> FALSE }T
-
-\ ------------------------------------------------------------------------------
-TESTING multi-line ( comments
-
-T{ ( 1 2 3
-4 5 6
-7 8 9 ) 11 22 33 -> 11 22 33 }T
-
-\ ------------------------------------------------------------------------------
-TESTING SOURCE-ID (can only test it does not return 0 or -1)
-
-T{ SOURCE-ID DUP -1 = SWAP 0= OR -> FALSE }T
-
-\ ------------------------------------------------------------------------------
-TESTING RENAME-FILE FILE-STATUS FLUSH-FILE
-
-: fn3 S" fatest3.txt" ;
-: >end fid1 @ FILE-SIZE DROP fid1 @ REPOSITION-FILE ;
-
-
-T{ fn3 DELETE-FILE DROP -> }T
-T{ fn1 fn3 RENAME-FILE 0= -> TRUE }T
-T{ fn1 FILE-STATUS SWAP DROP 0= -> FALSE }T
-T{ fn3 FILE-STATUS SWAP DROP 0= -> TRUE }T \ Return value is undefined
-T{ fn3 R/W OPEN-FILE SWAP fid1 ! -> 0 }T
-T{ >end -> 0 }T
-T{ S" Final line" fid1 @ WRITE-LINE -> 0 }T
-T{ fid1 @ FLUSH-FILE -> 0 }T \ Can only test FLUSH-FILE doesn't fail
-T{ fid1 @ CLOSE-FILE -> 0 }T
-
-\ Tidy the test folder
-T{ fn3 DELETE-FILE DROP -> }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of File-Access word tests) CR
diff --git a/amforth-6.5/common/lib/forth2012/tester/memorytest.fth b/amforth-6.5/common/lib/forth2012/tester/memorytest.fth
deleted file mode 100644
index 1967fc3..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/memorytest.fth
+++ /dev/null
@@ -1,93 +0,0 @@
-\ To test the ANS Forth Memory-Allocation word set
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.7 1 April 2012 Tests placed in the public domain.
-\ 0.6 30 January 2011 CHECKMEM modified to work with ttester.fs
-\ 0.5 30 November 2009 <false> replaced with FALSE
-\ 0.4 9 March 2009 Aligned test improved and data space pointer tested
-\ 0.3 6 March 2009 { and } replaced with T{ and }T
-\ 0.2 20 April 2007 ANS Forth words changed to upper case
-\ 0.1 October 2006 First version released
-
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\ and requires those files to have been loaded
-
-\ Words tested in this file are:
-\ ALLOCATE FREE RESIZE
-\
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - that 'addr -1 ALLOCATE' and 'addr -1 RESIZE' will return an error
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ - testing FREE failing is not done as it is likely to crash the
-\ system
-\ ------------------------------------------------------------------------------
-
-TESTING Memory-Allocation word set
-
-DECIMAL
-
-\ ------------------------------------------------------------------------------
-TESTING ALLOCATE FREE RESIZE
-
-VARIABLE addr1
-VARIABLE datsp
-
-HERE datsp !
-T{ 100 ALLOCATE SWAP addr1 ! -> 0 }T
-T{ addr1 @ ALIGNED -> addr1 @ }T \ Test address is aligned
-T{ HERE -> datsp @ }T \ Check data space pointer is unchanged
-T{ addr1 @ FREE -> 0 }T
-
-T{ 99 ALLOCATE SWAP addr1 ! -> 0 }T
-T{ addr1 @ ALIGNED -> addr1 @ }T
-T{ addr1 @ FREE -> 0 }T
-
-T{ 50 ALLOCATE SWAP addr1 ! -> 0 }T
-
-: writemem 0 DO I 1+ OVER C! 1+ LOOP DROP ; ( ad n -- )
-
-\ checkmem is defined this way to maintain compatibility with both
-\ tester.fr and ttester.fs which differ in their definitions of T{
-
-: checkmem ( ad n --- )
- 0
- DO
- >R
- T{ R@ C@ -> R> I 1+ SWAP >R }T
- R> 1+
- LOOP
- DROP
-;
-
-addr1 @ 50 writemem addr1 @ 50 checkmem
-
-T{ addr1 @ 28 RESIZE SWAP addr1 ! -> 0 }T
-addr1 @ 28 checkmem
-
-T{ addr1 @ 200 RESIZE SWAP addr1 ! -> 0 }T
-addr1 @ 28 checkmem
-
-\ ------------------------------------------------------------------------------
-TESTING failure of RESIZE and ALLOCATE (unlikely to be enough memory)
-
-T{ addr1 @ -1 RESIZE 0= -> addr1 @ FALSE }T
-
-T{ addr1 @ FREE -> 0 }T
-
-T{ -1 ALLOCATE SWAP DROP 0= -> FALSE }T \ Memory allocate failed
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of Memory-Allocation word tests) CR
diff --git a/amforth-6.5/common/lib/forth2012/tester/postponetest.fs b/amforth-6.5/common/lib/forth2012/tester/postponetest.fs
deleted file mode 100644
index b178be6..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/postponetest.fs
+++ /dev/null
@@ -1,379 +0,0 @@
-\ checks that postpone works correctly with words with special
-\ compilation semantics
-
-\ by M. Anton Ertl 1996
-
-\ This file is based on John Hayes' core.fr (coretest.fs), which has
-\ the following copyright notice:
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-
-\ my contributions to this file are in the public domain
-
-\ you have to load John Hayes' tester.fs (=tester.fr) and coretest.fs
-\ (core.fr) first
-
-\ These tests are especially useful for showing that state-smart
-\ implementations of words with special compilation semantics,
-\ combined with a straight-forward implementation of POSTPONE (and
-\ [COMPILE]) do not conform to the ANS Forth standard. The essential
-\ sentences in the standad are:
-
-\ 6.1.2033 POSTPONE CORE
-\ ...
-\ Compilation: ( <spaces>name -- )
-
-\ Skip leading space delimiters. Parse name delimited by a space. Find
-\ name. Append the compilation semantics of name to the current
-\ definition.
-
-\ 6.2.2530 [COMPILE] bracket-compile CORE EXT
-\ ...
-\ Compilation: ( <spaces>name -- )
-
-\ Skip leading space delimiters. Parse name delimited by a space. Find
-\ name. If name has other than default compilation semantics, append
-\ them to the current definition;...
-
-
-\ Note that the compilation semantics are appended, not some
-\ state-dependent semantics.
-
-\ first I test against a non-ANS solution suggested by Bernd Paysan
-
-: STATE@-NOW ( -- F )
- STATE @ ; IMMEDIATE
-
-: STATE@ ( -- F )
- POSTPONE STATE@-NOW ;
-
-t{ STATE@ -> STATE @ }t
-
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-\ here I test POSTPONE with all core words with special compilation
-\ semantics.
-
-TESTING POSTPONE +LOOP
-
-: POSTPONE-+LOOP
- POSTPONE +LOOP ;
-
-t{ : PGD2 DO I -1 [ POSTPONE-+LOOP ] ; -> }t
-t{ 1 4 PGD2 -> 4 3 2 1 }t
-t{ -1 2 PGD2 -> 2 1 0 -1 }t
-t{ MID-UINT MID-UINT+1 PGD2 -> MID-UINT+1 MID-UINT }t
-
-t{ : PGD4 DO 1 0 DO J LOOP -1 [ POSTPONE-+LOOP ] ; -> }t
-t{ 1 4 PGD4 -> 4 3 2 1 }t
-t{ -1 2 PGD4 -> 2 1 0 -1 }t
-t{ MID-UINT MID-UINT+1 PGD4 -> MID-UINT+1 MID-UINT }t
-
-TESTING POSTPONE ."
-
-: POSTPONE-."
- POSTPONE ." ;
-
-: PDQ2 [ POSTPONE-." YOU SHOULD SEE THIS LATER. " ] CR ;
-: PDQ1 [ POSTPONE-." YOU SHOULD SEE THIS FIRST. " ] CR ;
-t{ PDQ1 PDQ2 -> }t
-
-TESTING POSTPONE ;
-: POSTPONE-;
- POSTPONE ; ;
-
-t{ : PSC [ POSTPONE-; -> }t
-t{ PSC -> }t
-
-TESTING POSTPONE ABORT"
-
-: POSTPONE-ABORT"
- POSTPONE ABORT" ;
-
-t{ : PAQ1 [ POSTPONE-ABORT" THIS SHOULD NOT ABORT" ] ; -> }t
-
-TESTING POSTPONE BEGIN
-: POSTPONE-BEGIN
- POSTPONE BEGIN ;
-
-t{ : PB3 [ POSTPONE-BEGIN ] DUP 5 < WHILE DUP 1+ REPEAT ; -> }t
-t{ 0 PB3 -> 0 1 2 3 4 5 }t
-t{ 4 PB3 -> 4 5 }t
-t{ 5 PB3 -> 5 }t
-t{ 6 PB3 -> 6 }t
-
-t{ : PB4 [ POSTPONE-BEGIN ] DUP 1+ DUP 5 > UNTIL ; -> }t
-t{ 3 PB4 -> 3 4 5 6 }t
-t{ 5 PB4 -> 5 6 }t
-t{ 6 PB4 -> 6 7 }t
-
-t{ : PB5 [ POSTPONE-BEGIN ] DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }t
-t{ 1 PB5 -> 1 345 }t
-t{ 2 PB5 -> 2 345 }t
-t{ 3 PB5 -> 3 4 5 123 }t
-t{ 4 PB5 -> 4 5 123 }t
-t{ 5 PB5 -> 5 123 }t
-
-TESTING POSTPONE DO
-: POSTPONE-DO
- POSTPONE DO ;
-
-t{ : PDO1 [ POSTPONE-DO ] I LOOP ; -> }t
-t{ 4 1 PDO1 -> 1 2 3 }t
-t{ 2 -1 PDO1 -> -1 0 1 }t
-t{ MID-UINT+1 MID-UINT PDO1 -> MID-UINT }t
-
-t{ : PDO2 [ POSTPONE-DO ] I -1 +LOOP ; -> }t
-t{ 1 4 PDO2 -> 4 3 2 1 }t
-t{ -1 2 PDO2 -> 2 1 0 -1 }t
-t{ MID-UINT MID-UINT+1 PDO2 -> MID-UINT+1 MID-UINT }t
-
-t{ : PDO3 [ POSTPONE-DO ] 1 0 [ POSTPONE-DO ] J LOOP LOOP ; -> }t
-t{ 4 1 PDO3 -> 1 2 3 }t
-t{ 2 -1 PDO3 -> -1 0 1 }t
-t{ MID-UINT+1 MID-UINT PDO3 -> MID-UINT }t
-
-t{ : PDO4 [ POSTPONE-DO ] 1 0 [ POSTPONE-DO ] J LOOP -1 +LOOP ; -> }t
-t{ 1 4 PDO4 -> 4 3 2 1 }t
-t{ -1 2 PDO4 -> 2 1 0 -1 }t
-t{ MID-UINT MID-UINT+1 PDO4 -> MID-UINT+1 MID-UINT }t
-
-t{ : PDO5 123 SWAP 0 [ POSTPONE-DO ] I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }t
-t{ 1 PDO5 -> 123 }t
-t{ 5 PDO5 -> 123 }t
-t{ 6 PDO5 -> 234 }t
-
-t{ : PDO6 ( PAT: {0 0},{0 0}{1 0}{1 1},{0 0}{1 0}{1 1}{2 0}{2 1}{2 2} )
- 0 SWAP 0 [ POSTPONE-DO ]
- I 1+ 0 [ POSTPONE-DO ] I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }t
-t{ 1 PDO6 -> 1 }t
-t{ 2 PDO6 -> 3 }t
-t{ 3 PDO6 -> 4 1 2 }t
-
-TESTING POSTPONE DOES>
-: POSTPONE-DOES>
- POSTPONE DOES> ;
-
-t{ : PDOES1 [ POSTPONE-DOES> ] @ 1 + ; -> }t
-t{ : PDOES2 [ POSTPONE-DOES> ] @ 2 + ; -> }t
-t{ CREATE PCR1 -> }t
-t{ PCR1 -> HERE }t
-t{ ' PCR1 >BODY -> HERE }t
-t{ 1 , -> }t
-t{ PCR1 @ -> 1 }t
-t{ PDOES1 -> }t
-t{ PCR1 -> 2 }t
-t{ PDOES2 -> }t
-t{ PCR1 -> 3 }t
-
-t{ : PWEIRD: CREATE [ POSTPONE-DOES> ] 1 + [ POSTPONE-DOES> ] 2 + ; -> }t
-t{ PWEIRD: PW1 -> }t
-t{ ' PW1 >BODY -> HERE }t
-t{ PW1 -> HERE 1 + }t
-t{ PW1 -> HERE 2 + }t
-
-TESTING POSTPONE ELSE
-: POSTPONE-ELSE
- POSTPONE ELSE ;
-
-t{ : PELSE1 IF 123 [ POSTPONE-ELSE ] 234 THEN ; -> }t
-t{ 0 PELSE1 -> 234 }t
-t{ 1 PELSE1 -> 123 }t
-
-t{ : PELSE2 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 [ POSTPONE-ELSE ] 345 THEN ; -> }t
-t{ 1 PELSE2 -> 1 345 }t
-t{ 2 PELSE2 -> 2 345 }t
-t{ 3 PELSE2 -> 3 4 5 123 }t
-t{ 4 PELSE2 -> 4 5 123 }t
-t{ 5 PELSE2 -> 5 123 }t
-
-TESTING POSTPONE IF
-: POSTPONE-IF
- POSTPONE IF ;
-
-t{ : PIF1 [ POSTPONE-IF ] 123 THEN ; -> }t
-t{ : PIF2 [ POSTPONE-IF ] 123 ELSE 234 THEN ; -> }t
-t{ 0 PIF1 -> }t
-t{ 1 PIF1 -> 123 }t
-t{ -1 PIF1 -> 123 }t
-t{ 0 PIF2 -> 234 }t
-t{ 1 PIF2 -> 123 }t
-t{ -1 PIF1 -> 123 }t
-
-t{ : PIF6 ( N -- 0,1,..N ) DUP [ POSTPONE-IF ] DUP >R 1- RECURSE R> THEN ; -> }t
-t{ 0 PIF6 -> 0 }t
-t{ 1 PIF6 -> 0 1 }t
-t{ 2 PIF6 -> 0 1 2 }t
-t{ 3 PIF6 -> 0 1 2 3 }t
-t{ 4 PIF6 -> 0 1 2 3 4 }t
-
-TESTING POSTPONE LITERAL
-: POSTPONE-LITERAL
- POSTPONE LITERAL ;
-
-t{ : PLIT [ 42 POSTPONE-LITERAL ] ; -> }t
-t{ PLIT -> 42 }t
-
-TESTING POSTPONE LOOP
-: POSTPONE-LOOP
- POSTPONE LOOP ;
-
-t{ : PLOOP1 DO I [ POSTPONE-LOOP ] ; -> }t
-t{ 4 1 PLOOP1 -> 1 2 3 }t
-t{ 2 -1 PLOOP1 -> -1 0 1 }t
-t{ MID-UINT+1 MID-UINT PLOOP1 -> MID-UINT }t
-
-t{ : PLOOP3 DO 1 0 DO J [ POSTPONE-LOOP ] [ POSTPONE-LOOP ] ; -> }t
-t{ 4 1 PLOOP3 -> 1 2 3 }t
-t{ 2 -1 PLOOP3 -> -1 0 1 }t
-t{ MID-UINT+1 MID-UINT PLOOP3 -> MID-UINT }t
-
-t{ : PLOOP4 DO 1 0 DO J [ POSTPONE-LOOP ] -1 +LOOP ; -> }t
-t{ 1 4 PLOOP4 -> 4 3 2 1 }t
-t{ -1 2 PLOOP4 -> 2 1 0 -1 }t
-t{ MID-UINT MID-UINT+1 PLOOP4 -> MID-UINT+1 MID-UINT }t
-
-t{ : PLOOP5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN [ POSTPONE-LOOP ] ; -> }t
-t{ 1 PLOOP5 -> 123 }t
-t{ 5 PLOOP5 -> 123 }t
-t{ 6 PLOOP5 -> 234 }t
-
-t{ : PLOOP6 ( PAT: {0 0},{0 0}{1 0}{1 1},{0 0}{1 0}{1 1}{2 0}{2 1}{2 2} )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ [ POSTPONE-LOOP ]
- [ POSTPONE-LOOP ] ; -> }t
-t{ 1 PLOOP6 -> 1 }t
-t{ 2 PLOOP6 -> 3 }t
-t{ 3 PLOOP6 -> 4 1 2 }t
-
-TESTING POSTPONE POSTPONE
-: POSTPONE-POSTPONE
- POSTPONE POSTPONE ;
-
-t{ : PPP1 123 ; -> }t
-t{ : PPP4 [ POSTPONE-POSTPONE PPP1 ] ; IMMEDIATE -> }t
-t{ : PPP5 PPP4 ; -> }t
-t{ PPP5 -> 123 }t
-t{ : PPP6 345 ; IMMEDIATE -> }t
-t{ : PPP7 [ POSTPONE-POSTPONE PPP6 ] ; -> }t
-t{ PPP7 -> 345 }t
-
-TESTING POSTPONE RECURSE
-: POSTPONE-RECURSE
- POSTPONE RECURSE ;
-
-t{ : GREC ( N -- 0,1,..N ) DUP IF DUP >R 1- [ POSTPONE-RECURSE ] R> THEN ; -> }t
-t{ 0 GREC -> 0 }t
-t{ 1 GREC -> 0 1 }t
-t{ 2 GREC -> 0 1 2 }t
-t{ 3 GREC -> 0 1 2 3 }t
-t{ 4 GREC -> 0 1 2 3 4 }t
-
-TESTING POSTPONE REPEAT
-: POSTPONE-REPEAT
- POSTPONE REPEAT ;
-
-t{ : PREP3 BEGIN DUP 5 < WHILE DUP 1+ [ POSTPONE-REPEAT ] ; -> }t
-t{ 0 PREP3 -> 0 1 2 3 4 5 }t
-t{ 4 PREP3 -> 4 5 }t
-t{ 5 PREP3 -> 5 }t
-t{ 6 PREP3 -> 6 }t
-
-t{ : PREP5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ [ POSTPONE-REPEAT ] 123 ELSE 345 THEN ; -> }t
-t{ 1 PREP5 -> 1 345 }t
-t{ 2 PREP5 -> 2 345 }t
-t{ 3 PREP5 -> 3 4 5 123 }t
-t{ 4 PREP5 -> 4 5 123 }t
-t{ 5 PREP5 -> 5 123 }t
-
-TESTING POSTPONE S"
-: POSTPONE-S"
- POSTPONE S" ;
-
-t{ : PSQ4 [ POSTPONE-S" XY" ] ; -> }t
-t{ PSQ4 SWAP DROP -> 2 }t
-t{ PSQ4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }t
-
-TESTING POSTPONE THEN
-: POSTPONE-THEN
- POSTPONE THEN ;
-
-t{ : PTH1 IF 123 [ POSTPONE-THEN ] ; -> }t
-t{ : PTH2 IF 123 ELSE 234 [ POSTPONE-THEN ] ; -> }t
-t{ 0 PTH1 -> }t
-t{ 1 PTH1 -> 123 }t
-t{ -1 PTH1 -> 123 }t
-t{ 0 PTH2 -> 234 }t
-t{ 1 PTH2 -> 123 }t
-t{ -1 PTH1 -> 123 }t
-
-t{ : PTH5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 [ POSTPONE-THEN ] ; -> }t
-t{ 1 PTH5 -> 1 345 }t
-t{ 2 PTH5 -> 2 345 }t
-t{ 3 PTH5 -> 3 4 5 123 }t
-t{ 4 PTH5 -> 4 5 123 }t
-t{ 5 PTH5 -> 5 123 }t
-
-t{ : PTH6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> [ POSTPONE-THEN ] ; -> }t
-t{ 0 PTH6 -> 0 }t
-t{ 1 PTH6 -> 0 1 }t
-t{ 2 PTH6 -> 0 1 2 }t
-t{ 3 PTH6 -> 0 1 2 3 }t
-t{ 4 PTH6 -> 0 1 2 3 4 }t
-
-TESTING POSTPONE UNTIL
-: POSTPONE-UNTIL
- POSTPONE UNTIL ;
-
-t{ : PUNT4 BEGIN DUP 1+ DUP 5 > [ POSTPONE-UNTIL ] ; -> }t
-t{ 3 PUNT4 -> 3 4 5 6 }t
-t{ 5 PUNT4 -> 5 6 }t
-t{ 6 PUNT4 -> 6 7 }t
-
-TESTING POSTPONE WHILE
-: POSTPONE-WHILE
- POSTPONE WHILE ;
-
-t{ : PWH3 BEGIN DUP 5 < [ POSTPONE-WHILE ] DUP 1+ REPEAT ; -> }t
-t{ 0 PWH3 -> 0 1 2 3 4 5 }t
-t{ 4 PWH3 -> 4 5 }t
-t{ 5 PWH3 -> 5 }t
-t{ 6 PWH3 -> 6 }t
-
-t{ : PWH5 BEGIN DUP 2 > [ POSTPONE-WHILE ] DUP 5 < [ POSTPONE-WHILE ] DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }t
-t{ 1 PWH5 -> 1 345 }t
-t{ 2 PWH5 -> 2 345 }t
-t{ 3 PWH5 -> 3 4 5 123 }t
-t{ 4 PWH5 -> 4 5 123 }t
-t{ 5 PWH5 -> 5 123 }t
-
-
-TESTING POSTPONE [
-: POSTPONE-[
- POSTPONE [ ;
-
-t{ HERE POSTPONE-[ -> HERE }t
-
-TESTING POSTPONE [']
-: POSTPONE-[']
- POSTPONE ['] ;
-
-t{ : PTICK1 123 ; -> }t
-t{ : PTICK2 [ POSTPONE-['] PTICK1 ] ; IMMEDIATE -> }t
-t{ PTICK2 EXECUTE -> 123 }t
-
-TESTING POSTPONE [CHAR]
-: POSTPONE-[CHAR]
- POSTPONE [CHAR] ;
-
-t{ : PCHAR1 [ POSTPONE-[CHAR] X ] ; -> }t
-t{ : PCHAR2 [ POSTPONE-[CHAR] HELLO ] ; -> }t
-t{ PCHAR1 -> 58 }t
-t{ PCHAR2 -> 48 }t
-
diff --git a/amforth-6.5/common/lib/forth2012/tester/searchordertest.fth b/amforth-6.5/common/lib/forth2012/tester/searchordertest.fth
deleted file mode 100644
index 79f9de9..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/searchordertest.fth
+++ /dev/null
@@ -1,178 +0,0 @@
-\ To test the ANS Forth search-order word set and search order extensions
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.5 1 April 2012 Tests placed in the public domain.
-\ 0.4 6 March 2009 { and } replaced with T{ and }T
-\ 0.3 20 April 2007 ANS Forth words changed to upper case
-\ 0.2 30 Oct 2006 updated following GForth tests to get
-\ initial search order into a known state
-\ 0.1 Oct 2006 First version released
-
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\ and requires those files to have been loaded
-
-\ Words tested in this file are:
-\ FORTH-WORDLIST GET-ORDER SET-ORDER ALSO ONLY FORTH GET-CURRENT
-\ SET-CURRENT DEFINITIONS PREVIOUS SEARCH-WORDLIST WORDLIST FIND
-\ Words not fully tested:
-\ ORDER only tests that it executes, display is implementation
-\ dependent and should be visually inspected
-
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ - that ONLY FORTH DEFINITIONS will work at the start of the file
-\ to ensure the search order is in a known state
-\ ------------------------------------------------------------------------------
-
-ONLY FORTH DEFINITIONS
-
-TESTING Search-order word set
-
-DECIMAL
-
-VARIABLE wid1 VARIABLE wid2
-
-: save-orderlist ( widn ... wid1 n -> ) DUP , 0 ?DO , LOOP ;
-
-\ ------------------------------------------------------------------------------
-TESTING FORTH-WORDLIST GET-ORDER SET-ORDER
-
-T{ FORTH-WORDLIST wid1 ! -> }T
-
-CREATE order-list
-
-T{ GET-ORDER save-orderlist -> }T
-
-: get-orderlist ( -- widn ... wid1 n )
- order-list DUP @ CELLS ( -- ad n )
- OVER + ( -- ad ad' )
- ?DO I @ -1 CELLS +LOOP ( -- )
-;
-
-T{ GET-ORDER OVER -> GET-ORDER wid1 @ }T \ Forth wordlist at top
-T{ GET-ORDER SET-ORDER -> }T \ Effectively noop
-T{ GET-ORDER -> get-orderlist }T \ Check nothing changed
-T{ get-orderlist DROP get-orderlist 2* SET-ORDER -> }T
-T{ GET-ORDER -> get-orderlist DROP get-orderlist 2* }T
-T{ get-orderlist SET-ORDER GET-ORDER -> get-orderlist }T
-
-\ ------------------------------------------------------------------------------
-TESTING ALSO ONLY FORTH
-
-T{ ALSO GET-ORDER -> get-orderlist OVER SWAP 1+ }T
-T{ ONLY FORTH GET-ORDER -> get-orderlist }T \ See assumptions above
-
-\ ------------------------------------------------------------------------------
-TESTING GET-CURRENT SET-CURRENT WORDLIST (simple)
-
-T{ GET-CURRENT -> wid1 @ }T \ See assumptions above
-T{ WORDLIST wid2 ! -> }T
-T{ wid2 @ SET-CURRENT -> }T
-T{ GET-CURRENT -> wid2 @ }T
-T{ wid1 @ SET-CURRENT -> }T
-
-\ ------------------------------------------------------------------------------
-TESTING minimum search order list contains FORTH-WORDLIST and SET-ORDER
-
-: so1 SET-ORDER ; \ In case it is unavailable in the forth wordlist
-
-T{ ONLY FORTH-WORDLIST 1 SET-ORDER get-orderlist so1 -> }T
-T{ GET-ORDER -> get-orderlist }T
-
-\ ------------------------------------------------------------------------------
-TESTING GET-ORDER SET-ORDER with 0 and -1 number of wids argument
-
-: so2a GET-ORDER get-orderlist SET-ORDER ; \ To recover search order
-: so2 0 SET-ORDER so2a ;
-
-T{ so2 -> 0 }T \ 0 set-order leaves an empty search order
-
-: so3 -1 SET-ORDER so2a ;
-: so4 ONLY so2a ;
-
-T{ so3 -> so4 }T \ -1 SET-ORDER = ONLY
-
-\ ------------------------------------------------------------------------------
-TESTING DEFINITIONS PREVIOUS
-
-T{ ONLY FORTH DEFINITIONS -> }T
-T{ GET-CURRENT -> FORTH-WORDLIST }T
-T{ GET-ORDER wid2 @ SWAP 1+ SET-ORDER DEFINITIONS GET-CURRENT -> wid2 @ }T
-T{ GET-ORDER -> get-orderlist wid2 @ SWAP 1+ }T
-T{ PREVIOUS GET-ORDER -> get-orderlist }T
-T{ DEFINITIONS GET-CURRENT -> FORTH-WORDLIST }T
-
-\ ------------------------------------------------------------------------------
-TESTING SEARCH-WORDLIST WORDLIST FIND
-
-ONLY FORTH DEFINITIONS
-VARIABLE xt ' DUP xt !
-VARIABLE xti ' .( xti ! \ Immediate word
-
-T{ S" DUP" wid1 @ SEARCH-WORDLIST -> xt @ -1 }T
-T{ S" .(" wid1 @ SEARCH-WORDLIST -> xti @ 1 }T
-T{ S" DUP" wid2 @ SEARCH-WORDLIST -> 0 }T
-
-: c"dup" C" DUP" ;
-: c".(" C" .(" ;
-: c"x" C" unknown word" ;
-
-T{ c"dup" FIND -> xt @ -1 }T
-T{ c".(" FIND -> xti @ 1 }T
-T{ c"x" FIND -> c"x" 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING new definitions are put into the correct wordlist
-
-: alsowid2 ALSO GET-ORDER wid2 @ ROT DROP SWAP SET-ORDER ;
-alsowid2
-: w1 1234 ;
-DEFINITIONS
-: w1 -9876 ; IMMEDIATE
-
-ONLY FORTH
-T{ w1 -> 1234 }T
-DEFINITIONS
-T{ w1 -> 1234 }T
-alsowid2
-T{ w1 -> -9876 }T
-DEFINITIONS
-T{ w1 -> -9876 }T
-
-ONLY FORTH DEFINITIONS
-
-: so5 DUP IF SWAP EXECUTE THEN ;
-
-T{ S" w1" wid1 @ SEARCH-WORDLIST so5 -> -1 1234 }T
-T{ S" w1" wid2 @ SEARCH-WORDLIST so5 -> 1 -9876 }T
-
-: c"w1" C" w1" ;
-T{ alsowid2 c"w1" FIND so5 -> 1 -9876 }T
-T{ PREVIOUS c"w1" FIND so5 -> -1 1234 }T
-
-\ ------------------------------------------------------------------------------
-TESTING ORDER \ Should display search order and compilation wordlist
-
-CR .( ONLY FORTH DEFINITIONS search order and compilation list) CR
-T{ ONLY FORTH DEFINITIONS ORDER -> }T
-
-CR .( Plus another unnamed wordlist at the head of the search order) CR
-T{ alsowid2 DEFINITIONS ORDER -> }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of Search Order word tests) CR
-
-ONLY FORTH DEFINITIONS \ Leave search order in the standard state
diff --git a/amforth-6.5/common/lib/forth2012/tester/searchordertest.txt b/amforth-6.5/common/lib/forth2012/tester/searchordertest.txt
deleted file mode 100644
index 9018a5d..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/searchordertest.txt
+++ /dev/null
@@ -1,184 +0,0 @@
-\ To test the ANS Forth search-order word set and search order extensions
-
-\ Copyright (C) Gerry Jackson 2006
-
-\ This program is free software; you can redistribute it and/or
-\ modify it any way.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ --------------------------------------------------------------------
-\ Version 0.1 Oct 2006 First version released
-
-\ --------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\ and requires those files to have been loaded
-
-\ Words tested in this file are:
-\ forth-wordlist get-order set-order also only forth get-current
-\ set-current definitions previous search-wordlist wordlist find
-\ Words not fully tested:
-\ order only tests that it executes, display is implementation
-\ dependent
-
-\ --------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - running on a case insensitive system. Strictly speaking ANS
-\ Forth words should be in upper case only, this file is mostly
-\ lower case
-\ - the forth wordlist is at the head of the search order and is
-\ also the compilation wordlist
-\ - tester.fr has been loaded prior to this file
-\ --------------------------------------------------------------------
-
-Testing Search-order word set
-
-decimal
-
-variable wid1 variable wid2
-
-: save-orderlist ( widn ... wid1 n -> ) dup , 0 ?do , loop ;
-
-\ --------------------------------------------------------------------
-
-Testing forth-wordlist get-order set-order
-
-{ forth-wordlist wid1 ! -> }
-
-create order-list
-
-{ get-order save-orderlist -> }
-
-: get-orderlist ( -- widn ... wid1 n )
- order-list dup @ cells ( -- ad n )
- over + ( -- ad ad' )
- ?do i @ -1 cells +loop ( -- )
-;
-
-{ get-order over -> get-order wid1 @ } \ Forth wordlist at top
-{ get-order set-order -> } \ Effectively noop
-{ get-order -> get-orderlist } \ Check nothing changed
-{ get-orderlist drop get-orderList 2* set-order -> }
-{ get-order -> get-orderlist drop get-orderList 2* }
-{ get-orderlist set-order get-order -> get-orderlist }
-
-\ --------------------------------------------------------------------
-
-Testing also only forth
-
-{ also get-order -> get-orderlist over swap 1+ }
-{ only forth get-order -> get-orderlist } \ See assumptions above
-
-\ --------------------------------------------------------------------
-
-Testing get-current set-current wordlist (simple)
-
-{ get-current -> wid1 @ } \ See assumptions above
-{ wordlist wid2 ! -> }
-{ wid2 @ set-current -> }
-{ get-current -> wid2 @ }
-{ wid1 @ set-current
-
-\ --------------------------------------------------------------------
-
-Testing minimum search order list contains forth-wordlist and set-order
-
-: so1 set-order ; \ In case it is unavailable in the forth wordlist
-
-{ only forth-wordlist 1 set-order get-orderlist so1 -> }
-{ get-order -> get-orderlist }
-
-\ --------------------------------------------------------------------
-
-Testing get-order set-order with 0 and -1 number of wids argument
-
-: so2a get-order get-orderlist set-order ; \ To recover search order
-: so2 0 set-order so2a ;
-
-{ so2 -> 0 } \ 0 set-order leaves an empty search order
-
-: so3 -1 set-order so2a ;
-: so4 only so2a ;
-
-{ so3 -> so4 } \ -1 set-order = only
-
-\ --------------------------------------------------------------------
-
-Testing definitions previous
-
-{ only forth definitions -> }
-{ get-current -> forth-wordlist }
-{ get-order wid2 @ swap 1+ set-order definitions get-current -> wid2 @ }
-{ get-order -> get-orderlist wid2 @ swap 1+ }
-{ previous get-order -> get-orderlist }
-{ definitions get-current -> forth-wordlist }
-
-\ --------------------------------------------------------------------
-
-Testing search-wordlist wordlist find
-
-only forth definitions
-variable xt ' dup xt !
-variable xti ' .( xti ! \ Immediate word
-
-{ s" dup" wid1 @ search-wordlist -> xt @ -1 }
-{ s" .(" wid1 @ search-wordlist -> xti @ 1 }
-{ s" dup" wid2 @ search-wordlist -> 0 }
-
-: c"dup" c" dup" ;
-: c".(" c" .(" ;
-: c"x" c" unknown word" ;
-
-{ c"dup" find -> xt @ -1 }
-{ c".(" find -> xti @ 1 }
-{ c"x" find -> c"x" 0 }
-
-\ --------------------------------------------------------------------
-
-Testing new definitions are put into the correct wordlist
-
-: alsowid2 also get-order wid2 @ rot drop swap set-order ;
-alsowid2
-: w1 1234 ;
-definitions
-: w1 -9876 ; immediate
-
-only forth
-{ w1 -> 1234 }
-definitions
-{ w1 -> 1234 }
-alsowid2
-{ w1 -> -9876 }
-definitions
-{ w1 -> -9876 }
-
-only forth definitions
-
-: so5 dup if swap execute then ;
-
-{ s" w1" wid1 @ search-wordlist so5 -> -1 1234 }
-{ s" w1" wid2 @ search-wordlist so5 -> 1 -9876 }
-
-: c"w1" c" w1" ;
-{ alsowid2 c"w1" find so5 -> 1 -9876 }
-{ previous c"w1" find so5 -> -1 1234 }
-
-\ --------------------------------------------------------------------
-
-Testing order \ Should display search order and compilation wordlist
-
-cr .( ONLY FORTH DEFINITIONS search order and compilation list) cr
-{ only forth definitions order -> }
-
-cr .( Plus another unnamed wordlist at the head of the search order) cr
-{ alsowid2 definitions order -> }
-
-\ --------------------------------------------------------------------
-
-cr .( Tests on Search Order words completed successfully) cr
-
-only forth definitions \ Leave search order in the standard state
diff --git a/amforth-6.5/common/lib/forth2012/tester/stringtest.fth b/amforth-6.5/common/lib/forth2012/tester/stringtest.fth
deleted file mode 100644
index 95e2bfe..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/stringtest.fth
+++ /dev/null
@@ -1,161 +0,0 @@
-\ To test the ANS Forth String word set
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.6 1 April 2012 Tests placed in the public domain.
-\ 0.5 29 April 2010 Added tests for SEARCH and COMPARE with
-\ all strings zero length (suggested by Krishna Myneni).
-\ SLITERAL test amended in line with comp.lang.forth
-\ discussion
-\ 0.4 30 November 2009 <true> and <false> replaced with TRUE
-\ and FALSE
-\ 0.3 6 March 2009 { and } replaced with T{ and }T
-\ 0.2 20 April 2007 ANS Forth words changed to upper case
-\ 0.1 Oct 2006 First version released
-
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program for the core word set
-\ and requires those files to have been loaded
-
-\ Words tested in this file are:
-\ -TRAILING /STRING BLANK CMOVE CMOVE> COMPARE SEARCH SLITERAL
-\
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ - COMPARE is case sensitive
-\ ------------------------------------------------------------------------------
-
-TESTING String word set
-
-DECIMAL
-
-T{ : s1 S" abcdefghijklmnopqrstuvwxyz" ; -> }T
-T{ : s2 S" abc" ; -> }T
-T{ : s3 S" jklmn" ; -> }T
-T{ : s4 S" z" ; -> }T
-T{ : s5 S" mnoq" ; -> }T
-T{ : s6 S" 12345" ; -> }T
-T{ : s7 S" " ; -> }T
-T{ : s8 S" abc " ; -> }T
-T{ : s9 S" " ; -> }T
-T{ : s10 S" a " ; -> }T
-
-\ ------------------------------------------------------------------------------
-TESTING -TRAILING
-
-T{ s1 -TRAILING -> s1 }T
-T{ s8 -TRAILING -> s8 2 - }T
-T{ s7 -TRAILING -> s7 }T
-T{ s9 -TRAILING -> s9 DROP 0 }T
-T{ s10 -TRAILING -> s10 1- }T
-
-\ ------------------------------------------------------------------------------
-TESTING /STRING
-
-T{ s1 5 /STRING -> s1 SWAP 5 + SWAP 5 - }T
-T{ s1 10 /STRING -4 /STRING -> s1 6 /STRING }T
-T{ s1 0 /STRING -> s1 }T
-
-\ ------------------------------------------------------------------------------
-TESTING SEARCH
-
-T{ s1 s2 SEARCH -> s1 TRUE }T
-T{ s1 s3 SEARCH -> s1 9 /STRING TRUE }T
-T{ s1 s4 SEARCH -> s1 25 /STRING TRUE }T
-T{ s1 s5 SEARCH -> s1 FALSE }T
-T{ s1 s6 SEARCH -> s1 FALSE }T
-T{ s1 s7 SEARCH -> s1 TRUE }T
-T{ s7 PAD 0 SEARCH -> s7 TRUE }T
-
-\ ------------------------------------------------------------------------------
-TESTING COMPARE
-
-T{ s1 s1 COMPARE -> 0 }T
-T{ s1 PAD SWAP CMOVE -> }T
-T{ s1 PAD OVER COMPARE -> 0 }T
-T{ s1 PAD 6 COMPARE -> 1 }T
-T{ PAD 10 s1 COMPARE -> -1 }T
-T{ s1 PAD 0 COMPARE -> 1 }T
-T{ PAD 0 s1 COMPARE -> -1 }T
-T{ s1 s6 COMPARE -> 1 }T
-T{ s6 s1 COMPARE -> -1 }T
-T{ s7 PAD 0 COMPARE -> 0 }T
-
-: "abdde" S" abdde" ;
-: "abbde" S" abbde" ;
-: "abcdf" S" abcdf" ;
-: "abcdee" S" abcdee" ;
-
-T{ s1 "abdde" COMPARE -> -1 }T
-T{ s1 "abbde" COMPARE -> 1 }T
-T{ s1 "abcdf" COMPARE -> -1 }T
-T{ s1 "abcdee" COMPARE -> 1 }T
-
-: s11 S" 0abc" ;
-: s12 S" 0aBc" ;
-
-T{ s11 s12 COMPARE -> 1 }T
-T{ s12 s11 COMPARE -> -1 }T
-
-\ ------------------------------------------------------------------------------
-TESTING CMOVE and CMOVE>
-
-PAD 30 CHARS 0 FILL
-T{ s1 PAD SWAP CMOVE -> }T
-T{ s1 PAD s1 SWAP DROP COMPARE -> 0 }T
-T{ s6 PAD 10 CHARS + SWAP CMOVE -> }T
-T{ S" abcdefghij12345pqrstuvwxyz" PAD s1 SWAP DROP COMPARE -> 0 }T
-T{ PAD 15 CHARS + PAD CHAR+ 6 CMOVE -> }T
-T{ S" apqrstuhij12345pqrstuvwxyz" PAD 26 COMPARE -> 0 }T
-T{ PAD PAD 3 CHARS + 7 CMOVE -> }T
-T{ S" apqapqapqa12345pqrstuvwxyz" PAD 26 COMPARE -> 0 }T
-T{ PAD PAD CHAR+ 10 CMOVE -> }T
-T{ S" aaaaaaaaaaa2345pqrstuvwxyz" PAD 26 COMPARE -> 0 }T
-T{ s7 PAD 14 CHARS + SWAP CMOVE -> }T
-T{ S" aaaaaaaaaaa2345pqrstuvwxyz" PAD 26 COMPARE -> 0 }T
-
-PAD 30 CHARS 0 FILL
-
-T{ s1 PAD SWAP CMOVE> -> }T
-T{ s1 PAD s1 SWAP DROP COMPARE -> 0 }T
-T{ s6 PAD 10 CHARS + SWAP CMOVE> -> }T
-T{ S" abcdefghij12345pqrstuvwxyz" PAD s1 SWAP DROP COMPARE -> 0 }T
-T{ PAD 15 CHARS + PAD CHAR+ 6 CMOVE> -> }T
-T{ S" apqrstuhij12345pqrstuvwxyz" PAD 26 COMPARE -> 0 }T
-T{ PAD 13 CHARS + PAD 10 CHARS + 7 CMOVE> -> }T
-T{ S" apqrstuhijtrstrstrstuvwxyz" PAD 26 COMPARE -> 0 }T
-T{ PAD 12 CHARS + PAD 11 CHARS + 10 CMOVE> -> }T
-T{ S" apqrstuhijtvvvvvvvvvvvwxyz" PAD 26 COMPARE -> 0 }T
-T{ s7 PAD 14 CHARS + SWAP CMOVE> -> }T
-T{ S" apqrstuhijtvvvvvvvvvvvwxyz" PAD 26 COMPARE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING BLANK
-
-: s13 S" aaaaa a" ; \ Don't move this down or might corrupt PAD
-
-T{ PAD 25 CHAR a FILL -> }T
-T{ PAD 5 CHARS + 6 BLANK -> }T
-T{ PAD 12 s13 COMPARE -> 0 }T
-
-\ ------------------------------------------------------------------------------
-TESTING SLITERAL
-
-T{ HERE DUP s1 DUP ALLOT ROT SWAP CMOVE s1 SWAP DROP 2CONSTANT s1a -> }T
-T{ : s14 [ s1a ] SLITERAL ; -> }T
-T{ s1a s14 COMPARE -> 0 }T
-T{ s1a DROP s14 DROP = -> FALSE }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of String word tests) CR
diff --git a/amforth-6.5/common/lib/forth2012/tester/tester-amforth.frt b/amforth-6.5/common/lib/forth2012/tester/tester-amforth.frt
deleted file mode 100644
index 01d3ca5..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/tester-amforth.frt
+++ /dev/null
@@ -1,66 +0,0 @@
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ modified for amforth by Matthias Trute 2007
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-variable VERBOSE
- 0 VERBOSE !
-
-variable ACTUAL-DEPTH \ STACK RECORD
-variable START-DEPTH
-
-: EMPTY-STACK \ ( ... -- ) EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
- depth START-DEPTH @ < if
- depth START-DEPTH @ swap do 0 loop
- then
- depth START-DEPTH @ > if
- depth START-DEPTH @ do drop loop
- then
-;
-
-: ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
- \ THE LINE THAT HAD THE ERROR.
- itype source type cr \ DISPLAY LINE CORRESPONDING TO ERROR
- EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-;
-
-variable ACTUAL-DEPTH \ STACK RECORD
-variable ACTUAL-RESULTS 20 cells allot \ reserve space in RAM
-
-: t{ \ ( -- ) SYNTACTIC SUGAR.
- depth START-DEPTH !
-;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- depth dup ACTUAL-DEPTH ! \ RECORD DEPTH
- START-DEPTH @ > if \ IF THERE IS SOMETHING ON STACK
- depth START-DEPTH @ - 0 do ACTUAL-RESULTS i cells + ! loop \ SAVE THEM
- then
-;
-
-: }t \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- depth ACTUAL-DEPTH @ = if \ IF DEPTHS MATCH
- depth START-DEPTH @ > if \ IF THERE IS SOMETHING ON THE STACK
- depth START-DEPTH @ - 0 do \ FOR EACH STACK ITEM
- ACTUAL-RESULTS i cells + @ \ COMPARE ACTUAL WITH EXPECTED
- <> if s" INCORRECT RESULT: " ERROR leave then
- loop
- then
- else \ DEPTH MISMATCH
- s" WRONG NUMBER OF RESULTS: " ERROR
- then
-;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- source VERBOSE @
- if dup >r type cr r> >in !
- else >in ! drop
- then ;
-
diff --git a/amforth-6.5/common/lib/forth2012/tester/toolstest.fth b/amforth-6.5/common/lib/forth2012/tester/toolstest.fth
deleted file mode 100644
index a35450b..0000000
--- a/amforth-6.5/common/lib/forth2012/tester/toolstest.fth
+++ /dev/null
@@ -1,172 +0,0 @@
-\ To test some of the ANS Forth Programming Tools and extension wordset
-
-\ This program was written by Gerry Jackson in 2006, with contributions from
-\ others where indicated, and is in the public domain - it can be distributed
-\ and/or modified in any way but please retain this notice.
-
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-\ The tests are not claimed to be comprehensive or correct
-
-\ ------------------------------------------------------------------------------
-\ Version 0.6 1 April 2012 Tests placed in the public domain.
-\ Further tests on [IF] [ELSE] [THEN]
-\ 0.5 30 November 2009 <true> and <false> replaced with TRUE and FALSE
-\ 0.4 6 March 2009 ENDIF changed to THEN. {...} changed to T{...}T
-\ 0.3 20 April 2007 ANS Forth words changed to upper case
-\ 0.2 30 Oct 2006 updated following GForth test to avoid
-\ changing stack depth during a colon definition
-\ 0.1 Oct 2006 First version released
-
-\ ------------------------------------------------------------------------------
-\ The tests are based on John Hayes test program
-
-\ Words tested in this file are:
-\ AHEAD [IF] [ELSE] [THEN] CS-PICK CS-ROLL
-\
-
-\ Words not tested:
-\ .S ? DUMP SEE WORDS
-\ ;CODE ASSEMBLER BYE CODE EDITOR FORGET STATE
-\ ------------------------------------------------------------------------------
-\ Assumptions and dependencies:
-\ - tester.fr or ttester.fs has been loaded prior to this file
-\ ------------------------------------------------------------------------------
-
-DECIMAL
-
-\ ------------------------------------------------------------------------------
-TESTING AHEAD
-
-T{ : pt1 AHEAD 1111 2222 THEN 3333 ; -> }T
-T{ pt1 -> 3333 }T
-
-\ ------------------------------------------------------------------------------
-TESTING [IF] [ELSE] [THEN]
-
-T{ TRUE [IF] 111 [ELSE] 222 [THEN] -> 111 }T
-T{ FALSE [IF] 111 [ELSE] 222 [THEN] -> 222 }T
-
-T{ TRUE [IF] 1 \ Code spread over more than 1 line
- 2
- [ELSE]
- 3
- 4
- [THEN] -> 1 2 }T
-T{ FALSE [IF]
- 1 2
- [ELSE]
- 3 4
- [THEN] -> 3 4 }T
-
-T{ TRUE [IF] 1 TRUE [IF] 2 [ELSE] 3 [THEN] [ELSE] 4 [THEN] -> 1 2 }T
-T{ FALSE [IF] 1 TRUE [IF] 2 [ELSE] 3 [THEN] [ELSE] 4 [THEN] -> 4 }T
-T{ TRUE [IF] 1 FALSE [IF] 2 [ELSE] 3 [THEN] [ELSE] 4 [THEN] -> 1 3 }T
-T{ FALSE [IF] 1 FALSE [IF] 2 [ELSE] 3 [THEN] [ELSE] 4 [THEN] -> 4 }T
-
-\ ------------------------------------------------------------------------------
-TESTING immediacy of [IF] [ELSE] [THEN]
-
-T{ : pt2 [ 0 ] [IF] 1111 [ELSE] 2222 [THEN] ; pt2 -> 2222 }T
-T{ : pt3 [ -1 ] [IF] 3333 [ELSE] 4444 [THEN] ; pt3 -> 3333 }T
-: pt9 bl WORD FIND ;
-T{ pt9 [IF] NIP -> 1 }T
-T{ pt9 [ELSE] NIP -> 1 }T
-T{ pt9 [THEN] NIP -> 1 }T
-
-\ -----------------------------------------------------------------------------
-TESTING [IF] and [ELSE] carry out a text scan by parsing and discarding words
-\ so that an [ELSE] or [THEN] in a comment or string is recognised
-
-: pt10 REFILL DROP REFILL DROP ;
-
-T{ 0 [IF] \ Words ignored up to [ELSE] 2
- [THEN] -> 2 }T
-T{ -1 [IF] 2 [ELSE] 3 s" [THEN] 4 pt10 ignored to end of line"
- [THEN] \ Precaution in case [THEN] in string isn't recognised
- -> 2 4 }T
-
-\ ------------------------------------------------------------------------------
-TESTING CS-PICK and CS-ROLL
-
-\ Test pt5 based on example in ANS document p 176.
-
-: ?repeat
- 0 CS-PICK POSTPONE UNTIL
-; IMMEDIATE
-
-VARIABLE pt4
-
-T{ : pt5 ( n1 -- )
- pt4 !
- BEGIN
- -1 pt4 +!
- pt4 @ 4 > 0= ?repeat \ Back to BEGIN if false
- 111
- pt4 @ 3 > 0= ?repeat
- 222
- pt4 @ 2 > 0= ?repeat
- 333
- pt4 @ 1 =
- UNTIL
-; -> }T
-
-T{ 6 pt5 -> 111 111 222 111 222 333 111 222 333 }T
-
-
-T{ : ?DONE POSTPONE IF 1 CS-ROLL ; IMMEDIATE -> }T \ Same as WHILE
-T{ : pt6
- >R
- BEGIN
- R@
- ?DONE
- R@
- R> 1- >R
- REPEAT
- R> DROP
- ; -> }T
-
-T{ 5 pt6 -> 5 4 3 2 1 }T
-
-: mix_up 2 CS-ROLL ; IMMEDIATE \ cs-rot
-
-: pt7 ( f3 f2 f1 -- ? )
- IF 1111 ROT ROT ( -- 1111 f3 f2 ) ( cs: -- orig1 )
- IF 2222 SWAP ( -- 1111 2222 f3 ) ( cs: -- orig1 orig2 )
- IF ( cs: -- orig1 orig2 orig3 )
- 3333 mix_up ( -- 1111 2222 3333 ) ( cs: -- orig2 orig3 orig1 )
- THEN ( cs: -- orig2 orig3 )
- 4444 \ Hence failure of first IF comes here and falls through
- THEN ( cs: -- orig2 )
- 5555 \ Failure of 3rd IF comes here
- THEN ( cs: -- )
- 6666 \ Failure of 2nd IF comes here
-;
-
-T{ -1 -1 -1 pt7 -> 1111 2222 3333 4444 5555 6666 }T
-T{ 0 -1 -1 pt7 -> 1111 2222 5555 6666 }T
-T{ 0 0 -1 pt7 -> 1111 0 6666 }T
-T{ 0 0 0 pt7 -> 0 0 4444 5555 6666 }T
-
-: [1cs-roll] 1 CS-ROLL ; IMMEDIATE
-
-T{ : pt8
- >R
- AHEAD 111
- BEGIN 222
- [1cs-roll]
- THEN
- 333
- R> 1- >R
- R@ 0<
- UNTIL
- R> DROP
- ; -> }T
-
-T{ 1 pt8 -> 333 222 333 }T
-
-\ ------------------------------------------------------------------------------
-
-CR .( End of Programming Tools word tests) CR
diff --git a/amforth-6.5/common/lib/forth2012/tools.frt b/amforth-6.5/common/lib/forth2012/tools.frt
deleted file mode 100644
index fdc8f08..0000000
--- a/amforth-6.5/common/lib/forth2012/tools.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-\ 'tools.frt' generated automatically, do not edit
-#include defined.frt
-#include dot-s.frt
-#include dumper.frt
-#include dump.frt
-#include question.frt
diff --git a/amforth-6.5/common/lib/forth2012/tools/bracket-conditional.frt b/amforth-6.5/common/lib/forth2012/tools/bracket-conditional.frt
deleted file mode 100644
index 5df8c28..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/bracket-conditional.frt
+++ /dev/null
@@ -1,20 +0,0 @@
-
-: [else] \ ( -- )
- begin
- begin
- parse-name
- dup
- while
- 2dup s" [else]" icompare
- ?dup 0=
- if exit then
- repeat 2drop
- refill 0=
- until
-; immediate
-
-: [if] \ ( flag -- )
- 0= if postpone [else] then
-; immediate
-
-: [then] ; immediate
diff --git a/amforth-6.5/common/lib/forth2012/tools/defined.frt b/amforth-6.5/common/lib/forth2012/tools/defined.frt
deleted file mode 100644
index cef7e78..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/defined.frt
+++ /dev/null
@@ -1,10 +0,0 @@
-
-\ http://www.forth200x.org/defined.html
-\ adapted to non-counted strings
-
-: [defined] parse-name find-name dup if swap drop then ; immediate
-: [undefined] postpone [defined] 0= ; immediate
-
-\ ... and without postpone (Enoch, Feb-2013)
-\ : [defined] parse-name find-name if drop -1 else 0 then ; immediate
-\ : [undefined] parse-name find-name if drop 0 else -1 then ; immediate
diff --git a/amforth-6.5/common/lib/forth2012/tools/dot-s.frt b/amforth-6.5/common/lib/forth2012/tools/dot-s.frt
deleted file mode 100644
index 1c86dd8..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/dot-s.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-\ a .s with the TOS printed *last*
-: .s depth 0 ?do depth i - 1- pick . loop ; \ No newline at end of file
diff --git a/amforth-6.5/common/lib/forth2012/tools/dump.frt b/amforth-6.5/common/lib/forth2012/tools/dump.frt
deleted file mode 100644
index fba47d7..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/dump.frt
+++ /dev/null
@@ -1,50 +0,0 @@
-
-\ dump memories
-\ usage is
-\ addr len [ei]dump
-\ output looks like (for word oriented memories)
-\ (ATmega32)> 0 10 edump
-\ 0000 - FFFF D9FF 17D9 2117 0121 5201 0052 DE00 .......!!..RR...
-\ 0008 - 0CDE 6F0C 3B6F 193B 0019 3200 0B32 140B ...oo;;....22...
-
-\ RAM dump is byte oriented:
-\ 00B0 BD 3E 55 33 5B E6 C4 9B 4A 63 72 20 63 72 20 24 .>U3[...Jcr.cr.$
-\ 00C0 62 30 20 32 30 20 64 75 6D 70 20 63 72 20 63 72 b0.20.dump.cr.cr
-
-hex
-
-: ?ascii ( char -- printable-char )
- dup 20 < if drop 2e
- else dup 7e >
- if drop 2e then
- then ;
-
-: .2hex s>d <# # # #> type ;
-: .4hex s>d <# # # # # #> type ;
-
-: dump ( addr count -- )
- cr 0
- do dup .4hex space
- 10 0 do dup i + c@ .2hex space loop 2 spaces
- 10 0 do dup i + c@ ?ascii emit loop
- 10 + cr
- 10 +loop drop ;
-
-: split ( n - c c ) dup $ff and swap $ff00 and $100 / $ff and swap ;
-
-: idump ( addr count -- )
- cr 0
- do dup .4hex space [char] - emit space
- 8 0 do dup i + @i .4hex space loop 2 spaces
- 8 0 do dup i + @i split ?ascii emit ?ascii emit loop
- 8 + cr
- 8 +loop drop ;
-
-: edump ( addr count -- )
- cr 0
- do dup .4hex space [char] - emit space
- 08 0 do dup i cells + @e .4hex space loop 2 spaces
- 08 0 do dup i cells + @e split ?ascii emit ?ascii emit loop
- 10 + cr
- 10 +loop drop ;
-
diff --git a/amforth-6.5/common/lib/forth2012/tools/dumper.frt b/amforth-6.5/common/lib/forth2012/tools/dumper.frt
deleted file mode 100644
index fdb1c09..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/dumper.frt
+++ /dev/null
@@ -1,57 +0,0 @@
-\ dump cells from addr upward for len. mk03.10.2008
-
-\ We want xdump ( addr len -- ) doing output like this:
-\ xxx0 cccc cccc cccc cccc cccc cccc cccc cccc
-\ xxx8 cccc cccc cccc cccc cccc cccc cccc cccc
-\ ...
-
-\ That is, we alway print 8 cells. And want to see them in segments of 8 cells,
-\ all starting at xxx0 or xxx8 addresses.
-\ So we have to trimm addr and len first:
-\ Clear lower 3 bits of addr, then set lower 3 bits of len
-\ The rest shoud be obvious.
-
-hex
-
-\ helper word
-\ print a number in a field with 0 filled
-: u.r ( u w -- )
- >r 0 \ see u.
- <#
- r> 0 ?do # loop
- #>
- type
-;
-
-( item -- )
-: .item 4 u.r space ;
-
-( addr -- )
-: i? @i .item ;
-: e? @e .item ;
-: ? @ .item ;
-
-( addr n -- addr+n )
-: .icells 0 do dup i? 1+ loop ; \ flash
-: .ecells 0 do dup e? cell+ loop ; \ eeprom
-: .rcells 0 do dup ? cell+ loop ; \ ram
-
-( addr -- )
-: .addr cr .item space ;
-
-( addr1 len1 -- addr2 len2 )
-: trimm swap fff8 and swap 7 or ;
-
-( adr len -- )
-: <dump postpone trimm postpone 0 postpone ?do postpone dup
- postpone .addr 8 postpone literal ; immediate
-
-( n -- )
-: dump> postpone +loop postpone drop ; immediate
-
-( addr len -- )
-: idump <dump .icells 8 dump> ;
-: edump <dump .ecells 10 dump> ;
-: dump <dump .rcells 10 dump> ;
-
-\ finis tested ok on amforth-2.9 05.10.2008 mk
diff --git a/amforth-6.5/common/lib/forth2012/tools/name2compile.frt b/amforth-6.5/common/lib/forth2012/tools/name2compile.frt
deleted file mode 100644
index fa50d2b..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/name2compile.frt
+++ /dev/null
@@ -1,9 +0,0 @@
-
-: name>compile ( nt -- xt1 xt2)
- dup nfa>cfa swap name>flags immediate? 1 = if
- ['] execute
- else
- ['] ,
- then
-;
-
diff --git a/amforth-6.5/common/lib/forth2012/tools/name2interpret.frt b/amforth-6.5/common/lib/forth2012/tools/name2interpret.frt
deleted file mode 100644
index 417980a..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/name2interpret.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-: name>interpret ( nt -- xt )
- nfa>cfa
-;
diff --git a/amforth-6.5/common/lib/forth2012/tools/question.frt b/amforth-6.5/common/lib/forth2012/tools/question.frt
deleted file mode 100644
index bd96e6c..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/question.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-\ displays the value of the given address with current base
-: ? ( addr -- )
- @ . ;
diff --git a/amforth-6.5/common/lib/forth2012/tools/see.frt b/amforth-6.5/common/lib/forth2012/tools/see.frt
deleted file mode 100644
index 5b5fda5..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/see.frt
+++ /dev/null
@@ -1,56 +0,0 @@
-hex
-\ decompiler
-
-\ marker --see--
-
-: .name ( nfa -- ) \ Namensfeld ausgeben
- icount $ff and dup 15 < if itype else drop drop ." :noname" then ;
-
-' exit constant exitxt \ Adresse des xt zu "exit" speichern
-' cr @i constant docolxt \ Adresse des Forth-DOCOLON VM Interpreter
-' cr 1+ @i constant litxt \ Adresse des xt zu "(lit)" speichern
-' bl @i constant dovarxt \ Adresse des xt zu "VARIABLE"
-' base @i constant douser \ Adresse des xt zu "USER"
-' emit @i constant dodefer \
-' s" 9 + @i constant doslit \ Adresse des xt zu "(slit)" speichern
-' if 2 + @i constant do0branch \ Adresse des xt zu "0branch" speichern
-' else 2 + @i constant dobranch \ Adresse des xt zu "branch" speichern
-' loop 2 + @i constant doloop \ Adresse des xt zu "(loop)" speichern
-' +loop 2 + @i constant do+loop \ Adresse des xt zu "(+loop)" speichern
-' do 2 + @i constant dodo \ Adresse des xt zu "(do)" speichern
-' ?do 2 + @i constant doqdo \ Adresse des xt zu "(?do)" speichern
-
-: see ( "<spaces>name" -- ) \ decompiler
- parse-name find-name if
- dup @i over - 1 = if dup >name .name space ." is a primitive" then
- dup @i dovarxt = if ." variable " 1+ dup @i . then
- dup @i douser = if ." user " 1+ dup @i . then
- dup @i dodefer = if ." defer " then
- dup @i docolxt = if
- [char] : emit space dup >name .name
- begin
- cr [char] [ emit space dup u. [char] ] emit space 2 spaces
- 1+ dup @i dup 4 .r space ( get next xt )
- dup litxt = if drop 1+ dup @i . 0 then
- dup exitxt = if drop [char] ; emit 1 then
- dup doslit = if
- drop [char] . emit [char] " emit space 1+ dup .name [char] " emit
- dup @i $FF and 2/ 2 + + 0
- then
- dup do0branch = if drop ." 0branch -> " 1+ dup @i 1- u. 0 then
- dup dobranch = if drop ." branch -> " 1+ dup @i 1- u. 0 then
- dup dodo = if drop ." do -> " 1+ dup @i 1- u. 0 then
- dup doqdo = if drop ." ?do -> " 1+ dup @i 1- u. 0 then
- dup doloop = if drop ." loop -> " 1+ dup @i 1- u. 0 then
- dup do+loop = if drop ." +loop -> " 1+ dup @i 1- u. 0 then
- dup 1 > if dup >name .name then
- 1 =
- until then
- drop
- else
- ." not found"
- then
-;
-
-\ Beispiel:
-\ ' see see
diff --git a/amforth-6.5/common/lib/forth2012/tools/synonym.frt b/amforth-6.5/common/lib/forth2012/tools/synonym.frt
deleted file mode 100644
index bb51c61..0000000
--- a/amforth-6.5/common/lib/forth2012/tools/synonym.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-\ SYNONYM <newname> <oldname>
-
-\
-\ does not check for reference to itself
-\
-: synonym
- create immediate ' ,
- does>
- @i state @ if , else execute then
-;
-
-\ : synonym : bl word find >r compile, postpone ; r> 0> IF immedate THEN ; \ No newline at end of file
diff --git a/amforth-6.5/common/lib/fsm.frt b/amforth-6.5/common/lib/fsm.frt
deleted file mode 100644
index 94af976..0000000
--- a/amforth-6.5/common/lib/fsm.frt
+++ /dev/null
@@ -1,67 +0,0 @@
-\ FSM routines, from a paper presented by J . Noble-----
-\ ---------------------------------------------------------
-\ you can find the paper at http://www.forth.org/literature/noble.html
-\ The fsm: word has been modified to correctly increment addresses by
-\ word, instead of byte. and to also use the i@ dictionary fetch word.
-\ Ver 1.1 fsm: now implements "The best FSM so far" (see paper). State
-\ is now a heap variable with it's address in the dictionary of the fsm.
-\ Written by Bernard Mentink
-
-marker _fsm_
-
-hex
-
-\ dummy nop word for readability
-: wide ;
-
-\ perform word that executes vector
-: perform
- @i execute ;
-
-\ Get 2 cells from dictionary space
-: 2@i
- dup 1+ @i swap @i ;
-
-\ comment if you have this word.
-: tuck swap over ;
-
-\ Allocate a RAM variable on the data space, init with x, and return RAM address
-: >ram ( x -- addr ) here 1 cells allot tuck ! ;
-
-
-\ This word creates FSM transition tables
-: fsm: ( width -- )
- create 0 >ram , , ] \ ram addr of state stored in dict,also width.
- does> ( col# adr -- )
- dup dup >r 2@i @ * 2* + ( -- col#+width*state )
- swap 2* 1+ 1+ + ( -- offset-to-action)
- dup >r ( -- offset-to-action)
- perform ( ? )
- r> 1+ ( -- offset-to-update)
- perform ( -- state')
- r> @i ! ; \ update state
-
-
-\ ......... some test code ..............
-\ un-comment the code lines to test state changes dependant on input supplied
-\ e.g 2 test_fsm, 0 test_fsm etc
-\ If you want the address of the state variable associated with your state
-\ machine, create the following word : mystate ['] test_fsm 1+ i@ ;
-
-\ : one ." one " ;
-\ : two ." two " ;
-\ : three ." three " ;
-\ : four ." four " ;
-\ : nop ." nop " ;
-
-\ 0 constant >0
-\ 1 constant >1
-\ 2 constant >2
-
-\ a test state-machine table
-\ 4 wide fsm: test_fsm
-\ input: | 0 | 1 | 2 | 3 |
-\ state: ---------------------------------------------
-\ ( 0 ) nop >0 one >1 one >1 two >2
-\ ( 1 ) four >1 one >1 nop >1 two >2
-\ ( 2 ) nop >2 two >2 nop >2 nop >2 ;
diff --git a/amforth-6.5/common/lib/hardware/1wire-crc8-test.frt b/amforth-6.5/common/lib/hardware/1wire-crc8-test.frt
deleted file mode 100644
index 1c628d6..0000000
--- a/amforth-6.5/common/lib/hardware/1wire-crc8-test.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ 2013-01-21 EW
-
-marker --start--
-
-include ewlib/1wire_crc8.fs
-
-\ testdata from Dallas Application Note 27
-\ A2 00 00 00 01 B8 1C 02
-\ ^^crc fam.code^^
-
-: run_test
- $A2 \ crc
- $00 $00 $00 $01 $B8 $1C $02 \ rom id
- #7 \ N
- .s
- 1w.crc8? if
- ." crc ok"
- else
- ." crc error"
- then
- cr
- $A2 1+ \ WRONG CRC!
- $00 $00 $00 $01 $B8 $1C $02 \ rom id
- #7 \ N
- .s
- 1w.crc8? if
- ." crc ok"
- else
- ." crc error"
- then
- cr
-
- \ reverse test
- $02 $1C $B8 $01 $00 $00 $00 $A2
- #7 .s
- 1w.crc8.rev? if
- ." crc ok"
- else
- ." crc error"
- then
- cr
-
- $02 $1C $B8 $01 $00 $00 $00 $A2 1+ \ WRONG CRC!
- #7 .s
- 1w.crc8.rev? if
- ." crc ok"
- else
- ." crc error"
- then
- cr
-
-
-;
-
diff --git a/amforth-6.5/common/lib/hardware/1wire-crc8.frt b/amforth-6.5/common/lib/hardware/1wire-crc8.frt
deleted file mode 100644
index e727ac7..0000000
--- a/amforth-6.5/common/lib/hardware/1wire-crc8.frt
+++ /dev/null
@@ -1,65 +0,0 @@
-\ 2013-01-21 EW ewlib/1wire_crc8.fs
-\ 1wire 8bit crc check, as used by ds18s20
-\ based on C code by Colin O'Flynn and M.Thomas, found at
-\ http://www.siwawi.arubi.uni-kl.de/avr_projects/tempsensor/ds18x20_demo_20110209.zip
-
-
-$18 constant 1w.crc8.polynom
-variable 1w.crc.shreg \ crc shift register
-variable 1w.crc.byte \ current input byte
-variable 1w.crc.fbit \ feedbackbit
-
-\ process 1 bit from input
-: ((1w.crc8))
- 1w.crc.shreg @ 1w.crc.byte @ xor $01 and
- dup 1w.crc.fbit !
- if \ fbit set
- 1w.crc.shreg @ 1w.crc8.polynom xor
- 1w.crc.shreg !
- then
- 1w.crc.shreg @ 1 rshift $7f and
- 1w.crc.shreg !
- 1w.crc.fbit @ if
- 1w.crc.shreg @ $80 or
- 1w.crc.shreg !
- then
-;
-\ process 1 byte of input
-: (1w.crc8) ( x -- )
- ( tos ) 1w.crc.byte !
- 8 0 do
- ((1w.crc8))
- 1w.crc.byte @ 1 rshift
- 1w.crc.byte !
- loop
-;
-
-\ process N bytes from stack, leave crc
-: 1w.crc8 ( xN-1 .. x0 N -- crc )
- 0 1w.crc.shreg !
- 0 1w.crc.byte !
- 0 1w.crc.fbit !
- 0 ?do
- (1w.crc8)
- loop
- 1w.crc.shreg @
-;
-\ process N bytes from stack, compare with crc, leave flag
-: 1w.crc8? ( crc xN-1 .. x0 N -- t/f )
- 1w.crc8 =
-;
-
-\ same as 1w.crc8, but process data in reverse (stack) order!
-: 1w.crc8.rev ( x0 .. xN-1 N -- crc )
- 0 1w.crc.shreg !
- 0 1w.crc.byte !
- 0 1w.crc.fbit !
- 1 over ?do i pick (1w.crc8) -1 +loop
- 0 ?do drop loop
- 1w.crc.shreg @
-;
-: 1w.crc8.rev? ( x0 .. xN-1 crc N -- t/f )
- swap >r \ save crc
- 1w.crc8.rev
- r> =
-;
diff --git a/amforth-6.5/common/lib/hardware/1wire-ds18s20.frt b/amforth-6.5/common/lib/hardware/1wire-ds18s20.frt
deleted file mode 100644
index 95be0c1..0000000
--- a/amforth-6.5/common/lib/hardware/1wire-ds18s20.frt
+++ /dev/null
@@ -1,32 +0,0 @@
-\ 2009-12-23 EW ewlib/1w_ds18s20.fs
-\ 2013-01-13 ported to amforth-5.0
-
-\ --- Fam.10 DS18S20 thermometer -----------------------------
-
-\ conversion + warten ist schon rum!
-: 1w.rd.T ( addr[8] -- x1=Tl x2=Th x3 .. x9=crc )
- 1w.reset drop \ fixme: if ... then
- \ device addressieren
- 1w.cmd.matchrom &9 >1w
- 1w.cmd.readdata &1 >1w
- &9 <1w
-;
-
-\ convert answer to physical units 1/100 C
-: ds18s20.decode ( x1 .. x9=crc -- T*100 ok )
- 7 0 do drop loop \ ignore crc
- 8 lshift + \ combine T_h T_l
- &100 &2 */ \ scale
- 0 \ ok, because we ignore crc
-;
-: ds18s20.decode.check ( x1 .. x9=crc -- T*100 ok=0 | error=1 )
- 7 pick >r 8 pick >r \ save data
- 8 1w.crc8.rev? if \ crc good?
- r> r> 8 lshift +
- &100 &2 */
- 0 \ ok
- else
- r> r> drop drop
- 1 \ error
- then
-; \ No newline at end of file
diff --git a/amforth-6.5/common/lib/hardware/1wire.frt b/amforth-6.5/common/lib/hardware/1wire.frt
deleted file mode 100644
index 6d96759..0000000
--- a/amforth-6.5/common/lib/hardware/1wire.frt
+++ /dev/null
@@ -1,222 +0,0 @@
-\ Adapted from 4e4th:
-\ all relevant words are lowercase.
-\ romid is now a forth 2012 buffer.
-\ assembly part rewritten from scratch
-\ renamed to file extension frt
-\ requires buffer:
-\ NAME
-\ 1wire.frt
-\ SYNOPSIS
-\ Example high-level Forth functions for Dallas 1-wire devices
-\ DESCRIPTION
-\
-\ USES
-\ Uses the following kernel functions (provided by 1wire.asm)
-\ 1W.RESET [ -- f ] Initialize 1-wire devices; return true if present
-\ 1W.SLOT [ c -- c' ] Write and read one bit to/from 1-wire.
-\
-\ COPYRIGHT
-\ [c] 2012 Bradford J. Rodriguez.
-\
-\ This program is free software; you can redistribute it and/or modify
-\ it under the terms of the GNU General Public License as published by
-\ the Free Software Foundation; either version 3 of the License, or
-\ [at your option] any later version.
-\
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-\ GNU General Public License for more details.
-\
-\ You should have received a copy of the GNU General Public License
-\ along with this program. If not, see <http://www.gnu.org/licenses/>.
-\
-\ Commercial inquiries should be directed to the author at
-\ 115 First St., #105, Collingwood, Ontario L9Y 4W3 Canada
-\ or via email to bj@camelforth.com
-\ ******
-
-
-\ Basic 1-wire operations
-\ 1W.TOUCH ( c1 -- c2 ) Write and read one byte to/from 1-wire bus.
-\ This implements the "touch byte" function described in Dallas
-\ Application Note 74. It expects a byte c1 which is sent over the
-\ 1-wire bus. To perform a read operation, this must be FF hex.
-\ The returned byte c2 is the data read back from the bus. For a
-\ read operation, this is the read data; for a write operation, this
-\ has no significance and can be discarded.
-\
-\ C!1W ( c -- ) Write one byte to the 1-wire bus.
-\ This uses 1W.TOUCH to write one byte of data. The value returned
-\ by 1W.TOUCH is discarded.
-\
-\ C@1W ( -- c ) Read one byte from the 1-wire bus.
-\ This uses 1W.TOUCH with an input parameter of FF hex to read one
-\ byte from a 1-wire device.
-\
-
-\ #include buffer.frt
-
-: 1w.touch ( c1 -- c2 )
- 1w.slot 1w.slot 1w.slot 1w.slot
- 1w.slot 1w.slot 1w.slot 1w.slot ;
-
-: c!1w ( c -- ) 1w.touch drop ;
-: c@1w ( -- c ) $ff 1w.touch ;
-: n>1w ( xN .. x1 N -- ) 0 ?do c!1w loop ;
-: n<1w ( N -- x1 .. xN ) 0 ?do c@1w loop ;
-
-\ SHOWID should be used ONLY if there is a single 1-wire device attached.
-: 1w.showid
- 1w.reset if base @ hex
- $33 c!1w
- c@1w . c@1w . c@1w . c@1w .
- c@1w . c@1w . c@1w . c@1w .
- base !
- then ;
-
-\ Maxim 1-wire ROM Search algorithm
-\ per AN937 "Book of iButton Standards", figure 5-3
-
-variable lastdisc ( used as byte variable )
-lastdisc 1+ constant doneflag ( used as byte variable )
-
-variable rombit ( used as byte variable, 1..64 )
-rombit 1+ constant discmark ( used as byte variable )
-
-8 buffer: romid ( 8 byte array )
-
-: !rombit ( f -- )
- rombit c@ 1- 8 /mod ( -- f bit# byte# )
- romid + ( -- f bit# addr )
- 1 rot lshift ( -- f addr bitmask )
- rot if ( f true, set bit )
- over c@ or swap c!
- else ( f false, clear bit )
- invert over c@ and swap c!
- then
-;
-
-: @rombit ( -- f )
- rombit c@ 1- 8 /mod ( -- bit# byte# )
- romid + c@ ( -- bit# byte )
- 1 rot lshift ( -- byte bitmask )
- and
-;
-
-: newsearch 0 lastdisc ! ; ( clear LASTDISC and DONEFLAG )
-
-: romsearch ( -- f ) ( Returns 0 or 1 )
- 0 ( default return value )
- doneflag c@ if
- 0 doneflag c!
- exit
- then
- 1w.reset if ( presence signal detected? )
-
- 1 rombit c! ( yes: set ROM bit index to 1 )
- 0 discmark c! ( set discrepancy marker to 0 )
- $f0 c!1w ( send search command on bus )
- begin
- $03 1w.slot 1w.slot ( read two bits: ba000000 )
- dup $c0 = if ( bitA = bitB = 1?)
- drop
- 0 lastdisc c!
- exit
- else dup 0= if ( bitA = bitB = 0?)
- drop
- rombit c@ lastdisc c@ = if
- 1 !rombit
- else rombit c@ lastdisc c@ > if
- 0 !rombit
- rombit c@ discmark c!
- else @rombit 0= if
- rombit c@ discmark c!
- then then then
- else
- $40 and ( bit A value )
- !rombit
- then then
- @rombit if 1 else 0 then 1w.slot drop ( send ROM bit to bus )
- rombit c@ 1+ dup rombit c!
- $40 > until
- discmark c@ dup lastdisc c!
- 0= if
- 1 doneflag c!
- else
- drop 1 ( set return value to true )
- then
-
- else ( no presence signal )
- 0 lastdisc c!
- then
-;
-
-\ Demonstrates how to use ROMSEARCH to find all attached devices )
-
-: 1w.scan ( -- )
- 1w.reset if ( presence signal detected? )
- base @ hex
- newsearch
- begin
- romsearch
- romid 8 + romid do i c@ 3 u.r loop cr
- 0= until
- cr base !
- then
-;
-
-\ 1w.current is the device the host is currently
-\ communicating with.
-8 buffer: 1w.current
-
-\ define a 1wire device. At compile time
-\ take 8 numbers from the stack, at runtime
-\ copy these numbers to owcurrent and give
-\ this address back to the caller
-\ e.g.
-\ > hex 1w.scan
-\ 28 4C 75 CC 2 0 0 CD
-\ ok
-\ > 28 4C 75 CC 2 0 0 CD 1w.device: sensor1
-\ > sensor1 ( -- addr)
-\ note that the byte order is the same that
-\ 1w.scan prints, your numbers will be different.
-: 1w.device:
- ( n1 .. n8 -- )
- create
- , , , , , , , ,
- does>
- ( -- n1 .. n8 )
- 8 bounds do
- i @i
- loop ;
-
-\ Start an addressed command. This sends RESET, Match ROM [55h],
-\ and the 8 bytes of ROMID. It should be followed by a DS18B20
-\ function command.
-
-: 1w.matchrom ( rom-id -- )
- 1w.reset if
- $55 c!1w ( send Match ROM command )
- 8 0 do c!1w loop ( send 8 id bytes )
- else ." failed" drop then
-;
-
-: 1w.skiprom ( -- )
- 1w.reset if
- $cc c!1w
- then
-;
-
-\ Function commands that address a single device.
-\ They require either a 1w.skiprom to talk to the
-\ only device present on the bus or 1w.matchrom with
-\ a specific ROM-ID to activate a specific one.
-
-: 1w.dumpscratch ( -- ) ( display 9 bytes of scratchpad )
- $BE c!1w
- c@1w . c@1w . c@1w . c@1w .
- c@1w . c@1w . c@1w . c@1w .
- c@1w .
-;
diff --git a/amforth-6.5/common/lib/hardware/date-time.frt b/amforth-6.5/common/lib/hardware/date-time.frt
deleted file mode 100644
index 13e5d25..0000000
--- a/amforth-6.5/common/lib/hardware/date-time.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-
-\ create task space
-$20 $20 0 task: t:date&time
-
-variable seconds
-\ runs every second
-: job-date&time
- 1 seconds +!
- \ more code for minute/hour/day...
- 0 \ flag for an endless loop
-;
-
-\ set up the task
-: setup-date&time
- t:date&time task-init \ create TCB in RAM
- 0 seconds ! \ more code for minutes etc
- t:date&time tcb>tid activate
- \ code from here is executed as task, later on
- ['] job-date&time every-second
-;
-
-\ setup and start the task "date/time"
-: turnkey-date&time
- onlytask \ set up multitasker
- 6 timer0.init timer0.start \ 16 MHz quartz
- \ insert task into task list
- setup-date&time t:date&time tcb>tid alsotask
- multi \ start multitasking
-;
diff --git a/amforth-6.5/common/lib/hardware/i2c-compass.frt b/amforth-6.5/common/lib/hardware/i2c-compass.frt
deleted file mode 100644
index daa6380..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-compass.frt
+++ /dev/null
@@ -1,49 +0,0 @@
-\
-\ compass module mmc2120 (memsic)
-\ hwid is always $30
-\ provides:
-\
-\ i2c.compass.get ( -- status X Y)
-\ X and Y are around 2000 (raw data)
-\ status is 0 if no error occured
-
-\ dechiffer of the raw data:
-\ according to http://www.aurob.com/?p=467
-\ interpolate linearly
-\ x=map(1900,2188,-180,180)
-\ y=map(1910,2193,-180,180)
-\ grad=atan2(x,y)*180/pi
-
-#require i2c.frt
-#require ms.frt
-
-$30 constant i2c.compass
-
-\ internal commands
-: i2c.compass.setcoil
- %00000010 0 2 i2c.compass i2c.n!
-;
-: i2c.compass.resetcoil
- %00000100 0 2 i2c.compass i2c.n!
-;
-
-: i2c.compass.measure
- %00000001 0 2 i2c.compass i2c.n!
-;
-
-: i2c.compass.fetchdata ( -- status x y )
- 5 0 i2c.compass i2c.n@
- ( -- status msb-x lsb-x msb-y lsb-y)
- swap >< or $fff and >r \ Y
- swap >< or $fff and r> \ X
-;
-
-\ get the raw data from the module
-\ the numbers for X/Y are usually around 2000.
-\ status is 0 if everything is ok
-: i2c.compass.get ( -- status x y )
- i2c.compass.resetcoil 1ms
- i2c.compass.setcoil 5 ms
- i2c.compass.measure 5 ms
- i2c.compass.fetchdata
-;
diff --git a/amforth-6.5/common/lib/hardware/i2c-detect.frt b/amforth-6.5/common/lib/hardware/i2c-detect.frt
deleted file mode 100644
index 6bd7fe4..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-detect.frt
+++ /dev/null
@@ -1,40 +0,0 @@
-\ detect presence of all possible devices on I2C bus
-\ only the 7 bit address schema is supported
-
-\ not all bitpatterns are valid 7bit i2c addresses
-: i2c.7bitaddr? ( a -- f) $7 $78 within ;
-
-: i2c.detect ( -- )
- base @ hex
- \ header line
- 4 spaces $10 0 do i 3 .r loop
- $80 0 do
- i $0f and 0= if
- cr i 2 .r [char] : emit space
- then
- i i2c.7bitaddr? if
- i i2c.ping? if \ does device respond?
- i 3 .r
- else
- ." --"
- then
- else
- ." "
- then
- loop
- cr base !
-;
-
-\ output looks like
-\ (ATmega1280)> i2c.detect
-\ 0 1 2 3 4 5 6 7 8 9 A B C D E F
-\ 0: -- -- -- -- -- -- -- -- --
-\ 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-\ 20: -- -- -- -- -- -- -- 27 -- -- -- -- -- -- -- --
-\ 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-\ 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-\ 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-\ 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-\ 70: -- -- -- -- -- -- -- --
-\ ok
-\
diff --git a/amforth-6.5/common/lib/hardware/i2c-eeprom-block.frt b/amforth-6.5/common/lib/hardware/i2c-eeprom-block.frt
deleted file mode 100644
index 22351fb..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-eeprom-block.frt
+++ /dev/null
@@ -1,77 +0,0 @@
-\
-\ I2C EEPROM driver for BLOCK wordset
-\
-\ call i2c.ee.blockinit to activate the driver
-\ for the BLOCK words.
-
-#require blocks.frt
-#require bounds.frt
-#require i2c-eeprom.frt
-#require ms.frt
-
-\ select a eeprom module.
-\ the pages differ in size.
-\ do not overrun them
-#16 constant 24c08
-#16 constant 24c16
-#32 constant 24c32
-#32 constant 24c64
-#64 constant 24c128
-#64 constant 24c256
-#128 constant 24c512
-#256 constant 24c1024
-
-\ runtime configurable parameters, taken from or
-\ calculated in i2c.ee.blockinit. Never change them directly
-variable i2c.ee.hwid
-variable i2c.ee.pagesize
-variable i2c.ee.pages/block
-
-: i2c.ee.read-page ( addr len page hwid -- )
- dup i2c.begin
- swap i2c.ee.pagesize @ * i2c.ee.send-addr
- i2c.restart \ repeated start
- i2c.rd i2c.tx
- 1- bounds over >r ?do i2c.rx i c! loop
- i2c.rxn r> c! \ last byte
- i2c.end
-;
-
-: i2c.ee.load-buffer ( a-addr u -- ) \ BLOCK API
- 1- i2c.ee.pages/block @ * \ start address
- i2c.ee.pages/block @ bounds ?do
- dup i2c.ee.pagesize @ i i2c.ee.hwid @ i2c.ee.read-page
- i2c.ee.pagesize @ +
- loop drop
-;
-
-: i2c.ee.write-page ( addr len page hwid -- )
- i2c.begin
- i2c.ee.pagesize @ * i2c.ee.send-addr
- bounds ?do i c@ i2c.tx loop
- i2c.end 5 ms \ make sure the eeprom gets ready again
-;
-
-: i2c.ee.save-buffer ( a-addr u -- ) \ BLOCK API
- 1- i2c.ee.pages/block @ * \ start address
- i2c.ee.pages/block @ bounds ?do
- dup i2c.ee.pagesize @ i i2c.ee.hwid @ i2c.ee.write-page
- i2c.ee.pagesize @ +
- loop drop
-;
-
-\ adjust the page size and update the #pages per block buffer
-: i2c.ee.setpagesize ( 24cxx -- )
- blocksize over / i2c.ee.pages/block !
- i2c.ee.pagesize !
-;
-
-\ for turnkey
-\ does not initialize TWI/I2C interface! (i2c.init.default)
-: i2c.ee.blockinit ( pagesize hwid -- )
- block:init
- ['] i2c.ee.load-buffer is load-buffer
- ['] i2c.ee.save-buffer is save-buffer
- i2c.ee.hwid !
- i2c.ee.setpagesize
-;
diff --git a/amforth-6.5/common/lib/hardware/i2c-eeprom-value.frt b/amforth-6.5/common/lib/hardware/i2c-eeprom-value.frt
deleted file mode 100644
index 50f0941..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-eeprom-value.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\
-\ A value stored in I2C EEPROM.
-\
-
-#require value.frt
-#require quotations.frt
-#require ms.frt
-#require i2c-eeprom.frt
-
-\ initial addr hwid ...
-\ 17 0 $50 i2c.value "name"
-: i2c.ee.value ( n addr hwid -- )
- (value)
- over , \ store the addr
- [: dup @i ( addr ) swap 3 + @i ( hwid) @i2c.ee ;] ,
- [: dup @i ( addr ) swap 3 + @i ( hwid) !i2c.ee 5 ms ;] ,
- dup , \ store hwid
- !i2c.ee \ store inital data
-;
diff --git a/amforth-6.5/common/lib/hardware/i2c-eeprom.frt b/amforth-6.5/common/lib/hardware/i2c-eeprom.frt
deleted file mode 100644
index 7468933..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-eeprom.frt
+++ /dev/null
@@ -1,47 +0,0 @@
-\
-\ Basic Access to I2C EEPROM
-\
-\ useful words are
-\ [¢]@i2c.ee/[c]!i2c.ee
-\ See cookbook for further information
-
-#require i2c.frt
-
-: i2c.ee.send-addr ( n -- )
- dup >< i2c.tx ( high byte ) i2c.tx ( low byte )
- \ no stop condition
-;
-
-\ The write methods do not wait afterwards!
-\ at least 5ms have to pass
-: c!i2c.ee ( c addr hwid -- )
- i2c.begin
- i2c.ee.send-addr
- i2c.tx
- i2c.end
-;
-
-: !i2c.ee ( c addr hwid -- )
- i2c.begin
- i2c.ee.send-addr
- dup >< i2c.tx i2c.tx
- i2c.end
-;
-
-: c@i2c.ee ( addr hwid -- c )
- dup i2c.begin
- swap i2c.ee.send-addr
- i2c.start \ repeated start
- i2c.rd i2c.tx \ hwid for reading
- i2c.rx
- i2c.end
-;
-
-: @i2c.ee ( addr hwid -- n )
- dup i2c.begin
- swap i2c.ee.send-addr
- i2c.start \ repeated start
- i2c.rd i2c.tx \ hwid for reading
- i2c.rx >< i2c.rxn or
- i2c.end
-;
diff --git a/amforth-6.5/common/lib/hardware/i2c-lcd.frt b/amforth-6.5/common/lib/hardware/i2c-lcd.frt
deleted file mode 100644
index b404f21..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-lcd.frt
+++ /dev/null
@@ -1,31 +0,0 @@
-
-\ #require i2c-pe.frt
-
-$27 Evalue i2c.lcd.hwid
-
-%00010000 Evalue lcd.En \ enable bit
-%00100000 Evalue lcd.Rw \ read/write bit
-%01000000 Evalue lcd.Rs \ register select bit
-
-: i2c.lcd.pulse ( n -- )
- dup lcd.En or i2c.pe.c!
- lcd.En invert and i2c.pe.c!
-;
-
-: i2c.lcd.!4bit ( n -- )
- dup i2c.pe.c!
- i2c.lcd.pulse
-;
-
-: i2c.lcd.send ( c mode -- )
- >r dup >< $0f and r@ or i2c.lcd.!4bit ( high )
- $0f and r> or i2c.lcd.!4bit ( low )
-;
-
-: i2c.lcd.cmd ( c -- )
- 0 i2c.lcd.send
-;
-
-: i2c.lcd.write ( c -- )
- lcd.Rs i2c.lcd.send
-;
diff --git a/amforth-6.5/common/lib/hardware/i2c-value.frt b/amforth-6.5/common/lib/hardware/i2c-value.frt
deleted file mode 100644
index 7638be6..0000000
--- a/amforth-6.5/common/lib/hardware/i2c-value.frt
+++ /dev/null
@@ -1,23 +0,0 @@
-\
-\ an I2C value
-\
-
-#require values.frt
-#require quotations.frt
-#require i2c.frt
-
-\ initial hwid ...
-\ 17 $3D i2c.cvalue "name"
-: i2c.cvalue ( n addr hwid -- )
- (value)
- dup , \ store the hwid
- [: dup @i ( hwid) i2c.c@ ;] ,
- [: dup @i ( hwid) i2c.c! ;] ,
- i2c.c! \ store inital data
-;
-
-\ use case: port extender
-\ $ff $3d i2c.cvalue keys
-\ $00 to keys ( turn all off )
-\ keys $01 and if ( if key 1 is pressed )
-\
diff --git a/amforth-6.5/common/lib/hardware/i2c.frt b/amforth-6.5/common/lib/hardware/i2c.frt
deleted file mode 100644
index 8941c5f..0000000
--- a/amforth-6.5/common/lib/hardware/i2c.frt
+++ /dev/null
@@ -1,87 +0,0 @@
-\ basic I2C operations, uses 7bit bus addresses
-\ uses the TWI module of the Atmega's.
-\ #require builds.frt
-\ #require bitnames.frt
-
-\ low level driver words
-\ #require i2c-twi-master.frt
-
-\ provides public commands
-
-\ i2c.begin -- starts a I2C bus cycle
-\ i2c.end -- ends a I2C bus cycle
-\ the following operation use a complete bus cycle
-\ i2c.c! -- send one byte
-\ i2c.c@ -- read one byte
-\ i2c.n! -- send n bytes to device
-\ i2c.n@ -- read n bytes from device
-\ i2c.m!n@ -- first send m bytes, than read n bytes
-
-\ convert the bus address into a sendable byte
-\ the address bits are the upper 7 ones,
-\ the LSB is the read/write bit.
-
-: i2c.wr 2* ;
-: i2c.rd 2* 1+ ;
-
-\ aquire the bus and select a device
-\ start a write transaction
-: i2c.begin ( hwid -- )
- dup i2c.current !
- i2c.start i2c.wr i2c.tx
-;
-
-\ start a read transaction
-: i2c.begin-read ( hwid -- )
- dup i2c.current !
- i2c.start i2c.rd i2c.tx
-;
-
-\ release the bus and deselect the device
-: i2c.end ( -- )
- i2c.stop
- 0 i2c.current !
-;
-
-\ tranfser data from/to data stack
-
-\ fetch a byte from the device
-: i2c.c@ ( hwid -- c )
- i2c.begin-read
- i2c.rxn
- i2c.end
-;
-
-\ store a byte to a device
-: i2c.c! ( c hwid -- )
- i2c.begin
- i2c.tx
- i2c.end
-;
-
-\ send n bytes to device
-: i2c.n! ( xn .. x1 N hwid -- )
- i2c.begin
- 0 ?do \ uses N
- i2c.tx \ send x1 ... xn
- loop
- i2c.end
-;
-
-\ get n bytes from device
-: i2c.n@ ( n hwid -- x1 .. xn )
- i2c.begin-read
- 1- 0 max 0 ?do i2c.rx loop i2c.rxn
- i2c.end
-;
-
-\ complex and flexible transaction word
-\ send m bytes x1..xm and fetch n bytes y1..yn afterwards
-: i2c.m!n@ ( n xm .. x1 m hwid -- x1 .. xn )
- dup >r i2c.begin
- 0 ?do i2c.tx loop \ send m bytes
- i2c.restart \ repeated start
- r> i2c.rd i2c.tx \ re-send addr, switch to read mode
- 1- 0 max 0 ?do i2c.rx loop i2c.rxn \ read x1 .. xn
- i2c.end
-;
diff --git a/amforth-6.5/common/lib/hardware/int-critical-test.frt b/amforth-6.5/common/lib/hardware/int-critical-test.frt
deleted file mode 100644
index ac07fe7..0000000
--- a/amforth-6.5/common/lib/hardware/int-critical-test.frt
+++ /dev/null
@@ -1,14 +0,0 @@
-
-\ #require int-critical.frt
-
-: bar ." bar" int? . ;
-: baz ." baz" int? . ;
-: qux ." qux" int? . ;
-
-: foo
- bar
- critical[
- \ nothing will disturb us here
- baz
- ]critical \ now interrupts or other things may happen again
- qux ;
diff --git a/amforth-6.5/common/lib/hardware/int-critical.frt b/amforth-6.5/common/lib/hardware/int-critical.frt
deleted file mode 100644
index d3bbf7f..0000000
--- a/amforth-6.5/common/lib/hardware/int-critical.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-
-\ include mcu specific file
-\ #require int-q.frt
-
-: critical[
- r> int? >r >r \ keep the current state
- -int
-;
-
-: ]critical
- r> r> if +int then >r \ will crash if not matched
-;
diff --git a/amforth-6.5/common/lib/hardware/mmc-test.frt b/amforth-6.5/common/lib/hardware/mmc-test.frt
deleted file mode 100644
index b69fd90..0000000
--- a/amforth-6.5/common/lib/hardware/mmc-test.frt
+++ /dev/null
@@ -1,96 +0,0 @@
-\ MMC+SD card - Lubos Pekny, www.forth.cz
-\ Library for amforth 3.0, mFC modification
-\ Max. 4GB no SDHC, access thru buffer 512B or short block or direct
-
-\ V.1.0, 16.07.2009, tested on atmega32, amforth30mFC12.zip
-\ - used SPI (MOSI, MISO, SCK, SS)
-\ mmc_init, mmc_CID, mmc_CSD, mmc_read, mmc_mread, mmc_write,
-\ mmc_blk@, mmc_blk!, mmc_c@, mmc_c!, mmc_end?, mmc_end!
-
-hex
-
-\ ----- Test -----
-
-mmc_init . \ init card
-mmc_CID . 10 0 mmc. \ view 16B of mmc_buf
-mmc_CSD . 10 0 mmc.
-
-
-\ read
-200 1234 0 mmc_read . \ read 512B from sect. 0:1234
-200 0 mmc. \ view buf
-
-
-\ open+read, short block
-100 1234 0 mmc_read . \ open sector 0:1234, read 256B
-mmc_buf 100 + 100 mmc_blk@ \ read 256B, buf+offset 256B
-200 0 mmc. \ view buf
-
-
-\ open, short block
-0 1234 0 mmc_read . \ open sector 0:1234
-mmc_buf 100 + 100 mmc_blk@ \ read 256B, buf+offset 256B
-mmc_buf 100 mmc_blk@ \ read 256B, switched 256B
-200 0 mmc. \ view buf
-
-
-\ open, direct byte access
-0 1234 0 mmc_read . \ open sector 0:1234
-+mmc
-mmc_c@ . mmc_c@ . \ read 2 bytes from sector
-1FE mmc_dummy \ read other 510 bytes
-1FE mmc_#buf +! \ update counter
-mmc_end? . \ if end of sector then crc dummy
--mmc
-
-
-\ multiread
-200 1234 0 mmc_mread . \ open,read 512B from sect. 1234
-200 0 mmc. \ view buf
-+mmc
-200 0 mmc_(read) . \ read 512B from sect. 1235
-200 0 mmc. \ view buf
-200 0 mmc_(read) . \ read 512B from sect. 1236
-200 0 mmc. \ view buf
-mmc_rstop . \ stop and -mmc
-
-
-\ write
-200 1234 0 mmc_read .
-200 0 mmc.
-ABBA mmc_buf ! \ change 2 bytes in buf
-200 1234 0 mmc_write . \ write 512B to addr. 1234
-200 1234 0 mmc_read .
-200 0 mmc.
-
-
-\ open+write, short block
-ACCA mmc_buf ! \ change 2 bytes in buf
-ADDA mmc_buf 100 + ! \ change 2 bytes in buf
-100 1234 0 mmc_write . \ open sector 1234, write 256B
-mmc_buf 100 + 100 mmc_blk! . \ write 256B, buf+offset 256B
-200 1234 0 mmc_read .
-200 0 mmc.
-
-
-\ open, direct byte access
-0 1234 0 mmc_write .
-+mmc
-AE mmc_c! EA mmc_c! \ write 2 bytes to sector
-1FE mmc_dummy \ write FF, 510x
-1FE mmc_#buf +! \ update counter
-mmc_end! . \ if end then wait while busy
--mmc
-200 1234 0 mmc_read .
-200 0 mmc.
-
-
-\ multiwrite
-ABCD mmc_buf !
-200 1234 0 mmc_mwrite . \ open,write 512B to sect. 1234
-+mmc
-200 0 mmc_(mwrite) . \ write 512B to sect. 1235
-200 0 mmc_(mwrite) . \ write 512B to sect. 1236
-mmc_wstop . \ stop and -mmc
-
-\ end of file
diff --git a/amforth-6.5/common/lib/hardware/power-save.frt b/amforth-6.5/common/lib/hardware/power-save.frt
deleted file mode 100644
index 36e729f..0000000
--- a/amforth-6.5/common/lib/hardware/power-save.frt
+++ /dev/null
@@ -1,36 +0,0 @@
-
-\ fixme: currently the controller sleep too often
-\ that breaks the poll based emit almost completely
-\ either use the interrupt based emit or include an
-\ empty timer task that wakes the controller up
-\
-: idle
- begin
- $0 sleep \ save power, returns on interrupt
- pause \ give cpu away
- again
-;
-
-$20 $20 0 task: idle-task
-
-: start-idle-task
- idle-task tcb>tid
- activate \ words after this line are run in new task
- idle
-;
-
-: starttasker
- idle-task task-init \ create TCB in RAM
- start-idle-task \ activate tasks job
-
- onlytask \ make cmd loop task-1
- idle-task tcb>tid alsotask \ start task-2
- multi \ activate multitasking
-;
-: run-turnkey
- applturnkey
- init
- starttasker
-;
-
-\ ' run-turnkey is turnkey \ make run-turnkey start on power up
diff --git a/amforth-6.5/common/lib/hardware/spi-mmc.frt b/amforth-6.5/common/lib/hardware/spi-mmc.frt
deleted file mode 100644
index 7513e58..0000000
--- a/amforth-6.5/common/lib/hardware/spi-mmc.frt
+++ /dev/null
@@ -1,98 +0,0 @@
-
-
-: spi.init ( -- )
- +spi
- spi.mode0 spi.setmode
- -spi2x
-;
-
-: spi.mmc.dummy ( x -- )
- 0 ?do $ff c!spi loop
-;
-
-: spi.mmc.init ( -- )
- sd.init
- spi.init
- $11 spi.sd.dummy
-;
-
-\ every command has 48 bits=6bytes
-: mmc.cmd ( n1 n2 ... n6 -- )
- -mmc 20 ms \ de-select the card
- $FF c!spi \ some random bits
- +mmc 20 ms \ re-select the card
- $40 or \ set bit 6 if the first byte assuming bit7 is 0
- &6 0 do c!spi loop ; \ send 48bits
-
-
-\ response actions
-\ there are different resonses: r1, r2, r3, r7
-\ r1 is the single byte response ( 0 means no error)
-\ 0 b6 b5 b4 b3 b2 b1 b0
-\ | | | | | | |
-\ | | | | | | In idle state
-\ | | | | | Erase Reset
-\ | | | | Illegal Command
-\ | | | Command CRC error
-\ | | Erase Sequence Error
-\ | Address Error
-\ Parameter Error
-
-\ waiting for cmd response
-: mmc.cresp ( -- c|-1 )
- $FF 0 do
- c@spi dup $80 and 0= \ bit7=0?
- if unloop exit then \ -- c, 0=ok
- drop \ --
- loop -1 ; \ -- -1, timeout
-
-
-\ waiting for data response
-: mmc.dresp ( -- c|-1 )
- $FF 0 do
- c@spi dup $11 and 1 = \ xxx0ccc1
- if
- $0F and unloop exit \ -- c, 5=ok
- then
- drop \ --
- loop -1 ; \ -- -1, timeout
-
-: R1 ( -- f )
- mmc.cresp
-;
-
-: cmd0 ( -- f ) $95 0 0 0 0 0 mmc.cmd R1 1 = ; \ GO_IDLE_STATE - reset
-: cmd1 ( -- f ) $ff 0 0 0 0 1 mmc.cmd R1 0= ; \ SEND_OP_COND init
-: cmd16 ( -- ) $FF 0 0 2 0 16 mmc.cmd R1 drop ; \ SET_BLOCKLEN default 512
-
-\ waiting for data token
-
-: mmc.wait_data_token ( -- f ) 0 16 0 do c@spi $FE = if drop true leave then loop ;
-
-\ read CSD and CID into a 16 byte buffer
-16 buffer: mmc.infoblock
-
-: mmc.readblock ( addr len -- )
- mmc.wait_data_token
- if
- bounds do c@spi i c! loop
- else abort" Could not read MMC data block"
- then ;
-
-: cmd9 ( -- ) $ff 0 0 0 0 9 mmc.cmd R1 mmc.infoblock 16 mmc.readblock ; \ SEND_CSD
-: cmd10 ( -- ) $ff 0 0 0 0 10 mmc.cmd R1 mmc.infoblock 16 mmc.readblock ; \ SEND_CID
-
-\ READ SINGLE BLOCK
-: cmd17 ( addr n -- f )
- >r $ff ( CRC ) r> s>d 17 mmc.cmd R1 mmc.readblock ;
-
-: mmc.writeblock ( addr len -- )
- mmc.wait_data_token
- if
- bounds do i c@ c!spi loop
- else abort" Could not write MMC data block"
- then ;
-
-\ WRITE SINGLE BLOCK (n=512 bytes)
-: cmd24 ( addr n -- f )
- >r $ff ( CRC ) r> s>d 24 mmc.cmd R1 mmc.writeblock ;
diff --git a/amforth-6.5/common/lib/hardware/timer-test.frt b/amforth-6.5/common/lib/hardware/timer-test.frt
deleted file mode 100644
index 7092892..0000000
--- a/amforth-6.5/common/lib/hardware/timer-test.frt
+++ /dev/null
@@ -1,22 +0,0 @@
-\ test routines for timer
-
-\ prints the tick value every second (or so)
-\ until a key is pressed. Usage:
-\ ' test-every-second every-second
-: test-every-second
- @tick u. key?
-;
-
-\ runs a single word n-times. prints the milliseconds
-\ for the whole run
-\ usage
-\ ' foo 10 benchme
-\ executes too 10 times and prints the elapsed time
-
-: benchme ( xt n -- )
- dup >r
- @tick >r
- 0 ?do dup execute loop drop
- @tick r> -
- cr r> u. ." iterations in " u. ." ms" cr
-;
diff --git a/amforth-6.5/common/lib/hardware/timer.frt b/amforth-6.5/common/lib/hardware/timer.frt
deleted file mode 100644
index 5e73b6e..0000000
--- a/amforth-6.5/common/lib/hardware/timer.frt
+++ /dev/null
@@ -1,56 +0,0 @@
-\ generic timer routines, based
-\ upon hardware modules.
-
-\ requires
-\ timer0.frt OR timer1.frt
-\ provides
-\ expired? -- checks whether a counter has expired
-\ elapsed -- get the elapsed time in ms
-\ after -- execute a word after n ms after now
-\ ms -- alternative implementation for ANS94 ms
-\ every -- runs a word every cycle. the word provides an exit flag
-\ every-second -- runs a word every second
-\
-: @tick
- timer0.tick @
- \ timer1.tick @
- \ timer2.tick @
-;
-
-\ a timer is generally a timer tick number.
-\ the actual meaning is either the start time
-\ or the desired end time. All math is done
-\ using unsigned numbers. The maximum interval
-\ is 65.535 seconds (little more then a minute)
-
-\ check if the the timer t has expired
-: expired? ( t -- flag )
- pause @tick - 0> invert
-;
-
-\ alternative implementation for ms
-: ms @tick + begin dup expired? until drop ;
-
-\ get the elapsed time since t
-: elapsed ( t -- n )
- @tick swap -
-;
-
-\ execute the word after u milliseconds
-\ ex: ' foo 10 after
-: after ( xt u -- )
- ms execute
-;
-
-\ execute a word every u ms. The word
-\ has the stack effect ( -- f). If f is
-\ false, the loop ends
-: every ( xt u -- )
- begin over over after until drop drop
-;
-
-\
-: every-second ( xt -- )
- 1000 every
-;
-
diff --git a/amforth-6.5/common/lib/hardware/vt100.frt b/amforth-6.5/common/lib/hardware/vt100.frt
deleted file mode 100644
index ca84bd6..0000000
--- a/amforth-6.5/common/lib/hardware/vt100.frt
+++ /dev/null
@@ -1,59 +0,0 @@
-\ ansi terminal codes
-
-: ESC[ #27 emit [char] ] emit ;
-
-\ some helper words: print a number *without*
-\ leading space in decimal
-: .n base @ swap decimal 0 u.r base ! ;
-: .;n [char] ; emit .n ;
-: ESC[ #27 emit [char] [ emit ;
-
-\ position curser on terminal
-: at-xy ( u1 u2 -- )
- 1+ swap 1+ swap ESC[ .n .;n [char] H emit
-;
-
-\ clear page
-: page ( -- )
- ESC[ ." 2J" 0 0 at-xy
-;
-
-\ more definitions based on gforth' ansi.fs
-
-: foreground ( n -- | set foreground color to n )
- ESC[ #30 + .n [char] m emit
-;
-
-: background ( n -- | set background color to n )
- ESC[ #40 + .n [char] m emit
-;
-
-: text_normal ( -- | set normal text display )
- ESC[ [char] 0 emit [char] m emit
-;
-
-: text_bold ( -- | set bold text )
- ESC[ [char] 1 emit [char] m emit
-;
-
-: text_underline ( -- | set underlined text )
- ESC[ [char] 4 emit [char] m emit
-;
-
-: text_blink ( -- | set blinking text )
- ESC[ [char] 5 emit [char] m emit
-;
-
-: text_reverse ( -- | set reverse video text )
- ESC[ [char] 7 emit [char] m emit
-;
-
-
-#0 constant Black
-#1 constant Red
-#2 constant Green
-#3 constant Yellow
-#4 constant Blue
-#5 constant Brown
-#6 constant Cyan
-#7 constant White
diff --git a/amforth-6.5/common/lib/hardware/xonxoff.frt b/amforth-6.5/common/lib/hardware/xonxoff.frt
deleted file mode 100644
index d6a59d9..0000000
--- a/amforth-6.5/common/lib/hardware/xonxoff.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\
-\ enrich the serial IO with XON/XOFF
-\ this is not a complete and fool-proof
-\
-
-\ #requires is.frt
-
-$11 constant XON
-$13 constant XOFF
-
-\ original refill
-variable xt-refill
-
-: refill-xon
- XON emit
- xt-refill @ execute
- XOFF emit
-;
-
-: +xonxoff
- ['] refill defer@ xt-refill !
- ['] refill-xon is refill
-;
-
-: -xonxoff
- xt-refill @ is refill
-;
diff --git a/amforth-6.5/common/lib/help-words.frt b/amforth-6.5/common/lib/help-words.frt
deleted file mode 100644
index e3e85cd..0000000
--- a/amforth-6.5/common/lib/help-words.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-
-\ requires help
-
-get-current
-help-wl set-current
-
-: emit
- ." ( c -- ) "
- ." R:( -- ) "
- ." emits a single character on the terminal, calls pause" ;
-
-: key
- ." ( -- c ) "
- ." R: ( -- ) "
- ." waits for a key stroke, calls pause "
-;
-
-
-set-current
diff --git a/amforth-6.5/common/lib/help.frt b/amforth-6.5/common/lib/help.frt
deleted file mode 100644
index 45e877e..0000000
--- a/amforth-6.5/common/lib/help.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ small online help system
-
-\ usage
-\ help <word>
-\ prints the stack effects and a short description
-
-wordlist constant help-wl
-
-: help
- parse-name help-wl search-wordlist
- if execute then
-;
-
diff --git a/amforth-6.5/common/lib/in.frt b/amforth-6.5/common/lib/in.frt
deleted file mode 100644
index b2af5f3..0000000
--- a/amforth-6.5/common/lib/in.frt
+++ /dev/null
@@ -1,36 +0,0 @@
-\ invented at the Euro Forth 2016 to
-\ define a word in a vocabulary different
-\ to CURRENT
-
-\ #require also.frt
-\ #require previous.frt
-\ #require definitions.frt
-
-
-: in ( "voc" "defining-word" -- )
- get-current >r also ' execute
- definitions previous ' execute r> set-current
-;
-
-\ use as follows, require vocabulary.frt first
-\ vocabulary gui
-\ in gui : foo ( .. -- .. ) ... ;
-\ in gui variable bar
-\ in gui defer baz
-\ show what's in gui
-\ also gui words previous
-\ remeber: gui is a vocabulary, not a wordlist
-\
-\ Alternative implementation uses wordlist id's
-\ instead of vocabularies. All the #require
-\ lines can be omitted.
-\
-\ : IN ( wid "action" -- )
-\ get-current >r set-current ' execute r> set-current ;
-\
-\ use it like
-\ wordlist constant gui
-\ ... same as above
-\ show the content of gui
-\ gui show-wordlist
-\
diff --git a/amforth-6.5/common/lib/iniside-q.frt b/amforth-6.5/common/lib/iniside-q.frt
deleted file mode 100644
index 15c56e7..0000000
--- a/amforth-6.5/common/lib/iniside-q.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-: inside? ( x start len -- flag ) >r - r> u< ;
-
diff --git a/amforth-6.5/common/lib/local.frt b/amforth-6.5/common/lib/local.frt
deleted file mode 100644
index 94cf86d..0000000
--- a/amforth-6.5/common/lib/local.frt
+++ /dev/null
@@ -1,63 +0,0 @@
-\ trivial local
-
-\ there is exactly one local called X
-\ it is not initialized upon entry
-\ it works like a local should do:
-\ get the content by calling X, assign
-\ a new value with TO
-
-\ separate local stack
-
-\ max. call depth 10
-#10 cells constant l-sizee
-
-\ the local stack pointer and the stack itself
-l-size cell+ buffer: lsp
-
-\ initialize l-stackpointer, call it
-\ in e.g. turnkey prior to use!
-: l-init lsp l-size + lsp ! ;
-
-\ general stack access, unsued
-: l@ lsp @ @ ;
-: l! lsp @ ! ;
-: l-free 1 cells lsp +! ;
-: l-alloc -1 cells lsp +! ;
-: >l l! l-alloc ;
-: l> l-free l@ ;
-
-: local@ negate lsp @ + @ ;
-: local! negate lsp @ + ! ;
-
-\ define a local by its offset
-\ relative to the local stack pointer
-: local ( offset "name" -- )
- (value) ,
- ['] local@ ,
- ['] local! ,
-;
-
-\ should be smarter, it should
-\ check whether X is used at all
-\ and allocate the local stack
-\ only if needed.
-: : : l-alloc ;
-: ; l-free postpone ; ; immediate
-
-\ globally define a label for the first
-\ local variable. The X is a global name
-\ but has local content. If using more,
-\ add a l-alloc/l-free pair in the : and ;
-\ definitions above.
-
-0 local X
-
-\ test cases
-\ l-init
-\ : test1 to X X . ;
-\ 1 test1
-\ -> 1
-\ : test2 1 test1 to X X . ;
-\ 2 test2
-\ -> 1 2
-\ \ No newline at end of file
diff --git a/amforth-6.5/common/lib/macro.frt b/amforth-6.5/common/lib/macro.frt
deleted file mode 100644
index cde7dee..0000000
--- a/amforth-6.5/common/lib/macro.frt
+++ /dev/null
@@ -1,25 +0,0 @@
-\ source
-\ Message-ID: <hembp6$l40$1@news.eternal-september.org>
-\ From: "Gerry" <gerry@jackson9000.fsnet.co.uk>
-\ Newsgroups: comp.lang.forth
-\ Subject: Re: LC53 statistics
-\ Date: Thu, 26 Nov 2009 16:52:34 -0000
-
-\ macros are strings delimited by a single
-\ character not to be used within the macro
-\ itself
-
-: macro
- : char parse postpone sliteral postpone evaluate
- postpone ; immediate
-;
-
-\ Usage is e.g.
-
-\ macro square " dup *" ok
-\ : foo 5 square . ; ok
-\ foo 25 ok
-\ macro s2 - dup + - ok
-\ : bar 6 s2 ; ok
-\ bar 12 ok
-
diff --git a/amforth-6.5/common/lib/minus-loop.frt b/amforth-6.5/common/lib/minus-loop.frt
deleted file mode 100644
index 89e2dbd..0000000
--- a/amforth-6.5/common/lib/minus-loop.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ just like +loop but counts
-\ downward for positive numbers.
-
-: -loop ( runtime: x -- )
- postpone negate postpone +loop
-; immediate
-
-\ use case
-\ : test 0 ?do i . 1 -loop ;
-\ -2 test
-\ prints
-\ 0 -1 -2
-\ be aware that this is not common sense; gforth prints only
-\ 0 -1
-\ \ No newline at end of file
diff --git a/amforth-6.5/common/lib/modules-test.frt b/amforth-6.5/common/lib/modules-test.frt
deleted file mode 100644
index df45c7c..0000000
--- a/amforth-6.5/common/lib/modules-test.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Test case for modules - Example code from
-\ http://theforth.net/package/modules
-\ http://theforth.net/package/modules/current-view/glossary.md
-
-\ #require modules.frt
-
-module greet
-
- : hello ." Hello " ;
- : mods ." Modules " ;
-
- : hi hello mods ;
-
- export hi
-end-module
diff --git a/amforth-6.5/common/lib/modules.frt b/amforth-6.5/common/lib/modules.frt
deleted file mode 100644
index 7948e58..0000000
--- a/amforth-6.5/common/lib/modules.frt
+++ /dev/null
@@ -1,28 +0,0 @@
-\ VFX like modules based on Forth-94 wordlists uho 2016-04-16
-\ ----------------------------------------------------------------
-\ http://theforth.net/package/modules
-\ http://theforth.net/package/modules/current-view/glossary.md
-
-\ modified for amforth (@ -> @i for numbers kept in the dictionary )
-
-\ #require set-order.frt
-\ #require get-order.frt
-\ #require previous.frt
-
-: module ( <name> -- old-current )
- get-current wordlist create dup >r ,
- get-order r@ swap 1+ set-order
- r> set-current ;
-
-: export ( <name> old-current -- old-currrent )
- >r >in @ ' swap >in ! ( -- 'name )
- get-current r@ set-current ( -- 'name current )
- create swap , set-current r>
- does> @i execute ;
-
-: expose-module ( <name> -- )
- get-order ' >body @i swap 1+ set-order ;
-
-: end-module ( old-current -- )
- set-current previous ;
-
diff --git a/amforth-6.5/common/lib/multitask-messages.frt b/amforth-6.5/common/lib/multitask-messages.frt
deleted file mode 100644
index af16249..0000000
--- a/amforth-6.5/common/lib/multitask-messages.frt
+++ /dev/null
@@ -1,14 +0,0 @@
-variable message \ the message box, the data exchanged itself.
-cvariable sender \ a task local semaphore
-
-: send ( message -- )
- sender wait
- message !
- sender signal
-;
-
-: receive
- sender wait
- message @
- sender signal
-;
diff --git a/amforth-6.5/common/lib/multitask-new.frt b/amforth-6.5/common/lib/multitask-new.frt
deleted file mode 100644
index 1612f32..0000000
--- a/amforth-6.5/common/lib/multitask-new.frt
+++ /dev/null
@@ -1,9 +0,0 @@
-\ Multitasker
-\ new
-
-\ idea: fork the current task, leaving it empty
-\ assign a new XT to it
-\ start/stop/pause/resume it
-\ PAUSE based
-\
-
diff --git a/amforth-6.5/common/lib/multitask-semaphore.frt b/amforth-6.5/common/lib/multitask-semaphore.frt
deleted file mode 100644
index 3b9cca4..0000000
--- a/amforth-6.5/common/lib/multitask-semaphore.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Semaphores (Source: B. Rodriguez)
-\ cvariable sem1
-\ : read sem1 wait do-something sem1 signal ;
-\ do-something has the ressource controlled by sem1 exlusivly
-\ wait can be used to communicate with interrupt service routines too
-\
-: wait ( addr - )
- begin pause dup c@ until \ wait for non-zero = available
- 0 swap c!
-;
-
-: signal ( addr -- )
- 1 swap c! \ non-zero means available
-;
-
diff --git a/amforth-6.5/common/lib/multitask-test.frt b/amforth-6.5/common/lib/multitask-test.frt
deleted file mode 100644
index 8574bb9..0000000
--- a/amforth-6.5/common/lib/multitask-test.frt
+++ /dev/null
@@ -1,44 +0,0 @@
-
-\ load the multitasker
-\ #require multitask.frt
-
-: 1ms 1000 0 do 500 0 do loop loop ;
-
-: ms ( n -- ) \ call pause on wait
- pause 0 ?do 1ms loop ;
-
- \ create a persistent task
-variable N
-: init
- 0 N !
-;
-\ --- task 2 ---
-: demo-task
- begin
- 1 N +!
- &500 ms
- again ;
-
-$40 $40 0 task: task_demo \ allocate task data space
-
-: setup-demo-task
- task_demo tib>tcb
- activate \ words after this line are run in new task
- demo-task
-;
-
-: starttasker
- task_demo task-init \ create TCB in RAM
- setup-demo-task \ activate tasks job
-
- onlytask \ make cmd loop task-1
- task_demo tib>tcb alsotask \ start task-2
- multi \ activate multitasking
-;
-\ make this the turnkey vector
-\
-: task-turnkey
- applturnkey
- init
- starttasker
-;
diff --git a/amforth-6.5/common/lib/multitask.frt b/amforth-6.5/common/lib/multitask.frt
deleted file mode 100644
index 4d2f699..0000000
--- a/amforth-6.5/common/lib/multitask.frt
+++ /dev/null
@@ -1,135 +0,0 @@
-\ lib/multitask.frt
-\ -------------------------------------------------------------------
-\ Cooperative Multitasker based on
-\ Message-ID: <1187362648.046634.262200@o80g2000hse.googlegroups.com>
-\ From: Brad Eckert <nospaambrad1@tinyboot.com>
-\ Newsgroups: comp.lang.forth
-\ Subject: Re: Tiny OS based on byte-code interpreter
-\ Date: Fri, 17 Aug 2007 07:57:28 -0700
-
-\ TCB (task control block) structure, identical to user area
-\ Offs_| _Name___ | __Description__________________________ |
-\ 0 | status | xt of word that resumes this task | <-- UP
-\ 2 | follower | address of the next task's status |
-\ 4 | RP0 | initial return stack pointer |
-\ 6 | SP0 | initial data stack pointer |
-\ 8 | sp | -> top of stack |
-\ 10 | handler | catch/throw handler |
-\ ... more user variables (mostly IO related)
-
-\ please note that with amforth rp@ @ accesses another location
-\ than r@ due to hardware characteristics.
-
-\ marker _multitask_
-\ #require builds.frt
-
-#0 user status
-#2 user follower
-
-:noname ( 'status1 -- 'status2 ) cell+ @ dup @ i-cell+ >r ; constant pass
-:noname ( 'status1 -- ) up! sp @ sp! rp! ; constant wake
-
-\ switch to the next task in the list
-: multitaskpause ( -- ) rp@ sp@ sp ! follower @ dup @ i-cell+ >r ;
-: stop ( -- ) pass status ! pause ; \ sleep current task
-: task-sleep ( tid -- ) pass swap ! ; \ sleep another task
-: task-awake ( tid -- ) wake swap ! ; \ wake another task
-
-: cell- negate cell+ negate ;
-
-\ continue the code as a task in a predefined tcb
-: activate ( tid -- )
- dup #6 + @ cell-
- over #4 + @ cell- ( -- tid sp rp ) \ point to RP0 SP0
- r> over i-cell+ ! ( save entry at rp ) \ skip all after ACTIVATE
- over ! ( save rp at sp ) \ save stack context for WAKE
- over #8 + ! ( save sp in tos )
- task-awake
-;
-
-\ task: allocates stack space and creates the task control block
-\ alsotask appends the tcb to the (circular, existing) list of TCB
-
-: task: ( C: dstacksize rstacksize add.usersize "name" -- )
- ( R: -- task-information-block )
- <builds
- here , \ store address of TCB
- [ s" /user" environment search-wordlist drop execute ] literal
- ( add.usersize ) + allot \ default user area size
- \ allocate stacks
- ( rstacksize ) allot here , \ store rp0
- ( dstacksize ) allot here , \ store sp0
-
- 1 allot \ keep here away, amforth specific
- does>
- \ leave flash addr on stack
-;
-
-: tib>tcb ( tib -- tcb ) @i ;
-: tib>rp0 ( tib -- rp0 ) i-cell+ @i ;
-: tib>sp0 ( tib -- sp0 ) i-cell+ i-cell+ @i ;
-: tib>size ( tib -- size )
- dup tib>tcb swap tib>sp0 1+ swap -
-;
-: task-init ( tib -- )
- dup tib>tcb over tib>size 0 fill \ clear RAM for tcb and stacks
- dup tib>sp0 over tib>tcb #6 + ! \ store sp0 in tcb[6]
- dup tib>sp0 cell- over tib>tcb #8 + ! \ store sp0-- in tcb[8], tos
- dup tib>rp0 over tib>tcb #4 + ! \ store rp0 in tcb[4]
- #10 over tib>tcb #12 + ! \ store base in tcb[12]
- tib>tcb task-sleep \ store 'pass' in tcb[0]
-;
-
-\ stop multitasking
-: single ( -- ) \ initialize the multitasker with the serial terminal
- ['] noop ['] pause defer!
-;
-
-\ start multitasking
-: multi ( -- )
- ['] multitaskpause ['] pause defer!
-;
-
-
-\ initialize the multitasker with the current task only
-: onlytask ( -- )
- wake status ! \ own status is running
- up@ follower ! \ point to myself
-;
-
-
-\ insert new task structure into task list
-: alsotask ( tid -- )
- ['] pause defer@ >r \ stop multitasking
- single
- follower @ ( -- tid f)
- over ( -- tid f tid )
- follower ! ( -- tid f )
- swap cell+ ( -- f tid-f )
- !
- r> ['] pause defer! \ restore multitasking
-;
-
-\ print all tasks with their id and status
-: tasks ( -- )
- status ( -- tid ) \ starting value
- dup
- begin ( -- tid1 ctid )
- dup u. ( -- tid1 ctid )
- dup @ ( -- tid1 ctid status )
- dup wake = if ." running" drop else
- pass = if ." sleeping" else
- -1 abort" unknown" then
- then
-\ dup #4 + @ ." rp0=" dup u. cell- @ ." TOR=" u.
-\ dup #6 + @ ." sp0=" dup u. cell- @ ." TOS=" u.
-\ dup #8 + @ ." sp=" u.
- cr
- cell+ @ ( -- tid1 next-tid )
- 2dup = ( -- f flag)
- until
- 2drop
- ." Multitasker is "
- ['] pause defer@ ['] noop = if ." not " then
- ." running"
-;
diff --git a/amforth-6.5/common/lib/profiler.frt b/amforth-6.5/common/lib/profiler.frt
deleted file mode 100644
index d2515e7..0000000
--- a/amforth-6.5/common/lib/profiler.frt
+++ /dev/null
@@ -1,31 +0,0 @@
-\ A profiler counts the number of calls
-\ of any word being defined afterwards.
-\
-\ global state: on and off
-variable profiling?
-: profile:on -1 profiling? ! ;
-: profile:off 0 profiling? ! ;
-
-: profiler profiling? @ if 1 swap +! else drop then ;
-\ re-define colon
-: : :
- here 2 allot postpone literal postpone profiler
-;
-
-\ get the address of the profiling data.
-: xt>prf ( xt -- addr )
- cell+ @i
-;
-
-\ useful stuff
-: .prf xt>prf @ u. ;
-: prf-reset xt>prf 0 swap ! ;
-
-\ usage
-\ : foo bar baz ;
-\ profile:on -- turn on profiling
-\ ' foo .prf -- gets the number of calls to foo
-\ ' foo prf-reset -- resets this number
-\ profile:off -- turn off profiling
-\ wanna profile system words? just re-define them now ;)
-\ e.g. : + + ;
diff --git a/amforth-6.5/common/lib/quotations.frt b/amforth-6.5/common/lib/quotations.frt
deleted file mode 100644
index 7f7659b..0000000
--- a/amforth-6.5/common/lib/quotations.frt
+++ /dev/null
@@ -1,26 +0,0 @@
-\ anonymous definitions in a definition
-\ typical usage
-\ : foo ... [: some words ;] ... ;
-\
-\ is equivalent to
-\
-\ :noname some words ; Constant #temp#
-\ : foo ... #temp# ... ;
-\
-\ #require 2-fetch.frt
-\ #require 2-store.frt
-
-: [: ( -- quotation-sys )
- postpone ahead
- latest @ newest 2@ \ save definition state
- :noname \ defines quotation-sys as ( -- latest newest XT ) ( 4 cells)
-; immediate
-
-: ;] ( compile-time: quotation-sys -- ; run-time: -- xt )
- postpone ; >r
- newest 2! latest ! \ restore definiion state
- postpone then
- r>
- postpone literal
- ]
-; immediate
diff --git a/amforth-6.5/common/lib/random.frt b/amforth-6.5/common/lib/random.frt
deleted file mode 100644
index 4f2138c..0000000
--- a/amforth-6.5/common/lib/random.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-
-\ simple random number generator.
-\ based upon comus by Will Baden
-
-variable rnd \ holds some entropy
-
-\ get a random number
-: random ( -- n )
- rnd @ 31421 * 6927 + dup rnd !
-;
-
-\ get a random number between 0 and u
-: rand ( u -- 0..u-1)
- random um* nip ;
-;
diff --git a/amforth-6.5/common/lib/recognizer.frt b/amforth-6.5/common/lib/recognizer.frt
deleted file mode 100644
index 87e812a..0000000
--- a/amforth-6.5/common/lib/recognizer.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ common recognizer words
-\
-\ platform specific code, selected via include directory
-\ #include recognizer-arch.frt
-\
-\ build the methods table for a recognizer
-: dt:token: ( interpret-xt compile-xt postpone-xt "name" -- )
- create swap rot , , ,
-;
-
-\ get and set the stack content
-: set-recognizers forth-recognizer set-stack ;
-: get-recognizers forth-recognizer get-stack ;
-
-\ usage see Recognizer Recipes
diff --git a/amforth-6.5/common/lib/regexp.frt b/amforth-6.5/common/lib/regexp.frt
deleted file mode 100644
index eda1d4a..0000000
--- a/amforth-6.5/common/lib/regexp.frt
+++ /dev/null
@@ -1,65 +0,0 @@
-\ Regular Expressions by Brian W. Kernighan and Rob Pike
-\ Believed to be in the public domain (The Beez)
-
-\ adaption for amforth by MT
-Edefer (matchhere)
-
-: false 0 ;
-: 0<> 0= 0= ;
-\ end adaption for amforth
-
-: (match*) ( a n ra rn c --f)
- begin
- >r 2over 2over (matchhere) if r> drop 2drop 2drop true exit then
- 2over if c@ dup [char] . = swap r@ = or else dup xor then r> swap
- while \ character equals text?
- >r 2>r 1 /string 2r> r> \ if so, match again
- repeat
- drop 2drop 2drop false \ clean up, return false
-;
-
-: (match?) ( a n ra rn c --f)
- >r 2over 2over (matchhere) if r> drop 2drop 2drop true exit then
- 2over if c@ dup [char] . = swap r> = or else r> drop dup xor then
- if 2>r 1 /string 2r> (matchhere) else 2drop 2drop false then
-; \ character equals text?
-:noname ( a n ra rn -- f)
- dup if \ regular expression a null string?
- over char+ c@ dup [char] * = \ if not, does it equal a '*'
- if \ if so, call (match*)
- drop over c@ >r 2 /string r> (match*) exit
- else \ otherwise, does it equal a '?'
- [char] ? =
- if \ if so, call (match?)
- over c@ >r 2 /string r> (match?) exit
- else \ otherwise does it equal a '$'
- over c@ [char] $ = over 1 = and
- if \ and is it the last character?
- 2drop nip 0= exit \ is so, check length of text
- else \ finally, check if it char matches
- 2over 0<> >r c@ >r over c@ dup
- [char] . = swap r> = or r> and
- if 1 /string 2>r 1 /string 2r> recurse exit then false
- then \ if so recurse, otherwise quit
- then
- then
- else
- true \ zero length regular expression
- then >r 2drop 2drop r> \ clean up and exit
-; is (matchhere) \ assign to DEFER (we got 'em)
-
-: match ( a n ra rn --f)
- dup if over c@ [char] ^ = if 1 /string (matchhere) exit then then
- begin \ if caret, chop it
- 2over 2over (matchhere) if 2drop 2drop true exit then
- >r over r> swap \ match characters
- while \ until no more text
- 2>r 1 /string 2r> \ chop text
- repeat 2drop 2drop false \ clean up
-;
-
-\ s" 0,9" s" ^0,?9$" match . .s cr
-\ s" 0:9" s" ^0,?9$" match . .s cr
-\ s" 09" s" ^0,?9$" match . .s cr
-\ s" 009" s" ^0,?9$" match . .s cr
-\ s" 0,,9" s" ^0,?9$" match . .s cr cr
diff --git a/amforth-6.5/common/lib/reverse.frt b/amforth-6.5/common/lib/reverse.frt
deleted file mode 100644
index 9d468f4..0000000
--- a/amforth-6.5/common/lib/reverse.frt
+++ /dev/null
@@ -1,17 +0,0 @@
-\ LIFO made FIFO
-\ ( X1 .. Xn n -- Xn .. X1 n )
-: reverse
- >r
- sp@ sp@ r@ cells + \ ( bot-addr top-addr )
- begin
- over over < \ bot top cross each other?
- while \ no
- dup @ >r \ save top-cell content
- over @ over ! \ replace top-cell
- over r> swap ! \ replace bot-cell
- cell- swap cell+ swap
- repeat
- 2drop
- r>
-;
-
diff --git a/amforth-6.5/common/lib/search-name.frt b/amforth-6.5/common/lib/search-name.frt
deleted file mode 100644
index b47ddd9..0000000
--- a/amforth-6.5/common/lib/search-name.frt
+++ /dev/null
@@ -1,18 +0,0 @@
-
-\ just like search-wordlist
-\ searches a given wordlist for a word and returns its
-\ name token (NT) or 0 if not found.
-\
-
-\ #require quotations.frt
-
-\ the analogon to search-wordlist
-: search-name ( addr len wid -- nt | 0 )
- >r 0 [: ( addr len ignored nt -- addr len false true | nt false )
- >r drop 2dup r@ name>string icompare if
- r> drop 0 -1 else 2drop r> 0 then ;]
- r> traverse-wordlist ( -- addr len false | nt )
- dup 0= if
- nip nip
- then
-;
diff --git a/amforth-6.5/common/lib/sinus.frt b/amforth-6.5/common/lib/sinus.frt
deleted file mode 100644
index e2a6733..0000000
--- a/amforth-6.5/common/lib/sinus.frt
+++ /dev/null
@@ -1,50 +0,0 @@
-\ Sinus and Cosinus
-\ Use table calculating integer sin.
-\ Get values scaled by 10K.
-
-\ tested ok on amforth-1.5 build 24.09.08
-
-decimal
-
-create sintab \ 0...90 degrees, Index in degrees
-0000 , 0175 , 0349 , 0523 , 0698 , 0872 ,
-1045 , 1219 , 1392 , 1564 , 1736 , 1908 ,
-2079 , 2250 , 2419 , 2588 , 2756 , 2924 ,
-3090 , 3256 , 3420 , 3584 , 3746 , 3907 ,
-4067 , 4226 , 4384 , 4540 , 4695 , 4848 ,
-5000 , 5150 , 5299 , 5446 , 5592 , 5736 ,
-5878 , 6018 , 6157 , 6293 , 6428 , 6561 ,
-6691 , 6820 , 6947 , 7071 , 7193 , 7314 ,
-7431 , 7547 , 7660 , 7771 , 7880 , 7986 ,
-8090 , 8192 , 8290 , 8387 , 8480 , 8572 ,
-8660 , 8746 , 8829 , 8910 , 8988 , 9063 ,
-9135 , 9205 , 9272 , 9336 , 9397 , 9455 ,
-9511 , 9563 , 9613 , 9659 , 9703 , 9744 ,
-9781 , 9816 , 9848 , 9877 , 9903 , 9925 ,
-9945 , 9962 , 9976 , 9986 , 9994 , 9998 ,
-10000 ,
-
-: sinus@ sintab + @i ;
-: sin ( degrees -- sinus )
- dup 0< >r abs
- 360 mod
- dup 180 > if 180 - 1 >r else 0 >r then
- dup 90 > if 180 swap - then
- sinus@
- r> if negate then
- r> if negate then ;
-: cos 90 + sin ;
-
-( finis)
-
-\ Notes:
-
-\ In gforth it has to be : sinus@ ( degree -- ) cell * sintab + @i ;
-\ Since @i increments by 2 bytes each step in an atmega flash,
-\ there is no need for cell adjustment in amforth.
-
-\ In the phrase
-\ dup 180 > if 180 - 1 >r else 0 >r then
-\ 1 and 0 act as flags; TRUE and FALSE do this in gforth.
-
-\ mk
diff --git a/amforth-6.5/common/lib/sqrt.frt b/amforth-6.5/common/lib/sqrt.frt
deleted file mode 100644
index 577d370..0000000
--- a/amforth-6.5/common/lib/sqrt.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-\ Paul E Bennet comp.arch.embedded 4 May 2008
-: sqrt -1 swap over do 2 + dup +loop 2/ ;
-
diff --git a/amforth-6.5/common/lib/string-split.frt b/amforth-6.5/common/lib/string-split.frt
deleted file mode 100644
index 848102d..0000000
--- a/amforth-6.5/common/lib/string-split.frt
+++ /dev/null
@@ -1,38 +0,0 @@
-
-\ split a string at position n
-: split ( addr u n -- addr1 u1 addr2 u2 )
- \ addr2 = addr + n
- \ u2 = n - u
- >r ( -- addr u)
- r@ swap ( -- addr u1 u )
- r@ - ( -- addr u1 u2)
- rot dup r> + ( -- u1 u2 addr1 addr2)
- rot 2>r swap 2r>
-;
-
-\ split a string into two at the leftmost char position
-: $split ( addr u char -- addr1 u1 addr2 u2 )
- >r 2dup r> cscan ( -- addr u addr u1 )
- nip split
-;
-
-\ mostly syntactic sugar, improves readability however
-\ left part of a string
-: $left ( addr len l -- addr len')
- nip
-;
-
-\ right part of a string
-: $right ( addr len l -- addr' len' )
- /string
-;
-
-\ test cases
-\ > source char r $split type cr type
-\ rce char r $split type cr type
-\ sou
-\ > source 10 $right type
-\ $right type
-\ > source 8 $left type
-\ source 8 ok
-\ \ No newline at end of file
diff --git a/amforth-6.5/common/lib/to-name.frt b/amforth-6.5/common/lib/to-name.frt
deleted file mode 100644
index 806dc21..0000000
--- a/amforth-6.5/common/lib/to-name.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ go from the XT backwards to get the Name field
-: >name ( xt -- nfa )
- 1- \ link address
- \ tricky: we look for the flash cell whose address + it content & 0x00ff is
- \ this address
- dup 1- >r ( -- lfa )
- $ff swap
- begin
- 1- dup ( -- cnt lfa lfa )
- @i $00ff and 1+ 2/ ( -- cnt fla len )
- over + ( cnt fla lfa? )
- r@ = ( cnt fla lfa? )
- rot 1- dup >r 0= or ( fla flag )
- r> ( fla flag cnt )
- swap ( fla cnt flag )
- rot
- swap
- until
- swap drop
- r> drop
-;
diff --git a/amforth-6.5/common/lib/tracer.frt b/amforth-6.5/common/lib/tracer.frt
deleted file mode 100644
index 9c3536e..0000000
--- a/amforth-6.5/common/lib/tracer.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ tracer Emma Ledwidge's and Gerry
-\ flag to dynamically turn trace output
-\ on and off
-variable tracing?
-: trace:on -1 tracing? ! ;
-: trace:off 0 tracing? ! ;
-
-: tracer tracing? @ if cr itype space .s else 2drop then ;
-
-: : >in @ >r : r> >in !
- parse-name postpone sliteral postpone tracer
-;
-
diff --git a/amforth-6.5/common/lib/u-2slash.frt b/amforth-6.5/common/lib/u-2slash.frt
deleted file mode 100644
index 3f36bb5..0000000
--- a/amforth-6.5/common/lib/u-2slash.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-
-\ unsigned division by 2.
-\ -1 u2/ . gives 32737
-\ -1 2/ . gives -1
-\ -1 2 / . gives 0
-
-: u2/ 1 rshift ;
diff --git a/amforth-6.5/common/lib/u-star-slash-mod.frt b/amforth-6.5/common/lib/u-star-slash-mod.frt
deleted file mode 100644
index 8d1e28f..0000000
--- a/amforth-6.5/common/lib/u-star-slash-mod.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-
-\ was part of the core
-: u*/mod
- >r um* r>
- um/mod
-;
-
diff --git a/amforth-6.5/common/lib/uzerodotr.frt b/amforth-6.5/common/lib/uzerodotr.frt
deleted file mode 100644
index b8c7312..0000000
--- a/amforth-6.5/common/lib/uzerodotr.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ ( ud n -- )
-\ Numeric IO
-\ Print n digits, fill in preceeding zeros if needed
-
-: u0.r ( u n -- )
- >r 0 <# r> 0 ?do # loop #> type
-; \ No newline at end of file
diff --git a/amforth-6.5/common/lib/vocabulary.frt b/amforth-6.5/common/lib/vocabulary.frt
deleted file mode 100644
index 6f47dfd..0000000
--- a/amforth-6.5/common/lib/vocabulary.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-\ create a vocabulary, at runtime replace
-\ the first entry in the search-list
-: vocabulary ( "char" -- )
- <builds
- wordlist ,
- does>
- @i >r
- get-order nip
- r> swap
- set-order
-;
diff --git a/amforth-6.5/common/lib/watcher.frt b/amforth-6.5/common/lib/watcher.frt
deleted file mode 100644
index dedf190..0000000
--- a/amforth-6.5/common/lib/watcher.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-
-\ watcher
-\ catch a read/write action on a particular address
-\ and execute a predefined debug action.
-
-\ core routines
-variable watch-addr
-defer watch-action
-\ redefine memory access words
-: ! dup watch-addr @ = if watch-action then ! ;
-: c@ dup watch-addr @ = if watch-action then c@ ;
-: c! dup watch-addr @ = if watch-action then c! ;
-\ this one is last
-: @ dup watch-addr @ = if watch-action then @ ;
-\ simply use the debugshell
-' ?? is watch-action
-
-\ possible modifications
-\ use an address range
-\ use a list of addresses (address ranges)
-\ ? \ No newline at end of file
diff --git a/amforth-6.5/common/lib/wordlist-tools.frt b/amforth-6.5/common/lib/wordlist-tools.frt
deleted file mode 100644
index 43a5f63..0000000
--- a/amforth-6.5/common/lib/wordlist-tools.frt
+++ /dev/null
@@ -1,18 +0,0 @@
-\ Message-ID: <hjckgg$ojs$1@news.eternal-september.org>
-\ From: "David N. Williams" <williams@umich.edu>
-\ Newsgroups: comp.lang.forth
-\ Subject: >ORDER ORDER> ORDER@
-\ Date: Fri, 22 Jan 2010 11:41:50 -0500
-
-
-: >order ( wid -- order: wid )
- >r get-order r> swap 1+ set-order ;
-
-: order> ( order: wid -- s: wid )
- get-order swap >r 1- set-order r> ;
-
-: order@ ( order: wid -- s: wid )
- get-order over >r 0 ?do drop loop r> ;
-\ mlg's definition:
-\ : order@ ( -- wid ) order> dup >order ;
-
diff --git a/amforth-6.5/common/words/2drop.asm b/amforth-6.5/common/words/2drop.asm
deleted file mode 100644
index 8db2003..0000000
--- a/amforth-6.5/common/words/2drop.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( x1 x2 -- )
-; Stack
-; Remove the 2 top elements
-
-.if cpu_msp430==1
- HEADER(XT_2DROP,5,"2drop",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_2DROP:
- .dw $ff05
- .db "2drop",0
- .dw VE_HEAD
- .set VE_HEAD = VE_2DROP
-XT_2DROP:
- .dw DO_COLON
-PFA_2DROP:
-.endif
- .dw XT_DROP
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/2dup.asm b/amforth-6.5/common/words/2dup.asm
deleted file mode 100644
index 258c4f9..0000000
--- a/amforth-6.5/common/words/2dup.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( x1 x2 -- x1 x2 x1 x2 )
-; Stack
-; Duplicate the 2 top elements
-
-.if cpu_msp430==1
- HEADER(XT_2DUP,4,"2dup",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_2DUP:
- .dw $ff04
- .db "2dup"
- .dw VE_HEAD
- .set VE_HEAD = VE_2DUP
-XT_2DUP:
- .dw DO_COLON
-PFA_2DUP:
-.endif
-
- .dw XT_OVER
- .dw XT_OVER
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/2literal.asm b/amforth-6.5/common/words/2literal.asm
deleted file mode 100644
index 31b03cf..0000000
--- a/amforth-6.5/common/words/2literal.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- x1 x2 ) (C: x1 x2 -- )
-; Compiler
-; compile a cell pair literal in colon definitions
-.if cpu_msp430==1
- IMMED(XT_2LITERAL,8,"2literal",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_2LITERAL:
- .dw $0008
- .db "2literal"
- .dw VE_HEAD
- .set VE_HEAD = VE_2LITERAL
-XT_2LITERAL:
- .dw DO_COLON
-PFA_2LITERAL:
-.endif
- .dw XT_SWAP
- .dw XT_LITERAL
- .dw XT_LITERAL
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/2swap.asm b/amforth-6.5/common/words/2swap.asm
deleted file mode 100644
index 1056c54..0000000
--- a/amforth-6.5/common/words/2swap.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( x1 x2 x3 x4 -- x3 x4 x1 x2 )
-; Stack
-; Exchange the two top cell pairs
-
-.if cpu_msp430==1
- HEADER(XT_2SWAP,5,"2swap",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_2SWAP:
- .dw $ff05
- .db "2swap",0
- .dw VE_HEAD
- .set VE_HEAD = VE_2SWAP
-XT_2SWAP:
- .dw DO_COLON
-PFA_2SWAP:
-
-.endif
- .dw XT_ROT
- .dw XT_TO_R
- .dw XT_ROT
- .dw XT_R_FROM
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/_template.asm b/amforth-6.5/common/words/_template.asm
deleted file mode 100644
index 1b42fcf..0000000
--- a/amforth-6.5/common/words/_template.asm
+++ /dev/null
@@ -1,8 +0,0 @@
-
-.if cpu_msp430==1
-; HEADER(XT_2SWAP,5,"2swap",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-.endif
diff --git a/amforth-6.5/common/words/abort-string.asm b/amforth-6.5/common/words/abort-string.asm
deleted file mode 100644
index 116b1dc..0000000
--- a/amforth-6.5/common/words/abort-string.asm
+++ /dev/null
@@ -1,29 +0,0 @@
-;C ABORT" i*x 0 -- i*x R: j*x -- j*x x1=0
-;C i*x x1 -- R: j*x -- x1<>0
-; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
-
-.if cpu_msp430==1
- ; IMMED(ABORTQUOTE,6,"ABORT"",DOCOLON)
- DW link
- DB 0FEh ; immediate
-.set link = $
- DB 6,"abort",'"'
- .align 16
-XT_ABORTQUOTE:
- .DW DOCOLON
-.endif
-
-.if cpu_avr8==1
-VE_ABORTQUOTE:
- .dw $0006
- .db "abort",'"'
- .dw VE_HEAD
- .set VE_HEAD = VE_ABORTQUOTE
-XT_ABORTQUOTE:
- .dw DO_COLON
-PFA_ABORTQUOTE:
-.endif
- .dw XT_SQUOTE
- .dw XT_COMPILE
- .dw XT_QABORT
- .DW XT_EXIT
diff --git a/amforth-6.5/common/words/abort.asm b/amforth-6.5/common/words/abort.asm
deleted file mode 100644
index 05fe858..0000000
--- a/amforth-6.5/common/words/abort.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( i*x -- ) (R: j*y -- )
-; Exceptions
-; send an exception -1
-.if cpu_msp430==1
- HEADER(XT_ABORT,5,"abort",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_ABORT:
- .dw $ff05
- .db "abort",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ABORT
-XT_ABORT:
- .dw DO_COLON
-PFA_ABORT:
-.endif
- .dw XT_TRUE
- .dw XT_THROW
diff --git a/amforth-6.5/common/words/abs.asm b/amforth-6.5/common/words/abs.asm
deleted file mode 100644
index 429a603..0000000
--- a/amforth-6.5/common/words/abs.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-;C ABS n1 -- +n2 absolute value
-; DUP ?NEGATE ;
-
-.if cpu_msp430==1
- HEADER(XT_ABS,3,"abs",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_ABS:
- .dw $ff03
- .db "abs",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ABS
-XT_ABS:
- .dw DO_COLON
-PFA_ABS:
-
-.endif
-
- .DW XT_DUP,XT_QNEGATE,XT_EXIT
diff --git a/amforth-6.5/common/words/accept.asm b/amforth-6.5/common/words/accept.asm
deleted file mode 100644
index 68afdb1..0000000
--- a/amforth-6.5/common/words/accept.asm
+++ /dev/null
@@ -1,95 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_ACCEPT,6,"accept",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_ACCEPT:
- .dw $ff06
- .db "accept"
- .dw VE_HEAD
- .set VE_HEAD = VE_ACCEPT
-XT_ACCEPT:
- .dw DO_COLON
-PFA_ACCEPT:
-
-.endif
- .DW XT_OVER,XT_PLUS,XT_1MINUS,XT_OVER
-ACC1: .DW XT_KEY,XT_DUP,XT_CRLFQ,XT_ZEROEQUAL,XT_DOCONDBRANCH
- DEST(ACC5)
- .DW XT_DUP,XT_DOLITERAL,8,XT_EQUAL,XT_DOCONDBRANCH
- DEST(ACC3)
- .DW XT_DROP,XT_ROT,XT_2DUP,XT_GREATER,XT_TO_R,XT_ROT,XT_ROT,XT_R_FROM,XT_DOCONDBRANCH
- DEST(ACC6)
- .DW XT_BS,XT_1MINUS,XT_TO_R,XT_OVER,XT_R_FROM,XT_UMAX
-ACC6: .DW XT_DOBRANCH
- DEST(ACC4)
-
-
-ACC3: ; check for remaining control characters, replace them with blank
- .dw XT_DUP ; ( -- addr k k )
- .dw XT_BL
- .dw XT_LESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_ACCEPT6)
- .dw XT_DROP
- .dw XT_BL
-PFA_ACCEPT6:
- .DW XT_DUP,XT_EMIT,XT_OVER,XT_CSTORE,XT_1PLUS,XT_OVER,XT_UMIN
-ACC4: .DW XT_DOBRANCH
- DEST(ACC1)
-ACC5: .DW XT_DROP,XT_NIP,XT_SWAP,XT_MINUS,XT_CR,XT_EXIT
-
-
-; ( -- )
-; System
-; send a backspace character to overwrite the current char
-.if cpu_msp430==1
- HEADLESS(XT_BS,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-;VE_BS:
-; .dw $ff02
-; .db "bs"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_BS
-XT_BS:
- .dw DO_COLON
-.endif
- .dw XT_DOLITERAL
- .dw 8
- .dw XT_DUP
- .dw XT_EMIT
- .dw XT_SPACE
- .dw XT_EMIT
- .dw XT_EXIT
-
-
-; ( c -- f )
-; System
-; is the character a line end character?
-.if cpu_msp430==1
- HEADLESS(XT_CRLFQ,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-;VE_CRLFQ:
-; .dw $ff02
-; .db "crlf?"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_CRLFQ
-XT_CRLFQ:
- .dw DO_COLON
-.endif
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw 13
- .dw XT_EQUAL
- .dw XT_SWAP
- .dw XT_DOLITERAL
- .dw 10
- .dw XT_EQUAL
- .dw XT_OR
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/again.asm b/amforth-6.5/common/words/again.asm
deleted file mode 100644
index 507e1ed..0000000
--- a/amforth-6.5/common/words/again.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- ) (C: dest -- )
-; Compiler
-; compile a jump back to dest
-
-.if cpu_msp430==1
- IMMED(XT_AGAIN,5,"again",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_AGAIN:
- .dw $0005
- .db "again",0
- .dw VE_HEAD
- .set VE_HEAD = VE_AGAIN
-XT_AGAIN:
- .dw DO_COLON
-PFA_AGAIN:
-.endif
- .dw XT_COMPILE
- .dw XT_DOBRANCH
- .dw XT_LRESOLVE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/ahead.asm b/amforth-6.5/common/words/ahead.asm
deleted file mode 100644
index d883543..0000000
--- a/amforth-6.5/common/words/ahead.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( f -- ) (C: -- orig )
-; Compiler
-; do a unconditional branch
-
-.if cpu_msp430==1
- IMMED(XT_AHEAD,5,"ahead",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_AHEAD:
- .dw $0005
- .db "ahead",0
- .dw VE_HEAD
- .set VE_HEAD = VE_AHEAD
-XT_AHEAD:
- .dw DO_COLON
-PFA_AHEAD:
-.endif
- .dw XT_COMPILE
- .dw XT_DOBRANCH
- .dw XT_GMARK
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/backslash.asm b/amforth-6.5/common/words/backslash.asm
deleted file mode 100644
index 5364b9f..0000000
--- a/amforth-6.5/common/words/backslash.asm
+++ /dev/null
@@ -1,30 +0,0 @@
-; ( "ccc<eol>" -- )
-; Compiler
-; everything up to the end of the current line is a comment
-
-.if cpu_msp430==1
-; HEADER(XT_BACKSLASH,1,'\',DOCOLON)
- DW link
- DB 0FEh ; immediate
-.set link = $
- DB 1,5ch
- .align 16
-XT_BACKSLASH:
- .DW DOCOLON
-.endif
-
-.if cpu_avr8==1
-VE_BACKSLASH:
- .dw $0001
- .db $5c,0
- .dw VE_HEAD
- .set VE_HEAD = VE_BACKSLASH
-XT_BACKSLASH:
- .dw DO_COLON
-PFA_BACKSLASH:
-.endif
- .dw XT_SOURCE
- .dw XT_NIP
- .dw XT_TO_IN
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/base.asm b/amforth-6.5/common/words/base.asm
deleted file mode 100644
index 5f686b6..0000000
--- a/amforth-6.5/common/words/base.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- a-addr )
-; Numeric IO
-; location of the cell containing the number conversion radix
-
-.if cpu_msp430==1
- HEADER(XT_BASE,4,"base",DOUSER)
-.endif
-
-.if cpu_avr8==1
-VE_BASE:
- .dw $ff04
- .db "base"
- .dw VE_HEAD
- .set VE_HEAD = VE_BASE
-XT_BASE:
- .dw PFA_DOUSER
-PFA_BASE:
-.endif
- .dw USER_BASE
diff --git a/amforth-6.5/common/words/begin.asm b/amforth-6.5/common/words/begin.asm
deleted file mode 100644
index b2e3c22..0000000
--- a/amforth-6.5/common/words/begin.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( -- ) (C: -- dest )
-; Compiler
-; put the next location for a transfer of control onto the control flow stack
-
-.if cpu_msp430==1
- IMMED(XT_BEGIN,5,"begin",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_BEGIN:
- .dw $0005
- .db "begin",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BEGIN
-XT_BEGIN:
- .dw DO_COLON
-PFA_BEGIN:
-.endif
- .dw XT_LMARK
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/bin.asm b/amforth-6.5/common/words/bin.asm
deleted file mode 100644
index 573c2f6..0000000
--- a/amforth-6.5/common/words/bin.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; Numeric IO
-; set base for numeric conversion to 10
-
-.if cpu_msp430==1
- HEADER(XT_BIN,3,"bin",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_BIN:
- .dw $ff03
- .db "bin",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BIN
-XT_BIN:
- .dw DO_COLON
-PFA_BIN:
-.endif
- .dw XT_TWO
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/bl.asm b/amforth-6.5/common/words/bl.asm
deleted file mode 100644
index cf242da..0000000
--- a/amforth-6.5/common/words/bl.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- 32 )
-; Character IO
-; put ascii code of the blank to the stack
-
-.if cpu_msp430==1
- HEADER(XT_BL,2,"bl",DOCON)
-.endif
-
-.if cpu_avr8==1
-VE_BL:
- .dw $ff02
- .db "bl"
- .dw VE_HEAD
- .set VE_HEAD = VE_BL
-XT_BL:
- .dw PFA_DOVARIABLE
-PFA_BL:
-.endif
- .dw 32
diff --git a/amforth-6.5/common/words/bounds.asm b/amforth-6.5/common/words/bounds.asm
deleted file mode 100644
index 0dd0555..0000000
--- a/amforth-6.5/common/words/bounds.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( addr len -- addr+len addr )
-; Tools
-; convert a string to an address range
-
-.if cpu_msp430==1
- HEADER(XT_BOUNDS,6,"bounds",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_BOUNDS:
- .dw $ff06
- .db "bounds"
- .dw VE_HEAD
- .set VE_HEAD = VE_BOUNDS
-XT_BOUNDS:
- .dw DO_COLON
-PFA_BOUNDS:
-.endif
- .dw XT_OVER
- .dw XT_PLUS
- .dw XT_SWAP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/bracketchar.asm b/amforth-6.5/common/words/bracketchar.asm
deleted file mode 100644
index ee55be0..0000000
--- a/amforth-6.5/common/words/bracketchar.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- c ) (C: "<space>name" -- )
-; Tools
-; skip leading space delimites, place the first character of the word on the stack
-
-.if cpu_msp430==1
- IMMED(XT_BRACKETCHAR,6,"[char]",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_BRACKETCHAR:
- .dw $0006
- .db "[char]"
- .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCHAR
-XT_BRACKETCHAR:
- .dw DO_COLON
-PFA_BRACKETCHAR:
-.endif
- .dw XT_COMPILE
- .dw XT_DOLITERAL
- .dw XT_CHAR
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/bracketcompile.asm b/amforth-6.5/common/words/bracketcompile.asm
deleted file mode 100644
index 01a1512..0000000
--- a/amforth-6.5/common/words/bracketcompile.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- c ) (C: "<space>name" -- )
-; Compiler
-; Append the compilation semantics of "name" to the dictionary, if any
-
-.if cpu_msp430==1
- IMMED(XT_BRACKETCOMPILE,9,"[compile]",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_BRACKETCOMPILE:
- .dw $0009
- .db "[compile]",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETCOMPILE
-XT_BRACKETCOMPILE:
- .dw DO_COLON
-PFA_BRACKETCOMPILE:
-.endif
- .dw XT_COMPILE
- .dw XT_COMPILE
- .dw XT_TICK
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/brackettick.asm b/amforth-6.5/common/words/brackettick.asm
deleted file mode 100644
index 4905ae3..0000000
--- a/amforth-6.5/common/words/brackettick.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- xt ) (C: "<space>name" -- )
-; Compiler
-; what ' does in the interpreter mode, do in colon definitions
-
-.if cpu_msp430==1
- IMMED(XT_BRACKETTICK,3,"[']",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_BRACKETTICK:
- .dw $0003
- .db "[']",0
- .dw VE_HEAD
- .set VE_HEAD = VE_BRACKETTICK
-XT_BRACKETTICK:
- .dw DO_COLON
-PFA_BRACKETTICK:
-.endif
- .dw XT_TICK
- .dw XT_LITERAL
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/build-info.tmpl b/amforth-6.5/common/words/build-info.tmpl
deleted file mode 100644
index 6df97b8..0000000
--- a/amforth-6.5/common/words/build-info.tmpl
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( -- i-addr len ) System
-; R( -- )
-; Build Info as flash string
-
-.if cpu_msp430==1
- HEADER(XT_BUILDINFO,10,"build-info",DOCOLON)
- .dw XT_DOSLITERAL
- .db @TSTAMPLEN@
- .db "@TSTAMP@"
- .align 16
-.endif
-
-.if cpu_avr8==1
-VE_BUILDINFO:
- .dw $ff0a
- .db "build-info"
- .dw VE_HEAD
- .set VE_HEAD = VE_BUILDINFO
-XT_BUILDINFO:
- .dw DO_COLON
-PFA_BUILDINFO:
- .dw XT_DOSLITERAL
- .dw @TSTAMPLEN@
- .db "@TSTAMP@"
-.endif
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/catch.asm b/amforth-6.5/common/words/catch.asm
deleted file mode 100644
index c67be65..0000000
--- a/amforth-6.5/common/words/catch.asm
+++ /dev/null
@@ -1,39 +0,0 @@
-; ( i*x xt -- j*x 0 | i*x n )
-; Exceptions
-; execute XT and check for exceptions.
-
-.if cpu_msp430==1
- HEADER(XT_CATCH,5,"catch",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_CATCH:
- .dw $ff05
- .db "catch",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CATCH
-XT_CATCH:
- .dw DO_COLON
-PFA_CATCH:
-.endif
-
- ; sp@ >r
- .dw XT_SP_FETCH
- .dw XT_TO_R
- ; handler @ >r
- .dw XT_HANDLER
- .dw XT_FETCH
- .dw XT_TO_R
- ; rp@ handler !
- .dw XT_RP_FETCH
- .dw XT_HANDLER
- .dw XT_STORE
- .dw XT_EXECUTE
- ; r> handler !
- .dw XT_R_FROM
- .dw XT_HANDLER
- .dw XT_STORE
- .dw XT_R_FROM
- .dw XT_DROP
- .dw XT_ZERO
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/cfg-order.asm b/amforth-6.5/common/words/cfg-order.asm
deleted file mode 100644
index 2fba330..0000000
--- a/amforth-6.5/common/words/cfg-order.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- wid-n .. wid-1 n)
-; Search Order
-; Get the current search order word list
-
-.if cpu_msp430==1
- HEADER(XT_CFG_ORDER,9,"cfg-order",DOCON)
-.endif
-
-.if cpu_avr8==1
-VE_CFG_ORDER:
- .dw $ff09
- .db "cfg-order",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CFG_ORDER
-XT_CFG_ORDER:
- .dw PFA_DOVARIABLE
-PFA_CFG_ORDER:
-.endif
- .dw CFG_ORDERLISTLEN
diff --git a/amforth-6.5/common/words/cfg-recognizer.asm b/amforth-6.5/common/words/cfg-recognizer.asm
deleted file mode 100644
index 8e6322a..0000000
--- a/amforth-6.5/common/words/cfg-recognizer.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- wid-n .. wid-1 n)
-; Search Order
-; Get the current search order word list
-
-.if cpu_msp430==1
- HEADER(XT_CFG_RECOGNIZER,8,"cfg-recs",DOCON)
-.endif
-
-.if cpu_avr8==1
-VE_CFG_RECOGNIZER:
- .dw $ff08
- .db "cfg-recs"
- .dw VE_HEAD
- .set VE_HEAD = VE_CFG_RECOGNIZER
-XT_CFG_RECOGNIZER:
- .dw PFA_DOVARIABLE
-PFA_CFG_RECOGNIZER:
-.endif
- .dw CFG_RECOGNIZERLISTLEN
diff --git a/amforth-6.5/common/words/char.asm b/amforth-6.5/common/words/char.asm
deleted file mode 100644
index 0fde37b..0000000
--- a/amforth-6.5/common/words/char.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( "<spaces>name" -- c )
-; Tools
-; copy the first character of the next word onto the stack
-
-.if cpu_msp430==1
- HEADER(XT_CHAR,4,"char",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_CHAR:
- .dw $ff04
- .db "char"
- .dw VE_HEAD
- .set VE_HEAD = VE_CHAR
-XT_CHAR:
- .dw DO_COLON
-PFA_CHAR:
-.endif
- .dw XT_PARSENAME
- .dw XT_DROP
- .dw XT_CFETCH
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/colon.asm b/amforth-6.5/common/words/colon.asm
deleted file mode 100644
index 3ec45ae..0000000
--- a/amforth-6.5/common/words/colon.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- ) (C: "<spaces>name" -- )
-; Compiler
-; create a named entry in the dictionary, XT is DO_COLON
-
-.if cpu_msp430==1
- HEADER(XT_COLON,1,":",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_COLON:
- .dw $ff01
- .db ":",0
- .dw VE_HEAD
- .set VE_HEAD = VE_COLON
-XT_COLON:
- .dw DO_COLON
-PFA_COLON:
-.endif
- .dw XT_DOCREATE
- .dw XT_COLONNONAME
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/compile.asm b/amforth-6.5/common/words/compile.asm
deleted file mode 100644
index 524cee6..0000000
--- a/amforth-6.5/common/words/compile.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- )
-; Dictionary
-; read the following cell from the dictionary and append it to the current dictionary position.
-
-.if cpu_msp430==1
- HEADER(XT_COMPILE,7,"compile",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_COMPILE:
- .dw $ff07
- .db "compile",0
- .dw VE_HEAD
- .set VE_HEAD = VE_COMPILE
-XT_COMPILE:
- .dw DO_COLON
-PFA_COMPILE:
-.endif
- .dw XT_R_FROM
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_TO_R
- .dw XT_FETCHI
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/constant.asm b/amforth-6.5/common/words/constant.asm
deleted file mode 100644
index 2f79dc3..0000000
--- a/amforth-6.5/common/words/constant.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- x ) (C: x "<spaces>name" -- )
-; Compiler
-; create a constant in the dictionary
-
-.if cpu_msp430==1
- HEADER(XT_CONSTANT,8,"constant",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-VE_CONSTANT:
- .dw $ff08
- .db "constant"
- .dw VE_HEAD
- .set VE_HEAD = VE_CONSTANT
-XT_CONSTANT:
- .dw DO_COLON
-PFA_CONSTANT:
-.endif
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_COMPILE
- .dw PFA_DOVARIABLE
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/cr.asm b/amforth-6.5/common/words/cr.asm
deleted file mode 100644
index ba704ba..0000000
--- a/amforth-6.5/common/words/cr.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( -- )
-; Character IO
-; cause subsequent output appear at the beginning of the next line
-
-.if cpu_msp430==1
- HEADER(XT_CR,2,"cr",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_CR:
- .dw 0xff02
- .db "cr"
- .dw VE_HEAD
- .set VE_HEAD = VE_CR
-XT_CR:
- .dw DO_COLON
-PFA_CR:
-.endif
-
- .dw XT_DOLITERAL
- .dw 13
- .dw XT_EMIT
- .dw XT_DOLITERAL
- .dw 10
- .dw XT_EMIT
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/create.asm b/amforth-6.5/common/words/create.asm
deleted file mode 100644
index b288474..0000000
--- a/amforth-6.5/common/words/create.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- a-addr ) (C: "<spaces>name" -- )
-; Dictionary
-; create a dictionary header. XT is (constant), with the address of the data field of name
-
-.if cpu_msp430==1
- HEADER(XT_CREATE,6,"create",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_CREATE:
- .dw $ff06
- .db "create"
- .dw VE_HEAD
- .set VE_HEAD = VE_CREATE
-XT_CREATE:
- .dw DO_COLON
-PFA_CREATE:
-.endif
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_COMPILE
- .dw PFA_DOCONSTANT
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/cscan.asm b/amforth-6.5/common/words/cscan.asm
deleted file mode 100644
index e043f60..0000000
--- a/amforth-6.5/common/words/cscan.asm
+++ /dev/null
@@ -1,56 +0,0 @@
-; ( addr1 n1 c -- addr1 n2 )
-; String
-; Scan string at addr1/n1 for the first occurance of c, leaving addr1/n2, char at n2 is first non-c character
-
-.if cpu_msp430==1
- HEADER(XT_CSCAN,5,"cscan",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_CSCAN:
- .dw $ff05
- .db "cscan"
- .dw VE_HEAD
- .set VE_HEAD = VE_CSCAN
-XT_CSCAN:
- .dw DO_COLON
-PFA_CSCAN:
-.endif
- .dw XT_TO_R
- .dw XT_OVER
-PFA_CSCAN1:
- .dw XT_DUP
- .dw XT_CFETCH
- .dw XT_R_FETCH
- .dw XT_EQUAL
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_CSCAN2)
- .dw XT_SWAP
- .dw XT_1MINUS
- .dw XT_SWAP
- .dw XT_OVER
- .dw XT_ZEROLESS ; not negative
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_CSCAN2)
- .dw XT_1PLUS
- .dw XT_DOBRANCH
- DEST(PFA_CSCAN1)
-PFA_CSCAN2:
- .dw XT_NIP
- .dw XT_OVER
- .dw XT_MINUS
- .dw XT_R_FROM
- .dw XT_DROP
- .dw XT_EXIT
-
-; : my-cscan ( addr len c -- addr len' )
-; >r over ( -- addr len addr )
-; begin
-; dup c@ r@ <> while
-; swap 1- swap over 0 >= while
-; 1+
-; repeat then
-; nip over - r> drop
-; ;
diff --git a/amforth-6.5/common/words/cskip.asm b/amforth-6.5/common/words/cskip.asm
deleted file mode 100644
index d57ff9c..0000000
--- a/amforth-6.5/common/words/cskip.asm
+++ /dev/null
@@ -1,37 +0,0 @@
-; ( addr1 n1 c -- addr2 n2 )
-; String
-; skips leading occurancies in string at addr1/n1 leaving addr2/n2 pointing to the 1st non-c character
-
-.if cpu_msp430==1
- HEADER(XT_CSKIP,5,"cskip",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_CSKIP:
- .dw $ff05
- .db "cskip",0
- .dw VE_HEAD
- .set VE_HEAD = VE_CSKIP
-XT_CSKIP:
- .dw DO_COLON
-PFA_CSKIP:
-.endif
- .dw XT_TO_R ; ( -- addr1 n1 )
-PFA_CSKIP1:
- .dw XT_DUP ; ( -- addr' n' n' )
- .dw XT_DOCONDBRANCH ; ( -- addr' n')
- DEST(PFA_CSKIP2)
- .dw XT_OVER ; ( -- addr' n' addr' )
- .dw XT_CFETCH ; ( -- addr' n' c' )
- .dw XT_R_FETCH ; ( -- addr' n' c' c )
- .dw XT_EQUAL ; ( -- addr' n' f )
- .dw XT_DOCONDBRANCH ; ( -- addr' n')
- DEST(PFA_CSKIP2)
- .dw XT_ONE
- .dw XT_SLASHSTRING
- .dw XT_DOBRANCH
- DEST(PFA_CSKIP1)
-PFA_CSKIP2:
- .dw XT_R_FROM
- .dw XT_DROP ; ( -- addr2 n2)
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/d-dot-r.asm b/amforth-6.5/common/words/d-dot-r.asm
deleted file mode 100644
index cc556d7..0000000
--- a/amforth-6.5/common/words/d-dot-r.asm
+++ /dev/null
@@ -1,35 +0,0 @@
-; ( d w -- )
-; Numeric IO
-; singed PNO with double cell numbers, right aligned in width w
-
-.if cpu_msp430==1
- HEADER(XT_DDOTR,3,"d.r",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DDOTR:
- .dw $ff03
- .db "d.r",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DDOTR
-XT_DDOTR:
- .dw DO_COLON
-PFA_DDOTR:
-
-.endif
- .dw XT_TO_R
- .dw XT_TUCK
- .dw XT_DABS
- .dw XT_L_SHARP
- .dw XT_SHARP_S
- .dw XT_ROT
- .dw XT_SIGN
- .dw XT_SHARP_G
- .dw XT_R_FROM
- .dw XT_OVER
- .dw XT_MINUS
- .dw XT_SPACES
- .dw XT_TYPE
- .dw XT_EXIT
-; : d.r ( d n -- )
-; >r swap over dabs <# #s rot sign #> r> over - spaces type ;
diff --git a/amforth-6.5/common/words/d-dot.asm b/amforth-6.5/common/words/d-dot.asm
deleted file mode 100644
index 8aa1169..0000000
--- a/amforth-6.5/common/words/d-dot.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( d -- )
-; Numeric IO
-; singed PNO with double cell numbers
-
-.if cpu_msp430==1
- HEADER(XT_DDOT,2,"d.",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DDOT:
- .dw $ff02
- .db "d."
- .dw VE_HEAD
- .set VE_HEAD = VE_DDOT
-XT_DDOT:
- .dw DO_COLON
-PFA_DDOT:
-
-.endif
- .dw XT_ZERO
- .dw XT_DDOTR
- .dw XT_SPACE
- .dw XT_EXIT
-; : d. ( d -- ) 0 d.r space ;
diff --git a/amforth-6.5/common/words/decimal.asm b/amforth-6.5/common/words/decimal.asm
deleted file mode 100644
index de65dd4..0000000
--- a/amforth-6.5/common/words/decimal.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- )
-; Numeric IO
-; set base for numeric conversion to 10
-
-.if cpu_msp430==1
- HEADER(XT_DECIMAL,7,"decimal",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DECIMAL:
- .dw $ff07
- .db "decimal",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DECIMAL
-XT_DECIMAL:
- .dw DO_COLON
-PFA_DECIMAL:
-.endif
- .dw XT_DOLITERAL
- .dw 10
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/defer-fetch.asm b/amforth-6.5/common/words/defer-fetch.asm
deleted file mode 100644
index 6044afc..0000000
--- a/amforth-6.5/common/words/defer-fetch.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( xt1 -- xt2 )
-; System
-; returns the XT associated with the given XT
-
-.if cpu_msp430==1
- HEADER(XT_DEFERFETCH,6,"defer@",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DEFERFETCH:
- .dw $ff06
- .db "defer@"
- .dw VE_HEAD
- .set VE_HEAD = VE_DEFERFETCH
-XT_DEFERFETCH:
- .dw DO_COLON
-PFA_DEFERFETCH:
-.endif
- .dw XT_TO_BODY
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/defer-store.asm b/amforth-6.5/common/words/defer-store.asm
deleted file mode 100644
index 4ca579c..0000000
--- a/amforth-6.5/common/words/defer-store.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( xt1 xt2 -- )
-; System
-; stores xt1 as the xt to be executed when xt2 is called
-
-.if cpu_msp430==1
- HEADER(XT_DEFERSTORE,6,"defer!",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DEFERSTORE:
- .dw $ff06
- .db "defer!"
- .dw VE_HEAD
- .set VE_HEAD = VE_DEFERSTORE
-XT_DEFERSTORE:
- .dw DO_COLON
-PFA_DEFERSTORE:
-.endif
- .dw XT_TO_BODY
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/depth.asm b/amforth-6.5/common/words/depth.asm
deleted file mode 100644
index c17d84d..0000000
--- a/amforth-6.5/common/words/depth.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- n )
-; Stack
-; number of single-cell values contained in the data stack before n was placed on the stack.
-.if cpu_msp430==1
- HEADER(XT_DEPTH,5,"depth",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DEPTH:
- .dw $ff05
- .db "depth",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DEPTH
-XT_DEPTH:
- .dw DO_COLON
-PFA_DEPTH:
-.endif
- .dw XT_SP0
- .dw XT_SP_FETCH
- .dw XT_MINUS
- .dw XT_2SLASH
- .dw XT_1MINUS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/digit-q.asm b/amforth-6.5/common/words/digit-q.asm
deleted file mode 100644
index da19b55..0000000
--- a/amforth-6.5/common/words/digit-q.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( c -- (number|) flag )
-; Numeric IO
-; tries to convert a character to a number, set flag accordingly
-
-.if cpu_msp430==1
- HEADER(XT_DIGITQ,6,"digit?",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DIGITQ:
- .dw $ff06
- .db "digit?"
- .dw VE_HEAD
- .set VE_HEAD = VE_DIGITQ
-XT_DIGITQ:
- .dw DO_COLON
-PFA_DIGITQ:
-.endif
- .dw XT_TOUPPER
- .DW XT_DUP,XT_DOLITERAL,57,XT_GREATER,XT_DOLITERAL,256
- .DW XT_AND,XT_PLUS,XT_DUP,XT_DOLITERAL,320,XT_GREATER
- .DW XT_DOLITERAL,263,XT_AND,XT_MINUS,XT_DOLITERAL,48
- .DW XT_MINUS,XT_DUP,XT_BASE,XT_FETCH,XT_ULESS
- .DW XT_EXIT
diff --git a/amforth-6.5/common/words/do-create.asm b/amforth-6.5/common/words/do-create.asm
deleted file mode 100644
index 3f78729..0000000
--- a/amforth-6.5/common/words/do-create.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- ) (C: "<spaces>name" -- )
-; Compiler
-; parse the input and create an empty vocabulary entry without XT and data field (PF)
-
-.if cpu_msp430==1
- HEADER(XT_DOCREATE,8,"(create)",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DOCREATE:
- .dw $ff08
- .db "(create)"
- .dw VE_HEAD
- .set VE_HEAD = VE_DOCREATE
-XT_DOCREATE:
- .dw DO_COLON
-PFA_DOCREATE:
-.endif
- .DW XT_PARSENAME,XT_WLSCOPE ; ( -- addr len wid)
- .DW XT_DUP,XT_NEWEST,XT_CELLPLUS,XT_STORE ; save the wid
- .DW XT_HEADER,XT_NEWEST,XT_STORE ; save the nt
- .DW XT_EXIT
diff --git a/amforth-6.5/common/words/do.asm b/amforth-6.5/common/words/do.asm
deleted file mode 100644
index a289bf8..0000000
--- a/amforth-6.5/common/words/do.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( n1 n2 -- ) (R: -- loop-sys ) (C: -- do-sys )
-; Compiler
-; start do .. [+]loop
-
-.if cpu_msp430==1
- IMMED(XT_DO,2,"do",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DO:
- .dw $0002
- .db "do"
- .dw VE_HEAD
- .set VE_HEAD = VE_DO
-XT_DO:
- .dw DO_COLON
-PFA_DO:
-
-.endif
- .dw XT_COMPILE
- .dw XT_DODO
- .dw XT_LMARK
- .dw XT_ZERO
- .dw XT_TO_L
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/dot-quote.asm b/amforth-6.5/common/words/dot-quote.asm
deleted file mode 100644
index 46efce1..0000000
--- a/amforth-6.5/common/words/dot-quote.asm
+++ /dev/null
@@ -1,31 +0,0 @@
-; ( -- ) (C: "ccc<quote>" -- )
-; Compiler
-; compiles string into dictionary to be printed at runtime
-
-.if cpu_msp430==1
- ; IMMED(DOTQUOTE,2,"."",DOCOLON)
- DW link
- DB 0FEh ; immediate
-.set link = $
- DB 2,'.','"'
- .align 16
-DOTQUOTE: DW DOCOLON
-
-.endif
-
-.if cpu_avr8==1
-
-
-VE_DOTSTRING:
- .dw $0002
- .db ".",$22
- .dw VE_HEAD
- .set VE_HEAD = VE_DOTSTRING
-XT_DOTSTRING:
- .dw DO_COLON
-PFA_DOTSTRING:
-.endif
- .dw XT_SQUOTE
- .dw XT_COMPILE
- .dw XT_ITYPE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/dot-r.asm b/amforth-6.5/common/words/dot-r.asm
deleted file mode 100644
index 5a19168..0000000
--- a/amforth-6.5/common/words/dot-r.asm
+++ /dev/null
@@ -1,32 +0,0 @@
-; ( n w -- )
-; Numeric IO
-; singed PNO with single cell numbers, right aligned in width w
-
-.if cpu_msp430==1
-; HEADER(XT_DOTR,2,"..",DOCOLON)
- DW link
- DB 0FFh
-.set link = $
- DB 2,".",'r'
- .align 16
-XT_DOTR:
- .DW DOCOLON
-.endif
-
-.if cpu_avr8==1
-VE_DOTR:
- .dw $ff02
- .db ".r"
- .dw VE_HEAD
- .set VE_HEAD = VE_DOTR
-XT_DOTR:
- .dw DO_COLON
-PFA_DOTR:
-
-.endif
- .dw XT_TO_R
- .dw XT_S2D
- .dw XT_R_FROM
- .dw XT_DDOTR
- .dw XT_EXIT
-; : .r ( s n -- ) >r s>d r> d.r ;
diff --git a/amforth-6.5/common/words/dot-s.asm b/amforth-6.5/common/words/dot-s.asm
deleted file mode 100644
index b6736a5..0000000
--- a/amforth-6.5/common/words/dot-s.asm
+++ /dev/null
@@ -1,42 +0,0 @@
-; ( -- )
-; Tools
-; stack dump
-
-.if cpu_msp430==1
-; HEADER(XT_DOTS,2,"..",DOCOLON)
- DW link
- DB 0FFh
-.set link = $
- DB 2,".",'s'
- .align 16
-XT_DOTS:
- .DW DOCOLON
-.endif
-
-.if cpu_avr8==1
-VE_DOTS:
- .dw $ff02
- .db ".s"
- .dw VE_HEAD
- .set VE_HEAD = VE_DOTS
-XT_DOTS:
- .dw DO_COLON
-PFA_DOTS:
-.endif
- .dw XT_DEPTH
- .dw XT_UDOT
- .dw XT_SPACE
- .dw XT_DEPTH
- .dw XT_ZERO
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- DEST(PFA_DOTS2)
- .dw XT_DODO
-PFA_DOTS1:
- .dw XT_I
- .dw XT_PICK
- .dw XT_UDOT
- .dw XT_DOLOOP
- DEST(PFA_DOTS1)
-PFA_DOTS2:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/dot.asm b/amforth-6.5/common/words/dot.asm
deleted file mode 100644
index 32ad95f..0000000
--- a/amforth-6.5/common/words/dot.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( n -- )
-; Numeric IO
-; singed PNO with single cell numbers
-
-.if cpu_msp430==1
- HEADER(XT_DOT,1,".",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_DOT:
- .dw $ff01
- .db ".",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DOT
-XT_DOT:
- .dw DO_COLON
-PFA_DOT:
-.endif
- .dw XT_S2D
- .dw XT_DDOT
- .dw XT_EXIT
-; : . ( s -- ) s>d d. ;
diff --git a/amforth-6.5/common/words/dt-null.asm b/amforth-6.5/common/words/dt-null.asm
deleted file mode 100644
index 640562f..0000000
--- a/amforth-6.5/common/words/dt-null.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-; ( -- addr )
-; Interpreter
-; there is no parser for this recognizer, this is the default and failsafe part
-
-.if cpu_msp430==1
- HEADER(XT_DT_NULL,7,"dt:null",DOROM)
-.endif
-
-.if cpu_avr8==1
-VE_DT_NULL:
- .dw $ff07
- .db "dt:null"
- .dw VE_HEAD
- .set VE_HEAD = VE_DT_NULL
-XT_DT_NULL:
- .dw PFA_DOCONSTANT
-PFA_DT_NULL:
-.endif
- .dw XT_FAIL ; interpret
- .dw XT_FAIL ; compile
- .dw XT_FAIL ; postpone
-
-; ( addr len -- )
-; Interpreter
-; default failure action: throw exception -13.
-.if cpu_msp430==1
- HEADLESS(XT_FAIL,DOCOLON)
-.endif
-.if cpu_avr8==1
-;VE_FAIL:
-; .dw $ff04
-; .db "fail"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_FAIL
-XT_FAIL:
- .dw DO_COLON
-PFA_FAIL:
-.endif
- .dw XT_DOLITERAL
- .dw -13
- .dw XT_THROW
diff --git a/amforth-6.5/common/words/else.asm b/amforth-6.5/common/words/else.asm
deleted file mode 100644
index e0e2ff3..0000000
--- a/amforth-6.5/common/words/else.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; (C: orig1 -- orig2 )
-; Compiler
-; resolve the forward reference and place a new unresolved forward reference
-
-.if cpu_msp430==1
- IMMED(XT_ELSE,4,"else",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_ELSE:
- .dw $0004
- .db "else"
- .dw VE_HEAD
- .set VE_HEAD = VE_ELSE
-XT_ELSE:
- .dw DO_COLON
-PFA_ELSE:
-.endif
- .dw XT_COMPILE
- .dw XT_DOBRANCH
- .dw XT_GMARK
- .dw XT_SWAP
- .dw XT_GRESOLVE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/emit.asm b/amforth-6.5/common/words/emit.asm
deleted file mode 100644
index de194c3..0000000
--- a/amforth-6.5/common/words/emit.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( c -- )
-; Character IO
-; fetch the emit vector and execute it. should emit a character from TOS
-
-.if cpu_msp430==1
- DEFER(XT_EMIT,4,"emit")
-.endif
-
-.if cpu_avr8==1
-VE_EMIT:
- .dw $ff04
- .db "emit"
- .dw VE_HEAD
- .set VE_HEAD = VE_EMIT
-XT_EMIT:
- .dw PFA_DODEFER1
-PFA_EMIT:
-.endif
- .dw USER_EMIT
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/emitq.asm b/amforth-6.5/common/words/emitq.asm
deleted file mode 100644
index b1c04f2..0000000
--- a/amforth-6.5/common/words/emitq.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- f )
-; Character IO
-; fetch emit? vector and execute it. should return the ready-to-send condition
-
-.if cpu_msp430==1
- DEFER(XT_EMITQ,5,"emit?")
-.endif
-
-.if cpu_avr8==1
-VE_EMITQ:
- .dw $ff05
- .db "emit?",0
- .dw VE_HEAD
- .set VE_HEAD = VE_EMITQ
-XT_EMITQ:
- .dw PFA_DODEFER1
-PFA_EMITQ:
-.endif
- .dw USER_EMITQ
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/endloop.asm b/amforth-6.5/common/words/endloop.asm
deleted file mode 100644
index 26c9847..0000000
--- a/amforth-6.5/common/words/endloop.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_ENDLOOP,7,"endloop",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_ENDLOOP:
- .dw $ff07
- .db "endloop",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ENDLOOP
-XT_ENDLOOP:
- .dw DO_COLON
-PFA_ENDLOOP:
-.endif
-;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN --
-; <resolve backward loop
-; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT ;
-; resolve LEAVEs
-; This is a common factor of LOOP and +LOOP.
-
- .DW XT_LRESOLVE
-LOOP1: .DW XT_L_FROM,XT_QDUP,XT_DOCONDBRANCH
- DEST(LOOP2)
- .DW XT_THEN
- .dw XT_DOBRANCH
- DEST(LOOP1)
-LOOP2: .DW XT_EXIT
diff --git a/amforth-6.5/common/words/env-cpu.asm b/amforth-6.5/common/words/env-cpu.asm
deleted file mode 100644
index 3266b03..0000000
--- a/amforth-6.5/common/words/env-cpu.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- faddr len )
-; Environment
-; flash address of the CPU identification string
-
-.if cpu_msp430==1
- ENVIRONMENT(XT_ENV_CPU,3,"cpu")
-.endif
-
-.if cpu_avr8==1
-VE_ENV_CPU:
- .dw $ff03
- .db "cpu",0
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_CPU
-XT_ENV_CPU:
- .dw DO_COLON
-PFA_EN_CPU:
-.endif
- .dw XT_DOLITERAL
- .dw mcu_name
- .dw XT_ICOUNT
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/env-forthname.asm b/amforth-6.5/common/words/env-forthname.asm
deleted file mode 100644
index 025f818..0000000
--- a/amforth-6.5/common/words/env-forthname.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( -- faddr len )
-; Environment
-; flash address of the amforth name string
-.if cpu_msp430==1
- ENVIRONMENT(XT_ENV_FORTHNAME,10,"forth-name")
- .dw XT_DOSLITERAL
- .db 7
-.endif
-
-.if cpu_avr8==1
-VE_ENV_FORTHNAME:
- .dw $ff0a
- .db "forth-name"
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHNAME
-XT_ENV_FORTHNAME:
- .dw DO_COLON
-PFA_EN_FORTHNAME:
- .dw XT_DOSLITERAL
- .dw 7
-.endif
- .db "amforth"
-.if cpu_msp430==1
- .align 16
-.endif
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/env-forthversion.asm b/amforth-6.5/common/words/env-forthversion.asm
deleted file mode 100644
index 202e82b..0000000
--- a/amforth-6.5/common/words/env-forthversion.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( -- n )
-; Environment
-; version number of amforth
-.if cpu_msp430==1
- ENVIRONMENT(XT_ENV_FORTHVERSION,7,"version")
-.endif
-
-.if cpu_avr8==1
-VE_ENV_FORTHVERSION:
- .dw $ff07
- .db "version",0
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENV_FORTHVERSION
-XT_ENV_FORTHVERSION:
- .dw DO_COLON
-PFA_EN_FORTHVERSION:
-.endif
- .dw XT_DOLITERAL
- .dw 65
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/env-slashhold.asm b/amforth-6.5/common/words/env-slashhold.asm
deleted file mode 100644
index 9fa9468..0000000
--- a/amforth-6.5/common/words/env-slashhold.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- hldsize )
-; Environment
-; size of the pictured numeric output buffer in bytes
-
-.if cpu_msp430==1
- ENVIRONMENT(XT_ENVSLASHHOLD,5,"/hold",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_ENVSLASHHOLD:
- .dw $ff05
- .db "/hold",0
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVSLASHHOLD
-XT_ENVSLASHHOLD:
- .dw DO_COLON
-PFA_ENVSLASHHOLD:
-.endif
- .dw XT_PAD
- .dw XT_HERE
- .dw XT_MINUS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/env-usersize.asm b/amforth-6.5/common/words/env-usersize.asm
deleted file mode 100644
index 53bd58a..0000000
--- a/amforth-6.5/common/words/env-usersize.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- usersize )
-; Environment
-; size of the USER area in bytes
-.if cpu_msp430==1
- ENVIRONMENT(XT_ENVUSERSIZE,5,"/user")
-.endif
-
-.if cpu_avr8==1
-
-VE_ENVUSERSIZE:
- .dw $ff05
- .db "/user",0
- .dw VE_ENVHEAD
- .set VE_ENVHEAD = VE_ENVUSERSIZE
-XT_ENVUSERSIZE:
- .dw DO_COLON
-PFA_ENVUSERSIZE:
-.endif
- .dw XT_DOLITERAL
- .dw SYSUSERSIZE + APPUSERSIZE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/f_cpu.asm b/amforth-6.5/common/words/f_cpu.asm
deleted file mode 100644
index 3632b0c..0000000
--- a/amforth-6.5/common/words/f_cpu.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- d )
-; System
-; put the cpu frequency in Hz on stack
-.if cpu_msp430==1
- HEADER(XT_F_CPU,5,"f_cpu",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_F_CPU:
- .dw $ff05
- .db "f_cpu",0
- .dw VE_HEAD
- .set VE_HEAD = VE_F_CPU
-XT_F_CPU:
- .dw DO_COLON
-PFA_F_CPU:
-.endif
- .dw XT_DOLITERAL
- .dw (F_CPU % 65536)
- .dw XT_DOLITERAL
- .dw (F_CPU / 65536)
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/find-xt.asm b/amforth-6.5/common/words/find-xt.asm
deleted file mode 100644
index 0ed50b8..0000000
--- a/amforth-6.5/common/words/find-xt.asm
+++ /dev/null
@@ -1,55 +0,0 @@
-; ( c-addr len -- 0 | xt -1 | xt 1 )
-; Tools
-; search wordlists for an entry with the xt from c-addr/len
-
-.if cpu_msp430==1
- HEADER(XT_FINDXT,7,"find-xt",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_FINDXT:
- .dw $ff07
- .db "find-xt",0
- .dw VE_HEAD
- .set VE_HEAD = VE_FINDXT
-XT_FINDXT:
- .dw DO_COLON
-PFA_FINDXT:
-.endif
- .dw XT_DOLITERAL
- .dw XT_FINDXTA
- .dw XT_DOLITERAL
- .dw CFG_ORDERLISTLEN
- .dw XT_MAPSTACK
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_FINDXT1)
- .dw XT_2DROP
- .dw XT_ZERO
-PFA_FINDXT1:
- .dw XT_EXIT
-
-.if cpu_msp430==1
- HEADLESS(XT_FINDXTA,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-XT_FINDXTA:
- .dw DO_COLON
-PFA_FINDXTA:
-.endif
- .dw XT_TO_R
- .dw XT_2DUP
- .dw XT_R_FROM
- .dw XT_SEARCH_WORDLIST
- .dw XT_DUP
- .dw XT_DOCONDBRANCH
- DEST(PFA_FINDXTA1)
- .dw XT_TO_R
- .dw XT_NIP
- .dw XT_NIP
- .dw XT_R_FROM
- .dw XT_TRUE
-PFA_FINDXTA1:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/get-order.asm b/amforth-6.5/common/words/get-order.asm
deleted file mode 100644
index df9ee77..0000000
--- a/amforth-6.5/common/words/get-order.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- wid-n .. wid-1 n)
-; Search Order
-; Get the current search order word list
-
-.if cpu_msp430==1
- HEADER(XT_GET_ORDER,9,"get-order",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_GET_ORDER:
- .dw $ff09
- .db "get-order",0
- .dw VE_HEAD
- .set VE_HEAD = VE_GET_ORDER
-XT_GET_ORDER:
- .dw DO_COLON
-PFA_GET_ORDER:
-.endif
- .dw XT_DOLITERAL
- .dw CFG_ORDERLISTLEN
- .dw XT_GET_STACK
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/get-recognizer.asm b/amforth-6.5/common/words/get-recognizer.asm
deleted file mode 100644
index abfbe07..0000000
--- a/amforth-6.5/common/words/get-recognizer.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- rec-n .. rec-1 n)
-; Interpreter
-; Get the current recognizer list
-
-.if cpu_msp430==1
- HEADER(XT_GET_RECOGNIZERS,15,"get-recognizers",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_GET_RECOGNIZERS:
- .dw $ff0f
- .db "get-recognizers",0
- .dw VE_HEAD
- .set VE_HEAD = VE_GET_RECOGNIZERS
-XT_GET_RECOGNIZERS:
- .dw DO_COLON
-PFA_GET_RECOGNIZERS:
-.endif
- .dw XT_DOLITERAL
- .dw CFG_RECOGNIZERLISTLEN
- .dw XT_GET_STACK
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/get-stack.asm b/amforth-6.5/common/words/get-stack.asm
deleted file mode 100644
index 3127d76..0000000
--- a/amforth-6.5/common/words/get-stack.asm
+++ /dev/null
@@ -1,46 +0,0 @@
-; ( e-addr -- item-n .. item-1 n)
-; Tools
-; Get a stack from EEPROM
-
-.if cpu_msp430==1
- HEADER(XT_GET_STACK,9,"get-stack",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_GET_STACK:
- .dw $ff09
- .db "get-stack",0
- .dw VE_HEAD
- .set VE_HEAD = VE_GET_STACK
-XT_GET_STACK:
- .dw DO_COLON
-.endif
- .dw XT_DUP
- .dw XT_CELLPLUS
- .dw XT_SWAP
- .dw XT_FETCHE
- .dw XT_DUP
- .dw XT_TO_R
- .dw XT_ZERO
- .dw XT_SWAP ; go from bigger to smaller addresses
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- DEST(PFA_N_FETCH_E2)
- .dw XT_DODO
-PFA_N_FETCH_E1:
- ; ( ee-addr )
- .dw XT_I
- .dw XT_1MINUS
- .dw XT_CELLS ; ( -- ee-addr i*2 )
- .dw XT_OVER ; ( -- ee-addr i*2 ee-addr )
- .dw XT_PLUS ; ( -- ee-addr ee-addr+i
- .dw XT_FETCHE ;( -- ee-addr item_i )
- .dw XT_SWAP ;( -- item_i ee-addr )
- .dw XT_TRUE ; shortcut for -1
- .dw XT_DOPLUSLOOP
- DEST(PFA_N_FETCH_E1)
-PFA_N_FETCH_E2:
- .dw XT_2DROP
- .dw XT_R_FROM
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/git-info.tmpl b/amforth-6.5/common/words/git-info.tmpl
deleted file mode 100644
index 2486d16..0000000
--- a/amforth-6.5/common/words/git-info.tmpl
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( -- ) System
-; R( -- )
-; GIT Info
-
-.if cpu_msp430==1
- HEADER(XT_GITINFO,8,"git-info",DOCOLON)
- .dw XT_DOSLITERAL
- .db @BRLEN@
-.endif
-
-.if cpu_avr8==1
-VE_GITINFO:
- .dw $ff08
- .db "git-info"
- .dw VE_HEAD
- .set VE_HEAD = VE_GITINFO
-XT_GITINFO:
- .dw DO_COLON
-PFA_GITINFO:
- .dw XT_DOSLITERAL
- .dw @BRLEN@
-.endif
- .db "@BRNAME@"
-.if cpu_msp430==1
- .align 16
-.endif
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/handler.asm b/amforth-6.5/common/words/handler.asm
deleted file mode 100644
index 61b1c58..0000000
--- a/amforth-6.5/common/words/handler.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- a-addr )
-; Exceptions
-; USER variable used by catch/throw
-
-.if cpu_msp430==1
- HEADER(XT_HANDLER,7,"handler",DOUSER)
-.endif
-
-.if cpu_avr8==1
-VE_HANDLER:
- .dw $ff07
- .db "handler",0
- .dw VE_HEAD
- .set VE_HEAD = VE_HANDLER
-XT_HANDLER:
- .dw PFA_DOUSER
-PFA_HANDLER:
-.endif
- .dw USER_HANDLER
diff --git a/amforth-6.5/common/words/hex.asm b/amforth-6.5/common/words/hex.asm
deleted file mode 100644
index c87fa69..0000000
--- a/amforth-6.5/common/words/hex.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- )
-; Numeric IO
-; set base for numeric conversion to 10
-
-.if cpu_msp430==1
- HEADER(XT_HEX,3,"hex",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_HEX:
- .dw $ff03
- .db "hex",0
- .dw VE_HEAD
- .set VE_HEAD = VE_HEX
-XT_HEX:
- .dw DO_COLON
-PFA_HEX:
-.endif
- .dw XT_DOLITERAL
- .dw 16
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/hold.asm b/amforth-6.5/common/words/hold.asm
deleted file mode 100644
index dda538a..0000000
--- a/amforth-6.5/common/words/hold.asm
+++ /dev/null
@@ -1,29 +0,0 @@
-; ( c -- )
-; Numeric IO
-; prepend character to pictured numeric output buffer
-
-.if cpu_msp430==1
- HEADER(XT_HOLD,4,"hold",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_HOLD:
- .dw $ff04
- .db "hold"
- .dw VE_HEAD
- .set VE_HEAD = VE_HOLD
-XT_HOLD:
- .dw DO_COLON
-PFA_HOLD:
-.endif
- .dw XT_HLD
- .dw XT_DUP
- .dw XT_FETCH
- .dw XT_1MINUS
- .dw XT_DUP
- .dw XT_TO_R
- .dw XT_SWAP
- .dw XT_STORE
- .dw XT_R_FROM
- .dw XT_CSTORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/if.asm b/amforth-6.5/common/words/if.asm
deleted file mode 100644
index a3a0cc8..0000000
--- a/amforth-6.5/common/words/if.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( f -- ) (C: -- orig )
-; Compiler
-; start conditional branch
-
-.if cpu_msp430==1
- IMMED(XT_IF,2,"if",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_IF:
- .dw $0002
- .db "if"
- .dw VE_HEAD
- .set VE_HEAD = VE_IF
-XT_IF:
- .dw DO_COLON
-PFA_IF:
-.endif
- .dw XT_COMPILE
- .dw XT_DOCONDBRANCH
- .dw XT_GMARK
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/interpret.asm b/amforth-6.5/common/words/interpret.asm
deleted file mode 100644
index 37489ae..0000000
--- a/amforth-6.5/common/words/interpret.asm
+++ /dev/null
@@ -1,38 +0,0 @@
-; (i*x - j*x )
-; System
-; Interpret SOURCE word by word.
-
-.if cpu_msp430==1
- HEADER(XT_INTERPRET,9,"interpret",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_INTERPRET:
- .dw $ff09
- .db "interpret",0
- .dw VE_HEAD
- .set VE_HEAD = VE_INTERPRET
-XT_INTERPRET:
- .dw DO_COLON
-.endif
-PFA_INTERPRET:
- .dw XT_PARSENAME ; ( -- addr len )
- .dw XT_DUP ; ( -- addr len flag)
- .dw XT_DOCONDBRANCH
- DEST(PFA_INTERPRET2)
- .dw XT_FORTHRECOGNIZER
- .dw XT_RECOGNIZE
- .dw XT_STATE
- .dw XT_FETCH
- .dw XT_DOCONDBRANCH
- DEST(PFA_INTERPRET1)
- .dw XT_ICELLPLUS ; we need the compile action
-PFA_INTERPRET1:
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_QSTACK
- .dw XT_DOBRANCH
- DEST(PFA_INTERPRET)
-PFA_INTERPRET2:
- .dw XT_2DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/key.asm b/amforth-6.5/common/words/key.asm
deleted file mode 100644
index 06a4b47..0000000
--- a/amforth-6.5/common/words/key.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- c )
-; Character IO
-; fetch key vector and execute it, should leave a single character on TOS
-
-.if cpu_msp430==1
- DEFER(XT_KEY,3,"key")
-.endif
-
-.if cpu_avr8==1
-VE_KEY:
- .dw $ff03
- .db "key",0
- .dw VE_HEAD
- .set VE_HEAD = VE_KEY
-XT_KEY:
- .dw PFA_DODEFER1
-PFA_KEY:
-.endif
- .dw USER_KEY
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/keyq.asm b/amforth-6.5/common/words/keyq.asm
deleted file mode 100644
index 70e8c73..0000000
--- a/amforth-6.5/common/words/keyq.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- f)
-; Character IO
-; fetch key? vector and execute it. should turn on key sender, if it is disabled/stopped
-
-.if cpu_msp430==1
- DEFER(XT_KEYQ,4,"key?")
-.endif
-
-.if cpu_avr8==1
-VE_KEYQ:
- .dw $ff04
- .db "key?"
- .dw VE_HEAD
- .set VE_HEAD = VE_KEYQ
-XT_KEYQ:
- .dw PFA_DODEFER1
-PFA_KEYQ:
-.endif
- .dw USER_KEYQ
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/l-from.asm b/amforth-6.5/common/words/l-from.asm
deleted file mode 100644
index 353fbeb..0000000
--- a/amforth-6.5/common/words/l-from.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_L_FROM,2,"l>",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_L_FROM:
- .dw $ff02
- .db "l>"
- .dw VE_HEAD
- .set VE_HEAD = VE_L_FROM
-XT_L_FROM:
- .dw DO_COLON
-PFA_L_FROM:
-
-.endif
-;Z L> -- x L: x -- move from leave stack
-; LP @ @ -2 LP +! ;
-
- .dw XT_LP
- .dw XT_FETCH
- .dw XT_FETCH
- .dw XT_DOLITERAL
- .dw -2
- .dw XT_LP
- .dw XT_PLUSSTORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/l-paren.asm b/amforth-6.5/common/words/l-paren.asm
deleted file mode 100644
index b1d0ef1..0000000
--- a/amforth-6.5/common/words/l-paren.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( "ccc<paren>" -- )
-; Compiler
-; skip everything up to the closing bracket on the same line
-
-.if cpu_msp430==1
- IMMED(XT_PAREN,1,"(",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_LPAREN:
- .dw $0001
- .db "(" ,0
- .dw VE_HEAD
- .set VE_HEAD = VE_LPAREN
-XT_LPAREN:
- .dw DO_COLON
-PFA_LPAREN:
-.endif
- .dw XT_DOLITERAL
- .dw ')'
- .dw XT_PARSE
- .dw XT_2DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/leave.asm b/amforth-6.5/common/words/leave.asm
deleted file mode 100644
index a7e676c..0000000
--- a/amforth-6.5/common/words/leave.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( -- ) (R: loop-sys -- )
-; Compiler
-; immediatly leave the current DO..LOOP
-
-.if cpu_msp430==1
- IMMED(XT_LEAVE,5,"leave",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_LEAVE:
- .dw $0005
- .db "leave",0
- .dw VE_HEAD
- .set VE_HEAD = VE_LEAVE
-XT_LEAVE:
- .dw DO_COLON
-PFA_LEAVE:
-.endif
- .DW XT_COMPILE,XT_UNLOOP
- .DW XT_AHEAD,XT_TO_L,XT_EXIT
diff --git a/amforth-6.5/common/words/left-bracket.asm b/amforth-6.5/common/words/left-bracket.asm
deleted file mode 100644
index 1957d4f..0000000
--- a/amforth-6.5/common/words/left-bracket.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; Compiler
-; enter interpreter mode
-
-.if cpu_msp430==1
- IMMED(XT_LBRACKET,1,"[",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_LBRACKET:
- .dw $0001
- .db "[",0
- .dw VE_HEAD
- .set VE_HEAD = VE_LBRACKET
-XT_LBRACKET:
- .dw DO_COLON
-PFA_LBRACKET:
-.endif
- .dw XT_ZERO
- .dw XT_STATE
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/less-sharp.asm b/amforth-6.5/common/words/less-sharp.asm
deleted file mode 100644
index 122c246..0000000
--- a/amforth-6.5/common/words/less-sharp.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; Numeric IO
-; initialize the pictured numeric output conversion process
-
-.if cpu_msp430==1
- HEADER(XT_L_SHARP,2,"<#",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_L_SHARP:
- .dw $ff02
- .db "<#"
- .dw VE_HEAD
- .set VE_HEAD = VE_L_SHARP
-XT_L_SHARP:
- .dw DO_COLON
-PFA_L_SHARP:
-.endif
- .dw XT_PAD
- .dw XT_HLD
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/literal.asm b/amforth-6.5/common/words/literal.asm
deleted file mode 100644
index 7d69652..0000000
--- a/amforth-6.5/common/words/literal.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- n ) (C: n -- )
-; Compiler
-; compile a literal in colon defintions
-
-.if cpu_msp430==1
- IMMED(XT_LITERAL,7,"literal",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_LITERAL:
- .dw $0007
- .db "literal",0
- .dw VE_HEAD
- .set VE_HEAD = VE_LITERAL
-XT_LITERAL:
- .dw DO_COLON
-PFA_LITERAL:
-.endif
- .DW XT_COMPILE
- .DW XT_DOLITERAL
- .DW XT_COMMA
- .DW XT_EXIT
diff --git a/amforth-6.5/common/words/loop.asm b/amforth-6.5/common/words/loop.asm
deleted file mode 100644
index 9ffbfac..0000000
--- a/amforth-6.5/common/words/loop.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; (R: loop-sys -- ) (C: do-sys -- )
-; Compiler
-; compile (loop) and resolve the backward branch
-
-.if cpu_msp430==1
- IMMED(XT_LOOP,4,"loop",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_LOOP:
- .dw $0004
- .db "loop"
- .dw VE_HEAD
- .set VE_HEAD = VE_LOOP
-XT_LOOP:
- .dw DO_COLON
-PFA_LOOP:
-.endif
- .dw XT_COMPILE
- .dw XT_DOLOOP
- .dw XT_ENDLOOP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/map-stack.asm b/amforth-6.5/common/words/map-stack.asm
deleted file mode 100644
index 48995a1..0000000
--- a/amforth-6.5/common/words/map-stack.asm
+++ /dev/null
@@ -1,61 +0,0 @@
-; ( i*x XT e-addr -- j*y true | i*x false )
-; Tools
-; Iterate over a stack
-
-.if cpu_msp430==1
- HEADER(XT_MAPSTACK,9,"map-stack",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_MAPSTACK:
- .dw $ff09
- .db "map-stack",0
- .dw VE_HEAD
- .set VE_HEAD = VE_MAPSTACK
-XT_MAPSTACK:
- .dw DO_COLON
-PFA_MAPSTACK:
-.endif
- .dw XT_DUP
- .dw XT_CELLPLUS
- .dw XT_SWAP
- .dw XT_FETCHE
- .dw XT_CELLS
- .dw XT_BOUNDS
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- DEST(PFA_MAPSTACK3)
- .dw XT_DODO
-PFA_MAPSTACK1:
- .dw XT_I
- .dw XT_FETCHE ; -- i*x XT id
- .dw XT_SWAP
- .dw XT_TO_R
- .dw XT_R_FETCH
- .dw XT_EXECUTE ; i*x id -- j*y true | i*x false
- .dw XT_QDUP
- .dw XT_DOCONDBRANCH
- DEST(PFA_MAPSTACK2)
- .dw XT_R_FROM
- .dw XT_DROP
- .dw XT_UNLOOP
- .dw XT_EXIT
-PFA_MAPSTACK2:
- .dw XT_R_FROM
- .dw XT_TWO
- .dw XT_DOPLUSLOOP
- DEST(PFA_MAPSTACK1)
-PFA_MAPSTACK3:
- .dw XT_DROP
- .dw XT_ZERO
- .dw XT_EXIT
-
-;
-; : map-stack ( i*x XT e-addr -- j*y )
-; dup cell+ swap @e cells bounds ?do
-; ( -- i*x XT )
-; i @e swap >r r@ execute
-; ?dup if r> drop unloop exit then
-; r>
-; 2 +loop drop 0
-; ;
diff --git a/amforth-6.5/common/words/max.asm b/amforth-6.5/common/words/max.asm
deleted file mode 100644
index 44cbbad..0000000
--- a/amforth-6.5/common/words/max.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( n1 n2 -- n1|n2 )
-; Compare
-; compare two values, leave the bigger one
-
-.if cpu_msp430==1
- HEADER(XT_MAX,3,"max",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_MAX:
- .dw $ff03
- .db "max",0
- .dw VE_HEAD
- .set VE_HEAD = VE_MAX
-XT_MAX:
- .dw DO_COLON
-PFA_MAX:
-
-.endif
- .dw XT_2DUP
- .dw XT_LESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_MAX1)
- .dw XT_SWAP
-PFA_MAX1:
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/min.asm b/amforth-6.5/common/words/min.asm
deleted file mode 100644
index 59e9965..0000000
--- a/amforth-6.5/common/words/min.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-; ( n1 n2 -- n1|n2 )
-; Compare
-; compare two values leave the smaller one
-
-.if cpu_msp430==1
- HEADER(XT_MIN,3,"min",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_MIN:
- .dw $ff03
- .db "min",0
- .dw VE_HEAD
- .set VE_HEAD = VE_MIN
-XT_MIN:
- .dw DO_COLON
-PFA_MIN:
-.endif
- .dw XT_2DUP
- .dw XT_GREATER
- .dw XT_DOCONDBRANCH
- DEST(PFA_MIN1)
- .dw XT_SWAP
-PFA_MIN1:
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/mod.asm b/amforth-6.5/common/words/mod.asm
deleted file mode 100644
index 1f6cdee..0000000
--- a/amforth-6.5/common/words/mod.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( n1 n2 -- n3)
-; Arithmetics
-; divide n1 by n2 giving the remainder n3
-
-.if cpu_msp430==1
- HEADER(XT_MOD,3,"mod",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_MOD:
- .dw $ff03
- .db "mod",0
- .dw VE_HEAD
- .set VE_HEAD = VE_MOD
-XT_MOD:
- .dw DO_COLON
-PFA_MOD:
-.endif
- .dw XT_SLASHMOD
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/name2compile.asm b/amforth-6.5/common/words/name2compile.asm
deleted file mode 100644
index 129ea0f..0000000
--- a/amforth-6.5/common/words/name2compile.asm
+++ /dev/null
@@ -1,31 +0,0 @@
-; ( nt -- xt1 xt2 )
-; Tools (ext)
-; get the execution token from the name token in compile state
-.if cpu_msp430==1
- HEADER(XT_NAME2COMPILE,12,"name>compile",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_NAME2COMPILE:
- .dw $ff0c
- .db "name>compile"
- .dw VE_HEAD
- .set VE_HEAD = VE_NAME2COMPILE
-XT_NAME2COMPILE:
- .dw DO_COLON
-PFA_NAME2COMPILE:
-.endif
- .dw XT_DUP
- .dw XT_NFA2CFA
- .dw XT_SWAP
- .dw XT_NAME2FLAGS
- .dw XT_IMMEDIATEQ
- .dw XT_DOCONDBRANCH
- DEST(NAME2COMPILE1)
- .dw XT_DOLITERAL
- .dw XT_COMMA
- .dw XT_EXIT
-NAME2COMPILE1:
- .dw XT_DOLITERAL
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/name2interpret.asm b/amforth-6.5/common/words/name2interpret.asm
deleted file mode 100644
index 5a43389..0000000
--- a/amforth-6.5/common/words/name2interpret.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( nt -- xt )
-; Tools (ext)
-; get the execution token from the name token
-.if cpu_msp430==1
- HEADER(XT_NAME2INTERPRET,14,"name>interpret",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_NAME2INTERPRET:
- .dw $ff0e
- .db "name>interpret"
- .dw VE_HEAD
- .set VE_HEAD = VE_NAME2INTERPRET
-XT_NAME2INTERPRET:
- .dw DO_COLON
-PFA_NAME2INTERPRET:
-.endif
- .dw XT_NFA2CFA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/name2string.asm b/amforth-6.5/common/words/name2string.asm
deleted file mode 100644
index 733e143..0000000
--- a/amforth-6.5/common/words/name2string.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( nt -- addr len )
-; Tools Ext (2012)
-; get a (flash) string from a name token nt
-
-.if cpu_msp430==1
- HEADER(XT_NAME2STRING,11,"name>string",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_NAME2STRING:
- .dw $ff0b
- .db "name>string",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NAME2STRING
-XT_NAME2STRING:
- .dw DO_COLON
-PFA_NAME2STRING:
-
-.endif
- .dw XT_ICOUNT ; ( -- addr n )
- .dw XT_DOLITERAL
- .dw 255
- .dw XT_AND ; mask immediate bit
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/noop.asm b/amforth-6.5/common/words/noop.asm
deleted file mode 100644
index 9a99c28..0000000
--- a/amforth-6.5/common/words/noop.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- )
-; Tools
-; do nothing
-
-.if cpu_msp430==1
- HEADER(XT_NOOP,4,"noop",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_NOOP:
- .dw $ff04
- .db "noop"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOOP
-XT_NOOP:
- .dw DO_COLON
-PFA_NOOP:
-.endif
- .DW XT_EXIT
diff --git a/amforth-6.5/common/words/not-equal.asm b/amforth-6.5/common/words/not-equal.asm
deleted file mode 100644
index 2d103ed..0000000
--- a/amforth-6.5/common/words/not-equal.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( n1 n2 -- flag)
-; Compare
-; true if n1 is not equal to n2
-
-.if cpu_msp430==1
- HEADER(XT_NOTEQUAL,2,"<>",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_NOTEQUAL:
- .dw $ff02
- .db "<>"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOTEQUAL
-XT_NOTEQUAL:
- .dw DO_COLON
-PFA_NOTEQUAL:
-.endif
-
- .DW XT_EQUAL,XT_ZEROEQUAL,XT_EXIT
diff --git a/amforth-6.5/common/words/num-constants.asm b/amforth-6.5/common/words/num-constants.asm
deleted file mode 100644
index 88d1449..0000000
--- a/amforth-6.5/common/words/num-constants.asm
+++ /dev/null
@@ -1,51 +0,0 @@
-.if cpu_msp430==1
- HEADER(XT_ZERO,1,"0",DOCON)
- DW 0
-.endif
-
-.if cpu_msp430==1
- HEADER(XT_ONE,1,"1",DOCON)
-.endif
-
-.if cpu_avr8==1
-VE_ONE:
- .dw $ff01
- .db "1",0
- .dw VE_HEAD
- .set VE_HEAD = VE_ONE
-XT_ONE:
- .dw PFA_DOVARIABLE
-PFA_ONE:
-.endif
- .DW 1
-
-.if cpu_msp430==1
- HEADER(XT_TWO,1,"2",DOCON)
-.endif
-
-.if cpu_avr8==1
-VE_TWO:
- .dw $ff01
- .db "2",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TWO
-XT_TWO:
- .dw PFA_DOVARIABLE
-PFA_TWO:
-.endif
- .DW 2
-.if cpu_msp430==1
- HEADER(XT_MINUSONE,2,"-1",DOCON)
-.endif
-
-.if cpu_avr8==1
-VE_MINUSONE:
- .dw $ff02
- .db "-1"
- .dw VE_HEAD
- .set VE_HEAD = VE_MINUSONE
-XT_MINUSONE:
- .dw PFA_DOVARIABLE
-PFA_MINUSONE:
-.endif
- .DW -1
diff --git a/amforth-6.5/common/words/number.asm b/amforth-6.5/common/words/number.asm
deleted file mode 100644
index 0c22655..0000000
--- a/amforth-6.5/common/words/number.asm
+++ /dev/null
@@ -1,101 +0,0 @@
-; (addr len -- [n|d size] f)
-; Numeric IO
-; convert a string at addr to a number
-
-.if cpu_msp430==1
- HEADER(XT_NUMBER,6,"number",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_NUMBER:
- .dw $ff06
- .db "number"
- .dw VE_HEAD
- .set VE_HEAD = VE_NUMBER
-XT_NUMBER:
- .dw DO_COLON
-PFA_NUMBER:
-.endif
- .dw XT_BASE
- .dw XT_FETCH
- .dw XT_TO_R
- .dw XT_QSIGN
- .dw XT_TO_R
- .dw XT_SET_BASE
- .dw XT_QSIGN
- .dw XT_R_FROM
- .dw XT_OR
- .dw XT_TO_R
- ; check whether something is left
- .dw XT_DUP
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBER0)
- ; nothing is left. It cannot be a number at all
- .dw XT_2DROP
- .dw XT_R_FROM
- .dw XT_DROP
- .dw XT_R_FROM
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_ZERO
- .dw XT_EXIT
-PFA_NUMBER0:
- .dw XT_2TO_R
- .dw XT_ZERO ; starting value
- .dw XT_ZERO
- .dw XT_2R_FROM
- .dw XT_TO_NUMBER ; ( 0. addr len -- d addr' len'
- ; check length of the remaining string.
- ; if zero: a single cell number is entered
- .dw XT_QDUP
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBER1)
- ; if equal 1: mayba a trailing dot? --> double cell number
- .dw XT_ONE
- .dw XT_EQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBER2)
- ; excatly one character is left
- .dw XT_CFETCH
- .dw XT_DOLITERAL
- .dw 46 ; .
- .dw XT_EQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBER6)
- ; its a double cell number
- ; incorporate sign into number
- .dw XT_R_FROM
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBER3)
- .dw XT_DNEGATE
-PFA_NUMBER3:
- .dw XT_TWO
- .dw XT_DOBRANCH
- DEST(PFA_NUMBER5)
-PFA_NUMBER2:
- .dw XT_DROP
-PFA_NUMBER6:
- .dw XT_2DROP
- .dw XT_R_FROM
- .dw XT_DROP
- .dw XT_R_FROM
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_ZERO
- .dw XT_EXIT
-PFA_NUMBER1:
- .dw XT_2DROP ; remove the address
- ; incorporate sign into number
- .dw XT_R_FROM
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBER4)
- .dw XT_NEGATE
-PFA_NUMBER4:
- .dw XT_ONE
-PFA_NUMBER5:
- .dw XT_R_FROM
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_TRUE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/pad.asm b/amforth-6.5/common/words/pad.asm
deleted file mode 100644
index 93a2863..0000000
--- a/amforth-6.5/common/words/pad.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- a-addr )
-; System Variable
-; Address of the temporary scratch buffer.
-
-.if cpu_msp430==1
- HEADER(XT_PAD,3,"pad",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_PAD:
- .dw $ff03
- .db "pad",0
- .dw VE_HEAD
- .set VE_HEAD = VE_PAD
-XT_PAD:
- .dw DO_COLON
-PFA_PAD:
-.endif
- .dw XT_HERE
- .dw XT_DOLITERAL
- .dw 40
- .dw XT_PLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/parse-name.asm b/amforth-6.5/common/words/parse-name.asm
deleted file mode 100644
index 3c26396..0000000
--- a/amforth-6.5/common/words/parse-name.asm
+++ /dev/null
@@ -1,60 +0,0 @@
-; ( "<name>" -- c-addr u )
-; String
-; In the SOURCE buffer parse whitespace delimited string. Returns string address within SOURCE.
-
-.if cpu_msp430==1
- HEADER(XT_PARSENAME,10,"parse-name",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-VE_PARSENAME:
- .dw $FF0A
- .db "parse-name"
- .dw VE_HEAD
- .set VE_HEAD = VE_PARSENAME
-XT_PARSENAME:
- .dw DO_COLON
-PFA_PARSENAME:
-.endif
- .dw XT_BL
- .dw XT_SKIPSCANCHAR
- .dw XT_EXIT
-
-; ( c -- addr2 len2 )
-; String
-; skips char and scan what's left in source for char
-.if cpu_msp430==1
- HEADLESS(XT_SKIPSCANCHAR,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-;VE_SKIPSCANCHAR:
-; .dw $FF0A
-; .db "skipscanchar"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_SKIPSCANCHAR
-XT_SKIPSCANCHAR:
- .dw DO_COLON
-PFA_SKIPSCANCHAR:
-.endif
- .dw XT_TO_R
- .dw XT_SOURCE
- .dw XT_TO_IN
- .dw XT_FETCH
- .dw XT_SLASHSTRING
-
- .dw XT_R_FETCH
- .dw XT_CSKIP
- .dw XT_R_FROM
- .dw XT_CSCAN
-
- ; adjust >IN
- .dw XT_2DUP
- .dw XT_PLUS
- .dw XT_SOURCE
- .dw XT_DROP
- .dw XT_MINUS
- .dw XT_TO_IN
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/parse.asm b/amforth-6.5/common/words/parse.asm
deleted file mode 100644
index 0e51c05..0000000
--- a/amforth-6.5/common/words/parse.asm
+++ /dev/null
@@ -1,33 +0,0 @@
-; ( char "ccc<char>" -- c-addr u )
-; String
-; in input buffer parse ccc delimited string by the delimiter char.
-
-.if cpu_msp430==1
- HEADER(XT_PARSE,5,"parse",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_PARSE:
- .dw $ff05
- .db "parse",0
- .dw VE_HEAD
- .set VE_HEAD = VE_PARSE
-XT_PARSE:
- .dw DO_COLON
-PFA_PARSE:
-.endif
- .dw XT_TO_R ; ( -- )
- .dw XT_SOURCE ; ( -- addr len)
- .dw XT_TO_IN ; ( -- addr len >in)
- .dw XT_FETCH
- .dw XT_SLASHSTRING ; ( -- addr' len' )
-
- .dw XT_R_FROM ; ( -- addr' len' c)
- .dw XT_CSCAN ; ( -- addr' len'')
- .dw XT_DUP ; ( -- addr' len'' len'')
- .dw XT_1PLUS
- .dw XT_TO_IN ; ( -- addr' len'' len'' >in)
- .dw XT_PLUSSTORE ; ( -- addr' len')
- .dw XT_ONE
- .dw XT_SLASHSTRING
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/pick.asm b/amforth-6.5/common/words/pick.asm
deleted file mode 100644
index 4e246ea..0000000
--- a/amforth-6.5/common/words/pick.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_PICK,4,"pick",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_PICK:
- .dw $ff04
- .db "pick"
- .dw VE_HEAD
- .set VE_HEAD = VE_PICK
-XT_PICK:
- .dw DO_COLON
-PFA_PICK:
-.endif
- .dw XT_1PLUS
- .dw XT_CELLS
- .dw XT_SP_FETCH
- .dw XT_PLUS
- .dw XT_FETCH
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/place.asm b/amforth-6.5/common/words/place.asm
deleted file mode 100644
index 916b0ae..0000000
--- a/amforth-6.5/common/words/place.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( addr1 len1 addr2 -- )
-; String
-; copy string as counted string
-
-.if cpu_msp430==1
- HEADER(XT_PLACE,5,"place",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_PLACE:
- .dw $ff05
- .db "place",0
- .dw VE_HEAD
- .set VE_HEAD = VE_PLACE
-XT_PLACE:
- .dw DO_COLON
-PFA_PLACE:
-.endif
- .dw XT_2DUP ; ( -- addr1 len1 addr2 len1 addr2)
- .dw XT_CSTORE ; ( -- addr1 len1 addr2)
- .dw XT_1PLUS ; ( -- addr1 len1 addr2')
- .dw XT_SWAP ; ( -- addr1 addr2' len1)
- .dw XT_CMOVE ; ( --- )
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/plusloop.asm b/amforth-6.5/common/words/plusloop.asm
deleted file mode 100644
index df7925c..0000000
--- a/amforth-6.5/common/words/plusloop.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( n -- ) (R: loop-sys -- loop-sys| ) (C: do-sys -- )
-; Compiler
-; compile (+loop) and resolve branches
-
-.if cpu_msp430==1
- IMMED(XT_PLUSLOOP,5,"+loop",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_PLUSLOOP:
- .dw $0005
- .db "+loop",0
- .dw VE_HEAD
- .set VE_HEAD = VE_PLUSLOOP
-XT_PLUSLOOP:
- .dw DO_COLON
-PFA_PLUSLOOP:
-.endif
- .dw XT_COMPILE
- .dw XT_DOPLUSLOOP
- .dw XT_ENDLOOP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/postpone.asm b/amforth-6.5/common/words/postpone.asm
deleted file mode 100644
index 10f36df..0000000
--- a/amforth-6.5/common/words/postpone.asm
+++ /dev/null
@@ -1,32 +0,0 @@
-; ( "<space>name" -- )
-; Compiler
-; Append the compilation semantics of "name" to the dictionary
-
-.if cpu_msp430==1
- IMMED(XT_POSTPONE,8,"postpone",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_POSTPONE:
- .dw $0008
- .db "postpone"
- .dw VE_HEAD
- .set VE_HEAD = VE_POSTPONE
-XT_POSTPONE:
- .dw DO_COLON
-PFA_POSTPONE:
-.endif
- .dw XT_PARSENAME
- .dw XT_FORTHRECOGNIZER
- .dw XT_RECOGNIZE
- .dw XT_DUP
- .dw XT_TO_R
- .dw XT_ICELLPLUS
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_R_FROM
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/prompt-error.asm b/amforth-6.5/common/words/prompt-error.asm
deleted file mode 100644
index 5d94faa..0000000
--- a/amforth-6.5/common/words/prompt-error.asm
+++ /dev/null
@@ -1,64 +0,0 @@
-; ( n -- )
-; System
-; process the error prompt
-
-.if cpu_msp430==1
- HEADLESS(XT_DEFAULT_PROMPTERROR,DOCOLON)
- DW XT_DOSLITERAL
- DB 4," ?? "
- .align 16
-.endif
-
-.if cpu_avr8==1
-;VE_PROMPTERROR:
-; .dw $ff04
-; .db "p_er"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_PROMPTERROR
-XT_DEFAULT_PROMPTERROR:
- .dw DO_COLON
-PFA_DEFAULT_PROMPTERROR:
- .dw XT_DOSLITERAL
- .dw 4
- .db " ?? "
-.endif
- .dw XT_ITYPE
- .dw XT_BASE
- .dw XT_FETCH
- .dw XT_TO_R
- .dw XT_DECIMAL
- .dw XT_DOT
- .dw XT_TO_IN
- .dw XT_FETCH
- .dw XT_DOT
- .dw XT_R_FROM
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_EXIT
-
-; ------------------------
-
-.if cpu_msp430==1
-; DEFER(XT_PROMPTERROR,6,".error")
- DW link
- DB 0FFh
-.set link = $
- DB 6,".","error"
- .align 16
-XT_PROMPTERROR:
- DW DODEFER
-.endif
-
-.if cpu_avr8==1
-VE_PROMPTERROR:
- .dw $FF06
- .db ".error"
- .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTERROR
-XT_PROMPTERROR:
- .dw PFA_DODEFER1
-PFA_PROMPTERROR:
-.endif
- .dw USER_P_ERR
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/prompt-ok.asm b/amforth-6.5/common/words/prompt-ok.asm
deleted file mode 100644
index 6a73974..0000000
--- a/amforth-6.5/common/words/prompt-ok.asm
+++ /dev/null
@@ -1,52 +0,0 @@
-; ( -- )
-; System
-; send the READY prompt to the command line
-
-.if cpu_msp430==1
- HEADLESS(XT_DEFAULT_PROMPTOK,DOCOLON)
- DW XT_DOSLITERAL
- DB 3," ok"
-.endif
-
-.if cpu_avr8==1
-;VE_PROMPTOK:
-; .dw $ff02
-; .db "ok"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_PROMPTOK
-XT_DEFAULT_PROMPTOK:
- .dw DO_COLON
-PFA_DEFAULT_PROMPTOK:
- .dw XT_DOSLITERAL
- .dw 3
- .db " ok",0
-.endif
- .dw XT_ITYPE
- .dw XT_EXIT
-
-; ------------------------
-
-.if cpu_msp430==1
-; DEFER(XT_PROMPTOK,2,"ok")
- DW link
- DB 0FFh
-.set link = $
- DB 3,".","ok"
- .align 16
-XT_PROMPTOK:
- DW DODEFER
-.endif
-
-.if cpu_avr8==1
-VE_PROMPTOK:
- .dw $FF03
- .db ".ok"
- .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTOK
-XT_PROMPTOK:
- .dw PFA_DODEFER1
-PFA_PROMPTOK:
-.endif
- .dw USER_P_OK
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/prompt-ready.asm b/amforth-6.5/common/words/prompt-ready.asm
deleted file mode 100644
index ad5915c..0000000
--- a/amforth-6.5/common/words/prompt-ready.asm
+++ /dev/null
@@ -1,54 +0,0 @@
-; ( n -- )
-; System
-; process the error prompt
-
-.if cpu_msp430==1
- HEADLESS(XT_DEFAULT_PROMPTREADY,DOCOLON)
- DW XT_DOSLITERAL
- DB 2,"> "
- .align 16
-.endif
-
-.if cpu_avr8==1
-;VE_PROMPTRDY:
-; .dw $ff04
-; .db "p_er"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_PROMPTRDY
-XT_DEFAULT_PROMPTREADY:
- .dw DO_COLON
-PFA_DEFAULT_PROMPTREADY:
- .dw XT_DOSLITERAL
- .dw 2
- .db "> "
-.endif
- .dw XT_CR
- .dw XT_ITYPE
- .dw XT_EXIT
-
-; ------------------------
-
-.if cpu_msp430==1
-; DEFER(XT_PROMPTREADY,6,".ready")
- DW link
- DB 0FFh
-.set link = $
- DB 6,".","ready"
- .align 16
-XT_PROMPTREADY:
- DW DODEFER
-.endif
-
-.if cpu_avr8==1
-VE_PROMPTREADY:
- .dw $FF06
- .db ".ready"
- .dw VE_HEAD
- .set VE_HEAD = VE_PROMPTREADY
-XT_PROMPTREADY:
- .dw PFA_DODEFER1
-PFA_PROMPTREADY:
-.endif
- .dw USER_P_RDY
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/q-abort.asm b/amforth-6.5/common/words/q-abort.asm
deleted file mode 100644
index 89f25bf..0000000
--- a/amforth-6.5/common/words/q-abort.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-;Z ?ABORT f c-addr u -- abort & print msg
-; ROT IF ITYPE ABORT THEN 2DROP ;
-
-.if cpu_msp430==1
- HEADER(XT_QABORT,6,"?abort",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_QABORT:
- .dw $ff06
- .db "?abort"
- .dw VE_HEAD
- .set VE_HEAD = VE_QABORT
-XT_QABORT:
- .dw DO_COLON
-PFA_QABORT:
-
-.endif
- .DW XT_ROT,XT_DOCONDBRANCH
- DEST(QABO1)
- .DW XT_ITYPE,XT_ABORT
-QABO1: .DW XT_2DROP,XT_EXIT
diff --git a/amforth-6.5/common/words/q-dnegate.asm b/amforth-6.5/common/words/q-dnegate.asm
deleted file mode 100644
index a9938c6..0000000
--- a/amforth-6.5/common/words/q-dnegate.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-;Z ?DNEGATE d1 n -- d2 negate d1 if n negative
-; 0< IF DNEGATE THEN ; ...a common factor
-
-.if cpu_msp430==1
- HEADER(XT_QDNEGATE,8,"?dnegate",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_QDNEGATE:
- .dw $ff08
- .db "?dnegate"
- .dw VE_HEAD
- .set VE_HEAD = VE_QDNEGATE
-XT_QDNEGATE:
- .dw DO_COLON
-PFA_QDNEGATE:
-.endif
- .DW XT_ZEROLESS,XT_DOCONDBRANCH
- DEST(DNEG1)
- .DW XT_DNEGATE
-DNEG1: .DW XT_EXIT
diff --git a/amforth-6.5/common/words/q-negate.asm b/amforth-6.5/common/words/q-negate.asm
deleted file mode 100644
index b6fe534..0000000
--- a/amforth-6.5/common/words/q-negate.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-;Z ?NEGATE n1 n2 -- n3 negate n1 if n2 negative
-; 0< IF NEGATE THEN ; ...a common factor
-
-.if cpu_msp430==1
- HEADER(XT_QNEGATE,7,"?negate",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_QNEGATE:
- .dw $ff07
- .db "?negate"
- .dw VE_HEAD
- .set VE_HEAD = VE_QNEGATE
-XT_QNEGATE:
- .dw DO_COLON
-PFA_QNEGATE:
-
-.endif
- .DW XT_ZEROLESS,XT_DOCONDBRANCH
- DEST(QNEG1)
- .DW XT_NEGATE
-QNEG1: .DW XT_EXIT
diff --git a/amforth-6.5/common/words/q-sign.asm b/amforth-6.5/common/words/q-sign.asm
deleted file mode 100644
index 8f0422b..0000000
--- a/amforth-6.5/common/words/q-sign.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-
-.if cpu_msp430==1
- HEADLESS(XT_QSIGN,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-XT_QSIGN:
- .dw DO_COLON
-PFA_QSIGN: ; ( c -- )
-.endif
- .dw XT_OVER ; ( -- addr len addr )
- .dw XT_CFETCH
- .dw XT_DOLITERAL
- .dw '-'
- .dw XT_EQUAL ; ( -- addr len flag )
- .dw XT_DUP
- .dw XT_TO_R
- .dw XT_DOCONDBRANCH
- DEST(PFA_NUMBERSIGN_DONE)
- .dw XT_ONE ; skip sign character
- .dw XT_SLASHSTRING
-PFA_NUMBERSIGN_DONE:
- .dw XT_R_FROM
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/q-stack.asm b/amforth-6.5/common/words/q-stack.asm
deleted file mode 100644
index f652bb2..0000000
--- a/amforth-6.5/common/words/q-stack.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( -- )
-; Tools
-; check data stack depth and exit to quit if underrun
-.if cpu_msp430==1
- HEADER(XT_QSTACK,6,"?stack",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_QSTACK:
- .dw $ff06
- .db "?stack"
- .dw VE_HEAD
- .set VE_HEAD = VE_QSTACK
-XT_QSTACK:
- .dw DO_COLON
-PFA_QSTACK:
-.endif
- .dw XT_DEPTH
- .dw XT_ZEROLESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_QSTACK1)
- .dw XT_DOLITERAL
- .dw -4
- .dw XT_THROW
-PFA_QSTACK1:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/qdo.asm b/amforth-6.5/common/words/qdo.asm
deleted file mode 100644
index 491d06c..0000000
--- a/amforth-6.5/common/words/qdo.asm
+++ /dev/null
@@ -1,54 +0,0 @@
-; ( n1|u1 n2|u2 -- ) R( -- | loop-sys ) (C: -- do-sys)
-; Compiler
-; start a ?do .. [+]loop control structure
-
-.if cpu_msp430==1
- IMMED(XT_QDO,3,"?do",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-VE_QDO:
- .dw $0003
- .db "?do",0
- .dw VE_HEAD
- .set VE_HEAD = VE_QDO
-XT_QDO:
- .dw DO_COLON
-PFA_QDO:
-.endif
- .dw XT_COMPILE
- .dw XT_QDOCHECK
- .dw XT_IF
- .dw XT_DO
- .dw XT_SWAP ; DO sets a 0 marker on the leave stack
- .dw XT_TO_L ; then follows at the end.
- .dw XT_EXIT
-
-; there is no special runtime for ?do, the do runtime
-; gets wrapped with the sequence
-; ... ?do-check if do ..... loop then
-; with
-; : ?do-check ( n1 n2 -- n1 n2 true | false )
-; 2dup = dup >r if 2drop then r> invert ;
-
-.if cpu_msp430==1
- HEADLESS(XT_QDOCHECK,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-XT_QDOCHECK:
- .dw DO_COLON
-PFA_QDOCHECK:
-.endif
- .dw XT_2DUP
- .dw XT_EQUAL
- .dw XT_DUP
- .dw XT_TO_R
- .dw XT_DOCONDBRANCH
- DEST(PFA_QDOCHECK1)
- .dw XT_2DROP
-PFA_QDOCHECK1:
- .dw XT_R_FROM
- .dw XT_INVERT
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/quit.asm b/amforth-6.5/common/words/quit.asm
deleted file mode 100644
index 2a30e4c..0000000
--- a/amforth-6.5/common/words/quit.asm
+++ /dev/null
@@ -1,58 +0,0 @@
-; ( -- )
-; System
-; main loop of amforth. accept - interpret in an endless loop
-
-.if cpu_msp430==1
- HEADER(XT_QUIT,4,"quit",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_QUIT:
- .dw $ff04
- .db "quit"
- .dw VE_HEAD
- .set VE_HEAD = VE_QUIT
-XT_QUIT:
- .dw DO_COLON
-.endif
-PFA_QUIT:
- .dw XT_LP0,XT_LP,XT_STORE
- .dw XT_SP0
- .dw XT_SP_STORE
- .dw XT_RP0
- .dw XT_RP_STORE
- .dw XT_LBRACKET
-
-PFA_QUIT2:
- .dw XT_STATE
- .dw XT_FETCH
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_QUIT4)
- .dw XT_PROMPTREADY
-PFA_QUIT4:
- .dw XT_REFILL
- .dw XT_DOCONDBRANCH
- DEST(PFA_QUIT3)
- .dw XT_DOLITERAL
- .dw XT_INTERPRET
- .dw XT_CATCH
- .dw XT_QDUP
- .dw XT_DOCONDBRANCH
- DEST(PFA_QUIT3)
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw -2
- .dw XT_LESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_QUIT5)
- .dw XT_PROMPTERROR
-PFA_QUIT5:
- .dw XT_DOBRANCH
- DEST(PFA_QUIT)
-PFA_QUIT3:
- .dw XT_PROMPTOK
- .dw XT_DOBRANCH
- DEST(PFA_QUIT2)
-; .dw XT_EXIT ; never reached
-
diff --git a/amforth-6.5/common/words/rdefer-fetch.asm b/amforth-6.5/common/words/rdefer-fetch.asm
deleted file mode 100644
index 0424bd8..0000000
--- a/amforth-6.5/common/words/rdefer-fetch.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( xt1 -- xt2 )
-; System
-; The defer@ for ram defers
-.if cpu_msp430==1
- HEADER(XT_RDEFERFETCH,7,"Rdefer@",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_RDEFERFETCH:
- .dw $ff07
- .db "Rdefer@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERFETCH
-XT_RDEFERFETCH:
- .dw DO_COLON
-PFA_RDEFERFETCH:
-.endif
- .dw XT_FETCHI
- .dw XT_FETCH
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/rdefer-store.asm b/amforth-6.5/common/words/rdefer-store.asm
deleted file mode 100644
index 906ca15..0000000
--- a/amforth-6.5/common/words/rdefer-store.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( xt1 xt2 -- )
-; System
-; The defer! for ram defers
-.if cpu_msp430==1
- HEADER(XT_RDEFERSTORE,7,"Rdefer!",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_RDEFERSTORE:
- .dw $ff07
- .db "Rdefer!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RDEFERSTORE
-XT_RDEFERSTORE:
- .dw DO_COLON
-PFA_RDEFERSTORE:
-.endif
- .dw XT_FETCHI
- .dw XT_STORE
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/rec-find.asm b/amforth-6.5/common/words/rec-find.asm
deleted file mode 100644
index 01a2aa1..0000000
--- a/amforth-6.5/common/words/rec-find.asm
+++ /dev/null
@@ -1,85 +0,0 @@
-; ( addr len -- xt flags dt:xt | dt:null )
-; Interpreter
-; search for a word
-.if cpu_msp430==1
- HEADER(XT_REC_FIND,8,"rec:find",DOCOLON)
-.endif
-.if cpu_avr8==1
-VE_REC_FIND:
- .dw $ff08
- .db "rec:find"
- .dw VE_HEAD
- .set VE_HEAD = VE_REC_FIND
-XT_REC_FIND:
- .dw DO_COLON
-PFA_REC_FIND:
-.endif
- .DW XT_FINDXT
- .dw XT_DUP
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_REC_WORD_FOUND)
- .dw XT_DROP
- .dw XT_DT_NULL
- .dw XT_EXIT
-PFA_REC_WORD_FOUND:
- .dw XT_DT_XT
-
- .dw XT_EXIT
-
-; ( -- addr )
-; Interpreter
-; actions to handle execution tokens and their flags
-.if cpu_msp430==1
- HEADER(XT_DT_XT,6,"dt:xt",DOROM)
-.endif
-
-.if cpu_avr8==1
-VE_DT_XT:
- .dw $ff05
- .db "dt:xt",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DT_XT
-XT_DT_XT:
- .dw PFA_DOCONSTANT
-PFA_DT_XT:
-.endif
- .dw XT_R_WORD_INTERPRET
- .dw XT_R_WORD_COMPILE
- .dw XT_2LITERAL
-
-; ( XT flags -- )
-; Interpreter
-; interpret method for WORD recognizer
-.if cpu_msp430==1
- HEADLESS(XT_R_WORD_INTERPRET,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-XT_R_WORD_INTERPRET:
- .dw DO_COLON
-PFA_R_WORD_INTERPRET:
-.endif
- .dw XT_DROP ; the flags are in the way
- .dw XT_EXECUTE
- .dw XT_EXIT
-
-; ( XT flags -- )
-; Interpreter
-; Compile method for WORD recognizer
-.if cpu_msp430==1
- HEADLESS(XT_R_WORD_COMPILE,DOCOLON)
-.endif
-.if cpu_avr8==1
-XT_R_WORD_COMPILE:
- .dw DO_COLON
-PFA_R_WORD_COMPILE:
-.endif
- .dw XT_ZEROLESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_R_WORD_COMPILE1)
- .dw XT_COMMA
- .dw XT_EXIT
-PFA_R_WORD_COMPILE1:
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/rec-intnum.asm b/amforth-6.5/common/words/rec-intnum.asm
deleted file mode 100644
index 15400e1..0000000
--- a/amforth-6.5/common/words/rec-intnum.asm
+++ /dev/null
@@ -1,76 +0,0 @@
-; ( -- addr )
-; Interpreter
-; Method table for single cell integers
-.if cpu_msp430==1
- HEADER(XT_DT_NUM,6,"dt:num",DOROM)
-.endif
-
-.if cpu_avr8==1
-VE_DT_NUM:
- .dw $ff06
- .db "dt:num"
- .dw VE_HEAD
- .set VE_HEAD = VE_DT_NUM
-XT_DT_NUM:
- .dw PFA_DOCONSTANT
-PFA_DT_NUM:
-.endif
- .dw XT_NOOP ; interpret
- .dw XT_LITERAL ; compile
- .dw XT_LITERAL ; postpone
-
-; ( -- addr )
-; Interpreter
-; Method table for double cell integers
-.if cpu_msp430==1
- HEADER(XT_DT_DNUM,7,"dt:dnum",DOROM)
-.endif
-
-.if cpu_avr8==1
-VE_DT_DNUM:
- .dw $ff07
- .db "dt:dnum",0
- .dw VE_HEAD
- .set VE_HEAD = VE_DT_DNUM
-XT_DT_DNUM:
- .dw PFA_DOCONSTANT
-PFA_DT_DNUM:
-.endif
- .dw XT_NOOP ; interpret
- .dw XT_2LITERAL ; compile
- .dw XT_2LITERAL ; postpone
-
-; ( addr len -- f )
-; Interpreter
-; recognizer for integer numbers
-.if cpu_msp430==1
- HEADER(XT_REC_NUM,7,"rec:num",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-VE_REC_NUM:
- .dw $ff07
- .db "rec:num",0
- .dw VE_HEAD
- .set VE_HEAD = VE_REC_NUM
-XT_REC_NUM:
- .dw DO_COLON
-PFA_REC_NUM:
-.endif
- ; try converting to a number
- .dw XT_NUMBER
- .dw XT_DOCONDBRANCH
- DEST(PFA_REC_NONUMBER)
- .dw XT_ONE
- .dw XT_EQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_REC_INTNUM2)
- .dw XT_DT_NUM
- .dw XT_EXIT
-PFA_REC_INTNUM2:
- .dw XT_DT_DNUM
- .dw XT_EXIT
-PFA_REC_NONUMBER:
- .dw XT_DT_NULL
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/recognize.asm b/amforth-6.5/common/words/recognize.asm
deleted file mode 100644
index 2dc9690..0000000
--- a/amforth-6.5/common/words/recognize.asm
+++ /dev/null
@@ -1,73 +0,0 @@
-; (addr len recstack -- i*x dt:token | dt:null )
-; System
-; walk the recognizer stack
-
-.if cpu_msp430==1
- HEADER(XT_RECOGNIZE,9,"recognize",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_RECOGNIZE:
- .dw $ff09
- .db "recognize",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RECOGNIZE
-XT_RECOGNIZE:
- .dw DO_COLON
-PFA_RECOGNIZE:
-.endif
- .dw XT_DOLITERAL
- .dw XT_RECOGNIZE_A
- .dw XT_SWAP
- .dw XT_MAPSTACK
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_RECOGNIZE1)
- .dw XT_2DROP
- .dw XT_DT_NULL
-PFA_RECOGNIZE1:
- .dw XT_EXIT
-
-.if cpu_msp430==1
- HEADLESS(XT_RECOGNIZE_A,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-; ( addr len XT -- addr len [ dt:xt -1 | 0 ] )
-XT_RECOGNIZE_A:
- .dw DO_COLON
-PFA_RECOGNIZE_A:
-.endif
- .dw XT_ROT ; -- len xt addr
- .dw XT_ROT ; -- xt addr len
- .dw XT_2DUP
- .dw XT_2TO_R
- .dw XT_ROT ; -- addr len xt
- .dw XT_EXECUTE ; -- i*x dt:* | dt:null
- .dw XT_2R_FROM
- .dw XT_ROT
- .dw XT_DUP
- .dw XT_DT_NULL
- .dw XT_EQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_RECOGNIZE_A1)
- .dw XT_DROP
- .dw XT_ZERO
- .dw XT_EXIT
-PFA_RECOGNIZE_A1:
- .dw XT_NIP
- .dw XT_NIP
- .dw XT_TRUE
- .dw XT_EXIT
-
-; : recognize ( addr len stack-id -- i*x dt:* | dt:null )
-; [: ( addr len -- addr len 0 | i*x dt:* -1 )
-; rot rot 2dup 2>r rot execute 2r> rot
-; dup dt:null = ( -- addr len dt:* f )
-; if drop 0 else nip nip -1 then
-; ;]
-; map-stack ( -- i*x addr len dt:* f )
-; 0= if \ a recognizer did the job, remove addr/len
-; 2drop dt:null
-; then ;
-;
diff --git a/amforth-6.5/common/words/recurse.asm b/amforth-6.5/common/words/recurse.asm
deleted file mode 100644
index c1f0114..0000000
--- a/amforth-6.5/common/words/recurse.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; Compiler
-; compile the XT of the word currently being defined into the dictionary
-
-.if cpu_msp430==1
- IMMED(RECURSE,7,"recurse",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_RECURSE:
- .dw $0007
- .db "recurse",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RECURSE
-XT_RECURSE:
- .dw DO_COLON
-PFA_RECURSE:
-.endif
- .dw XT_LATEST
- .dw XT_FETCH
- .dw XT_COMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/refill.asm b/amforth-6.5/common/words/refill.asm
deleted file mode 100644
index a7c918d..0000000
--- a/amforth-6.5/common/words/refill.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- f )
-; System
-; refills the input buffer
-
-.if cpu_msp430==1
- DEFER(XT_REFILL,6,"refill")
-.endif
-
-.if cpu_avr8==1
-VE_REFILL:
- .dw $ff06
- .db "refill"
- .dw VE_HEAD
- .set VE_HEAD = VE_REFILL
-XT_REFILL:
- .dw PFA_DODEFER1
-PFA_REFILL:
-.endif
- .dw USER_REFILL
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
diff --git a/amforth-6.5/common/words/repeat.asm b/amforth-6.5/common/words/repeat.asm
deleted file mode 100644
index 9ee9b09..0000000
--- a/amforth-6.5/common/words/repeat.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- ) (C: orig dest -- )
-; Compiler
-; continue execution at dest, resolve orig
-
-.if cpu_msp430==1
- IMMED(XT_REPEAT,6,"repeat",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_REPEAT:
- .dw $0006
- .db "repeat"
- .dw VE_HEAD
- .set VE_HEAD = VE_REPEAT
-XT_REPEAT:
- .dw DO_COLON
-PFA_REPEAT:
-.endif
- .dw XT_AGAIN
- .dw XT_THEN
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/reveal.asm b/amforth-6.5/common/words/reveal.asm
deleted file mode 100644
index b0b4931..0000000
--- a/amforth-6.5/common/words/reveal.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- )
-; Dictionary
-; makes an entry in a wordlist visible, if not already done.
-
-.if cpu_msp430==1
- HEADER(XT_REVEAL,6,"reveal",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_REVEAL:
- .dw $ff06
- .db "reveal"
- .dw VE_HEAD
- .set VE_HEAD = VE_REVEAL
-XT_REVEAL:
- .dw DO_COLON
-PFA_REVEAL:
-.endif
- .DW XT_NEWEST,XT_CELLPLUS,XT_FETCH ; only if wordlist is in use
- .DW XT_QDUP,XT_DOCONDBRANCH
- DEST(REVEAL1)
- .DW XT_NEWEST,XT_FETCH,XT_SWAP,XT_STOREE
-; .DW XT_ZERO,XT_NEWEST,XT_CELLPLUS,XT_STORE ; clean wordlist entry
-REVEAL1:
- .DW XT_EXIT
diff --git a/amforth-6.5/common/words/right-bracket.asm b/amforth-6.5/common/words/right-bracket.asm
deleted file mode 100644
index 85dbd6a..0000000
--- a/amforth-6.5/common/words/right-bracket.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; Compiler
-; enter compiler mode
-
-.if cpu_msp430==1
- HEADER(XT_RBRACKET,1,"]",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_RBRACKET:
- .dw $ff01
- .db "]",0
- .dw VE_HEAD
- .set VE_HEAD = VE_RBRACKET
-XT_RBRACKET:
- .dw DO_COLON
-PFA_RBRACKET:
-.endif
- .dw XT_ONE
- .dw XT_STATE
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/s-to-d.asm b/amforth-6.5/common/words/s-to-d.asm
deleted file mode 100644
index 374cc6a..0000000
--- a/amforth-6.5/common/words/s-to-d.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( n1 -- d1 )
-; Conversion
-; extend (signed) single cell value to double cell
-.if cpu_msp430==1
- HEADER(XT_S2D,3,"s>d",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_S2D:
- .dw $ff03
- .db "s>d",0
- .dw VE_HEAD
- .set VE_HEAD = VE_S2D
-XT_S2D:
- .dw DO_COLON
-PFA_S2D:
-.endif
- .dw XT_DUP
- .dw XT_ZEROLESS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/search-wordlist.asm b/amforth-6.5/common/words/search-wordlist.asm
deleted file mode 100644
index 3d82de4..0000000
--- a/amforth-6.5/common/words/search-wordlist.asm
+++ /dev/null
@@ -1,72 +0,0 @@
-; ( c-addr len wid -- [ 0 ] | [ xt [-1|1]] )
-; Search Order
-; searches the word list wid for the word at c-addr/len
-
-.if cpu_msp430==1
- HEADER(XT_SEARCH_WORDLIST,15,"search-wordlist",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SEARCH_WORDLIST:
- .dw $ff0f
- .db "search-wordlist",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SEARCH_WORDLIST
-XT_SEARCH_WORDLIST:
- .dw DO_COLON
-PFA_SEARCH_WORDLIST:
-.endif
- .dw XT_TO_R
- .dw XT_ZERO
- .dw XT_DOLITERAL
- .dw XT_ISWORD
- .dw XT_R_FROM
- .dw XT_TRAVERSEWORDLIST
- .dw XT_DUP
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_SEARCH_WORDLIST1)
- .dw XT_2DROP
- .dw XT_DROP
- .dw XT_ZERO
- .dw XT_EXIT
-PFA_SEARCH_WORDLIST1:
- ; ... get the XT ...
- .dw XT_DUP
- .dw XT_NFA2CFA
- ; .. and get the header flag
- .dw XT_SWAP
- .dw XT_NAME2FLAGS
- .dw XT_IMMEDIATEQ
- .dw XT_EXIT
-
-.if cpu_msp430==1
- HEADLESS(XT_ISWORD,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-XT_ISWORD:
- .dw DO_COLON
-PFA_ISWORD:
-.endif
- ; ( c-addr len 0 nt -- c-addr len 0 true| nt false )
- .dw XT_TO_R
- .dw XT_DROP
- .dw XT_2DUP
- .dw XT_R_FETCH ; -- addr len addr len nt
- .dw XT_NAME2STRING
- .dw XT_ICOMPARE ; (-- addr len f )
- .dw XT_DOCONDBRANCH
- DEST(PFA_ISWORD3)
- ; not now
- .dw XT_R_FROM
- .dw XT_DROP
- .dw XT_ZERO
- .dw XT_TRUE ; maybe next word
- .dw XT_EXIT
-PFA_ISWORD3:
- ; we found the word, now clean up iteration data ...
- .dw XT_2DROP
- .dw XT_R_FROM
- .dw XT_ZERO ; finish traverse-wordlist
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/semicolon.asm b/amforth-6.5/common/words/semicolon.asm
deleted file mode 100644
index 35c3a17..0000000
--- a/amforth-6.5/common/words/semicolon.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- )
-; Compiler
-; finish colon defintion, compiles (exit) and returns to interpret state
-
-.if cpu_msp430==1
- IMMED(XT_SEMICOLON,1,";",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_SEMICOLON:
- .dw $0001
- .db $3b,0
- .dw VE_HEAD
- .set VE_HEAD = VE_SEMICOLON
-XT_SEMICOLON:
- .dw DO_COLON
-PFA_SEMICOLON:
-.endif
- .dw XT_COMPILE
- .dw XT_EXIT
- .dw XT_LBRACKET
- .dw XT_REVEAL
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/set-base.asm b/amforth-6.5/common/words/set-base.asm
deleted file mode 100644
index 8e9c10b..0000000
--- a/amforth-6.5/common/words/set-base.asm
+++ /dev/null
@@ -1,58 +0,0 @@
-; ( addr len -- addr' len' )
-; Numeric IO
-; skip a numeric prefix character
-
-.if cpu_msp430==1
- HEADLESS(XT_BASES,DOROM)
-.endif
-
-.if cpu_avr8==1
-XT_BASES:
- .dw PFA_DOCONSTANT
-.endif
- .dw 10,16,2,10 ; last one could a 8 instead.
-
-.if cpu_msp430==1
- HEADLESS(XT_SET_BASE,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-XT_SET_BASE:
- .dw DO_COLON
-PFA_SET_BASE: ; ( adr1 len1 -- adr2 len2 )
-.endif
- .dw XT_OVER
- .dw XT_CFETCH
- .dw XT_DOLITERAL
- .dw 35
- .dw XT_MINUS
- .dw XT_DUP
- .dw XT_ZERO
- .dw XT_DOLITERAL
- .dw 4
- .dw XT_WITHIN
- .dw XT_DOCONDBRANCH
- DEST(SET_BASE1)
- .if cpu_msp430==1
- .dw XT_CELLS
- .endif
- .dw XT_BASES
- .dw XT_PLUS
- .dw XT_FETCHI
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_ONE
- .dw XT_SLASHSTRING
- .dw XT_DOBRANCH
- DEST(SET_BASE2)
-SET_BASE1:
- .dw XT_DROP
-SET_BASE2:
- .dw XT_EXIT
-
-; create bases 10 , 16 , 2 , 8 ,
-; : set-base 35 - dup 0 4 within if
-; bases + @i base ! 1 /string
-; else
-; drop
-; then ;
diff --git a/amforth-6.5/common/words/set-order.asm b/amforth-6.5/common/words/set-order.asm
deleted file mode 100644
index f9b0439..0000000
--- a/amforth-6.5/common/words/set-order.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( widn .. wid-1 n -- )
-; Search Order
-; replace the search order list
-
-.if cpu_msp430==1
- HEADER(XT_SET_ORDER,9,"set-order",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SET_ORDER:
- .dw $ff09
- .db "set-order",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SET_ORDER
-XT_SET_ORDER:
- .dw DO_COLON
-PFA_SET_ORDER:
-.endif
- .dw XT_DOLITERAL
- .dw CFG_ORDERLISTLEN
- .dw XT_SET_STACK
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/set-recognizer.asm b/amforth-6.5/common/words/set-recognizer.asm
deleted file mode 100644
index 7d9dc1c..0000000
--- a/amforth-6.5/common/words/set-recognizer.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( rec-n .. rec-1 n -- )
-; Interpreter
-; replace the recognizer list
-
-.if cpu_msp430==1
- HEADER(XT_SET_RECOGNIZERS,15,"set-recognizers",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SET_RECOGNIZERS:
- .dw $ff0f
- .db "set-recognizers",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SET_RECOGNIZERS
-XT_SET_RECOGNIZERS:
- .dw DO_COLON
-PFA_SET_RECOGNIZERS:
-.endif
- .dw XT_DOLITERAL
- .dw CFG_RECOGNIZERLISTLEN
- .dw XT_SET_STACK
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/set-stack.asm b/amforth-6.5/common/words/set-stack.asm
deleted file mode 100644
index 9c95a0b..0000000
--- a/amforth-6.5/common/words/set-stack.asm
+++ /dev/null
@@ -1,43 +0,0 @@
-; ( rec-n .. rec-1 n ee-addr -- )
-; Tools
-; Write a stack to EEPROM
-.if cpu_msp430==1
- HEADER(XT_SET_STACK,9,"set-stack",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SET_STACK:
- .dw $ff09
- .db "set-stack",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SET_STACK
-XT_SET_STACK:
- .dw DO_COLON
-PFA_SET_STACK:
-.endif
- .dw XT_OVER
- .dw XT_ZEROLESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_SET_STACK0)
- .dw XT_DOLITERAL
- .dw -4
- .dw XT_THROW
-PFA_SET_STACK0:
- .dw XT_2DUP
- .dw XT_STOREE ; ( -- i_n .. i_0 n e-addr )
- .dw XT_SWAP
- .dw XT_ZERO
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- DEST(PFA_SET_STACK2)
- .dw XT_DODO
-PFA_SET_STACK1:
- .dw XT_CELLPLUS ; ( -- i_x e-addr )
- .dw XT_TUCK ; ( -- e-addr i_x e-addr
- .dw XT_STOREE
- .dw XT_DOLOOP
- DEST(PFA_SET_STACK1)
-PFA_SET_STACK2:
- .dw XT_DROP
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/sharp-greater.asm b/amforth-6.5/common/words/sharp-greater.asm
deleted file mode 100644
index 914aba2..0000000
--- a/amforth-6.5/common/words/sharp-greater.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( d1 -- addr count )
-; Numeric IO
-; Pictured Numeric Output: convert PNO buffer into an string
-
-.if cpu_msp430==1
- HEADER(XT_SHARP_G,2,"#>",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SHARP_G:
- .dw $ff02
- .db "#>"
- .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_G
-XT_SHARP_G:
- .dw DO_COLON
-PFA_SHARP_G:
-.endif
- .dw XT_2DROP
- .dw XT_HLD
- .dw XT_FETCH
- .dw XT_PAD
- .dw XT_OVER
- .dw XT_MINUS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/sharp-s.asm b/amforth-6.5/common/words/sharp-s.asm
deleted file mode 100644
index 58fd508..0000000
--- a/amforth-6.5/common/words/sharp-s.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( d -- 0 )
-; Numeric IO
-; pictured numeric output: convert all digits until 0 (zero) is reached
-
-.if cpu_msp430==1
- HEADER(XT_SHARP_S,2,"#s",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SHARP_S:
- .dw $ff02
- .db "#s"
- .dw VE_HEAD
- .set VE_HEAD = VE_SHARP_S
-XT_SHARP_S:
- .dw DO_COLON
-PFA_SHARP_S:
-.endif
-NUMS1:
- .dw XT_SHARP
- .dw XT_2DUP
- .dw XT_OR
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(NUMS1) ; PFA_SHARP_S
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/sharp.asm b/amforth-6.5/common/words/sharp.asm
deleted file mode 100644
index 7659a39..0000000
--- a/amforth-6.5/common/words/sharp.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-; ( d1 -- d2 )
-; Numeric IO
-; pictured numeric output: convert one digit
-
-.if cpu_msp430==1
- HEADER(XT_SHARP,1,"#",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_SHARP:
- .dw $ff01
- .db "#",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SHARP
-XT_SHARP:
- .dw DO_COLON
-PFA_SHARP:
-.endif
- .dw XT_BASE
- .dw XT_FETCH
- .dw XT_UDSLASHMOD
- .dw XT_ROT
- .dw XT_DOLITERAL
- .dw 9
- .dw XT_OVER
- .dw XT_LESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_SHARP1)
- .dw XT_DOLITERAL
- .dw 7
- .dw XT_PLUS
-PFA_SHARP1:
- .dw XT_DOLITERAL
- .dw 48 ; ASCII 0
- .dw XT_PLUS
- .dw XT_HOLD
- .dw XT_EXIT
-; : # ( ud1 -- ud2 )
-; base @ ud/mod rot 9 over < if 7 + then 30 + hold ;
diff --git a/amforth-6.5/common/words/show-wordlist.asm b/amforth-6.5/common/words/show-wordlist.asm
deleted file mode 100644
index d150639..0000000
--- a/amforth-6.5/common/words/show-wordlist.asm
+++ /dev/null
@@ -1,38 +0,0 @@
-; ( wid -- )
-; Tools
-; prints the name of the words in a wordlist
-
-.if cpu_msp430==1
- HEADER(XT_SHOWWORDLIST,13,"show-wordlist",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SHOWWORDLIST:
- .dw $ff0d
- .db "show-wordlist",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SHOWWORDLIST
-XT_SHOWWORDLIST:
- .dw DO_COLON
-PFA_SHOWWORDLIST:
-.endif
- .dw XT_DOLITERAL
- .dw XT_SHOWWORD
- .dw XT_SWAP
- .dw XT_TRAVERSEWORDLIST
- .dw XT_EXIT
-
-.if cpu_msp430==1
- HEADLESS(XT_SHOWWORD,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-XT_SHOWWORD:
- .dw DO_COLON
-PFA_SHOWWORD:
-.endif
- .dw XT_NAME2STRING
- .dw XT_ITYPE
- .dw XT_SPACE ; ( -- addr n)
- .dw XT_TRUE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/sign.asm b/amforth-6.5/common/words/sign.asm
deleted file mode 100644
index f532bbe..0000000
--- a/amforth-6.5/common/words/sign.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( n -- )
-; Numeric IO
-; place a - in HLD if n is negative
-
-.if cpu_msp430==1
- HEADER(XT_SIGN,4,"sign",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SIGN:
- .dw $ff04
- .db "sign"
- .dw VE_HEAD
- .set VE_HEAD = VE_SIGN
-XT_SIGN:
- .dw DO_COLON
-PFA_SIGN:
-.endif
- .dw XT_ZEROLESS
- .dw XT_DOCONDBRANCH
- DEST(PFA_SIGN1)
- .dw XT_DOLITERAL
- .dw 45 ; ascii -
- .dw XT_HOLD
-PFA_SIGN1:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/slash-string.asm b/amforth-6.5/common/words/slash-string.asm
deleted file mode 100644
index bded983..0000000
--- a/amforth-6.5/common/words/slash-string.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-; ( addr1 u1 n -- addr2 u2 )
-; String
-; adjust string from addr1 to addr1+n, reduce length from u1 to u2 by n
-
-.if cpu_msp430==1
- HEADER(XT_SLASHSTRING,7,"/string",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SLASHSTRING:
- .dw $ff07
- .db "/string",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLASHSTRING
-XT_SLASHSTRING:
- .dw DO_COLON
-PFA_SLASHSTRING:
-.endif
- .dw XT_ROT
- .dw XT_OVER
- .dw XT_PLUS
- .dw XT_ROT
- .dw XT_ROT
- .dw XT_MINUS
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/slash.asm b/amforth-6.5/common/words/slash.asm
deleted file mode 100644
index 3f0e3af..0000000
--- a/amforth-6.5/common/words/slash.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( n1 n2 -- n3)
-; Arithmetics
-; divide n1 by n2. giving the quotient
-
-.if cpu_msp430==1
- HEADER(SLASH,1,"/",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_SLASH:
- .dw $ff01
- .db "/",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLASH
-XT_SLASH:
- .dw DO_COLON
-PFA_SLASH:
-.endif
- .dw XT_SLASHMOD
- .dw XT_NIP
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/sliteral.asm b/amforth-6.5/common/words/sliteral.asm
deleted file mode 100644
index 9233796..0000000
--- a/amforth-6.5/common/words/sliteral.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; (C: addr len -- )
-; String
-; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
-.if cpu_msp430==1
- IMMED(XT_SLITERAL,8,"sliteral",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SLITERAL:
- .dw $0008
- .db "sliteral"
- .dw VE_HEAD
- .set VE_HEAD = VE_SLITERAL
-XT_SLITERAL:
- .dw DO_COLON
-PFA_SLITERAL:
-.endif
- .dw XT_COMPILE
- .dw XT_DOSLITERAL ; ( -- addr n)
- .dw XT_SCOMMA
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/source.asm b/amforth-6.5/common/words/source.asm
deleted file mode 100644
index a1ac867..0000000
--- a/amforth-6.5/common/words/source.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( -- addr n )
-; System
-; address and current length of the input buffer
-
-.if cpu_msp430==1
- DEFER(XT_SOURCE,6,"source")
-.endif
-
-.if cpu_avr8==1
-VE_SOURCE:
- .dw $FF06
- .db "source"
- .dw VE_HEAD
- .set VE_HEAD = VE_SOURCE
-XT_SOURCE:
- .dw PFA_DODEFER1
-PFA_SOURCE:
-.endif
- .dw USER_SOURCE
- .dw XT_UDEFERFETCH
- .dw XT_UDEFERSTORE
-
-
diff --git a/amforth-6.5/common/words/space.asm b/amforth-6.5/common/words/space.asm
deleted file mode 100644
index bf4175d..0000000
--- a/amforth-6.5/common/words/space.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( -- )
-; Character IO
-; emits a space (bl)
-
-.if cpu_msp430==1
- HEADER(XT_SPACE,5,"space",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SPACE:
- .dw $ff05
- .db "space",0
- .dw VE_HEAD
- .set VE_HEAD = VE_SPACE
-XT_SPACE:
- .dw DO_COLON
-PFA_SPACE:
-.endif
- .dw XT_BL
- .dw XT_EMIT
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/spaces.asm b/amforth-6.5/common/words/spaces.asm
deleted file mode 100644
index 7ecbcd8..0000000
--- a/amforth-6.5/common/words/spaces.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( n -- )
-; Character IO
-; emits n space(s) (bl)
-
-.if cpu_msp430==1
- HEADER(XT_SPACES,6,"spaces",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SPACES:
- .dw $ff06
- .db "spaces"
- .dw VE_HEAD
- .set VE_HEAD = VE_SPACES
-XT_SPACES:
- .dw DO_COLON
-PFA_SPACES:
-
-.endif
-;C SPACES n -- output n spaces
-; BEGIN DUP 0> WHILE SPACE 1- REPEAT DROP ;
- .DW XT_ZERO, XT_MAX
-SPCS1: .DW XT_DUP,XT_DOCONDBRANCH
- DEST(SPCS2)
- .DW XT_SPACE,XT_1MINUS,XT_DOBRANCH
- DEST(SPCS1)
-SPCS2: .DW XT_DROP,XT_EXIT
diff --git a/amforth-6.5/common/words/squote.asm b/amforth-6.5/common/words/squote.asm
deleted file mode 100644
index 98cfa33..0000000
--- a/amforth-6.5/common/words/squote.asm
+++ /dev/null
@@ -1,33 +0,0 @@
-; ( -- addr len) (C: <cchar> -- )
-; Compiler
-; compiles a string to flash, at runtime leaves ( -- flash-addr count) on stack
-
-.if cpu_msp430==1
- DW link
- DB 0FEh ; immediate
-.set link = $
- DB 2,"s",'"'
- .align 16
-XT_SQUOTE: DW DOCOLON
-.endif
-
-.if cpu_avr8==1
-VE_SQUOTE:
- .dw $0002
- .db "s",$22
- .dw VE_HEAD
- .set VE_HEAD = VE_SQUOTE
-XT_SQUOTE:
- .dw DO_COLON
-PFA_SQUOTE:
-.endif
- .dw XT_DOLITERAL
- .dw 34 ; 0x22
- .dw XT_PARSE ; ( -- addr n)
- .dw XT_STATE
- .dw XT_FETCH
- .dw XT_DOCONDBRANCH
- DEST(PFA_SQUOTE1)
- .dw XT_SLITERAL
-PFA_SQUOTE1:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/star.asm b/amforth-6.5/common/words/star.asm
deleted file mode 100644
index a09e00c..0000000
--- a/amforth-6.5/common/words/star.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( n1 n2 -- n3 )
-; Arithmetics
-; multiply routine
-
-.if cpu_msp430==1
- HEADER(STAR,1,"*",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_STAR:
- .dw $ff01
- .db "*",0
- .dw VE_HEAD
- .set VE_HEAD = VE_STAR
-XT_STAR:
- .dw DO_COLON
-PFA_STAR:
-.endif
-
- .dw XT_MSTAR
- .dw XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/then.asm b/amforth-6.5/common/words/then.asm
deleted file mode 100644
index edd0665..0000000
--- a/amforth-6.5/common/words/then.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-; ( -- ) (C: orig -- )
-; Compiler
-; finish if
-
-.if cpu_msp430==1
- IMMED(XT_THEN,4,"then",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_THEN:
- .dw $0004
- .db "then"
- .dw VE_HEAD
- .set VE_HEAD = VE_THEN
-XT_THEN:
- .dw DO_COLON
-PFA_THEN:
-.endif
- .dw XT_GRESOLVE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/throw.asm b/amforth-6.5/common/words/throw.asm
deleted file mode 100644
index 24877a3..0000000
--- a/amforth-6.5/common/words/throw.asm
+++ /dev/null
@@ -1,39 +0,0 @@
-; ( n -- )
-; Exceptions
-; throw an exception
-
-.if cpu_msp430==1
- HEADER(XT_THROW,5,"throw",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_THROW:
- .dw $ff05
- .db "throw",0
- .dw VE_HEAD
- .set VE_HEAD = VE_THROW
-XT_THROW:
- .dw DO_COLON
-PFA_THROW:
-.endif
- .dw XT_DUP
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(PFA_THROW1)
- .dw XT_DROP
- .dw XT_EXIT
-PFA_THROW1:
- .dw XT_HANDLER
- .dw XT_FETCH
- .dw XT_RP_STORE
- .dw XT_R_FROM
- .dw XT_HANDLER
- .dw XT_STORE
- .dw XT_R_FROM
- .dw XT_SWAP
- .dw XT_TO_R
- .dw XT_SP_STORE
- .dw XT_DROP
- .dw XT_R_FROM
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/tib.asm b/amforth-6.5/common/words/tib.asm
deleted file mode 100644
index ca5601f..0000000
--- a/amforth-6.5/common/words/tib.asm
+++ /dev/null
@@ -1,96 +0,0 @@
-; ( -- f )
-; System
-; refills the input buffer
-.if cpu_msp430==1
- HEADER(XT_REFILLTIB,10,"refill-tib",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_REFILLTIB:
- .dw $ff0a
- .db "refill-tib"
- .dw VE_HEAD
- .set VE_HEAD = VE_REFILLTIB
-XT_REFILLTIB:
- .dw DO_COLON
-PFA_REFILLTIB:
-.endif
- .dw XT_TIB
- .dw XT_DOLITERAL
- .dw TIB_SIZE
- .dw XT_ACCEPT
- .dw XT_NUMBERTIB
- .dw XT_STORE
- .dw XT_ZERO
- .dw XT_TO_IN
- .dw XT_STORE
- .dw XT_TRUE ; -1
- .dw XT_EXIT
-
-; ( -- addr n )
-; System
-; address and current length of the input buffer
-.if cpu_msp430==1
- HEADER(XT_SOURCETIB,10,"source-tib",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_SOURCETIB:
- .dw $FF0A
- .db "source-tib"
- .dw VE_HEAD
- .set VE_HEAD = VE_SOURCETIB
-XT_SOURCETIB:
- .dw DO_COLON
-PFA_SOURCETIB:
-.endif
- .dw XT_TIB
- .dw XT_NUMBERTIB
- .dw XT_FETCH
- .dw XT_EXIT
-
-; ( -- addr )
-; System Variable
-; terminal input buffer address
-.if cpu_msp430==1
- VARIABLE(XT_TIB,3,"tib")
- .DW TIBAREA
-.endif
-
-.if cpu_avr8==1
-VE_TIB:
- .dw $ff03
- .db "tib",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TIB
-XT_TIB:
- .dw PFA_DOVARIABLE
-PFA_TIB:
- .dw ram_tib
-.dseg
-ram_tib: .byte TIB_SIZE
-.cseg
-.endif
-
-; ( -- addr )
-; System Variable
-; variable holding the number of characters in TIB
-.if cpu_msp430==1
- VARIABLE(XT_NUMBERTIB,4,"#tib")
- .DW RAM_NUMBERTIB
-.endif
-
-.if cpu_avr8==1
-VE_NUMBERTIB:
- .dw $ff04
- .db "#tib"
- .dw VE_HEAD
- .set VE_HEAD = VE_NUMBERTIB
-XT_NUMBERTIB:
- .dw PFA_DOVARIABLE
-PFA_NUMBERTIB:
- .dw ram_sharptib
-.dseg
-ram_sharptib: .byte 2
-.cseg
-.endif
diff --git a/amforth-6.5/common/words/tick.asm b/amforth-6.5/common/words/tick.asm
deleted file mode 100644
index 3d04411..0000000
--- a/amforth-6.5/common/words/tick.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-; ( "<spaces>name" -- XT )
-; Dictionary
-; search dictionary for name, return XT or throw an exception -13
-
-.if cpu_msp430==1
- HEADER(XT_TICK,1,27h,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TICK:
- .dw $ff01
- .db "'",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TICK
-XT_TICK:
- .dw DO_COLON
-PFA_TICK:
-.endif
- .dw XT_PARSENAME
- .dw XT_FORTHRECOGNIZER
- .dw XT_RECOGNIZE
- ; a word is tickable unless DT:TOKEN is DT:NULL or
- ; the interpret action is a NOOP
- .dw XT_DUP
- .dw XT_DT_NULL
- .dw XT_EQUAL
- .dw XT_SWAP
- .dw XT_FETCHI
- .dw XT_DOLITERAL
- .dw XT_NOOP
- .dw XT_EQUAL
- .dw XT_OR
- .dw XT_DOCONDBRANCH
- DEST(PFA_TICK1)
- .dw XT_DOLITERAL
- .dw -13
- .dw XT_THROW
-PFA_TICK1:
- .dw XT_DROP
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/to-in.asm b/amforth-6.5/common/words/to-in.asm
deleted file mode 100644
index 29ca20c..0000000
--- a/amforth-6.5/common/words/to-in.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( -- a-addr )
-; System Variable
-; pointer to current read position in input buffer
-
-.if cpu_msp430==1
- HEADER(XT_TO_IN,3,">in",DOUSER)
-.endif
-
-.if cpu_avr8==1
-VE_TO_IN:
- .dw $ff03
- .db ">in",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_IN
-XT_TO_IN:
- .dw PFA_DOUSER
-PFA_TO_IN:
-.endif
- .dw USER_TO_IN
diff --git a/amforth-6.5/common/words/to-l.asm b/amforth-6.5/common/words/to-l.asm
deleted file mode 100644
index 0312da9..0000000
--- a/amforth-6.5/common/words/to-l.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_TO_L,2,">l",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TO_L:
- .dw $ff02
- .db ">l"
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_L
-XT_TO_L:
- .dw DO_COLON
-PFA_TO_L:
-.endif
-;Z >L x -- L: -- x move to leave stack
-; CELL LP +! LP @ ! ; (L stack grows up)
-
- .dw XT_TWO
- .dw XT_LP
- .dw XT_PLUSSTORE
- .dw XT_LP
- .dw XT_FETCH
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/to-lower.asm b/amforth-6.5/common/words/to-lower.asm
deleted file mode 100644
index fe9328c..0000000
--- a/amforth-6.5/common/words/to-lower.asm
+++ /dev/null
@@ -1,33 +0,0 @@
-; ( C -- c)
-; String
-; if C is an uppercase letter convert it to lowercase
-
-.if cpu_msp430==1
- HEADER(XT_TOLOWER,7,"tolower",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_TOLOWER:
- .dw $ff07
- .db "tolower",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TOLOWER
-XT_TOLOWER:
- .dw DO_COLON
-PFA_TOLOWER:
-.endif
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw 'A'
- .dw XT_DOLITERAL
- .dw 'Z'+1
- .dw XT_WITHIN
- .dw XT_DOCONDBRANCH
- DEST(PFA_TOLOWER0)
- .dw XT_DOLITERAL
- .dw 32
- .dw XT_OR
-PFA_TOLOWER0:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/to-number.asm b/amforth-6.5/common/words/to-number.asm
deleted file mode 100644
index 18ab6f4..0000000
--- a/amforth-6.5/common/words/to-number.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-; ( ud1 c-addr1 u1 -- ud2 c-addr2 u2 )
-; Numeric IO
-; convert a string to a number c-addr2/u2 is the unconverted string
-
-.if cpu_msp430==1
- HEADER(XT_TO_NUMBER,7,">number",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TO_NUMBER:
- .dw $ff07
- .db ">number",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TO_NUMBER
-XT_TO_NUMBER:
- .dw DO_COLON
-
-.endif
-
-TONUM1: .DW XT_DUP,XT_DOCONDBRANCH
- DEST(TONUM3)
- .DW XT_OVER,XT_CFETCH,XT_DIGITQ
- .DW XT_ZEROEQUAL,XT_DOCONDBRANCH
- DEST(TONUM2)
- .DW XT_DROP,XT_EXIT
-TONUM2: .DW XT_TO_R,XT_2SWAP,XT_BASE,XT_FETCH,XT_UDSTAR
- .DW XT_R_FROM,XT_MPLUS,XT_2SWAP
- .DW XT_ONE,XT_SLASHSTRING,XT_DOBRANCH
- DEST(TONUM1)
-TONUM3: .DW XT_EXIT
-
-;C >NUMBER ud adr u -- ud' adr' u'
-;C convert string to number
-; BEGIN
-; DUP WHILE
-; OVER C@ DIGIT?
-; 0= IF DROP EXIT THEN
-; >R 2SWAP BASE @ UD*
-; R> M+ 2SWAP
-; 1 /STRING
-; REPEAT ;
diff --git a/amforth-6.5/common/words/to-upper.asm b/amforth-6.5/common/words/to-upper.asm
deleted file mode 100644
index 180cd5d..0000000
--- a/amforth-6.5/common/words/to-upper.asm
+++ /dev/null
@@ -1,31 +0,0 @@
-; ( c -- C )
-; String
-; if c is a lowercase letter convert it to uppercase
-
-.if cpu_msp430==1
- HEADER(XT_TOUPPER,7,"toupper",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TOUPPER:
- .dw $ff07
- .db "toupper",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TOUPPER
-XT_TOUPPER:
- .dw DO_COLON
-PFA_TOUPPER:
-.endif
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw 'a'
- .dw XT_DOLITERAL
- .dw 'z'+1
- .dw XT_WITHIN
- .dw XT_DOCONDBRANCH
- DEST(PFA_TOUPPER0)
- .dw XT_DOLITERAL
- .dw 223 ; inverse of 0x20: 0xdf
- .dw XT_AND
-PFA_TOUPPER0:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/to.asm b/amforth-6.5/common/words/to.asm
deleted file mode 100644
index 0bb1aec..0000000
--- a/amforth-6.5/common/words/to.asm
+++ /dev/null
@@ -1,59 +0,0 @@
-; ( n <name> -- )
-; Tools
-; store the TOS to the named value (eeprom cell)
-
-.if cpu_msp430==1
- IMMED(XT_TO,2,"to",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TO:
- .dw $0002
- .db "to"
- .dw VE_HEAD
- .set VE_HEAD = VE_TO
-XT_TO:
- .dw DO_COLON
-PFA_TO:
-.endif
- .dw XT_TICK
- .dw XT_TO_BODY
- .dw XT_STATE
- .dw XT_FETCH
- .dw XT_DOCONDBRANCH
- DEST(PFA_TO1)
- .dw XT_COMPILE
- .dw XT_DOTO
- .dw XT_COMMA
- .dw XT_EXIT
-
-; ( n -- ) (R: IP -- IP+1)
-; Tools
-; runtime portion of to
-;VE_DOTO:
-; .dw $ff04
-; .db "(to)"
-; .dw VE_HEAD
-; .set VE_HEAD = VE_DOTO
-.if cpu_msp430==1
- HEADLESS(XT_DOTO,DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-XT_DOTO:
- .dw DO_COLON
-PFA_DOTO:
-.endif
- .dw XT_R_FROM
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_TO_R
- .dw XT_FETCHI
-PFA_TO1:
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/traverse-wordlist.asm b/amforth-6.5/common/words/traverse-wordlist.asm
deleted file mode 100644
index b6c00e0..0000000
--- a/amforth-6.5/common/words/traverse-wordlist.asm
+++ /dev/null
@@ -1,49 +0,0 @@
-; ( i*x xt wid -- j*x )
-; Tools Ext (2012)
-; call the xt for every member of the wordlist wid until xt returns false
-
-.if cpu_msp430==1
- HEADER(XT_TRAVERSEWORDLIST,17,"traverse-wordlist",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TRAVERSEWORDLIST:
- .dw $ff11
- .db "traverse-wordlist",0
- .dw VE_HEAD
- .set VE_HEAD = VE_TRAVERSEWORDLIST
-XT_TRAVERSEWORDLIST:
- .dw DO_COLON
-PFA_TRAVERSEWORDLIST:
-
-.endif
- .dw XT_FETCHE
-PFA_TRAVERSEWORDLIST1:
- .dw XT_DUP ; ( -- xt nt nt )
- .dw XT_DOCONDBRANCH ; ( -- nt ) is nfa = counted string
- DEST(PFA_TRAVERSEWORDLIST2)
- .dw XT_2DUP
- .dw XT_2TO_R
- .dw XT_SWAP
- .dw XT_EXECUTE
- .dw XT_2R_FROM
- .dw XT_ROT
- .dw XT_DOCONDBRANCH
- DEST(PFA_TRAVERSEWORDLIST2)
- .dw XT_NFA2LFA
- .dw XT_FETCHI
- .dw XT_DOBRANCH ; ( -- addr )
- DEST(PFA_TRAVERSEWORDLIST1) ; ( -- addr )
-PFA_TRAVERSEWORDLIST2:
- .dw XT_2DROP
- .dw XT_EXIT
-
-; : traverse-wordlist ( i*x xt wid -- i*x' )
-; begin @ dup
-; while
-; 2dup 2>r
-; swap execute ( i*x nt -- i*x' f )
-; 2r> rot
-; while
-; nfa>lfa @i
-; repeat then 2drop ;
diff --git a/amforth-6.5/common/words/tuck.asm b/amforth-6.5/common/words/tuck.asm
deleted file mode 100644
index 173dc8c..0000000
--- a/amforth-6.5/common/words/tuck.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( n1 n2 -- n2 n1 n2 )
-; Stack
-; Copy the first (top) stack item below the second stack item.
-
-.if cpu_msp430==1
- HEADER(XT_TUCK,4,"tuck",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TUCK:
- .dw $ff04
- .db "tuck"
- .dw VE_HEAD
- .set VE_HEAD = VE_TUCK
-XT_TUCK:
- .dw DO_COLON
-PFA_TUCK:
-.endif
- .dw XT_SWAP
- .dw XT_OVER
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/type.asm b/amforth-6.5/common/words/type.asm
deleted file mode 100644
index 66929b0..0000000
--- a/amforth-6.5/common/words/type.asm
+++ /dev/null
@@ -1,32 +0,0 @@
-; ( addr n -- )
-; Character IO
-; print a RAM based string
-
-.if cpu_msp430==1
- HEADER(XT_TYPE,4,"type",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_TYPE:
- .dw $ff04
- .db "type"
- .dw VE_HEAD
- .set VE_HEAD = VE_TYPE
-XT_TYPE:
- .dw DO_COLON
-PFA_TYPE:
-
-.endif
- .dw XT_BOUNDS
- .dw XT_QDOCHECK
- .dw XT_DOCONDBRANCH
- DEST(PFA_TYPE2)
- .dw XT_DODO
-PFA_TYPE1:
- .dw XT_I
- .dw XT_CFETCH
- .dw XT_EMIT
- .dw XT_DOLOOP
- DEST(PFA_TYPE1)
-PFA_TYPE2:
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/u-dot-r.asm b/amforth-6.5/common/words/u-dot-r.asm
deleted file mode 100644
index 18cb089..0000000
--- a/amforth-6.5/common/words/u-dot-r.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( u w -- )
-; Numeric IO
-; unsigned PNO with single cells numbers, right aligned in width w
-
-.if cpu_msp430==1
- HEADER(XT_UDOTR,3,"u.r",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_UDOTR:
- .dw $ff03
- .db "u.r",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UDOTR
-XT_UDOTR:
- .dw DO_COLON
-PFA_UDOTR:
-.endif
- .dw XT_ZERO
- .dw XT_SWAP
- .dw XT_UDDOTR
- .dw XT_EXIT
-; : u.r ( s n -- ) 0 swap ud.r ;
diff --git a/amforth-6.5/common/words/u-dot.asm b/amforth-6.5/common/words/u-dot.asm
deleted file mode 100644
index 100a53d..0000000
--- a/amforth-6.5/common/words/u-dot.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( u -- )
-; Numeric IO
-; unsigned PNO with single cell numbers
-
-.if cpu_msp430==1
- HEADER(XT_UDOT,2,"u.",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UDOT:
- .dw $ff02
- .db "u."
- .dw VE_HEAD
- .set VE_HEAD = VE_UDOT
-XT_UDOT:
- .dw DO_COLON
-PFA_UDOT:
-.endif
- .dw XT_ZERO
- .dw XT_UDDOT
- .dw XT_EXIT
-; : u. ( us -- ) 0 ud. ;
diff --git a/amforth-6.5/common/words/u-greater.asm b/amforth-6.5/common/words/u-greater.asm
deleted file mode 100644
index 4de1b85..0000000
--- a/amforth-6.5/common/words/u-greater.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( u1 u2 -- flag )
-; Compare
-; true if u1 > u2 (unsigned)
-
-.if cpu_msp430==1
- HEADER(XT_UGREATER,2,"u>",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UGREATER:
- .dw $ff02
- .db "u>"
- .dw VE_HEAD
- .set VE_HEAD = VE_UGREATER
-XT_UGREATER:
- .dw DO_COLON
-PFA_UGREATER:
-.endif
- .DW XT_SWAP
- .dw XT_ULESS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/ud-dot-r.asm b/amforth-6.5/common/words/ud-dot-r.asm
deleted file mode 100644
index 7db9c2e..0000000
--- a/amforth-6.5/common/words/ud-dot-r.asm
+++ /dev/null
@@ -1,31 +0,0 @@
-; ( ud w -- )
-; Numeric IO
-; unsigned PNO with double cell numbers, right aligned in width w
-
-.if cpu_msp430==1
- HEADER(XT_UDDOTR,4,"ud.r",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_UDDOTR:
- .dw $ff04
- .db "ud.r"
- .dw VE_HEAD
- .set VE_HEAD = VE_UDDOTR
-XT_UDDOTR:
- .dw DO_COLON
-PFA_UDDOTR:
-.endif
- .dw XT_TO_R
- .dw XT_L_SHARP
- .dw XT_SHARP_S
- .dw XT_SHARP_G
- .dw XT_R_FROM
- .dw XT_OVER
- .dw XT_MINUS
- .dw XT_SPACES
- .dw XT_TYPE
- .dw XT_EXIT
-; : ud.r ( ud n -- ) >r <# #s #> r> over - spaces type ; \ No newline at end of file
diff --git a/amforth-6.5/common/words/ud-dot.asm b/amforth-6.5/common/words/ud-dot.asm
deleted file mode 100644
index c45ed5e..0000000
--- a/amforth-6.5/common/words/ud-dot.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( ud -- )
-; Numeric IO
-; unsigned PNO with double cell numbers
-
-.if cpu_msp430==1
- HEADER(XT_UDDOT,3,"ud.",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UDDOT:
- .dw $ff03
- .db "ud.",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UDDOT
-XT_UDDOT:
- .dw DO_COLON
-PFA_UDDOT:
-.endif
- .dw XT_ZERO
- .dw XT_UDDOTR
- .dw XT_SPACE
- .dw XT_EXIT
-; : ud. ( ud -- ) 0 ud.r space ; \ No newline at end of file
diff --git a/amforth-6.5/common/words/ud-slash-mod.asm b/amforth-6.5/common/words/ud-slash-mod.asm
deleted file mode 100644
index ad50afa..0000000
--- a/amforth-6.5/common/words/ud-slash-mod.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-; ( d1 n -- rem ud2 )
-; Arithmetics
-; unsigned double cell division with remainder
-
-.if cpu_msp430==1
- HEADER(XT_UDSLASHMOD,6,"ud/mod",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UDSLASHMOD:
- .dw $ff06
- .db "ud/mod"
- .dw VE_HEAD
- .set VE_HEAD = VE_UDSLASHMOD
-XT_UDSLASHMOD:
- .dw DO_COLON
-PFA_UDSLASHMOD:
-.endif
- .dw XT_TO_R
- .dw XT_ZERO
- .dw XT_R_FETCH
- .dw XT_UMSLASHMOD
- .dw XT_R_FROM
- .dw XT_SWAP
- .dw XT_TO_R
- .dw XT_UMSLASHMOD
- .dw XT_R_FROM
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/ud-star.asm b/amforth-6.5/common/words/ud-star.asm
deleted file mode 100644
index 64642da..0000000
--- a/amforth-6.5/common/words/ud-star.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_UDSTAR,3,"ud*",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UDSTAR:
- .dw $ff03
- .db "ud*"
- .dw VE_HEAD
- .set VE_HEAD = VE_UDSTAR
-XT_UDSTAR:
- .dw DO_COLON
-PFA_UDSTAR:
-
-.endif
-;Z UD* ud1 d2 -- ud3 32*16->32 multiply
-; XT_DUP >R UM* DROP XT_SWAP R> UM* ROT + ;
-
- .DW XT_DUP,XT_TO_R,XT_UMSTAR,XT_DROP
- .DW XT_SWAP,XT_R_FROM,XT_UMSTAR,XT_ROT,XT_PLUS,XT_EXIT
diff --git a/amforth-6.5/common/words/udefer-fetch.asm b/amforth-6.5/common/words/udefer-fetch.asm
deleted file mode 100644
index 81a1084..0000000
--- a/amforth-6.5/common/words/udefer-fetch.asm
+++ /dev/null
@@ -1,23 +0,0 @@
-; ( xt1 -- xt2 )
-; System
-; does the real defer@ for user based defers
-
-.if cpu_msp430==1
- HEADER(XT_UDEFERFETCH,7,"Udefer@",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UDEFERFETCH:
- .dw $ff07
- .db "Udefer@",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERFETCH
-XT_UDEFERFETCH:
- .dw DO_COLON
-PFA_UDEFERFETCH:
-.endif
- .dw XT_FETCHI
- .dw XT_UP_FETCH
- .dw XT_PLUS
- .dw XT_FETCH
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/udefer-store.asm b/amforth-6.5/common/words/udefer-store.asm
deleted file mode 100644
index 447f58e..0000000
--- a/amforth-6.5/common/words/udefer-store.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( xt1 xt2 -- )
-; System
-; does the real defer! for user based defers
-
-.if cpu_msp430==1
- HEADER(XT_UDEFERSTORE,7,"Udefer!",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UDEFERSTORE:
- .dw $ff07
- .db "Udefer!",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UDEFERSTORE
-XT_UDEFERSTORE:
- .dw DO_COLON
-PFA_UDEFERSTORE:
-.endif
-
- .dw XT_FETCHI
- .dw XT_UP_FETCH
- .dw XT_PLUS
- .dw XT_STORE
- .dw XT_EXIT
-
diff --git a/amforth-6.5/common/words/umax.asm b/amforth-6.5/common/words/umax.asm
deleted file mode 100644
index fb16de5..0000000
--- a/amforth-6.5/common/words/umax.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_UMAX,4,"umax",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UMAX:
- .dw $ff04
- .db "umax"
- .dw VE_HEAD
- .set VE_HEAD = VE_UMAX
-XT_UMAX:
- .dw DO_COLON
-PFA_UMAX:
-.endif
-
- .DW XT_2DUP,XT_ULESS
- .dw XT_DOCONDBRANCH
- DEST(UMAX1)
- .DW XT_SWAP
-UMAX1: .DW XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/umin.asm b/amforth-6.5/common/words/umin.asm
deleted file mode 100644
index c789095..0000000
--- a/amforth-6.5/common/words/umin.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-
-.if cpu_msp430==1
- HEADER(XT_UMIN,4,"umin",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UMIN:
- .dw $ff04
- .db "umin"
- .dw VE_HEAD
- .set VE_HEAD = VE_UMIN
-XT_UMIN:
- .dw DO_COLON
-PFA_UMIN:
-.endif
- .DW XT_2DUP,XT_UGREATER
- .dw XT_DOCONDBRANCH
- DEST(UMIN1)
- .DW XT_SWAP
-UMIN1: .DW XT_DROP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/until.asm b/amforth-6.5/common/words/until.asm
deleted file mode 100644
index 74ec04b..0000000
--- a/amforth-6.5/common/words/until.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( f -- ) (C: dest -- )
-; Compiler
-; finish begin with conditional branch, leaves the loop if true flag at runtime
-
-.if cpu_msp430==1
- IMMED(XT_UNTIL,5,"until",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_UNTIL:
- .dw $0005
- .db "until",0
- .dw VE_HEAD
- .set VE_HEAD = VE_UNTIL
-XT_UNTIL:
- .dw DO_COLON
-PFA_UNTIL:
-.endif
- .dw XT_DOLITERAL
- .dw XT_DOCONDBRANCH
- .dw XT_COMMA
-
- .dw XT_LRESOLVE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/variable.asm b/amforth-6.5/common/words/variable.asm
deleted file mode 100644
index fe3e245..0000000
--- a/amforth-6.5/common/words/variable.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( cchar -- )
-; Compiler
-; create a dictionary entry for a variable and allocate 1 cell RAM
-
-.if cpu_msp430==1
- HEADER(XT_VARIABLE,8,"variable",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-VE_VARIABLE:
- .dw $ff08
- .db "variable"
- .dw VE_HEAD
- .set VE_HEAD = VE_VARIABLE
-XT_VARIABLE:
- .dw DO_COLON
-PFA_VARIABLE:
-.endif
- .dw XT_HERE
- .dw XT_CONSTANT
- .dw XT_TWO
- .dw XT_ALLOT
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/ver.asm b/amforth-6.5/common/words/ver.asm
deleted file mode 100644
index 3e0105a..0000000
--- a/amforth-6.5/common/words/ver.asm
+++ /dev/null
@@ -1,42 +0,0 @@
-; ( -- )
-; Tools
-; print the version string
-
-.if cpu_msp430==1
- HEADER(XT_DOT_VER,3,"ver",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_DOT_VER:
- .dw $ff03
- .db "ver"
- .dw VE_HEAD
- .set VE_HEAD = VE_DOT_VER
-XT_DOT_VER:
- .dw DO_COLON
-PFA_DOT_VER:
-.endif
- .dw XT_ENV_FORTHNAME
- .dw XT_ITYPE
- .dw XT_SPACE
- .dw XT_BASE
- .dw XT_FETCH
-
- .dw XT_ENV_FORTHVERSION
- .dw XT_DECIMAL
- .dw XT_S2D
- .dw XT_L_SHARP
- .dw XT_SHARP
- .dw XT_DOLITERAL
- .dw '.'
- .dw XT_HOLD
- .dw XT_SHARP_S
- .dw XT_SHARP_G
- .dw XT_TYPE
- .dw XT_BASE
- .dw XT_STORE
- .dw XT_SPACE
- .dw XT_ENV_CPU
- .dw XT_ITYPE
-
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/warm.asm b/amforth-6.5/common/words/warm.asm
deleted file mode 100644
index 5634fa0..0000000
--- a/amforth-6.5/common/words/warm.asm
+++ /dev/null
@@ -1,27 +0,0 @@
-; ( nx* -- ) (R: ny* -- )
-; System
-; initialize amforth further. executes turnkey operation and go to quit
-
-.if cpu_msp430==1
- HEADER(XT_WARM,4,"warm",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_WARM:
- .dw $ff04
- .db "warm"
- .dw VE_HEAD
- .set VE_HEAD = VE_WARM
-XT_WARM:
- .dw DO_COLON
-PFA_WARM:
-.endif
- .dw XT_INIT_RAM
- .dw XT_DOLITERAL
- .dw XT_NOOP
- .dw XT_DOLITERAL
- .dw XT_PAUSE
- .dw XT_DEFERSTORE
- .dw XT_LBRACKET
- .dw XT_TURNKEY
- .dw XT_QUIT ; never returns
diff --git a/amforth-6.5/common/words/while.asm b/amforth-6.5/common/words/while.asm
deleted file mode 100644
index c21a6c1..0000000
--- a/amforth-6.5/common/words/while.asm
+++ /dev/null
@@ -1,21 +0,0 @@
-; ( f -- ) (C: dest -- orig dest )
-; Compiler
-; at runtime skip until repeat if non-true
-
-.if cpu_msp430==1
- IMMED(XT_WHILE,5,"while",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_WHILE:
- .dw $0005
- .db "while",0
- .dw VE_HEAD
- .set VE_HEAD = VE_WHILE
-XT_WHILE:
- .dw DO_COLON
-PFA_WHILE:
-.endif
- .dw XT_IF
- .dw XT_SWAP
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/within.asm b/amforth-6.5/common/words/within.asm
deleted file mode 100644
index 9aaa77a..0000000
--- a/amforth-6.5/common/words/within.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( n min max -- f)
-; Compare
-; check if n is within min..max
-
-.if cpu_msp430==1
- HEADER(XT_WITHIN,6,"within",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_WITHIN:
- .dw $ff06
- .db "within"
- .dw VE_HEAD
- .set VE_HEAD = VE_WITHIN
-XT_WITHIN:
- .dw DO_COLON
-PFA_WITHIN:
-.endif
- .dw XT_OVER
- .dw XT_MINUS
- .dw XT_TO_R
- .dw XT_MINUS
- .dw XT_R_FROM
- .dw XT_ULESS
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/word.asm b/amforth-6.5/common/words/word.asm
deleted file mode 100644
index 9f24f85..0000000
--- a/amforth-6.5/common/words/word.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( c -- addr )
-; Tools
-; skip leading delimiter character and parse SOURCE until the next delimiter. copy the word to HERE
-
-.if cpu_msp430==1
- HEADER(XT_WORD,4,"word",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-VE_WORD:
- .dw $ff04
- .db "word"
- .dw VE_HEAD
- .set VE_HEAD = VE_WORD
-XT_WORD:
- .dw DO_COLON
-PFA_WORD:
-.endif
- .dw XT_SKIPSCANCHAR ; factor for both parse/word
- ; move to HERE
- .dw XT_HERE
- .dw XT_PLACE
- ; leave result
- .dw XT_HERE
- .dw XT_EXIT
diff --git a/amforth-6.5/common/words/words.asm b/amforth-6.5/common/words/words.asm
deleted file mode 100644
index a6f345e..0000000
--- a/amforth-6.5/common/words/words.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-; ( -- )
-; Tools
-; prints a list of all (visible) words in the dictionary
-
-.if cpu_msp430==1
- HEADER(XT_WORDS,5,"words",DOCOLON)
-.endif
-
-.if cpu_avr8==1
-
-
-VE_WORDS:
- .dw $ff05
- .db "words",0
- .dw VE_HEAD
- .set VE_HEAD = VE_WORDS
-XT_WORDS:
- .dw DO_COLON
-PFA_WORDS:
-.endif
- .dw XT_DOLITERAL
- .dw CFG_ORDERLISTLEN+2
- .dw XT_FETCHE
- .dw XT_SHOWWORDLIST
- .dw XT_EXIT
diff --git a/amforth-6.5/doc/AmForth.epub b/amforth-6.5/doc/AmForth.epub
deleted file mode 100644
index 8d1e828..0000000
--- a/amforth-6.5/doc/AmForth.epub
+++ /dev/null
Binary files differ
diff --git a/amforth-6.5/doc/amforth.pdf b/amforth-6.5/doc/amforth.pdf
deleted file mode 100644
index a337298..0000000
--- a/amforth-6.5/doc/amforth.pdf
+++ /dev/null
Binary files differ
diff --git a/amforth-6.5/doc/tools/_mapping.py b/amforth-6.5/doc/tools/_mapping.py
deleted file mode 100644
index 6feea17..0000000
--- a/amforth-6.5/doc/tools/_mapping.py
+++ /dev/null
@@ -1,293 +0,0 @@
-# -*- coding: utf-8 -*-
-"""
- pygments.lexers._mapping
- ~~~~~~~~~~~~~~~~~~~~~~~~
-
- Lexer mapping defintions. This file is generated by itself. Everytime
- you change something on a builtin lexer defintion, run this script from
- the lexers folder to update it.
-
- Do not alter the LEXERS dictionary by hand.
-
- :copyright: Copyright 2006-2012 by the Pygments team, see AUTHORS.
- :license: BSD, see LICENSE for details.
-"""
-
-LEXERS = {
- 'ABAPLexer': ('pygments.lexers.other', 'ABAP', ('abap',), ('*.abap',), ('text/x-abap',)),
- 'ActionScript3Lexer': ('pygments.lexers.web', 'ActionScript 3', ('as3', 'actionscript3'), ('*.as',), ('application/x-actionscript', 'text/x-actionscript', 'text/actionscript')),
- 'ActionScriptLexer': ('pygments.lexers.web', 'ActionScript', ('as', 'actionscript'), ('*.as',), ('application/x-actionscript3', 'text/x-actionscript3', 'text/actionscript3')),
- 'AdaLexer': ('pygments.lexers.compiled', 'Ada', ('ada', 'ada95ada2005'), ('*.adb', '*.ads', '*.ada'), ('text/x-ada',)),
- 'AntlrActionScriptLexer': ('pygments.lexers.parsers', 'ANTLR With ActionScript Target', ('antlr-as', 'antlr-actionscript'), ('*.G', '*.g'), ()),
- 'AntlrCSharpLexer': ('pygments.lexers.parsers', 'ANTLR With C# Target', ('antlr-csharp', 'antlr-c#'), ('*.G', '*.g'), ()),
- 'AntlrCppLexer': ('pygments.lexers.parsers', 'ANTLR With CPP Target', ('antlr-cpp',), ('*.G', '*.g'), ()),
- 'AntlrJavaLexer': ('pygments.lexers.parsers', 'ANTLR With Java Target', ('antlr-java',), ('*.G', '*.g'), ()),
- 'AntlrLexer': ('pygments.lexers.parsers', 'ANTLR', ('antlr',), (), ()),
- 'AntlrObjectiveCLexer': ('pygments.lexers.parsers', 'ANTLR With ObjectiveC Target', ('antlr-objc',), ('*.G', '*.g'), ()),
- 'AntlrPerlLexer': ('pygments.lexers.parsers', 'ANTLR With Perl Target', ('antlr-perl',), ('*.G', '*.g'), ()),
- 'AntlrPythonLexer': ('pygments.lexers.parsers', 'ANTLR With Python Target', ('antlr-python',), ('*.G', '*.g'), ()),
- 'AntlrRubyLexer': ('pygments.lexers.parsers', 'ANTLR With Ruby Target', ('antlr-ruby', 'antlr-rb'), ('*.G', '*.g'), ()),
- 'ApacheConfLexer': ('pygments.lexers.text', 'ApacheConf', ('apacheconf', 'aconf', 'apache'), ('.htaccess', 'apache.conf', 'apache2.conf'), ('text/x-apacheconf',)),
- 'AppleScriptLexer': ('pygments.lexers.other', 'AppleScript', ('applescript',), ('*.applescript',), ()),
- 'AsymptoteLexer': ('pygments.lexers.other', 'Asymptote', ('asy', 'asymptote'), ('*.asy',), ('text/x-asymptote',)),
- 'AutohotkeyLexer': ('pygments.lexers.other', 'autohotkey', ('ahk',), ('*.ahk', '*.ahkl'), ('text/x-autohotkey',)),
- 'AwkLexer': ('pygments.lexers.other', 'Awk', ('awk', 'gawk', 'mawk', 'nawk'), ('*.awk',), ('application/x-awk',)),
- 'BBCodeLexer': ('pygments.lexers.text', 'BBCode', ('bbcode',), (), ('text/x-bbcode',)),
- 'BaseMakefileLexer': ('pygments.lexers.text', 'Base Makefile', ('basemake',), (), ()),
- 'BashLexer': ('pygments.lexers.shell', 'Bash', ('bash', 'sh', 'ksh'), ('*.sh', '*.ksh', '*.bash', '*.ebuild', '*.eclass', '.bashrc', 'bashrc', '.bash_*', 'bash_*'), ('application/x-sh', 'application/x-shellscript')),
- 'BashSessionLexer': ('pygments.lexers.shell', 'Bash Session', ('console',), ('*.sh-session',), ('application/x-shell-session',)),
- 'BatchLexer': ('pygments.lexers.shell', 'Batchfile', ('bat',), ('*.bat', '*.cmd'), ('application/x-dos-batch',)),
- 'BefungeLexer': ('pygments.lexers.other', 'Befunge', ('befunge',), ('*.befunge',), ('application/x-befunge',)),
- 'BlitzMaxLexer': ('pygments.lexers.compiled', 'BlitzMax', ('blitzmax', 'bmax'), ('*.bmx',), ('text/x-bmx',)),
- 'BooLexer': ('pygments.lexers.dotnet', 'Boo', ('boo',), ('*.boo',), ('text/x-boo',)),
- 'BrainfuckLexer': ('pygments.lexers.other', 'Brainfuck', ('brainfuck', 'bf'), ('*.bf', '*.b'), ('application/x-brainfuck',)),
- 'BroLexer': ('pygments.lexers.other', 'Bro', ('bro',), ('*.bro',), ()),
- 'CLexer': ('pygments.lexers.compiled', 'C', ('c',), ('*.c', '*.h', '*.idc'), ('text/x-chdr', 'text/x-csrc')),
- 'CMakeLexer': ('pygments.lexers.text', 'CMake', ('cmake',), ('*.cmake', 'CMakeLists.txt'), ('text/x-cmake',)),
- 'CObjdumpLexer': ('pygments.lexers.asm', 'c-objdump', ('c-objdump',), ('*.c-objdump',), ('text/x-c-objdump',)),
- 'CSharpAspxLexer': ('pygments.lexers.dotnet', 'aspx-cs', ('aspx-cs',), ('*.aspx', '*.asax', '*.ascx', '*.ashx', '*.asmx', '*.axd'), ()),
- 'CSharpLexer': ('pygments.lexers.dotnet', 'C#', ('csharp', 'c#'), ('*.cs',), ('text/x-csharp',)),
- 'Cfengine3Lexer': ('pygments.lexers.other', 'CFEngine3', ('cfengine3', 'cf3'), ('*.cf',), ()),
- 'CheetahHtmlLexer': ('pygments.lexers.templates', 'HTML+Cheetah', ('html+cheetah', 'html+spitfire'), (), ('text/html+cheetah', 'text/html+spitfire')),
- 'CheetahJavascriptLexer': ('pygments.lexers.templates', 'JavaScript+Cheetah', ('js+cheetah', 'javascript+cheetah', 'js+spitfire', 'javascript+spitfire'), (), ('application/x-javascript+cheetah', 'text/x-javascript+cheetah', 'text/javascript+cheetah', 'application/x-javascript+spitfire', 'text/x-javascript+spitfire', 'text/javascript+spitfire')),
- 'CheetahLexer': ('pygments.lexers.templates', 'Cheetah', ('cheetah', 'spitfire'), ('*.tmpl', '*.spt'), ('application/x-cheetah', 'application/x-spitfire')),
- 'CheetahXmlLexer': ('pygments.lexers.templates', 'XML+Cheetah', ('xml+cheetah', 'xml+spitfire'), (), ('application/xml+cheetah', 'application/xml+spitfire')),
- 'ClojureLexer': ('pygments.lexers.jvm', 'Clojure', ('clojure', 'clj'), ('*.clj',), ('text/x-clojure', 'application/x-clojure')),
- 'CoffeeScriptLexer': ('pygments.lexers.web', 'CoffeeScript', ('coffee-script', 'coffeescript'), ('*.coffee',), ('text/coffeescript',)),
- 'ColdfusionHtmlLexer': ('pygments.lexers.templates', 'Coldfusion HTML', ('cfm',), ('*.cfm', '*.cfml', '*.cfc'), ('application/x-coldfusion',)),
- 'ColdfusionLexer': ('pygments.lexers.templates', 'cfstatement', ('cfs',), (), ()),
- 'CommonLispLexer': ('pygments.lexers.functional', 'Common Lisp', ('common-lisp', 'cl'), ('*.cl', '*.lisp', '*.el'), ('text/x-common-lisp',)),
- 'CoqLexer': ('pygments.lexers.functional', 'Coq', ('coq',), ('*.v',), ('text/x-coq',)),
- 'CppLexer': ('pygments.lexers.compiled', 'C++', ('cpp', 'c++'), ('*.cpp', '*.hpp', '*.c++', '*.h++', '*.cc', '*.hh', '*.cxx', '*.hxx'), ('text/x-c++hdr', 'text/x-c++src')),
- 'CppObjdumpLexer': ('pygments.lexers.asm', 'cpp-objdump', ('cpp-objdump', 'c++-objdumb', 'cxx-objdump'), ('*.cpp-objdump', '*.c++-objdump', '*.cxx-objdump'), ('text/x-cpp-objdump',)),
- 'CssDjangoLexer': ('pygments.lexers.templates', 'CSS+Django/Jinja', ('css+django', 'css+jinja'), (), ('text/css+django', 'text/css+jinja')),
- 'CssErbLexer': ('pygments.lexers.templates', 'CSS+Ruby', ('css+erb', 'css+ruby'), (), ('text/css+ruby',)),
- 'CssGenshiLexer': ('pygments.lexers.templates', 'CSS+Genshi Text', ('css+genshitext', 'css+genshi'), (), ('text/css+genshi',)),
- 'CssLexer': ('pygments.lexers.web', 'CSS', ('css',), ('*.css',), ('text/css',)),
- 'CssPhpLexer': ('pygments.lexers.templates', 'CSS+PHP', ('css+php',), (), ('text/css+php',)),
- 'CssSmartyLexer': ('pygments.lexers.templates', 'CSS+Smarty', ('css+smarty',), (), ('text/css+smarty',)),
- 'CythonLexer': ('pygments.lexers.compiled', 'Cython', ('cython', 'pyx'), ('*.pyx', '*.pxd', '*.pxi'), ('text/x-cython', 'application/x-cython')),
- 'DLexer': ('pygments.lexers.compiled', 'D', ('d',), ('*.d', '*.di'), ('text/x-dsrc',)),
- 'DObjdumpLexer': ('pygments.lexers.asm', 'd-objdump', ('d-objdump',), ('*.d-objdump',), ('text/x-d-objdump',)),
- 'DarcsPatchLexer': ('pygments.lexers.text', 'Darcs Patch', ('dpatch',), ('*.dpatch', '*.darcspatch'), ()),
- 'DartLexer': ('pygments.lexers.web', 'Dart', ('dart',), ('*.dart',), ('text/x-dart',)),
- 'DebianControlLexer': ('pygments.lexers.text', 'Debian Control file', ('control',), ('control',), ()),
- 'DelphiLexer': ('pygments.lexers.compiled', 'Delphi', ('delphi', 'pas', 'pascal', 'objectpascal'), ('*.pas',), ('text/x-pascal',)),
- 'DiffLexer': ('pygments.lexers.text', 'Diff', ('diff', 'udiff'), ('*.diff', '*.patch'), ('text/x-diff', 'text/x-patch')),
- 'DjangoLexer': ('pygments.lexers.templates', 'Django/Jinja', ('django', 'jinja'), (), ('application/x-django-templating', 'application/x-jinja')),
- 'DtdLexer': ('pygments.lexers.web', 'DTD', ('dtd',), ('*.dtd',), ('application/xml-dtd',)),
- 'DuelLexer': ('pygments.lexers.web', 'Duel', ('duel', 'Duel Engine', 'Duel View', 'JBST', 'jbst', 'JsonML+BST'), ('*.duel', '*.jbst'), ('text/x-duel', 'text/x-jbst')),
- 'DylanLexer': ('pygments.lexers.compiled', 'Dylan', ('dylan',), ('*.dylan', '*.dyl'), ('text/x-dylan',)),
- 'ECLLexer': ('pygments.lexers.other', 'ECL', ('ecl',), ('*.ecl',), ('application/x-ecl',)),
- 'ECLexer': ('pygments.lexers.compiled', 'eC', ('ec',), ('*.ec', '*.eh'), ('text/x-echdr', 'text/x-ecsrc')),
- 'ElixirConsoleLexer': ('pygments.lexers.functional', 'Elixir iex session', ('iex',), (), ('text/x-elixir-shellsession',)),
- 'ElixirLexer': ('pygments.lexers.functional', 'Elixir', ('elixir', 'ex', 'exs'), ('*.ex', '*.exs'), ('text/x-elixir',)),
- 'ErbLexer': ('pygments.lexers.templates', 'ERB', ('erb',), (), ('application/x-ruby-templating',)),
- 'ErlangLexer': ('pygments.lexers.functional', 'Erlang', ('erlang',), ('*.erl', '*.hrl', '*.es', '*.escript'), ('text/x-erlang',)),
- 'ErlangShellLexer': ('pygments.lexers.functional', 'Erlang erl session', ('erl',), ('*.erl-sh',), ('text/x-erl-shellsession',)),
- 'EvoqueHtmlLexer': ('pygments.lexers.templates', 'HTML+Evoque', ('html+evoque',), ('*.html',), ('text/html+evoque',)),
- 'EvoqueLexer': ('pygments.lexers.templates', 'Evoque', ('evoque',), ('*.evoque',), ('application/x-evoque',)),
- 'EvoqueXmlLexer': ('pygments.lexers.templates', 'XML+Evoque', ('xml+evoque',), ('*.xml',), ('application/xml+evoque',)),
- 'FSharpLexer': ('pygments.lexers.dotnet', 'FSharp', ('fsharp',), ('*.fs', '*.fsi'), ('text/x-fsharp',)),
- 'FactorLexer': ('pygments.lexers.agile', 'Factor', ('factor',), ('*.factor',), ('text/x-factor',)),
- 'FancyLexer': ('pygments.lexers.agile', 'Fancy', ('fancy', 'fy'), ('*.fy', '*.fancypack'), ('text/x-fancysrc',)),
- 'FantomLexer': ('pygments.lexers.compiled', 'Fantom', ('fan',), ('*.fan',), ('application/x-fantom',)),
- 'FelixLexer': ('pygments.lexers.compiled', 'Felix', ('felix', 'flx'), ('*.flx', '*.flxh'), ('text/x-felix',)),
- 'FortranLexer': ('pygments.lexers.compiled', 'Fortran', ('fortran',), ('*.f', '*.f90', '*.F', '*.F90'), ('text/x-fortran',)),
- 'ForthLexer': ('pygments.lexers.forth', 'Forth', ('forth',), ('*.frt', '*.fs'), ('application/x-forth',)),
- 'GLShaderLexer': ('pygments.lexers.compiled', 'GLSL', ('glsl',), ('*.vert', '*.frag', '*.geo'), ('text/x-glslsrc',)),
- 'GasLexer': ('pygments.lexers.asm', 'GAS', ('gas',), ('*.s', '*.S'), ('text/x-gas',)),
- 'GenshiLexer': ('pygments.lexers.templates', 'Genshi', ('genshi', 'kid', 'xml+genshi', 'xml+kid'), ('*.kid',), ('application/x-genshi', 'application/x-kid')),
- 'GenshiTextLexer': ('pygments.lexers.templates', 'Genshi Text', ('genshitext',), (), ('application/x-genshi-text', 'text/x-genshi')),
- 'GettextLexer': ('pygments.lexers.text', 'Gettext Catalog', ('pot', 'po'), ('*.pot', '*.po'), ('application/x-gettext', 'text/x-gettext', 'text/gettext')),
- 'GherkinLexer': ('pygments.lexers.other', 'Gherkin', ('Cucumber', 'cucumber', 'Gherkin', 'gherkin'), ('*.feature',), ('text/x-gherkin',)),
- 'GnuplotLexer': ('pygments.lexers.other', 'Gnuplot', ('gnuplot',), ('*.plot', '*.plt'), ('text/x-gnuplot',)),
- 'GoLexer': ('pygments.lexers.compiled', 'Go', ('go',), ('*.go',), ('text/x-gosrc',)),
- 'GoodDataCLLexer': ('pygments.lexers.other', 'GoodData-CL', ('gooddata-cl',), ('*.gdc',), ('text/x-gooddata-cl',)),
- 'GosuLexer': ('pygments.lexers.jvm', 'Gosu', ('gosu',), ('*.gs', '*.gsx', '*.gsp', '*.vark'), ('text/x-gosu',)),
- 'GosuTemplateLexer': ('pygments.lexers.jvm', 'Gosu Template', ('gst',), ('*.gst',), ('text/x-gosu-template',)),
- 'GroffLexer': ('pygments.lexers.text', 'Groff', ('groff', 'nroff', 'man'), ('*.[1234567]', '*.man'), ('application/x-troff', 'text/troff')),
- 'GroovyLexer': ('pygments.lexers.jvm', 'Groovy', ('groovy',), ('*.groovy',), ('text/x-groovy',)),
- 'HamlLexer': ('pygments.lexers.web', 'Haml', ('haml', 'HAML'), ('*.haml',), ('text/x-haml',)),
- 'HaskellLexer': ('pygments.lexers.functional', 'Haskell', ('haskell', 'hs'), ('*.hs',), ('text/x-haskell',)),
- 'HaxeLexer': ('pygments.lexers.web', 'haXe', ('hx', 'haXe'), ('*.hx',), ('text/haxe',)),
- 'HtmlDjangoLexer': ('pygments.lexers.templates', 'HTML+Django/Jinja', ('html+django', 'html+jinja'), (), ('text/html+django', 'text/html+jinja')),
- 'HtmlGenshiLexer': ('pygments.lexers.templates', 'HTML+Genshi', ('html+genshi', 'html+kid'), (), ('text/html+genshi',)),
- 'HtmlLexer': ('pygments.lexers.web', 'HTML', ('html',), ('*.html', '*.htm', '*.xhtml', '*.xslt'), ('text/html', 'application/xhtml+xml')),
- 'HtmlPhpLexer': ('pygments.lexers.templates', 'HTML+PHP', ('html+php',), ('*.phtml',), ('application/x-php', 'application/x-httpd-php', 'application/x-httpd-php3', 'application/x-httpd-php4', 'application/x-httpd-php5')),
- 'HtmlSmartyLexer': ('pygments.lexers.templates', 'HTML+Smarty', ('html+smarty',), (), ('text/html+smarty',)),
- 'HttpLexer': ('pygments.lexers.text', 'HTTP', ('http',), (), ()),
- 'HybrisLexer': ('pygments.lexers.other', 'Hybris', ('hybris', 'hy'), ('*.hy', '*.hyb'), ('text/x-hybris', 'application/x-hybris')),
- 'IniLexer': ('pygments.lexers.text', 'INI', ('ini', 'cfg'), ('*.ini', '*.cfg'), ('text/x-ini',)),
- 'IoLexer': ('pygments.lexers.agile', 'Io', ('io',), ('*.io',), ('text/x-iosrc',)),
- 'IokeLexer': ('pygments.lexers.jvm', 'Ioke', ('ioke', 'ik'), ('*.ik',), ('text/x-iokesrc',)),
- 'IrcLogsLexer': ('pygments.lexers.text', 'IRC logs', ('irc',), ('*.weechatlog',), ('text/x-irclog',)),
- 'JSONLexer': ('pygments.lexers.web', 'JSON', ('json',), ('*.json',), ('application/json',)),
- 'JadeLexer': ('pygments.lexers.web', 'Jade', ('jade', 'JADE'), ('*.jade',), ('text/x-jade',)),
- 'JavaLexer': ('pygments.lexers.jvm', 'Java', ('java',), ('*.java',), ('text/x-java',)),
- 'JavascriptDjangoLexer': ('pygments.lexers.templates', 'JavaScript+Django/Jinja', ('js+django', 'javascript+django', 'js+jinja', 'javascript+jinja'), (), ('application/x-javascript+django', 'application/x-javascript+jinja', 'text/x-javascript+django', 'text/x-javascript+jinja', 'text/javascript+django', 'text/javascript+jinja')),
- 'JavascriptErbLexer': ('pygments.lexers.templates', 'JavaScript+Ruby', ('js+erb', 'javascript+erb', 'js+ruby', 'javascript+ruby'), (), ('application/x-javascript+ruby', 'text/x-javascript+ruby', 'text/javascript+ruby')),
- 'JavascriptGenshiLexer': ('pygments.lexers.templates', 'JavaScript+Genshi Text', ('js+genshitext', 'js+genshi', 'javascript+genshitext', 'javascript+genshi'), (), ('application/x-javascript+genshi', 'text/x-javascript+genshi', 'text/javascript+genshi')),
- 'JavascriptLexer': ('pygments.lexers.web', 'JavaScript', ('js', 'javascript'), ('*.js',), ('application/javascript', 'application/x-javascript', 'text/x-javascript', 'text/javascript')),
- 'JavascriptPhpLexer': ('pygments.lexers.templates', 'JavaScript+PHP', ('js+php', 'javascript+php'), (), ('application/x-javascript+php', 'text/x-javascript+php', 'text/javascript+php')),
- 'JavascriptSmartyLexer': ('pygments.lexers.templates', 'JavaScript+Smarty', ('js+smarty', 'javascript+smarty'), (), ('application/x-javascript+smarty', 'text/x-javascript+smarty', 'text/javascript+smarty')),
- 'JspLexer': ('pygments.lexers.templates', 'Java Server Page', ('jsp',), ('*.jsp',), ('application/x-jsp',)),
- 'KotlinLexer': ('pygments.lexers.jvm', 'Kotlin', ('kotlin',), ('*.kt',), ('text/x-kotlin',)),
- 'LighttpdConfLexer': ('pygments.lexers.text', 'Lighttpd configuration file', ('lighty', 'lighttpd'), (), ('text/x-lighttpd-conf',)),
- 'LiterateHaskellLexer': ('pygments.lexers.functional', 'Literate Haskell', ('lhs', 'literate-haskell'), ('*.lhs',), ('text/x-literate-haskell',)),
- 'LlvmLexer': ('pygments.lexers.asm', 'LLVM', ('llvm',), ('*.ll',), ('text/x-llvm',)),
- 'LogtalkLexer': ('pygments.lexers.other', 'Logtalk', ('logtalk',), ('*.lgt',), ('text/x-logtalk',)),
- 'LuaLexer': ('pygments.lexers.agile', 'Lua', ('lua',), ('*.lua', '*.wlua'), ('text/x-lua', 'application/x-lua')),
- 'MOOCodeLexer': ('pygments.lexers.other', 'MOOCode', ('moocode',), ('*.moo',), ('text/x-moocode',)),
- 'MakefileLexer': ('pygments.lexers.text', 'Makefile', ('make', 'makefile', 'mf', 'bsdmake'), ('*.mak', 'Makefile', 'makefile', 'Makefile.*', 'GNUmakefile'), ('text/x-makefile',)),
- 'MakoCssLexer': ('pygments.lexers.templates', 'CSS+Mako', ('css+mako',), (), ('text/css+mako',)),
- 'MakoHtmlLexer': ('pygments.lexers.templates', 'HTML+Mako', ('html+mako',), (), ('text/html+mako',)),
- 'MakoJavascriptLexer': ('pygments.lexers.templates', 'JavaScript+Mako', ('js+mako', 'javascript+mako'), (), ('application/x-javascript+mako', 'text/x-javascript+mako', 'text/javascript+mako')),
- 'MakoLexer': ('pygments.lexers.templates', 'Mako', ('mako',), ('*.mao',), ('application/x-mako',)),
- 'MakoXmlLexer': ('pygments.lexers.templates', 'XML+Mako', ('xml+mako',), (), ('application/xml+mako',)),
- 'MaqlLexer': ('pygments.lexers.other', 'MAQL', ('maql',), ('*.maql',), ('text/x-gooddata-maql', 'application/x-gooddata-maql')),
- 'MasonLexer': ('pygments.lexers.templates', 'Mason', ('mason',), ('*.m', '*.mhtml', '*.mc', '*.mi', 'autohandler', 'dhandler'), ('application/x-mason',)),
- 'MatlabLexer': ('pygments.lexers.math', 'Matlab', ('matlab',), ('*.m',), ('text/matlab',)),
- 'MatlabSessionLexer': ('pygments.lexers.math', 'Matlab session', ('matlabsession',), (), ()),
- 'MiniDLexer': ('pygments.lexers.agile', 'MiniD', ('minid',), ('*.md',), ('text/x-minidsrc',)),
- 'ModelicaLexer': ('pygments.lexers.other', 'Modelica', ('modelica',), ('*.mo',), ('text/x-modelica',)),
- 'Modula2Lexer': ('pygments.lexers.compiled', 'Modula-2', ('modula2', 'm2'), ('*.def', '*.mod'), ('text/x-modula2',)),
- 'MoinWikiLexer': ('pygments.lexers.text', 'MoinMoin/Trac Wiki markup', ('trac-wiki', 'moin'), (), ('text/x-trac-wiki',)),
- 'MoonScriptLexer': ('pygments.lexers.agile', 'MoonScript', ('moon', 'moonscript'), ('*.moon',), ('text/x-moonscript', 'application/x-moonscript')),
- 'MuPADLexer': ('pygments.lexers.math', 'MuPAD', ('mupad',), ('*.mu',), ()),
- 'MxmlLexer': ('pygments.lexers.web', 'MXML', ('mxml',), ('*.mxml',), ()),
- 'MySqlLexer': ('pygments.lexers.sql', 'MySQL', ('mysql',), (), ('text/x-mysql',)),
- 'MyghtyCssLexer': ('pygments.lexers.templates', 'CSS+Myghty', ('css+myghty',), (), ('text/css+myghty',)),
- 'MyghtyHtmlLexer': ('pygments.lexers.templates', 'HTML+Myghty', ('html+myghty',), (), ('text/html+myghty',)),
- 'MyghtyJavascriptLexer': ('pygments.lexers.templates', 'JavaScript+Myghty', ('js+myghty', 'javascript+myghty'), (), ('application/x-javascript+myghty', 'text/x-javascript+myghty', 'text/javascript+mygthy')),
- 'MyghtyLexer': ('pygments.lexers.templates', 'Myghty', ('myghty',), ('*.myt', 'autodelegate'), ('application/x-myghty',)),
- 'MyghtyXmlLexer': ('pygments.lexers.templates', 'XML+Myghty', ('xml+myghty',), (), ('application/xml+myghty',)),
- 'NasmLexer': ('pygments.lexers.asm', 'NASM', ('nasm',), ('*.asm', '*.ASM'), ('text/x-nasm',)),
- 'NemerleLexer': ('pygments.lexers.dotnet', 'Nemerle', ('nemerle',), ('*.n',), ('text/x-nemerle',)),
- 'NewLispLexer': ('pygments.lexers.functional', 'NewLisp', ('newlisp',), ('*.lsp', '*.nl'), ('text/x-newlisp', 'application/x-newlisp')),
- 'NewspeakLexer': ('pygments.lexers.other', 'Newspeak', ('newspeak',), ('*.ns2',), ('text/x-newspeak',)),
- 'NginxConfLexer': ('pygments.lexers.text', 'Nginx configuration file', ('nginx',), (), ('text/x-nginx-conf',)),
- 'NimrodLexer': ('pygments.lexers.compiled', 'Nimrod', ('nimrod', 'nim'), ('*.nim', '*.nimrod'), ('text/x-nimrod',)),
- 'NumPyLexer': ('pygments.lexers.math', 'NumPy', ('numpy',), (), ()),
- 'ObjdumpLexer': ('pygments.lexers.asm', 'objdump', ('objdump',), ('*.objdump',), ('text/x-objdump',)),
- 'ObjectiveCLexer': ('pygments.lexers.compiled', 'Objective-C', ('objective-c', 'objectivec', 'obj-c', 'objc'), ('*.m',), ('text/x-objective-c',)),
- 'ObjectiveJLexer': ('pygments.lexers.web', 'Objective-J', ('objective-j', 'objectivej', 'obj-j', 'objj'), ('*.j',), ('text/x-objective-j',)),
- 'OcamlLexer': ('pygments.lexers.functional', 'OCaml', ('ocaml',), ('*.ml', '*.mli', '*.mll', '*.mly'), ('text/x-ocaml',)),
- 'OctaveLexer': ('pygments.lexers.math', 'Octave', ('octave',), ('*.m',), ('text/octave',)),
- 'OocLexer': ('pygments.lexers.compiled', 'Ooc', ('ooc',), ('*.ooc',), ('text/x-ooc',)),
- 'OpaLexer': ('pygments.lexers.functional', 'Opa', ('opa',), ('*.opa',), ('text/x-opa',)),
- 'OpenEdgeLexer': ('pygments.lexers.other', 'OpenEdge ABL', ('openedge', 'abl', 'progress'), ('*.p', '*.cls'), ('text/x-openedge', 'application/x-openedge')),
- 'PerlLexer': ('pygments.lexers.agile', 'Perl', ('perl', 'pl'), ('*.pl', '*.pm'), ('text/x-perl', 'application/x-perl')),
- 'PhpLexer': ('pygments.lexers.web', 'PHP', ('php', 'php3', 'php4', 'php5'), ('*.php', '*.php[345]'), ('text/x-php',)),
- 'PlPgsqlLexer': ('pygments.lexers.sql', 'PL/pgSQL', ('plpgsql',), (), ('text/x-plpgsql',)),
- 'PostScriptLexer': ('pygments.lexers.other', 'PostScript', ('postscript',), ('*.ps', '*.eps'), ('application/postscript',)),
- 'PostgresConsoleLexer': ('pygments.lexers.sql', 'PostgreSQL console (psql)', ('psql', 'postgresql-console', 'postgres-console'), (), ('text/x-postgresql-psql',)),
- 'PostgresLexer': ('pygments.lexers.sql', 'PostgreSQL SQL dialect', ('postgresql', 'postgres'), (), ('text/x-postgresql',)),
- 'PovrayLexer': ('pygments.lexers.other', 'POVRay', ('pov',), ('*.pov', '*.inc'), ('text/x-povray',)),
- 'PowerShellLexer': ('pygments.lexers.shell', 'PowerShell', ('powershell', 'posh', 'ps1'), ('*.ps1',), ('text/x-powershell',)),
- 'PrologLexer': ('pygments.lexers.compiled', 'Prolog', ('prolog',), ('*.prolog', '*.pro', '*.pl'), ('text/x-prolog',)),
- 'PropertiesLexer': ('pygments.lexers.text', 'Properties', ('properties',), ('*.properties',), ('text/x-java-properties',)),
- 'ProtoBufLexer': ('pygments.lexers.other', 'Protocol Buffer', ('protobuf',), ('*.proto',), ()),
- 'PyPyLogLexer': ('pygments.lexers.text', 'PyPy Log', ('pypylog', 'pypy'), ('*.pypylog',), ('application/x-pypylog',)),
- 'Python3Lexer': ('pygments.lexers.agile', 'Python 3', ('python3', 'py3'), (), ('text/x-python3', 'application/x-python3')),
- 'Python3TracebackLexer': ('pygments.lexers.agile', 'Python 3.0 Traceback', ('py3tb',), ('*.py3tb',), ('text/x-python3-traceback',)),
- 'PythonConsoleLexer': ('pygments.lexers.agile', 'Python console session', ('pycon',), (), ('text/x-python-doctest',)),
- 'PythonLexer': ('pygments.lexers.agile', 'Python', ('python', 'py'), ('*.py', '*.pyw', '*.sc', 'SConstruct', 'SConscript', '*.tac'), ('text/x-python', 'application/x-python')),
- 'PythonTracebackLexer': ('pygments.lexers.agile', 'Python Traceback', ('pytb',), ('*.pytb',), ('text/x-python-traceback',)),
- 'RConsoleLexer': ('pygments.lexers.math', 'RConsole', ('rconsole', 'rout'), ('*.Rout',), ()),
- 'RagelCLexer': ('pygments.lexers.parsers', 'Ragel in C Host', ('ragel-c',), ('*.rl',), ()),
- 'RagelCppLexer': ('pygments.lexers.parsers', 'Ragel in CPP Host', ('ragel-cpp',), ('*.rl',), ()),
- 'RagelDLexer': ('pygments.lexers.parsers', 'Ragel in D Host', ('ragel-d',), ('*.rl',), ()),
- 'RagelEmbeddedLexer': ('pygments.lexers.parsers', 'Embedded Ragel', ('ragel-em',), ('*.rl',), ()),
- 'RagelJavaLexer': ('pygments.lexers.parsers', 'Ragel in Java Host', ('ragel-java',), ('*.rl',), ()),
- 'RagelLexer': ('pygments.lexers.parsers', 'Ragel', ('ragel',), (), ()),
- 'RagelObjectiveCLexer': ('pygments.lexers.parsers', 'Ragel in Objective C Host', ('ragel-objc',), ('*.rl',), ()),
- 'RagelRubyLexer': ('pygments.lexers.parsers', 'Ragel in Ruby Host', ('ragel-ruby', 'ragel-rb'), ('*.rl',), ()),
- 'RawTokenLexer': ('pygments.lexers.special', 'Raw token data', ('raw',), (), ('application/x-pygments-tokens',)),
- 'RebolLexer': ('pygments.lexers.other', 'REBOL', ('rebol',), ('*.r', '*.r3'), ('text/x-rebol',)),
- 'RedcodeLexer': ('pygments.lexers.other', 'Redcode', ('redcode',), ('*.cw',), ()),
- 'RhtmlLexer': ('pygments.lexers.templates', 'RHTML', ('rhtml', 'html+erb', 'html+ruby'), ('*.rhtml',), ('text/html+ruby',)),
- 'RstLexer': ('pygments.lexers.text', 'reStructuredText', ('rst', 'rest', 'restructuredtext'), ('*.rst', '*.rest'), ('text/x-rst', 'text/prs.fallenstein.rst')),
- 'RubyConsoleLexer': ('pygments.lexers.agile', 'Ruby irb session', ('rbcon', 'irb'), (), ('text/x-ruby-shellsession',)),
- 'RubyLexer': ('pygments.lexers.agile', 'Ruby', ('rb', 'ruby', 'duby'), ('*.rb', '*.rbw', 'Rakefile', '*.rake', '*.gemspec', '*.rbx', '*.duby'), ('text/x-ruby', 'application/x-ruby')),
- 'SLexer': ('pygments.lexers.math', 'S', ('splus', 's', 'r'), ('*.S', '*.R'), ('text/S-plus', 'text/S', 'text/R')),
- 'SMLLexer': ('pygments.lexers.functional', 'Standard ML', ('sml',), ('*.sml', '*.sig', '*.fun'), ('text/x-standardml', 'application/x-standardml')),
- 'SassLexer': ('pygments.lexers.web', 'Sass', ('sass', 'SASS'), ('*.sass',), ('text/x-sass',)),
- 'ScalaLexer': ('pygments.lexers.jvm', 'Scala', ('scala',), ('*.scala',), ('text/x-scala',)),
- 'ScamlLexer': ('pygments.lexers.web', 'Scaml', ('scaml', 'SCAML'), ('*.scaml',), ('text/x-scaml',)),
- 'SchemeLexer': ('pygments.lexers.functional', 'Scheme', ('scheme', 'scm'), ('*.scm', '*.ss', '*.rkt'), ('text/x-scheme', 'application/x-scheme')),
- 'ScilabLexer': ('pygments.lexers.math', 'Scilab', ('scilab',), ('*.sci', '*.sce', '*.tst'), ('text/scilab',)),
- 'ScssLexer': ('pygments.lexers.web', 'SCSS', ('scss',), ('*.scss',), ('text/x-scss',)),
- 'SmalltalkLexer': ('pygments.lexers.other', 'Smalltalk', ('smalltalk', 'squeak'), ('*.st',), ('text/x-smalltalk',)),
- 'SmartyLexer': ('pygments.lexers.templates', 'Smarty', ('smarty',), ('*.tpl',), ('application/x-smarty',)),
- 'SnobolLexer': ('pygments.lexers.other', 'Snobol', ('snobol',), ('*.snobol',), ('text/x-snobol',)),
- 'SourcesListLexer': ('pygments.lexers.text', 'Debian Sourcelist', ('sourceslist', 'sources.list'), ('sources.list',), ()),
- 'SqlLexer': ('pygments.lexers.sql', 'SQL', ('sql',), ('*.sql',), ('text/x-sql',)),
- 'SqliteConsoleLexer': ('pygments.lexers.sql', 'sqlite3con', ('sqlite3',), ('*.sqlite3-console',), ('text/x-sqlite3-console',)),
- 'SquidConfLexer': ('pygments.lexers.text', 'SquidConf', ('squidconf', 'squid.conf', 'squid'), ('squid.conf',), ('text/x-squidconf',)),
- 'SspLexer': ('pygments.lexers.templates', 'Scalate Server Page', ('ssp',), ('*.ssp',), ('application/x-ssp',)),
- 'SystemVerilogLexer': ('pygments.lexers.hdl', 'systemverilog', ('sv',), ('*.sv', '*.svh'), ('text/x-systemverilog',)),
- 'TclLexer': ('pygments.lexers.agile', 'Tcl', ('tcl',), ('*.tcl',), ('text/x-tcl', 'text/x-script.tcl', 'application/x-tcl')),
- 'TcshLexer': ('pygments.lexers.shell', 'Tcsh', ('tcsh', 'csh'), ('*.tcsh', '*.csh'), ('application/x-csh',)),
- 'TeaTemplateLexer': ('pygments.lexers.templates', 'Tea', ('tea',), ('*.tea',), ('text/x-tea',)),
- 'TexLexer': ('pygments.lexers.text', 'TeX', ('tex', 'latex'), ('*.tex', '*.aux', '*.toc'), ('text/x-tex', 'text/x-latex')),
- 'TextLexer': ('pygments.lexers.special', 'Text only', ('text',), ('*.txt',), ('text/plain',)),
- 'UrbiscriptLexer': ('pygments.lexers.other', 'UrbiScript', ('urbiscript',), ('*.u',), ('application/x-urbiscript',)),
- 'ValaLexer': ('pygments.lexers.compiled', 'Vala', ('vala', 'vapi'), ('*.vala', '*.vapi'), ('text/x-vala',)),
- 'VbNetAspxLexer': ('pygments.lexers.dotnet', 'aspx-vb', ('aspx-vb',), ('*.aspx', '*.asax', '*.ascx', '*.ashx', '*.asmx', '*.axd'), ()),
- 'VbNetLexer': ('pygments.lexers.dotnet', 'VB.net', ('vb.net', 'vbnet'), ('*.vb', '*.bas'), ('text/x-vbnet', 'text/x-vba')),
- 'VelocityHtmlLexer': ('pygments.lexers.templates', 'HTML+Velocity', ('html+velocity',), (), ('text/html+velocity',)),
- 'VelocityLexer': ('pygments.lexers.templates', 'Velocity', ('velocity',), ('*.vm', '*.fhtml'), ()),
- 'VelocityXmlLexer': ('pygments.lexers.templates', 'XML+Velocity', ('xml+velocity',), (), ('application/xml+velocity',)),
- 'VerilogLexer': ('pygments.lexers.hdl', 'verilog', ('v',), ('*.v',), ('text/x-verilog',)),
- 'VhdlLexer': ('pygments.lexers.hdl', 'vhdl', ('vhdl',), ('*.vhdl', '*.vhd'), ('text/x-vhdl',)),
- 'VimLexer': ('pygments.lexers.text', 'VimL', ('vim',), ('*.vim', '.vimrc', '.exrc', '.gvimrc', '_vimrc', '_exrc', '_gvimrc', 'vimrc', 'gvimrc'), ('text/x-vim',)),
- 'XQueryLexer': ('pygments.lexers.web', 'XQuery', ('xquery', 'xqy'), ('*.xqy', '*.xquery'), ('text/xquery', 'application/xquery')),
- 'XmlDjangoLexer': ('pygments.lexers.templates', 'XML+Django/Jinja', ('xml+django', 'xml+jinja'), (), ('application/xml+django', 'application/xml+jinja')),
- 'XmlErbLexer': ('pygments.lexers.templates', 'XML+Ruby', ('xml+erb', 'xml+ruby'), (), ('application/xml+ruby',)),
- 'XmlLexer': ('pygments.lexers.web', 'XML', ('xml',), ('*.xml', '*.xsl', '*.rss', '*.xslt', '*.xsd', '*.wsdl'), ('text/xml', 'application/xml', 'image/svg+xml', 'application/rss+xml', 'application/atom+xml')),
- 'XmlPhpLexer': ('pygments.lexers.templates', 'XML+PHP', ('xml+php',), (), ('application/xml+php',)),
- 'XmlSmartyLexer': ('pygments.lexers.templates', 'XML+Smarty', ('xml+smarty',), (), ('application/xml+smarty',)),
- 'XsltLexer': ('pygments.lexers.web', 'XSLT', ('xslt',), ('*.xsl', '*.xslt'), ('application/xsl+xml', 'application/xslt+xml')),
- 'YamlLexer': ('pygments.lexers.text', 'YAML', ('yaml',), ('*.yaml', '*.yml'), ('text/x-yaml',)),
-}
-
-if __name__ == '__main__':
- import sys
- import os
-
- # lookup lexers
- found_lexers = []
- sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..', '..'))
- for filename in os.listdir('.'):
- if filename.endswith('.py') and not filename.startswith('_'):
- module_name = 'pygments.lexers.%s' % filename[:-3]
- print module_name
- module = __import__(module_name, None, None, [''])
- for lexer_name in module.__all__:
- lexer = getattr(module, lexer_name)
- found_lexers.append(
- '%r: %r' % (lexer_name,
- (module_name,
- lexer.name,
- tuple(lexer.aliases),
- tuple(lexer.filenames),
- tuple(lexer.mimetypes))))
- # sort them, that should make the diff files for svn smaller
- found_lexers.sort()
-
- # extract useful sourcecode from this file
- f = open(__file__)
- try:
- content = f.read()
- finally:
- f.close()
- header = content[:content.find('LEXERS = {')]
- footer = content[content.find("if __name__ == '__main__':"):]
-
- # write new file
- f = open(__file__, 'w')
- f.write(header)
- f.write('LEXERS = {\n %s,\n}\n\n' % ',\n '.join(found_lexers))
- f.write(footer)
- f.close()
diff --git a/amforth-6.5/doc/tools/forth.py b/amforth-6.5/doc/tools/forth.py
deleted file mode 100644
index 7f5a121..0000000
--- a/amforth-6.5/doc/tools/forth.py
+++ /dev/null
@@ -1,184 +0,0 @@
-# -*- coding: utf-8 -*-
-"""
- pygments.lexers.forth
- ~~~~~~~~~~~~~~~~~~~~~
-
- :copyright: Copyright 2006-2012 by the Pygments team, see AUTHORS.
- :license: BSD, see LICENSE for details.
-"""
-
-import re
-
-from pygments.lexer import RegexLexer, include, bygroups, using, \
- this, combined, ExtendedRegexLexer
-from pygments.token import Error, Punctuation, Literal, Token, \
- Text, Comment, Operator, Keyword, Name, String, Number, Generic
-from pygments.lexers.web import HtmlLexer
-
-
-# backwards compatibility
-from pygments.lexers.sql import SqlLexer, MySqlLexer, SqliteConsoleLexer
-from pygments.lexers.shell import BashLexer, BashSessionLexer, BatchLexer, \
- TcshLexer
-
-__all__ = ['ForthLexer']
-
-
-class ForthLexer(RegexLexer):
- """
- Lexer for Forth files.
-
- *New in Pygments ??*
- """
- name = 'Forth'
- aliases = ['forth']
- filenames = ['*.frt', '*.fs']
- mimetypes = ['application/x-forth']
-
- delimiter = r'\s'
- delimiter_end = r'(?=[%s])' % delimiter
-
- valid_name_chars = r'[^%s]' % delimiter
- valid_name = r"%s+%s" % (valid_name_chars, delimiter_end)
-
- flags = re.IGNORECASE | re.MULTILINE
-
- tokens = {
- 'root': [
- (r'\s+', Text),
- # All comment types
- (r'\\.*?\n', Comment.Single),
- (r'\([\s].*?\)', Comment.Single),
- # defining words. The next word is a new command name
- (r'(:|variable|constant|value|buffer:)(\s+)',bygroups(Keyword.Namespace, Text), 'worddef'),
- # strings are rather simple
- (r'([\.sc]")(\s+?)', bygroups(String, Text), 'stringdef'),
- # keywords from the various wordsets
- # *** Wordset BLOCK
- (r'(blk|block|buffer|evaluate|flush|load|save-buffers|update|'
- # *** Wordset BLOCK-EXT
- r'empty-buffers|list|refill|scr|thru|'
- # *** Wordset CORE
- r'\#s|\*\/mod|\+loop|\/mod|0<|0=|1\+|1-|2!|'
- r'2\*|2\/|2@|2drop|2dup|2over|2swap|>body|'
- r'>in|>number|>r|\?dup|abort|abort\"|abs|'
- r'accept|align|aligned|allot|and|base|begin|'
- r'bl|c!|c,|c@|cell\+|cells|char|char\+|'
- r'chars|constant|count|cr|create|decimal|'
- r'depth|do|does>|drop|dup|else|emit|environment\?|'
- r'evaluate|execute|exit|fill|find|fm\/mod|'
- r'here|hold|i|if|immediate|invert|j|key|'
- r'leave|literal|loop|lshift|m\*|max|min|'
- r'mod|move|negate|or|over|postpone|quit|'
- r'r>|r@|recurse|repeat|rot|rshift|s\"|s>d|'
- r'sign|sm\/rem|source|space|spaces|state|swap|'
- r'then|type|u\.|u\<|um\*|um\/mod|unloop|until|'
- r'variable|while|word|xor|\[char\]|\[\'\]|'
- r'@|!|\#|<\#|\#>|:|;|\+|-|\*|\/|,|<|>|\|1\+|1-|\.|'
- # *** Wordset CORE-EXT
- r'\.r|0<>|'
- r'0>|2>r|2r>|2r@|:noname|\?do|again|c\"|'
- r'case|compile,|endcase|endof|erase|false|'
- r'hex|marker|nip|of|pad|parse|pick|refill|'
- r'restore-input|roll|save-input|source-id|to|'
- r'true|tuck|u\.r|u>|unused|value|within|'
- r'\[compile\]|'
- # *** Wordset CORE-EXT-obsolescent
- r'\#tib|convert|expect|query|span|'
- r'tib|'
- # *** Wordset DOUBLE
- r'2constant|2literal|2variable|d\+|d-|'
- r'd\.|d\.r|d0<|d0=|d2\*|d2\/|d<|d=|d>s|'
- r'dabs|dmax|dmin|dnegate|m\*\/|m\+|'
- # *** Wordset DOUBLE-EXT
- r'2rot|du<|'
- # *** Wordset EXCEPTION
- r'catch|throw|'
- # *** Wordset EXCEPTION-EXT
- r'abort|abort\"|'
- # *** Wordset FACILITY
- r'at-xy|key\?|page|'
- # *** Wordset FACILITY-EXT
- r'ekey|ekey>char|ekey\?|emit\?|ms|time&date|'
- # *** Wordset FILE
- r'BIN|CLOSE-FILE|CREATE-FILE|DELETE-FILE|FILE-POSITION|'
- r'FILE-SIZE|INCLUDE-FILE|INCLUDED|OPEN-FILE|R\/O|'
- r'R\/W|READ-FILE|READ-LINE|REPOSITION-FILE|RESIZE-FILE|'
- r'S\"|SOURCE-ID|W/O|WRITE-FILE|WRITE-LINE|'
- # *** Wordset FILE-EXT
- r'FILE-STATUS|FLUSH-FILE|REFILL|RENAME-FILE|'
- # *** Wordset FLOAT
- r'>float|d>f|'
- r'f!|f\*|f\+|f-|f\/|f0<|f0=|f<|f>d|f@|'
- r'falign|faligned|fconstant|fdepth|fdrop|fdup|'
- r'fliteral|float\+|floats|floor|fmax|fmin|'
- r'fnegate|fover|frot|fround|fswap|fvariable|'
- r'represent|'
- # *** Wordset FLOAT-EXT
- r'df!|df@|dfalign|dfaligned|dfloat\+|'
- r'dfloats|f\*\*|f\.|fabs|facos|facosh|falog|'
- r'fasin|fasinh|fatan|fatan2|fatanh|fcos|fcosh|'
- r'fe\.|fexp|fexpm1|fln|flnp1|flog|fs\.|fsin|'
- r'fsincos|fsinh|fsqrt|ftan|ftanh|f~|precision|'
- r'set-precision|sf!|sf@|sfalign|sfaligned|sfloat\+|'
- r'sfloats|'
- # *** Wordset LOCAL
- r'\(local\)|to|'
- # *** Wordset LOCAL-EXT
- r'locals\||'
- # *** Wordset MEMORY
- r'allocate|free|resize|'
- # *** Wordset SEARCH
- r'definitions|find|forth-wordlist|get-current|'
- r'get-order|search-wordlist|set-current|set-order|'
- r'wordlist|'
- # *** Wordset SEARCH-EXT
- r'also|forth|only|order|previous|'
- # *** Wordset STRING
- r'-trailing|\/string|blank|cmove|cmove>|compare|'
- r'search|sliteral|'
- # *** Wordset TOOLS
- r'.s|dump|see|words|'
- # *** Wordset TOOLS-EXT
- r';code|'
- r'ahead|assembler|bye|code|cs-pick|cs-roll|'
- r'editor|state|\[else\]|\[if\]|\[then\]|'
- # *** Wordset TOOLS-EXT-obsolescent
- r'forget|'
- # Forth 2012
- r'defer|defer@|defer!|action-of|begin-structure|field:|buffer:|'
- r'parse-name|buffer:|traverse-wordlist|n>r|nr>|2value|fvalue|'
- r'name>interpret|name>compile|name>string|'
- r'cfield:|end-structure)'+delimiter, Keyword),
-
- # Numbers
- (r'(\$[0-9A-Fa-f]+)', Number.Hex),
- (r'(\#|%|&|\-|\+)?[0-9]+', Number.Integer),
- (r'(\#|%|&|\-|\+)?[0-9\.]+', Keyword.Type),
- # amforth specific
- (r'(@i|!i|@e|!e|pause|noop|turnkey|sleep|'
- r'itype|icompare|sp@|sp!|rp@|rp!|up@|up!|'
- r'>a|a>|a@|a!|a@+|a@-|>b|b>|b@|b!|b@+|b@-|'
- r'find-name|1ms|'
- r'sp0|rp0|\(evaluate\)|int-trap|int!)'+delimiter, Name.Constant),
- # a proposal
- (r'(do-recognizer|r:fail|recognizer:|get-recognizers|set-recognizers|r:float|r>comp|r>int|r>post|'
- r'r:name|r:word|r:dnum|r:num|recognizer|forth-recognizer|rec:num|rec:float|rec:word)'
- +delimiter, Name.Decorator),
- # defining words. The next word is a new command name
- (r'(Evalue|Rvalue|Uvalue|Edefer|Rdefer|Udefer)(\s+)',bygroups(Keyword.Namespace, Text), 'worddef'),
-
- (valid_name, Name.Function), # Anything else is executed
-
- ],
-
- 'worddef': [
- (r'[\S]*', Name.Class, '#pop')
- ],
- 'stringdef': [
- (r'[^"]*', String, '#pop')
- ],
-
- }
-
-
diff --git a/amforth-6.5/examples/ascii.frt b/amforth-6.5/examples/ascii.frt
deleted file mode 100644
index ab09ad6..0000000
--- a/amforth-6.5/examples/ascii.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ print a ascii table
-: .ascii
-base @
-$7f $20 do
- i emit
- decimal ." , dec: " i .
- hex ." , hex: " i .
- 8 base ! ." , oct: " i .
- 2 base ! ." , bin: " i .
- cr
-loop
-base !
-;
diff --git a/amforth-6.5/examples/co.frt b/amforth-6.5/examples/co.frt
deleted file mode 100644
index 0351ff9..0000000
--- a/amforth-6.5/examples/co.frt
+++ /dev/null
@@ -1,36 +0,0 @@
-\ coroutines
-
-: co r> r> swap >r >r ;
-
-: tokyo
- ." Here Tokyo over" cr co
- ." What gives? over" cr co
- ." Yes, more? over" cr co
- ." over and out" cr
-;
-
-: amsterdam
- tokyo
- ." here Amsterdam over" cr co
- ." has it arrived over" cr co
- ." no. over and out" cr
-;
-
-\ amsterdam
-
-\ generate a list of numbers, one by one
-: producer ( n -- n' n' ) begin 1+ dup co again ;
-: consumer
- \ setup producer
- 0 producer \ returns with a new number
- \ now starts a ping-pong via co calls
- \ every call to co *here* will give a new number
- \ which has to be consumed.
- begin dup . 10 < while co repeat
- \ stop producer and clean up data
- r> drop drop
-;
-\ output:
-\ > consumer
-\ 0 1 2 3 4 5 6 7 8 9 10 ok
-\ >
diff --git a/amforth-6.5/examples/date-time.frt b/amforth-6.5/examples/date-time.frt
deleted file mode 100644
index 13e5d25..0000000
--- a/amforth-6.5/examples/date-time.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-
-\ create task space
-$20 $20 0 task: t:date&time
-
-variable seconds
-\ runs every second
-: job-date&time
- 1 seconds +!
- \ more code for minute/hour/day...
- 0 \ flag for an endless loop
-;
-
-\ set up the task
-: setup-date&time
- t:date&time task-init \ create TCB in RAM
- 0 seconds ! \ more code for minutes etc
- t:date&time tcb>tid activate
- \ code from here is executed as task, later on
- ['] job-date&time every-second
-;
-
-\ setup and start the task "date/time"
-: turnkey-date&time
- onlytask \ set up multitasker
- 6 timer0.init timer0.start \ 16 MHz quartz
- \ insert task into task list
- setup-date&time t:date&time tcb>tid alsotask
- multi \ start multitasking
-;
diff --git a/amforth-6.5/examples/easter.frt b/amforth-6.5/examples/easter.frt
deleted file mode 100644
index f742d31..0000000
--- a/amforth-6.5/examples/easter.frt
+++ /dev/null
@@ -1,112 +0,0 @@
-
-\ Date of Easter According to Knuth
-\ Donald E. Knuth, _The Art of Computer Programming_, 1.3.2 Exercise
-\ 14-15.
-\ [Commentary by Knuth, Forth by Wil Baden. This is not well-suited
-\ for Forth, but there's no advantage in purifying it.]
-\ The following algorithm, due to the Neapolitan astronomer Aloysius
-\ Lilius and the German Jesuit mathematician Christopher Clavius in
-\ the late 16th century, is used by most Western churches to
-\ determine the date of Easter Sunday for any year after 1582.
-
-\ Counters.
-
-\ Y
-\ Year.
-\ G
-\ Golden number.
-\ C
-\ Century.
-\ X
-\ Century leap year adjustment.
-\ Z
-\ Moon's orbit adjustment.
-\ D
-\ Sunday date.
-\ E
-\ Epact.
-\ N
-\ Day of month.
-
-variable easter.y \ Year
-variable easter.g \ Golden number
-variable easter.c \ Century
-variable easter.x \ Century leap year adjustment
-variable easter.z \ Moon's orbit adjustment
-variable easter.d \ Sunday date
-variable easter.e \ Epact
-variable easter.n \ Day of month
-
-\ EASTER ( yyyyy -- dd mm yyyyy )
-\ Compute date of Easter for year _yyyyy_.
-
-: easter ( yyyyy -- dd mm yyyyy )
- easter.y ! ( )
- \ E1. Golden number.
- \ _G_ is the so-called "golden number" of the year in the
- \ 19-year Metonic cycle.
-
- easter.y @ 19 mod 1+ easter.g !
-
- \ E2. Century.
- \ When _Y_ is not a multiple of 100, _C_ is the century number;
- \ for example, 1984 is in the twentieth century.
-
- easter.y @ 100 / 1+ easter.c !
-
- \ E3. Corrections.
- \ Here _X_ is the number of years, such as 1900, in which leap
- \ year was dropped in order to keep in step with the sun; _Z_ is
- \ a special correction designed to synchronize Easter with the
- \ moon's orbit.
-
- easter.c @ 3 4 */ 12 - easter.x !
- easter.c @ 8 * 5 + 25 / 5 - easter.z !
-
- \ E4. Find Sunday.
- \ March ((-_D_) mod 7) actually will be a Sunday.
-
- easter.y @ 5 4 */ easter.x @ - 10 - easter.d !
-
- \ E5. Epact.
- \ This number _E_ is the _epact_, which specifies when a full
- \ moon occurs.
-
- easter.g @ 11 * 20 + easter.z @ + easter.x @ - 30 mod
- dup 0< if 30 + then
- easter.e !
- easter.e @ 25 = dup if drop easter.g @ 11 > then
- dup 0= if drop easter.e @ 24 = then
- if 1 easter.e +! then
-
- \ E6. Find full moon.
- \ Easter is supposedly the first Sunday following the first full
- \ moon that occurs on or after March 21. Actually perturbations
- \ in the moon's orbit do not make this strictly true, but we are
- \ concerned here with the "calendar moon" rather than the actual
- \ moon. The _N_th of March is a calendar full moon.
-
- 44 easter.e @ - easter.n !
- easter.n @ 21 < if 30 easter.n +! then
-
- \ E7. Advance to Sunday.
-
- easter.n @ 7 +
- easter.d @ easter.n @ + 7 mod -
- easter.n !
-
- \ E8. Get month.
-
- easter.n @ 31 > if
- easter.n @ 31 - 4 easter.y @
- else
- easter.n @ 3 easter.y @
- then ;
-
-\ .EASTER ( yyyyy -- )
-\ Display date of Easter for year _yyyyy_.
-
-: .easter ( yyyyy -- )
- easter . 4 = if ." April" else ." March" then 3 .R ;
-
-\\ ************************* End of Easter *************************
diff --git a/amforth-6.5/examples/fib.frt b/amforth-6.5/examples/fib.frt
deleted file mode 100644
index 3eaab4a..0000000
--- a/amforth-6.5/examples/fib.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-( fibonacci number )
-: fib
- dup 2 > if
- dup 1- recurse swap 1- 1- recurse + exit
- then
- drop 1
-;
-
-: fib-iter 0 1 rot 0 ?do over + swap loop drop ;
-
-: dfib-iter >r 0 s>d 1 s>d r> 0 ?do 2over d+ 2swap loop 2drop .s ;
-
diff --git a/amforth-6.5/examples/forward-declarations-test.frt b/amforth-6.5/examples/forward-declarations-test.frt
deleted file mode 100644
index b44ce94..0000000
--- a/amforth-6.5/examples/forward-declarations-test.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-forward: foo
-
-: bar foo ;
-: baz foo ;
-
-bar \ should cause an error: foo not bound, or (simpler) silently crash
-
-: foo ." I'm foo the first" ;
-bar \ should execute the does> part of forward: for foo
-: foo ." I'm the second foo" ;
-baz \ uses the new definition of foo!
-
diff --git a/amforth-6.5/examples/forward-declarations.frt b/amforth-6.5/examples/forward-declarations.frt
deleted file mode 100644
index 274edf4..0000000
--- a/amforth-6.5/examples/forward-declarations.frt
+++ /dev/null
@@ -1,23 +0,0 @@
-: forward:
- dp
- create
- ,
- \ save more information?
- does>
- \ get the current name and
- \ lookup the dictionary. get the
- \ XT and replace the dictionary entry in the
- \ *caller* with it. After that execute it too
- \ next code is executed only once if successful
- dup 1- swap @i here iplace here count ( copy to temporary ram)
- find-name if \ unless some wordlist voodoo is in place...
- swap over = abort" found only forward declaration."
- dup r@ 1- !i execute
- else
- \ can only happen if search wordlist has changed
- true abort" unresolved forward declaration"
- then
-;
-
-
-
diff --git a/amforth-6.5/examples/fsm.frt b/amforth-6.5/examples/fsm.frt
deleted file mode 100644
index 94af976..0000000
--- a/amforth-6.5/examples/fsm.frt
+++ /dev/null
@@ -1,67 +0,0 @@
-\ FSM routines, from a paper presented by J . Noble-----
-\ ---------------------------------------------------------
-\ you can find the paper at http://www.forth.org/literature/noble.html
-\ The fsm: word has been modified to correctly increment addresses by
-\ word, instead of byte. and to also use the i@ dictionary fetch word.
-\ Ver 1.1 fsm: now implements "The best FSM so far" (see paper). State
-\ is now a heap variable with it's address in the dictionary of the fsm.
-\ Written by Bernard Mentink
-
-marker _fsm_
-
-hex
-
-\ dummy nop word for readability
-: wide ;
-
-\ perform word that executes vector
-: perform
- @i execute ;
-
-\ Get 2 cells from dictionary space
-: 2@i
- dup 1+ @i swap @i ;
-
-\ comment if you have this word.
-: tuck swap over ;
-
-\ Allocate a RAM variable on the data space, init with x, and return RAM address
-: >ram ( x -- addr ) here 1 cells allot tuck ! ;
-
-
-\ This word creates FSM transition tables
-: fsm: ( width -- )
- create 0 >ram , , ] \ ram addr of state stored in dict,also width.
- does> ( col# adr -- )
- dup dup >r 2@i @ * 2* + ( -- col#+width*state )
- swap 2* 1+ 1+ + ( -- offset-to-action)
- dup >r ( -- offset-to-action)
- perform ( ? )
- r> 1+ ( -- offset-to-update)
- perform ( -- state')
- r> @i ! ; \ update state
-
-
-\ ......... some test code ..............
-\ un-comment the code lines to test state changes dependant on input supplied
-\ e.g 2 test_fsm, 0 test_fsm etc
-\ If you want the address of the state variable associated with your state
-\ machine, create the following word : mystate ['] test_fsm 1+ i@ ;
-
-\ : one ." one " ;
-\ : two ." two " ;
-\ : three ." three " ;
-\ : four ." four " ;
-\ : nop ." nop " ;
-
-\ 0 constant >0
-\ 1 constant >1
-\ 2 constant >2
-
-\ a test state-machine table
-\ 4 wide fsm: test_fsm
-\ input: | 0 | 1 | 2 | 3 |
-\ state: ---------------------------------------------
-\ ( 0 ) nop >0 one >1 one >1 two >2
-\ ( 1 ) four >1 one >1 nop >1 two >2
-\ ( 2 ) nop >2 two >2 nop >2 nop >2 ;
diff --git a/amforth-6.5/examples/i2c-compass.frt b/amforth-6.5/examples/i2c-compass.frt
deleted file mode 100644
index 651af14..0000000
--- a/amforth-6.5/examples/i2c-compass.frt
+++ /dev/null
@@ -1,55 +0,0 @@
-\
-\ compass module mmc2120 (memsic)
-\ hwid is always $30
-\ provides:
-\
-\ i2c.compass.get ( -- status X Y)
-\ X and Y are around 2000 (raw data)
-\ status is 0 if no error occured
-
-\ further calculation?
-
-$30 constant i2c.compass
-
-\ internal commands
-: i2c.compass.setcoil
- i2c.compass i2c.begin
- 0 i2c.tx
- %00000010 i2c.tx \ set coil
- i2c.end
-;
-: i2c.compass.resetcoil
- i2c.compass i2c.begin
- 0 i2c.tx
- %00000100 i2c.tx \ reset coil
- i2c.end
-;
-
-: i2c.compass.measure
- i2c.compass i2c.begin
- 0 i2c.tx
- %00000001 i2c.tx \ start measurement
- i2c.end
-;
-
-: i2c.compass.fetchdata ( -- status x y )
- i2c.compass i2c.begin
- 0 i2c.tx
- i2c.start \ rep-start
- i2c.compass i2c.rd i2c.tx
- 4 0 do i2c.rx loop i2c.rxn
- i2c.end
- ( -- status msb-x lsb-x msb-y lsb-y)
- swap >< or $fff and >r \ Y
- swap >< or $fff and r> \ X
-;
-
-\ get the raw data from the module
-\ the numbers for X/Y are usually around 2000.
-\ status is 0 if everything is ok
-: i2c.compass.get ( -- status x y )
- i2c.compass.resetcoil 1ms
- i2c.compass.setcoil 5 ms
- i2c.compass.measure 5 ms
- i2c.compass.fetchdata
-;
diff --git a/amforth-6.5/examples/life.frt b/amforth-6.5/examples/life.frt
deleted file mode 100644
index a8543c1..0000000
--- a/amforth-6.5/examples/life.frt
+++ /dev/null
@@ -1,178 +0,0 @@
-\ Conway's Game of Life, or Occam's Razor Dulled
-
-\ The original ANS Forth version by Leo Wong (see bottom)
-\ has been modified slightly to allow it to run under
-\ kForth. Also, delays have been changed from 1000 ms to
-\ 100 ms for faster update --- K. Myneni, 12-26-2001
-\
-marker Genesis
-
-\ needs portpone.frt, marker.frt, 2x.frt, ans.frt
-\ and finally vt100.frt already loaded
-
-decimal
-
-\ ANS Forth this life is remains and
-1 chars constant /char
-: c+! ( char c-addr -- ) dup >r c@ + r> c! ;
-
-\ the universal pattern; optimum is 25x80, but that
-\ requires memory. The 10x20 screen works on an Atmega16
-
-&10 constant How-Deep
-&20 constant How-Wide
-
-\ nothing beyound this line should be changed
-
-How-Wide How-Deep * 1- \ 1- prevents scrolling on my screen
- constant Homes
-
-\ world wrap
-: World
- variable ( -- ) Homes chars allot
- does> ( u -- c-addr ) @i swap Homes + Homes mod chars + ;
-
-World old
-World new
-
-\ biostatistics
-
-\ begin hexadecimal numbering
-hex \ hex xy : x holds life , y holds neighbors count
-
-10 constant Alive \ 0y = not alive
-
-\ Conway's rules:
-\ a life depends on the number of its next-door neighbors
-
-\ it dies if it has fewer than 2 neighbors
-: Lonely ( char -- flag ) 12 < ;
-
-\ it dies if it has more than 3 neighbors
-: Crowded ( char -- flag ) 13 > ;
-
-: -Sustaining ( char -- flag )
- dup Lonely swap Crowded or ;
-
-\ it is born if it has exactly 3 neighbors
-: Quickening ( char -- flag )
- 03 = ;
-
-\ back to decimal
-decimal
-
-\ compass points
-: N ( i -- j ) How-Wide - ;
-: S ( i -- j ) How-Wide + ;
-: E ( i -- j ) 1+ ;
-: W ( i -- j ) 1- ;
-
-\ census
-: Home+! ( -1|1 i -- ) >r Alive * r> new c+! ;
-
-: Neighbors+! ( -1|0|1 i -- )
- 2dup N W new c+! 2dup N new c+! 2dup N E new c+!
- 2dup W new c+! ( i ) 2dup E new c+!
- 2dup S W new c+! 2dup S new c+! S E new c+! ;
-
-: Bureau-of-Vital-Statistics ( -1|1 i -- )
- 2dup Home+! Neighbors+! ;
-
-\ mortal coils
-char ? constant Soul
- bl constant Body
-
-\ at home
-: Home ( char i -- ) How-Wide /mod at-xy emit ;
-
-\ changes, changes
-: Is-Born ( i -- )
- Soul over Home
- 1 swap Bureau-of-Vital-Statistics ;
-: Dies ( i -- )
- Body over Home
- -1 swap Bureau-of-Vital-Statistics ;
-
-\ the one and the many
-: One ( c-addr -- i )
- 0 old - /char / ;
-: Everything ( -- )
- 0 old Homes
- begin dup
- while over c@ dup Alive and
- if -Sustaining if over One Dies then
- else Quickening if over One Is-Born then then
- 1 /string
- repeat 2drop
- How-Wide 1- How-Deep 1- at-xy ;
-
-\ in the beginning
-: Void ( -- )
- 0 old Homes blank ;
-
-\ spirit
-: Voice ( -- c-addr u )
- page
- ." Say: " 0 new dup Homes accept ;
-
-\ subtlety
-: Serpent ( -- )
- 0 2 at-xy ." Press a key for knowledge." key drop
- 0 2 at-xy ." Press space to re-start, Esc to escape life." ;
-
-\ the primal state
-: Innocence ( -- )
- Homes 0
- do i new c@ Alive / i Neighbors+! loop ;
-
-\ children become parents
-: Passes ( -- ) 0 new 0 old Homes cmove ;
-
-\ a garden
-: Paradise ( c-addr u -- )
- >r How-Deep How-Wide * How-Deep 2 mod 0= How-Wide and -
- r@ - 2/ old
- r> cmove
- 0 old Homes 0
- do count bl <>
- dup if Soul i Home then
- Alive and i new c!
- loop drop
- Serpent
- Innocence Passes ;
-
-: Creation ( -- ) Void Voice Paradise ;
-
-\ the human element
-
-( 1000) 100 constant Ideas
-: Dreams ( -- ) Ideas ms ;
-
-( 1000) 100 constant Images
-: Meditation ( -- ) Images ms ;
-
-\ free will
-: Action ( -- char )
- key? dup
- if drop key
- dup bl = if Creation then
- then ;
-
-\ environmental dependence
-27 constant Escape
-
-\ history
-: Goes-On ( -- )
- begin Everything Passes
- Dreams Action Meditation
- Escape = until ;
-
-\ a vision
-: Life ( -- ) Creation Goes-On ;
-
-
-\ run the word Life and enjoy
-
-\ Copyright 1995 Leo Wong
-\ hello@albany.net
-\ http://www.albany.net/~hello/
diff --git a/amforth-6.5/examples/literacy.frt b/amforth-6.5/examples/literacy.frt
deleted file mode 100644
index b9b0bd9..0000000
--- a/amforth-6.5/examples/literacy.frt
+++ /dev/null
@@ -1,49 +0,0 @@
-\ from Newsgroups: comp.lang.forth
-\ Date: Sun, 28 Dec 2014 14:12:44 -0800 (PST)
-\ Message-ID: <fdfa0f77-57f9-4ea6-b5bc-32d5651aabef@googlegroups.com>
-\ Subject: String literacy
-\ From: Julian Fondren <julian....@gmail.com>
-\ Adapted to most recent recognizer RFD
-
-
-\ Also, notice how I intend code by two spaces? That makes it very
-\ clear what's code and what's me talking about code, without the
-\ reader having to keep switching between two files, say. It also
-\ allows me to tie documentation and source together in such a way
-\ that one will seldom be supplied without the other. You could
-\ even organize your code into 'blocks', with corresponding 'shadow
-\ blocks' ... well, once again, let's just do it:
-
-\ This is the entire contents of literate.fs:
-
- ' noop ' noop ' noop recognizer: r:noop
- : literacy-recognizer ( c-addr u -- r:noop | r:fail )
- 2drop source s" " string-prefix? if r:fail else 0 parse 2drop r:noop then ;
-
- \ place it at the top of the recognizer stack
- forth-recognizers get-recognizers
- 1+ ' literacy-recognizer swap
- forth-recognizers set-recognizers
-
-And the entire rest of my post will be the contents of a file
-named hello.fs, which makes use of it:
-
---- hello.fs begins next line ---
- require literate.fs
-
-Having required literate.fs, the rest of this file is commentary unless
-intended by two spaces.
-
-For example, Forth will pass over the following:
-
-: hello ( -- ) cr ." Hello!" ;
-
-But will compile and execute these indented statements:
-
- : goodbye ( -- )
- cr ." Good bye." ;
-
- goodbye bye bye bye
-
-(This behavior is also seen interactively.)
-
diff --git a/amforth-6.5/examples/local.frt b/amforth-6.5/examples/local.frt
deleted file mode 100644
index 71564a2..0000000
--- a/amforth-6.5/examples/local.frt
+++ /dev/null
@@ -1,64 +0,0 @@
-\ trivial local
-
-\ there is exactly one local called X
-\ it is not initialized upon entry
-\ it works like a local should do:
-\ get the content by calling X, assign
-\ a new value with TO
-
-\ separate local stack
-\ max. call depth 10
-
-\ "2" means "1 cells", if portability is a concern
-
-#10 cells constant l-size
-\ the local stack pointer and the stack itself
-l-size cell+ buffer: lsp
-
-\ initialize l-stackpointer, call it
-\ in e.g. turnkey prior to use!
-: l-init lsp l-size + lsp ! ;
-
-\ general stack access, unsued
-: l@ lsp @ @ ;
-: l! lsp @ ! ;
-: l-free 2 lsp +! ;
-: l-alloc -2 lsp +! ;
-: >l l! l-alloc ;
-: l> l-free l@ ;
-
-: local@ negate lsp @ + @ ;
-: local! negate lsp @ + ! ;
-
-\ define a local by its offset
-\ relative to the local stack pointer
-: local ( offset "name" -- )
- (value) ,
- ['] local@ ,
- ['] local! ,
-;
-
-\ should be smarter, it should
-\ check whether X is used at all
-\ and allocate the local stack
-\ only if needed.
-: : : l-alloc ;
-: ; l-free postpone ; ; immediate
-
-\ globally define a label for the first
-\ local variable. The X is a global name
-\ but has local content. If using more,
-\ add a l-alloc/l-free pair in the : and ;
-\ definitions above.
-
-0 local X
-
-\ test cases
-\ l-init
-\ : test1 to X X . ;
-\ 1 test1
-\ -> 1
-\ : test2 1 test1 to X X . ;
-\ 2 test2
-\ -> 1 2
-\ \ No newline at end of file
diff --git a/amforth-6.5/examples/many.frt b/amforth-6.5/examples/many.frt
deleted file mode 100644
index c5bfc49..0000000
--- a/amforth-6.5/examples/many.frt
+++ /dev/null
@@ -1,13 +0,0 @@
-\ Rick VanNorman, clf 15. Apr 1997
-
-: many key? if key drop exit then 0 >in ! ;
-
-\ use it like
-\ > 0
-\ > dup . 1+ many
-\ 0 1 2 3 4 5 6 .....
-\
-\ this repeats the current input line until a key
-\ is hit. The repeat can, of course, cause a total
-\ desaster
-\ \ No newline at end of file
diff --git a/amforth-6.5/examples/parsed-to.frt b/amforth-6.5/examples/parsed-to.frt
deleted file mode 100644
index 8c06769..0000000
--- a/amforth-6.5/examples/parsed-to.frt
+++ /dev/null
@@ -1,22 +0,0 @@
-
-\ prepend -> to a value name and act like TO
-\ 42 to answer
-\ is the same as
- \ 42 ->answer
-\ The -> should be made a synonymous to TO
-\
-\ actions
-:noname defer! ;
-:noname postpone literal postpone defer! ;
-:noname postpone 2literal ;
-recognizer: r:parsed-to
-
-: rec-parsed-to ( addr len -- addr r:parsed-to | r:fail )
- over @ $3e2d = ( -> ) 0= if 2drop r:fail exit then
- \ something left?
- 2 /string dup 0= if 2drop r:fail exit then
- \ search for the name
- find-name 0= if r:fail exit then
- ( -- xt )
- r:parsed-to
-;
diff --git a/amforth-6.5/examples/queens.frt b/amforth-6.5/examples/queens.frt
deleted file mode 100644
index e20b05d..0000000
--- a/amforth-6.5/examples/queens.frt
+++ /dev/null
@@ -1,54 +0,0 @@
-\ Copyright (c) 2007 the authors listed at the following URL, and/or
-\ the authors of referenced articles or incorporated external code:
-\ http://en.literateprograms.org/Eight_queens_puzzle_(Forth)?action=history&offset=20070512025943
-\
-\ Permission is hereby granted, free of charge, to any person obtaining
-\ a copy of this software and associated documentation files (the
-\ "Software"), to deal in the Software without restriction, including
-\ without limitation the rights to use, copy, modify, merge, publish,
-\ distribute, sublicense, and/or sell copies of the Software, and to
-\ permit persons to whom the Software is furnished to do so, subject to
-\ the following conditions:
-\
-\ The above copyright notice and this permission notice shall be
-\ included in all copies or substantial portions of the Software.
-\
-\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-\ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-\ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-\ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-\ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-\
-\ Retrieved from: http://en.literateprograms.org/Eight_queens_puzzle_(Forth)?oldid=10015
-marker queen
-
- : bits ( bits -- mask ) 1 swap lshift 1- ;
- : lowBit ( mask -- bit ) dup negate and ;
- : lowBit- ( mask -- mask ) dup 1- and ;
- : third ( a b c -- a b c a ) 2 pick ;
-
- variable solutions
- variable nodes
- : poss ( a b c -- a b c a&b&c ) dup 2over and and ;
-
- : next3 ( dl dr f Qfilebit -- dl dr f dl' dr' f' )
- invert >r
- third r@ and 2* 1+
- third r@ and 2/
- third r> and ;
-
- : try ( dl dr f -- ) \ bitmasks for unused diagonals and files
- dup if 1 nodes +! poss
- begin ?dup while
- dup >r lowBit next3 recurse r> lowBit-
- repeat
- else ( .sol) 1 solutions +! then
- drop drop drop ;
-
- : queens ( n -- ) >r
- 0 solutions ! 0 nodes !
- -1 dup r@ bits try
- r> . ." queens: " solutions @ u. ." solutions, " nodes @ u. ." nodes" ;
-
diff --git a/amforth-6.5/examples/readme.txt b/amforth-6.5/examples/readme.txt
deleted file mode 100644
index 940d913..0000000
--- a/amforth-6.5/examples/readme.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-This folder contains some example codes not
-related to any application.
-
-easter.frt: calculates the date of easter. almost unmodfied version
- of Will Baden's code
-
-fib.frt: simple benchmark. calculate a fibonacci number using
- different algorithm.
-
-sieve.frt: not-so simple benchmark modelled after the sieve code
- of Marcel Hendrix. Uses single bits to store the is-prim flag.
-
-run-hayes.frt: demonstrate the use of the amforth-upload.py utility
- and the special #include syntax. The test itself is a slightly
- modified HAYES test suite
-
-queens.frt: solves the queens problem for various size, maybe useful
- as a benchmark.
-
-ascii.frt: prints an ascii table on screen
-
-life.frt: Conveys game of life. Its very memory intensive, the example
- code works on an Atmega16, but a bigger one would allow larger
- worlds.
-
-string-rec.frt: converts a " delimited string into a printable,
- compilable and postponable text object. It replaces the s" command.
-
-sierpinski.frt: simple fractal generator. Illustrates the use of
- the amforth-shell to include library files.
-
-co.frt: co routines aka subroutines for nonpreemtive multitasking.
- Examples on how to use them are included.
-
-many.frt: Repeat the input line until a key is hit. Use it with care
- since it can cause a lot of trouble. Since the input line is re-parsed
- every time, it is much slower than a compiled word.
diff --git a/amforth-6.5/examples/rec-char.frt b/amforth-6.5/examples/rec-char.frt
deleted file mode 100644
index 1e7b1ac..0000000
--- a/amforth-6.5/examples/rec-char.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-\ check for the 'c' syntax for single
-\ characters.
-: rec:char ( addr len -- n r:num | r:fail )
- 3 = if \ a three character string
- dup c@ [char] ' = if \ starts with a '
- dup 2 + c@ [char] ' = if \ and ends with a '
- 1+ c@ r:num exit
- then
- then
- then
- drop r:fail
-;
diff --git a/amforth-6.5/examples/rec-double-paren.frt b/amforth-6.5/examples/rec-double-paren.frt
deleted file mode 100644
index 254fa9e..0000000
--- a/amforth-6.5/examples/rec-double-paren.frt
+++ /dev/null
@@ -1,73 +0,0 @@
-\
-\ Purpose: temporarly switch off all actions until
-\ a delimiting word is found and executed.
-\ Useful to comment larger text parts.
-\
-\ (( switches to a limited command set and
-\ makes all words no-operations. Only words
-\ in a special wordlist are allowed for
-\ execution. )) is one of them and switches
-\ back to normal operation.
-\
-\ The recognizer switch survives REFILL's so
-\ multi line comments work too. This is an
-\ example for replacing the whole system
-\ recognizer stack with another one.
-\
-\ Author: Matthias Trute
-\ Date: Oct 14, 2016
-\ License: Public Domain
-\
-
-\ keep the previously active forth-recognizer stack
-variable old-f-rs
-wordlist constant comment-actions
-
-get-current
-comment-actions set-current
-
-\ only words in this wordlist are executed inside comments
-\ at least the )) is needed.
-
-\ switch back to the saved recognizer stack
-: ))
- old-f-rs @ to forth-recognizer
-; immediate
-
-\ that's all for the comment actions
-set-current
-
-\ every word found is fine. Even the ones that are not found
-\ in the dictionary
-' noop dup dup recognizer: r:skip
-: rec:skip ( addr len -- r:skip ) 2drop r:skip ;
-
-\ search only in the comment-actions wordlist
-: rec:comment-actions ( addr len -- xt +/-1 r:word | r:fail )
- comment-actions search-wordlist ( xt +/-1 | 0 )
- ?dup if r:word else r:fail then
-;
-
-\ a simple two-element recognizer stack
-2 recognizer constant rs:comment
-' rec:skip ' rec:comment-actions 2 rs:comment set-recognizers
-
-\ save the current recognizer stack and
-\ switch over to the limited one
-: (( ( -- )
- forth-recognizer old-f-rs !
- rs:comment to forth-recognizer
-; immediate
-
-\ ------------- Test Cases ----------------
-\
-\ : rec:comment rs:comment do-recognizer ;
-\ T{ S" DUP" rec:comment -> r:skip }T
-\ T{ S" 1234" rec:comment -> r:skip }T
-
-\ the XT of )) is not important
-\ T{ S" ))" rec:comment rot drop -> 1 r:word }T
-\
-\ ------------------------------------------
-\ with nesting the [IF] [ELSE] [THEN] can be
-\ implemented likewise.
diff --git a/amforth-6.5/examples/rec-name.frt b/amforth-6.5/examples/rec-name.frt
deleted file mode 100644
index 3957133..0000000
--- a/amforth-6.5/examples/rec-name.frt
+++ /dev/null
@@ -1,18 +0,0 @@
-
-\ #require recognizer.frt
-\ #require find-name.frt
-
-\ from forth 2012
-:noname name>interpret execute ;
-:noname name>compile execute ;
-:noname postpone literal ;
-recognizer: r:name
-
-\ the parsing word
-: rec:name ( addr len -- nt r:name | r:fail)
- find-name ?dup
- if r:name else r:fail then
-;
-
-\ replace rec:word with rec:name
-\ everthing else should work as before
diff --git a/amforth-6.5/examples/run-hayes.frt b/amforth-6.5/examples/run-hayes.frt
deleted file mode 100644
index 3549977..0000000
--- a/amforth-6.5/examples/run-hayes.frt
+++ /dev/null
@@ -1,26 +0,0 @@
-\
-\ process this file with amforth-upload.py and
-\ the proper setting of $AMFORTH_LIB (basedir of
-\ you amforth file tree)
-\ WIN (untested, DOS Box)
-\ cd c:\amforth-x.y
-\ set AMFORTH_LIB=c:\amforth-x.y
-\ python tools\amforth-upload.py -t com1: examples\run-hayes.frt
-\ UNIX / MAC (Terminal)
-\ cd $HOME/amforth-x.y
-\ export AMFORTH_LIB=$HOME/amforth-x.y
-\ tools/amforth-upload.py -t /dev/ttyUSB0 examples/run-hayes.frt
-\ enjoy!
-\
-\ it is meant to be run on a newly flashed
-\ controller, e.g. all the dict_* are included
-\
-
-\ include all sources
-#include ans94/core.frt
-#include ans94/tester/tester-amforth.frt
-#include ans94/double.frt
-#include ans94/core-ext/marker.frt
-\ and finally run all the tests
-
-#include ans94/tester/core.fr
diff --git a/amforth-6.5/examples/scope.frt b/amforth-6.5/examples/scope.frt
deleted file mode 100644
index d6a5d31..0000000
--- a/amforth-6.5/examples/scope.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ The following example shows how to create a library of words under a special
-\ wordlist (can_lib). This example also shows how to chain scope calls safely.
-
-wordlist constant can_lib
-
-get-order 1+ can_lib swap set-order \ can_lib would be searched first
-
-: can_scope ( addr len -- addr' len' wid )
- 2dup
- 4 > if \ name length check
- s" can_" tuck icompare if \ name prefix check
- 4 /string \ drop prefix from created word
- can_lib exit
- then
- else
- drop
- then
- [ ' wlscope defer@ ] literal execute
-;
-
-' can_scope is wlscope
diff --git a/amforth-6.5/examples/sierpinsi.frt b/amforth-6.5/examples/sierpinsi.frt
deleted file mode 100644
index 19fe920..0000000
--- a/amforth-6.5/examples/sierpinsi.frt
+++ /dev/null
@@ -1,26 +0,0 @@
-\ Sierpinski fractal
-\ richard.w@gmail.com, clf 13.2.2015
-
-\ additional words from the forth lib
-\ #require buffer.frt
-\ #require blank.frt
-\ #require chars.frt
-
-64 constant size
-char * constant '*'
-size buffer: line[]
-
-line[] size blank '*' size 2/ chars line[] + c! ( init )
-
-: .line[] ( -- ) line[] size type cr ;
-: =*? ( addr -- f ) c@ '*' = ;
-: >char ( f f -- ch ) xor [ '*' bl - ] literal and bl + ;
-: init-flags ( -- f-1 f0 ) 0 line[] =*? ;
-: sierp-line ( -- ) init-flags line[] size bounds do
- i 1 chars + =*? rot over >char i c!
- loop 2drop ;
-: sierpinski ( -- ) size 2/ 0 do .line[] sierp-line loop ;
-
-\
-\ sierpinski prints the fractal on the terminal
-\ \ No newline at end of file
diff --git a/amforth-6.5/examples/sieve.frt b/amforth-6.5/examples/sieve.frt
deleted file mode 100644
index 13c45f2..0000000
--- a/amforth-6.5/examples/sieve.frt
+++ /dev/null
@@ -1,58 +0,0 @@
-\ sieve benchmark, modified version of
-\ marcel hendrix' sources. Uses single bits
-\ insted of whole bytes to store the is-prime
-\ marker cuts memory footprint to 1/8th.
-
-\ runtime: ATMega644 @ 16MHz 2,3 seconds per DO-PRIME
-
-marker _sieve_
-
-decimal
-
-1000 constant #times
-8192 constant size \ needs 1KB
-
-variable flags size 8 / allot
-
-\ highly un-optimized words
-: bit-addr ( addr bit -- eff-addr )
- \ every byte has 8 bits. addr = addr + (bit >> 3)
- 3 rshift ( -- addr off)
- + ( -- eff-addr)
-;
-
-: bit? ( addr bit -- f )
- swap over bit-addr swap ( -- eff-addr bit )
- 7 and 1 swap lshift ( -- eff-addr bitmask)
- swap c@ and ( -- f)
-;
-
-: bit-reset ( addr bit -- )
- swap over bit-addr swap ( -- eff-addr bit )
- 7 and 1 swap lshift ( -- eff-addr bitmask)
- invert over c@ and swap c!
-;
-
-: 2drop drop drop ;
-
-: DO-PRIME flags [ size 8 / ] literal -1 fill
- 0 size 0 do
- flags i
- bit? if
- i 2* 3 +
- dup i +
- begin
- dup
- size u<
- while
- flags over bit-reset
- over +
- repeat
- 2drop 1+
- then
- loop ;
-
-: primes cr #times u. ." iterations."
- 0 #times 0 do drop DO-PRIME loop
- cr . ." primes found, " ;
-
diff --git a/amforth-6.5/examples/stack.frt b/amforth-6.5/examples/stack.frt
deleted file mode 100644
index b640cfb..0000000
--- a/amforth-6.5/examples/stack.frt
+++ /dev/null
@@ -1,76 +0,0 @@
-\
-\ separate stacks for cell sized data
-\
-\ Date: Nov 13, 2016
-\ Author: Matthias Trute
-
-\ allocate a stack region with at most
-\ size elements
-: stack ( size -- stack-id )
- 1+ ( size ) cells here swap allot
- 0 over ! \ empty stack
-;
-
-\ replace the stack content with data from
-\ the data stack.
-: set-stack ( rec-n .. rec-1 n recstack-id -- )
- over 0< if -4 throw then \ stack underflow
- 2dup ! cell+ swap cells bounds
- ?do i ! 1 cells +loop
-;
-
-\ read the whole stack to the data stack
-: get-stack ( recstack-id -- rec-n .. rec-1 n )
- dup @ >r r@ cells + r@ begin
- ?dup
- while
- 1- over ( -- a n a )
- @ ( -- a n r_i)
- rot 1 cells -
- rot ( -- r_i a n )
- repeat
- drop r>
-;
-
-\ execute XT for earch element of the stack
-\ leave the loop if the XT returns TRUE
-: map-stack ( i*x XT stack-id -- j*y f )
- dup cell+ swap @ cells bounds ?do
- ( -- i*x XT )
- i @ swap dup >r execute
- ?dup if r> drop unloop exit then
- r> 1 cells +loop
- drop 0
-;
-
-\ add an item as new top of the stack
-: >stack ( x stack-id -- )
- 2dup 2>r nip get-stack 2r> rot 1+ swap set-stack
-;
-
-\ destructivly get Top Of Stack
-: stack> ( stack-id -- x )
- dup >r get-stack 1- r> rot >r set-stack r>
-;
-
-\ actual stack depth
-: depth-stack ( stack-id -- n )
- @
-;
-
-\ copy a stack item
-: pick-stack ( n stack-id -- n' )
- 2dup depth-stack 0 swap within 0= if -9 throw then
- cell+ swap cells + @
-;
-
-\ add an item at the bottom of a stack
-: >back ( x stack-id -- )
- dup >r get-stack 1+ r> set-stack
-;
-
-\ destructivly get Bottom Of Stack
-: back> ( stack-id -- x )
- dup >r get-stack 1- r> set-stack
-;
-
diff --git a/amforth-6.5/examples/string-rec.frt b/amforth-6.5/examples/string-rec.frt
deleted file mode 100644
index b1bd930..0000000
--- a/amforth-6.5/examples/string-rec.frt
+++ /dev/null
@@ -1,28 +0,0 @@
-
-\ use " as string delimiters. Everything
-\ between two " is a string. It replaces
-\ the forth command s" completly
-\ instead of s" foo" use "foo". The space
-\ after s" is no longer needed, instead it
-\ a part of the string. s" foo" and " foo"
-\ differ with the leading space in the latter
-
-\ strings live as long as the SOURCE is
-\ unchanged! Compilation is done to the
-\ flash if called in compile state.
-\ postponing a compiled string is not yet
-\ supported.
-
-\ #require recognizer.frt
-
-' noop
-:noname postpone sliteral ;
-:noname -48 throw ; recognizer: r:string
-
-: rec:string ( addr len -- addr' len' r:string | r:fail )
- over c@ [char] " <> if 2drop r:fail exit then
- negate 1+ >in +! drop \ reset parse area to SOURCE
- [char] " parse \ get trailing delimiter
- -1 /string
- r:string
-;
diff --git a/amforth-6.5/examples/time-rec.frt b/amforth-6.5/examples/time-rec.frt
deleted file mode 100644
index 9fa77e8..0000000
--- a/amforth-6.5/examples/time-rec.frt
+++ /dev/null
@@ -1,59 +0,0 @@
-
-\ recognize a time information in the format
-\ hh:mm:ss (two : between numbers)
-\ returns either r:fail (if unsuccessful) or
-\ a double number representing the seconds of the
-\ time stamp
-
-\ append it to the recognizer stack with
-\ ' rec:h:m:s get-recognizers 1+ set-recognizers
-\ and than enter 02:00:00 to get 7200. (double
-\ cell number) which is the number of seconds
-\ 2 hours have.
-
-#require m-star-slash.frt
-
-\ some factors.
-\ is the character a ':' ?
-: ':'? ( addr len -- addr+1 len-1 f )
- over >r 1 /string r> c@ [char] : = ;
-
-\ extract a number from the current string
-: get-number ( addr len -- d addr' len' )
- 0. 2swap >number
-;
-
-\ (hours*60+minutes)*60+seconds, factor during calculation
-: a+60b 2swap 60 1 m*/ d+ ;
-
-: rec:h:m:s ( c-addr u -- d r:dnum | r:fail )
- get-number ( -- hh. addr len )
- ':'? 0= if 2drop 2drop r:fail exit then
-
- get-number ( -- hh. mm. addr+1 len-1 )
- \ add hours to minutes
- 2>r a+60b 2r>
- ':'? 0= if 2drop 2drop r:fail exit then
-
- get-number \ -- (hh*60+mm). ss. addr len
- \ len must now be 0 or its not a time stamp
- if drop 2drop 2drop r:fail exit then drop
- \ add minutes to seconds and finish
- a+60b r:dnum
-;
-
-\ wishlist:
-\ validate the values for minutes and seconds (between 0 and 59)
-\ factor the code
-\ add milliseconds?
-
-\ test cases (xy=XT of r:dnum, ab=XT of r:fail)
-\ tests are made outside of the interpreter, thus the
-\ need for explicit strings.
-
-\ > s" 01:00:00" rec:h:m:s . d.
-\ xy 3600
-\ > s" 01:00:0a" rec:h:m:s .
-\ ab
-\ > s" 72:00:09" rec:h:m:s . d.
-\ xy 259200
diff --git a/amforth-6.5/examples/value-variations.frt b/amforth-6.5/examples/value-variations.frt
deleted file mode 100644
index df7ec91..0000000
--- a/amforth-6.5/examples/value-variations.frt
+++ /dev/null
@@ -1,65 +0,0 @@
-\ This file contains variations of the
-\ standard VALUE. in amforth values are
-\ stored in EEPROM and occupy 1 cell (2bytes).
-\ Calling the name of a value returns this
-\ information on the stack. With the command
-\ TO this data can be changed. Implementation
-\ allows to extend this schema to any data
-\ in any memory.
-
-\ First example is a 1byte value in RAM:
-
-\ two helper words,
-: c@v @i c@ ;
-: c!v @i c! ;
-
-: cvalue ( n "name" -- )
- (value) \ create a new wordlist entry
- here , \ the address for the methods
- postpone c@v \ method for the read operation
- postpone c!v \ method for the write (TO) operation
- here 1 allot ! \ allocate the memory and initialize it
- ;
-
-\ $dead cvalue answer will store only the lower byte
-\ of the number ($ad). The upper byte is either ignored
-\ (TO) or set to 0
-
-
-\ a buffered value is a value that tolerates heavy write access
-\ by using a RAM cell as a cache.
-
-\ you need to define a trigger, that flushes the cache
-\ warm-cache initializes the cache with the stored data
-\ (to be called in turnkey and similiar actions)
-
-\ it is a matter of style whether a sequence should be
-\ ' vvv method
-\ or
-\ method vvv
-\ is used. The implementation below goes the first way
-\ since parsing words are considered suboptimal by the
-\ gurus (they are state smart and less flexible)
-
-\ 2 is a magic number
-: @cache 2 + @i @ ;
-: !cache 2 + @i ! ;
-
-: flush-cache 1+ dup 2 + @i @ swap @i !e ;
-: warm-cache 1+ dup @i @e swap 2 + @i ! ;
-
-: cache-value
- (value)
- dup ehere dup , dup cell+ to ehere !e
- postpone @cache
- postpone !cache
- here 2 ( 1 cell ) allot dup , ! \ 3 address units, remember?
-;
-
-\ \ test case
-\ ehere dup . \ keep the eeprom address
-\ 42 cache-value c-dp
-\ 17 to c-dp
-\ c-dp . dup @e . \ prints 17 and 42
-\ ' c-dp flush-cache
-\ c-dp . dup @e . \ prints 17 and 17
diff --git a/amforth-6.5/msp430/amforth-interpreter.asm b/amforth-6.5/msp430/amforth-interpreter.asm
deleted file mode 100644
index 1862e84..0000000
--- a/amforth-6.5/msp430/amforth-interpreter.asm
+++ /dev/null
@@ -1,54 +0,0 @@
-DOCOLON:
- PUSH IP ; 3 save old IP on return stack
- MOV W,IP ; 1 set new IP to PFA
-
-.if WANT_INTERRUPTS==1
-DO_NEXT:
- TST ISR
- JNZ DO_INTERRUPT
- MOV @IP+,W ; fetch word address into W
-DO_REALLY_NEXT:
- MOV @W+,PC ; fetch code address into PC, W=PFA
-
-DO_INTERRUPT:
- SUB #2,PSP ; save tos
- MOV TOS,0(PSP)
- MOV ISR,TOS ; move to tos
- CLR ISR ; clear flag register
- MOV #XT_ISREXEC, W
- JMP DO_REALLY_NEXT
-
-irq1_handler:
- MOV #1, R15
- RETI
-irq2_handler:
- MOV #2, R15
- RETI
-irq3_handler:
- MOV #3, R15
- RETI
-irq4_handler:
- MOV #4, R15
- RETI
-irq5_handler:
- MOV #5, R15
- RETI
-irq6_handler:
- MOV #6, R15
- RETI
-irq7_handler:
- MOV #7, R15
- RETI
-irq8_handler:
- MOV #8, R15
- RETI
-irq9_handler:
- MOV #9, R15
- RETI
-irq10_handler:
- MOV #10, R15
-null_handler:
- RETI
-.else
- NEXT
-.endif
diff --git a/amforth-6.5/msp430/amforth.asm b/amforth-6.5/msp430/amforth.asm
deleted file mode 100644
index 6138394..0000000
--- a/amforth-6.5/msp430/amforth.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-
-.msp430
-
-.include "macros.asm" ; registers, macros, and header structure
-.include "ram.inc" ; RAM Leyout
-
-.org AMFORTH_START ; start address of Forth kernel
-.include "init.asm"
-.include "drivers.asm"
-.include "amforth-interpreter.asm"
-.include "itc430core.asm" ; code primitives
-.include "itc430hilvl.asm"
-
-; now include application specific parts
-.include "dict_appl.inc"
diff --git a/amforth-6.5/msp430/compat.inc b/amforth-6.5/msp430/compat.inc
deleted file mode 100644
index 56f4e48..0000000
--- a/amforth-6.5/msp430/compat.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-
-; a temporary hack until all words got migrated
-
- XT_FETCHE EQU XT_FETCH
- XT_STOREE EQU XT_STORE
-
- XT_TRUE EQU XT_MINUSONE
- XT_ICOMPARE EQU XT_COMPARE
-
- XT_CFGDEFERFETCH EQU XT_RDEFERFETCH
- XT_CFGDEFERSTORE EQU XT_RDEFERSTORE
diff --git a/amforth-6.5/msp430/devices/msp430f5529/device.asm b/amforth-6.5/msp430/devices/msp430f5529/device.asm
deleted file mode 100644
index 22112b1..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/device.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; device specific
-.include "msp430f5529.inc" ; MCU-specific register equates
-
-RAMSTART equ 2400h
-RAMEND equ 4400h
-INFOSTART equ 01800h
-INFOEND equ 0198Fh ; do not allow config flash to be erased
-FLASHSTART equ 04400h
-FLASHEND equ 0DFFFh
-MAINSEG equ 512
-INFOSEG equ 64
-INFO_SIZE equ 128 ; bytes
-
-.org 0FFFEh
-
- DC16 reset ; FFFE - Reset
diff --git a/amforth-6.5/msp430/devices/msp430f5529/drivers.asm b/amforth-6.5/msp430/devices/msp430f5529/drivers.asm
deleted file mode 100644
index 2793ccf..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/drivers.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-
-.include "drivers/flash.inc"
-
diff --git a/amforth-6.5/msp430/devices/msp430f5529/init.asm b/amforth-6.5/msp430/devices/msp430f5529/init.asm
deleted file mode 100644
index 3ce33c3..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/init.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-
-mcu_name:
- .db 11,"MSP430F5529"
diff --git a/amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc b/amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc
deleted file mode 100644
index 610358a..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc
+++ /dev/null
@@ -1,4371 +0,0 @@
-/* ============================================================================ */
-/* Copyright (c) 2015, Texas Instruments Incorporated */
-/* All rights reserved. */
-/* */
-/* Redistribution and use in source and binary forms, with or without */
-/* modification, are permitted provided that the following conditions */
-/* are met: */
-/* */
-/* * Redistributions of source code must retain the above copyright */
-/* notice, this list of conditions and the following disclaimer. */
-/* */
-/* * Redistributions in binary form must reproduce the above copyright */
-/* notice, this list of conditions and the following disclaimer in the */
-/* documentation and/or other materials provided with the distribution. */
-/* */
-/* * Neither the name of Texas Instruments Incorporated nor the names of */
-/* its contributors may be used to endorse or promote products derived */
-/* from this software without specific prior written permission. */
-/* */
-/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
-/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
-/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
-/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
-/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
-/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
-/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
-/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
-/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
-/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ============================================================================ */
-
-/********************************************************************
-*
-* Standard register and bit definitions for the Texas Instruments
-* MSP430 microcontroller.
-*
-* This file supports assembler and C development for
-* MSP430F5529 devices.
-*
-* Texas Instruments, Version 1.4
-*
-* Rev. 1.0, Setup
-* Rev. 1.1, Fixed Error in DMA Trigger Definitons
-* Rev. 1.2, fixed SYSUNIV_BUSIFG definition
-* fixed wrong bit definition in PM5CTL0 (LOCKLPM5)
-* Rev. 1.3, Changed access type of DMAxSZ registers to word only
-* Rev. 1.4 Changed access type of TimerA/B registers to word only
-*
-********************************************************************/
-
-/************************************************************
-* STANDARD BITS
-************************************************************/
-
-#define BIT0 (0x0001)
-#define BIT1 (0x0002)
-#define BIT2 (0x0004)
-#define BIT3 (0x0008)
-#define BIT4 (0x0010)
-#define BIT5 (0x0020)
-#define BIT6 (0x0040)
-#define BIT7 (0x0080)
-#define BIT8 (0x0100)
-#define BIT9 (0x0200)
-#define BITA (0x0400)
-#define BITB (0x0800)
-#define BITC (0x1000)
-#define BITD (0x2000)
-#define BITE (0x4000)
-#define BITF (0x8000)
-
-/************************************************************
-* STATUS REGISTER BITS
-************************************************************/
-
-#define C (0x0001)
-#define Z (0x0002)
-#define N (0x0004)
-#define V (0x0100)
-#define GIE (0x0008)
-#define CPUOFF (0x0010)
-#define OSCOFF (0x0020)
-#define SCG0 (0x0040)
-#define SCG1 (0x0080)
-
-/* Low Power Modes coded with Bits 4-7 in SR */
-
-#define LPM0 (CPUOFF)
-#define LPM1 (SCG0+CPUOFF)
-#define LPM2 (SCG1+CPUOFF)
-#define LPM3 (SCG1+SCG0+CPUOFF)
-#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
-/* End #defines for assembler */
-
-/************************************************************
-* CPU
-************************************************************/
-
-/************************************************************
-* PERIPHERAL FILE MAP
-************************************************************/
-
-
-/************************************************************
-* ADC12 PLUS
-************************************************************/
-
-#define ADC12CTL0 0x0700 /* ADC12+ Control 0 */
-#define ADC12CTL1 0x0702 /* ADC12+ Control 1 */
-#define ADC12CTL2 0x0704 /* ADC12+ Control 2 */
-#define ADC12IFG 0x070A /* ADC12+ Interrupt Flag */
-#define ADC12IE 0x070C /* ADC12+ Interrupt Enable */
-#define ADC12IV 0x070E /* ADC12+ Interrupt Vector Word */
-#define ADC12MEM0 0x0720 /* ADC12 Conversion Memory 0 */
-#define ADC12MEM1 0x0722 /* ADC12 Conversion Memory 1 */
-#define ADC12MEM2 0x0724 /* ADC12 Conversion Memory 2 */
-#define ADC12MEM3 0x0726 /* ADC12 Conversion Memory 3 */
-#define ADC12MEM4 0x0728 /* ADC12 Conversion Memory 4 */
-#define ADC12MEM5 0x072A /* ADC12 Conversion Memory 5 */
-#define ADC12MEM6 0x072C /* ADC12 Conversion Memory 6 */
-#define ADC12MEM7 0x072E /* ADC12 Conversion Memory 7 */
-#define ADC12MEM8 0x0730 /* ADC12 Conversion Memory 8 */
-#define ADC12MEM9 0x0732 /* ADC12 Conversion Memory 9 */
-#define ADC12MEM10 0x0734 /* ADC12 Conversion Memory 10 */
-#define ADC12MEM11 0x0736 /* ADC12 Conversion Memory 11 */
-#define ADC12MEM12 0x0738 /* ADC12 Conversion Memory 12 */
-#define ADC12MEM13 0x073A /* ADC12 Conversion Memory 13 */
-#define ADC12MEM14 0x073C /* ADC12 Conversion Memory 14 */
-#define ADC12MEM15 0x073E /* ADC12 Conversion Memory 15 */
-#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
-
-#define ADC12MCTL0 0x0710 /* ADC12 Memory Control 0 */
-#define ADC12MCTL1 0x0711 /* ADC12 Memory Control 1 */
-#define ADC12MCTL2 0x0712 /* ADC12 Memory Control 2 */
-#define ADC12MCTL3 0x0713 /* ADC12 Memory Control 3 */
-#define ADC12MCTL4 0x0714 /* ADC12 Memory Control 4 */
-#define ADC12MCTL5 0x0715 /* ADC12 Memory Control 5 */
-#define ADC12MCTL6 0x0716 /* ADC12 Memory Control 6 */
-#define ADC12MCTL7 0x0717 /* ADC12 Memory Control 7 */
-#define ADC12MCTL8 0x0718 /* ADC12 Memory Control 8 */
-#define ADC12MCTL9 0x0719 /* ADC12 Memory Control 9 */
-#define ADC12MCTL10 0x071A /* ADC12 Memory Control 10 */
-#define ADC12MCTL11 0x071B /* ADC12 Memory Control 11 */
-#define ADC12MCTL12 0x071C /* ADC12 Memory Control 12 */
-#define ADC12MCTL13 0x071D /* ADC12 Memory Control 13 */
-#define ADC12MCTL14 0x071E /* ADC12 Memory Control 14 */
-#define ADC12MCTL15 0x071F /* ADC12 Memory Control 15 */
-#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
-
-/* ADC12CTL0 Control Bits */
-#define ADC12SC (0x0001) /* ADC12 Start Conversion */
-#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */
-#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */
-#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */
-#define ADC12ON (0x0010) /* ADC12 On/enable */
-#define ADC12REFON (0x0020) /* ADC12 Reference on */
-#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
-#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */
-#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */
-#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */
-#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */
-#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */
-#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */
-#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */
-#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */
-#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */
-
-/* ADC12CTL0 Control Bits */
-#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
-#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
-#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */
-#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */
-#define ADC12ON_L (0x0010) /* ADC12 On/enable */
-#define ADC12REFON_L (0x0020) /* ADC12 Reference on */
-#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */
-#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
-
-/* ADC12CTL0 Control Bits */
-#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */
-#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */
-#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */
-#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */
-#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */
-#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */
-#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */
-#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */
-
-#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */
-#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */
-#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */
-#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */
-#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */
-#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */
-#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */
-#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */
-#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */
-#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */
-#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */
-#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */
-#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */
-#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */
-#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */
-#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */
-
-#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */
-#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */
-#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */
-#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */
-#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */
-#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */
-#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */
-#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */
-#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */
-#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */
-#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */
-#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */
-#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */
-#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */
-#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */
-#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */
-
-/* ADC12CTL1 Control Bits */
-#define ADC12BUSY (0x0001) /* ADC12 Busy */
-#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
-#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
-#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */
-#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */
-#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
-#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
-#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
-#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
-#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
-#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */
-#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */
-#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */
-#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */
-#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */
-#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */
-
-/* ADC12CTL1 Control Bits */
-#define ADC12BUSY_L (0x0001) /* ADC12 Busy */
-#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
-#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
-#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */
-#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */
-#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
-#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
-#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
-
-/* ADC12CTL1 Control Bits */
-#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
-#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
-#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */
-#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */
-#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */
-#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */
-#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */
-#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */
-
-#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */
-#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */
-#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */
-#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */
-
-#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */
-#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */
-#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */
-#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */
-
-#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */
-#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */
-#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */
-#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */
-#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */
-#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */
-#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */
-#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */
-
-#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */
-#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */
-#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */
-#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */
-
-#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */
-#define ADC12CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */
-#define ADC12CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */
-#define ADC12CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */
-#define ADC12CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */
-#define ADC12CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */
-#define ADC12CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */
-#define ADC12CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */
-#define ADC12CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */
-#define ADC12CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */
-#define ADC12CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */
-#define ADC12CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */
-#define ADC12CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */
-#define ADC12CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */
-#define ADC12CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */
-#define ADC12CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */
-
-/* ADC12CTL2 Control Bits */
-#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */
-#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */
-#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */
-#define ADC12DF (0x0008) /* ADC12+ Data Format */
-#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */
-#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */
-#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */
-#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */
-
-/* ADC12CTL2 Control Bits */
-#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */
-#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */
-#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */
-#define ADC12DF_L (0x0008) /* ADC12+ Data Format */
-#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */
-#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */
-#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */
-
-/* ADC12CTL2 Control Bits */
-#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */
-
-#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
-#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
-#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
-#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
-
-/* ADC12MCTLx Control Bits */
-#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
-#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
-#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
-#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
-#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */
-#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */
-#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */
-#define ADC12EOS (0x0080) /* ADC12 End of Sequence */
-
-#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */
-#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */
-#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */
-#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */
-#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */
-#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */
-#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */
-#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */
-#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */
-#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */
-#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */
-#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */
-#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */
-#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */
-#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */
-#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */
-
-#define ADC12SREF_0 (0x0000) /* ADC12 Select Reference 0 */
-#define ADC12SREF_1 (0x0010) /* ADC12 Select Reference 1 */
-#define ADC12SREF_2 (0x0020) /* ADC12 Select Reference 2 */
-#define ADC12SREF_3 (0x0030) /* ADC12 Select Reference 3 */
-#define ADC12SREF_4 (0x0040) /* ADC12 Select Reference 4 */
-#define ADC12SREF_5 (0x0050) /* ADC12 Select Reference 5 */
-#define ADC12SREF_6 (0x0060) /* ADC12 Select Reference 6 */
-#define ADC12SREF_7 (0x0070) /* ADC12 Select Reference 7 */
-
-#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */
-#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */
-#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */
-#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */
-#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */
-#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */
-#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */
-#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */
-#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */
-#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */
-#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */
-#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */
-#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */
-#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */
-#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */
-#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */
-
-#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */
-#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */
-#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */
-#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */
-#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */
-#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */
-#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */
-#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */
-
-#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */
-#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */
-#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */
-#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */
-#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */
-#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */
-#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */
-#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */
-
-#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */
-#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */
-#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */
-#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */
-#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */
-#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */
-#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */
-#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */
-#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */
-#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */
-#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */
-#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */
-#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */
-#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */
-#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */
-#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */
-
-#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */
-#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */
-#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */
-#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */
-#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */
-#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */
-#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */
-#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */
-
-#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */
-#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */
-#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */
-#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */
-#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */
-#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */
-#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */
-#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */
-
-/* ADC12IV Definitions */
-#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
-#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
-#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
-#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */
-#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */
-#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */
-#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */
-#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */
-#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */
-#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */
-#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */
-#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */
-#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */
-#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */
-#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */
-#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */
-#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */
-#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */
-#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */
-
-/************************************************************
-* Comparator B
-************************************************************/
-#define __MSP430_HAS_COMPB_ /* Definition to show that Module is available */
-#define __MSP430_BASEADDRESS_COMPB_ 0x08C0
-#define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__
-
-#define CBCTL0 0x08C0 /* Comparator B Control Register 0 */
-#define CBCTL1 0x08C2 /* Comparator B Control Register 1 */
-#define CBCTL2 0x08C4 /* Comparator B Control Register 2 */
-#define CBCTL3 0x08C6 /* Comparator B Control Register 3 */
-#define CBINT 0x08CC /* Comparator B Interrupt Register */
-#define CBIV 0x08CE /* Comparator B Interrupt Vector Word */
-
-
-/* CBCTL0 Control Bits */
-#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */
-#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */
-#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */
-#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */
-//#define RESERVED (0x0010) /* Comp. B */
-//#define RESERVED (0x0020) /* Comp. B */
-//#define RESERVED (0x0040) /* Comp. B */
-#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */
-#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */
-#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */
-#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */
-#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */
-//#define RESERVED (0x1000) /* Comp. B */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */
-
-/* CBCTL0 Control Bits */
-#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */
-#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */
-#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */
-#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */
-//#define RESERVED (0x0010) /* Comp. B */
-//#define RESERVED (0x0020) /* Comp. B */
-//#define RESERVED (0x0040) /* Comp. B */
-#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */
-//#define RESERVED (0x1000) /* Comp. B */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-
-/* CBCTL0 Control Bits */
-//#define RESERVED (0x0010) /* Comp. B */
-//#define RESERVED (0x0020) /* Comp. B */
-//#define RESERVED (0x0040) /* Comp. B */
-#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */
-#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */
-#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */
-#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */
-//#define RESERVED (0x1000) /* Comp. B */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */
-
-#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */
-#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */
-#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */
-#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */
-#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */
-#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */
-#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */
-#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */
-#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */
-#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */
-#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */
-#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */
-#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */
-#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */
-#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */
-#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */
-
-#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */
-#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */
-#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */
-#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */
-#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */
-#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */
-#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */
-#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */
-#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */
-#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */
-#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */
-#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */
-#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */
-#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */
-#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */
-#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */
-
-/* CBCTL1 Control Bits */
-#define CBOUT (0x0001) /* Comp. B Output */
-#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */
-#define CBF (0x0004) /* Comp. B Enable Output Filter */
-#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */
-#define CBSHORT (0x0010) /* Comp. B Input Short */
-#define CBEX (0x0020) /* Comp. B Exchange Inputs */
-#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */
-#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */
-#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */
-#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */
-#define CBON (0x0400) /* Comp. B enable */
-#define CBMRVL (0x0800) /* Comp. B CBMRV Level */
-#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-//#define RESERVED (0x8000) /* Comp. B */
-
-/* CBCTL1 Control Bits */
-#define CBOUT_L (0x0001) /* Comp. B Output */
-#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */
-#define CBF_L (0x0004) /* Comp. B Enable Output Filter */
-#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */
-#define CBSHORT_L (0x0010) /* Comp. B Input Short */
-#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */
-#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */
-#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-//#define RESERVED (0x8000) /* Comp. B */
-
-/* CBCTL1 Control Bits */
-#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */
-#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */
-#define CBON_H (0x0004) /* Comp. B enable */
-#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */
-#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-//#define RESERVED (0x8000) /* Comp. B */
-
-#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */
-#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */
-#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */
-#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */
-
-#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */
-#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */
-#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/
-#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */
-
-
-/* CBCTL2 Control Bits */
-#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
-#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
-#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
-#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
-#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
-#define CBRSEL (0x0020) /* Comp. B Reference select */
-#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */
-#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */
-#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */
-#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */
-#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */
-#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */
-#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */
-#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */
-#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */
-#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */
-
-/* CBCTL2 Control Bits */
-#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */
-#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */
-#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */
-#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */
-#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */
-#define CBRSEL_L (0x0020) /* Comp. B Reference select */
-#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */
-#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */
-
-/* CBCTL2 Control Bits */
-#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */
-#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */
-#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */
-#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */
-#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */
-#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */
-#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */
-#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */
-
-#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */
-#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */
-#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */
-#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */
-#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */
-#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */
-#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */
-#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */
-#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */
-#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */
-#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */
-#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */
-#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */
-#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */
-#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */
-#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */
-#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */
-#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */
-#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */
-#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */
-#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */
-#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */
-#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */
-#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */
-#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */
-#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */
-#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */
-#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */
-#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */
-#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */
-#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */
-#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */
-
-#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */
-#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */
-#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */
-#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */
-
-#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */
-#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */
-#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */
-#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */
-#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */
-#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */
-#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */
-#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */
-#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */
-#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */
-#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */
-#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */
-#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */
-#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */
-#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */
-#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */
-#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */
-#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */
-#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */
-#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */
-#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */
-#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */
-#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */
-#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */
-#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */
-#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */
-#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */
-#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */
-#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */
-#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */
-#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */
-#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */
-
-#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */
-#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */
-#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */
-#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */
-
-
-#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
-#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
-#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
-#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
-#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
-#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
-#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
-#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
-#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */
-#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */
-#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */
-#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */
-#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */
-#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */
-#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */
-#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */
-
-#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */
-#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */
-#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */
-#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */
-#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */
-#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */
-#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */
-#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */
-
-#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */
-#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */
-#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */
-#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */
-#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */
-#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */
-#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */
-#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */
-
-
-/* CBINT Control Bits */
-#define CBIFG (0x0001) /* Comp. B Interrupt Flag */
-#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
-//#define RESERVED (0x0004) /* Comp. B */
-//#define RESERVED (0x0008) /* Comp. B */
-//#define RESERVED (0x0010) /* Comp. B */
-//#define RESERVED (0x0020) /* Comp. B */
-//#define RESERVED (0x0040) /* Comp. B */
-//#define RESERVED (0x0080) /* Comp. B */
-#define CBIE (0x0100) /* Comp. B Interrupt Enable */
-#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */
-//#define RESERVED (0x0400) /* Comp. B */
-//#define RESERVED (0x0800) /* Comp. B */
-//#define RESERVED (0x1000) /* Comp. B */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-//#define RESERVED (0x8000) /* Comp. B */
-
-/* CBINT Control Bits */
-#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */
-#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */
-//#define RESERVED (0x0004) /* Comp. B */
-//#define RESERVED (0x0008) /* Comp. B */
-//#define RESERVED (0x0010) /* Comp. B */
-//#define RESERVED (0x0020) /* Comp. B */
-//#define RESERVED (0x0040) /* Comp. B */
-//#define RESERVED (0x0080) /* Comp. B */
-//#define RESERVED (0x0400) /* Comp. B */
-//#define RESERVED (0x0800) /* Comp. B */
-//#define RESERVED (0x1000) /* Comp. B */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-//#define RESERVED (0x8000) /* Comp. B */
-
-/* CBINT Control Bits */
-//#define RESERVED (0x0004) /* Comp. B */
-//#define RESERVED (0x0008) /* Comp. B */
-//#define RESERVED (0x0010) /* Comp. B */
-//#define RESERVED (0x0020) /* Comp. B */
-//#define RESERVED (0x0040) /* Comp. B */
-//#define RESERVED (0x0080) /* Comp. B */
-#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */
-#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */
-//#define RESERVED (0x0400) /* Comp. B */
-//#define RESERVED (0x0800) /* Comp. B */
-//#define RESERVED (0x1000) /* Comp. B */
-//#define RESERVED (0x2000) /* Comp. B */
-//#define RESERVED (0x4000) /* Comp. B */
-//#define RESERVED (0x8000) /* Comp. B */
-
-/* CBIV Definitions */
-#define CBIV_NONE (0x0000) /* No Interrupt pending */
-#define CBIV_CBIFG (0x0002) /* CBIFG */
-#define CBIV_CBIIFG (0x0004) /* CBIIFG */
-
-/*************************************************************
-* CRC Module
-*************************************************************/
-
-#define CRCDI 0x0150 /* CRC Data In Register */
-#define CRCDIRB 0x0152 /* CRC data in reverse byte Register */
-#define CRCINIRES 0x0154 /* CRC Initialisation Register and Result Register */
-#define CRCRESR 0x0156 /* CRC reverse result Register */
-
-/************************************************************
-* DMA_X
-************************************************************/
-#define __MSP430_HAS_DMAX_3_ /* Definition to show that Module is available */
-#define __MSP430_BASEADDRESS_DMAX_3_ 0x0500
-#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__
-
-#define DMACTL0 0x0500 /* DMA Module Control 0 */
-#define DMACTL1 0x0502 /* DMA Module Control 1 */
-#define DMACTL2 0x0504 /* DMA Module Control 2 */
-#define DMACTL3 0x0506 /* DMA Module Control 3 */
-#define DMACTL4 0x0508 /* DMA Module Control 4 */
-#define DMAIV 0x050E /* DMA Interrupt Vector Word */
-
-#define DMA0CTL 0x0510 /* DMA Channel 0 Control */
-#define DMA0SA 0x0512 /* DMA Channel 0 Source Address */
-#define DMA0DA 0x0516 /* DMA Channel 0 Destination Address */
-#define DMA0SZ 0x051A /* DMA Channel 0 Transfer Size */
-
-#define DMA1CTL 0x0520 /* DMA Channel 1 Control */
-#define DMA1SA 0x0522 /* DMA Channel 1 Source Address */
-#define DMA1DA 0x0526 /* DMA Channel 1 Destination Address */
-#define DMA1SZ 0x052A /* DMA Channel 1 Transfer Size */
-
-#define DMA2CTL 0x0530 /* DMA Channel 2 Control */
-#define DMA2SA 0x0532 /* DMA Channel 2 Source Address */
-#define DMA2DA 0x0536 /* DMA Channel 2 Destination Address */
-#define DMA2SZ 0x053A /* DMA Channel 2 Transfer Size */
-
-/* DMACTL0 Control Bits */
-#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
-#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
-#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
-#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
-#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
-#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
-#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
-#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
-#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
-#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
-
-/* DMACTL0 Control Bits */
-#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
-#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
-#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
-#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
-#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
-
-/* DMACTL0 Control Bits */
-#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
-#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
-#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
-#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
-#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
-
-/* DMACTL01 Control Bits */
-#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
-#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
-#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
-#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
-#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
-
-/* DMACTL01 Control Bits */
-#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
-#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
-#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
-#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
-#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
-
-
-/* DMACTL4 Control Bits */
-#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
-#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
-#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
-
-/* DMACTL4 Control Bits */
-#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
-#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
-#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
-
-
-
-/* DMAxCTL Control Bits */
-#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
-#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
-#define DMAIE (0x0004) /* DMA interrupt enable */
-#define DMAIFG (0x0008) /* DMA interrupt flag */
-#define DMAEN (0x0010) /* DMA enable */
-#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
-#define DMASRCBYTE (0x0040) /* DMA source byte */
-#define DMADSTBYTE (0x0080) /* DMA destination byte */
-#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
-#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
-#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
-#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
-#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
-#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
-#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
-
-/* DMAxCTL Control Bits */
-#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
-#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
-#define DMAIE_L (0x0004) /* DMA interrupt enable */
-#define DMAIFG_L (0x0008) /* DMA interrupt flag */
-#define DMAEN_L (0x0010) /* DMA enable */
-#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
-#define DMASRCBYTE_L (0x0040) /* DMA source byte */
-#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
-
-/* DMAxCTL Control Bits */
-#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
-#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
-#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
-#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
-#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
-#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
-#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
-
-#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */
-#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */
-#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */
-#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */
-
-#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */
-#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */
-#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */
-#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */
-
-#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */
-#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */
-#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */
-#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */
-
-#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */
-#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */
-#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */
-#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */
-#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */
-#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */
-#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */
-#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */
-
-/* DMAIV Definitions */
-#define DMAIV_NONE (0x0000) /* No Interrupt pending */
-#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
-#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
-#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
-
-#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
-#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
-#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
-#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
-#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
-#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */
-#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */
-#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */
-#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */
-#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */
-#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */
-#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */
-#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */
-#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */
-#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */
-#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */
-#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */
-#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */
-#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */
-#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */
-#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */
-#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */
-#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */
-#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */
-#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */
-#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */
-#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */
-#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */
-#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: USB ready */
-#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */
-#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
-#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
-#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
-#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
-#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
-#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
-#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */
-#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */
-#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */
-#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */
-#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */
-#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */
-#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */
-#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */
-#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */
-#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */
-#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */
-#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */
-#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */
-#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */
-#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */
-#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */
-#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */
-#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */
-#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */
-#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */
-#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */
-#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */
-#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */
-#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: USB ready */
-#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */
-#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
-#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
-#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
-#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
-#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
-#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
-#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */
-#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */
-#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */
-#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */
-#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */
-#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */
-#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */
-#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */
-#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */
-#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */
-#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */
-#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */
-#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */
-#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */
-#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */
-#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */
-#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */
-#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */
-#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */
-#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */
-#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */
-#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */
-#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */
-#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: USB ready */
-#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */
-#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
-#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA0TSEL__DMA_REQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
-#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
-#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
-#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
-#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
-#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */
-#define DMA0TSEL__TA2CCR2 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */
-#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */
-#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */
-#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */
-#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */
-#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */
-#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */
-#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */
-#define DMA0TSEL__RES14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */
-#define DMA0TSEL__RES15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */
-#define DMA0TSEL__USCIA0RX (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */
-#define DMA0TSEL__USCIA0TX (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */
-#define DMA0TSEL__USCIB0RX (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */
-#define DMA0TSEL__USCIB0TX (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */
-#define DMA0TSEL__USCIA1RX (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */
-#define DMA0TSEL__USCIA1TX (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */
-#define DMA0TSEL__USCIB1RX (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */
-#define DMA0TSEL__USCIB1TX (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */
-#define DMA0TSEL__ADC12IFG (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */
-#define DMA0TSEL__RES25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */
-#define DMA0TSEL__RES26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */
-#define DMA0TSEL__USB_FNRXD (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */
-#define DMA0TSEL__USB_READY (0x001C) /* DMA channel 0 transfer select 28: USB ready */
-#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */
-#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
-#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA1TSEL__DMA_REQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
-#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
-#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
-#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
-#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
-#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */
-#define DMA1TSEL__TA2CCR2 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */
-#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */
-#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */
-#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */
-#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */
-#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */
-#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */
-#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */
-#define DMA1TSEL__RES14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */
-#define DMA1TSEL__RES15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */
-#define DMA1TSEL__USCIA0RX (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */
-#define DMA1TSEL__USCIA0TX (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */
-#define DMA1TSEL__USCIB0RX (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */
-#define DMA1TSEL__USCIB0TX (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */
-#define DMA1TSEL__USCIA1RX (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */
-#define DMA1TSEL__USCIA1TX (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */
-#define DMA1TSEL__USCIB1RX (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */
-#define DMA1TSEL__USCIB1TX (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */
-#define DMA1TSEL__ADC12IFG (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */
-#define DMA1TSEL__RES25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */
-#define DMA1TSEL__RES26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */
-#define DMA1TSEL__USB_FNRXD (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */
-#define DMA1TSEL__USB_READY (0x1C00) /* DMA channel 1 transfer select 28: USB ready */
-#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */
-#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
-#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA2TSEL__DMA_REQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
-#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
-#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
-#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
-#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
-#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */
-#define DMA2TSEL__TA2CCR2 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */
-#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */
-#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */
-#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */
-#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */
-#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */
-#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */
-#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */
-#define DMA2TSEL__RES14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */
-#define DMA2TSEL__RES15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */
-#define DMA2TSEL__USCIA0RX (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */
-#define DMA2TSEL__USCIA0TX (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */
-#define DMA2TSEL__USCIB0RX (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */
-#define DMA2TSEL__USCIB0TX (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */
-#define DMA2TSEL__USCIA1RX (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */
-#define DMA2TSEL__USCIA1TX (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */
-#define DMA2TSEL__USCIB1RX (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */
-#define DMA2TSEL__USCIB1TX (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */
-#define DMA2TSEL__ADC12IFG (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */
-#define DMA2TSEL__RES25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */
-#define DMA2TSEL__RES26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */
-#define DMA2TSEL__USB_FNRXD (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */
-#define DMA2TSEL__USB_READY (0x001C) /* DMA channel 2 transfer select 28: USB ready */
-#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */
-#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
-#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
-
-/*************************************************************
-* Flash Memory
-*************************************************************/
-
-#define FCTL1 0x0140 /* FLASH Control 1 */
-//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */
-#define FCTL3 0x0144 /* FLASH Control 3 */
-#define FCTL4 0x0146 /* FLASH Control 4 */
-
-#define FRPW (0x9600) /* Flash password returned by read */
-#define FWPW (0xA500) /* Flash password for write */
-#define FXPW (0x3300) /* for use with XOR instruction */
-#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */
-#define FWKEY (0xA500) /* (legacy definition) Flash key for write */
-#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */
-
-/* FCTL1 Control Bits */
-//#define RESERVED (0x0001) /* Reserved */
-#define ERASE (0x0002) /* Enable bit for Flash segment erase */
-#define MERAS (0x0004) /* Enable bit for Flash mass erase */
-//#define RESERVED (0x0008) /* Reserved */
-//#define RESERVED (0x0010) /* Reserved */
-#define SWRT (0x0020) /* Smart Write enable */
-#define WRT (0x0040) /* Enable bit for Flash write */
-#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
-
-/* FCTL1 Control Bits */
-//#define RESERVED (0x0001) /* Reserved */
-#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */
-#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */
-//#define RESERVED (0x0008) /* Reserved */
-//#define RESERVED (0x0010) /* Reserved */
-#define SWRT_L (0x0020) /* Smart Write enable */
-#define WRT_L (0x0040) /* Enable bit for Flash write */
-#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */
-
-
-/* FCTL3 Control Bits */
-#define BUSY (0x0001) /* Flash busy: 1 */
-#define KEYV (0x0002) /* Flash Key violation flag */
-#define ACCVIFG (0x0004) /* Flash Access violation flag */
-#define WAIT (0x0008) /* Wait flag for segment write */
-#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
-#define EMEX (0x0020) /* Flash Emergency Exit */
-#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
-//#define RESERVED (0x0080) /* Reserved */
-
-/* FCTL3 Control Bits */
-#define BUSY_L (0x0001) /* Flash busy: 1 */
-#define KEYV_L (0x0002) /* Flash Key violation flag */
-#define ACCVIFG_L (0x0004) /* Flash Access violation flag */
-#define WAIT_L (0x0008) /* Wait flag for segment write */
-#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
-#define EMEX_L (0x0020) /* Flash Emergency Exit */
-#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
-//#define RESERVED (0x0080) /* Reserved */
-
-
-/* FCTL4 Control Bits */
-#define VPE (0x0001) /* Voltage Changed during Program Error Flag */
-#define MGR0 (0x0010) /* Marginal read 0 mode. */
-#define MGR1 (0x0020) /* Marginal read 1 mode. */
-#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
-
-/* FCTL4 Control Bits */
-#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */
-#define MGR0_L (0x0010) /* Marginal read 0 mode. */
-#define MGR1_L (0x0020) /* Marginal read 1 mode. */
-#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */
-
-
-/************************************************************
-* HARDWARE MULTIPLIER 32Bit
-************************************************************/
-
-#define MPY 0x04C0 /* Multiply Unsigned/Operand 1 */
-#define MPYS 0x04C2 /* Multiply Signed/Operand 1 */
-#define MAC 0x04C4 /* Multiply Unsigned and Accumulate/Operand 1 */
-#define MACS 0x04C6 /* Multiply Signed and Accumulate/Operand 1 */
-#define OP2 0x04C8 /* Operand 2 */
-#define RESLO 0x04CA /* Result Low Word */
-#define RESHI 0x04CC /* Result High Word */
-#define SUMEXT 0x04CE /* Sum Extend */
-
-#define MPY32L 0x04D0 /* 32-bit operand 1 - multiply - low word */
-#define MPY32H 0x04D2 /* 32-bit operand 1 - multiply - high word */
-#define MPYS32L 0x04D4 /* 32-bit operand 1 - signed multiply - low word */
-#define MPYS32H 0x04D6 /* 32-bit operand 1 - signed multiply - high word */
-#define MAC32L 0x04D8 /* 32-bit operand 1 - multiply accumulate - low word */
-#define MAC32H 0x04DA /* 32-bit operand 1 - multiply accumulate - high word */
-#define MACS32L 0x04DC /* 32-bit operand 1 - signed multiply accumulate - low word */
-#define MACS32H 0x04DE /* 32-bit operand 1 - signed multiply accumulate - high word */
-#define OP2L 0x04E0 /* 32-bit operand 2 - low word */
-#define OP2H 0x04E2 /* 32-bit operand 2 - high word */
-#define RES0 0x04E4 /* 32x32-bit result 0 - least significant word */
-#define RES1 0x04E6 /* 32x32-bit result 1 */
-#define RES2 0x04E8 /* 32x32-bit result 2 */
-#define RES3 0x04EA /* 32x32-bit result 3 - most significant word */
-#define MPY32CTL0 0x04EC /* MPY32 Control Register 0 */
-
-#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
-#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
-#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
-#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
-#define OP2_B OP2_L /* Operand 2 (Byte Access) */
-#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
-#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
-#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
-#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
-#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
-#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
-#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
-#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
-#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
-#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
-
-
-/* MPY32CTL0 Control Bits */
-#define MPYC (0x0001) /* Carry of the multiplier */
-//#define RESERVED (0x0002) /* Reserved */
-#define MPYFRAC (0x0004) /* Fractional mode */
-#define MPYSAT (0x0008) /* Saturation mode */
-#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
-#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
-#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
-#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
-#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
-#define MPYDLY32 (0x0200) /* Delayed write mode */
-
-/* MPY32CTL0 Control Bits */
-#define MPYC_L (0x0001) /* Carry of the multiplier */
-//#define RESERVED (0x0002) /* Reserved */
-#define MPYFRAC_L (0x0004) /* Fractional mode */
-#define MPYSAT_L (0x0008) /* Saturation mode */
-#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
-#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
-#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
-#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
-
-/* MPY32CTL0 Control Bits */
-//#define RESERVED (0x0002) /* Reserved */
-#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
-#define MPYDLY32_H (0x0002) /* Delayed write mode */
-
-#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
-#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
-#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
-#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
-#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
-#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
-#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
-#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
-
-/************************************************************
-* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
-************************************************************/
-
-#define PAIN 0x0200 /* Port A Input */
-#define PAOUT 0x0202 /* Port A Output */
-#define PADIR 0x0204 /* Port A Direction */
-#define PAREN 0x0206 /* Port A Resistor Enable */
-#define PADS 0x0208 /* Port A Drive Strenght */
-#define PASEL 0x020A /* Port A Selection */
-#define PASEL_L (PASEL)
-#define PASEL_H (PASEL+1)
-#define PAIES 0x0218 /* Port A Interrupt Edge Select */
-#define PAIE 0x021A /* Port A Interrupt Enable */
-#define PAIFG 0x021C /* Port A Interrupt Flag */
-
-#define P1IV 0x020E /* Port 1 Interrupt Vector Word */
-#define P2IV 0x021E /* Port 2 Interrupt Vector Word */
-#define P1IN (PAIN_L) /* Port 1 Input */
-#define P1OUT (PAOUT_L) /* Port 1 Output */
-#define P1DIR (PADIR_L) /* Port 1 Direction */
-#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
-#define P1DS (PADS_L) /* Port 1 Drive Strenght */
-#define P1SEL (PASEL_L) /* Port 1 Selection */
-#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
-#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
-#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
-
-//Definitions for P1IV
-#define P1IV_NONE (0x0000) /* No Interrupt pending */
-#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
-#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
-#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
-#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
-#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
-#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
-#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
-#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
-
-
-#define P2IN (PAIN_H) /* Port 2 Input */
-#define P2OUT (PAOUT_H) /* Port 2 Output */
-#define P2DIR (PADIR_H) /* Port 2 Direction */
-#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
-#define P2DS (PADS_H) /* Port 2 Drive Strenght */
-#define P2SEL (PASEL_H) /* Port 2 Selection */
-#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
-#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
-#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
-
-//Definitions for P2IV
-#define P2IV_NONE (0x0000) /* No Interrupt pending */
-#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
-#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
-#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
-#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
-#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
-#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
-#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
-#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
-
-
-
-/************************************************************
-* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
-************************************************************/
-
-#define PBIN 0x0220 /* Port B Input */
-#define PBOUT 0x0222 /* Port B Output */
-#define PBDIR 0x0224 /* Port B Direction */
-#define PBREN 0x0226 /* Port B Resistor Enable */
-#define PBDS 0x0228 /* Port B Drive Strenght */
-#define PBSEL 0x022A /* Port B Selection */
-#define PBSEL_H (PBSEL+1)
-
-#define P3IN (PBIN_L) /* Port 3 Input */
-#define P3OUT (PBOUT_L) /* Port 3 Output */
-#define P3DIR (PBDIR_L) /* Port 3 Direction */
-#define P3REN (PBREN_L) /* Port 3 Resistor Enable */
-#define P3DS (PBDS_L) /* Port 3 Drive Strenght */
-#define P3SEL (PBSEL_L) /* Port 3 Selection */
-
-
-#define P4IN (PBIN_H) /* Port 4 Input */
-#define P4OUT (PBOUT_H) /* Port 4 Output */
-#define P4DIR (PBDIR_H) /* Port 4 Direction */
-#define P4REN (PBREN_H) /* Port 4 Resistor Enable */
-#define P4DS (PBDS_H) /* Port 4 Drive Strenght */
-#define P4SEL (PBSEL_H) /* Port 4 Selection */
-
-
-
-/************************************************************
-* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
-************************************************************/
-
-#define PCIN 0x0240 /* Port C Input */
-#define PCOUT 0x0242 /* Port C Output */
-#define PCDIR 0x0244 /* Port C Direction */
-#define PCREN 0x0246 /* Port C Resistor Enable */
-#define PCDS 0x0248 /* Port C Drive Strenght */
-#define PCSEL 0x024A /* Port C Selection */
-
-#define P5IN (PCIN_L) /* Port 5 Input */
-#define P5OUT (PCOUT_L) /* Port 5 Output */
-#define P5DIR (PCDIR_L) /* Port 5 Direction */
-#define P5REN (PCREN_L) /* Port 5 Resistor Enable */
-#define P5DS (PCDS_L) /* Port 5 Drive Strenght */
-#define P5SEL (PCSEL_L) /* Port 5 Selection */
-
-
-#define P6IN (PCIN_H) /* Port 6 Input */
-#define P6OUT (PCOUT_H) /* Port 6 Output */
-#define P6DIR (PCDIR_H) /* Port 6 Direction */
-#define P6REN (PCREN_H) /* Port 6 Resistor Enable */
-#define P6DS (PCDS_H) /* Port 6 Drive Strenght */
-#define P6SEL (PCSEL_H) /* Port 6 Selection */
-
-
-
-/************************************************************
-* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
-************************************************************/
-
-#define PDIN 0x0260 /* Port D Input */
-#define PDOUT 0x0262 /* Port D Output */
-#define PDDIR 0x0264 /* Port D Direction */
-#define PDREN 0x0266 /* Port D Resistor Enable */
-#define PDDS 0x0268 /* Port D Drive Strenght */
-#define PDSEL 0x026A /* Port D Selection */
-
-#define P7IN (PDIN_L) /* Port 7 Input */
-#define P7OUT (PDOUT_L) /* Port 7 Output */
-#define P7DIR (PDDIR_L) /* Port 7 Direction */
-#define P7REN (PDREN_L) /* Port 7 Resistor Enable */
-#define P7DS (PDDS_L) /* Port 7 Drive Strenght */
-#define P7SEL (PDSEL_L) /* Port 7 Selection */
-
-
-#define P8IN (PDIN_H) /* Port 8 Input */
-#define P8OUT (PDOUT_H) /* Port 8 Output */
-#define P8DIR (PDDIR_H) /* Port 8 Direction */
-#define P8REN (PDREN_H) /* Port 8 Resistor Enable */
-#define P8DS (PDDS_H) /* Port 8 Drive Strenght */
-#define P8SEL (PDSEL_H) /* Port 8 Selection */
-
-
-
-/************************************************************
-* DIGITAL I/O PortJ Pull up / Pull down Resistors
-************************************************************/
-
-#define PJIN 0x0320 /* Port J Input */
-#define PJOUT 0x0322 /* Port J Output */
-#define PJDIR 0x0324 /* Port J Direction */
-#define PJREN 0x0326 /* Port J Resistor Enable */
-#define PJDS 0x0328 /* Port J Drive Strenght */
-
-/************************************************************
-* PORT MAPPING CONTROLLER
-************************************************************/
-#define PMAPKEYID 0x01C0 /* Port Mapping Key register */
-#define PMAPCTL 0x01C2 /* Port Mapping control register */
-
-#define PMAPKEY (0x2D52) /* Port Mapping Key */
-#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */
-#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */
-
-/* PMAPCTL Control Bits */
-#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */
-#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */
-
-/* PMAPCTL Control Bits */
-#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */
-#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */
-
-
-/************************************************************
-* PORT 4 MAPPING CONTROLLER
-************************************************************/
-
-#define P4MAP01 0x01E0 /* Port P4.0/1 mapping register */
-#define P4MAP23 0x01E2 /* Port P4.2/3 mapping register */
-#define P4MAP45 0x01E4 /* Port P4.4/5 mapping register */
-#define P4MAP67 0x01E6 /* Port P4.6/7 mapping register */
-
-#define P4MAP0 P4MAP01_L /* Port P4.0 mapping register */
-#define P4MAP1 P4MAP01_H /* Port P4.1 mapping register */
-#define P4MAP2 P4MAP23_L /* Port P4.2 mapping register */
-#define P4MAP3 P4MAP23_H /* Port P4.3 mapping register */
-#define P4MAP4 P4MAP45_L /* Port P4.4 mapping register */
-#define P4MAP5 P4MAP45_H /* Port P4.5 mapping register */
-#define P4MAP6 P4MAP67_L /* Port P4.6 mapping register */
-#define P4MAP7 P4MAP67_H /* Port P4.7 mapping register */
-
-#define PM_NONE 0
-#define PM_CBOUT0 1
-#define PM_TB0CLK 1
-#define PM_ADC12CLK 2
-#define PM_DMAE0 2
-#define PM_SVMOUT 3
-#define PM_TB0OUTH 3
-#define PM_TB0CCR0A 4
-#define PM_TB0CCR1A 5
-#define PM_TB0CCR2A 6
-#define PM_TB0CCR3A 7
-#define PM_TB0CCR4A 8
-#define PM_TB0CCR5A 9
-#define PM_TB0CCR6A 10
-#define PM_UCA1RXD 11
-#define PM_UCA1SOMI 11
-#define PM_UCA1TXD 12
-#define PM_UCA1SIMO 12
-#define PM_UCA1CLK 13
-#define PM_UCB1STE 13
-#define PM_UCB1SOMI 14
-#define PM_UCB1SCL 14
-#define PM_UCB1SIMO 15
-#define PM_UCB1SDA 15
-#define PM_UCB1CLK 16
-#define PM_UCA1STE 16
-#define PM_CBOUT1 17
-#define PM_MCLK 18
-#define PM_ANALOG 31
-
-/************************************************************
-* PMM - Power Management System
-************************************************************/
-
-#define PMMCTL0 0x0120 /* PMM Control 0 */
-#define PMMCTL1 0x0122 /* PMM Control 1 */
-#define SVSMHCTL 0x0124 /* SVS and SVM high side control register */
-#define SVSMLCTL 0x0126 /* SVS and SVM low side control register */
-#define SVSMIO 0x0128 /* SVSIN and SVSOUT control register */
-#define PMMIFG 0x012C /* PMM Interrupt Flag */
-#define PMMRIE 0x012E /* PMM and RESET Interrupt Enable */
-#define PM5CTL0 0x0130 /* PMM Power Mode 5 Control Register 0 */
-
-#define PMMPW (0xA500) /* PMM Register Write Password */
-#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
-
-/* PMMCTL0 Control Bits */
-#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */
-#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */
-#define PMMSWBOR (0x0004) /* PMM Software BOR */
-#define PMMSWPOR (0x0008) /* PMM Software POR */
-#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
-#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */
-
-/* PMMCTL0 Control Bits */
-#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */
-#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */
-#define PMMSWBOR_L (0x0004) /* PMM Software BOR */
-#define PMMSWPOR_L (0x0008) /* PMM Software POR */
-#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
-#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */
-
-
-#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */
-#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */
-#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */
-#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */
-
-
-/* PMMCTL1 Control Bits */
-#define PMMREFMD (0x0001) /* PMM Reference Mode */
-#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
-#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
-
-/* PMMCTL1 Control Bits */
-#define PMMREFMD_L (0x0001) /* PMM Reference Mode */
-#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */
-#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */
-
-
-/* SVSMHCTL Control Bits */
-#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
-#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
-#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
-#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */
-#define SVSHMD (0x0010) /* SVS high side mode */
-#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */
-#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */
-#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */
-#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */
-#define SVSHE (0x0400) /* SVS high side enable */
-#define SVSHFP (0x0800) /* SVS high side full performace mode */
-#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */
-#define SVMHE (0x4000) /* SVM high side enable */
-#define SVMHFP (0x8000) /* SVM high side full performace mode */
-
-/* SVSMHCTL Control Bits */
-#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
-#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
-#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
-#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */
-#define SVSHMD_L (0x0010) /* SVS high side mode */
-#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */
-#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */
-
-/* SVSMHCTL Control Bits */
-#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */
-#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */
-#define SVSHE_H (0x0004) /* SVS high side enable */
-#define SVSHFP_H (0x0008) /* SVS high side full performace mode */
-#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */
-#define SVMHE_H (0x0040) /* SVM high side enable */
-#define SVMHFP_H (0x0080) /* SVM high side full performace mode */
-
-#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */
-#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */
-#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */
-#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */
-#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */
-#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */
-#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */
-#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */
-
-#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */
-#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */
-#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */
-#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */
-
-
-/* SVSMLCTL Control Bits */
-#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
-#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
-#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
-#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */
-#define SVSLMD (0x0010) /* SVS low side mode */
-#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */
-#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */
-#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */
-#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */
-#define SVSLE (0x0400) /* SVS low side enable */
-#define SVSLFP (0x0800) /* SVS low side full performace mode */
-#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */
-#define SVMLE (0x4000) /* SVM low side enable */
-#define SVMLFP (0x8000) /* SVM low side full performace mode */
-
-/* SVSMLCTL Control Bits */
-#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
-#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
-#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
-#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */
-#define SVSLMD_L (0x0010) /* SVS low side mode */
-#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */
-#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */
-
-/* SVSMLCTL Control Bits */
-#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */
-#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */
-#define SVSLE_H (0x0004) /* SVS low side enable */
-#define SVSLFP_H (0x0008) /* SVS low side full performace mode */
-#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */
-#define SVMLE_H (0x0040) /* SVM low side enable */
-#define SVMLFP_H (0x0080) /* SVM low side full performace mode */
-
-#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */
-#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */
-#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */
-#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */
-#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */
-#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */
-#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */
-#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */
-
-#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */
-#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */
-#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */
-#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */
-
-
-/* SVSMIO Control Bits */
-#define SVMLOE (0x0008) /* SVM low side output enable */
-#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */
-#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */
-#define SVMHOE (0x0800) /* SVM high side output enable */
-#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */
-
-/* SVSMIO Control Bits */
-#define SVMLOE_L (0x0008) /* SVM low side output enable */
-#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */
-#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */
-
-/* SVSMIO Control Bits */
-#define SVMHOE_H (0x0008) /* SVM high side output enable */
-#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */
-
-
-/* PMMIFG Control Bits */
-#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
-#define SVMLIFG (0x0002) /* SVM low side interrupt flag */
-#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
-#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
-#define SVMHIFG (0x0020) /* SVM high side interrupt flag */
-#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
-#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
-#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
-#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
-#define SVSHIFG (0x1000) /* SVS low side interrupt flag */
-#define SVSLIFG (0x2000) /* SVS high side interrupt flag */
-#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
-
-/* PMMIFG Control Bits */
-#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */
-#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */
-#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */
-#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */
-#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */
-#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */
-
-/* PMMIFG Control Bits */
-#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
-#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
-#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
-#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */
-#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */
-#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
-
-#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */
-
-
-/* PMMIE and RESET Control Bits */
-#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
-#define SVMLIE (0x0002) /* SVM low side interrupt enable */
-#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
-#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
-#define SVMHIE (0x0020) /* SVM high side interrupt enable */
-#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
-#define SVSLPE (0x0100) /* SVS low side POR enable */
-#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */
-#define SVSHPE (0x1000) /* SVS high side POR enable */
-#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */
-
-/* PMMIE and RESET Control Bits */
-#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */
-#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */
-#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */
-#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */
-#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */
-#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */
-
-/* PMMIE and RESET Control Bits */
-#define SVSLPE_H (0x0001) /* SVS low side POR enable */
-#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */
-#define SVSHPE_H (0x0010) /* SVS high side POR enable */
-#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */
-
-/* PM5CTL0 Power Mode 5 Control Bits */
-#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
-
-/* PM5CTL0 Power Mode 5 Control Bits */
-#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
-
-#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
-
-/*************************************************************
-* RAM Control Module
-*************************************************************/
-
-#define RCCTL0 0x0158 /* Ram Controller Control Register */
-
-/* RCCTL0 Control Bits */
-#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */
-#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */
-#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */
-#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */
-#define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */
-
-/* RCCTL0 Control Bits */
-#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */
-#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */
-#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */
-#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */
-#define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */
-
-
-#define RCKEY (0x5A00)
-
-/************************************************************
-* Shared Reference
-************************************************************/
-
-#define REFCTL0 0x01B0 /* REF Shared Reference control register 0 */
-
-/* REFCTL0 Control Bits */
-#define REFON (0x0001) /* REF Reference On */
-#define REFOUT (0x0002) /* REF Reference output Buffer On */
-//#define RESERVED (0x0004) /* Reserved */
-#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
-#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
-#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
-//#define RESERVED (0x0040) /* Reserved */
-#define REFMSTR (0x0080) /* REF Master Control */
-#define REFGENACT (0x0100) /* REF Reference generator active */
-#define REFBGACT (0x0200) /* REF Reference bandgap active */
-#define REFGENBUSY (0x0400) /* REF Reference generator busy */
-#define BGMODE (0x0800) /* REF Bandgap mode */
-//#define RESERVED (0x1000) /* Reserved */
-//#define RESERVED (0x2000) /* Reserved */
-//#define RESERVED (0x4000) /* Reserved */
-//#define RESERVED (0x8000) /* Reserved */
-
-/* REFCTL0 Control Bits */
-#define REFON_L (0x0001) /* REF Reference On */
-#define REFOUT_L (0x0002) /* REF Reference output Buffer On */
-//#define RESERVED (0x0004) /* Reserved */
-#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
-#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
-#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
-//#define RESERVED (0x0040) /* Reserved */
-#define REFMSTR_L (0x0080) /* REF Master Control */
-//#define RESERVED (0x1000) /* Reserved */
-//#define RESERVED (0x2000) /* Reserved */
-//#define RESERVED (0x4000) /* Reserved */
-//#define RESERVED (0x8000) /* Reserved */
-
-/* REFCTL0 Control Bits */
-//#define RESERVED (0x0004) /* Reserved */
-//#define RESERVED (0x0040) /* Reserved */
-#define REFGENACT_H (0x0001) /* REF Reference generator active */
-#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
-#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
-#define BGMODE_H (0x0008) /* REF Bandgap mode */
-//#define RESERVED (0x1000) /* Reserved */
-//#define RESERVED (0x2000) /* Reserved */
-//#define RESERVED (0x4000) /* Reserved */
-//#define RESERVED (0x8000) /* Reserved */
-
-#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */
-#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
-#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
-#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
-
-/************************************************************
-* Real Time Clock
-************************************************************/
-
-#define RTCCTL01 0x04A0 /* Real Timer Control 0/1 */
-#define RTCCTL23 0x04A2 /* Real Timer Control 2/3 */
-#define RTCPS0CTL 0x04A8 /* Real Timer Prescale Timer 0 Control */
-#define RTCPS1CTL 0x04AA /* Real Timer Prescale Timer 1 Control */
-#define RTCPS 0x04AC /* Real Timer Prescale Timer Control */
-#define RTCIV 0x04AE /* Real Time Clock Interrupt Vector */
-#define RTCTIM0 0x04B0 /* Real Time Clock Time 0 */
-#define RTCTIM1 0x04B2 /* Real Time Clock Time 1 */
-#define RTCDATE 0x04B4 /* Real Time Clock Date */
-#define RTCYEAR 0x04B6 /* Real Time Clock Year */
-#define RTCAMINHR 0x04B8 /* Real Time Clock Alarm Min/Hour */
-#define RTCADOWDAY 0x04BA /* Real Time Clock Alarm day of week/day */
-
-#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
-#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
-#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
-#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
-#define RTCNT12 RTCTIM0
-#define RTCNT34 RTCTIM1
-#define RTCNT1 RTCTIM0_L
-#define RTCNT2 RTCTIM0_H
-#define RTCNT3 RTCTIM1_L
-#define RTCNT4 RTCTIM1_H
-#define RTCSEC RTCTIM0_L
-#define RTCMIN RTCTIM0_H
-#define RTCHOUR RTCTIM1_L
-#define RTCDOW RTCTIM1_H
-#define RTCDAY RTCDATE_L
-#define RTCMON RTCDATE_H
-#define RTCYEARL RTCYEAR_L
-#define RTCYEARH RTCYEAR_H
-#define RT0PS RTCPS_L
-#define RT1PS RTCPS_H
-#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
-#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
-#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
-#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
-
-/* RTCCTL01 Control Bits */
-#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
-#define RTCHOLD (0x4000) /* RTC Hold */
-#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */
-#define RTCRDY (0x1000) /* RTC Ready */
-#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */
-#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */
-#define RTCTEV1 (0x0200) /* RTC Time Event 1 */
-#define RTCTEV0 (0x0100) /* RTC Time Event 0 */
-//#define Reserved (0x0080)
-#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
-#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
-#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
-//#define Reserved (0x0008)
-#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
-#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
-#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
-
-/* RTCCTL01 Control Bits */
-//#define Reserved (0x0080)
-#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
-#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
-#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
-//#define Reserved (0x0008)
-#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
-#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
-#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
-
-/* RTCCTL01 Control Bits */
-#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
-#define RTCHOLD_H (0x0040) /* RTC Hold */
-#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
-#define RTCRDY_H (0x0010) /* RTC Ready */
-#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */
-#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */
-#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
-#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
-//#define Reserved (0x0080)
-//#define Reserved (0x0008)
-
-#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
-#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */
-#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */
-#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */
-#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */
-#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */
-#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */
-#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
-#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
-#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
-#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
-#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
-#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
-#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
-#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
-
-/* RTCCTL23 Control Bits */
-#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
-#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
-#define RTCCALS (0x0080) /* RTC Calibration Sign */
-//#define Reserved (0x0040)
-#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
-#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
-#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
-#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
-#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
-#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
-
-/* RTCCTL23 Control Bits */
-#define RTCCALS_L (0x0080) /* RTC Calibration Sign */
-//#define Reserved (0x0040)
-#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
-#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
-#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
-#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
-#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
-#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
-
-/* RTCCTL23 Control Bits */
-#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
-#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
-//#define Reserved (0x0040)
-
-#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
-#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
-#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
-#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
-
-
-
-#define RTCAE (0x80) /* Real Time Clock Alarm enable */
-
-
-
-
-/* RTCPS0CTL Control Bits */
-//#define Reserved (0x8000)
-#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
-#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
-#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
-#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
-//#define Reserved (0x0400)
-//#define Reserved (0x0200)
-#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
-#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
-#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
-#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
-#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
-
-/* RTCPS0CTL Control Bits */
-//#define Reserved (0x8000)
-//#define Reserved (0x0400)
-//#define Reserved (0x0200)
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
-#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
-#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
-#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
-#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
-
-/* RTCPS0CTL Control Bits */
-//#define Reserved (0x8000)
-#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */
-#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
-#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
-#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
-//#define Reserved (0x0400)
-//#define Reserved (0x0200)
-#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-
-#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
-#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
-#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
-#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
-#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
-#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
-#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
-#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
-
-#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */
-#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */
-#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */
-#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */
-#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */
-#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */
-#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */
-#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */
-
-
-/* RTCPS1CTL Control Bits */
-#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */
-#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */
-#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
-#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
-#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
-//#define Reserved (0x0400)
-//#define Reserved (0x0200)
-#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
-#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
-#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
-#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
-#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
-
-/* RTCPS1CTL Control Bits */
-//#define Reserved (0x0400)
-//#define Reserved (0x0200)
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
-#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
-#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
-#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
-#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
-
-/* RTCPS1CTL Control Bits */
-#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */
-#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */
-#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
-#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
-#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
-//#define Reserved (0x0400)
-//#define Reserved (0x0200)
-#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-
-#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
-#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
-#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
-#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
-#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
-#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
-#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
-#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
-
-#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */
-#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */
-#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */
-#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */
-#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */
-#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */
-#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */
-#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */
-
-#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */
-#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */
-#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */
-#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */
-
-/* RTC Definitions */
-#define RTCIV_NONE (0x0000) /* No Interrupt pending */
-#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
-#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
-#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
-#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
-#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
-
-/* Legacy Definitions */
-#define RTC_NONE (0x0000) /* No Interrupt pending */
-#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
-#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
-#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
-#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
-#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
-
-/************************************************************
-* SFR - Special Function Register Module
-************************************************************/
-
-#define SFRIE1 0x0100 /* Interrupt Enable 1 */
-
-/* SFRIE1 Control Bits */
-#define WDTIE (0x0001) /* WDT Interrupt Enable */
-#define OFIE (0x0002) /* Osc Fault Enable */
-//#define Reserved (0x0004)
-#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
-#define NMIIE (0x0010) /* NMI Interrupt Enable */
-#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */
-#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
-#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
-
-#define WDTIE_L (0x0001) /* WDT Interrupt Enable */
-#define OFIE_L (0x0002) /* Osc Fault Enable */
-//#define Reserved (0x0004)
-#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
-#define NMIIE_L (0x0010) /* NMI Interrupt Enable */
-#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */
-#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
-#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
-
-
-#define SFRIFG1 0x0102 /* Interrupt Flag 1 */
-/* SFRIFG1 Control Bits */
-#define WDTIFG (0x0001) /* WDT Interrupt Flag */
-#define OFIFG (0x0002) /* Osc Fault Flag */
-//#define Reserved (0x0004)
-#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
-#define NMIIFG (0x0010) /* NMI Interrupt Flag */
-//#define Reserved (0x0020)
-#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
-#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
-
-#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
-#define OFIFG_L (0x0002) /* Osc Fault Flag */
-//#define Reserved (0x0004)
-#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
-#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
-//#define Reserved (0x0020)
-#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
-#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
-
-
-#define SFRRPCR 0x0104 /* RESET Pin Control Register */
-/* SFRRPCR Control Bits */
-#define SYSNMI (0x0001) /* NMI select */
-#define SYSNMIIES (0x0002) /* NMI edge select */
-#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
-#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
-
-#define SYSNMI_L (0x0001) /* NMI select */
-#define SYSNMIIES_L (0x0002) /* NMI edge select */
-#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
-#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
-
-
-/************************************************************
-* SYS - System Module
-************************************************************/
-
-#define SYSCTL 0x0180 /* System control */
-#define SYSBSLC 0x0182 /* Boot strap configuration area */
-#define SYSJMBC 0x0186 /* JTAG mailbox control */
-#define SYSJMBI0 0x0188 /* JTAG mailbox input 0 */
-#define SYSJMBI1 0x018A /* JTAG mailbox input 1 */
-#define SYSJMBO0 0x018C /* JTAG mailbox output 0 */
-#define SYSJMBO1 0x018E /* JTAG mailbox output 1 */
-
-#define SYSBERRIV 0x0198 /* Bus Error vector generator */
-#define SYSUNIV 0x019A /* User NMI vector generator */
-#define SYSSNIV 0x019C /* System NMI vector generator */
-#define SYSRSTIV 0x019E /* Reset vector generator */
-
-/* SYSCTL Control Bits */
-#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
-//#define RESERVED (0x0002) /* SYS - Reserved */
-#define SYSPMMPE (0x0004) /* SYS - PMM access protect */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
-#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-/* SYSCTL Control Bits */
-#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
-//#define RESERVED (0x0002) /* SYS - Reserved */
-#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
-#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-
-/* SYSBSLC Control Bits */
-#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */
-#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */
-#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-//#define RESERVED (0x0010) /* SYS - Reserved */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */
-#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */
-
-/* SYSBSLC Control Bits */
-#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */
-#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */
-#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-//#define RESERVED (0x0010) /* SYS - Reserved */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-
-/* SYSBSLC Control Bits */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-//#define RESERVED (0x0010) /* SYS - Reserved */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */
-#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */
-
-/* SYSJMBC Control Bits */
-#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
-#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
-#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
-#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
-#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
-#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-/* SYSJMBC Control Bits */
-#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
-#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
-#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
-#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
-#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
-#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-
-
-
-
-
-
-/* SYSUNIV Definitions */
-#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */
-#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */
-#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */
-#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */
-#define SYSUNIV_BUSIFG (0x0008) /* SYSUNIV : Bus Error */
-#define SYSUNIV_SYSBUSIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIFG (legacy) */
-
-/* SYSSNIV Definitions */
-#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */
-#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */
-#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */
-#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */
-#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */
-#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */
-#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */
-#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */
-#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */
-#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */
-
-/* SYSRSTIV Definitions */
-#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
-#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
-#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
-#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
-#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
-#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
-#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */
-#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */
-#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */
-#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */
-#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
-#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
-#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
-#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */
-#define SYSRSTIV_FLLUL (0x001C) /* SYSRSTIV : FLL unlock */
-#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
-#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */
-
-/************************************************************
-* Timer0_A5
-************************************************************/
-
-#define TA0CTL 0x0340 /* Timer0_A5 Control */
-#define TA0CCTL0 0x0342 /* Timer0_A5 Capture/Compare Control 0 */
-#define TA0CCTL1 0x0344 /* Timer0_A5 Capture/Compare Control 1 */
-#define TA0CCTL2 0x0346 /* Timer0_A5 Capture/Compare Control 2 */
-#define TA0CCTL3 0x0348 /* Timer0_A5 Capture/Compare Control 3 */
-#define TA0CCTL4 0x034A /* Timer0_A5 Capture/Compare Control 4 */
-#define TA0R 0x0350 /* Timer0_A5 */
-#define TA0CCR0 0x0352 /* Timer0_A5 Capture/Compare 0 */
-#define TA0CCR1 0x0354 /* Timer0_A5 Capture/Compare 1 */
-#define TA0CCR2 0x0356 /* Timer0_A5 Capture/Compare 2 */
-#define TA0CCR3 0x0358 /* Timer0_A5 Capture/Compare 3 */
-#define TA0CCR4 0x035A /* Timer0_A5 Capture/Compare 4 */
-#define TA0IV 0x036E /* Timer0_A5 Interrupt Vector Word */
-#define TA0EX0 0x0360 /* Timer0_A5 Expansion Register 0 */
-
-/* TAxCTL Control Bits */
-#define TASSEL1 (0x0200) /* Timer A clock source select 1 */
-#define TASSEL0 (0x0100) /* Timer A clock source select 0 */
-#define ID1 (0x0080) /* Timer A clock input divider 1 */
-#define ID0 (0x0040) /* Timer A clock input divider 0 */
-#define MC1 (0x0020) /* Timer A mode control 1 */
-#define MC0 (0x0010) /* Timer A mode control 0 */
-#define TACLR (0x0004) /* Timer A counter clear */
-#define TAIE (0x0002) /* Timer A counter interrupt enable */
-#define TAIFG (0x0001) /* Timer A counter interrupt flag */
-
-#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */
-#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
-#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */
-#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */
-#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */
-#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */
-#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */
-#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */
-#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */
-#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */
-#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */
-#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */
-#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */
-#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
-#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */
-#define MC__CONTINOUS (0x0020) /* Legacy define */
-#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */
-#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */
-#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */
-#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */
-#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */
-#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */
-#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */
-#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */
-#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */
-
-/* TAxCCTLx Control Bits */
-#define CM1 (0x8000) /* Capture mode 1 */
-#define CM0 (0x4000) /* Capture mode 0 */
-#define CCIS1 (0x2000) /* Capture input select 1 */
-#define CCIS0 (0x1000) /* Capture input select 0 */
-#define SCS (0x0800) /* Capture sychronize */
-#define SCCI (0x0400) /* Latched capture signal (read) */
-#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
-#define OUTMOD2 (0x0080) /* Output mode 2 */
-#define OUTMOD1 (0x0040) /* Output mode 1 */
-#define OUTMOD0 (0x0020) /* Output mode 0 */
-#define CCIE (0x0010) /* Capture/compare interrupt enable */
-#define CCI (0x0008) /* Capture input signal (read) */
-#define OUT (0x0004) /* PWM Output signal if output mode 0 */
-#define COV (0x0002) /* Capture/compare overflow flag */
-#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-
-#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */
-#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */
-#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */
-#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */
-#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */
-#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */
-#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */
-#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */
-#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */
-#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */
-#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */
-#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */
-#define CM_0 (0x0000) /* Capture mode: 0 - disabled */
-#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */
-#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */
-#define CM_3 (0xC000) /* Capture mode: 1 - both edges */
-
-
-/* TAxEX0 Control Bits */
-#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
-#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
-#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
-
-#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */
-#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */
-#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */
-#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */
-#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */
-#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */
-#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */
-#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */
-
-/* T0A5IV Definitions */
-#define TA0IV_NONE (0x0000) /* No Interrupt pending */
-#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
-#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
-#define TA0IV_TACCR3 (0x0006) /* TA0CCR3_CCIFG */
-#define TA0IV_TACCR4 (0x0008) /* TA0CCR4_CCIFG */
-#define TA0IV_5 (0x000A) /* Reserved */
-#define TA0IV_6 (0x000C) /* Reserved */
-#define TA0IV_TAIFG (0x000E) /* TA0IFG */
-
-/* Legacy Defines */
-#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */
-#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */
-#define TA0IV_TA0CCR3 (0x0006) /* TA0CCR3_CCIFG */
-#define TA0IV_TA0CCR4 (0x0008) /* TA0CCR4_CCIFG */
-#define TA0IV_TA0IFG (0x000E) /* TA0IFG */
-
-/************************************************************
-* Timer1_A3
-************************************************************/
-
-#define TA1CTL 0x0380 /* Timer1_A3 Control */
-#define TA1CCTL0 0x0382 /* Timer1_A3 Capture/Compare Control 0 */
-#define TA1CCTL1 0x0384 /* Timer1_A3 Capture/Compare Control 1 */
-#define TA1CCTL2 0x0386 /* Timer1_A3 Capture/Compare Control 2 */
-#define TA1R 0x0390 /* Timer1_A3 */
-#define TA1CCR0 0x0392 /* Timer1_A3 Capture/Compare 0 */
-#define TA1CCR1 0x0394 /* Timer1_A3 Capture/Compare 1 */
-#define TA1CCR2 0x0396 /* Timer1_A3 Capture/Compare 2 */
-#define TA1IV 0x03AE /* Timer1_A3 Interrupt Vector Word */
-#define TA1EX0 0x03A0 /* Timer1_A3 Expansion Register 0 */
-
-/* Bits are already defined within the Timer0_Ax */
-
-/* TA1IV Definitions */
-#define TA1IV_NONE (0x0000) /* No Interrupt pending */
-#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
-#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
-#define TA1IV_3 (0x0006) /* Reserved */
-#define TA1IV_4 (0x0008) /* Reserved */
-#define TA1IV_5 (0x000A) /* Reserved */
-#define TA1IV_6 (0x000C) /* Reserved */
-#define TA1IV_TAIFG (0x000E) /* TA1IFG */
-
-/* Legacy Defines */
-#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */
-#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */
-#define TA1IV_TA1IFG (0x000E) /* TA1IFG */
-
-/************************************************************
-* Timer2_A3
-************************************************************/
-
-#define TA2CTL 0x0400 /* Timer2_A3 Control */
-#define TA2CCTL0 0x0402 /* Timer2_A3 Capture/Compare Control 0 */
-#define TA2CCTL1 0x0404 /* Timer2_A3 Capture/Compare Control 1 */
-#define TA2CCTL2 0x0406 /* Timer2_A3 Capture/Compare Control 2 */
-#define TA2R 0x0410 /* Timer2_A3 */
-#define TA2CCR0 0x0412 /* Timer2_A3 Capture/Compare 0 */
-#define TA2CCR1 0x0414 /* Timer2_A3 Capture/Compare 1 */
-#define TA2CCR2 0x0416 /* Timer2_A3 Capture/Compare 2 */
-#define TA2IV 0x042E /* Timer2_A3 Interrupt Vector Word */
-#define TA2EX0 0x0420 /* Timer2_A3 Expansion Register 0 */
-
-/* Bits are already defined within the Timer0_Ax */
-
-/* TA2IV Definitions */
-#define TA2IV_NONE (0x0000) /* No Interrupt pending */
-#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */
-#define TA2IV_TACCR2 (0x0004) /* TA2CCR2_CCIFG */
-#define TA2IV_3 (0x0006) /* Reserved */
-#define TA2IV_4 (0x0008) /* Reserved */
-#define TA2IV_5 (0x000A) /* Reserved */
-#define TA2IV_6 (0x000C) /* Reserved */
-#define TA2IV_TAIFG (0x000E) /* TA2IFG */
-
-/* Legacy Defines */
-#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */
-#define TA2IV_TA2CCR2 (0x0004) /* TA2CCR2_CCIFG */
-#define TA2IV_TA2IFG (0x000E) /* TA2IFG */
-
-/************************************************************
-* Timer0_B7
-************************************************************/
-
-#define TB0CTL 0x03C0 /* Timer0_B7 Control */
-#define TB0CCTL0 0x03C2 /* Timer0_B7 Capture/Compare Control 0 */
-#define TB0CCTL1 0x03C4 /* Timer0_B7 Capture/Compare Control 1 */
-#define TB0CCTL2 0x03C6 /* Timer0_B7 Capture/Compare Control 2 */
-#define TB0CCTL3 0x03C8 /* Timer0_B7 Capture/Compare Control 3 */
-#define TB0CCTL4 0x03CA /* Timer0_B7 Capture/Compare Control 4 */
-#define TB0CCTL5 0x03CC /* Timer0_B7 Capture/Compare Control 5 */
-#define TB0CCTL6 0x03CE /* Timer0_B7 Capture/Compare Control 6 */
-#define TB0R 0x03D0 /* Timer0_B7 */
-#define TB0CCR0 0x03D2 /* Timer0_B7 Capture/Compare 0 */
-#define TB0CCR1 0x03D4 /* Timer0_B7 Capture/Compare 1 */
-#define TB0CCR2 0x03D6 /* Timer0_B7 Capture/Compare 2 */
-#define TB0CCR3 0x03D8 /* Timer0_B7 Capture/Compare 3 */
-#define TB0CCR4 0x03DA /* Timer0_B7 Capture/Compare 4 */
-#define TB0CCR5 0x03DC /* Timer0_B7 Capture/Compare 5 */
-#define TB0CCR6 0x03DE /* Timer0_B7 Capture/Compare 6 */
-#define TB0EX0 0x03E0 /* Timer0_B7 Expansion Register 0 */
-#define TB0IV 0x03EE /* Timer0_B7 Interrupt Vector Word */
-
-/* Legacy Type Definitions for TimerB */
-#define TBCTL TB0CTL /* Timer0_B7 Control */
-#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */
-#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */
-#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */
-#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */
-#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */
-#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */
-#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */
-#define TBR TB0R /* Timer0_B7 */
-#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */
-#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */
-#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */
-#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */
-#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */
-#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */
-#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */
-#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */
-#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */
-#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
-#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
-
-
-/* TBxCTL Control Bits */
-#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
-#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
-#define CNTL1 (0x1000) /* Counter lenght 1 */
-#define CNTL0 (0x0800) /* Counter lenght 0 */
-#define TBSSEL1 (0x0200) /* Clock source 1 */
-#define TBSSEL0 (0x0100) /* Clock source 0 */
-#define TBCLR (0x0004) /* Timer0_B7 counter clear */
-#define TBIE (0x0002) /* Timer0_B7 interrupt enable */
-#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */
-
-#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
-#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
-
-#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */
-#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */
-#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */
-#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */
-#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */
-#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */
-#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */
-#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */
-#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
-#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
-#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
-#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
-#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
-#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
-#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
-#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
-#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */
-#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
-#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */
-#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */
-#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */
-#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */
-#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */
-#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */
-#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */
-
-/* Additional Timer B Control Register bits are defined in Timer A */
-/* TBxCCTLx Control Bits */
-#define CLLD1 (0x0400) /* Compare latch load source 1 */
-#define CLLD0 (0x0200) /* Compare latch load source 0 */
-
-#define SLSHR1 (0x0400) /* Compare latch load source 1 */
-#define SLSHR0 (0x0200) /* Compare latch load source 0 */
-
-#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
-#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
-#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
-#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
-
-#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
-#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
-#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
-#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
-
-/* TBxEX0 Control Bits */
-#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */
-#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */
-#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */
-
-#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
-#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
-#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
-#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
-#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
-#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
-#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
-#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
-#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
-#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
-#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
-#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
-#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
-#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
-#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
-#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
-
-/* TB0IV Definitions */
-#define TB0IV_NONE (0x0000) /* No Interrupt pending */
-#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */
-#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */
-#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */
-#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */
-#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */
-#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */
-#define TB0IV_TBIFG (0x000E) /* TB0IFG */
-
-/* Legacy Defines */
-#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */
-#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */
-#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */
-#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */
-#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */
-#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */
-#define TB0IV_TB0IFG (0x000E) /* TB0IFG */
-
-
-/************************************************************
-* USB
-************************************************************/
-
-/* ========================================================================= */
-/* USB Configuration Registers */
-/* ========================================================================= */
-#define USBKEYID 0x0900 /* USB Controller key register */
-#define USBCNF 0x0902 /* USB Module configuration register */
-#define USBPHYCTL 0x0904 /* USB PHY control register */
-#define USBPWRCTL 0x0908 /* USB Power control register */
-#define USBPLLCTL 0x0910 /* USB PLL control register */
-#define USBPLLDIVB 0x0912 /* USB PLL Clock Divider Buffer control register */
-#define USBPLLIR 0x0914 /* USB PLL Interrupt control register */
-
-#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */
-#define USBKEY (0x9628) /* USB Control Register key */
-
-/* USBCNF Control Bits */
-#define USB_EN (0x0001) /* USB - Module enable */
-#define PUR_EN (0x0002) /* USB - PUR pin enable */
-#define PUR_IN (0x0004) /* USB - PUR pin input value */
-#define BLKRDY (0x0008) /* USB - Block ready signal for DMA */
-#define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-//#define RESERVED (0x0100) /* USB - */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBCNF Control Bits */
-#define USB_EN_L (0x0001) /* USB - Module enable */
-#define PUR_EN_L (0x0002) /* USB - PUR pin enable */
-#define PUR_IN_L (0x0004) /* USB - PUR pin input value */
-#define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */
-#define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-//#define RESERVED (0x0100) /* USB - */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-
-/* USBPHYCTL Control Bits */
-#define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */
-#define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */
-#define PUIN0 (0x0004) /* USB - PU0/DP Input Data */
-#define PUIN1 (0x0008) /* USB - PU1/DM Input Data */
-//#define RESERVED (0x0010) /* USB - */
-#define PUOPE (0x0020) /* USB - USB Port Output Enable */
-//#define RESERVED (0x0040) /* USB - */
-#define PUSEL (0x0080) /* USB - USB Port Function Select */
-#define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0100) /* USB - */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPHYCTL Control Bits */
-#define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */
-#define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */
-#define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */
-#define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */
-//#define RESERVED (0x0010) /* USB - */
-#define PUOPE_L (0x0020) /* USB - USB Port Output Enable */
-//#define RESERVED (0x0040) /* USB - */
-#define PUSEL_L (0x0080) /* USB - USB Port Function Select */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0100) /* USB - */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPHYCTL Control Bits */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-#define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0100) /* USB - */
-//#define RESERVED (0x0200) /* USB - */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-#define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */
-#define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */
-
-/* USBPWRCTL Control Bits */
-#define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */
-#define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */
-#define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */
-#define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */
-#define USBDETEN (0x0010) /* USB - VBUS on/off events enable */
-#define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */
-#define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */
-//#define RESERVED (0x0080) /* USB - */
-#define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */
-#define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */
-#define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */
-#define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */
-#define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPWRCTL Control Bits */
-#define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */
-#define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */
-#define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */
-#define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */
-#define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */
-#define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */
-#define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */
-//#define RESERVED (0x0080) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPWRCTL Control Bits */
-//#define RESERVED (0x0080) /* USB - */
-#define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */
-#define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */
-#define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */
-#define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */
-#define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-
-/* USBPLLCTL Control Bits */
-//#define RESERVED (0x0001) /* USB - */
-//#define RESERVED (0x0002) /* USB - */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-#define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */
-#define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */
-#define UPLLEN (0x0100) /* USB - PLL enable */
-#define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPLLCTL Control Bits */
-//#define RESERVED (0x0001) /* USB - */
-//#define RESERVED (0x0002) /* USB - */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-#define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */
-#define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPLLCTL Control Bits */
-//#define RESERVED (0x0001) /* USB - */
-//#define RESERVED (0x0002) /* USB - */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-#define UPLLEN_H (0x0001) /* USB - PLL enable */
-#define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */
-//#define RESERVED (0x0400) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-#define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */
-#define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */
-#define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */
-#define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */
-
-#define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */
-#define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */
-#define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */
-
-/* USBPLLDIVB Control Bits */
-#define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */
-#define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */
-#define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */
-#define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */
-#define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */
-#define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-#define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */
-#define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */
-#define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPLLDIVB Control Bits */
-#define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */
-#define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */
-#define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */
-#define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */
-#define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */
-#define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPLLDIVB Control Bits */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-#define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */
-#define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */
-#define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */
-#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */
-#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */
-#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */
-#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */
-#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */
-#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */
-#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */
-#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */
-#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */
-#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */
-#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */
-#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */
-#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */
-#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */
-#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */
-#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */
-#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */
-#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */
-#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */
-#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */
-#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */
-#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */
-#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */
-#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */
-#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */
-#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */
-#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */
-#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */
-#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */
-#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */
-#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */
-#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */
-#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */
-#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */
-#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */
-#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */
-#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */
-#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */
-#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */
-#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */
-#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */
-#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */
-
-
-/* USBPLLIR Control Bits */
-#define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */
-#define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */
-#define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-#define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */
-#define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */
-#define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPLLIR Control Bits */
-#define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */
-#define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */
-#define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-/* USBPLLIR Control Bits */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-#define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */
-#define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */
-#define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */
-//#define RESERVED (0x0800) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-//#define RESERVED (0x2000) /* USB - */
-//#define RESERVED (0x4000) /* USB - */
-//#define RESERVED (0x8000) /* USB - */
-
-
-
-/* ========================================================================= */
-/* USB Control Registers */
-/* ========================================================================= */
-#define USBIEPCNF_0 0x0920 /* USB Input endpoint_0: Configuration */
-#define USBIEPCNT_0 0x0921 /* USB Input endpoint_0: Byte Count */
-#define USBOEPCNF_0 0x0922 /* USB Output endpoint_0: Configuration */
-#define USBOEPCNT_0 0x0923 /* USB Output endpoint_0: byte count */
-#define USBIEPIE 0x092E /* USB Input endpoint interrupt enable flags */
-#define USBOEPIE 0x092F /* USB Output endpoint interrupt enable flags */
-#define USBIEPIFG 0x0930 /* USB Input endpoint interrupt flags */
-#define USBOEPIFG 0x0931 /* USB Output endpoint interrupt flags */
-#define USBVECINT 0x0932 /* USB Vector interrupt register */
-#define USBMAINT 0x0936 /* USB maintenance register */
-#define USBTSREG 0x0938 /* USB Time Stamp register */
-#define USBFN 0x093A /* USB Frame number */
-#define USBCTL 0x093C /* USB control register */
-#define USBIE 0x093D /* USB interrupt enable register */
-#define USBIFG 0x093E /* USB interrupt flag register */
-#define USBFUNADR 0x093F /* USB Function address register */
-
-#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */
-
-/* USBIEPCNF_0 Control Bits */
-/* USBOEPCNF_0 Control Bits */
-//#define RESERVED (0x0001) /* USB - */
-//#define RESERVED (0x0001) /* USB - */
-#define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */
-#define STALL (0x0008) /* USB - Stall Condition */
-//#define RESERVED (0x0010) /* USB - */
-#define TOGGLE (0x0020) /* USB - Toggle Bit */
-//#define RESERVED (0x0040) /* USB - */
-#define UBME (0x0080) /* USB - UBM In-Endpoint Enable */
-
-/* USBIEPBCNT_0 Control Bits */
-/* USBOEPBCNT_0 Control Bits */
-#define CNT0 (0x0001) /* USB - Byte Count Bit 0 */
-#define CNT1 (0x0001) /* USB - Byte Count Bit 1 */
-#define CNT2 (0x0004) /* USB - Byte Count Bit 2 */
-#define CNT3 (0x0008) /* USB - Byte Count Bit 3 */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-#define NAK (0x0080) /* USB - No Acknowledge Status Bit */
-
-
-/* USBMAINT Control Bits */
-#define UTIFG (0x0001) /* USB - Timer Interrupt Flag */
-#define UTIE (0x0002) /* USB - Timer Interrupt Enable */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-#define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */
-#define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */
-#define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */
-#define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */
-//#define RESERVED (0x1000) /* USB - */
-#define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */
-#define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */
-#define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */
-
-/* USBMAINT Control Bits */
-#define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */
-#define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-//#define RESERVED (0x1000) /* USB - */
-
-/* USBMAINT Control Bits */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-//#define RESERVED (0x0020) /* USB - */
-//#define RESERVED (0x0040) /* USB - */
-//#define RESERVED (0x0080) /* USB - */
-#define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */
-#define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */
-#define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */
-#define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */
-//#define RESERVED (0x1000) /* USB - */
-#define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */
-#define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */
-#define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */
-
-#define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */
-#define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */
-#define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */
-#define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */
-
-#define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */
-#define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */
-#define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */
-#define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */
-#define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */
-#define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */
-#define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */
-#define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */
-
-/* USBCTL Control Bits */
-#define DIR (0x0001) /* USB - Data Response Bit */
-//#define RESERVED (0x0002) /* USB - */
-//#define RESERVED (0x0004) /* USB - */
-//#define RESERVED (0x0008) /* USB - */
-#define FRSTE (0x0010) /* USB - Function Reset Connection Enable */
-#define RWUP (0x0020) /* USB - Device Remote Wakeup Request */
-#define FEN (0x0040) /* USB - Function Enable Bit */
-//#define RESERVED (0x0080) /* USB - */
-
-/* USBIE Control Bits */
-#define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */
-//#define RESERVED (0x0002) /* USB - */
-#define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-#define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */
-#define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */
-#define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */
-
-/* USBIFG Control Bits */
-#define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */
-//#define RESERVED (0x0002) /* USB - */
-#define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */
-//#define RESERVED (0x0008) /* USB - */
-//#define RESERVED (0x0010) /* USB - */
-#define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */
-#define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */
-#define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */
-
-//values of USBVECINT when USB-interrupt occured
-#define USBVECINT_NONE 0x00
-#define USBVECINT_PWR_DROP 0x02
-#define USBVECINT_PLL_LOCK 0x04
-#define USBVECINT_PLL_SIGNAL 0x06
-#define USBVECINT_PLL_RANGE 0x08
-#define USBVECINT_PWR_VBUSOn 0x0A
-#define USBVECINT_PWR_VBUSOff 0x0C
-#define USBVECINT_USB_TIMESTAMP 0x10
-#define USBVECINT_INPUT_ENDPOINT0 0x12
-#define USBVECINT_OUTPUT_ENDPOINT0 0x14
-#define USBVECINT_RSTR 0x16
-#define USBVECINT_SUSR 0x18
-#define USBVECINT_RESR 0x1A
-#define USBVECINT_SETUP_PACKET_RECEIVED 0x20
-#define USBVECINT_STPOW_PACKET_RECEIVED 0x22
-#define USBVECINT_INPUT_ENDPOINT1 0x24
-#define USBVECINT_INPUT_ENDPOINT2 0x26
-#define USBVECINT_INPUT_ENDPOINT3 0x28
-#define USBVECINT_INPUT_ENDPOINT4 0x2A
-#define USBVECINT_INPUT_ENDPOINT5 0x2C
-#define USBVECINT_INPUT_ENDPOINT6 0x2E
-#define USBVECINT_INPUT_ENDPOINT7 0x30
-#define USBVECINT_OUTPUT_ENDPOINT1 0x32
-#define USBVECINT_OUTPUT_ENDPOINT2 0x34
-#define USBVECINT_OUTPUT_ENDPOINT3 0x36
-#define USBVECINT_OUTPUT_ENDPOINT4 0x38
-#define USBVECINT_OUTPUT_ENDPOINT5 0x3A
-#define USBVECINT_OUTPUT_ENDPOINT6 0x3C
-#define USBVECINT_OUTPUT_ENDPOINT7 0x3E
-
-
-/* ========================================================================= */
-/* USB Operation Registers */
-/* ========================================================================= */
-
-#define USBIEPSIZXY_7 0x23FF /* Input Endpoint_7: X/Y-buffer size */
-#define USBIEPBCTY_7 0x23FE /* Input Endpoint_7: Y-byte count */
-#define USBIEPBBAY_7 0x23FD /* Input Endpoint_7: Y-buffer base addr. */
-//sfrb Spare (0x23FC) /* Not used */
-//sfrb Spare (0x23FB) /* Not used */
-#define USBIEPBCTX_7 0x23FA /* Input Endpoint_7: X-byte count */
-#define USBIEPBBAX_7 0x23F9 /* Input Endpoint_7: X-buffer base addr. */
-#define USBIEPCNF_7 0x23F8 /* Input Endpoint_7: Configuration */
-#define USBIEPSIZXY_6 0x23F7 /* Input Endpoint_6: X/Y-buffer size */
-#define USBIEPBCTY_6 0x23F6 /* Input Endpoint_6: Y-byte count */
-#define USBIEPBBAY_6 0x23F5 /* Input Endpoint_6: Y-buffer base addr. */
-//sfrb Spare (0x23F4) /* Not used */
-//sfrb Spare (0x23F3) /* Not used */
-#define USBIEPBCTX_6 0x23F2 /* Input Endpoint_6: X-byte count */
-#define USBIEPBBAX_6 0x23F1 /* Input Endpoint_6: X-buffer base addr. */
-#define USBIEPCNF_6 0x23F0 /* Input Endpoint_6: Configuration */
-#define USBIEPSIZXY_5 0x23EF /* Input Endpoint_5: X/Y-buffer size */
-#define USBIEPBCTY_5 0x23EE /* Input Endpoint_5: Y-byte count */
-#define USBIEPBBAY_5 0x23ED /* Input Endpoint_5: Y-buffer base addr. */
-//sfrb Spare (0x23EC) /* Not used */
-//sfrb Spare (0x23EB) /* Not used */
-#define USBIEPBCTX_5 0x23EA /* Input Endpoint_5: X-byte count */
-#define USBIEPBBAX_5 0x23E9 /* Input Endpoint_5: X-buffer base addr. */
-#define USBIEPCNF_5 0x23E8 /* Input Endpoint_5: Configuration */
-#define USBIEPSIZXY_4 0x23E7 /* Input Endpoint_4: X/Y-buffer size */
-#define USBIEPBCTY_4 0x23E6 /* Input Endpoint_4: Y-byte count */
-#define USBIEPBBAY_4 0x23E5 /* Input Endpoint_4: Y-buffer base addr. */
-//sfrb Spare (0x23E4) /* Not used */
-//sfrb Spare (0x23E3) /* Not used */
-#define USBIEPBCTX_4 0x23E2 /* Input Endpoint_4: X-byte count */
-#define USBIEPBBAX_4 0x23E1 /* Input Endpoint_4: X-buffer base addr. */
-#define USBIEPCNF_4 0x23E0 /* Input Endpoint_4: Configuration */
-#define USBIEPSIZXY_3 0x23DF /* Input Endpoint_3: X/Y-buffer size */
-#define USBIEPBCTY_3 0x23DE /* Input Endpoint_3: Y-byte count */
-#define USBIEPBBAY_3 0x23DD /* Input Endpoint_3: Y-buffer base addr. */
-//sfrb Spare (0x23DC) /* Not used */
-//sfrb Spare (0x23DB) /* Not used */
-#define USBIEPBCTX_3 0x23DA /* Input Endpoint_3: X-byte count */
-#define USBIEPBBAX_3 0x23D9 /* Input Endpoint_3: X-buffer base addr. */
-#define USBIEPCNF_3 0x23D8 /* Input Endpoint_3: Configuration */
-#define USBIEPSIZXY_2 0x23D7 /* Input Endpoint_2: X/Y-buffer size */
-#define USBIEPBCTY_2 0x23D6 /* Input Endpoint_2: Y-byte count */
-#define USBIEPBBAY_2 0x23D5 /* Input Endpoint_2: Y-buffer base addr. */
-//sfrb Spare (0x23D4) /* Not used */
-//sfrb Spare (0x23D3) /* Not used */
-#define USBIEPBCTX_2 0x23D2 /* Input Endpoint_2: X-byte count */
-#define USBIEPBBAX_2 0x23D1 /* Input Endpoint_2: X-buffer base addr. */
-#define USBIEPCNF_2 0x23D0 /* Input Endpoint_2: Configuration */
-#define USBIEPSIZXY_1 0x23CF /* Input Endpoint_1: X/Y-buffer size */
-#define USBIEPBCTY_1 0x23CE /* Input Endpoint_1: Y-byte count */
-#define USBIEPBBAY_1 0x23CD /* Input Endpoint_1: Y-buffer base addr. */
-//sfrb Spare (0x23CC) /* Not used */
-//sfrb Spare (0x23CB) /* Not used */
-#define USBIEPBCTX_1 0x23CA /* Input Endpoint_1: X-byte count */
-#define USBIEPBBAX_1 0x23C9 /* Input Endpoint_1: X-buffer base addr. */
-#define USBIEPCNF_1 0x23C8 /* Input Endpoint_1: Configuration */
-//sfrb (0x23C7) /* */
-//sfrb RESERVED (0x1C00) /* */
-//sfrb (0x23C0) /* */
-#define USBOEPSIZXY_7 0x23BF /* Output Endpoint_7: X/Y-buffer size */
-#define USBOEPBCTY_7 0x23BE /* Output Endpoint_7: Y-byte count */
-#define USBOEPBBAY_7 0x23BD /* Output Endpoint_7: Y-buffer base addr. */
-//sfrb Spare (0x23BC) /* Not used */
-//sfrb Spare (0x23BB) /* Not used */
-#define USBOEPBCTX_7 0x23BA /* Output Endpoint_7: X-byte count */
-#define USBOEPBBAX_7 0x23B9 /* Output Endpoint_7: X-buffer base addr. */
-#define USBOEPCNF_7 0x23B8 /* Output Endpoint_7: Configuration */
-#define USBOEPSIZXY_6 0x23B7 /* Output Endpoint_6: X/Y-buffer size */
-#define USBOEPBCTY_6 0x23B6 /* Output Endpoint_6: Y-byte count */
-#define USBOEPBBAY_6 0x23B5 /* Output Endpoint_6: Y-buffer base addr. */
-//sfrb Spare (0x23B4) /* Not used */
-//sfrb Spare (0x23B3) /* Not used */
-#define USBOEPBCTX_6 0x23B2 /* Output Endpoint_6: X-byte count */
-#define USBOEPBBAX_6 0x23B1 /* Output Endpoint_6: X-buffer base addr. */
-#define USBOEPCNF_6 0x23B0 /* Output Endpoint_6: Configuration */
-#define USBOEPSIZXY_5 0x23AF /* Output Endpoint_5: X/Y-buffer size */
-#define USBOEPBCTY_5 0x23AE /* Output Endpoint_5: Y-byte count */
-#define USBOEPBBAY_5 0x23AD /* Output Endpoint_5: Y-buffer base addr. */
-//sfrb Spare (0x23AC) /* Not used */
-//sfrb Spare (0x23AB) /* Not used */
-#define USBOEPBCTX_5 0x23AA /* Output Endpoint_5: X-byte count */
-#define USBOEPBBAX_5 0x23A9 /* Output Endpoint_5: X-buffer base addr. */
-#define USBOEPCNF_5 0x23A8 /* Output Endpoint_5: Configuration */
-#define USBOEPSIZXY_4 0x23A7 /* Output Endpoint_4: X/Y-buffer size */
-#define USBOEPBCTY_4 0x23A6 /* Output Endpoint_4: Y-byte count */
-#define USBOEPBBAY_4 0x23A5 /* Output Endpoint_4: Y-buffer base addr. */
-//sfrb Spare (0x23A4) /* Not used */
-//sfrb Spare (0x23A3) /* Not used */
-#define USBOEPBCTX_4 0x23A2 /* Output Endpoint_4: X-byte count */
-#define USBOEPBBAX_4 0x23A1 /* Output Endpoint_4: X-buffer base addr. */
-#define USBOEPCNF_4 0x23A0 /* Output Endpoint_4: Configuration */
-#define USBOEPSIZXY_3 0x239F /* Output Endpoint_3: X/Y-buffer size */
-#define USBOEPBCTY_3 0x239E /* Output Endpoint_3: Y-byte count */
-#define USBOEPBBAY_3 0x239D /* Output Endpoint_3: Y-buffer base addr. */
-//sfrb Spare (0x239C) /* Not used */
-//sfrb Spare (0x239B) /* Not used */
-#define USBOEPBCTX_3 0x239A /* Output Endpoint_3: X-byte count */
-#define USBOEPBBAX_3 0x2399 /* Output Endpoint_3: X-buffer base addr. */
-#define USBOEPCNF_3 0x2398 /* Output Endpoint_3: Configuration */
-#define USBOEPSIZXY_2 0x2397 /* Output Endpoint_2: X/Y-buffer size */
-#define USBOEPBCTY_2 0x2396 /* Output Endpoint_2: Y-byte count */
-#define USBOEPBBAY_2 0x2395 /* Output Endpoint_2: Y-buffer base addr. */
-//sfrb Spare (0x2394) /* Not used */
-//sfrb Spare (0x2393) /* Not used */
-#define USBOEPBCTX_2 0x2392 /* Output Endpoint_2: X-byte count */
-#define USBOEPBBAX_2 0x2391 /* Output Endpoint_2: X-buffer base addr. */
-#define USBOEPCNF_2 0x2390 /* Output Endpoint_2: Configuration */
-#define USBOEPSIZXY_1 0x238F /* Output Endpoint_1: X/Y-buffer size */
-#define USBOEPBCTY_1 0x238E /* Output Endpoint_1: Y-byte count */
-#define USBOEPBBAY_1 0x238D /* Output Endpoint_1: Y-buffer base addr. */
-//sfrb Spare (0x238C) /* Not used */
-//sfrb Spare (0x238B) /* Not used */
-#define USBOEPBCTX_1 0x238A /* Output Endpoint_1: X-byte count */
-#define USBOEPBBAX_1 0x2389 /* Output Endpoint_1: X-buffer base addr. */
-#define USBOEPCNF_1 0x2388 /* Output Endpoint_1: Configuration */
-#define USBSUBLK 0x2380 /* Setup Packet Block */
-#define USBIEP0BUF 0x2378 /* Input endpoint_0 buffer */
-#define USBOEP0BUF 0x2370 /* Output endpoint_0 buffer */
-#define USBTOPBUFF 0x236F /* Top of buffer space */
-// (1904 Bytes) /* Buffer space */
-#define USBSTABUFF 0x1C00 /* Start of buffer space */
-
-/* USBIEPCNF_n Control Bits */
-/* USBOEPCNF_n Control Bits */
-//#define RESERVED (0x0001) /* USB - */
-//#define RESERVED (0x0001) /* USB - */
-#define DBUF (0x0010) /* USB - Double Buffer Enable */
-//#define RESERVED (0x0040) /* USB - */
-
-/* USBIEPBCNT_n Control Bits */
-/* USBOEPBCNT_n Control Bits */
-#define CNT4 (0x0010) /* USB - Byte Count Bit 3 */
-#define CNT5 (0x0020) /* USB - Byte Count Bit 3 */
-#define CNT6 (0x0040) /* USB - Byte Count Bit 3 */
-/************************************************************
-* UNIFIED CLOCK SYSTEM
-************************************************************/
-
-#define UCSCTL0 0x0160 /* UCS Control Register 0 */
-#define UCSCTL1 0x0162 /* UCS Control Register 1 */
-#define UCSCTL2 0x0164 /* UCS Control Register 2 */
-#define UCSCTL3 0x0166 /* UCS Control Register 3 */
-#define UCSCTL4 0x0168 /* UCS Control Register 4 */
-#define UCSCTL5 0x016A /* UCS Control Register 5 */
-#define UCSCTL6 0x016C /* UCS Control Register 6 */
-#define UCSCTL7 0x016E /* UCS Control Register 7 */
-#define UCSCTL8 0x0170 /* UCS Control Register 8 */
-
-/* UCSCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */
-#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */
-#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */
-#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */
-#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */
-#define DCO0 (0x0100) /* DCO TAP Bit : 0 */
-#define DCO1 (0x0200) /* DCO TAP Bit : 1 */
-#define DCO2 (0x0400) /* DCO TAP Bit : 2 */
-#define DCO3 (0x0800) /* DCO TAP Bit : 3 */
-#define DCO4 (0x1000) /* DCO TAP Bit : 4 */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */
-#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */
-#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */
-#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */
-#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */
-#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */
-#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */
-#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */
-#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL1 Control Bits */
-#define DISMOD (0x0001) /* Disable Modulation */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */
-#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */
-#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL1 Control Bits */
-#define DISMOD_L (0x0001) /* Disable Modulation */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */
-#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */
-#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-
-#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */
-#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */
-#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */
-#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */
-#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */
-#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */
-#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */
-#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */
-
-
-/* UCSCTL2 Control Bits */
-#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */
-#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */
-#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */
-#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */
-#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */
-#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */
-#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */
-#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */
-#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */
-#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */
-#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */
-#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL2 Control Bits */
-#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */
-#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */
-#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */
-#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */
-#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */
-#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */
-#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */
-#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL2 Control Bits */
-#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */
-#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */
-#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */
-#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */
-//#define RESERVED (0x8000) /* RESERVED */
-
-#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */
-#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */
-#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */
-#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */
-#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */
-#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */
-#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */
-#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */
-#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */
-#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */
-#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */
-#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */
-#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */
-#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */
-
-
-/* UCSCTL3 Control Bits */
-#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */
-#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */
-#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */
-//#define RESERVED (0x0008) /* RESERVED */
-#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */
-#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */
-#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL3 Control Bits */
-#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */
-#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */
-#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */
-//#define RESERVED (0x0008) /* RESERVED */
-#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */
-#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */
-#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-
-#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */
-#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */
-#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */
-#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */
-#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */
-#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */
-#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */
-#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */
-#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */
-#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */
-#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */
-#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */
-#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */
-#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */
-#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */
-#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */
-#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */
-#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */
-#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */
-#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */
-#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */
-#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */
-#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */
-#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */
-#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */
-
-/* UCSCTL4 Control Bits */
-#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
-#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
-#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
-//#define RESERVED (0x0008) /* RESERVED */
-#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
-#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
-#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
-#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
-#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL4 Control Bits */
-#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
-#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
-#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
-//#define RESERVED (0x0008) /* RESERVED */
-#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
-#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
-#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL4 Control Bits */
-//#define RESERVED (0x0008) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
-#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
-#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-#define SELM_0 (0x0000) /* MCLK Source Select 0 */
-#define SELM_1 (0x0001) /* MCLK Source Select 1 */
-#define SELM_2 (0x0002) /* MCLK Source Select 2 */
-#define SELM_3 (0x0003) /* MCLK Source Select 3 */
-#define SELM_4 (0x0004) /* MCLK Source Select 4 */
-#define SELM_5 (0x0005) /* MCLK Source Select 5 */
-#define SELM_6 (0x0006) /* MCLK Source Select 6 */
-#define SELM_7 (0x0007) /* MCLK Source Select 7 */
-#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */
-#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
-#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */
-#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
-#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */
-#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */
-
-#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
-#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
-#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
-#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
-#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
-#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
-#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
-#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
-#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */
-#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
-#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */
-#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
-#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */
-#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */
-
-#define SELA_0 (0x0000) /* ACLK Source Select 0 */
-#define SELA_1 (0x0100) /* ACLK Source Select 1 */
-#define SELA_2 (0x0200) /* ACLK Source Select 2 */
-#define SELA_3 (0x0300) /* ACLK Source Select 3 */
-#define SELA_4 (0x0400) /* ACLK Source Select 4 */
-#define SELA_5 (0x0500) /* ACLK Source Select 5 */
-#define SELA_6 (0x0600) /* ACLK Source Select 6 */
-#define SELA_7 (0x0700) /* ACLK Source Select 7 */
-#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */
-#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
-#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */
-#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */
-#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */
-#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */
-
-/* UCSCTL5 Control Bits */
-#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
-#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
-#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
-//#define RESERVED (0x0008) /* RESERVED */
-#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
-#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
-#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
-#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
-#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
-//#define RESERVED (0x0800) /* RESERVED */
-#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */
-#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */
-#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL5 Control Bits */
-#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
-#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
-#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
-//#define RESERVED (0x0008) /* RESERVED */
-#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
-#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
-#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL5 Control Bits */
-//#define RESERVED (0x0008) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
-#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
-#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
-//#define RESERVED (0x0800) /* RESERVED */
-#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */
-#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */
-#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */
-//#define RESERVED (0x8000) /* RESERVED */
-
-#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
-#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
-#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
-#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
-#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
-#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
-#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */
-#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */
-#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
-#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
-#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
-#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
-#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
-#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
-
-#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
-#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
-#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
-#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
-#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
-#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
-#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */
-#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */
-#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
-#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
-#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
-#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
-#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
-#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
-
-#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
-#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
-#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
-#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
-#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
-#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
-#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */
-#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */
-#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
-#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
-#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
-#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
-#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
-#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
-
-#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */
-#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */
-#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */
-#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */
-#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */
-#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */
-#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */
-#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */
-#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */
-#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */
-#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */
-#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */
-#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */
-#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */
-
-
-/* UCSCTL6 Control Bits */
-#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
-#define SMCLKOFF (0x0002) /* SMCLK Off */
-#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */
-#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */
-#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
-#define XTS (0x0020) /* 1: Selects high-freq. oscillator */
-#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */
-#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */
-#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
-//#define RESERVED (0x2000) /* RESERVED */
-#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */
-#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */
-
-/* UCSCTL6 Control Bits */
-#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */
-#define SMCLKOFF_L (0x0002) /* SMCLK Off */
-#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */
-#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */
-#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
-#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */
-#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */
-#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-
-/* UCSCTL6 Control Bits */
-#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
-//#define RESERVED (0x2000) /* RESERVED */
-#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */
-#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */
-
-#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */
-#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */
-#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */
-#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */
-#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */
-#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */
-#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */
-#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */
-#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */
-#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */
-#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */
-#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */
-
-
-/* UCSCTL7 Control Bits */
-#define DCOFFG (0x0001) /* DCO Fault Flag */
-#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
-//#define RESERVED (0x0004) /* RESERVED */
-#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */
-//#define RESERVED (0x0010) /* RESERVED */
-//#define RESERVED (0x0020) /* RESERVED */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL7 Control Bits */
-#define DCOFFG_L (0x0001) /* DCO Fault Flag */
-#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */
-//#define RESERVED (0x0004) /* RESERVED */
-#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */
-//#define RESERVED (0x0010) /* RESERVED */
-//#define RESERVED (0x0020) /* RESERVED */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-
-
-/* UCSCTL8 Control Bits */
-#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
-#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
-#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
-#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */
-//#define RESERVED (0x0010) /* RESERVED */
-//#define RESERVED (0x0020) /* RESERVED */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* UCSCTL8 Control Bits */
-#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
-#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
-#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
-#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */
-//#define RESERVED (0x0010) /* RESERVED */
-//#define RESERVED (0x0020) /* RESERVED */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0100) /* RESERVED */
-//#define RESERVED (0x0200) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-
-/************************************************************
-* USCI A0
-************************************************************/
-
-#define UCA0CTLW0 0x05C0 /* USCI A0 Control Word Register 0 */
-#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
-#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
-#define UCA0BRW 0x05C6 /* USCI A0 Baud Word Rate 0 */
-#define UCA0BRW_L (UCA0BRW)
-#define UCA0BRW_H (UCA0BRW+1)
-#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
-#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
-#define UCA0MCTL 0x05C8 /* USCI A0 Modulation Control */
-#define UCA0STAT 0x05CA /* USCI A0 Status Register */
-#define UCA0RXBUF 0x05CC /* USCI A0 Receive Buffer */
-#define UCA0TXBUF 0x05CE /* USCI A0 Transmit Buffer */
-#define UCA0ABCTL 0x05D0 /* USCI A0 LIN Control */
-#define UCA0IRCTL 0x05D2 /* USCI A0 IrDA Transmit Control */
-#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
-#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
-#define UCA0ICTL 0x05DC /* USCI A0 Interrupt Enable Register */
-#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */
-#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */
-#define UCA0IV 0x05DE /* USCI A0 Interrupt Vector Register */
-
-
-/************************************************************
-* USCI B0
-************************************************************/
-
-#define UCB0CTLW0 0x05E0 /* USCI B0 Control Word Register 0 */
-#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
-#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
-#define UCB0BRW 0x05E6 /* USCI B0 Baud Word Rate 0 */
-#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
-#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
-#define UCB0STAT 0x05EA /* USCI B0 Status Register */
-#define UCB0RXBUF 0x05EC /* USCI B0 Receive Buffer */
-#define UCB0TXBUF 0x05EE /* USCI B0 Transmit Buffer */
-#define UCB0I2COA 0x05F0 /* USCI B0 I2C Own Address */
-#define UCB0I2CSA 0x05F2 /* USCI B0 I2C Slave Address */
-#define UCB0ICTL 0x05FC /* USCI B0 Interrupt Enable Register */
-#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */
-#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */
-#define UCB0IV 0x05FE /* USCI B0 Interrupt Vector Register */
-
-
-// UCAxCTL0 UART-Mode Control Bits
-#define UCPEN (0x80) /* Async. Mode: Parity enable */
-#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
-#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
-#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
-#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
-#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
-#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
-#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
-
-// UCxxCTL0 SPI-Mode Control Bits
-#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
-#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
-#define UCMST (0x08) /* Sync. Mode: Master Select */
-
-// UCBxCTL0 I2C-Mode Control Bits
-#define UCA10 (0x80) /* 10-bit Address Mode */
-#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
-#define UCMM (0x20) /* Multi-Master Environment */
-//#define res (0x10) /* reserved */
-#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
-#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
-#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
-#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
-
-// UCAxCTL1 UART-Mode Control Bits
-#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
-#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
-#define UCRXEIE (0x20) /* RX Error interrupt enable */
-#define UCBRKIE (0x10) /* Break interrupt enable */
-#define UCDORM (0x08) /* Dormant (Sleep) Mode */
-#define UCTXADDR (0x04) /* Send next Data as Address */
-#define UCTXBRK (0x02) /* Send next Data as Break */
-#define UCSWRST (0x01) /* USCI Software Reset */
-
-// UCxxCTL1 SPI-Mode Control Bits
-//#define res (0x20) /* reserved */
-//#define res (0x10) /* reserved */
-//#define res (0x08) /* reserved */
-//#define res (0x04) /* reserved */
-//#define res (0x02) /* reserved */
-
-// UCBxCTL1 I2C-Mode Control Bits
-//#define res (0x20) /* reserved */
-#define UCTR (0x10) /* Transmit/Receive Select/Flag */
-#define UCTXNACK (0x08) /* Transmit NACK */
-#define UCTXSTP (0x04) /* Transmit STOP */
-#define UCTXSTT (0x02) /* Transmit START */
-#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
-#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
-#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
-#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
-#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */
-#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */
-#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */
-
-/* UCAxMCTL Control Bits */
-#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
-#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
-#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
-#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
-#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
-#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
-#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
-#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
-
-#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
-#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
-#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
-#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
-#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
-#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
-#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
-#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
-#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
-#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
-#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
-#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
-#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
-#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
-#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
-#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
-
-#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
-#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
-#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
-#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
-#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
-#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
-#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
-#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
-
-/* UCAxSTAT Control Bits */
-#define UCLISTEN (0x80) /* USCI Listen mode */
-#define UCFE (0x40) /* USCI Frame Error Flag */
-#define UCOE (0x20) /* USCI Overrun Error Flag */
-#define UCPE (0x10) /* USCI Parity Error Flag */
-#define UCBRK (0x08) /* USCI Break received */
-#define UCRXERR (0x04) /* USCI RX Error Flag */
-#define UCADDR (0x02) /* USCI Address received Flag */
-#define UCBUSY (0x01) /* USCI Busy Flag */
-#define UCIDLE (0x02) /* USCI Idle line detected Flag */
-
-
-/* UCBxSTAT Control Bits */
-#define UCSCLLOW (0x40) /* SCL low */
-#define UCGC (0x20) /* General Call address received Flag */
-#define UCBBUSY (0x10) /* Bus Busy Flag */
-
-/* UCAxIRTCTL Control Bits */
-#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
-#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
-#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
-#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
-#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
-#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
-#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
-#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
-
-/* UCAxIRRCTL Control Bits */
-#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
-#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
-#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
-#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
-#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
-#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
-#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
-#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
-
-/* UCAxABCTL Control Bits */
-//#define res (0x80) /* reserved */
-//#define res (0x40) /* reserved */
-#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
-#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
-#define UCSTOE (0x08) /* Sync-Field Timeout error */
-#define UCBTOE (0x04) /* Break Timeout error */
-//#define res (0x02) /* reserved */
-#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
-
-/* UCBxI2COA Control Bits */
-#define UCGCEN (0x8000) /* I2C General Call enable */
-#define UCOA9 (0x0200) /* I2C Own Address 9 */
-#define UCOA8 (0x0100) /* I2C Own Address 8 */
-#define UCOA7 (0x0080) /* I2C Own Address 7 */
-#define UCOA6 (0x0040) /* I2C Own Address 6 */
-#define UCOA5 (0x0020) /* I2C Own Address 5 */
-#define UCOA4 (0x0010) /* I2C Own Address 4 */
-#define UCOA3 (0x0008) /* I2C Own Address 3 */
-#define UCOA2 (0x0004) /* I2C Own Address 2 */
-#define UCOA1 (0x0002) /* I2C Own Address 1 */
-#define UCOA0 (0x0001) /* I2C Own Address 0 */
-
-/* UCBxI2COA Control Bits */
-#define UCOA7_L (0x0080) /* I2C Own Address 7 */
-#define UCOA6_L (0x0040) /* I2C Own Address 6 */
-#define UCOA5_L (0x0020) /* I2C Own Address 5 */
-#define UCOA4_L (0x0010) /* I2C Own Address 4 */
-#define UCOA3_L (0x0008) /* I2C Own Address 3 */
-#define UCOA2_L (0x0004) /* I2C Own Address 2 */
-#define UCOA1_L (0x0002) /* I2C Own Address 1 */
-#define UCOA0_L (0x0001) /* I2C Own Address 0 */
-
-/* UCBxI2COA Control Bits */
-#define UCGCEN_H (0x0080) /* I2C General Call enable */
-#define UCOA9_H (0x0002) /* I2C Own Address 9 */
-#define UCOA8_H (0x0001) /* I2C Own Address 8 */
-
-/* UCBxI2CSA Control Bits */
-#define UCSA9 (0x0200) /* I2C Slave Address 9 */
-#define UCSA8 (0x0100) /* I2C Slave Address 8 */
-#define UCSA7 (0x0080) /* I2C Slave Address 7 */
-#define UCSA6 (0x0040) /* I2C Slave Address 6 */
-#define UCSA5 (0x0020) /* I2C Slave Address 5 */
-#define UCSA4 (0x0010) /* I2C Slave Address 4 */
-#define UCSA3 (0x0008) /* I2C Slave Address 3 */
-#define UCSA2 (0x0004) /* I2C Slave Address 2 */
-#define UCSA1 (0x0002) /* I2C Slave Address 1 */
-#define UCSA0 (0x0001) /* I2C Slave Address 0 */
-
-/* UCBxI2CSA Control Bits */
-#define UCSA7_L (0x0080) /* I2C Slave Address 7 */
-#define UCSA6_L (0x0040) /* I2C Slave Address 6 */
-#define UCSA5_L (0x0020) /* I2C Slave Address 5 */
-#define UCSA4_L (0x0010) /* I2C Slave Address 4 */
-#define UCSA3_L (0x0008) /* I2C Slave Address 3 */
-#define UCSA2_L (0x0004) /* I2C Slave Address 2 */
-#define UCSA1_L (0x0002) /* I2C Slave Address 1 */
-#define UCSA0_L (0x0001) /* I2C Slave Address 0 */
-
-/* UCBxI2CSA Control Bits */
-#define UCSA9_H (0x0002) /* I2C Slave Address 9 */
-#define UCSA8_H (0x0001) /* I2C Slave Address 8 */
-
-/* UCAxIE Control Bits */
-#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */
-#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */
-
-/* UCBxIE Control Bits */
-#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */
-#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */
-#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */
-#define UCSTTIE (0x0004) /* START Condition interrupt enable */
-
-/* UCAxIFG Control Bits */
-#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */
-#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */
-
-/* UCBxIFG Control Bits */
-#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */
-#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */
-#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */
-#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */
-
-/* USCI Definitions */
-#define USCI_NONE (0x0000) /* No Interrupt pending */
-#define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */
-#define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */
-#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
-#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
-#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
-#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
-#define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */
-#define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */
-
-/************************************************************
-* USCI A1
-************************************************************/
-
-#define UCA1CTLW0 0x0600 /* USCI A1 Control Word Register 0 */
-#define UCA1CTLW0_L (UCA1CTLW0)
-#define UCA1CTLW0_H (UCA1CTLW0+1)
-#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */
-#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */
-#define UCA1BRW 0x0606 /* USCI A1 Baud Word Rate 0 */
-#define UCA1BRW_L (UCA1BRW)
-#define UCA1BRW_H (UCA1BRW+1)
-#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */
-#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */
-#define UCA1MCTL 0x0608 /* USCI A1 Modulation Control */
-#define UCA1STAT 0x060A /* USCI A1 Status Register */
-#define UCA1RXBUF 0x060C /* USCI A1 Receive Buffer */
-#define UCA1TXBUF 0x060E /* USCI A1 Transmit Buffer */
-#define UCA1ABCTL 0x0610 /* USCI A1 LIN Control */
-#define UCA1IRCTL 0x0612 /* USCI A1 IrDA Transmit Control */
-#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */
-#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */
-#define UCA1ICTL 0x061C /* USCI A1 Interrupt Enable Register */
-#define UCA1ICTL_L (UCA1ICTL)
-#define UCA1ICTL_H (UCA1ICTL+1)
-
-#define UCA1IE UCA1ICTL_L /* USCI A1 Interrupt Enable Register */
-#define UCA1IFG UCA1ICTL_H /* USCI A1 Interrupt Flags Register */
-#define UCA1IV 0x061E /* USCI A1 Interrupt Vector Register */
-
-
-/************************************************************
-* USCI B1
-************************************************************/
-
-#define UCB1CTLW0 0x0620 /* USCI B1 Control Word Register 0 */
-#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */
-#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */
-#define UCB1BRW 0x0626 /* USCI B1 Baud Word Rate 0 */
-#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */
-#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */
-#define UCB1STAT 0x062A /* USCI B1 Status Register */
-#define UCB1RXBUF 0x062C /* USCI B1 Receive Buffer */
-#define UCB1TXBUF 0x062E /* USCI B1 Transmit Buffer */
-#define UCB1I2COA 0x0630 /* USCI B1 I2C Own Address */
-#define UCB1I2CSA 0x0632 /* USCI B1 I2C Slave Address */
-#define UCB1ICTL 0x063C /* USCI B1 Interrupt Enable Register */
-#define UCB1IE UCB1ICTL_L /* USCI B1 Interrupt Enable Register */
-#define UCB1IFG UCB1ICTL_H /* USCI B1 Interrupt Flags Register */
-#define UCB1IV 0x063E /* USCI B1 Interrupt Vector Register */
-
-/************************************************************
-* WATCHDOG TIMER A
-************************************************************/
-#define WDTCTL 0x015C /* Watchdog Timer Control */
-/* The bit names have been prefixed with "WDT" */
-/* WDTCTL Control Bits */
-#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
-#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
-#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
-#define WDTCNTCL (0x0008) /* WDT - Timer Clear */
-#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
-#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
-#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
-#define WDTHOLD (0x0080) /* WDT - Timer hold */
-
-/* WDTCTL Control Bits */
-#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
-#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
-#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
-#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
-#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
-#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
-#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
-#define WDTHOLD_L (0x0080) /* WDT - Timer hold */
-
-
-#define WDTPW (0x5A00)
-
-#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */
-#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */
-#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */
-#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */
-#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */
-#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */
-#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */
-#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */
-#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */
-#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */
-#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */
-#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */
-#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */
-#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */
-#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */
-#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */
-
-#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
-#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */
-#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
-#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */
-#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
-#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */
-#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
-
-
-/* WDT-interval times [1ms] coded with Bits 0-2 */
-/* WDT is clocked by fSMCLK (assumed 1MHz) */
-#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
-#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
-#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
-#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
-/* WDT is clocked by fACLK (assumed 32KHz) */
-#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
-#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
-#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
-#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
-/* Watchdog mode -> reset after expired time */
-/* WDT is clocked by fSMCLK (assumed 1MHz) */
-#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
-#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
-#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
-#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
-/* WDT is clocked by fACLK (assumed 32KHz) */
-#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
-#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
-#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
-#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
-
-
-/************************************************************
-* TLV Descriptors
-************************************************************/
-
-#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */
-#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */
-#define TLV_START (0x1A08) /* Start Address of the TLV structure */
-#define TLV_END (0x1AFF) /* End Address of the TLV structure */
-
-#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
-#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
-#define TLV_Reserved3 (0x03) /* Future usage */
-#define TLV_Reserved4 (0x04) /* Future usage */
-#define TLV_BLANK (0x05) /* Blank descriptor */
-#define TLV_Reserved6 (0x06) /* Future usage */
-#define TLV_Reserved7 (0x07) /* Serial Number */
-#define TLV_DIERECORD (0x08) /* Die Record */
-#define TLV_ADCCAL (0x11) /* ADC12 calibration */
-#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
-#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
-#define TLV_REFCAL (0x12) /* REF calibration */
-#define TLV_TAGEXT (0xFE) /* Tag extender */
-#define TLV_TAGEND (0xFF) // Tag End of Table
-
-
-/************************************************************
-* Interrupt Vectors (offset from 0xFF80)
-************************************************************/
-
-
-#define RTC_VECTOR (42) /* 0xFFD2 RTC */
-#define PORT2_VECTOR (43) /* 0xFFD4 Port 2 */
-#define TIMER2_A1_VECTOR (44) /* 0xFFD6 Timer2_A5 CC1-4, TA */
-#define TIMER2_A0_VECTOR (45) /* 0xFFD8 Timer2_A5 CC0 */
-#define USCI_B1_VECTOR (46) /* 0xFFDA USCI B1 Receive/Transmit */
-#define USCI_A1_VECTOR (47) /* 0xFFDC USCI A1 Receive/Transmit */
-#define PORT1_VECTOR (48) /* 0xFFDE Port 1 */
-#define TIMER1_A1_VECTOR (49) /* 0xFFE0 Timer1_A3 CC1-2, TA1 */
-#define TIMER1_A0_VECTOR (50) /* 0xFFE2 Timer1_A3 CC0 */
-#define DMA_VECTOR (51) /* 0xFFE4 DMA */
-#define USB_UBM_VECTOR (52) /* 0xFFE6 USB Timer / cable event / USB reset */
-#define TIMER0_A1_VECTOR (53) /* 0xFFE8 Timer0_A5 CC1-4, TA */
-#define TIMER0_A0_VECTOR (54) /* 0xFFEA Timer0_A5 CC0 */
-#define ADC12_VECTOR (55) /* 0xFFEC ADC */
-#define USCI_B0_VECTOR (56) /* 0xFFEE USCI B0 Receive/Transmit */
-#define USCI_A0_VECTOR (57) /* 0xFFF0 USCI A0 Receive/Transmit */
-#define WDT_VECTOR (58) /* 0xFFF2 Watchdog Timer */
-#define TIMER0_B1_VECTOR (59) /* 0xFFF4 Timer0_B7 CC1-6, TB */
-#define TIMER0_B0_VECTOR (60) /* 0xFFF6 Timer0_B7 CC0 */
-#define COMP_B_VECTOR (61) /* 0xFFF8 Comparator B */
-#define UNMI_VECTOR (62) /* 0xFFFA User Non-maskable */
-#define SYSNMI_VECTOR (63) /* 0xFFFC System Non-maskable */
-#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */
-
-/************************************************************
-* End of Modules
-************************************************************/
-
diff --git a/amforth-6.5/msp430/devices/msp430f5529/words/cold.asm b/amforth-6.5/msp430/devices/msp430f5529/words/cold.asm
deleted file mode 100644
index b16f18f..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/words/cold.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-CODEHEADER(XT_COLD, 4, "cold")
-; ----------------------------------------------------------------------
-
-main: ; Debugger requires the 'main' symbol.
-reset:
-
- mov #5A80h, &WDTCTL ; Watchdog off
-
- ; Now it is time to initialize hardware. (Porting: Change this !)
-
- ;------------------------------------------------------------------------------
- ; Init Clock
-
- bis.w #40h, r2
- mov.w #20h, &166h
- mov.w #144h, &168h
- mov.w #1308h, &160h
- mov.w #40h, &162h
- mov.w #0F4h, &164h
- nop
- nop
- nop
- bic.w #40h, r2
-
-reset_loop:
- mov.w #0h, &16Eh
- bic.w #2h, &102h
- bit.w #2h, &102h
- jc reset_loop
-
- ;------------------------------------------------------------------------------
-
-; Forth registers
- MOV #RSTACK,SP ; set up stack
- MOV #PSTACK,PSP
- MOV #UAREA,UP ; initial user pointer
- CLR R15
-
-; now hand over to Forth with WARM (a colon word)
- MOV #XT_WARM+2,IP
- NEXT
diff --git a/amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm b/amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm
deleted file mode 100644
index 621fc72..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-ENVIRONMENT(XT_ENV_MCU_INFO,8,"mcu-info")
- .DW XT_DOLITERAL
- .dw mcuinfo
- .DW XT_EXIT
-mcuinfo:
- ; first fixed sized elements
- .dw RAMEND-RAMSTART ; RAM Size
- .dw 0 ; EEPROM Size
- .dw AMFORTH_START-1 ; max-dp
- .dw 1 ; number of interrupts
diff --git a/amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm b/amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm
deleted file mode 100644
index 4bcd00c..0000000
--- a/amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm
+++ /dev/null
@@ -1,16 +0,0 @@
- CODEHEADER(XT_USART,6,"+usart")
- ; USCI_A0
- mov.b #030h, &P4SEL ; Use P4.4/P4.5 for USCI_A1 TXD/RXD
-
- ;------------------------------------------------------------------------------
- ; Init serial communication
-
- mov.b #UCSWRST, &UCA1CTL1 ; **Put state machine in reset**
- bis.b #UCSSEL_2, &UCA1CTL1 ; SMCLK
-
- mov.w #4, &UCA1BRW ; 8 MHz 115200 Baud
- mov.b #3Bh, &UCA1MCTL ; Modulation UCBRSx=5, UCBRFx=3, UCOS16
-
- bic.b #UCSWRST, &UCA1CTL1 ; **Initialize USCI state machine**
-
- NEXT
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/device.asm b/amforth-6.5/msp430/devices/msp430fr5969/device.asm
deleted file mode 100644
index 45c9b5e..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/device.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; device specific
-.include "msp430fr5969.inc" ; MCU-specific register equates
-
-RAMSTART equ 1C00h
-RAMEND equ 2400h
-INFOSTART equ 01800h ; INFO D Area
-INFOEND equ 0197fh ; do not allow config flash to be erased
-FLASHSTART equ 4400h
-FLASHEND equ 0FFFFh
-MAINSEG equ 512
-INFOSEG equ 64
-INFO_SIZE equ 128 ; bytes
-
-.org 0FFFEh
-
- DC16 reset ; FFFE - Reset
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/drivers.asm b/amforth-6.5/msp430/devices/msp430fr5969/drivers.asm
deleted file mode 100644
index fbdf81a..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/drivers.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-
-.include "drivers/fram.inc"
-
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/init.asm b/amforth-6.5/msp430/devices/msp430fr5969/init.asm
deleted file mode 100644
index 32451c5..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/init.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-
-mcu_name:
- .db 12,"MSP430FR5969"
- .align 16
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc b/amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc
deleted file mode 100644
index 116f915..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc
+++ /dev/null
@@ -1,3908 +0,0 @@
-/* ============================================================================ */
-/* Copyright (c) 2015, Texas Instruments Incorporated */
-/* All rights reserved. */
-/* */
-/* Redistribution and use in source and binary forms, with or without */
-/* modification, are permitted provided that the following conditions */
-/* are met: */
-/* */
-/* * Redistributions of source code must retain the above copyright */
-/* notice, this list of conditions and the following disclaimer. */
-/* */
-/* * Redistributions in binary form must reproduce the above copyright */
-/* notice, this list of conditions and the following disclaimer in the */
-/* documentation and/or other materials provided with the distribution. */
-/* */
-/* * Neither the name of Texas Instruments Incorporated nor the names of */
-/* its contributors may be used to endorse or promote products derived */
-/* from this software without specific prior written permission. */
-/* */
-/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
-/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
-/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
-/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
-/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
-/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
-/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
-/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
-/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
-/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ============================================================================ */
-
-/********************************************************************
-*
-* Standard register and bit definitions for the Texas Instruments
-* MSP430 microcontroller.
-*
-* This file supports assembler and C development for
-* MSP430FR5969 devices.
-*
-* Texas Instruments, Version 1.4
-*
-* Rev. 1.0, Setup
-* Rev. 1.1 updated PxSELC register address to offset 0x16 (instead of 0x10)
-* replaced Comperator B with Comperator E
-* Rev. 1.2 fixed typo in SYSRSTIV_MPUSEG defintions
-* replaced COMP_B with COMP_E
-* Rev. 1.3 removed not available PxDS Register definitions
-* Rev. 1.4 replaced NACCESSx with NWAITSx
-*
-********************************************************************/
-
-/************************************************************
-* STANDARD BITS
-************************************************************/
-
-#define BIT0 (0x0001)
-#define BIT1 (0x0002)
-#define BIT2 (0x0004)
-#define BIT3 (0x0008)
-#define BIT4 (0x0010)
-#define BIT5 (0x0020)
-#define BIT6 (0x0040)
-#define BIT7 (0x0080)
-#define BIT8 (0x0100)
-#define BIT9 (0x0200)
-#define BITA (0x0400)
-#define BITB (0x0800)
-#define BITC (0x1000)
-#define BITD (0x2000)
-#define BITE (0x4000)
-#define BITF (0x8000)
-
-/************************************************************
-* STATUS REGISTER BITS
-************************************************************/
-
-#define C (0x0001)
-#define Z (0x0002)
-#define N (0x0004)
-#define V (0x0100)
-#define GIE (0x0008)
-#define CPUOFF (0x0010)
-#define OSCOFF (0x0020)
-#define SCG0 (0x0040)
-#define SCG1 (0x0080)
-
-/* Low Power Modes coded with Bits 4-7 in SR */
-
-#ifndef __STDC_ /* Begin #defines for assembler */
-#define LPM0 (CPUOFF)
-#define LPM1 (SCG0+CPUOFF)
-#define LPM2 (SCG1+CPUOFF)
-#define LPM3 (SCG1+SCG0+CPUOFF)
-#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
-/* End #defines for assembler */
-
-#else /* Begin #defines for C */
-#define LPM0_bits (CPUOFF)
-#define LPM1_bits (SCG0+CPUOFF)
-#define LPM2_bits (SCG1+CPUOFF)
-#define LPM3_bits (SCG1+SCG0+CPUOFF)
-#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
-
-#include "in430.h"
-
-#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
-#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
-#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
-#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
-#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
-#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
-#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
-#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
-#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
-#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
-#endif /* End #defines for C */
-
-/************************************************************
-* CPU
-************************************************************/
-
-/************************************************************
-* PERIPHERAL FILE MAP
-************************************************************/
-
-
-/************************************************************
-* ADC12_B
-************************************************************/
-
-#define ADC12CTL0 0x0800 /* ADC12 B Control 0 */
-#define ADC12CTL1 0x0802 /* ADC12 B Control 1 */
-#define ADC12CTL2 0x0804 /* ADC12 B Control 2 */
-#define ADC12CTL3 0x0806 /* ADC12 B Control 3 */
-#define ADC12LO 0x0808 /* ADC12 B Window Comparator High Threshold */
-#define ADC12HI 0x080A /* ADC12 B Window Comparator High Threshold */
-#define ADC12IFGR0 0x080C /* ADC12 B Interrupt Flag 0 */
-#define ADC12IFGR1 0x080E /* ADC12 B Interrupt Flag 1 */
-#define ADC12IFGR2 0x0810 /* ADC12 B Interrupt Flag 2 */
-#define ADC12IER0 0x0812 /* ADC12 B Interrupt Enable 0 */
-#define ADC12IER1 0x0814 /* ADC12 B Interrupt Enable 1 */
-#define ADC12IER2 0x0816 /* ADC12 B Interrupt Enable 2 */
-#define ADC12IV 0x0818 /* ADC12 B Interrupt Vector Word */
-
-#define ADC12MCTL0 0x0820 /* ADC12 Memory Control 0 */
-#define ADC12MCTL1 0x0822 /* ADC12 Memory Control 1 */
-#define ADC12MCTL2 0x0824 /* ADC12 Memory Control 2 */
-#define ADC12MCTL3 0x0826 /* ADC12 Memory Control 3 */
-#define ADC12MCTL4 0x0828 /* ADC12 Memory Control 4 */
-#define ADC12MCTL5 0x082A /* ADC12 Memory Control 5 */
-#define ADC12MCTL6 0x082C /* ADC12 Memory Control 6 */
-#define ADC12MCTL7 0x082E /* ADC12 Memory Control 7 */
-#define ADC12MCTL8 0x0830 /* ADC12 Memory Control 8 */
-#define ADC12MCTL9 0x0832 /* ADC12 Memory Control 9 */
-#define ADC12MCTL10 0x0834 /* ADC12 Memory Control 10 */
-#define ADC12MCTL11 0x0836 /* ADC12 Memory Control 11 */
-#define ADC12MCTL12 0x0838 /* ADC12 Memory Control 12 */
-#define ADC12MCTL13 0x083A /* ADC12 Memory Control 13 */
-#define ADC12MCTL14 0x083C /* ADC12 Memory Control 14 */
-#define ADC12MCTL15 0x083E /* ADC12 Memory Control 15 */
-#define ADC12MCTL16 0x0840 /* ADC12 Memory Control 16 */
-#define ADC12MCTL17 0x0842 /* ADC12 Memory Control 17 */
-#define ADC12MCTL18 0x0844 /* ADC12 Memory Control 18 */
-#define ADC12MCTL19 0x0846 /* ADC12 Memory Control 19 */
-#define ADC12MCTL20 0x0848 /* ADC12 Memory Control 20 */
-#define ADC12MCTL21 0x084A /* ADC12 Memory Control 21 */
-#define ADC12MCTL22 0x084C /* ADC12 Memory Control 22 */
-#define ADC12MCTL23 0x084E /* ADC12 Memory Control 23 */
-#define ADC12MCTL24 0x0850 /* ADC12 Memory Control 24 */
-#define ADC12MCTL25 0x0852 /* ADC12 Memory Control 25 */
-#define ADC12MCTL26 0x0854 /* ADC12 Memory Control 26 */
-#define ADC12MCTL27 0x0856 /* ADC12 Memory Control 27 */
-#define ADC12MCTL28 0x0858 /* ADC12 Memory Control 28 */
-#define ADC12MCTL29 0x085A /* ADC12 Memory Control 29 */
-#define ADC12MCTL30 0x085C /* ADC12 Memory Control 30 */
-#define ADC12MCTL31 0x085E /* ADC12 Memory Control 31 */
-#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
-
-
-#define ADC12MEM0 0x0860 /* ADC12 Conversion Memory 0 */
-#define ADC12MEM1 0x0862 /* ADC12 Conversion Memory 1 */
-#define ADC12MEM2 0x0864 /* ADC12 Conversion Memory 2 */
-#define ADC12MEM3 0x0866 /* ADC12 Conversion Memory 3 */
-#define ADC12MEM4 0x0868 /* ADC12 Conversion Memory 4 */
-#define ADC12MEM5 0x086A /* ADC12 Conversion Memory 5 */
-#define ADC12MEM6 0x086C /* ADC12 Conversion Memory 6 */
-#define ADC12MEM7 0x086E /* ADC12 Conversion Memory 7 */
-#define ADC12MEM8 0x0870 /* ADC12 Conversion Memory 8 */
-#define ADC12MEM9 0x0872 /* ADC12 Conversion Memory 9 */
-#define ADC12MEM10 0x0874 /* ADC12 Conversion Memory 10 */
-#define ADC12MEM11 0x0876 /* ADC12 Conversion Memory 11 */
-#define ADC12MEM12 0x0878 /* ADC12 Conversion Memory 12 */
-#define ADC12MEM13 0x087A /* ADC12 Conversion Memory 13 */
-#define ADC12MEM14 0x087C /* ADC12 Conversion Memory 14 */
-#define ADC12MEM15 0x087E /* ADC12 Conversion Memory 15 */
-#define ADC12MEM16 0x0880 /* ADC12 Conversion Memory 16 */
-#define ADC12MEM17 0x0882 /* ADC12 Conversion Memory 17 */
-#define ADC12MEM18 0x0884 /* ADC12 Conversion Memory 18 */
-#define ADC12MEM19 0x0886 /* ADC12 Conversion Memory 19 */
-#define ADC12MEM20 0x0888 /* ADC12 Conversion Memory 20 */
-#define ADC12MEM21 0x088A /* ADC12 Conversion Memory 21 */
-#define ADC12MEM22 0x088C /* ADC12 Conversion Memory 22 */
-#define ADC12MEM23 0x088E /* ADC12 Conversion Memory 23 */
-#define ADC12MEM24 0x0890 /* ADC12 Conversion Memory 24 */
-#define ADC12MEM25 0x0892 /* ADC12 Conversion Memory 25 */
-#define ADC12MEM26 0x0894 /* ADC12 Conversion Memory 26 */
-#define ADC12MEM27 0x0896 /* ADC12 Conversion Memory 27 */
-#define ADC12MEM28 0x0898 /* ADC12 Conversion Memory 28 */
-#define ADC12MEM29 0x089A /* ADC12 Conversion Memory 29 */
-#define ADC12MEM30 0x089C /* ADC12 Conversion Memory 30 */
-#define ADC12MEM31 0x089E /* ADC12 Conversion Memory 31 */
-#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
-
-/* ADC12CTL0 Control Bits */
-#define ADC12SC (0x0001) /* ADC12 Start Conversion */
-#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */
-#define ADC12ON (0x0010) /* ADC12 On/enable */
-#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */
-#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */
-#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */
-#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */
-#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */
-#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */
-#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */
-#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */
-#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */
-
-/* ADC12CTL0 Control Bits */
-#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
-#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
-#define ADC12ON_L (0x0010) /* ADC12 On/enable */
-#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
-
-/* ADC12CTL0 Control Bits */
-#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */
-#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */
-#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */
-#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */
-#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */
-#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */
-#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */
-#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */
-
-#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */
-#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */
-#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */
-#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */
-#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */
-#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */
-#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */
-#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */
-#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */
-#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */
-#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */
-#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */
-#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */
-#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */
-#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */
-#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */
-
-#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */
-#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */
-#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */
-#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */
-#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */
-#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */
-#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */
-#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */
-#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */
-#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */
-#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */
-#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */
-#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */
-#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */
-#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */
-#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */
-
-/* ADC12CTL1 Control Bits */
-#define ADC12BUSY (0x0001) /* ADC12 Busy */
-#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
-#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
-#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */
-#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */
-#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
-#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
-#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
-#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
-#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
-#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */
-#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */
-#define ADC12SHS2 (0x1000) /* ADC12 Sample/Hold Source Bit: 2 */
-#define ADC12PDIV0 (0x2000) /* ADC12 Predivider Bit: 0 */
-#define ADC12PDIV1 (0x4000) /* ADC12 Predivider Bit: 1 */
-
-/* ADC12CTL1 Control Bits */
-#define ADC12BUSY_L (0x0001) /* ADC12 Busy */
-#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
-#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
-#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */
-#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */
-#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
-#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
-#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
-
-/* ADC12CTL1 Control Bits */
-#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
-#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
-#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */
-#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */
-#define ADC12SHS2_H (0x0010) /* ADC12 Sample/Hold Source Bit: 2 */
-#define ADC12PDIV0_H (0x0020) /* ADC12 Predivider Bit: 0 */
-#define ADC12PDIV1_H (0x0040) /* ADC12 Predivider Bit: 1 */
-
-#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */
-#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */
-#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */
-#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */
-
-#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */
-#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */
-#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */
-#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */
-
-#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */
-#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */
-#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */
-#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */
-#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */
-#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */
-#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */
-#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */
-
-#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */
-#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */
-#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */
-#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */
-#define ADC12SHS_4 (0x1000) /* ADC12 Sample/Hold Source: 4 */
-#define ADC12SHS_5 (0x1400) /* ADC12 Sample/Hold Source: 5 */
-#define ADC12SHS_6 (0x1800) /* ADC12 Sample/Hold Source: 6 */
-#define ADC12SHS_7 (0x1C00) /* ADC12 Sample/Hold Source: 7 */
-
-#define ADC12PDIV_0 (0x0000) /* ADC12 Clock predivider Select 0 */
-#define ADC12PDIV_1 (0x2000) /* ADC12 Clock predivider Select 1 */
-#define ADC12PDIV_2 (0x4000) /* ADC12 Clock predivider Select 2 */
-#define ADC12PDIV_3 (0x6000) /* ADC12 Clock predivider Select 3 */
-#define ADC12PDIV__1 (0x0000) /* ADC12 Clock predivider Select: /1 */
-#define ADC12PDIV__4 (0x2000) /* ADC12 Clock predivider Select: /4 */
-#define ADC12PDIV__32 (0x4000) /* ADC12 Clock predivider Select: /32 */
-#define ADC12PDIV__64 (0x6000) /* ADC12 Clock predivider Select: /64 */
-
-/* ADC12CTL2 Control Bits */
-#define ADC12PWRMD (0x0001) /* ADC12 Power Mode */
-#define ADC12DF (0x0008) /* ADC12 Data Format */
-#define ADC12RES0 (0x0010) /* ADC12 Resolution Bit: 0 */
-#define ADC12RES1 (0x0020) /* ADC12 Resolution Bit: 1 */
-
-/* ADC12CTL2 Control Bits */
-#define ADC12PWRMD_L (0x0001) /* ADC12 Power Mode */
-#define ADC12DF_L (0x0008) /* ADC12 Data Format */
-#define ADC12RES0_L (0x0010) /* ADC12 Resolution Bit: 0 */
-#define ADC12RES1_L (0x0020) /* ADC12 Resolution Bit: 1 */
-
-
-#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
-#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
-#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
-#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
-
-#define ADC12RES__8BIT (0x0000) /* ADC12+ Resolution : 8 Bit */
-#define ADC12RES__10BIT (0x0010) /* ADC12+ Resolution : 10 Bit */
-#define ADC12RES__12BIT (0x0020) /* ADC12+ Resolution : 12 Bit */
-
-/* ADC12CTL3 Control Bits */
-#define ADC12CSTARTADD0 (0x0001) /* ADC12 Conversion Start Address Bit: 0 */
-#define ADC12CSTARTADD1 (0x0002) /* ADC12 Conversion Start Address Bit: 1 */
-#define ADC12CSTARTADD2 (0x0004) /* ADC12 Conversion Start Address Bit: 2 */
-#define ADC12CSTARTADD3 (0x0008) /* ADC12 Conversion Start Address Bit: 3 */
-#define ADC12CSTARTADD4 (0x0010) /* ADC12 Conversion Start Address Bit: 4 */
-#define ADC12BATMAP (0x0040) /* ADC12 Internal AVCC/2 select */
-#define ADC12TCMAP (0x0080) /* ADC12 Internal TempSensor select */
-#define ADC12ICH0MAP (0x0100) /* ADC12 Internal Channel 0 select */
-#define ADC12ICH1MAP (0x0200) /* ADC12 Internal Channel 1 select */
-#define ADC12ICH2MAP (0x0400) /* ADC12 Internal Channel 2 select */
-#define ADC12ICH3MAP (0x0800) /* ADC12 Internal Channel 3 select */
-
-/* ADC12CTL3 Control Bits */
-#define ADC12CSTARTADD0_L (0x0001) /* ADC12 Conversion Start Address Bit: 0 */
-#define ADC12CSTARTADD1_L (0x0002) /* ADC12 Conversion Start Address Bit: 1 */
-#define ADC12CSTARTADD2_L (0x0004) /* ADC12 Conversion Start Address Bit: 2 */
-#define ADC12CSTARTADD3_L (0x0008) /* ADC12 Conversion Start Address Bit: 3 */
-#define ADC12CSTARTADD4_L (0x0010) /* ADC12 Conversion Start Address Bit: 4 */
-#define ADC12BATMAP_L (0x0040) /* ADC12 Internal AVCC/2 select */
-#define ADC12TCMAP_L (0x0080) /* ADC12 Internal TempSensor select */
-
-/* ADC12CTL3 Control Bits */
-#define ADC12ICH0MAP_H (0x0001) /* ADC12 Internal Channel 0 select */
-#define ADC12ICH1MAP_H (0x0002) /* ADC12 Internal Channel 1 select */
-#define ADC12ICH2MAP_H (0x0004) /* ADC12 Internal Channel 2 select */
-#define ADC12ICH3MAP_H (0x0008) /* ADC12 Internal Channel 3 select */
-
-#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */
-#define ADC12CSTARTADD_1 (0x0001) /* ADC12 Conversion Start Address: 1 */
-#define ADC12CSTARTADD_2 (0x0002) /* ADC12 Conversion Start Address: 2 */
-#define ADC12CSTARTADD_3 (0x0003) /* ADC12 Conversion Start Address: 3 */
-#define ADC12CSTARTADD_4 (0x0004) /* ADC12 Conversion Start Address: 4 */
-#define ADC12CSTARTADD_5 (0x0005) /* ADC12 Conversion Start Address: 5 */
-#define ADC12CSTARTADD_6 (0x0006) /* ADC12 Conversion Start Address: 6 */
-#define ADC12CSTARTADD_7 (0x0007) /* ADC12 Conversion Start Address: 7 */
-#define ADC12CSTARTADD_8 (0x0008) /* ADC12 Conversion Start Address: 8 */
-#define ADC12CSTARTADD_9 (0x0009) /* ADC12 Conversion Start Address: 9 */
-#define ADC12CSTARTADD_10 (0x000A) /* ADC12 Conversion Start Address: 10 */
-#define ADC12CSTARTADD_11 (0x000B) /* ADC12 Conversion Start Address: 11 */
-#define ADC12CSTARTADD_12 (0x000C) /* ADC12 Conversion Start Address: 12 */
-#define ADC12CSTARTADD_13 (0x000D) /* ADC12 Conversion Start Address: 13 */
-#define ADC12CSTARTADD_14 (0x000E) /* ADC12 Conversion Start Address: 14 */
-#define ADC12CSTARTADD_15 (0x000F) /* ADC12 Conversion Start Address: 15 */
-#define ADC12CSTARTADD_16 (0x0010) /* ADC12 Conversion Start Address: 16 */
-#define ADC12CSTARTADD_17 (0x0011) /* ADC12 Conversion Start Address: 17 */
-#define ADC12CSTARTADD_18 (0x0012) /* ADC12 Conversion Start Address: 18 */
-#define ADC12CSTARTADD_19 (0x0013) /* ADC12 Conversion Start Address: 19 */
-#define ADC12CSTARTADD_20 (0x0014) /* ADC12 Conversion Start Address: 20 */
-#define ADC12CSTARTADD_21 (0x0015) /* ADC12 Conversion Start Address: 21 */
-#define ADC12CSTARTADD_22 (0x0016) /* ADC12 Conversion Start Address: 22 */
-#define ADC12CSTARTADD_23 (0x0017) /* ADC12 Conversion Start Address: 23 */
-#define ADC12CSTARTADD_24 (0x0018) /* ADC12 Conversion Start Address: 24 */
-#define ADC12CSTARTADD_25 (0x0019) /* ADC12 Conversion Start Address: 25 */
-#define ADC12CSTARTADD_26 (0x001A) /* ADC12 Conversion Start Address: 26 */
-#define ADC12CSTARTADD_27 (0x001B) /* ADC12 Conversion Start Address: 27 */
-#define ADC12CSTARTADD_28 (0x001C) /* ADC12 Conversion Start Address: 28 */
-#define ADC12CSTARTADD_29 (0x001D) /* ADC12 Conversion Start Address: 29 */
-#define ADC12CSTARTADD_30 (0x001E) /* ADC12 Conversion Start Address: 30 */
-#define ADC12CSTARTADD_31 (0x001F) /* ADC12 Conversion Start Address: 31 */
-
-/* ADC12MCTLx Control Bits */
-#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
-#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
-#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
-#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
-#define ADC12INCH4 (0x0010) /* ADC12 Input Channel Select Bit 4 */
-#define ADC12EOS (0x0080) /* ADC12 End of Sequence */
-#define ADC12VRSEL0 (0x0100) /* ADC12 VR Select Bit 0 */
-#define ADC12VRSEL1 (0x0200) /* ADC12 VR Select Bit 1 */
-#define ADC12VRSEL2 (0x0400) /* ADC12 VR Select Bit 2 */
-#define ADC12VRSEL3 (0x0800) /* ADC12 VR Select Bit 3 */
-#define ADC12DIF (0x2000) /* ADC12 Differential mode (only for even Registers) */
-#define ADC12WINC (0x4000) /* ADC12 Comparator window enable */
-
-/* ADC12MCTLx Control Bits */
-#define ADC12INCH0_L (0x0001) /* ADC12 Input Channel Select Bit 0 */
-#define ADC12INCH1_L (0x0002) /* ADC12 Input Channel Select Bit 1 */
-#define ADC12INCH2_L (0x0004) /* ADC12 Input Channel Select Bit 2 */
-#define ADC12INCH3_L (0x0008) /* ADC12 Input Channel Select Bit 3 */
-#define ADC12INCH4_L (0x0010) /* ADC12 Input Channel Select Bit 4 */
-#define ADC12EOS_L (0x0080) /* ADC12 End of Sequence */
-
-/* ADC12MCTLx Control Bits */
-#define ADC12VRSEL0_H (0x0001) /* ADC12 VR Select Bit 0 */
-#define ADC12VRSEL1_H (0x0002) /* ADC12 VR Select Bit 1 */
-#define ADC12VRSEL2_H (0x0004) /* ADC12 VR Select Bit 2 */
-#define ADC12VRSEL3_H (0x0008) /* ADC12 VR Select Bit 3 */
-#define ADC12DIF_H (0x0020) /* ADC12 Differential mode (only for even Registers) */
-#define ADC12WINC_H (0x0040) /* ADC12 Comparator window enable */
-
-
-
-
-#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */
-#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */
-#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */
-#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */
-#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */
-#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */
-#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */
-#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */
-#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */
-#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */
-#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */
-#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */
-#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */
-#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */
-#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */
-#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */
-#define ADC12INCH_16 (0x0010) /* ADC12 Input Channel 16 */
-#define ADC12INCH_17 (0x0011) /* ADC12 Input Channel 17 */
-#define ADC12INCH_18 (0x0012) /* ADC12 Input Channel 18 */
-#define ADC12INCH_19 (0x0013) /* ADC12 Input Channel 19 */
-#define ADC12INCH_20 (0x0014) /* ADC12 Input Channel 20 */
-#define ADC12INCH_21 (0x0015) /* ADC12 Input Channel 21 */
-#define ADC12INCH_22 (0x0016) /* ADC12 Input Channel 22 */
-#define ADC12INCH_23 (0x0017) /* ADC12 Input Channel 23 */
-#define ADC12INCH_24 (0x0018) /* ADC12 Input Channel 24 */
-#define ADC12INCH_25 (0x0019) /* ADC12 Input Channel 25 */
-#define ADC12INCH_26 (0x001A) /* ADC12 Input Channel 26 */
-#define ADC12INCH_27 (0x001B) /* ADC12 Input Channel 27 */
-#define ADC12INCH_28 (0x001C) /* ADC12 Input Channel 28 */
-#define ADC12INCH_29 (0x001D) /* ADC12 Input Channel 29 */
-#define ADC12INCH_30 (0x001E) /* ADC12 Input Channel 30 */
-#define ADC12INCH_31 (0x001F) /* ADC12 Input Channel 31 */
-
-#define ADC12VRSEL_0 (0x0000) /* ADC12 Select Reference 0 */
-#define ADC12VRSEL_1 (0x0100) /* ADC12 Select Reference 1 */
-#define ADC12VRSEL_2 (0x0200) /* ADC12 Select Reference 2 */
-#define ADC12VRSEL_3 (0x0300) /* ADC12 Select Reference 3 */
-#define ADC12VRSEL_4 (0x0400) /* ADC12 Select Reference 4 */
-#define ADC12VRSEL_5 (0x0500) /* ADC12 Select Reference 5 */
-#define ADC12VRSEL_6 (0x0600) /* ADC12 Select Reference 6 */
-#define ADC12VRSEL_7 (0x0700) /* ADC12 Select Reference 7 */
-#define ADC12VRSEL_8 (0x0800) /* ADC12 Select Reference 8 */
-#define ADC12VRSEL_9 (0x0900) /* ADC12 Select Reference 9 */
-#define ADC12VRSEL_10 (0x0A00) /* ADC12 Select Reference 10 */
-#define ADC12VRSEL_11 (0x0B00) /* ADC12 Select Reference 11 */
-#define ADC12VRSEL_12 (0x0C00) /* ADC12 Select Reference 12 */
-#define ADC12VRSEL_13 (0x0D00) /* ADC12 Select Reference 13 */
-#define ADC12VRSEL_14 (0x0E00) /* ADC12 Select Reference 14 */
-#define ADC12VRSEL_15 (0x0F00) /* ADC12 Select Reference 15 */
-
-/* ADC12HI Control Bits */
-
-
-/* ADC12LO Control Bits */
-
-
-
-/* ADC12IER0 Control Bits */
-#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */
-#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */
-#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */
-#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */
-#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */
-#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */
-#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */
-#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */
-#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */
-#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */
-#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */
-#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */
-#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */
-#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */
-#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */
-#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */
-
-/* ADC12IER0 Control Bits */
-#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */
-#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */
-#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */
-#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */
-#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */
-#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */
-#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */
-#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */
-
-/* ADC12IER0 Control Bits */
-#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */
-#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */
-#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */
-#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */
-#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */
-#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */
-#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */
-#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */
-
-/* ADC12IER1 Control Bits */
-#define ADC12IE16 (0x0001) /* ADC12 Memory 16 Interrupt Enable */
-#define ADC12IE17 (0x0002) /* ADC12 Memory 17 Interrupt Enable */
-#define ADC12IE18 (0x0004) /* ADC12 Memory 18 Interrupt Enable */
-#define ADC12IE19 (0x0008) /* ADC12 Memory 19 Interrupt Enable */
-#define ADC12IE20 (0x0010) /* ADC12 Memory 20 Interrupt Enable */
-#define ADC12IE21 (0x0020) /* ADC12 Memory 21 Interrupt Enable */
-#define ADC12IE22 (0x0040) /* ADC12 Memory 22 Interrupt Enable */
-#define ADC12IE23 (0x0080) /* ADC12 Memory 23 Interrupt Enable */
-#define ADC12IE24 (0x0100) /* ADC12 Memory 24 Interrupt Enable */
-#define ADC12IE25 (0x0200) /* ADC12 Memory 25 Interrupt Enable */
-#define ADC12IE26 (0x0400) /* ADC12 Memory 26 Interrupt Enable */
-#define ADC12IE27 (0x0800) /* ADC12 Memory 27 Interrupt Enable */
-#define ADC12IE28 (0x1000) /* ADC12 Memory 28 Interrupt Enable */
-#define ADC12IE29 (0x2000) /* ADC12 Memory 29 Interrupt Enable */
-#define ADC12IE30 (0x4000) /* ADC12 Memory 30 Interrupt Enable */
-#define ADC12IE31 (0x8000) /* ADC12 Memory 31 Interrupt Enable */
-
-/* ADC12IER1 Control Bits */
-#define ADC12IE16_L (0x0001) /* ADC12 Memory 16 Interrupt Enable */
-#define ADC12IE17_L (0x0002) /* ADC12 Memory 17 Interrupt Enable */
-#define ADC12IE18_L (0x0004) /* ADC12 Memory 18 Interrupt Enable */
-#define ADC12IE19_L (0x0008) /* ADC12 Memory 19 Interrupt Enable */
-#define ADC12IE20_L (0x0010) /* ADC12 Memory 20 Interrupt Enable */
-#define ADC12IE21_L (0x0020) /* ADC12 Memory 21 Interrupt Enable */
-#define ADC12IE22_L (0x0040) /* ADC12 Memory 22 Interrupt Enable */
-#define ADC12IE23_L (0x0080) /* ADC12 Memory 23 Interrupt Enable */
-
-/* ADC12IER1 Control Bits */
-#define ADC12IE24_H (0x0001) /* ADC12 Memory 24 Interrupt Enable */
-#define ADC12IE25_H (0x0002) /* ADC12 Memory 25 Interrupt Enable */
-#define ADC12IE26_H (0x0004) /* ADC12 Memory 26 Interrupt Enable */
-#define ADC12IE27_H (0x0008) /* ADC12 Memory 27 Interrupt Enable */
-#define ADC12IE28_H (0x0010) /* ADC12 Memory 28 Interrupt Enable */
-#define ADC12IE29_H (0x0020) /* ADC12 Memory 29 Interrupt Enable */
-#define ADC12IE30_H (0x0040) /* ADC12 Memory 30 Interrupt Enable */
-#define ADC12IE31_H (0x0080) /* ADC12 Memory 31 Interrupt Enable */
-
-/* ADC12IER2 Control Bits */
-#define ADC12INIE (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
-#define ADC12LOIE (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
-#define ADC12HIIE (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
-#define ADC12OVIE (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */
-#define ADC12TOVIE (0x0020) /* ADC12 Timer Overflow interrupt enable */
-#define ADC12RDYIE (0x0040) /* ADC12 local buffered reference ready interrupt enable */
-
-/* ADC12IER2 Control Bits */
-#define ADC12INIE_L (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
-#define ADC12LOIE_L (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
-#define ADC12HIIE_L (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
-#define ADC12OVIE_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */
-#define ADC12TOVIE_L (0x0020) /* ADC12 Timer Overflow interrupt enable */
-#define ADC12RDYIE_L (0x0040) /* ADC12 local buffered reference ready interrupt enable */
-
-
-/* ADC12IFGR0 Control Bits */
-#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */
-#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */
-#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */
-#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */
-#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */
-#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */
-#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */
-#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */
-#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */
-#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */
-#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */
-#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */
-#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */
-#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */
-#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */
-#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */
-
-/* ADC12IFGR0 Control Bits */
-#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */
-#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */
-#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */
-#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */
-#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */
-#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */
-#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */
-#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */
-
-/* ADC12IFGR0 Control Bits */
-#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */
-#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */
-#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */
-#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */
-#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */
-#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */
-#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */
-#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */
-
-/* ADC12IFGR1 Control Bits */
-#define ADC12IFG16 (0x0001) /* ADC12 Memory 16 Interrupt Flag */
-#define ADC12IFG17 (0x0002) /* ADC12 Memory 17 Interrupt Flag */
-#define ADC12IFG18 (0x0004) /* ADC12 Memory 18 Interrupt Flag */
-#define ADC12IFG19 (0x0008) /* ADC12 Memory 19 Interrupt Flag */
-#define ADC12IFG20 (0x0010) /* ADC12 Memory 20 Interrupt Flag */
-#define ADC12IFG21 (0x0020) /* ADC12 Memory 21 Interrupt Flag */
-#define ADC12IFG22 (0x0040) /* ADC12 Memory 22 Interrupt Flag */
-#define ADC12IFG23 (0x0080) /* ADC12 Memory 23 Interrupt Flag */
-#define ADC12IFG24 (0x0100) /* ADC12 Memory 24 Interrupt Flag */
-#define ADC12IFG25 (0x0200) /* ADC12 Memory 25 Interrupt Flag */
-#define ADC12IFG26 (0x0400) /* ADC12 Memory 26 Interrupt Flag */
-#define ADC12IFG27 (0x0800) /* ADC12 Memory 27 Interrupt Flag */
-#define ADC12IFG28 (0x1000) /* ADC12 Memory 28 Interrupt Flag */
-#define ADC12IFG29 (0x2000) /* ADC12 Memory 29 Interrupt Flag */
-#define ADC12IFG30 (0x4000) /* ADC12 Memory 30 Interrupt Flag */
-#define ADC12IFG31 (0x8000) /* ADC12 Memory 31 Interrupt Flag */
-
-/* ADC12IFGR1 Control Bits */
-#define ADC12IFG16_L (0x0001) /* ADC12 Memory 16 Interrupt Flag */
-#define ADC12IFG17_L (0x0002) /* ADC12 Memory 17 Interrupt Flag */
-#define ADC12IFG18_L (0x0004) /* ADC12 Memory 18 Interrupt Flag */
-#define ADC12IFG19_L (0x0008) /* ADC12 Memory 19 Interrupt Flag */
-#define ADC12IFG20_L (0x0010) /* ADC12 Memory 20 Interrupt Flag */
-#define ADC12IFG21_L (0x0020) /* ADC12 Memory 21 Interrupt Flag */
-#define ADC12IFG22_L (0x0040) /* ADC12 Memory 22 Interrupt Flag */
-#define ADC12IFG23_L (0x0080) /* ADC12 Memory 23 Interrupt Flag */
-
-/* ADC12IFGR1 Control Bits */
-#define ADC12IFG24_H (0x0001) /* ADC12 Memory 24 Interrupt Flag */
-#define ADC12IFG25_H (0x0002) /* ADC12 Memory 25 Interrupt Flag */
-#define ADC12IFG26_H (0x0004) /* ADC12 Memory 26 Interrupt Flag */
-#define ADC12IFG27_H (0x0008) /* ADC12 Memory 27 Interrupt Flag */
-#define ADC12IFG28_H (0x0010) /* ADC12 Memory 28 Interrupt Flag */
-#define ADC12IFG29_H (0x0020) /* ADC12 Memory 29 Interrupt Flag */
-#define ADC12IFG30_H (0x0040) /* ADC12 Memory 30 Interrupt Flag */
-#define ADC12IFG31_H (0x0080) /* ADC12 Memory 31 Interrupt Flag */
-
-/* ADC12IFGR2 Control Bits */
-#define ADC12INIFG (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
-#define ADC12LOIFG (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
-#define ADC12HIIFG (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
-#define ADC12OVIFG (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */
-#define ADC12TOVIFG (0x0020) /* ADC12 Timer Overflow interrupt Flag */
-#define ADC12RDYIFG (0x0040) /* ADC12 local buffered reference ready interrupt Flag */
-
-/* ADC12IFGR2 Control Bits */
-#define ADC12INIFG_L (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
-#define ADC12LOIFG_L (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
-#define ADC12HIIFG_L (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
-#define ADC12OVIFG_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */
-#define ADC12TOVIFG_L (0x0020) /* ADC12 Timer Overflow interrupt Flag */
-#define ADC12RDYIFG_L (0x0040) /* ADC12 local buffered reference ready interrupt Flag */
-
-
-/* ADC12IV Definitions */
-#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
-#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
-#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
-#define ADC12IV_ADC12HIIFG (0x0006) /* ADC12HIIFG */
-#define ADC12IV_ADC12LOIFG (0x0008) /* ADC12LOIFG */
-#define ADC12IV_ADC12INIFG (0x000A) /* ADC12INIFG */
-#define ADC12IV_ADC12IFG0 (0x000C) /* ADC12IFG0 */
-#define ADC12IV_ADC12IFG1 (0x000E) /* ADC12IFG1 */
-#define ADC12IV_ADC12IFG2 (0x0010) /* ADC12IFG2 */
-#define ADC12IV_ADC12IFG3 (0x0012) /* ADC12IFG3 */
-#define ADC12IV_ADC12IFG4 (0x0014) /* ADC12IFG4 */
-#define ADC12IV_ADC12IFG5 (0x0016) /* ADC12IFG5 */
-#define ADC12IV_ADC12IFG6 (0x0018) /* ADC12IFG6 */
-#define ADC12IV_ADC12IFG7 (0x001A) /* ADC12IFG7 */
-#define ADC12IV_ADC12IFG8 (0x001C) /* ADC12IFG8 */
-#define ADC12IV_ADC12IFG9 (0x001E) /* ADC12IFG9 */
-#define ADC12IV_ADC12IFG10 (0x0020) /* ADC12IFG10 */
-#define ADC12IV_ADC12IFG11 (0x0022) /* ADC12IFG11 */
-#define ADC12IV_ADC12IFG12 (0x0024) /* ADC12IFG12 */
-#define ADC12IV_ADC12IFG13 (0x0026) /* ADC12IFG13 */
-#define ADC12IV_ADC12IFG14 (0x0028) /* ADC12IFG14 */
-#define ADC12IV_ADC12IFG15 (0x002A) /* ADC12IFG15 */
-#define ADC12IV_ADC12IFG16 (0x002C) /* ADC12IFG16 */
-#define ADC12IV_ADC12IFG17 (0x002E) /* ADC12IFG17 */
-#define ADC12IV_ADC12IFG18 (0x0030) /* ADC12IFG18 */
-#define ADC12IV_ADC12IFG19 (0x0032) /* ADC12IFG19 */
-#define ADC12IV_ADC12IFG20 (0x0034) /* ADC12IFG20 */
-#define ADC12IV_ADC12IFG21 (0x0036) /* ADC12IFG21 */
-#define ADC12IV_ADC12IFG22 (0x0038) /* ADC12IFG22 */
-#define ADC12IV_ADC12IFG23 (0x003A) /* ADC12IFG23 */
-#define ADC12IV_ADC12IFG24 (0x003C) /* ADC12IFG24 */
-#define ADC12IV_ADC12IFG25 (0x003E) /* ADC12IFG25 */
-#define ADC12IV_ADC12IFG26 (0x0040) /* ADC12IFG26 */
-#define ADC12IV_ADC12IFG27 (0x0042) /* ADC12IFG27 */
-#define ADC12IV_ADC12IFG28 (0x0044) /* ADC12IFG28 */
-#define ADC12IV_ADC12IFG29 (0x0046) /* ADC12IFG29 */
-#define ADC12IV_ADC12IFG30 (0x0048) /* ADC12IFG30 */
-#define ADC12IV_ADC12IFG31 (0x004A) /* ADC12IFG31 */
-#define ADC12IV_ADC12RDYIFG (0x004C) /* ADC12RDYIFG */
-
-
-/************************************************************
-* AES256 Accelerator
-************************************************************/
-
-#define AESACTL0 0x09C0 /* AES accelerator control register 0 */
-#define AESACTL1 0x09C2 /* AES accelerator control register 1 */
-#define AESASTAT 0x09C4 /* AES accelerator status register */
-#define AESAKEY 0x09C6 /* AES accelerator key register */
-#define AESADIN 0x09C8 /* AES accelerator data in register */
-#define AESADOUT 0x09CA /* AES accelerator data out register */
-#define AESAXDIN 0x09CC /* AES accelerator XORed data in register */
-#define AESAXIN 0x09CE /* AES accelerator XORed data in register (no trigger) */
-
-
-/* AESACTL0 Control Bits */
-#define AESOP0 (0x0001) /* AES Operation Bit: 0 */
-#define AESOP1 (0x0002) /* AES Operation Bit: 1 */
-#define AESKL0 (0x0004) /* AES Key length Bit: 0 */
-#define AESKL1 (0x0008) /* AES Key length Bit: 1 */
-#define AESTRIG (0x0010) /* AES Trigger Select */
-#define AESCM0 (0x0020) /* AES Cipher mode select Bit: 0 */
-#define AESCM1 (0x0040) /* AES Cipher mode select Bit: 1 */
-#define AESSWRST (0x0080) /* AES Software Reset */
-#define AESRDYIFG (0x0100) /* AES ready interrupt flag */
-#define AESERRFG (0x0800) /* AES Error Flag */
-#define AESRDYIE (0x1000) /* AES ready interrupt enable*/
-#define AESCMEN (0x8000) /* AES DMA cipher mode enable*/
-
-/* AESACTL0 Control Bits */
-#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */
-#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */
-#define AESKL0_L (0x0004) /* AES Key length Bit: 0 */
-#define AESKL1_L (0x0008) /* AES Key length Bit: 1 */
-#define AESTRIG_L (0x0010) /* AES Trigger Select */
-#define AESCM0_L (0x0020) /* AES Cipher mode select Bit: 0 */
-#define AESCM1_L (0x0040) /* AES Cipher mode select Bit: 1 */
-#define AESSWRST_L (0x0080) /* AES Software Reset */
-
-/* AESACTL0 Control Bits */
-#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */
-#define AESERRFG_H (0x0008) /* AES Error Flag */
-#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/
-#define AESCMEN_H (0x0080) /* AES DMA cipher mode enable*/
-
-#define AESOP_0 (0x0000) /* AES Operation: Encrypt */
-#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */
-#define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */
-#define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */
-
-#define AESKL_0 (0x0000) /* AES Key length: AES128 */
-#define AESKL_1 (0x0004) /* AES Key length: AES192 */
-#define AESKL_2 (0x0008) /* AES Key length: AES256 */
-#define AESKL__128 (0x0000) /* AES Key length: AES128 */
-#define AESKL__192 (0x0004) /* AES Key length: AES192 */
-#define AESKL__256 (0x0008) /* AES Key length: AES256 */
-
-#define AESCM_0 (0x0000) /* AES Cipher mode select: ECB */
-#define AESCM_1 (0x0020) /* AES Cipher mode select: CBC */
-#define AESCM_2 (0x0040) /* AES Cipher mode select: OFB */
-#define AESCM_3 (0x0060) /* AES Cipher mode select: CFB */
-#define AESCM__ECB (0x0000) /* AES Cipher mode select: ECB */
-#define AESCM__CBC (0x0020) /* AES Cipher mode select: CBC */
-#define AESCM__OFB (0x0040) /* AES Cipher mode select: OFB */
-#define AESCM__CFB (0x0060) /* AES Cipher mode select: CFB */
-
-
-/* AESACTL1 Control Bits */
-#define AESBLKCNT0 (0x0001) /* AES Cipher Block Counter Bit: 0 */
-#define AESBLKCNT1 (0x0002) /* AES Cipher Block Counter Bit: 1 */
-#define AESBLKCNT2 (0x0004) /* AES Cipher Block Counter Bit: 2 */
-#define AESBLKCNT3 (0x0008) /* AES Cipher Block Counter Bit: 3 */
-#define AESBLKCNT4 (0x0010) /* AES Cipher Block Counter Bit: 4 */
-#define AESBLKCNT5 (0x0020) /* AES Cipher Block Counter Bit: 5 */
-#define AESBLKCNT6 (0x0040) /* AES Cipher Block Counter Bit: 6 */
-#define AESBLKCNT7 (0x0080) /* AES Cipher Block Counter Bit: 7 */
-
-/* AESACTL1 Control Bits */
-#define AESBLKCNT0_L (0x0001) /* AES Cipher Block Counter Bit: 0 */
-#define AESBLKCNT1_L (0x0002) /* AES Cipher Block Counter Bit: 1 */
-#define AESBLKCNT2_L (0x0004) /* AES Cipher Block Counter Bit: 2 */
-#define AESBLKCNT3_L (0x0008) /* AES Cipher Block Counter Bit: 3 */
-#define AESBLKCNT4_L (0x0010) /* AES Cipher Block Counter Bit: 4 */
-#define AESBLKCNT5_L (0x0020) /* AES Cipher Block Counter Bit: 5 */
-#define AESBLKCNT6_L (0x0040) /* AES Cipher Block Counter Bit: 6 */
-#define AESBLKCNT7_L (0x0080) /* AES Cipher Block Counter Bit: 7 */
-
-
-/* AESASTAT Control Bits */
-#define AESBUSY (0x0001) /* AES Busy */
-#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */
-#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */
-#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */
-#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
-#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
-#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
-#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
-#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */
-#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */
-#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */
-#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */
-#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */
-#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */
-#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */
-#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */
-
-/* AESASTAT Control Bits */
-#define AESBUSY_L (0x0001) /* AES Busy */
-#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */
-#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */
-#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */
-#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
-#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
-#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
-#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
-
-/* AESASTAT Control Bits */
-#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */
-#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */
-#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */
-#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */
-#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */
-#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */
-#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */
-#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */
-
-/************************************************************
-* Capacitive_Touch_IO 0
-************************************************************/
-
-#define CAPTIO0CTL 0x043E /* Capacitive_Touch_IO 0 control register */
-#define CAPSIO0CTL CAPTIO0CTL /* legacy define */
-
-/************************************************************
-* Capacitive_Touch_IO 1
-************************************************************/
-
-#define CAPTIO1CTL 0x047E /* Capacitive_Touch_IO 1 control register */
-
-#define CAPSIO1CTL CAPTIO1CTL /* legacy define */
-
-/* CAPTIOxCTL Control Bits */
-#define CAPTIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */
-#define CAPTIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */
-#define CAPTIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */
-#define CAPTIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */
-#define CAPTIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */
-#define CAPTIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */
-#define CAPTIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */
-#define CAPTIOEN (0x0100) /* CapTouchIO Enable */
-#define CAPTIO (0x0200) /* CapTouchIO state */
-
-/* CAPTIOxCTL Control Bits */
-#define CAPTIOPISEL0_L (0x0002) /* CapTouchIO Pin Select Bit: 0 */
-#define CAPTIOPISEL1_L (0x0004) /* CapTouchIO Pin Select Bit: 1 */
-#define CAPTIOPISEL2_L (0x0008) /* CapTouchIO Pin Select Bit: 2 */
-#define CAPTIOPOSEL0_L (0x0010) /* CapTouchIO Port Select Bit: 0 */
-#define CAPTIOPOSEL1_L (0x0020) /* CapTouchIO Port Select Bit: 1 */
-#define CAPTIOPOSEL2_L (0x0040) /* CapTouchIO Port Select Bit: 2 */
-#define CAPTIOPOSEL3_L (0x0080) /* CapTouchIO Port Select Bit: 3 */
-
-/* CAPTIOxCTL Control Bits */
-#define CAPTIOEN_H (0x0001) /* CapTouchIO Enable */
-#define CAPTIO_H (0x0002) /* CapTouchIO state */
-
-/* Legacy defines */
-#define CAPSIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */
-#define CAPSIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */
-#define CAPSIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */
-#define CAPSIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */
-#define CAPSIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */
-#define CAPSIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */
-#define CAPSIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */
-#define CAPSIOEN (0x0100) /* CapTouchIO Enable */
-#define CAPSIO (0x0200) /* CapTouchIO state */
-
-/************************************************************
-* Comparator E
-************************************************************/
-
-#define CECTL0 0x08C0 /* Comparator E Control Register 0 */
-#define CECTL1 0x08C2 /* Comparator E Control Register 1 */
-#define CECTL2 0x08C4 /* Comparator E Control Register 2 */
-#define CECTL3 0x08C6 /* Comparator E Control Register 3 */
-#define CEINT 0x08CC /* Comparator E Interrupt Register */
-#define CEIV 0x08CE /* Comparator E Interrupt Vector Word */
-
-/* CECTL0 Control Bits */
-#define CEIPSEL0 (0x0001) /* Comp. E Pos. Channel Input Select 0 */
-#define CEIPSEL1 (0x0002) /* Comp. E Pos. Channel Input Select 1 */
-#define CEIPSEL2 (0x0004) /* Comp. E Pos. Channel Input Select 2 */
-#define CEIPSEL3 (0x0008) /* Comp. E Pos. Channel Input Select 3 */
-//#define RESERVED (0x0010) /* Comp. E */
-//#define RESERVED (0x0020) /* Comp. E */
-//#define RESERVED (0x0040) /* Comp. E */
-#define CEIPEN (0x0080) /* Comp. E Pos. Channel Input Enable */
-#define CEIMSEL0 (0x0100) /* Comp. E Neg. Channel Input Select 0 */
-#define CEIMSEL1 (0x0200) /* Comp. E Neg. Channel Input Select 1 */
-#define CEIMSEL2 (0x0400) /* Comp. E Neg. Channel Input Select 2 */
-#define CEIMSEL3 (0x0800) /* Comp. E Neg. Channel Input Select 3 */
-//#define RESERVED (0x1000) /* Comp. E */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-#define CEIMEN (0x8000) /* Comp. E Neg. Channel Input Enable */
-
-/* CECTL0 Control Bits */
-#define CEIPSEL0_L (0x0001) /* Comp. E Pos. Channel Input Select 0 */
-#define CEIPSEL1_L (0x0002) /* Comp. E Pos. Channel Input Select 1 */
-#define CEIPSEL2_L (0x0004) /* Comp. E Pos. Channel Input Select 2 */
-#define CEIPSEL3_L (0x0008) /* Comp. E Pos. Channel Input Select 3 */
-//#define RESERVED (0x0010) /* Comp. E */
-//#define RESERVED (0x0020) /* Comp. E */
-//#define RESERVED (0x0040) /* Comp. E */
-#define CEIPEN_L (0x0080) /* Comp. E Pos. Channel Input Enable */
-//#define RESERVED (0x1000) /* Comp. E */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-
-/* CECTL0 Control Bits */
-//#define RESERVED (0x0010) /* Comp. E */
-//#define RESERVED (0x0020) /* Comp. E */
-//#define RESERVED (0x0040) /* Comp. E */
-#define CEIMSEL0_H (0x0001) /* Comp. E Neg. Channel Input Select 0 */
-#define CEIMSEL1_H (0x0002) /* Comp. E Neg. Channel Input Select 1 */
-#define CEIMSEL2_H (0x0004) /* Comp. E Neg. Channel Input Select 2 */
-#define CEIMSEL3_H (0x0008) /* Comp. E Neg. Channel Input Select 3 */
-//#define RESERVED (0x1000) /* Comp. E */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-#define CEIMEN_H (0x0080) /* Comp. E Neg. Channel Input Enable */
-
-#define CEIPSEL_0 (0x0000) /* Comp. E V+ terminal Input Select: Channel 0 */
-#define CEIPSEL_1 (0x0001) /* Comp. E V+ terminal Input Select: Channel 1 */
-#define CEIPSEL_2 (0x0002) /* Comp. E V+ terminal Input Select: Channel 2 */
-#define CEIPSEL_3 (0x0003) /* Comp. E V+ terminal Input Select: Channel 3 */
-#define CEIPSEL_4 (0x0004) /* Comp. E V+ terminal Input Select: Channel 4 */
-#define CEIPSEL_5 (0x0005) /* Comp. E V+ terminal Input Select: Channel 5 */
-#define CEIPSEL_6 (0x0006) /* Comp. E V+ terminal Input Select: Channel 6 */
-#define CEIPSEL_7 (0x0007) /* Comp. E V+ terminal Input Select: Channel 7 */
-#define CEIPSEL_8 (0x0008) /* Comp. E V+ terminal Input Select: Channel 8 */
-#define CEIPSEL_9 (0x0009) /* Comp. E V+ terminal Input Select: Channel 9 */
-#define CEIPSEL_10 (0x000A) /* Comp. E V+ terminal Input Select: Channel 10 */
-#define CEIPSEL_11 (0x000B) /* Comp. E V+ terminal Input Select: Channel 11 */
-#define CEIPSEL_12 (0x000C) /* Comp. E V+ terminal Input Select: Channel 12 */
-#define CEIPSEL_13 (0x000D) /* Comp. E V+ terminal Input Select: Channel 13 */
-#define CEIPSEL_14 (0x000E) /* Comp. E V+ terminal Input Select: Channel 14 */
-#define CEIPSEL_15 (0x000F) /* Comp. E V+ terminal Input Select: Channel 15 */
-
-#define CEIMSEL_0 (0x0000) /* Comp. E V- Terminal Input Select: Channel 0 */
-#define CEIMSEL_1 (0x0100) /* Comp. E V- Terminal Input Select: Channel 1 */
-#define CEIMSEL_2 (0x0200) /* Comp. E V- Terminal Input Select: Channel 2 */
-#define CEIMSEL_3 (0x0300) /* Comp. E V- Terminal Input Select: Channel 3 */
-#define CEIMSEL_4 (0x0400) /* Comp. E V- Terminal Input Select: Channel 4 */
-#define CEIMSEL_5 (0x0500) /* Comp. E V- Terminal Input Select: Channel 5 */
-#define CEIMSEL_6 (0x0600) /* Comp. E V- Terminal Input Select: Channel 6 */
-#define CEIMSEL_7 (0x0700) /* Comp. E V- Terminal Input Select: Channel 7 */
-#define CEIMSEL_8 (0x0800) /* Comp. E V- terminal Input Select: Channel 8 */
-#define CEIMSEL_9 (0x0900) /* Comp. E V- terminal Input Select: Channel 9 */
-#define CEIMSEL_10 (0x0A00) /* Comp. E V- terminal Input Select: Channel 10 */
-#define CEIMSEL_11 (0x0B00) /* Comp. E V- terminal Input Select: Channel 11 */
-#define CEIMSEL_12 (0x0C00) /* Comp. E V- terminal Input Select: Channel 12 */
-#define CEIMSEL_13 (0x0D00) /* Comp. E V- terminal Input Select: Channel 13 */
-#define CEIMSEL_14 (0x0E00) /* Comp. E V- terminal Input Select: Channel 14 */
-#define CEIMSEL_15 (0x0F00) /* Comp. E V- terminal Input Select: Channel 15 */
-
-/* CECTL1 Control Bits */
-#define CEOUT (0x0001) /* Comp. E Output */
-#define CEOUTPOL (0x0002) /* Comp. E Output Polarity */
-#define CEF (0x0004) /* Comp. E Enable Output Filter */
-#define CEIES (0x0008) /* Comp. E Interrupt Edge Select */
-#define CESHORT (0x0010) /* Comp. E Input Short */
-#define CEEX (0x0020) /* Comp. E Exchange Inputs */
-#define CEFDLY0 (0x0040) /* Comp. E Filter delay Bit 0 */
-#define CEFDLY1 (0x0080) /* Comp. E Filter delay Bit 1 */
-#define CEPWRMD0 (0x0100) /* Comp. E Power mode Bit 0 */
-#define CEPWRMD1 (0x0200) /* Comp. E Power mode Bit 1 */
-#define CEON (0x0400) /* Comp. E enable */
-#define CEMRVL (0x0800) /* Comp. E CEMRV Level */
-#define CEMRVS (0x1000) /* Comp. E Output selects between VREF0 or VREF1*/
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-//#define RESERVED (0x8000) /* Comp. E */
-
-/* CECTL1 Control Bits */
-#define CEOUT_L (0x0001) /* Comp. E Output */
-#define CEOUTPOL_L (0x0002) /* Comp. E Output Polarity */
-#define CEF_L (0x0004) /* Comp. E Enable Output Filter */
-#define CEIES_L (0x0008) /* Comp. E Interrupt Edge Select */
-#define CESHORT_L (0x0010) /* Comp. E Input Short */
-#define CEEX_L (0x0020) /* Comp. E Exchange Inputs */
-#define CEFDLY0_L (0x0040) /* Comp. E Filter delay Bit 0 */
-#define CEFDLY1_L (0x0080) /* Comp. E Filter delay Bit 1 */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-//#define RESERVED (0x8000) /* Comp. E */
-
-/* CECTL1 Control Bits */
-#define CEPWRMD0_H (0x0001) /* Comp. E Power mode Bit 0 */
-#define CEPWRMD1_H (0x0002) /* Comp. E Power mode Bit 1 */
-#define CEON_H (0x0004) /* Comp. E enable */
-#define CEMRVL_H (0x0008) /* Comp. E CEMRV Level */
-#define CEMRVS_H (0x0010) /* Comp. E Output selects between VREF0 or VREF1*/
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-//#define RESERVED (0x8000) /* Comp. E */
-
-#define CEPWRMD_0 (0x0000) /* Comp. E Power mode 0 */
-#define CEPWRMD_1 (0x0100) /* Comp. E Power mode 1 */
-#define CEPWRMD_2 (0x0200) /* Comp. E Power mode 2 */
-#define CEPWRMD_3 (0x0300) /* Comp. E Power mode 3*/
-
-#define CEFDLY_0 (0x0000) /* Comp. E Filter delay 0 : 450ns */
-#define CEFDLY_1 (0x0040) /* Comp. E Filter delay 1 : 900ns */
-#define CEFDLY_2 (0x0080) /* Comp. E Filter delay 2 : 1800ns */
-#define CEFDLY_3 (0x00C0) /* Comp. E Filter delay 3 : 3600ns */
-
-
-/* CECTL2 Control Bits */
-#define CEREF00 (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */
-#define CEREF01 (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */
-#define CEREF02 (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */
-#define CEREF03 (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */
-#define CEREF04 (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */
-#define CERSEL (0x0020) /* Comp. E Reference select */
-#define CERS0 (0x0040) /* Comp. E Reference Source Bit : 0 */
-#define CERS1 (0x0080) /* Comp. E Reference Source Bit : 1 */
-#define CEREF10 (0x0100) /* Comp. E Reference 1 Resistor Select Bit : 0 */
-#define CEREF11 (0x0200) /* Comp. E Reference 1 Resistor Select Bit : 1 */
-#define CEREF12 (0x0400) /* Comp. E Reference 1 Resistor Select Bit : 2 */
-#define CEREF13 (0x0800) /* Comp. E Reference 1 Resistor Select Bit : 3 */
-#define CEREF14 (0x1000) /* Comp. E Reference 1 Resistor Select Bit : 4 */
-#define CEREFL0 (0x2000) /* Comp. E Reference voltage level Bit : 0 */
-#define CEREFL1 (0x4000) /* Comp. E Reference voltage level Bit : 1 */
-#define CEREFACC (0x8000) /* Comp. E Reference Accuracy */
-
-/* CECTL2 Control Bits */
-#define CEREF00_L (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */
-#define CEREF01_L (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */
-#define CEREF02_L (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */
-#define CEREF03_L (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */
-#define CEREF04_L (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */
-#define CERSEL_L (0x0020) /* Comp. E Reference select */
-#define CERS0_L (0x0040) /* Comp. E Reference Source Bit : 0 */
-#define CERS1_L (0x0080) /* Comp. E Reference Source Bit : 1 */
-
-/* CECTL2 Control Bits */
-#define CEREF10_H (0x0001) /* Comp. E Reference 1 Resistor Select Bit : 0 */
-#define CEREF11_H (0x0002) /* Comp. E Reference 1 Resistor Select Bit : 1 */
-#define CEREF12_H (0x0004) /* Comp. E Reference 1 Resistor Select Bit : 2 */
-#define CEREF13_H (0x0008) /* Comp. E Reference 1 Resistor Select Bit : 3 */
-#define CEREF14_H (0x0010) /* Comp. E Reference 1 Resistor Select Bit : 4 */
-#define CEREFL0_H (0x0020) /* Comp. E Reference voltage level Bit : 0 */
-#define CEREFL1_H (0x0040) /* Comp. E Reference voltage level Bit : 1 */
-#define CEREFACC_H (0x0080) /* Comp. E Reference Accuracy */
-
-#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */
-#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */
-#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */
-#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */
-#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */
-#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */
-#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */
-#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */
-#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */
-#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */
-#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */
-#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */
-#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */
-#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */
-#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */
-#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */
-#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */
-#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */
-#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */
-#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */
-#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */
-#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */
-#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */
-#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */
-#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */
-#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */
-#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */
-#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */
-#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */
-#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */
-#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */
-#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */
-
-#define CERS_0 (0x0000) /* Comp. E Reference Source 0 : Off */
-#define CERS_1 (0x0040) /* Comp. E Reference Source 1 : Vcc */
-#define CERS_2 (0x0080) /* Comp. E Reference Source 2 : Shared Ref. */
-#define CERS_3 (0x00C0) /* Comp. E Reference Source 3 : Shared Ref. / Off */
-
-#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */
-#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */
-#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */
-#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */
-#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */
-#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */
-#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */
-#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */
-#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */
-#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */
-#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */
-#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */
-#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */
-#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */
-#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */
-#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */
-#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */
-#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */
-#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */
-#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */
-#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */
-#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */
-#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */
-#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */
-#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */
-#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */
-#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */
-#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */
-#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */
-#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */
-#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */
-#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */
-
-#define CEREFL_0 (0x0000) /* Comp. E Reference voltage level 0 : None */
-#define CEREFL_1 (0x2000) /* Comp. E Reference voltage level 1 : 1.2V */
-#define CEREFL_2 (0x4000) /* Comp. E Reference voltage level 2 : 2.0V */
-#define CEREFL_3 (0x6000) /* Comp. E Reference voltage level 3 : 2.5V */
-
-
-#define CEPD0 (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */
-#define CEPD1 (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */
-#define CEPD2 (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */
-#define CEPD3 (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */
-#define CEPD4 (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */
-#define CEPD5 (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */
-#define CEPD6 (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */
-#define CEPD7 (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */
-#define CEPD8 (0x0100) /* Comp. E Disable Input Buffer of Port Register .8 */
-#define CEPD9 (0x0200) /* Comp. E Disable Input Buffer of Port Register .9 */
-#define CEPD10 (0x0400) /* Comp. E Disable Input Buffer of Port Register .10 */
-#define CEPD11 (0x0800) /* Comp. E Disable Input Buffer of Port Register .11 */
-#define CEPD12 (0x1000) /* Comp. E Disable Input Buffer of Port Register .12 */
-#define CEPD13 (0x2000) /* Comp. E Disable Input Buffer of Port Register .13 */
-#define CEPD14 (0x4000) /* Comp. E Disable Input Buffer of Port Register .14 */
-#define CEPD15 (0x8000) /* Comp. E Disable Input Buffer of Port Register .15 */
-
-#define CEPD0_L (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */
-#define CEPD1_L (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */
-#define CEPD2_L (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */
-#define CEPD3_L (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */
-#define CEPD4_L (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */
-#define CEPD5_L (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */
-#define CEPD6_L (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */
-#define CEPD7_L (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */
-
-#define CEPD8_H (0x0001) /* Comp. E Disable Input Buffer of Port Register .8 */
-#define CEPD9_H (0x0002) /* Comp. E Disable Input Buffer of Port Register .9 */
-#define CEPD10_H (0x0004) /* Comp. E Disable Input Buffer of Port Register .10 */
-#define CEPD11_H (0x0008) /* Comp. E Disable Input Buffer of Port Register .11 */
-#define CEPD12_H (0x0010) /* Comp. E Disable Input Buffer of Port Register .12 */
-#define CEPD13_H (0x0020) /* Comp. E Disable Input Buffer of Port Register .13 */
-#define CEPD14_H (0x0040) /* Comp. E Disable Input Buffer of Port Register .14 */
-#define CEPD15_H (0x0080) /* Comp. E Disable Input Buffer of Port Register .15 */
-
-
-/* CEINT Control Bits */
-#define CEIFG (0x0001) /* Comp. E Interrupt Flag */
-#define CEIIFG (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */
-//#define RESERVED (0x0004) /* Comp. E */
-//#define RESERVED (0x0008) /* Comp. E */
-#define CERDYIFG (0x0010) /* Comp. E Comparator_E ready interrupt flag */
-//#define RESERVED (0x0020) /* Comp. E */
-//#define RESERVED (0x0040) /* Comp. E */
-//#define RESERVED (0x0080) /* Comp. E */
-#define CEIE (0x0100) /* Comp. E Interrupt Enable */
-#define CEIIE (0x0200) /* Comp. E Interrupt Enable Inverted Polarity */
-//#define RESERVED (0x0400) /* Comp. E */
-//#define RESERVED (0x0800) /* Comp. E */
-#define CERDYIE (0x1000) /* Comp. E Comparator_E ready interrupt enable */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-//#define RESERVED (0x8000) /* Comp. E */
-
-/* CEINT Control Bits */
-#define CEIFG_L (0x0001) /* Comp. E Interrupt Flag */
-#define CEIIFG_L (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */
-//#define RESERVED (0x0004) /* Comp. E */
-//#define RESERVED (0x0008) /* Comp. E */
-#define CERDYIFG_L (0x0010) /* Comp. E Comparator_E ready interrupt flag */
-//#define RESERVED (0x0020) /* Comp. E */
-//#define RESERVED (0x0040) /* Comp. E */
-//#define RESERVED (0x0080) /* Comp. E */
-//#define RESERVED (0x0400) /* Comp. E */
-//#define RESERVED (0x0800) /* Comp. E */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-//#define RESERVED (0x8000) /* Comp. E */
-
-/* CEINT Control Bits */
-//#define RESERVED (0x0004) /* Comp. E */
-//#define RESERVED (0x0008) /* Comp. E */
-//#define RESERVED (0x0020) /* Comp. E */
-//#define RESERVED (0x0040) /* Comp. E */
-//#define RESERVED (0x0080) /* Comp. E */
-#define CEIE_H (0x0001) /* Comp. E Interrupt Enable */
-#define CEIIE_H (0x0002) /* Comp. E Interrupt Enable Inverted Polarity */
-//#define RESERVED (0x0400) /* Comp. E */
-//#define RESERVED (0x0800) /* Comp. E */
-#define CERDYIE_H (0x0010) /* Comp. E Comparator_E ready interrupt enable */
-//#define RESERVED (0x2000) /* Comp. E */
-//#define RESERVED (0x4000) /* Comp. E */
-//#define RESERVED (0x8000) /* Comp. E */
-
-/* CEIV Definitions */
-#define CEIV_NONE (0x0000) /* No Interrupt pending */
-#define CEIV_CEIFG (0x0002) /* CEIFG */
-#define CEIV_CEIIFG (0x0004) /* CEIIFG */
-#define CEIV_CERDYIFG (0x000A) /* CERDYIFG */
-
-/*************************************************************
-* CRC Module
-*************************************************************/
-
-#define CRCDI 0x0150 /* CRC Data In Register */
-#define CRCDIRB 0x0152 /* CRC data in reverse byte Register */
-#define CRCINIRES 0x0154 /* CRC Initialisation Register and Result Register */
-#define CRCRESR 0x0156 /* CRC reverse result Register */
-
-/************************************************************
-* CLOCK SYSTEM
-************************************************************/
-
-#define CSCTL0 0x0160 /* CS Control Register 0 */
-#define CSCTL1 0x0162 /* CS Control Register 1 */
-#define CSCTL2 0x0164 /* CS Control Register 2 */
-#define CSCTL3 0x0166 /* CS Control Register 3 */
-#define CSCTL4 0x0168 /* CS Control Register 4 */
-#define CSCTL5 0x016A /* CS Control Register 5 */
-#define CSCTL6 0x016C /* CS Control Register 6 */
-
-/* CSCTL0 Control Bits */
-
-#define CSKEY (0xA500) /* CS Password */
-#define CSKEY_H (0xA5) /* CS Password for high byte access */
-
-/* CSCTL1 Control Bits */
-#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */
-#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */
-#define DCOFSEL2 (0x0008) /* DCO frequency select Bit: 2 */
-#define DCORSEL (0x0040) /* DCO range select. */
-
-/* CSCTL1 Control Bits */
-#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */
-#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */
-#define DCOFSEL2_L (0x0008) /* DCO frequency select Bit: 2 */
-#define DCORSEL_L (0x0040) /* DCO range select. */
-
-
-#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */
-#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */
-#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */
-#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */
-#define DCOFSEL_4 (0x0008) /* DCO frequency select: 4 */
-#define DCOFSEL_5 (0x000A) /* DCO frequency select: 5 */
-#define DCOFSEL_6 (0x000C) /* DCO frequency select: 6 */
-#define DCOFSEL_7 (0x000E) /* DCO frequency select: 7 */
-
-
-/* CSCTL2 Control Bits */
-#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
-#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
-#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
-#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
-#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
-#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
-#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* CSCTL2 Control Bits */
-#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
-#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
-#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
-#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
-#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* CSCTL2 Control Bits */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
-#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
-#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-#define SELM_0 (0x0000) /* MCLK Source Select 0 */
-#define SELM_1 (0x0001) /* MCLK Source Select 1 */
-#define SELM_2 (0x0002) /* MCLK Source Select 2 */
-#define SELM_3 (0x0003) /* MCLK Source Select 3 */
-#define SELM_4 (0x0004) /* MCLK Source Select 4 */
-#define SELM_5 (0x0005) /* MCLK Source Select 5 */
-#define SELM_6 (0x0006) /* MCLK Source Select 6 */
-#define SELM_7 (0x0007) /* MCLK Source Select 7 */
-#define SELM__LFXTCLK (0x0000) /* MCLK Source Select LFXTCLK */
-#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
-#define SELM__LFMODCLK (0x0002) /* MCLK Source Select LFMODOSC */
-#define SELM__LFMODOSC (0x0002) /* MCLK Source Select LFMODOSC (legacy) */
-#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
-#define SELM__MODCLK (0x0004) /* MCLK Source Select MODOSC */
-#define SELM__MODOSC (0x0004) /* MCLK Source Select MODOSC (legacy) */
-#define SELM__HFXTCLK (0x0005) /* MCLK Source Select HFXTCLK */
-
-#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
-#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
-#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
-#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
-#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
-#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
-#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
-#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
-#define SELS__LFXTCLK (0x0000) /* SMCLK Source Select LFXTCLK */
-#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
-#define SELS__LFMODCLK (0x0020) /* SMCLK Source Select LFMODOSC */
-#define SELS__LFMODOSC (0x0020) /* SMCLK Source Select LFMODOSC (legacy) */
-#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
-#define SELS__MODCLK (0x0040) /* SMCLK Source Select MODOSC */
-#define SELS__MODOSC (0x0040) /* SMCLK Source Select MODOSC (legacy) */
-#define SELS__HFXTCLK (0x0050) /* SMCLK Source Select HFXTCLK */
-
-#define SELA_0 (0x0000) /* ACLK Source Select 0 */
-#define SELA_1 (0x0100) /* ACLK Source Select 1 */
-#define SELA_2 (0x0200) /* ACLK Source Select 2 */
-#define SELA_3 (0x0300) /* ACLK Source Select 3 */
-#define SELA_4 (0x0400) /* ACLK Source Select 4 */
-#define SELA_5 (0x0500) /* ACLK Source Select 5 */
-#define SELA_6 (0x0600) /* ACLK Source Select 6 */
-#define SELA_7 (0x0700) /* ACLK Source Select 7 */
-#define SELA__LFXTCLK (0x0000) /* ACLK Source Select LFXTCLK */
-#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
-#define SELA__LFMODCLK (0x0200) /* ACLK Source Select LFMODOSC */
-#define SELA__LFMODOSC (0x0200) /* ACLK Source Select LFMODOSC (legacy) */
-
-/* CSCTL3 Control Bits */
-#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
-#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
-#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
-#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
-#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
-#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
-#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* CSCTL3 Control Bits */
-#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
-#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
-#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
-#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
-#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-/* CSCTL3 Control Bits */
-//#define RESERVED (0x0004) /* RESERVED */
-//#define RESERVED (0x0008) /* RESERVED */
-//#define RESERVED (0x0040) /* RESERVED */
-//#define RESERVED (0x0080) /* RESERVED */
-#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
-#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
-#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
-//#define RESERVED (0x0400) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x1000) /* RESERVED */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x4000) /* RESERVED */
-//#define RESERVED (0x8000) /* RESERVED */
-
-#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
-#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
-#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
-#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
-#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
-#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
-#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
-#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
-#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
-#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
-#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
-#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
-
-#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
-#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
-#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
-#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
-#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
-#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
-#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
-#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
-#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
-#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
-#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
-#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
-
-#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
-#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
-#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
-#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
-#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
-#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
-#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
-#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
-#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
-#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
-#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
-#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
-
-
-/* CSCTL4 Control Bits */
-#define LFXTOFF (0x0001) /* Low Frequency Oscillator (LFXT) disable */
-#define SMCLKOFF (0x0002) /* SMCLK Off */
-#define VLOOFF (0x0008) /* VLO Off */
-#define LFXTBYPASS (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
-#define LFXTDRIVE0 (0x0040) /* LFXT Drive Level mode Bit 0 */
-#define LFXTDRIVE1 (0x0080) /* LFXT Drive Level mode Bit 1 */
-#define HFXTOFF (0x0100) /* High Frequency Oscillator disable */
-#define HFFREQ0 (0x0400) /* HFXT frequency selection Bit 1 */
-#define HFFREQ1 (0x0800) /* HFXT frequency selection Bit 0 */
-#define HFXTBYPASS (0x1000) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
-#define HFXTDRIVE0 (0x4000) /* HFXT Drive Level mode Bit 0 */
-#define HFXTDRIVE1 (0x8000) /* HFXT Drive Level mode Bit 1 */
-
-/* CSCTL4 Control Bits */
-#define LFXTOFF_L (0x0001) /* Low Frequency Oscillator (LFXT) disable */
-#define SMCLKOFF_L (0x0002) /* SMCLK Off */
-#define VLOOFF_L (0x0008) /* VLO Off */
-#define LFXTBYPASS_L (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
-#define LFXTDRIVE0_L (0x0040) /* LFXT Drive Level mode Bit 0 */
-#define LFXTDRIVE1_L (0x0080) /* LFXT Drive Level mode Bit 1 */
-
-/* CSCTL4 Control Bits */
-#define HFXTOFF_H (0x0001) /* High Frequency Oscillator disable */
-#define HFFREQ0_H (0x0004) /* HFXT frequency selection Bit 1 */
-#define HFFREQ1_H (0x0008) /* HFXT frequency selection Bit 0 */
-#define HFXTBYPASS_H (0x0010) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
-#define HFXTDRIVE0_H (0x0040) /* HFXT Drive Level mode Bit 0 */
-#define HFXTDRIVE1_H (0x0080) /* HFXT Drive Level mode Bit 1 */
-
-#define LFXTDRIVE_0 (0x0000) /* LFXT Drive Level mode: 0 */
-#define LFXTDRIVE_1 (0x0040) /* LFXT Drive Level mode: 1 */
-#define LFXTDRIVE_2 (0x0080) /* LFXT Drive Level mode: 2 */
-#define LFXTDRIVE_3 (0x00C0) /* LFXT Drive Level mode: 3 */
-
-#define HFFREQ_0 (0x0000) /* HFXT frequency selection: 0 */
-#define HFFREQ_1 (0x0400) /* HFXT frequency selection: 1 */
-#define HFFREQ_2 (0x0800) /* HFXT frequency selection: 2 */
-#define HFFREQ_3 (0x0C00) /* HFXT frequency selection: 3 */
-
-#define HFXTDRIVE_0 (0x0000) /* HFXT Drive Level mode: 0 */
-#define HFXTDRIVE_1 (0x4000) /* HFXT Drive Level mode: 1 */
-#define HFXTDRIVE_2 (0x8000) /* HFXT Drive Level mode: 2 */
-#define HFXTDRIVE_3 (0xC000) /* HFXT Drive Level mode: 3 */
-
-/* CSCTL5 Control Bits */
-#define LFXTOFFG (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */
-#define HFXTOFFG (0x0002) /* HFXT High Frequency Oscillator Fault Flag */
-#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */
-#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */
-
-/* CSCTL5 Control Bits */
-#define LFXTOFFG_L (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */
-#define HFXTOFFG_L (0x0002) /* HFXT High Frequency Oscillator Fault Flag */
-#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */
-#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */
-
-
-/* CSCTL6 Control Bits */
-#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
-#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
-#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
-#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */
-
-/* CSCTL6 Control Bits */
-#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
-#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
-#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
-#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */
-
-
-/************************************************************
-* DMA_X
-************************************************************/
-
-#define DMACTL0 0x0500 /* DMA Module Control 0 */
-#define DMACTL1 0x0502 /* DMA Module Control 1 */
-#define DMACTL2 0x0504 /* DMA Module Control 2 */
-#define DMACTL3 0x0506 /* DMA Module Control 3 */
-#define DMACTL4 0x0508 /* DMA Module Control 4 */
-#define DMAIV 0x050E /* DMA Interrupt Vector Word */
-
-#define DMA0CTL 0x0510 /* DMA Channel 0 Control */
-#define DMA0SA 0x0512 /* DMA Channel 0 Source Address */
-#define DMA0DA 0x0516 /* DMA Channel 0 Destination Address */
-#define DMA0SZ 0x051A /* DMA Channel 0 Transfer Size */
-
-#define DMA1CTL 0x0520 /* DMA Channel 1 Control */
-#define DMA1SA 0x0522 /* DMA Channel 1 Source Address */
-#define DMA1DA 0x0526 /* DMA Channel 1 Destination Address */
-#define DMA1SZ 0x052A /* DMA Channel 1 Transfer Size */
-
-#define DMA2CTL 0x0530 /* DMA Channel 2 Control */
-#define DMA2SA 0x0532 /* DMA Channel 2 Source Address */
-#define DMA2DA 0x0536 /* DMA Channel 2 Destination Address */
-#define DMA2SZ 0x053A /* DMA Channel 2 Transfer Size */
-
-/* DMACTL0 Control Bits */
-#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
-#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
-#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
-#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
-#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
-#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
-#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
-#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
-#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
-#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
-
-/* DMACTL0 Control Bits */
-#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
-#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
-#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
-#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
-#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
-
-/* DMACTL0 Control Bits */
-#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
-#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
-#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
-#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
-#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
-
-/* DMACTL01 Control Bits */
-#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
-#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
-#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
-#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
-#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
-
-/* DMACTL01 Control Bits */
-#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
-#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
-#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
-#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
-#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
-
-
-/* DMACTL4 Control Bits */
-#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
-#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
-#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
-
-/* DMACTL4 Control Bits */
-#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
-#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
-#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
-
-
-
-/* DMAxCTL Control Bits */
-#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
-#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
-#define DMAIE (0x0004) /* DMA interrupt enable */
-#define DMAIFG (0x0008) /* DMA interrupt flag */
-#define DMAEN (0x0010) /* DMA enable */
-#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
-#define DMASRCBYTE (0x0040) /* DMA source byte */
-#define DMADSTBYTE (0x0080) /* DMA destination byte */
-#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
-#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
-#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
-#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
-#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
-#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
-#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
-
-/* DMAxCTL Control Bits */
-#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
-#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
-#define DMAIE_L (0x0004) /* DMA interrupt enable */
-#define DMAIFG_L (0x0008) /* DMA interrupt flag */
-#define DMAEN_L (0x0010) /* DMA enable */
-#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
-#define DMASRCBYTE_L (0x0040) /* DMA source byte */
-#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
-
-/* DMAxCTL Control Bits */
-#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
-#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
-#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
-#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
-#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
-#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
-#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
-
-#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */
-#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */
-#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */
-#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */
-
-#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */
-#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */
-#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */
-#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */
-
-#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */
-#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */
-#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */
-#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */
-
-#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */
-#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */
-#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */
-#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */
-#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */
-#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */
-#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */
-#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */
-
-/* DMAIV Definitions */
-#define DMAIV_NONE (0x0000) /* No Interrupt pending */
-#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
-#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
-#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
-
-#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
-#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: */
-#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: */
-#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: */
-#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: */
-#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: */
-#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: */
-#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: */
-#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: */
-#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: */
-#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: */
-#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: */
-#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: */
-#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: */
-#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: */
-#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: */
-#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: */
-#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: */
-#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: */
-#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: */
-#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: */
-#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: */
-#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: */
-#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: */
-#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: */
-#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: */
-#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: */
-#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: */
-#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: */
-#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: */
-#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
-#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
-#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: */
-#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: */
-#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: */
-#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: */
-#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: */
-#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: */
-#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: */
-#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: */
-#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: */
-#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: */
-#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: */
-#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: */
-#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: */
-#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: */
-#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: */
-#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: */
-#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: */
-#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: */
-#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: */
-#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: */
-#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: */
-#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: */
-#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: */
-#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: */
-#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: */
-#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: */
-#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: */
-#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: */
-#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: */
-#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
-#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
-#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: */
-#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: */
-#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: */
-#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: */
-#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: */
-#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: */
-#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: */
-#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: */
-#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: */
-#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: */
-#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: */
-#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: */
-#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: */
-#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: */
-#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: */
-#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: */
-#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: */
-#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: */
-#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: */
-#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: */
-#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: */
-#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: */
-#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: */
-#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: */
-#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: */
-#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: */
-#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: */
-#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: */
-#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: */
-#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
-#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA0TSEL__DMAREQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
-#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: TA0CCR0 */
-#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: TA0CCR2 */
-#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: TA1CCR0 */
-#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: TA1CCR2 */
-#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 3: TA2CCR0 */
-#define DMA0TSEL__TA3CCR0 (0x0006) /* DMA channel 0 transfer select 4: TA3CCR0 */
-#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TB0CCR0 */
-#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TB0CCR2 */
-#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: RES9 */
-#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: RES10 */
-#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: RES11 */
-#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: RES12 */
-#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: RES13 */
-#define DMA0TSEL__UCA0RXIFG (0x000E) /* DMA channel 0 transfer select 14: UCA0RXIFG */
-#define DMA0TSEL__UCA0TXIFG (0x000F) /* DMA channel 0 transfer select 15: UCA0TXIFG */
-#define DMA0TSEL__UCA1RXIFG (0x0010) /* DMA channel 0 transfer select 16: UCA1RXIFG */
-#define DMA0TSEL__UCA1TXIFG (0x0011) /* DMA channel 0 transfer select 17: UCA1TXIFG */
-#define DMA0TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 0 transfer select 18: UCB0RXIFG0 */
-#define DMA0TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 0 transfer select 19: UCB0TXIFG0 */
-#define DMA0TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 0 transfer select 20: UCB0RXIFG1 */
-#define DMA0TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 0 transfer select 21: UCB0TXIFG1 */
-#define DMA0TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 0 transfer select 22: UCB0RXIFG2 */
-#define DMA0TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 0 transfer select 23: UCB0TXIFG2 */
-#define DMA0TSEL__UCB0RXIFG3 (0x0018) /* DMA channel 0 transfer select 24: UCB0RXIFG3 */
-#define DMA0TSEL__UCB0TXIFG3 (0x0019) /* DMA channel 0 transfer select 25: UCB0TXIFG3 */
-#define DMA0TSEL__ADC12IFG (0x001A) /* DMA channel 0 transfer select 26: ADC12IFG */
-#define DMA0TSEL__RES27 (0x001B) /* DMA channel 0 transfer select 27: RES27 */
-#define DMA0TSEL__RES28 (0x001C) /* DMA channel 0 transfer select 28: RES28 */
-#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: MPY */
-#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
-#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA1TSEL__DMAREQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
-#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: TA0CCR0 */
-#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: TA0CCR2 */
-#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: TA1CCR0 */
-#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: TA1CCR2 */
-#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: TA2CCR0 */
-#define DMA1TSEL__TA3CCR0 (0x0600) /* DMA channel 1 transfer select 6: TA3CCR0 */
-#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TB0CCR0 */
-#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TB0CCR2 */
-#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: RES9 */
-#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: RES10 */
-#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: RES11 */
-#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: RES12 */
-#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: RES13 */
-#define DMA1TSEL__UCA0RXIFG (0x0E00) /* DMA channel 1 transfer select 14: UCA0RXIFG */
-#define DMA1TSEL__UCA0TXIFG (0x0F00) /* DMA channel 1 transfer select 15: UCA0TXIFG */
-#define DMA1TSEL__UCA1RXIFG (0x1000) /* DMA channel 1 transfer select 16: UCA1RXIFG */
-#define DMA1TSEL__UCA1TXIFG (0x1100) /* DMA channel 1 transfer select 17: UCA1TXIFG */
-#define DMA1TSEL__UCB0RXIFG0 (0x1200) /* DMA channel 1 transfer select 18: UCB0RXIFG0 */
-#define DMA1TSEL__UCB0TXIFG0 (0x1300) /* DMA channel 1 transfer select 19: UCB0TXIFG0 */
-#define DMA1TSEL__UCB0RXIFG1 (0x1400) /* DMA channel 1 transfer select 20: UCB0RXIFG1 */
-#define DMA1TSEL__UCB0TXIFG1 (0x1500) /* DMA channel 1 transfer select 21: UCB0TXIFG1 */
-#define DMA1TSEL__UCB0RXIFG2 (0x1600) /* DMA channel 1 transfer select 22: UCB0RXIFG2 */
-#define DMA1TSEL__UCB0TXIFG2 (0x1700) /* DMA channel 1 transfer select 23: UCB0TXIFG2 */
-#define DMA1TSEL__UCB0RXIFG3 (0x1800) /* DMA channel 1 transfer select 24: UCB0RXIFG3 */
-#define DMA1TSEL__UCB0TXIFG3 (0x1900) /* DMA channel 1 transfer select 25: UCB0TXIFG3 */
-#define DMA1TSEL__ADC12IFG (0x1A00) /* DMA channel 1 transfer select 26: ADC12IFG */
-#define DMA1TSEL__RES27 (0x1B00) /* DMA channel 1 transfer select 27: RES27 */
-#define DMA1TSEL__RES28 (0x1C00) /* DMA channel 1 transfer select 28: RES28 */
-#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: MPY */
-#define DMA1TSEL__DMA2IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA2IFG */
-#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
-
-#define DMA2TSEL__DMAREQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
-#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: TA0CCR0 */
-#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: TA0CCR2 */
-#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: TA1CCR0 */
-#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: TA1CCR2 */
-#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: TA2CCR0 */
-#define DMA2TSEL__TA3CCR0 (0x0006) /* DMA channel 2 transfer select 6: TA3CCR0 */
-#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TB0CCR0 */
-#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TB0CCR2 */
-#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: RES9 */
-#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: RES10 */
-#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: RES11 */
-#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: RES12 */
-#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: RES13 */
-#define DMA2TSEL__UCA0RXIFG (0x000E) /* DMA channel 2 transfer select 14: UCA0RXIFG */
-#define DMA2TSEL__UCA0TXIFG (0x000F) /* DMA channel 2 transfer select 15: UCA0TXIFG */
-#define DMA2TSEL__UCA1RXIFG (0x0010) /* DMA channel 2 transfer select 16: UCA1RXIFG */
-#define DMA2TSEL__UCA1TXIFG (0x0011) /* DMA channel 2 transfer select 17: UCA1TXIFG */
-#define DMA2TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 2 transfer select 18: UCB0RXIFG0 */
-#define DMA2TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 2 transfer select 19: UCB0TXIFG0 */
-#define DMA2TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 2 transfer select 20: UCB0RXIFG1 */
-#define DMA2TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 2 transfer select 21: UCB0TXIFG1 */
-#define DMA2TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 2 transfer select 22: UCB0RXIFG2 */
-#define DMA2TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 2 transfer select 23: UCB0TXIFG2 */
-#define DMA2TSEL__UCB0RXIFG3 (0x0018) /* DMA channel 2 transfer select 24: UCB0RXIFG3 */
-#define DMA2TSEL__UCB0TXIFG3 (0x0019) /* DMA channel 2 transfer select 25: UCB0TXIFG3 */
-#define DMA2TSEL__ADC12IFG (0x001A) /* DMA channel 2 transfer select 26: ADC12IFG */
-#define DMA2TSEL__RES27 (0x001B) /* DMA channel 2 transfer select 27: RES27 */
-#define DMA2TSEL__RES28 (0x001C) /* DMA channel 2 transfer select 28: RES28 */
-#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: MPY */
-#define DMA2TSEL__DMA2IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA2IFG */
-#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
-
-/*************************************************************
-* FRAM Memory
-*************************************************************/
-
-#define FRCTL0 0x0140 /* FRAM Controller Control 0 */
-#define GCCTL0 0x0144 /* General Control 0 */
-#define GCCTL1 0x0146 /* General Control 1 */
-
-#define FRCTLPW (0xA500) /* FRAM password for write */
-#define FRPW (0x9600) /* FRAM password returned by read */
-#define FWPW (0xA500) /* FRAM password for write */
-#define FXPW (0x3300) /* for use with XOR instruction */
-
-/* FRCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-#define NWAITS0 (0x0010) /* FRAM Wait state control Bit: 0 */
-#define NWAITS1 (0x0020) /* FRAM Wait state control Bit: 1 */
-#define NWAITS2 (0x0040) /* FRAM Wait state control Bit: 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-
-/* FRCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-//#define RESERVED (0x0002) /* RESERVED */
-//#define RESERVED (0x0004) /* RESERVED */
-#define NWAITS0_L (0x0010) /* FRAM Wait state control Bit: 0 */
-#define NWAITS1_L (0x0020) /* FRAM Wait state control Bit: 1 */
-#define NWAITS2_L (0x0040) /* FRAM Wait state control Bit: 2 */
-//#define RESERVED (0x0080) /* RESERVED */
-
-
-#define NWAITS_0 (0x0000) /* FRAM Wait state control: 0 */
-#define NWAITS_1 (0x0010) /* FRAM Wait state control: 1 */
-#define NWAITS_2 (0x0020) /* FRAM Wait state control: 2 */
-#define NWAITS_3 (0x0030) /* FRAM Wait state control: 3 */
-#define NWAITS_4 (0x0040) /* FRAM Wait state control: 4 */
-#define NWAITS_5 (0x0050) /* FRAM Wait state control: 5 */
-#define NWAITS_6 (0x0060) /* FRAM Wait state control: 6 */
-#define NWAITS_7 (0x0070) /* FRAM Wait state control: 7 */
-
-/* Legacy Defines */
-#define NACCESS0 (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */
-#define NACCESS1 (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */
-#define NACCESS2 (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */
-#define NACCESS_0 (0x0000) /* FRAM Wait state Generator Access Time control: 0 */
-#define NACCESS_1 (0x0010) /* FRAM Wait state Generator Access Time control: 1 */
-#define NACCESS_2 (0x0020) /* FRAM Wait state Generator Access Time control: 2 */
-#define NACCESS_3 (0x0030) /* FRAM Wait state Generator Access Time control: 3 */
-#define NACCESS_4 (0x0040) /* FRAM Wait state Generator Access Time control: 4 */
-#define NACCESS_5 (0x0050) /* FRAM Wait state Generator Access Time control: 5 */
-#define NACCESS_6 (0x0060) /* FRAM Wait state Generator Access Time control: 6 */
-#define NACCESS_7 (0x0070) /* FRAM Wait state Generator Access Time control: 7 */
-
-
-/* GCCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-#define FRLPMPWR (0x0002) /* FRAM Enable FRAM auto power up after LPM */
-#define FRPWR (0x0004) /* FRAM Power Control */
-#define ACCTEIE (0x0008) /* RESERVED */
-//#define RESERVED (0x0010) /* RESERVED */
-#define CBDIE (0x0020) /* Enable NMI event if correctable bit error detected */
-#define UBDIE (0x0040) /* Enable NMI event if uncorrectable bit error detected */
-#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
-
-/* GCCTL0 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-#define FRLPMPWR_L (0x0002) /* FRAM Enable FRAM auto power up after LPM */
-#define FRPWR_L (0x0004) /* FRAM Power Control */
-#define ACCTEIE_L (0x0008) /* RESERVED */
-//#define RESERVED (0x0010) /* RESERVED */
-#define CBDIE_L (0x0020) /* Enable NMI event if correctable bit error detected */
-#define UBDIE_L (0x0040) /* Enable NMI event if uncorrectable bit error detected */
-#define UBDRSTEN_L (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
-
-
-/* GCCTL1 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-#define CBDIFG (0x0002) /* FRAM correctable bit error flag */
-#define UBDIFG (0x0004) /* FRAM uncorrectable bit error flag */
-#define ACCTEIFG (0x0008) /* Access time error flag */
-
-/* GCCTL1 Control Bits */
-//#define RESERVED (0x0001) /* RESERVED */
-#define CBDIFG_L (0x0002) /* FRAM correctable bit error flag */
-#define UBDIFG_L (0x0004) /* FRAM uncorrectable bit error flag */
-#define ACCTEIFG_L (0x0008) /* Access time error flag */
-
-
-/************************************************************
-* Memory Protection Unit
-************************************************************/
-
-#define MPUCTL0 0x05A0 /* MPU Control Register 0 */
-#define MPUCTL1 0x05A2 /* MPU Control Register 1 */
-#define MPUSEGB2 0x05A4 /* MPU Segmentation Border 2 Register */
-#define MPUSEGB1 0x05A6 /* MPU Segmentation Border 1 Register */
-#define MPUSAM 0x05A8 /* MPU Access Management Register */
-#define MPUIPC0 0x05AA /* MPU IP Control 0 Register */
-#define MPUIPSEGB2 0x05AC /* MPU IP Segment Border 2 Register */
-#define MPUIPSEGB1 0x05AE /* MPU IP Segment Border 1 Register */
-
-/* MPUCTL0 Control Bits */
-#define MPUENA (0x0001) /* MPU Enable */
-#define MPULOCK (0x0002) /* MPU Lock */
-#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */
-
-/* MPUCTL0 Control Bits */
-#define MPUENA_L (0x0001) /* MPU Enable */
-#define MPULOCK_L (0x0002) /* MPU Lock */
-#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */
-
-#define MPUPW (0xA500) /* MPU Access Password */
-#define MPUPW_H (0xA5) /* MPU Access Password */
-
-/* MPUCTL1 Control Bits */
-#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
-#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
-#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
-#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */
-#define MPUSEGIPIFG (0x0010) /* MPU IP Memory Segment violation interupt flag */
-
-/* MPUCTL1 Control Bits */
-#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
-#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
-#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
-#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */
-#define MPUSEGIPIFG_L (0x0010) /* MPU IP Memory Segment violation interupt flag */
-
-
-/* MPUSEGB2 Control Bits */
-
-/* MPUSEGB2 Control Bits */
-
-/* MPUSEGB2 Control Bits */
-
-/* MPUSEGB1 Control Bits */
-
-/* MPUSEGB1 Control Bits */
-
-/* MPUSEGB1 Control Bits */
-
-/* MPUSAM Control Bits */
-#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */
-#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */
-#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */
-#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */
-#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */
-#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */
-#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */
-#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */
-#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */
-#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */
-#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */
-#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */
-#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */
-#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */
-#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */
-#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */
-
-/* MPUSAM Control Bits */
-#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */
-#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */
-#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */
-#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */
-#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */
-#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */
-#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */
-#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */
-
-/* MPUSAM Control Bits */
-#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */
-#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */
-#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */
-#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */
-#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */
-#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */
-#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */
-#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */
-
-/* MPUIPC0 Control Bits */
-#define MPUIPVS (0x0020) /* MPU MPU IP protection segment Violation Select */
-#define MPUIPENA (0x0040) /* MPU MPU IP Protection Enable */
-#define MPUIPLOCK (0x0080) /* MPU IP Protection Lock */
-
-/* MPUIPC0 Control Bits */
-#define MPUIPVS_L (0x0020) /* MPU MPU IP protection segment Violation Select */
-#define MPUIPENA_L (0x0040) /* MPU MPU IP Protection Enable */
-#define MPUIPLOCK_L (0x0080) /* MPU IP Protection Lock */
-
-
-/* MPUIPSEGB2 Control Bits */
-
-/* MPUIPSEGB2 Control Bits */
-
-/* MPUIPSEGB2 Control Bits */
-
-/* MPUIPSEGB1 Control Bits */
-
-/* MPUIPSEGB1 Control Bits */
-
-/* MPUIPSEGB1 Control Bits */
-
-/************************************************************
-* HARDWARE MULTIPLIER 32Bit
-************************************************************/
-
-#define MPY 0x04C0 /* Multiply Unsigned/Operand 1 */
-#define MPYS 0x04C2 /* Multiply Signed/Operand 1 */
-#define MAC 0x04C4 /* Multiply Unsigned and Accumulate/Operand 1 */
-#define MACS 0x04C6 /* Multiply Signed and Accumulate/Operand 1 */
-#define OP2 0x04C8 /* Operand 2 */
-#define RESLO 0x04CA /* Result Low Word */
-#define RESHI 0x04CC /* Result High Word */
-#define SUMEXT 0x04CE /* Sum Extend */
-
-#define MPY32L 0x04D0 /* 32-bit operand 1 - multiply - low word */
-#define MPY32H 0x04D2 /* 32-bit operand 1 - multiply - high word */
-#define MPYS32L 0x04D4 /* 32-bit operand 1 - signed multiply - low word */
-#define MPYS32H 0x04D6 /* 32-bit operand 1 - signed multiply - high word */
-#define MAC32L 0x04D8 /* 32-bit operand 1 - multiply accumulate - low word */
-#define MAC32H 0x04DA /* 32-bit operand 1 - multiply accumulate - high word */
-#define MACS32L 0x04DC /* 32-bit operand 1 - signed multiply accumulate - low word */
-#define MACS32H 0x04DE /* 32-bit operand 1 - signed multiply accumulate - high word */
-#define OP2L 0x04E0 /* 32-bit operand 2 - low word */
-#define OP2H 0x04E2 /* 32-bit operand 2 - high word */
-#define RES0 0x04E4 /* 32x32-bit result 0 - least significant word */
-#define RES1 0x04E6 /* 32x32-bit result 1 */
-#define RES2 0x04E8 /* 32x32-bit result 2 */
-#define RES3 0x04EA /* 32x32-bit result 3 - most significant word */
-#define MPY32CTL0 0x04EC /* MPY32 Control Register 0 */
-
-#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
-#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
-#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
-#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
-#define OP2_B OP2_L /* Operand 2 (Byte Access) */
-#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
-#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
-#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
-#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
-#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
-#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
-#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
-#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
-#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
-#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
-
-
-/* MPY32CTL0 Control Bits */
-#define MPYC (0x0001) /* Carry of the multiplier */
-//#define RESERVED (0x0002) /* Reserved */
-#define MPYFRAC (0x0004) /* Fractional mode */
-#define MPYSAT (0x0008) /* Saturation mode */
-#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
-#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
-#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
-#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
-#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
-#define MPYDLY32 (0x0200) /* Delayed write mode */
-
-/* MPY32CTL0 Control Bits */
-#define MPYC_L (0x0001) /* Carry of the multiplier */
-//#define RESERVED (0x0002) /* Reserved */
-#define MPYFRAC_L (0x0004) /* Fractional mode */
-#define MPYSAT_L (0x0008) /* Saturation mode */
-#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
-#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
-#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
-#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
-
-/* MPY32CTL0 Control Bits */
-//#define RESERVED (0x0002) /* Reserved */
-#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
-#define MPYDLY32_H (0x0002) /* Delayed write mode */
-
-#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
-#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
-#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
-#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
-#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
-#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
-#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
-#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
-
-/************************************************************
-* PMM - Power Management System for FRAM
-************************************************************/
-
-#define PMMCTL0 0x0120 /* PMM Control 0 */
-#define PMMIFG 0x012A /* PMM Interrupt Flag */
-#define PM5CTL0 0x0130 /* PMM Power Mode 5 Control Register 0 */
-
-#define PMMPW (0xA500) /* PMM Register Write Password */
-#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
-
-/* PMMCTL0 Control Bits */
-#define PMMSWBOR (0x0004) /* PMM Software BOR */
-#define PMMSWPOR (0x0008) /* PMM Software POR */
-#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
-#define SVSHE (0x0040) /* SVS high side enable */
-#define PMMLPRST (0x0080) /* PMM Low-Power Reset Enable */
-
-/* PMMCTL0 Control Bits */
-#define PMMSWBOR_L (0x0004) /* PMM Software BOR */
-#define PMMSWPOR_L (0x0008) /* PMM Software POR */
-#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
-#define SVSHE_L (0x0040) /* SVS high side enable */
-#define PMMLPRST_L (0x0080) /* PMM Low-Power Reset Enable */
-
-
-/* PMMIFG Control Bits */
-#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
-#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
-#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
-#define SVSHIFG (0x2000) /* SVS low side interrupt flag */
-#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
-
-/* PMMIFG Control Bits */
-#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
-#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
-#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
-#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */
-#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
-
-
-/* PM5CTL0 Power Mode 5 Control Bits */
-#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
-
-/* PM5CTL0 Power Mode 5 Control Bits */
-#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
-
-
-
-/************************************************************
-* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
-************************************************************/
-
-#define PAIN 0x0200 /* Port A Input */
-#define PAOUT 0x0202 /* Port A Output */
-#define PADIR 0x0204 /* Port A Direction */
-#define PAREN 0x0206 /* Port A Resistor Enable */
-#define PASEL0 0x020A /* Port A Selection 0 */
-#define PASEL0_H (PASEL0)
-#define PASEL1 0x020C /* Port A Selection 1 */
-#define PASEL1_H (PASEL1+1)
-#define PASELC 0x0216 /* Port A Complement Selection */
-#define PAIES 0x0218 /* Port A Interrupt Edge Select */
-#define PAIE 0x021A /* Port A Interrupt Enable */
-#define PAIFG 0x021C /* Port A Interrupt Flag */
-
-#define P1IV 0x020E /* Port 1 Interrupt Vector Word */
-#define P2IV 0x021E /* Port 2 Interrupt Vector Word */
-#define P1IN (PAIN_L) /* Port 1 Input */
-#define P1OUT (PAOUT_L) /* Port 1 Output */
-#define P1DIR (PADIR_L) /* Port 1 Direction */
-#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
-#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */
-#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */
-#define P1SELC (PASELC_L) /* Port 1 Complement Selection */
-#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
-#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
-#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
-
-//Definitions for P1IV
-#define P1IV_NONE (0x0000) /* No Interrupt pending */
-#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
-#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
-#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
-#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
-#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
-#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
-#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
-#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
-
-
-#define P2IN (PAIN_H) /* Port 2 Input */
-#define P2OUT (PAOUT_H) /* Port 2 Output */
-#define P2DIR (PADIR_H) /* Port 2 Direction */
-#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
-#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */
-#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */
-#define P2SELC (PASELC_H) /* Port 2 Complement Selection */
-#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
-#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
-#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
-
-//Definitions for P2IV
-#define P2IV_NONE (0x0000) /* No Interrupt pending */
-#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
-#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
-#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
-#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
-#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
-#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
-#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
-#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
-
-
-
-/************************************************************
-* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
-************************************************************/
-
-#define PBIN 0x0220 /* Port B Input */
-#define PBOUT 0x0222 /* Port B Output */
-#define PBDIR 0x0224 /* Port B Direction */
-#define PBREN 0x0226 /* Port B Resistor Enable */
-#define PBSEL0 0x022A /* Port B Selection 0 */
-#define PBSEL1 0x022C /* Port B Selection 1 */
-#define PBSELC 0x0236 /* Port B Complement Selection */
-#define PBIES 0x0238 /* Port B Interrupt Edge Select */
-#define PBIE 0x023A /* Port B Interrupt Enable */
-#define PBIFG 0x023C /* Port B Interrupt Flag */
-
-#define P3IV 0x022E /* Port 3 Interrupt Vector Word */
-#define P4IV 0x023E /* Port 4 Interrupt Vector Word */
-#define P3IN (PBIN_L) /* Port 3 Input */
-#define P3OUT (PBOUT_L) /* Port 3 Output */
-#define P3DIR (PBDIR_L) /* Port 3 Direction */
-#define P3REN (PBREN_L) /* Port 3 Resistor Enable */
-#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */
-#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */
-#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */
-#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
-#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
-#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
-
-//Definitions for P3IV
-#define P3IV_NONE (0x0000) /* No Interrupt pending */
-#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */
-#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */
-#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */
-#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */
-#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */
-#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */
-#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */
-#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */
-
-
-#define P4IN (PBIN_H) /* Port 4 Input */
-#define P4OUT (PBOUT_H) /* Port 4 Output */
-#define P4DIR (PBDIR_H) /* Port 4 Direction */
-#define P4REN (PBREN_H) /* Port 4 Resistor Enable */
-#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */
-#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */
-#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */
-#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
-#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
-#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
-
-//Definitions for P4IV
-#define P4IV_NONE (0x0000) /* No Interrupt pending */
-#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */
-#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */
-#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */
-#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */
-#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */
-#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */
-#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */
-#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */
-
-
-
-/************************************************************
-* DIGITAL I/O PortJ Pull up / Pull down Resistors
-************************************************************/
-
-#define PJIN 0x0320 /* Port J Input */
-#define PJOUT 0x0322 /* Port J Output */
-#define PJDIR 0x0324 /* Port J Direction */
-#define PJREN 0x0326 /* Port J Resistor Enable */
-#define PJSEL0 0x032A /* Port J Selection 0 */
-#define PJSEL1 0x032C /* Port J Selection 1 */
-#define PJSELC 0x0336 /* Port J Complement Selection */
-
-/************************************************************
-* Shared Reference
-************************************************************/
-
-#define REFCTL0 0x01B0 /* REF Shared Reference control register 0 */
-
-/* REFCTL0 Control Bits */
-#define REFON (0x0001) /* REF Reference On */
-#define REFOUT (0x0002) /* REF Reference output Buffer On */
-//#define RESERVED (0x0004) /* Reserved */
-#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
-#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
-#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
-#define REFGENOT (0x0040) /* REF Reference generator one-time trigger */
-#define REFBGOT (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */
-#define REFGENACT (0x0100) /* REF Reference generator active */
-#define REFBGACT (0x0200) /* REF Reference bandgap active */
-#define REFGENBUSY (0x0400) /* REF Reference generator busy */
-#define BGMODE (0x0800) /* REF Bandgap mode */
-#define REFGENRDY (0x1000) /* REF Reference generator ready */
-#define REFBGRDY (0x2000) /* REF Reference bandgap ready */
-//#define RESERVED (0x4000) /* Reserved */
-//#define RESERVED (0x8000) /* Reserved */
-
-/* REFCTL0 Control Bits */
-#define REFON_L (0x0001) /* REF Reference On */
-#define REFOUT_L (0x0002) /* REF Reference output Buffer On */
-//#define RESERVED (0x0004) /* Reserved */
-#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
-#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
-#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
-#define REFGENOT_L (0x0040) /* REF Reference generator one-time trigger */
-#define REFBGOT_L (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */
-//#define RESERVED (0x4000) /* Reserved */
-//#define RESERVED (0x8000) /* Reserved */
-
-/* REFCTL0 Control Bits */
-//#define RESERVED (0x0004) /* Reserved */
-#define REFGENACT_H (0x0001) /* REF Reference generator active */
-#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
-#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
-#define BGMODE_H (0x0008) /* REF Bandgap mode */
-#define REFGENRDY_H (0x0010) /* REF Reference generator ready */
-#define REFBGRDY_H (0x0020) /* REF Reference bandgap ready */
-//#define RESERVED (0x4000) /* Reserved */
-//#define RESERVED (0x8000) /* Reserved */
-
-#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.2V */
-#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
-#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
-#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
-
-/************************************************************
-* Real Time Clock
-************************************************************/
-
-#define RTCCTL01 0x04A0 /* Real Timer Control 0/1 */
-#define RTCCTL23 0x04A2 /* Real Timer Control 2/3 */
-#define RTCPS0CTL 0x04A8 /* Real Timer Prescale Timer 0 Control */
-#define RTCPS1CTL 0x04AA /* Real Timer Prescale Timer 1 Control */
-#define RTCPS 0x04AC /* Real Timer Prescale Timer Control */
-#define RTCIV 0x04AE /* Real Time Clock Interrupt Vector */
-#define RTCTIM0 0x04B0 /* Real Time Clock Time 0 */
-#define RTCTIM1 0x04B2 /* Real Time Clock Time 1 */
-#define RTCDATE 0x04B4 /* Real Time Clock Date */
-#define RTCYEAR 0x04B6 /* Real Time Clock Year */
-#define RTCAMINHR 0x04B8 /* Real Time Clock Alarm Min/Hour */
-#define RTCADOWDAY 0x04BA /* Real Time Clock Alarm day of week/day */
-#define BIN2BCD 0x04BC /* Real Time Binary-to-BCD conversion register */
-#define BCD2BIN 0x04BE /* Real Time BCD-to-binary conversion register */
-
-#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
-#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
-#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
-#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
-#define RTCNT12 RTCTIM0
-#define RTCNT34 RTCTIM1
-#define RTCNT1 RTCTIM0_L
-#define RTCNT2 RTCTIM0_H
-#define RTCNT3 RTCTIM1_L
-#define RTCNT4 RTCTIM1_H
-#define RTCSEC RTCTIM0_L
-#define RTCMIN RTCTIM0_H
-#define RTCHOUR RTCTIM1_L
-#define RTCDOW RTCTIM1_H
-#define RTCDAY RTCDATE_L
-#define RTCMON RTCDATE_H
-#define RTCYEARL RTCYEAR_L
-#define RTCYEARH RTCYEAR_H
-#define RT0PS RTCPS_L
-#define RT1PS RTCPS_H
-#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
-#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
-#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
-#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
-
-/* RTCCTL01 Control Bits */
-#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
-#define RTCHOLD (0x4000) /* RTC Hold */
-//#define RESERVED (0x2000) /* RESERVED */
-#define RTCRDY (0x1000) /* RTC Ready */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-#define RTCTEV1 (0x0200) /* RTC Time Event 1 */
-#define RTCTEV0 (0x0100) /* RTC Time Event 0 */
-#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
-#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
-#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
-#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
-#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
-#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
-#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
-#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
-
-/* RTCCTL01 Control Bits */
-//#define RESERVED (0x2000) /* RESERVED */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
-#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
-#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
-#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
-#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
-#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
-#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
-#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
-
-/* RTCCTL01 Control Bits */
-#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
-#define RTCHOLD_H (0x0040) /* RTC Hold */
-//#define RESERVED (0x2000) /* RESERVED */
-#define RTCRDY_H (0x0010) /* RTC Ready */
-//#define RESERVED (0x0800) /* RESERVED */
-//#define RESERVED (0x0400) /* RESERVED */
-#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
-#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
-
-#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
-#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
-#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
-#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
-#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
-#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
-#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
-#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
-
-/* RTCCTL23 Control Bits */
-#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
-#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
-#define RTCCALS (0x0080) /* RTC Calibration Sign */
-//#define Reserved (0x0040)
-#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
-#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
-#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
-#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
-#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
-#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
-
-/* RTCCTL23 Control Bits */
-#define RTCCALS_L (0x0080) /* RTC Calibration Sign */
-//#define Reserved (0x0040)
-#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
-#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
-#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
-#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
-#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
-#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
-
-/* RTCCTL23 Control Bits */
-#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
-#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
-//#define Reserved (0x0040)
-
-#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
-#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
-#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
-#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
-
-
-#define RTCAE (0x80) /* Real Time Clock Alarm enable */
-
-
-
-
-/* RTCPS0CTL Control Bits */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
-#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
-#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
-#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
-#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
-
-/* RTCPS0CTL Control Bits */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
-#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
-#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
-#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
-#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
-
-
-#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
-#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
-#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
-#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
-#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
-#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
-#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
-#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
-
-#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
-#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
-#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
-#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
-#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
-#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
-#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
-#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
-
-
-/* RTCPS1CTL Control Bits */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
-#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
-#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
-#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
-#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
-
-/* RTCPS1CTL Control Bits */
-//#define Reserved (0x0080)
-//#define Reserved (0x0040)
-//#define Reserved (0x0020)
-#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
-#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
-#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
-#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
-#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
-
-
-#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
-#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
-#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
-#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
-#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
-#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
-#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
-#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
-
-#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
-#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
-#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
-#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
-#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
-#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
-#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
-#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
-
-
-/* RTC Definitions */
-#define RTCIV_NONE (0x0000) /* No Interrupt pending */
-#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
-#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
-#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
-#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
-#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
-#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */
-
-/* Legacy Definitions */
-#define RTC_NONE (0x0000) /* No Interrupt pending */
-#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
-#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
-#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
-#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
-#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
-#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */
-
-/************************************************************
-* SFR - Special Function Register Module
-************************************************************/
-
-#define SFRIE1 0x0100 /* Interrupt Enable 1 */
-
-/* SFRIE1 Control Bits */
-#define WDTIE (0x0001) /* WDT Interrupt Enable */
-#define OFIE (0x0002) /* Osc Fault Enable */
-//#define Reserved (0x0004)
-#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
-#define NMIIE (0x0010) /* NMI Interrupt Enable */
-#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
-#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
-
-#define WDTIE_L (0x0001) /* WDT Interrupt Enable */
-#define OFIE_L (0x0002) /* Osc Fault Enable */
-//#define Reserved (0x0004)
-#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
-#define NMIIE_L (0x0010) /* NMI Interrupt Enable */
-#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
-#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
-
-
-#define SFRIFG1 0x0102 /* Interrupt Flag 1 */
-/* SFRIFG1 Control Bits */
-#define WDTIFG (0x0001) /* WDT Interrupt Flag */
-#define OFIFG (0x0002) /* Osc Fault Flag */
-//#define Reserved (0x0004)
-#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
-#define NMIIFG (0x0010) /* NMI Interrupt Flag */
-//#define Reserved (0x0020)
-#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
-#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
-
-#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
-#define OFIFG_L (0x0002) /* Osc Fault Flag */
-//#define Reserved (0x0004)
-#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
-#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
-//#define Reserved (0x0020)
-#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
-#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
-
-
-#define SFRRPCR 0x0104 /* RESET Pin Control Register */
-/* SFRRPCR Control Bits */
-#define SYSNMI (0x0001) /* NMI select */
-#define SYSNMIIES (0x0002) /* NMI edge select */
-#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
-#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
-
-#define SYSNMI_L (0x0001) /* NMI select */
-#define SYSNMIIES_L (0x0002) /* NMI edge select */
-#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
-#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
-
-
-/************************************************************
-* SYS - System Module
-************************************************************/
-
-#define SYSCTL 0x0180 /* System control */
-#define SYSJMBC 0x0186 /* JTAG mailbox control */
-#define SYSJMBI0 0x0188 /* JTAG mailbox input 0 */
-#define SYSJMBI1 0x018A /* JTAG mailbox input 1 */
-#define SYSJMBO0 0x018C /* JTAG mailbox output 0 */
-#define SYSJMBO1 0x018E /* JTAG mailbox output 1 */
-
-#define SYSUNIV 0x019A /* User NMI vector generator */
-#define SYSSNIV 0x019C /* System NMI vector generator */
-#define SYSRSTIV 0x019E /* Reset vector generator */
-
-/* SYSCTL Control Bits */
-#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
-//#define RESERVED (0x0002) /* SYS - Reserved */
-#define SYSPMMPE (0x0004) /* SYS - PMM access protect */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
-#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-/* SYSCTL Control Bits */
-#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
-//#define RESERVED (0x0002) /* SYS - Reserved */
-#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
-//#define RESERVED (0x0008) /* SYS - Reserved */
-#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
-#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
-//#define RESERVED (0x0040) /* SYS - Reserved */
-//#define RESERVED (0x0080) /* SYS - Reserved */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-
-/* SYSJMBC Control Bits */
-#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
-#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
-#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
-#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
-#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
-#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-/* SYSJMBC Control Bits */
-#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
-#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
-#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
-#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
-#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
-//#define RESERVED (0x0020) /* SYS - Reserved */
-#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
-#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
-//#define RESERVED (0x0100) /* SYS - Reserved */
-//#define RESERVED (0x0200) /* SYS - Reserved */
-//#define RESERVED (0x0400) /* SYS - Reserved */
-//#define RESERVED (0x0800) /* SYS - Reserved */
-//#define RESERVED (0x1000) /* SYS - Reserved */
-//#define RESERVED (0x2000) /* SYS - Reserved */
-//#define RESERVED (0x4000) /* SYS - Reserved */
-//#define RESERVED (0x8000) /* SYS - Reserved */
-
-
-
-
-
-
-
-
-/* SYSUNIV Definitions */
-#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */
-#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */
-#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */
-
-/* SYSSNIV Definitions */
-#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */
-#define SYSSNIV_RES02 (0x0002) /* SYSSNIV : Reserved */
-#define SYSSNIV_UBDIFG (0x0004) /* SYSSNIV : FRAM Uncorrectable bit Error */
-#define SYSSNIV_RES06 (0x0006) /* SYSSNIV : Reserved */
-#define SYSSNIV_MPUSEGPIFG (0x0008) /* SYSSNIV : MPUSEGPIFG violation */
-#define SYSSNIV_MPUSEGIIFG (0x000A) /* SYSSNIV : MPUSEGIIFG violation */
-#define SYSSNIV_MPUSEG1IFG (0x000C) /* SYSSNIV : MPUSEG1IFG violation */
-#define SYSSNIV_MPUSEG2IFG (0x000E) /* SYSSNIV : MPUSEG2IFG violation */
-#define SYSSNIV_MPUSEG3IFG (0x0010) /* SYSSNIV : MPUSEG3IFG violation */
-#define SYSSNIV_VMAIFG (0x0012) /* SYSSNIV : VMAIFG */
-#define SYSSNIV_JMBINIFG (0x0014) /* SYSSNIV : JMBINIFG */
-#define SYSSNIV_JMBOUTIFG (0x0016) /* SYSSNIV : JMBOUTIFG */
-#define SYSSNIV_CBDIFG (0x0018) /* SYSSNIV : FRAM Correctable Bit error */
-
-/* SYSRSTIV Definitions */
-#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
-#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
-#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
-#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
-#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
-#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
-#define SYSRSTIV_RES0C (0x000C) /* SYSRSTIV : Reserved */
-#define SYSRSTIV_SVSHIFG (0x000E) /* SYSRSTIV : SVSHIFG */
-#define SYSRSTIV_RES10 (0x0010) /* SYSRSTIV : Reserved */
-#define SYSRSTIV_RES12 (0x0012) /* SYSRSTIV : Reserved */
-#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
-#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
-#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
-#define SYSRSTIV_FRCTLPW (0x001A) /* SYSRSTIV : FRAM Key violation */
-#define SYSRSTIV_UBDIFG (0x001C) /* SYSRSTIV : FRAM Uncorrectable bit Error */
-#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
-#define SYSRSTIV_PMMPW (0x0020) /* SYSRSTIV : PMM Password violation */
-#define SYSRSTIV_MPUPW (0x0022) /* SYSRSTIV : MPU Password violation */
-#define SYSRSTIV_CSPW (0x0024) /* SYSRSTIV : CS Password violation */
-#define SYSRSTIV_MPUSEGPIFG (0x0026) /* SYSRSTIV : MPUSEGPIFG violation */
-#define SYSRSTIV_MPUSEGIIFG (0x0028) /* SYSRSTIV : MPUSEGIIFG violation */
-#define SYSRSTIV_MPUSEG1IFG (0x002A) /* SYSRSTIV : MPUSEG1IFG violation */
-#define SYSRSTIV_MPUSEG2IFG (0x002C) /* SYSRSTIV : MPUSEG2IFG violation */
-#define SYSRSTIV_MPUSEG3IFG (0x002E) /* SYSRSTIV : MPUSEG3IFG violation */
-#define SYSRSTIV_ACCTEIFG (0x0030) /* SYSRSTIV : ACCTEIFG access time error */
-
-/************************************************************
-* Timer0_A3
-************************************************************/
-
-#define TA0CTL 0x0340 /* Timer0_A3 Control */
-#define TA0CCTL0 0x0342 /* Timer0_A3 Capture/Compare Control 0 */
-#define TA0CCTL1 0x0344 /* Timer0_A3 Capture/Compare Control 1 */
-#define TA0CCTL2 0x0346 /* Timer0_A3 Capture/Compare Control 2 */
-#define TA0R 0x0350 /* Timer0_A3 */
-#define TA0CCR0 0x0352 /* Timer0_A3 Capture/Compare 0 */
-#define TA0CCR1 0x0354 /* Timer0_A3 Capture/Compare 1 */
-#define TA0CCR2 0x0356 /* Timer0_A3 Capture/Compare 2 */
-#define TA0IV 0x036E /* Timer0_A3 Interrupt Vector Word */
-#define TA0EX0 0x0360 /* Timer0_A3 Expansion Register 0 */
-
-/* TAxCTL Control Bits */
-#define TASSEL1 (0x0200) /* Timer A clock source select 1 */
-#define TASSEL0 (0x0100) /* Timer A clock source select 0 */
-#define ID1 (0x0080) /* Timer A clock input divider 1 */
-#define ID0 (0x0040) /* Timer A clock input divider 0 */
-#define MC1 (0x0020) /* Timer A mode control 1 */
-#define MC0 (0x0010) /* Timer A mode control 0 */
-#define TACLR (0x0004) /* Timer A counter clear */
-#define TAIE (0x0002) /* Timer A counter interrupt enable */
-#define TAIFG (0x0001) /* Timer A counter interrupt flag */
-
-#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */
-#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
-#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */
-#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */
-#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */
-#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */
-#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */
-#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */
-#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */
-#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */
-#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */
-#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */
-#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */
-#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
-#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */
-#define MC__CONTINOUS (0x0020) /* Legacy define */
-#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */
-#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */
-#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */
-#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */
-#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */
-#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */
-#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */
-#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */
-#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */
-
-/* TAxCCTLx Control Bits */
-#define CM1 (0x8000) /* Capture mode 1 */
-#define CM0 (0x4000) /* Capture mode 0 */
-#define CCIS1 (0x2000) /* Capture input select 1 */
-#define CCIS0 (0x1000) /* Capture input select 0 */
-#define SCS (0x0800) /* Capture sychronize */
-#define SCCI (0x0400) /* Latched capture signal (read) */
-#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
-#define OUTMOD2 (0x0080) /* Output mode 2 */
-#define OUTMOD1 (0x0040) /* Output mode 1 */
-#define OUTMOD0 (0x0020) /* Output mode 0 */
-#define CCIE (0x0010) /* Capture/compare interrupt enable */
-#define CCI (0x0008) /* Capture input signal (read) */
-#define OUT (0x0004) /* PWM Output signal if output mode 0 */
-#define COV (0x0002) /* Capture/compare overflow flag */
-#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-
-#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */
-#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */
-#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */
-#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */
-#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */
-#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */
-#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */
-#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */
-#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */
-#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */
-#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */
-#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */
-#define CM_0 (0x0000) /* Capture mode: 0 - disabled */
-#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */
-#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */
-#define CM_3 (0xC000) /* Capture mode: 1 - both edges */
-
-
-/* TAxEX0 Control Bits */
-#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
-#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
-#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
-
-#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */
-#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */
-#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */
-#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */
-#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */
-#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */
-#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */
-#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */
-
-/* T0A3IV Definitions */
-#define TA0IV_NONE (0x0000) /* No Interrupt pending */
-#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
-#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
-#define TA0IV_3 (0x0006) /* Reserved */
-#define TA0IV_4 (0x0008) /* Reserved */
-#define TA0IV_5 (0x000A) /* Reserved */
-#define TA0IV_6 (0x000C) /* Reserved */
-#define TA0IV_TAIFG (0x000E) /* TA0IFG */
-
-/* Legacy Defines */
-#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */
-#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */
-#define TA0IV_TA0IFG (0x000E) /* TA0IFG */
-
-/************************************************************
-* Timer1_A3
-************************************************************/
-
-#define TA1CTL 0x0380 /* Timer1_A3 Control */
-#define TA1CCTL0 0x0382 /* Timer1_A3 Capture/Compare Control 0 */
-#define TA1CCTL1 0x0384 /* Timer1_A3 Capture/Compare Control 1 */
-#define TA1CCTL2 0x0386 /* Timer1_A3 Capture/Compare Control 2 */
-#define TA1R 0x0390 /* Timer1_A3 */
-#define TA1CCR0 0x0392 /* Timer1_A3 Capture/Compare 0 */
-#define TA1CCR1 0x0394 /* Timer1_A3 Capture/Compare 1 */
-#define TA1CCR2 0x0396 /* Timer1_A3 Capture/Compare 2 */
-#define TA1IV 0x03AE /* Timer1_A3 Interrupt Vector Word */
-#define TA1EX0 0x03A0 /* Timer1_A3 Expansion Register 0 */
-
-/* Bits are already defined within the Timer0_Ax */
-
-/* TA1IV Definitions */
-#define TA1IV_NONE (0x0000) /* No Interrupt pending */
-#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
-#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
-#define TA1IV_3 (0x0006) /* Reserved */
-#define TA1IV_4 (0x0008) /* Reserved */
-#define TA1IV_5 (0x000A) /* Reserved */
-#define TA1IV_6 (0x000C) /* Reserved */
-#define TA1IV_TAIFG (0x000E) /* TA1IFG */
-
-/* Legacy Defines */
-#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */
-#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */
-#define TA1IV_TA1IFG (0x000E) /* TA1IFG */
-
-/************************************************************
-* Timer2_A2
-************************************************************/
-
-#define TA2CTL 0x0400 /* Timer2_A2 Control */
-#define TA2CCTL0 0x0402 /* Timer2_A2 Capture/Compare Control 0 */
-#define TA2CCTL1 0x0404 /* Timer2_A2 Capture/Compare Control 1 */
-#define TA2R 0x0410 /* Timer2_A2 */
-#define TA2CCR0 0x0412 /* Timer2_A2 Capture/Compare 0 */
-#define TA2CCR1 0x0414 /* Timer2_A2 Capture/Compare 1 */
-#define TA2IV 0x042E /* Timer2_A2 Interrupt Vector Word */
-#define TA2EX0 0x0420 /* Timer2_A2 Expansion Register 0 */
-
-/* Bits are already defined within the Timer0_Ax */
-
-/* TA2IV Definitions */
-#define TA2IV_NONE (0x0000) /* No Interrupt pending */
-#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */
-#define TA2IV_3 (0x0006) /* Reserved */
-#define TA2IV_4 (0x0008) /* Reserved */
-#define TA2IV_5 (0x000A) /* Reserved */
-#define TA2IV_6 (0x000C) /* Reserved */
-#define TA2IV_TAIFG (0x000E) /* TA2IFG */
-
-/* Legacy Defines */
-#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */
-#define TA2IV_TA2IFG (0x000E) /* TA2IFG */
-
-/************************************************************
-* Timer3_A2
-************************************************************/
-
-#define TA3CTL 0x0440 /* Timer3_A2 Control */
-#define TA3CCTL0 0x0442 /* Timer3_A2 Capture/Compare Control 0 */
-#define TA3CCTL1 0x0444 /* Timer3_A2 Capture/Compare Control 1 */
-#define TA3R 0x0450 /* Timer3_A2 */
-#define TA3CCR0 0x0452 /* Timer3_A2 Capture/Compare 0 */
-#define TA3CCR1 0x0454 /* Timer3_A2 Capture/Compare 1 */
-#define TA3IV 0x046E /* Timer3_A2 Interrupt Vector Word */
-#define TA3EX0 0x0460 /* Timer3_A2 Expansion Register 0 */
-
-/* Bits are already defined within the Timer0_Ax */
-
-/* TA3IV Definitions */
-#define TA3IV_NONE (0x0000) /* No Interrupt pending */
-#define TA3IV_TACCR1 (0x0002) /* TA3CCR1_CCIFG */
-#define TA3IV_3 (0x0006) /* Reserved */
-#define TA3IV_4 (0x0008) /* Reserved */
-#define TA3IV_5 (0x000A) /* Reserved */
-#define TA3IV_6 (0x000C) /* Reserved */
-#define TA3IV_TAIFG (0x000E) /* TA3IFG */
-
-/* Legacy Defines */
-#define TA3IV_TA3CCR1 (0x0002) /* TA3CCR1_CCIFG */
-#define TA3IV_TA3IFG (0x000E) /* TA3IFG */
-
-/************************************************************
-* Timer0_B7
-************************************************************/
-
-#define TB0CTL 0x03C0 /* Timer0_B7 Control */
-#define TB0CCTL0 0x03C2 /* Timer0_B7 Capture/Compare Control 0 */
-#define TB0CCTL1 0x03C4 /* Timer0_B7 Capture/Compare Control 1 */
-#define TB0CCTL2 0x03C6 /* Timer0_B7 Capture/Compare Control 2 */
-#define TB0CCTL3 0x03C8 /* Timer0_B7 Capture/Compare Control 3 */
-#define TB0CCTL4 0x03CA /* Timer0_B7 Capture/Compare Control 4 */
-#define TB0CCTL5 0x03CC /* Timer0_B7 Capture/Compare Control 5 */
-#define TB0CCTL6 0x03CE /* Timer0_B7 Capture/Compare Control 6 */
-#define TB0R 0x03D0 /* Timer0_B7 */
-#define TB0CCR0 0x03D2 /* Timer0_B7 Capture/Compare 0 */
-#define TB0CCR1 0x03D4 /* Timer0_B7 Capture/Compare 1 */
-#define TB0CCR2 0x03D6 /* Timer0_B7 Capture/Compare 2 */
-#define TB0CCR3 0x03D8 /* Timer0_B7 Capture/Compare 3 */
-#define TB0CCR4 0x03DA /* Timer0_B7 Capture/Compare 4 */
-#define TB0CCR5 0x03DC /* Timer0_B7 Capture/Compare 5 */
-#define TB0CCR6 0x03DE /* Timer0_B7 Capture/Compare 6 */
-#define TB0EX0 0x03E0 /* Timer0_B7 Expansion Register 0 */
-#define TB0IV 0x03EE /* Timer0_B7 Interrupt Vector Word */
-
-/* Legacy Type Definitions for TimerB */
-#define TBCTL TB0CTL /* Timer0_B7 Control */
-#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */
-#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */
-#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */
-#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */
-#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */
-#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */
-#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */
-#define TBR TB0R /* Timer0_B7 */
-#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */
-#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */
-#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */
-#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */
-#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */
-#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */
-#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */
-#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */
-#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */
-#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
-#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
-
-
-/* TBxCTL Control Bits */
-#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
-#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
-#define CNTL1 (0x1000) /* Counter lenght 1 */
-#define CNTL0 (0x0800) /* Counter lenght 0 */
-#define TBSSEL1 (0x0200) /* Clock source 1 */
-#define TBSSEL0 (0x0100) /* Clock source 0 */
-#define TBCLR (0x0004) /* Timer0_B7 counter clear */
-#define TBIE (0x0002) /* Timer0_B7 interrupt enable */
-#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */
-
-#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
-#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
-
-#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */
-#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */
-#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */
-#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */
-#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */
-#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */
-#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */
-#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */
-#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
-#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
-#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
-#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
-#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
-#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
-#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
-#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
-#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */
-#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
-#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */
-#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */
-#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */
-#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */
-#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */
-#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */
-#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */
-
-/* Additional Timer B Control Register bits are defined in Timer A */
-/* TBxCCTLx Control Bits */
-#define CLLD1 (0x0400) /* Compare latch load source 1 */
-#define CLLD0 (0x0200) /* Compare latch load source 0 */
-
-#define SLSHR1 (0x0400) /* Compare latch load source 1 */
-#define SLSHR0 (0x0200) /* Compare latch load source 0 */
-
-#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
-#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
-#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
-#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
-
-#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
-#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
-#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
-#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
-
-/* TBxEX0 Control Bits */
-#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */
-#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */
-#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */
-
-#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
-#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
-#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
-#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
-#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
-#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
-#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
-#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
-#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
-#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
-#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
-#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
-#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
-#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
-#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
-#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
-
-/* TB0IV Definitions */
-#define TB0IV_NONE (0x0000) /* No Interrupt pending */
-#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */
-#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */
-#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */
-#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */
-#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */
-#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */
-#define TB0IV_TBIFG (0x000E) /* TB0IFG */
-
-/* Legacy Defines */
-#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */
-#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */
-#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */
-#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */
-#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */
-#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */
-#define TB0IV_TB0IFG (0x000E) /* TB0IFG */
-
-
-/************************************************************
-* USCI A0
-************************************************************/
-
-#define UCA0CTLW0 0x05C0 /* USCI A0 Control Word Register 0 */
-#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
-#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
-#define UCA0CTLW1 0x05C2 /* USCI A0 Control Word Register 1 */
-#define UCA0BRW 0x05C6 /* USCI A0 Baud Word Rate 0 */
-#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
-#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
-#define UCA0MCTLW 0x05C8 /* USCI A0 Modulation Control */
-#define UCA0STATW 0x05CA /* USCI A0 Status Register */
-#define UCA0RXBUF 0x05CC /* USCI A0 Receive Buffer */
-#define UCA0TXBUF 0x05CE /* USCI A0 Transmit Buffer */
-#define UCA0ABCTL 0x05D0 /* USCI A0 LIN Control */
-#define UCA0IRCTL 0x05D2 /* USCI A0 IrDA Transmit Control */
-#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
-#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
-#define UCA0IE 0x05DA /* USCI A0 Interrupt Enable Register */
-#define UCA0IFG 0x05DC /* USCI A0 Interrupt Flags Register */
-#define UCA0IV 0x05DE /* USCI A0 Interrupt Vector Register */
-
-
-/************************************************************
-* USCI A1
-************************************************************/
-
-#define UCA1CTLW0 0x05E0 /* USCI A1 Control Word Register 0 */
-#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */
-#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */
-#define UCA1CTLW1 0x05E2 /* USCI A1 Control Word Register 1 */
-#define UCA1BRW 0x05E6 /* USCI A1 Baud Word Rate 0 */
-#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */
-#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */
-#define UCA1MCTLW 0x05E8 /* USCI A1 Modulation Control */
-#define UCA1STATW 0x05EA /* USCI A1 Status Register */
-#define UCA1RXBUF 0x05EC /* USCI A1 Receive Buffer */
-#define UCA1TXBUF 0x05EE /* USCI A1 Transmit Buffer */
-#define UCA1ABCTL 0x05F0 /* USCI A1 LIN Control */
-#define UCA1IRCTL 0x05F2 /* USCI A1 IrDA Transmit Control */
-#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */
-#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */
-#define UCA1IE 0x05FA /* USCI A1 Interrupt Enable Register */
-#define UCA1IFG 0x05FC /* USCI A1 Interrupt Flags Register */
-#define UCA1IV 0x05FE /* USCI A1 Interrupt Vector Register */
-
-
-/************************************************************
-* USCI B0
-************************************************************/
-
-
-#define UCB0CTLW0 0x0640 /* USCI B0 Control Word Register 0 */
-#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
-#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
-#define UCB0CTLW1 0x0642 /* USCI B0 Control Word Register 1 */
-#define UCB0BRW 0x0646 /* USCI B0 Baud Word Rate 0 */
-#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
-#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
-#define UCB0STATW 0x0648 /* USCI B0 Status Word Register */
-#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */
-#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */
-#define UCB0TBCNT 0x064A /* USCI B0 Byte Counter Threshold Register */
-#define UCB0RXBUF 0x064C /* USCI B0 Receive Buffer */
-#define UCB0TXBUF 0x064E /* USCI B0 Transmit Buffer */
-#define UCB0I2COA0 0x0654 /* USCI B0 I2C Own Address 0 */
-#define UCB0I2COA1 0x0656 /* USCI B0 I2C Own Address 1 */
-#define UCB0I2COA2 0x0658 /* USCI B0 I2C Own Address 2 */
-#define UCB0I2COA3 0x065A /* USCI B0 I2C Own Address 3 */
-#define UCB0ADDRX 0x065C /* USCI B0 Received Address Register */
-#define UCB0ADDMASK 0x065E /* USCI B0 Address Mask Register */
-#define UCB0I2CSA 0x0660 /* USCI B0 I2C Slave Address */
-#define UCB0IE 0x066A /* USCI B0 Interrupt Enable Register */
-#define UCB0IFG 0x066C /* USCI B0 Interrupt Flags Register */
-#define UCB0IV 0x066E /* USCI B0 Interrupt Vector Register */
-
-
-// UCAxCTLW0 UART-Mode Control Bits
-#define UCPEN (0x8000) /* Async. Mode: Parity enable */
-#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */
-#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */
-#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
-#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */
-#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */
-#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */
-#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
-#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */
-#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */
-#define UCRXEIE (0x0020) /* RX Error interrupt enable */
-#define UCBRKIE (0x0010) /* Break interrupt enable */
-#define UCDORM (0x0008) /* Dormant (Sleep) Mode */
-#define UCTXADDR (0x0004) /* Send next Data as Address */
-#define UCTXBRK (0x0002) /* Send next Data as Break */
-#define UCSWRST (0x0001) /* USCI Software Reset */
-
-// UCAxCTLW0 UART-Mode Control Bits
-#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */
-#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */
-#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */
-#define UCBRKIE_L (0x0010) /* Break interrupt enable */
-#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */
-#define UCTXADDR_L (0x0004) /* Send next Data as Address */
-#define UCTXBRK_L (0x0002) /* Send next Data as Break */
-#define UCSWRST_L (0x0001) /* USCI Software Reset */
-
-// UCAxCTLW0 UART-Mode Control Bits
-#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */
-#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */
-#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */
-#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
-#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */
-#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */
-#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */
-#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
-
-// UCxxCTLW0 SPI-Mode Control Bits
-#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */
-#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */
-#define UCMST (0x0800) /* Sync. Mode: Master Select */
-//#define res (0x0020) /* reserved */
-//#define res (0x0010) /* reserved */
-//#define res (0x0008) /* reserved */
-//#define res (0x0004) /* reserved */
-#define UCSTEM (0x0002) /* USCI STE Mode */
-
-// UCBxCTLW0 I2C-Mode Control Bits
-#define UCA10 (0x8000) /* 10-bit Address Mode */
-#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */
-#define UCMM (0x2000) /* Multi-Master Environment */
-//#define res (0x1000) /* reserved */
-//#define res (0x0100) /* reserved */
-#define UCTXACK (0x0020) /* Transmit ACK */
-#define UCTR (0x0010) /* Transmit/Receive Select/Flag */
-#define UCTXNACK (0x0008) /* Transmit NACK */
-#define UCTXSTP (0x0004) /* Transmit STOP */
-#define UCTXSTT (0x0002) /* Transmit START */
-
-// UCBxCTLW0 I2C-Mode Control Bits
-//#define res (0x1000) /* reserved */
-//#define res (0x0100) /* reserved */
-#define UCTXACK_L (0x0020) /* Transmit ACK */
-#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */
-#define UCTXNACK_L (0x0008) /* Transmit NACK */
-#define UCTXSTP_L (0x0004) /* Transmit STOP */
-#define UCTXSTT_L (0x0002) /* Transmit START */
-
-// UCBxCTLW0 I2C-Mode Control Bits
-#define UCA10_H (0x0080) /* 10-bit Address Mode */
-#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */
-#define UCMM_H (0x0020) /* Multi-Master Environment */
-//#define res (0x1000) /* reserved */
-//#define res (0x0100) /* reserved */
-
-#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */
-#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */
-#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */
-#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */
-
-#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */
-#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */
-#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */
-#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */
-#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */
-#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */
-#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */
-
-
-// UCAxCTLW1 UART-Mode Control Bits
-#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */
-#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */
-
-// UCAxCTLW1 UART-Mode Control Bits
-#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */
-#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */
-
-
-// UCBxCTLW1 I2C-Mode Control Bits
-#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */
-#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */
-#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */
-#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */
-#define UCSWACK (0x0010) /* USCI Software controlled ACK */
-#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
-#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
-
-// UCBxCTLW1 I2C-Mode Control Bits
-#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */
-#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */
-#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */
-#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */
-#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
-#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
-
-// UCBxCTLW1 I2C-Mode Control Bits
-#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */
-
-#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */
-#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */
-#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */
-#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */
-
-#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */
-#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */
-#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */
-#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */
-
-#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */
-#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */
-#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */
-#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */
-
-
-/* UCAxMCTLW Control Bits */
-#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */
-#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */
-#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */
-#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */
-#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */
-#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */
-#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */
-#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */
-#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */
-#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */
-#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */
-#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */
-#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */
-
-/* UCAxMCTLW Control Bits */
-#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */
-#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */
-#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */
-#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */
-#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */
-
-/* UCAxMCTLW Control Bits */
-#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */
-#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */
-#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */
-#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */
-#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */
-#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */
-#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */
-#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */
-
-#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
-#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
-#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
-#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
-#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
-#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
-#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
-#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
-#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
-#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
-#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
-#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
-#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
-#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
-#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
-#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
-
-
-/* UCAxSTATW Control Bits */
-#define UCLISTEN (0x0080) /* USCI Listen mode */
-#define UCFE (0x0040) /* USCI Frame Error Flag */
-#define UCOE (0x0020) /* USCI Overrun Error Flag */
-#define UCPE (0x0010) /* USCI Parity Error Flag */
-#define UCBRK (0x0008) /* USCI Break received */
-#define UCRXERR (0x0004) /* USCI RX Error Flag */
-#define UCADDR (0x0002) /* USCI Address received Flag */
-#define UCBUSY (0x0001) /* USCI Busy Flag */
-#define UCIDLE (0x0002) /* USCI Idle line detected Flag */
-
-
-/* UCBxSTATW I2C Control Bits */
-#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */
-#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */
-#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */
-#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */
-#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */
-#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */
-#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */
-#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */
-#define UCSCLLOW (0x0040) /* SCL low */
-#define UCGC (0x0020) /* General Call address received Flag */
-#define UCBBUSY (0x0010) /* Bus Busy Flag */
-
-/* UCBxTBCNT I2C Control Bits */
-#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */
-#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */
-#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */
-#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */
-#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */
-#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */
-#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */
-#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */
-
-/* UCAxIRCTL Control Bits */
-#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */
-#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */
-#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */
-#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */
-#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */
-#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */
-#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */
-#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */
-#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */
-#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */
-#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */
-#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */
-#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */
-#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */
-#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */
-#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */
-
-/* UCAxIRCTL Control Bits */
-#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */
-#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */
-#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */
-#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */
-#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */
-#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */
-#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */
-#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */
-
-/* UCAxIRCTL Control Bits */
-#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */
-#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */
-#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */
-#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */
-#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */
-#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */
-#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */
-#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */
-
-
-/* UCAxABCTL Control Bits */
-//#define res (0x80) /* reserved */
-//#define res (0x40) /* reserved */
-#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
-#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
-#define UCSTOE (0x08) /* Sync-Field Timeout error */
-#define UCBTOE (0x04) /* Break Timeout error */
-//#define res (0x02) /* reserved */
-#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
-
-/* UCBxI2COA0 Control Bits */
-#define UCGCEN (0x8000) /* I2C General Call enable */
-#define UCOAEN (0x0400) /* I2C Own Address enable */
-#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
-#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
-#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
-#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
-#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
-#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
-#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
-#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
-#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
-#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
-
-/* UCBxI2COA0 Control Bits */
-#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
-#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
-#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
-#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
-#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
-#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
-#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
-#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
-
-/* UCBxI2COA0 Control Bits */
-#define UCGCEN_H (0x0080) /* I2C General Call enable */
-#define UCOAEN_H (0x0004) /* I2C Own Address enable */
-#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
-#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
-
-/* UCBxADDRX Control Bits */
-#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */
-#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */
-#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */
-#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */
-#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */
-#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */
-#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */
-#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */
-#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */
-#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */
-
-/* UCBxADDRX Control Bits */
-#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */
-#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */
-#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */
-#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */
-#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */
-#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */
-#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */
-#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */
-
-/* UCBxADDRX Control Bits */
-#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */
-#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */
-
-/* UCBxADDMASK Control Bits */
-#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */
-#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */
-#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */
-#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */
-#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */
-#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */
-#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */
-#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */
-#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */
-#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */
-
-/* UCBxADDMASK Control Bits */
-#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */
-#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */
-#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */
-#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */
-#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */
-#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */
-#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */
-#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */
-
-/* UCBxADDMASK Control Bits */
-#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */
-#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */
-
-/* UCBxI2CSA Control Bits */
-#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */
-#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */
-#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */
-#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */
-#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */
-#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */
-#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */
-#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */
-#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */
-#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */
-
-/* UCBxI2CSA Control Bits */
-#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */
-#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */
-#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */
-#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */
-#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */
-#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */
-#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */
-#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */
-
-/* UCBxI2CSA Control Bits */
-#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */
-#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */
-
-/* UCAxIE UART Control Bits */
-#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */
-#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */
-#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */
-#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */
-
-/* UCAxIE/UCBxIE SPI Control Bits */
-
-/* UCBxIE I2C Control Bits */
-#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */
-#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */
-#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */
-#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */
-#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */
-#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */
-#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */
-#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */
-#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */
-#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */
-#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */
-#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */
-#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */
-#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */
-
-/* UCAxIFG UART Control Bits */
-#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */
-#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */
-#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */
-#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */
-
-/* UCBxIFG Control Bits */
-#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */
-#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */
-#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */
-#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */
-#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */
-#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */
-#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */
-#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */
-#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */
-#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */
-#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */
-#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */
-// #define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */
-#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */
-#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */
-
-/* USCI UART Definitions */
-#define USCI_NONE (0x0000) /* No Interrupt pending */
-#define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */
-#define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */
-#define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */
-#define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */
-
-/* USCI SPI Definitions */
-#define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */
-#define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */
-
-/* USCI I2C Definitions */
-#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */
-#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */
-#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/
-#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/
-#define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */
-#define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */
-#define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */
-#define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */
-#define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */
-#define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */
-#define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */
-#define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */
-#define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */
-#define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */
-#define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */
-
-/************************************************************
-* WATCHDOG TIMER A
-************************************************************/
-
-#define WDTCTL 0x015C /* Watchdog Timer Control */
-/* The bit names have been prefixed with "WDT" */
-/* WDTCTL Control Bits */
-#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
-#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
-#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
-#define WDTCNTCL (0x0008) /* WDT - Timer Clear */
-#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
-#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
-#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
-#define WDTHOLD (0x0080) /* WDT - Timer hold */
-
-/* WDTCTL Control Bits */
-#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
-#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
-#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
-#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
-#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
-#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
-#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
-#define WDTHOLD_L (0x0080) /* WDT - Timer hold */
-
-
-#define WDTPW (0x5A00)
-
-#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */
-#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */
-#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */
-#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */
-#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */
-#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */
-#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */
-#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */
-#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */
-#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */
-#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */
-#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */
-#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */
-#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */
-#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */
-#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */
-
-#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
-#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */
-#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
-#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */
-#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
-#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */
-#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
-
-
-/* WDT-interval times [1ms] coded with Bits 0-2 */
-/* WDT is clocked by fSMCLK (assumed 1MHz) */
-#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
-#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
-#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
-#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
-/* WDT is clocked by fACLK (assumed 32KHz) */
-#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
-#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
-#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
-#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
-/* Watchdog mode -> reset after expired time */
-/* WDT is clocked by fSMCLK (assumed 1MHz) */
-#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
-#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
-#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
-#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
-/* WDT is clocked by fACLK (assumed 32KHz) */
-#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
-#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
-#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
-#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
-
-
-/************************************************************
-* TLV Descriptors
-************************************************************/
-
-#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */
-#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */
-#define TLV_START (0x1A08) /* Start Address of the TLV structure */
-#define TLV_END (0x1AFF) /* End Address of the TLV structure */
-
-#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
-#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
-#define TLV_Reserved3 (0x03) /* Future usage */
-#define TLV_Reserved4 (0x04) /* Future usage */
-#define TLV_BLANK (0x05) /* Blank descriptor */
-#define TLV_Reserved6 (0x06) /* Future usage */
-#define TLV_Reserved7 (0x07) /* Serial Number */
-#define TLV_DIERECORD (0x08) /* Die Record */
-#define TLV_ADCCAL (0x11) /* ADC12 calibration */
-#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
-#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
-#define TLV_REFCAL (0x12) /* REF calibration */
-#define TLV_TAGEXT (0xFE) /* Tag extender */
-#define TLV_TAGEND (0xFF) // Tag End of Table
-
-
-/************************************************************
-* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
-************************************************************/
-
-
-#define AES256_VECTOR (31) /* 0xFFCC AES256 */
-#define RTC_VECTOR (32) /* 0xFFCE RTC */
-#define PORT4_VECTOR (33) /* 0xFFD0 Port 4 */
-#define PORT3_VECTOR (34) /* 0xFFD2 Port 3 */
-#define TIMER3_A1_VECTOR (35) /* 0xFFD4 Timer3_A2 CC1, TA */
-#define TIMER3_A0_VECTOR (36) /* 0xFFD6 Timer3_A2 CC0 */
-#define PORT2_VECTOR (37) /* 0xFFD8 Port 2 */
-#define TIMER2_A1_VECTOR (38) /* 0xFFDA Timer2_A2 CC1, TA */
-#define TIMER2_A0_VECTOR (39) /* 0xFFDC Timer2_A2 CC0 */
-#define PORT1_VECTOR (40) /* 0xFFDE Port 1 */
-#define TIMER1_A1_VECTOR (41) /* 0xFFE0 Timer1_A3 CC1-2, TA */
-#define TIMER1_A0_VECTOR (42) /* 0xFFE2 Timer1_A3 CC0 */
-#define DMA_VECTOR (43) /* 0xFFE4 DMA */
-#define USCI_A1_VECTOR (44) /* 0xFFE6 USCI A1 Receive/Transmit */
-#define TIMER0_A1_VECTOR (45) /* 0xFFE8 Timer0_A3 CC1-2, TA */
-#define TIMER0_A0_VECTOR (46) /* 0xFFEA Timer0_A3 CC0 */
-#define ADC12_VECTOR (47) /* 0xFFEC ADC */
-#define USCI_B0_VECTOR (48) /* 0xFFEE USCI B0 Receive/Transmit */
-#define USCI_A0_VECTOR (49) /* 0xFFF0 USCI A0 Receive/Transmit */
-#define WDT_VECTOR (50) /* 0xFFF2 Watchdog Timer */
-#define TIMER0_B1_VECTOR (51) /* 0xFFF4 Timer0_B7 CC1-6, TB */
-#define TIMER0_B0_VECTOR (52) /* 0xFFF6 Timer0_B7 CC0 */
-#define COMP_E_VECTOR (53) /* 0xFFF8 Comparator E */
-#define UNMI_VECTOR (54) /* 0xFFFA User Non-maskable */
-#define SYSNMI_VECTOR (55) /* 0xFFFC System Non-maskable */
-#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */
-
-/************************************************************
-* End of Modules
-************************************************************/
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm b/amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm
deleted file mode 100644
index 6abf0ba..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm
+++ /dev/null
@@ -1,30 +0,0 @@
-CODEHEADER(XT_COLD,4,"cold")
-main: ; Debugger requires the 'main' symbol.
-reset:
- mov #5A80h, &WDTCTL ; Watchdog off
-
- mov #0A500h, &MPUCTL0 ; Write password to enable access to MPU
- mov FLASHSTART>>4, &MPUSEGB1 ; B1 = Start of memory
- mov AMFORTH_START>>4, &MPUSEGB2 ; B2 = 0x10000 (Segment 3 is upper mem)
- mov #7577h, &MPUSAM ; write protect core system.
- mov #0A501h, &MPUCTL0 ; Enable MPU
- mov.b #0, &MPUCTL0+1 ; Disable MPU access
-
- ;------------------------------------------------------------------------------
- ; Init Clock
-
- mov #0A500h, &CSCTL0 ; Enable access to clock registers
- mov #0, &CSCTL3 ; Set all clock dividers to /1
- mov.b #0, &CSCTL0+1 ; Disable access to clock registers
-
-
- ;------------------------------------------------------------------------------
- ; Forth registers
- MOV #RSTACK,SP ; set up stack
- MOV #PSTACK,PSP
- MOV #UAREA,UP ; initial user pointer
-
- CLR R15
- ; now hand over to Forth with WARM (a colon word)
- MOV #XT_WARM+2,IP
- NEXT
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm b/amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm
deleted file mode 100644
index ec52936..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm
+++ /dev/null
@@ -1,11 +0,0 @@
-ENVIRONMENT(XT_ENV_MCU_INFO,8,"mcu-info")
- .DW XT_DOLITERAL
- .dw mcuinfo
- .DW XT_EXIT
-mcuinfo:
- ; first fixed sized elements
- .dw RAMEND-RAMSTART ; RAM Size
- .dw 0 ; EEPROM Size
- .dw AMFORTH_START-1 ; max-dp
- .dw 1 ; number of interrupts
-
diff --git a/amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm b/amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm
deleted file mode 100644
index 322f05a..0000000
--- a/amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm
+++ /dev/null
@@ -1,25 +0,0 @@
- CODEHEADER(XT_USART,6,"+usart")
-
- ;------------------------------------------------------------------------------
- ; Init IO
-
- bic #LOCKLPM5, &PM5CTL0 ; Unlock I/O pins
- mov.b #3, &P2SEL1 ; Use P2.0/P2.1 pins for Communication
- mov.b #0, &P2SEL0
-
- ;------------------------------------------------------------------------------
- ; Init serial communication
-
- ; f Baud UCOS16 UCBR UCBRF UCBRS
- ; 8000000 115200 1 4 5 0x55
-
- mov #UCSWRST, &UCA0CTLW0 ; **Put state machine in reset**
- bis #UCSSEL__SMCLK, &UCA0CTLW0 ; SMCLK
-
- mov #4, &UCA0BRW ; 8 MHz 115200 Baud
- mov #05501h|UCBRF_5, &UCA0MCTLW ; Modulation UCBRSx=55h, UCBRFx=5, UCOS16
-
- bic #UCSWRST, &UCA0CTLW0 ; **Initialize USCI state machine**
- ;------------------------------------------------------------------------------
-
- NEXT
diff --git a/amforth-6.5/msp430/devices/msp430g2553/device.asm b/amforth-6.5/msp430/devices/msp430g2553/device.asm
deleted file mode 100644
index eaf7c8b..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/device.asm
+++ /dev/null
@@ -1,36 +0,0 @@
-; device specific
-.include "msp430g2553.inc" ; MCU-specific register equates
-
-RAMSTART equ 0200h
-RAMEND equ 0400h
-
-INFOSTART equ 01000h
-INFOEND equ 010BFh ; do not allow config flash to be erased
-FLASHSTART equ 0C000h
-FLASHEND equ 0DFFFh
-MAINSEG equ 512
-INFOSEG equ 64
-INFO_SIZE equ 128 ; bytes
-
-.if WANT_INTERRUPTS == 1
-.org 0FFE0h
-
- DC16 null_handler ; 01: 0FFE0 Unused
- DC16 null_handler ; 02: 0FFE2 Unused
- DC16 irq1_handler ; 03: 0FFE4 Port 1
- DC16 irq2_handler ; 04: 0FFE6 Port 2
- DC16 null_handler ; 05: 0FFE8 Unused
- DC16 irq3_handler ; 06: 0FFEA ADC10
- DC16 irq4_handler ; 07: 0FFEC USCI Transmit - Terminal is polled
- DC16 irq5_handler ; 08: 0FFEE USCI Receive - no use for them
- DC16 irq6_handler ; 09: 0FFF0 Timer A
- DC16 irq7_handler ; 10: 0FFF2 Timer A
- DC16 null_handler ; 11: 0FFF4 Watchdog
- DC16 irq8_handler ; 12: 0FFF6 Comparantor
- DC16 irq9_handler ; 13: 0FFF8 Timer B
- DC16 irq10_handler ; 14: 0FFFA Timer B
- DC16 null_handler ; 15: 0FFFC NMI. Unused.
-.endif
-
-.org 0FFFEh
- DC16 reset ; FFFE - Reset
diff --git a/amforth-6.5/msp430/devices/msp430g2553/device.py b/amforth-6.5/msp430/devices/msp430g2553/device.py
deleted file mode 100644
index 513824d..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/device.py
+++ /dev/null
@@ -1,16 +0,0 @@
-MCUREGS = {
- 'P1IN': '$20',
- 'P1OUT':'$21',
- 'P1DIR':'$22',
- 'P1REN':'$27',
-
- 'P2IN' :'$28',
- 'P2OUT':'$29',
- 'P2DIR':'$2a',
- 'P2REN':'$2f',
-
- 'P3IN': '$18',
- 'P3OUT':'$19',
- 'P3DIR':'$1a',
- 'P3REN':'$10',
- }
diff --git a/amforth-6.5/msp430/devices/msp430g2553/drivers.asm b/amforth-6.5/msp430/devices/msp430g2553/drivers.asm
deleted file mode 100644
index 2793ccf..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/drivers.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-
-.include "drivers/flash.inc"
-
diff --git a/amforth-6.5/msp430/devices/msp430g2553/init.asm b/amforth-6.5/msp430/devices/msp430g2553/init.asm
deleted file mode 100644
index f3806ca..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/init.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-
-mcu_name:
- .db 11,"MSP430G2553"
diff --git a/amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc b/amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc
deleted file mode 100644
index 71cba98..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc
+++ /dev/null
@@ -1,851 +0,0 @@
-/********************************************************************
-*
-* Standard register and bit definitions for the Texas Instruments
-* MSP430G2553 microcontroller.
-*
-* Adapted for naken_asm - B. Rodriguez 1 mar 2014.
-*
-* Texas Instruments, Version 1.0
-*
-* Rev. 1.0, Setup
-*
-********************************************************************/
-
-/* ============================================================================ */
-/* Copyright (c) 2012, Texas Instruments Incorporated */
-/* All rights reserved. */
-/* */
-/* Redistribution and use in source and binary forms, with or without */
-/* modification, are permitted provided that the following conditions */
-/* are met: */
-/* */
-/* * Redistributions of source code must retain the above copyright */
-/* notice, this list of conditions and the following disclaimer. */
-/* */
-/* * Redistributions in binary form must reproduce the above copyright */
-/* notice, this list of conditions and the following disclaimer in the */
-/* documentation and/or other materials provided with the distribution. */
-/* */
-/* * Neither the name of Texas Instruments Incorporated nor the names of */
-/* its contributors may be used to endorse or promote products derived */
-/* from this software without specific prior written permission. */
-/* */
-/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
-/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
-/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
-/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
-/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
-/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
-/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
-/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
-/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
-/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ============================================================================ */
-
-/************************************************************
-* STANDARD BITS
-************************************************************/
-
-#define BIT0 (0x0001)
-#define BIT1 (0x0002)
-#define BIT2 (0x0004)
-#define BIT3 (0x0008)
-#define BIT4 (0x0010)
-#define BIT5 (0x0020)
-#define BIT6 (0x0040)
-#define BIT7 (0x0080)
-#define BIT8 (0x0100)
-#define BIT9 (0x0200)
-#define BITA (0x0400)
-#define BITB (0x0800)
-#define BITC (0x1000)
-#define BITD (0x2000)
-#define BITE (0x4000)
-#define BITF (0x8000)
-
-/************************************************************
-* STATUS REGISTER BITS
-************************************************************/
-
-#define C (0x0001)
-#define Z (0x0002)
-#define N (0x0004)
-#define V (0x0100)
-#define GIE (0x0008)
-#define CPUOFF (0x0010)
-#define OSCOFF (0x0020)
-#define SCG0 (0x0040)
-#define SCG1 (0x0080)
-
-/* Low Power Modes coded with Bits 4-7 in SR */
-
-#define LPM0 (CPUOFF)
-#define LPM1 (SCG0+CPUOFF)
-#define LPM2 (SCG1+CPUOFF)
-#define LPM3 (SCG1+SCG0+CPUOFF)
-#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
-
-/************************************************************
-* PERIPHERAL FILE MAP
-************************************************************/
-
-/************************************************************
-* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
-************************************************************/
-
-#define IE1 0x0000 /* Interrupt Enable 1 */
-#define WDTIE (0x01) /* Watchdog Interrupt Enable */
-#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
-#define NMIIE (0x10) /* NMI Interrupt Enable */
-#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
-
-#define IFG1 0x0002 /* Interrupt Flag 1 */
-#define WDTIFG (0x01) /* Watchdog Interrupt Flag */
-#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
-#define PORIFG (0x04) /* Power On Interrupt Flag */
-#define RSTIFG (0x08) /* Reset Interrupt Flag */
-#define NMIIFG (0x10) /* NMI Interrupt Flag */
-
-#define IE2 0x0001 /* Interrupt Enable 2 */
-#define UC0IE IE2
-#define UCA0RXIE (0x01)
-#define UCA0TXIE (0x02)
-#define UCB0RXIE (0x04)
-#define UCB0TXIE (0x08)
-
-#define IFG2 0x0003 /* Interrupt Flag 2 */
-#define UC0IFG IFG2
-#define UCA0RXIFG (0x01)
-#define UCA0TXIFG (0x02)
-#define UCB0RXIFG (0x04)
-#define UCB0TXIFG (0x08)
-
-
-/************************************************************
-* ADC10
-************************************************************/
-#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */
-
-#define ADC10DTC0 0x0048 /* ADC10 Data Transfer Control 0 */
-#define ADC10DTC1 0x0049 /* ADC10 Data Transfer Control 1 */
-#define ADC10AE0 0x004A /* ADC10 Analog Enable 0 */
-
-#define ADC10CTL0 0x01B0 /* ADC10 Control 0 */
-#define ADC10CTL1 0x01B2 /* ADC10 Control 1 */
-#define ADC10MEM 0x01B4 /* ADC10 Memory */
-#define ADC10SA 0x01BC /* ADC10 Data Transfer Start Address */
-
-/* ADC10CTL0 */
-#define ADC10SC (0x001) /* ADC10 Start Conversion */
-#define ENC (0x002) /* ADC10 Enable Conversion */
-#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */
-#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */
-#define ADC10ON (0x010) /* ADC10 On/Enable */
-#define REFON (0x020) /* ADC10 Reference on */
-#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */
-#define MSC (0x080) /* ADC10 Multiple SampleConversion */
-#define REFBURST (0x100) /* ADC10 Reference Burst Mode */
-#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */
-#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */
-#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */
-#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */
-#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */
-#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */
-#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */
-#define ADC10SHT_0 (0x0000) /* 4 x ADC10CLKs */
-#define ADC10SHT_1 (0x0800) /* 8 x ADC10CLKs */
-#define ADC10SHT_2 (0x1000) /* 16 x ADC10CLKs */
-#define ADC10SHT_3 (0x1800) /* 64 x ADC10CLKs */
-
-#define SREF_0 (0x0000) /* VR+ = AVCC and VR- = AVSS */
-#define SREF_1 (0x2000) /* VR+ = VREF+ and VR- = AVSS */
-#define SREF_2 (0x4000) /* VR+ = VEREF+ and VR- = AVSS */
-#define SREF_3 (0x6000) /* VR+ = VEREF+ and VR- = AVSS */
-#define SREF_4 (0x8000) /* VR+ = AVCC and VR- = VREF-/VEREF- */
-#define SREF_5 (0xA000) /* VR+ = VREF+ and VR- = VREF-/VEREF- */
-#define SREF_6 (0xC000) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
-#define SREF_7 (0xE000) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */
-
-/* ADC10CTL1 */
-#define ADC10BUSY (0x0001) /* ADC10 BUSY */
-#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */
-#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */
-#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */
-#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */
-#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */
-#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */
-#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */
-#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */
-#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */
-#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */
-#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */
-#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */
-#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */
-#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */
-#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */
-
-#define CONSEQ_0 (0x0000) /* Single channel single conversion */
-#define CONSEQ_1 (0x0002) /* Sequence of channels */
-#define CONSEQ_2 (0x0004) /* Repeat single channel */
-#define CONSEQ_3 (0x0006) /* Repeat sequence of channels */
-
-#define ADC10SSEL_0 (0x0000) /* ADC10OSC */
-#define ADC10SSEL_1 (0x0008) /* ACLK */
-#define ADC10SSEL_2 (0x0010) /* MCLK */
-#define ADC10SSEL_3 (0x0018) /* SMCLK */
-
-#define ADC10DIV_0 (0x0000) /* ADC10 Clock Divider Select 0 */
-#define ADC10DIV_1 (0x0020) /* ADC10 Clock Divider Select 1 */
-#define ADC10DIV_2 (0x0040) /* ADC10 Clock Divider Select 2 */
-#define ADC10DIV_3 (0x0060) /* ADC10 Clock Divider Select 3 */
-#define ADC10DIV_4 (0x0080) /* ADC10 Clock Divider Select 4 */
-#define ADC10DIV_5 (0x00A0) /* ADC10 Clock Divider Select 5 */
-#define ADC10DIV_6 (0x00C0) /* ADC10 Clock Divider Select 6 */
-#define ADC10DIV_7 (0x00E0) /* ADC10 Clock Divider Select 7 */
-
-#define SHS_0 (0x0000) /* ADC10SC */
-#define SHS_1 (0x0400) /* TA3 OUT1 */
-#define SHS_2 (0x0800) /* TA3 OUT0 */
-#define SHS_3 (0x0C00) /* TA3 OUT2 */
-
-#define INCH_0 (0x0000) /* Selects Channel 0 */
-#define INCH_1 (0x1000) /* Selects Channel 1 */
-#define INCH_2 (0x2000) /* Selects Channel 2 */
-#define INCH_3 (0x3000) /* Selects Channel 3 */
-#define INCH_4 (0x4000) /* Selects Channel 4 */
-#define INCH_5 (0x5000) /* Selects Channel 5 */
-#define INCH_6 (0x6000) /* Selects Channel 6 */
-#define INCH_7 (0x7000) /* Selects Channel 7 */
-#define INCH_8 (0x8000) /* Selects Channel 8 */
-#define INCH_9 (0x9000) /* Selects Channel 9 */
-#define INCH_10 (0xA000) /* Selects Channel 10 */
-#define INCH_11 (0xB000) /* Selects Channel 11 */
-#define INCH_12 (0xC000) /* Selects Channel 12 */
-#define INCH_13 (0xD000) /* Selects Channel 13 */
-#define INCH_14 (0xE000) /* Selects Channel 14 */
-#define INCH_15 (0xF000) /* Selects Channel 15 */
-
-/* ADC10DTC0 */
-#define ADC10FETCH (0x001) /* This bit should normally be reset */
-#define ADC10B1 (0x002) /* ADC10 block one */
-#define ADC10CT (0x004) /* ADC10 continuous transfer */
-#define ADC10TB (0x008) /* ADC10 two-block mode */
-#define ADC10DISABLE (0x000) /* ADC10DTC1 */
-
-/************************************************************
-* Basic Clock Module
-************************************************************/
-#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */
-
-#define DCOCTL 0x0056 /* DCO Clock Frequency Control */
-#define BCSCTL1 0x0057 /* Basic Clock System Control 1 */
-#define BCSCTL2 0x0058 /* Basic Clock System Control 2 */
-#define BCSCTL3 0x0053 /* Basic Clock System Control 3 */
-
-#define MOD0 (0x01) /* Modulation Bit 0 */
-#define MOD1 (0x02) /* Modulation Bit 1 */
-#define MOD2 (0x04) /* Modulation Bit 2 */
-#define MOD3 (0x08) /* Modulation Bit 3 */
-#define MOD4 (0x10) /* Modulation Bit 4 */
-#define DCO0 (0x20) /* DCO Select Bit 0 */
-#define DCO1 (0x40) /* DCO Select Bit 1 */
-#define DCO2 (0x80) /* DCO Select Bit 2 */
-
-#define RSEL0 (0x01) /* Range Select Bit 0 */
-#define RSEL1 (0x02) /* Range Select Bit 1 */
-#define RSEL2 (0x04) /* Range Select Bit 2 */
-#define RSEL3 (0x08) /* Range Select Bit 3 */
-#define DIVA0 (0x10) /* ACLK Divider 0 */
-#define DIVA1 (0x20) /* ACLK Divider 1 */
-#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
-#define XT2OFF (0x80) /* Enable XT2CLK */
-
-#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
-#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
-#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
-#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
-
-#define DIVS0 (0x02) /* SMCLK Divider 0 */
-#define DIVS1 (0x04) /* SMCLK Divider 1 */
-#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
-#define DIVM0 (0x10) /* MCLK Divider 0 */
-#define DIVM1 (0x20) /* MCLK Divider 1 */
-#define SELM0 (0x40) /* MCLK Source Select 0 */
-#define SELM1 (0x80) /* MCLK Source Select 1 */
-
-#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
-#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
-#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
-#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
-
-#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
-#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
-#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
-#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
-
-#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
-#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
-#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
-#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
-
-#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */
-#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */
-#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */
-#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */
-#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */
-#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */
-#define XT2S0 (0x40) /* Mode 0 for XT2 */
-#define XT2S1 (0x80) /* Mode 1 for XT2 */
-
-#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */
-#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */
-#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */
-#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */
-
-#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */
-#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */
-#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */
-#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */
-
-#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */
-#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */
-#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */
-#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */
-
-/************************************************************
-* Comparator A
-************************************************************/
-#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */
-
-#define CACTL1 0x0059 /* Comparator A Control 1 */
-#define CACTL2 0x005A /* Comparator A Control 2 */
-#define CAPD 0x005B /* Comparator A Port Disable */
-
-#define CAIFG (0x01) /* Comp. A Interrupt Flag */
-#define CAIE (0x02) /* Comp. A Interrupt Enable */
-#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
-#define CAON (0x08) /* Comp. A enable */
-#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
-#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
-#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
-#define CAEX (0x80) /* Comp. A Exchange Inputs */
-
-#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
-#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
-#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
-#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
-
-#define CAOUT (0x01) /* Comp. A Output */
-#define CAF (0x02) /* Comp. A Enable Output Filter */
-#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */
-#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */
-#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */
-#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */
-#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */
-#define CASHORT (0x80) /* Comp. A Short + and - Terminals */
-
-#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
-#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
-#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
-#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
-#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
-#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
-#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
-#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
-
-/*************************************************************
-* Flash Memory
-*************************************************************/
-#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
-
-#define FCTL1 0x0128 /* FLASH Control 1 */
-#define FCTL2 0x012A /* FLASH Control 2 */
-#define FCTL3 0x012C /* FLASH Control 3 */
-
-#define FRKEY (0x9600) /* Flash key returned by read */
-#define FWKEY (0xA500) /* Flash key for write */
-#define FXKEY (0x3300) /* for use with XOR instruction */
-
-#define ERASE (0x0002) /* Enable bit for Flash segment erase */
-#define MERAS (0x0004) /* Enable bit for Flash mass erase */
-#define WRT (0x0040) /* Enable bit for Flash write */
-#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
-#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
-
-#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
-#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
-#define FN2 (0x0004)
-#define FN3 (0x0008)
-#define FN4 (0x0010)
-#define FN5 (0x0020)
-#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
-#define FSSEL1 (0x0080) /* Flash clock select 1 */
-
-#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
-#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
-#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
-#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
-
-#define BUSY (0x0001) /* Flash busy: 1 */
-#define KEYV (0x0002) /* Flash Key violation flag */
-#define ACCVIFG (0x0004) /* Flash Access violation flag */
-#define WAIT (0x0008) /* Wait flag for segment write */
-#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
-#define EMEX (0x0020) /* Flash Emergency Exit */
-#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
-#define FAIL (0x0080) /* Last Program or Erase failed */
-
-/************************************************************
-* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
-************************************************************/
-#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
-#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
-
-#define P1IN 0x0020 /* Port 1 Input */
-#define P1OUT 0x0021 /* Port 1 Output */
-#define P1DIR 0x0022 /* Port 1 Direction */
-#define P1IFG 0x0023 /* Port 1 Interrupt Flag */
-#define P1IES 0x0024 /* Port 1 Interrupt Edge Select */
-#define P1IE 0x0025 /* Port 1 Interrupt Enable */
-#define P1SEL 0x0026 /* Port 1 Selection */
-#define P1SEL2 0x0041 /* Port 1 Selection 2 */
-#define P1REN 0x0027 /* Port 1 Resistor Enable */
-
-#define P2IN 0x0028 /* Port 2 Input */
-#define P2OUT 0x0029 /* Port 2 Output */
-#define P2DIR 0x002A /* Port 2 Direction */
-#define P2IFG 0x002B /* Port 2 Interrupt Flag */
-#define P2IES 0x002C /* Port 2 Interrupt Edge Select */
-#define P2IE 0x002D /* Port 2 Interrupt Enable */
-#define P2SEL 0x002E /* Port 2 Selection */
-#define P2SEL2 0x0042 /* Port 2 Selection 2 */
-#define P2REN 0x002F /* Port 2 Resistor Enable */
-
-/************************************************************
-* DIGITAL I/O Port3 Pull up / Pull down Resistors
-************************************************************/
-#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
-
-#define P3IN 0x0018 /* Port 3 Input */
-#define P3OUT 0x0019 /* Port 3 Output */
-#define P3DIR 0x001A /* Port 3 Direction */
-#define P3SEL 0x001B /* Port 3 Selection */
-#define P3SEL2 0x0043 /* Port 3 Selection 2 */
-#define P3REN 0x0010 /* Port 3 Resistor Enable */
-
-/************************************************************
-* Timer0_A3
-************************************************************/
-#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
-
-#define TA0IV 0x012E /* Timer0_A3 Interrupt Vector Word */
-#define TA0CTL 0x0160 /* Timer0_A3 Control */
-#define TA0CCTL0 0x0162 /* Timer0_A3 Capture/Compare Control 0 */
-#define TA0CCTL1 0x0164 /* Timer0_A3 Capture/Compare Control 1 */
-#define TA0CCTL2 0x0166 /* Timer0_A3 Capture/Compare Control 2 */
-#define TA0R 0x0170 /* Timer0_A3 */
-#define TA0CCR0 0x0172 /* Timer0_A3 Capture/Compare 0 */
-#define TA0CCR1 0x0174 /* Timer0_A3 Capture/Compare 1 */
-#define TA0CCR2 0x0176 /* Timer0_A3 Capture/Compare 2 */
-
-/* Alternate register names */
-#define TAIV TA0IV /* Timer A Interrupt Vector Word */
-#define TACTL TA0CTL /* Timer A Control */
-#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */
-#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */
-#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */
-#define TAR TA0R /* Timer A */
-#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */
-#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */
-#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */
-#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */
-#define TACTL_ TA0CTL_ /* Timer A Control */
-#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */
-#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */
-#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */
-#define TAR_ TA0R_ /* Timer A */
-#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */
-#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */
-#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */
-
-/* Alternate register names 2 */
-#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
-#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
-#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
-#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
-#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
-#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
-#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
-#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
-#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
-#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
-#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
-#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
-
-#define TASSEL1 (0x0200) /* Timer A clock source select 1 */
-#define TASSEL0 (0x0100) /* Timer A clock source select 0 */
-#define ID1 (0x0080) /* Timer A clock input divider 1 */
-#define ID0 (0x0040) /* Timer A clock input divider 0 */
-#define MC1 (0x0020) /* Timer A mode control 1 */
-#define MC0 (0x0010) /* Timer A mode control 0 */
-#define TACLR (0x0004) /* Timer A counter clear */
-#define TAIE (0x0002) /* Timer A counter interrupt enable */
-#define TAIFG (0x0001) /* Timer A counter interrupt flag */
-
-#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */
-#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
-#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */
-#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */
-#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */
-#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */
-#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */
-#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */
-#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */
-#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */
-#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */
-#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */
-
-#define CM1 (0x8000) /* Capture mode 1 */
-#define CM0 (0x4000) /* Capture mode 0 */
-#define CCIS1 (0x2000) /* Capture input select 1 */
-#define CCIS0 (0x1000) /* Capture input select 0 */
-#define SCS (0x0800) /* Capture sychronize */
-#define SCCI (0x0400) /* Latched capture signal (read) */
-#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
-#define OUTMOD2 (0x0080) /* Output mode 2 */
-#define OUTMOD1 (0x0040) /* Output mode 1 */
-#define OUTMOD0 (0x0020) /* Output mode 0 */
-#define CCIE (0x0010) /* Capture/compare interrupt enable */
-#define CCI (0x0008) /* Capture input signal (read) */
-#define OUT (0x0004) /* PWM Output signal if output mode 0 */
-#define COV (0x0002) /* Capture/compare overflow flag */
-#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-
-#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */
-#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */
-#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */
-#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */
-#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */
-#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */
-#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */
-#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */
-#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */
-#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */
-#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */
-#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */
-#define CM_0 (0x0000) /* Capture mode: 0 - disabled */
-#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */
-#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */
-#define CM_3 (0xC000) /* Capture mode: 1 - both edges */
-
-/* T0_A3IV Definitions */
-#define TA0IV_NONE (0x0000) /* No Interrupt pending */
-#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
-#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
-#define TA0IV_6 (0x0006) /* Reserved */
-#define TA0IV_8 (0x0008) /* Reserved */
-#define TA0IV_TAIFG (0x000A) /* TA0IFG */
-
-/************************************************************
-* Timer1_A3
-************************************************************/
-#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */
-
-#define TA1IV 0x011E /* Timer1_A3 Interrupt Vector Word */
-#define TA1CTL 0x0180 /* Timer1_A3 Control */
-#define TA1CCTL0 0x0182 /* Timer1_A3 Capture/Compare Control 0 */
-#define TA1CCTL1 0x0184 /* Timer1_A3 Capture/Compare Control 1 */
-#define TA1CCTL2 0x0186 /* Timer1_A3 Capture/Compare Control 2 */
-#define TA1R 0x0190 /* Timer1_A3 */
-#define TA1CCR0 0x0192 /* Timer1_A3 Capture/Compare 0 */
-#define TA1CCR1 0x0194 /* Timer1_A3 Capture/Compare 1 */
-#define TA1CCR2 0x0196 /* Timer1_A3 Capture/Compare 2 */
-
-/* Bits are already defined within the Timer0_Ax */
-
-/* T1_A3IV Definitions */
-#define TA1IV_NONE (0x0000) /* No Interrupt pending */
-#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
-#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
-#define TA1IV_TAIFG (0x000A) /* TA1IFG */
-
-/************************************************************
-* USCI
-************************************************************/
-#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */
-
-#define UCA0CTL0 0x0060 /* USCI A0 Control Register 0 */
-#define UCA0CTL1 0x0061 /* USCI A0 Control Register 1 */
-#define UCA0BR0 0x0062 /* USCI A0 Baud Rate 0 */
-#define UCA0BR1 0x0063 /* USCI A0 Baud Rate 1 */
-#define UCA0MCTL 0x0064 /* USCI A0 Modulation Control */
-#define UCA0STAT 0x0065 /* USCI A0 Status Register */
-#define UCA0RXBUF 0x0066 /* USCI A0 Receive Buffer */
-#define UCA0TXBUF 0x0067 /* USCI A0 Transmit Buffer */
-#define UCA0ABCTL 0x005D /* USCI A0 LIN Control */
-#define UCA0IRTCTL 0x005E /* USCI A0 IrDA Transmit Control */
-#define UCA0IRRCTL 0x005F /* USCI A0 IrDA Receive Control */
-
-#define UCB0CTL0 0x0068 /* USCI B0 Control Register 0 */
-#define UCB0CTL1 0x0069 /* USCI B0 Control Register 1 */
-#define UCB0BR0 0x006A /* USCI B0 Baud Rate 0 */
-#define UCB0BR1 0x006B /* USCI B0 Baud Rate 1 */
-#define UCB0I2CIE 0x006C /* USCI B0 I2C Interrupt Enable Register */
-#define UCB0STAT 0x006D /* USCI B0 Status Register */
-#define UCB0RXBUF 0x006E /* USCI B0 Receive Buffer */
-#define UCB0TXBUF 0x006F /* USCI B0 Transmit Buffer */
-#define UCB0I2COA 0x0118 /* USCI B0 I2C Own Address */
-#define UCB0I2CSA 0x011A /* USCI B0 I2C Slave Address */
-
-// UART-Mode Bits
-#define UCPEN (0x80) /* Async. Mode: Parity enable */
-#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
-#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
-#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
-#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
-#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */
-#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */
-#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
-
-// SPI-Mode Bits
-#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */
-#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */
-#define UCMST (0x08) /* Sync. Mode: Master Select */
-
-// I2C-Mode Bits
-#define UCA10 (0x80) /* 10-bit Address Mode */
-#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */
-#define UCMM (0x20) /* Multi-Master Environment */
-//#define res (0x10) /* reserved */
-#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */
-#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */
-#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */
-#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */
-
-// UART-Mode Bits
-#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */
-#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */
-#define UCRXEIE (0x20) /* RX Error interrupt enable */
-#define UCBRKIE (0x10) /* Break interrupt enable */
-#define UCDORM (0x08) /* Dormant (Sleep) Mode */
-#define UCTXADDR (0x04) /* Send next Data as Address */
-#define UCTXBRK (0x02) /* Send next Data as Break */
-#define UCSWRST (0x01) /* USCI Software Reset */
-
-// SPI-Mode Bits
-//#define res (0x20) /* reserved */
-//#define res (0x10) /* reserved */
-//#define res (0x08) /* reserved */
-//#define res (0x04) /* reserved */
-//#define res (0x02) /* reserved */
-
-// I2C-Mode Bits
-//#define res (0x20) /* reserved */
-#define UCTR (0x10) /* Transmit/Receive Select/Flag */
-#define UCTXNACK (0x08) /* Transmit NACK */
-#define UCTXSTP (0x04) /* Transmit STOP */
-#define UCTXSTT (0x02) /* Transmit START */
-#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */
-#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */
-#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */
-#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */
-
-#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */
-#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */
-#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */
-#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */
-#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */
-#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */
-#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */
-#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */
-
-#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
-#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
-#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
-#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
-#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
-#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
-#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
-#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
-#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
-#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
-#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
-#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
-#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
-#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
-#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
-#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
-
-#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */
-#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */
-#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */
-#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */
-#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */
-#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */
-#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */
-#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */
-
-#define UCLISTEN (0x80) /* USCI Listen mode */
-#define UCFE (0x40) /* USCI Frame Error Flag */
-#define UCOE (0x20) /* USCI Overrun Error Flag */
-#define UCPE (0x10) /* USCI Parity Error Flag */
-#define UCBRK (0x08) /* USCI Break received */
-#define UCRXERR (0x04) /* USCI RX Error Flag */
-#define UCADDR (0x02) /* USCI Address received Flag */
-#define UCBUSY (0x01) /* USCI Busy Flag */
-#define UCIDLE (0x02) /* USCI Idle line detected Flag */
-
-//#define res (0x80) /* reserved */
-//#define res (0x40) /* reserved */
-//#define res (0x20) /* reserved */
-//#define res (0x10) /* reserved */
-#define UCNACKIE (0x08) /* NACK Condition interrupt enable */
-#define UCSTPIE (0x04) /* STOP Condition interrupt enable */
-#define UCSTTIE (0x02) /* START Condition interrupt enable */
-#define UCALIE (0x01) /* Arbitration Lost interrupt enable */
-
-
-#define UCSCLLOW (0x40) /* SCL low */
-#define UCGC (0x20) /* General Call address received Flag */
-#define UCBBUSY (0x10) /* Bus Busy Flag */
-#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */
-#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */
-#define UCSTTIFG (0x02) /* START Condition interrupt Flag */
-#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */
-
-#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */
-#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */
-#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */
-#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */
-#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */
-#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */
-#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */
-#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */
-
-#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */
-#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */
-#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */
-#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */
-#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */
-#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */
-#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */
-#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */
-
-//#define res (0x80) /* reserved */
-//#define res (0x40) /* reserved */
-#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
-#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
-#define UCSTOE (0x08) /* Sync-Field Timeout error */
-#define UCBTOE (0x04) /* Break Timeout error */
-//#define res (0x02) /* reserved */
-#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
-
-#define UCGCEN (0x8000) /* I2C General Call enable */
-#define UCOA9 (0x0200) /* I2C Own Address 9 */
-#define UCOA8 (0x0100) /* I2C Own Address 8 */
-#define UCOA7 (0x0080) /* I2C Own Address 7 */
-#define UCOA6 (0x0040) /* I2C Own Address 6 */
-#define UCOA5 (0x0020) /* I2C Own Address 5 */
-#define UCOA4 (0x0010) /* I2C Own Address 4 */
-#define UCOA3 (0x0008) /* I2C Own Address 3 */
-#define UCOA2 (0x0004) /* I2C Own Address 2 */
-#define UCOA1 (0x0002) /* I2C Own Address 1 */
-#define UCOA0 (0x0001) /* I2C Own Address 0 */
-
-#define UCSA9 (0x0200) /* I2C Slave Address 9 */
-#define UCSA8 (0x0100) /* I2C Slave Address 8 */
-#define UCSA7 (0x0080) /* I2C Slave Address 7 */
-#define UCSA6 (0x0040) /* I2C Slave Address 6 */
-#define UCSA5 (0x0020) /* I2C Slave Address 5 */
-#define UCSA4 (0x0010) /* I2C Slave Address 4 */
-#define UCSA3 (0x0008) /* I2C Slave Address 3 */
-#define UCSA2 (0x0004) /* I2C Slave Address 2 */
-#define UCSA1 (0x0002) /* I2C Slave Address 1 */
-#define UCSA0 (0x0001) /* I2C Slave Address 0 */
-
-/************************************************************
-* WATCHDOG TIMER
-************************************************************/
-#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
-
-#define WDTCTL 0x0120 /* Watchdog Timer Control */
-/* The bit names have been prefixed with "WDT" */
-#define WDTIS0 (0x0001)
-#define WDTIS1 (0x0002)
-#define WDTSSEL (0x0004)
-#define WDTCNTCL (0x0008)
-#define WDTTMSEL (0x0010)
-#define WDTNMI (0x0020)
-#define WDTNMIES (0x0040)
-#define WDTHOLD (0x0080)
-
-#define WDTPW (0x5A00)
-
-/* WDT-interval times [1ms] coded with Bits 0-2 */
-/* WDT is clocked by fSMCLK (assumed 1MHz) */
-#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
-#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
-#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
-#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
-/* WDT is clocked by fACLK (assumed 32KHz) */
-#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
-#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
-#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
-#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
-/* Watchdog mode -> reset after expired time */
-/* WDT is clocked by fSMCLK (assumed 1MHz) */
-#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
-#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
-#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
-#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
-/* WDT is clocked by fACLK (assumed 32KHz) */
-#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
-#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
-#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
-#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
-
-/* INTERRUPT CONTROL */
-/* These two bits are defined in the Special Function Registers */
-/* #define WDTIE 0x01 */
-/* #define WDTIFG 0x01 */
-
-/************************************************************
-* Calibration Data in Info Mem
-************************************************************/
-
-#ifndef __DisableCalData
-
-#define CALDCO_16MHZ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
-#define CALBC1_16MHZ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
-#define CALDCO_12MHZ 0x10FA /* DCOCTL Calibration Data for 12MHz */
-#define CALBC1_12MHZ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
-#define CALDCO_8MHZ 0x10FC /* DCOCTL Calibration Data for 8MHz */
-#define CALBC1_8MHZ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
-#define CALDCO_1MHZ 0x10FE /* DCOCTL Calibration Data for 1MHz */
-#define CALBC1_1MHZ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
-
-#endif /* #ifndef __DisableCalData */
-
-
-/************************************************************
-* Interrupt Vectors (offset from 0xFFE0)
-************************************************************/
-
-#define PORT1_VECTOR (0x0004) /* 0xFFE4 Port 1 */
-#define PORT2_VECTOR (0x0006) /* 0xFFE6 Port 2 */
-#define ADC10_VECTOR (0x000A) /* 0xFFEA ADC10 */
-#define USCIAB0TX_VECTOR (0x000C) /* 0xFFEC USCI A0/B0 Transmit */
-#define USCIAB0RX_VECTOR (0x000E) /* 0xFFEE USCI A0/B0 Receive */
-#define TIMER0_A1_VECTOR (0x0010) /* 0xFFF0 Timer0)A CC1, TA0 */
-#define TIMER0_A0_VECTOR (0x0012) /* 0xFFF2 Timer0_A CC0 */
-#define WDT_VECTOR (0x0014) /* 0xFFF4 Watchdog Timer */
-#define COMPARATORA_VECTOR (0x0016) /* 0xFFF6 Comparator A */
-#define TIMER1_A1_VECTOR (0x0018) /* 0xFFF8 Timer1_A CC1-4, TA1 */
-#define TIMER1_A0_VECTOR (0x001A) /* 0xFFFA Timer1_A CC0 */
-#define NMI_VECTOR (0x001C) /* 0xFFFC Non-maskable */
-#define RESET_VECTOR (0x001E) /* 0xFFFE Reset [Highest Priority] */
-
-/************************************************************
-* End of Modules
-************************************************************/
diff --git a/amforth-6.5/msp430/devices/msp430g2553/words/cold.asm b/amforth-6.5/msp430/devices/msp430g2553/words/cold.asm
deleted file mode 100644
index 0828eb4..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/words/cold.asm
+++ /dev/null
@@ -1,41 +0,0 @@
-CODEHEADER(XT_COLD,4,"cold")
-main: ; Debugger requires the 'main' symbol.
-reset:
- ; Watchdog Timer
- MOV #(WDTPW+WDTHOLD),&WDTCTL ; stop watchdog timer
-
- ; Basic Clock Module
- ; My thanks to the 4e4th team for the following two lines!
- MOV.B &CALBC1_8MHZ, &BCSCTL1 ; Set DCO
- MOV.B &CALDCO_8MHZ, &DCOCTL ; to 8 MHz.
-
- MOV.B #00h,&BCSCTL2 ; MCLK=DCO/1, SMCLK=DCO/1
-
- ; Flash Memory Controller
- ; Flash Timing Generator frequency must be 257-476 kHz.
- ; 8 MHZ/17 = 470.59 kHz. tFTG=2.125 msec.
- ; At 470 kHz, byte/word program time is 35*tFTG = 75 usec.
- ; Cumulative program time to any 64-byte block (between erasures)
- ; must not exceed 4 msec, thus 53 writes at 250 kHz. Therefore,
- ; do not use exclusively byte writes in a 64-byte block.
- ; Also, "a flash word (low + high byte) must not
- ; be written more than twice between erasures."
- ; Program/Erase endurance is 10,000 cycles minimum.
- MOV #FWKEY+0,&FCTL1 ; write & erase modes OFF
- MOV #FWKEY+FSSEL1+16,&FCTL2 ; SMCLK/17 = 471 kHz.
- MOV #FWKEY+LOCK,&FCTL3 ; lock flash memory against writing
-
- ; Interrupt Enables
- MOV.B #0,&IE1 ; no interrupts enabled
- MOV.B #0,&IE2 ; no interrupts enabled
-
- ; Forth registers
- MOV #RSTACK,SP ; set up stack
- MOV #PSTACK,PSP
- MOV #UAREA,UP ; initial user pointer
-
- CLR R15
-
- ; now hand over to Forth with WARM (a colon word)
- MOV #XT_WARM+2,IP
- NEXT
diff --git a/amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm b/amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm
deleted file mode 100644
index 621fc72..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-ENVIRONMENT(XT_ENV_MCU_INFO,8,"mcu-info")
- .DW XT_DOLITERAL
- .dw mcuinfo
- .DW XT_EXIT
-mcuinfo:
- ; first fixed sized elements
- .dw RAMEND-RAMSTART ; RAM Size
- .dw 0 ; EEPROM Size
- .dw AMFORTH_START-1 ; max-dp
- .dw 1 ; number of interrupts
diff --git a/amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm b/amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm
deleted file mode 100644
index e8c7693..0000000
--- a/amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm
+++ /dev/null
@@ -1,13 +0,0 @@
- CODEHEADER(XT_USART,6,"+usart")
- ; USCI_A0
- MOV.B #06,&P1SEL ; P1.1,2 are UART
- MOV.B #06,&P1SEL2 ; P1.1,2 are UART
-
- BIS.B #UCSWRST,&UCA0CTL1 ; SWRST while configuring!
- MOV.B #00h,&UCA0CTL0 ; UART, 8N1, LSB first
- MOV.B #81h,&UCA0CTL1 ; BRCLK = SMCLK, SWRST set
- MOV.B #41h,&UCA0BR0 ; 9600 Baud at 8 MHz
- MOV.B #03h,&UCA0BR1
- MOV.B #04h,&UCA0MCTL ; UCBRFx=0, UCBRSx=2 for 9600 baud
- BIC.B #UCSWRST,&UCA0CTL1 ; done configuring
- NEXT
diff --git a/amforth-6.5/msp430/drivers/flash.inc b/amforth-6.5/msp430/drivers/flash.inc
deleted file mode 100644
index 1c13cde..0000000
--- a/amforth-6.5/msp430/drivers/flash.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-; FLASH MEMORY OPERATIONS
-; Note that an I! or IC! to a RAM address >FLASHSTART will work -- it
-; will enable the flash, write the RAM, and then disable the flash.
-; An FLERASE to a RAM address will merely clear that one RAM cell.
-
-.include "drivers/flash/words/flerase.asm"
-
-; Program Space (Flash) operators
-
-.include "drivers/flash/words/i-store.asm"
-.include "drivers/flash/words/ic-store.asm"
-.include "drivers/flash/words/d-to-i.asm"
-
-.include "drivers/flash/words/flaligned.asm"
-.include "drivers/flash/words/save.asm"
-.include "drivers/flash/words/init-ram.asm"
diff --git a/amforth-6.5/msp430/drivers/flash/words/d-to-i.asm b/amforth-6.5/msp430/drivers/flash/words/d-to-i.asm
deleted file mode 100644
index 12081f0..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/d-to-i.asm
+++ /dev/null
@@ -1,38 +0,0 @@
-;Z D->I c-addr1 c-addr2 u -- move Data->Code
-; Block move from Data space to Code space. Flashable.
-; For the MSP430, this uses a "smart" algorithm that uses word writes,
-; rather than byte writes, whenever possible. Note that byte reads
-; are used for the source, so it need not be aligned.
- CODEHEADER(XT_DTOI,4,"d->i")
- MOV @PSP+,W ; dest adrs
- MOV @PSP+,X ; src adrs
- CMP #0,TOS
- JZ DTOI_X
-DTOI_LOOP: ; Begin flash write sequence
- DINT ; Disable interrupts
- MOV #FWKEY,&FCTL3 ; Clear LOCK
- MOV #FWKEY+WRT,&FCTL1 ; Enable write
- ; If length is 1, or dest. address is odd, do a byte write.
- ; Else, do a word write.
- CMP #1,TOS
- JZ DTOI_BYTE
- BIT #1,W
- JNZ DTOI_BYTE
-DTOI_WORD: MOV.B @X+,Y ; get low byte of word
- MOV.B @X+,Q ; get high byte of word
- SWPB Q
- BIS Q,Y ; merge bytes
- MOV Y,0(W) ; write byte to dest
- ADD #2,W
- SUB #1,TOS ; another 1 will be subtracted below
- JMP DTOI_END
-DTOI_BYTE: MOV.B @X+,0(W) ; copy byte from src to dest
- ADD #1,W
-DTOI_END: ; End flash write sequence
- MOV #FWKEY,&FCTL1 ; Done. Clear WRT.
- MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
- EINT ; Enable interrupts
- SUB #1,TOS
- JNZ DTOI_LOOP
-DTOI_X: MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/drivers/flash/words/flaligned.asm b/amforth-6.5/msp430/drivers/flash/words/flaligned.asm
deleted file mode 100644
index 9271eba..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/flaligned.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z FLALIGNED a -- a' align IDP to flash boundary
-; $200 OVER - $1FF AND + ;
- HEADER(XT_FLALIGNED,9,"flaligned",DOCOLON)
- DW XT_DOLITERAL,0200h,XT_OVER,XT_MINUS,XT_DOLITERAL,01FFh,XT_AND,XT_PLUS,XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/flash/words/flerase.asm b/amforth-6.5/msp430/drivers/flash/words/flerase.asm
deleted file mode 100644
index e8cf97e..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/flerase.asm
+++ /dev/null
@@ -1,39 +0,0 @@
-;Z FLERASE a-addr n --
- CODEHEADER(XT_FLERASE,7,"flerase")
- MOV @PSP+,W ; get address in W
- ADD W,TOS ; TOS=end adrs (first unerased adrs)
-FLE_1:
- CMP TOS,W ; adr-end
- JC FLE_X ; if no borrow, adr>=end, do not erase
- ; is it within Main flash?
- CMP #FLASHSTART,W
- JNC FLE_INFO ; if borrow, adr<start, check if Info
- CMP #FLASHEND+1,W
- JNC FLE_OK ; if no borrow, adr>end, check if Info
-FLE_INFO: ; is it within Info flash?
- CMP #INFOSTART,W
- JNC FLE_X ; if borrow, adr<start, do not erase
- CMP #INFOEND+1,W
- JC FLE_X ; if no borrow, adr>end, do not erase
-FLE_OK: ; Address is either in Main flash, or in Info flash.
- ; Segment Erase from flash.
- ; Assumes ACCVIE = NMIIE = OFIE = 0, watchdog disabled.
- ; Per section 5.3.2 of MSP430 Family User's Guide
- DINT ; Disable interrupts
- MOV #FWKEY,&FCTL3 ; Clear LOCK
- MOV #FWKEY+ERASE,&FCTL1 ; Enable segment erase
- MOV #-1,0(W) ; Dummy write in segment to erase
- MOV #FWKEY,&FCTL1 ; Done. Clear erase command.
- MOV #FWKEY+LOCK,&FCTL3 ; Done, set LOCK
- EINT ; Enable interrupts
- ; Advance flash pointer by 512 bytes or 128 bytes
- ; is it within Main flash?
- CMP #FLASHSTART,W
- JNC FL_INFO ; if borrow, adr<start, must be Info
- CMP #FLASHEND+1,W
- JC FL_INFO ; if no borrow, adr>end, must be Info
- ADD #(MAINSEG-INFOSEG),W
-FL_INFO: ADD #INFOSEG,W
- JMP FLE_1 ; continue till past end or outside limits
-FLE_X: MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/drivers/flash/words/i-store.asm b/amforth-6.5/msp430/drivers/flash/words/i-store.asm
deleted file mode 100644
index 5febc64..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/i-store.asm
+++ /dev/null
@@ -1,32 +0,0 @@
-;Z I! x a-addr -- store cell in Instruction memory
- CODEHEADER(XT_STOREI,2,"!i")
- MOV @PSP+,W ; get data to write
- BIT #1,TOS
- JNZ IST_X ; if not even address, do not write
- CMP @TOS,W
- JZ IST_X ; if memory is desired value, do not write
- ; is it within Main flash?
- CMP #FLASHSTART,TOS
- JNC IST_INFO ; if borrow, adr<start, check if Info
- CMP #FLASHEND+1,TOS
- JNC IST_OK ; if no borrow, adr>end, check if Info
-IST_INFO: ; is it within Info flash?
- CMP #INFOSTART,TOS
- JNC IST_RAM ; if borrow, adr<start, assume it's RAM
- CMP #INFOEND+1,TOS
- JC IST_RAM ; if no borrow, adr>end, assume it's RAM
-IST_OK: ; Address is either in Main flash, or in Info flash.
- ; Byte/word write from flash.
- ; Assumes location to write is already erased
- ; Assumes ACCVIE = NMIIE = OFIE = 0, watchdog disabled.
- ; Per section 5.3.3 of MSP430 Family User's Guide
- DINT ; Disable interrupts
- MOV #FWKEY,&FCTL3 ; Clear LOCK
- MOV #FWKEY+WRT,&FCTL1 ; Enable write
-IST_RAM: ; If RAM, jump here to write. FCTL1,FCTL3,EINT are superfluous
- MOV W,0(TOS) ; Write word to flash location
- MOV #FWKEY,&FCTL1 ; Done. Clear WRT.
- MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
- EINT ; Enable interrupts
-IST_X: MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/drivers/flash/words/ic-store.asm b/amforth-6.5/msp430/drivers/flash/words/ic-store.asm
deleted file mode 100644
index c8677ea..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/ic-store.asm
+++ /dev/null
@@ -1,29 +0,0 @@
-;Z IC! x a-addr -- store char in Instruction memory
- CODEHEADER(XT_CSTOREI,3,"c!i")
- MOV @PSP+,W ; get data to write
- CMP.B @TOS,W
- JZ IST_X ; if memory is desired value, do not write
- ; is it within Main flash?
- CMP #FLASHSTART,TOS
- JNC ICST_INFO ; if borrow, adr<start, check if Info
- CMP #FLASHEND+1,TOS
- JNC ICST_OK ; if no borrow, adr>end, check if Info
-ICST_INFO: ; is it within Info flash?
- CMP #INFOSTART,TOS
- JNC ICST_RAM ; if borrow, adr<start, assume it's RAM
- CMP #INFOEND+1,TOS
- JC ICST_RAM ; if no borrow, adr>end, assume it's RAM
-ICST_OK: ; Address is either in Main flash, or in Info flash.
- ; Byte/word write from flash.
- ; Assumes location to write is already erased
- ; Assumes ACCVIE = NMIIE = OFIE = 0, watchdog disabled.
- ; Per section 5.3.3 of MSP430 Family User's Guide
- DINT ; Disable interrupts
- MOV #FWKEY,&FCTL3 ; Clear LOCK
- MOV #FWKEY+WRT,&FCTL1 ; Enable write
-ICST_RAM: ; If RAM, jump here to write. FCTL1,FCTL3,EINT are superfluous
- MOV.B W,0(TOS) ; Write byte to flash location
- MOV #FWKEY,&FCTL1 ; Done. Clear WRT.
- MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
- EINT ; Enable interrupts
- JMP IST_X
diff --git a/amforth-6.5/msp430/drivers/flash/words/init-ram.asm b/amforth-6.5/msp430/drivers/flash/words/init-ram.asm
deleted file mode 100644
index 30fab64..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/init-ram.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-;Z INIT_RAM -- initialize RAM
-HEADER(XT_INIT_RAM,8,"init-ram",DOCOLON)
-; the first cell is either FFFF or the recognizer stack depth, see ram.asm
- DW XT_DOLITERAL, INFOSTART, XT_FETCH
- DW XT_ZEROLESS
- DW XT_DOCONDBRANCH
- DEST(COLD1)
-; there is no valid data in INFO flash
- DW XT_UINIT,XT_DOBRANCH
- DEST(COLD2)
-COLD1:
-; there is valid content in INFO, restore it
- DW XT_DOLITERAL, INFOSTART
-COLD2:
- DW XT_DOLITERAL,RAMINFOAREA,XT_DOLITERAL,INFO_SIZE,XT_CMOVE
- dw XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/flash/words/save.asm b/amforth-6.5/msp430/drivers/flash/words/save.asm
deleted file mode 100644
index 2e0e9c4..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/save.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-; SAVE erases the first 128 bytes of Info Flash, then
-; copies the User Area and subsequent RAM variables there.
- HEADER(SAVE,4,"SAVE",DOCOLON)
- DW XT_DOLITERAL,RAMINFOAREA
- DW XT_DOLITERAL,INFOSTART
- DW XT_DOLITERAL,INFO_SIZE
- DW XT_2DUP,XT_FLERASE,XT_DTOI,XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/flash/words/scrub.asm b/amforth-6.5/msp430/drivers/flash/words/scrub.asm
deleted file mode 100644
index 85fbe22..0000000
--- a/amforth-6.5/msp430/drivers/flash/words/scrub.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-; SCRUB erases the application area of the Program Flash,
-; and then does COLD to reset the User Variables.
- HEADER(SCRUB,5,"SCRUB",DOCOLON)
- DW XT_DOLITERAL,INFOSTART,XT_DOLITERAL,INFO_SIZE,FLERASE
- DW XT_DOLITERAL,FLASHSTART,XT_DOLITERAL,(FLASHEND-FLASHSTART),FLERASE
- DW XT_COLD,XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/fram.inc b/amforth-6.5/msp430/drivers/fram.inc
deleted file mode 100644
index 92d7674..0000000
--- a/amforth-6.5/msp430/drivers/fram.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-; FLASH MEMORY OPERATIONS
-; Note that an I! or IC! to a RAM address >FLASHSTART will work -- it
-; will enable the flash, write the RAM, and then disable the flash.
-; An FLERASE to a RAM address will merely clear that one RAM cell.
-
-; Program Space (FRAM) operators
-
-.include "drivers/fram/words/i-store.asm"
-.include "drivers/fram/words/ic-store.asm"
-.include "drivers/fram/words/d-to-i.asm"
-
-.include "drivers/fram/words/flaligned.asm"
-.include "drivers/fram/words/save.asm"
-.include "drivers/fram/words/init-ram.asm"
-
diff --git a/amforth-6.5/msp430/drivers/fram/words/d-to-i.asm b/amforth-6.5/msp430/drivers/fram/words/d-to-i.asm
deleted file mode 100644
index fdc7ef7..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/d-to-i.asm
+++ /dev/null
@@ -1,37 +0,0 @@
-;Z D->I c-addr1 c-addr2 u -- move Data->Code
-; Block move from Data space to Code space. Flashable.
-; For the MSP430, this uses a "smart" algorithm that uses word writes,
-; rather than byte writes, whenever possible. Note that byte reads
-; are used for the source, so it need not be aligned.
- CODEHEADER(XT_DTOI,4,"d->i")
- MOV @PSP+,W ; dest adrs
- MOV @PSP+,X ; src adrs
- CMP #0,TOS
- JZ DTOI_X
-DTOI_LOOP: ; Begin flash write sequence
- DINT ; Disable interrupts
- mov #0A500h, &MPUCTL0 ; Enable write access by disabling MPU
- ; If length is 1, or dest. address is odd, do a byte write.
- ; Else, do a word write.
- CMP #1,TOS
- JZ DTOI_BYTE
- BIT #1,W
- JNZ DTOI_BYTE
-DTOI_WORD: MOV.B @X+,Y ; get low byte of word
- MOV.B @X+,Q ; get high byte of word
- SWPB Q
- BIS Q,Y ; merge bytes
- MOV Y,0(W) ; write byte to dest
- ADD #2,W
- SUB #1,TOS ; another 1 will be subtracted below
- JMP DTOI_END
-DTOI_BYTE: MOV.B @X+,0(W) ; copy byte from src to dest
- ADD #1,W
-DTOI_END: ; End flash write sequence
- mov #0A501h, &MPUCTL0 ; Disable write access again
- mov.b #0, &MPUCTL0+1 ; Disable MPU access
- EINT ; Enable interrupts
- SUB #1,TOS
- JNZ DTOI_LOOP
-DTOI_X: MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/drivers/fram/words/flaligned.asm b/amforth-6.5/msp430/drivers/fram/words/flaligned.asm
deleted file mode 100644
index 9271eba..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/flaligned.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z FLALIGNED a -- a' align IDP to flash boundary
-; $200 OVER - $1FF AND + ;
- HEADER(XT_FLALIGNED,9,"flaligned",DOCOLON)
- DW XT_DOLITERAL,0200h,XT_OVER,XT_MINUS,XT_DOLITERAL,01FFh,XT_AND,XT_PLUS,XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/fram/words/i-store.asm b/amforth-6.5/msp430/drivers/fram/words/i-store.asm
deleted file mode 100644
index c4de731..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/i-store.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;Z I! x a-addr -- store cell in Instruction memory
- CODEHEADER(XT_STOREI,2,"!i")
-
- mov #0A500h, &MPUCTL0 ; Enable write access by disabling MPU
- MOV @PSP+,0(TOS)
- MOV @PSP+,TOS
- mov #0A501h, &MPUCTL0 ; Disable write access again
- mov.b #0, &MPUCTL0+1 ; Disable MPU access
-
- NEXT
diff --git a/amforth-6.5/msp430/drivers/fram/words/ic-store.asm b/amforth-6.5/msp430/drivers/fram/words/ic-store.asm
deleted file mode 100644
index dee4575..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/ic-store.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;Z IC! x a-addr -- store char in Instruction memory
- CODEHEADER(XT_CSTOREI,3,"c!i")
-
- mov #0A500h, &MPUCTL0 ; Enable write access by disabling MPU
- MOV @PSP+,W
- MOV.B W,0(TOS)
- MOV @PSP+,TOS
-
- mov #0A501h, &MPUCTL0 ; Disable write access again
- mov.b #0, &MPUCTL0+1 ; Disable MPU access
diff --git a/amforth-6.5/msp430/drivers/fram/words/init-ram.asm b/amforth-6.5/msp430/drivers/fram/words/init-ram.asm
deleted file mode 100644
index 30fab64..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/init-ram.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-;Z INIT_RAM -- initialize RAM
-HEADER(XT_INIT_RAM,8,"init-ram",DOCOLON)
-; the first cell is either FFFF or the recognizer stack depth, see ram.asm
- DW XT_DOLITERAL, INFOSTART, XT_FETCH
- DW XT_ZEROLESS
- DW XT_DOCONDBRANCH
- DEST(COLD1)
-; there is no valid data in INFO flash
- DW XT_UINIT,XT_DOBRANCH
- DEST(COLD2)
-COLD1:
-; there is valid content in INFO, restore it
- DW XT_DOLITERAL, INFOSTART
-COLD2:
- DW XT_DOLITERAL,RAMINFOAREA,XT_DOLITERAL,INFO_SIZE,XT_CMOVE
- dw XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/fram/words/save.asm b/amforth-6.5/msp430/drivers/fram/words/save.asm
deleted file mode 100644
index 96d2f0b..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/save.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-; SAVE erases the first 128 bytes of Info Flash, then
-; copies the User Area and subsequent RAM variables there.
- HEADER(SAVE,4,"SAVE",DOCOLON)
- DW XT_DOLITERAL,RAMINFOAREA
- DW XT_DOLITERAL,INFOSTART
- DW XT_DOLITERAL,INFO_SIZE
- DW XT_DTOI,XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/fram/words/scrub.asm b/amforth-6.5/msp430/drivers/fram/words/scrub.asm
deleted file mode 100644
index 85fbe22..0000000
--- a/amforth-6.5/msp430/drivers/fram/words/scrub.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-; SCRUB erases the application area of the Program Flash,
-; and then does COLD to reset the User Variables.
- HEADER(SCRUB,5,"SCRUB",DOCOLON)
- DW XT_DOLITERAL,INFOSTART,XT_DOLITERAL,INFO_SIZE,FLERASE
- DW XT_DOLITERAL,FLASHSTART,XT_DOLITERAL,(FLASHEND-FLASHSTART),FLERASE
- DW XT_COLD,XT_EXIT
diff --git a/amforth-6.5/msp430/drivers/usart_a0.inc b/amforth-6.5/msp430/drivers/usart_a0.inc
deleted file mode 100644
index 9ee8710..0000000
--- a/amforth-6.5/msp430/drivers/usart_a0.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-
-.set USART_TX_DATA=UCA0TXBUF
-.set USART_RX_DATA=UCA0RXBUF
-.set USART_TX_CFG=IFG2
-.set USART_RX_CFG=IFG2
-
-; UCAxTXIFG is set if transmit is completed, i.e. ready for the next char
-.set bm_USART_TXRD = UCA0TXIFG
-; UCAxRXIFG is set if an unread character is in the input buffer
-.set bm_USART_RXRD = UCA0RXIFG
-
-.include "words/usart-tx.asm"
-.include "words/usart-txq.asm"
-.include "words/usart-rx.asm"
-.include "words/usart-rxq.asm"
-;.include "words/usart-emit.asm"
-;.include "words/usart-key.asm"
-;.include "words/usart-keyq.asm"
-.include "words/usart-init.asm"
diff --git a/amforth-6.5/msp430/drivers/usart_a1.inc b/amforth-6.5/msp430/drivers/usart_a1.inc
deleted file mode 100644
index 0b7feb9..0000000
--- a/amforth-6.5/msp430/drivers/usart_a1.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-
-.set USART_TX_DATA=UCA1TXBUF
-.set USART_RX_DATA=UCA1RXBUF
-.set USART_TX_CFG=UCA1IFG
-.set USART_RX_CFG=UCA1IFG
-
-.set bm_USART_TXRD = UCTXIFG
-.set bm_USART_RXRD = UCRXIFG
-
-.include "words/usart-tx.asm"
-.include "words/usart-txq.asm"
-.include "words/usart-rx.asm"
-.include "words/usart-rxq.asm"
-;.include "words/usart-emit.asm"
-;.include "words/usart-key.asm"
-;.include "words/usart-keyq.asm"
-.include "words/usart-init.asm"
diff --git a/amforth-6.5/msp430/drivers/usart_f-a0.inc b/amforth-6.5/msp430/drivers/usart_f-a0.inc
deleted file mode 100644
index da0a0d8..0000000
--- a/amforth-6.5/msp430/drivers/usart_f-a0.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-
-.set USART_TX_DATA=UCA0TXBUF
-.set USART_RX_DATA=UCA0RXBUF
-.set USART_TX_CFG=UCA0IFG
-.set USART_RX_CFG=UCA0IFG
-
-; UCAxTXIFG is set if transmit is completed, i.e. ready for the next char
-.set bm_USART_TXRD = UCTXIFG
-; UCAxRXIFG is set if an unread character is in the input buffer
-.set bm_USART_RXRD = UCRXIFG
-
-.include "words/usart-tx.asm"
-.include "words/usart-txq.asm"
-.include "words/usart-rx.asm"
-.include "words/usart-rxq.asm"
-;.include "words/usart-emit.asm"
-;.include "words/usart-key.asm"
-;.include "words/usart-keyq.asm"
-.include "words/usart-init.asm"
diff --git a/amforth-6.5/msp430/epilogue.asm b/amforth-6.5/msp430/epilogue.asm
deleted file mode 100644
index 21bffef..0000000
--- a/amforth-6.5/msp430/epilogue.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-; ----------------------------------------------------------------------
-; END OF FORTH KERNEL
-
-.set lastword = link ; last word in dictionary
-.set lastenv = envlink
-
-END
diff --git a/amforth-6.5/msp430/itc430core.asm b/amforth-6.5/msp430/itc430core.asm
deleted file mode 100644
index 1d84882..0000000
--- a/amforth-6.5/msp430/itc430core.asm
+++ /dev/null
@@ -1,129 +0,0 @@
-; --------------------------------------
-; include all assembly primitves first
-
-.include "words/execute.asm"
-.include "words/lit.asm"
-.include "words/exit.asm"
-.include "words/variable.asm"
-.include "words/constant.asm"
-
-.include "words/do-variable.asm"
-.include "words/do-constant.asm"
-.include "words/do-does.asm"
-.include "words/user.asm"
-
-; ----------------------------------------------------------------------
-; STACK OPERATIONS
-
-.include "words/dup.asm"
-.include "words/qdup.asm"
-.include "words/drop.asm"
-.include "words/swap.asm"
-.include "words/over.asm"
-.include "words/rot.asm"
-.include "words/nip.asm"
-.include "words/tuck.asm"
-
-.include "words/to-r.asm"
-.include "words/r-from.asm"
-.include "words/r-fetch.asm"
-.include "words/2-to-r.asm"
-.include "words/2-r-from.asm"
-
-.include "words/sp-fetch.asm"
-.include "words/sp-store.asm"
-.include "words/rp-fetch.asm"
-.include "words/rp-store.asm"
-
-
-; ----------------------------------------------------------------------
-; MEMORY OPERATIONS
-
-.include "words/fetch.asm"
-.include "words/store.asm"
-.include "words/c-fetch.asm"
-.include "words/c-store.asm"
-
-
-; ----------------------------------------------------------------------
-; ARITHMETIC OPERATIONS
-
-.include "words/plus.asm"
-.include "words/plus-store.asm"
-.include "words/m-plus.asm"
-.include "words/minus.asm"
-.include "words/and.asm"
-.include "words/or.asm"
-.include "words/xor.asm"
-.include "words/invert.asm"
-.include "words/negate.asm"
-.include "words/1-plus.asm"
-.include "words/1-minus.asm"
-.include "words/byte-swap.asm"
-.include "words/2-star.asm"
-.include "words/2-slash.asm"
-.include "words/lshift.asm"
-.include "words/rshift.asm"
-
-; ----------------------------------------------------------------------
-; COMPARISON OPERATIONS
-
-.include "words/zero-equal.asm"
-.include "words/zero-less.asm"
-.include "words/equal.asm"
-.include "words/not-equal.asm"
-.include "words/less.asm"
-.include "words/greater.asm"
-.include "words/u-less.asm"
-.include "words/u-greater.asm"
-
-; ----------------------------------------------------------------------
-; LOOP AND BRANCH OPERATIONS
-
-.include "words/branch.asm"
-.include "words/q-branch.asm"
-.include "words/do-do.asm"
-.include "words/do-loop.asm"
-.include "words/do-plusloop.asm"
-.include "words/i.asm"
-.include "words/j.asm"
-.include "words/unloop.asm"
-
-; ----------------------------------------------------------------------
-; MULTIPLY AND DIVIDE
-
-.include "words/um-star.asm"
-.include "words/um-slash-mod.asm"
-
-; ----------------------------------------------------------------------
-; BLOCK AND STRING OPERATIONS
-
-.include "words/fill.asm"
-.include "words/cmove.asm"
-.include "words/cmove-up.asm"
-.include "words/cskip.asm"
-.include "words/cscan.asm"
-.include "words/s-equal.asm"
-
-; ----------------------------------------------------------------------
-; ALIGNMENT AND PORTABILITY OPERATORS
-; Many of these are synonyms for other words,
-; and so are defined as CODE words.
-.include "words/align.asm"
-.include "words/aligned.asm"
-.include "words/cellplus.asm"
-.include "words/cells.asm"
-.include "words/to-body.asm"
-.include "words/up.asm"
-
-; --------------------------------------------
-; Interrupt routines
-;
-.if WANT_INTERRUPTS==1
-.include "words/int-on.asm"
-.include "words/int-off.asm"
-.include "words/int-trap.asm"
-.include "words/int-fetch.asm"
-.include "words/int-store.asm"
-.include "words/isr-exec.asm"
-.endif \ No newline at end of file
diff --git a/amforth-6.5/msp430/itc430hilvl.asm b/amforth-6.5/msp430/itc430hilvl.asm
deleted file mode 100644
index 36f46e6..0000000
--- a/amforth-6.5/msp430/itc430hilvl.asm
+++ /dev/null
@@ -1,226 +0,0 @@
-; ----------------------------------------------------------------------
-; most highlevel words for the core system.
-
-; INPUT/OUTPUT ==================================
-.include "words/cr.asm"
-.include "words/space.asm"
-.include "words/spaces.asm"
-.include "words/umin.asm"
-.include "words/umax.asm"
-.include "words/accept.asm"
-.include "words/type.asm"
-
-; SYSTEM VARIABLES & CONSTANTS ==================
-
-.include "words/a-to-info.asm"
-.include "words/to-in.asm"
-.include "words/base.asm"
-.include "words/state.asm"
-.include "words/dp.asm"
-.include "words/get-current.asm"
-.include "words/hld.asm"
-.include "words/lp.asm"
-.include "words/idp.asm"
-.include "words/newest.asm"
-.include "words/latest.asm"
-.include "words/allot.asm"
-
-.include "words/pad.asm"
-.include "words/l-0.asm"
-.include "words/r-0.asm"
-.include "words/s-0.asm"
-.include "words/tib.asm"
-.include "words/bl.asm"
-.include "words/to-upper.asm"
-.include "words/uinit.asm"
-
-; ARITHMETIC OPERATORS ==========================
-.include "words/s-to-d.asm"
-.include "words/q-negate.asm"
-.include "words/abs.asm"
-.include "words/dnegate.asm"
-.include "words/q-dnegate.asm"
-.include "words/dabs.asm"
-.include "words/m-star.asm"
-.include "words/sm-rem.asm"
-.include "words/fm-mod.asm"
-.include "words/star.asm"
-.include "words/slash-mod.asm"
-.include "words/slash.asm"
-.include "words/mod.asm"
-.include "words/max.asm"
-.include "words/min.asm"
-
-; DOUBLE OPERATORS ==============================
-.include "words/2drop.asm"
-.include "words/2dup.asm"
-.include "words/2swap.asm"
-
-
-; HARVARD MODEL EXTENSIONS (split Code & Data)
-.include "words/icount.asm"
-.include "words/itype.asm"
-.include "words/do-squote.asm"
-.include "words/squote.asm"
-.include "words/dot-quote.asm"
-.include "words/sliteral.asm"
-.include "words/2literal.asm"
-.include "words/i-fetch.asm"
-.include "words/ic-fetch.asm"
-; NUMERIC OUTPUT ================================
-.include "words/ud-slash-mod.asm"
-.include "words/ud-star.asm"
-.include "words/hold.asm"
-.include "words/less-sharp.asm"
-.include "words/sharp.asm"
-.include "words/sharp-s.asm"
-.include "words/sharp-greater.asm"
-.include "words/sign.asm"
-.include "words/u-dot.asm"
-.include "words/dot.asm"
-.include "words/decimal.asm"
-.include "words/hex.asm"
-.include "words/bounds.asm"
-.include "words/pick.asm"
-
-; DICTIONARY MANAGEMENT =========================
-.include "words/here.asm"
-.include "words/comma.asm"
-.include "words/c-comma.asm"
-.include "words/i-here.asm"
-.include "words/i-allot.asm"
-
-; INTERPRETER ===================================
-.include "words/source.asm"
-.include "words/slash-string.asm"
-.include "words/parse.asm"
-.include "words/nfa-to-lfa.asm"
-.include "words/nfa-to-cfa.asm"
-.include "words/name2flags.asm"
-.include "words/immediate-q.asm"
-.include "words/find-xt.asm"
-.include "words/literal.asm"
-.include "words/digit-q.asm"
-.include "words/q-sign.asm"
-.include "words/set-base.asm"
-.include "words/to-number.asm"
-.include "words/number.asm"
-.include "words/forth-recognizer.asm"
-.include "words/interpret.asm"
-.include "words/prompt-ok.asm"
-.include "words/prompt-ready.asm"
-.include "words/prompt-error.asm"
-.include "words/refill.asm"
-.include "words/quit.asm"
-.include "words/abort.asm"
-.include "words/q-abort.asm"
-.include "words/abort-string.asm"
-.include "words/tick.asm"
-.include "words/char.asm"
-.include "words/bracketchar.asm"
-.include "words/l-paren.asm"
-
-; COMPILER ======================================
-.include "words/header.asm"
-.include "words/create.asm"
-.include "words/do-create.asm"
-.include "words/wlscope.asm"
-.include "words/does.asm"
-.include "words/recurse.asm"
-.include "words/left-bracket.asm"
-.include "words/right-bracket.asm"
-.include "words/reveal.asm"
-.include "words/colon.asm"
-.include "words/colon-noname.asm"
-.include "words/semicolon.asm"
-.include "words/brackettick.asm"
-.include "words/postpone.asm"
-.include "words/i-cellplus.asm"
-.include "words/immediate.asm"
-
-; EXCEPTIONS ======================
-.include "words/catch.asm"
-.include "words/handler.asm"
-.include "words/throw.asm"
-
-; CONTROL STRUCTURES ============================
-.include "words/g-resolve.asm"
-.include "words/g-mark.asm"
-.include "words/l-resolve.asm"
-.include "words/l-mark.asm"
-.include "words/compile.asm"
-
-.include "words/ahead.asm"
-.include "words/if.asm"
-.include "words/then.asm"
-.include "words/else.asm"
-.include "words/begin.asm"
-.include "words/until.asm"
-.include "words/again.asm"
-.include "words/while.asm"
-.include "words/repeat.asm"
-.include "words/to-l.asm"
-.include "words/l-from.asm"
-.include "words/do.asm"
-.include "words/qdo.asm"
-.include "words/endloop.asm"
-.include "words/loop.asm"
-.include "words/plusloop.asm"
-.include "words/leave.asm"
-
-; OTHER OPERATIONS ==============================
-.include "words/within.asm"
-.include "words/depth.asm"
-
-; UTILITY WORDS AND STARTUP =====================
-.include "words/words.asm"
-.include "words/traverse-wordlist.asm"
-.include "words/name2string.asm"
-.include "words/show-wordlist.asm"
-.include "words/u-dot-r.asm"
-.include "words/ud-dot.asm"
-.include "words/ud-dot-r.asm"
-.include "words/dot-r.asm"
-.include "words/d-dot.asm"
-.include "words/d-dot-r.asm"
-.include "words/cold.asm"
-.include "words/pause.asm"
-.include "words/warm.asm"
-.include "words/applturnkey.asm" ; from application!
-.include "words/environment.asm"
-.include "words/env-mcu-info.asm"
-.include "words/env-cpu.asm"
-.include "words/env-forthname.asm"
-.include "words/env-forthversion.asm"
-.include "words/ver.asm"
-.include "words/f_cpu.asm"
-.include "words/q-stack.asm"
-
-.include "words/backslash.asm"
-.include "words/parse-name.asm"
-.include "words/map-stack.asm"
-.include "words/recognize.asm"
-.include "words/dt-null.asm"
-.include "words/rec-find.asm"
-.include "words/rec-intnum.asm"
-
-.include "words/scomma.asm"
-.include "words/compare.asm"
-.include "words/search-wordlist.asm"
-.include "words/num-constants.asm"
-
-.include "words/do-defer.asm"
-.include "words/do-value.asm"
-.include "words/turnkey.asm"
-.include "words/to.asm"
-.include "words/defer-fetch.asm"
-.include "words/defer-store.asm"
-.include "words/noop.asm"
-.include "words/rdefer-fetch.asm"
-.include "words/rdefer-store.asm"
-.include "words/udefer-fetch.asm"
-.include "words/udefer-store.asm"
-.include "words/emit.asm"
-.include "words/emitq.asm"
-.include "words/key.asm"
-.include "words/keyq.asm"
diff --git a/amforth-6.5/msp430/lib/forth-2012/core-ext.frt b/amforth-6.5/msp430/lib/forth-2012/core-ext.frt
deleted file mode 100644
index a7ea6d6..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core-ext.frt
+++ /dev/null
@@ -1,12 +0,0 @@
-\ 'core-ext.frt' generated automatically, do not edit
-#include case.frt
-\ #include case-test.frt
-\ #include exceptions.frt
-#include marker.frt
-\ #include marker-test.frt
-
-\ update the environment
-\ get-current environment set-current
-\ : core-ext 0 ;
-\ reset the definition word list
-\ set-current
diff --git a/amforth-6.5/msp430/lib/forth-2012/core-ext/marker.frt b/amforth-6.5/msp430/lib/forth-2012/core-ext/marker.frt
deleted file mode 100644
index b4e47d3..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core-ext/marker.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-\ dummy marker
-: marker create ; \ No newline at end of file
diff --git a/amforth-6.5/msp430/lib/forth-2012/core.frt b/amforth-6.5/msp430/lib/forth-2012/core.frt
deleted file mode 100644
index f838dfc..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ 'core.frt' generated automatically, do not edit
-#include 2over.frt
-#include 2swap.frt
-#include blank.frt
-#include c-comma.frt
-#include char-plus.frt
-#include chars.frt
-#include dot-paren.frt
-#include environment-q.frt
-#include erase.frt
-#include evaluate.frt
-#include star-slash.frt
-#include move.frt
-#include source-id.frt
-#include find.frt
-
-\ update the environment
-get-current environment set-current
-: core -1 ;
-\ reset the definition word list
-set-current
diff --git a/amforth-6.5/msp430/lib/forth-2012/core/c-comma.frt b/amforth-6.5/msp430/lib/forth-2012/core/c-comma.frt
deleted file mode 100644
index 8741509..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core/c-comma.frt
+++ /dev/null
@@ -1,5 +0,0 @@
-
-\ only a dummy file for certain use cases like
-\ the hayes tester. The actual definition is
-\ already in the words/ directory
-
diff --git a/amforth-6.5/msp430/lib/forth-2012/core/environment-q.frt b/amforth-6.5/msp430/lib/forth-2012/core/environment-q.frt
deleted file mode 100644
index 3ba440f..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core/environment-q.frt
+++ /dev/null
@@ -1,28 +0,0 @@
-\ environment queries are placed in a
-\ separate wordlist.
-
-: environment? \ addr len -- 0|x*i -1
- environment search-wordlist dup
- if >r execute r> then
-;
-
-\ some environment queries
-
-\ save the definitions word list for this file
-\ and switch to the environment queries wordlist
-get-current environment set-current
-
-: /counted-strings &60 ;
-: floored 0 ;
-: address-unit-bits $10 ;
-: max-char $ff ;
-: max-d $7fffffff. ;
-: max-ud $ffffffff. ;
-: max-n $7fff ;
-: max-u $ffff ;
-
-: return-stack-cells &10 ;
-: stack-cells &10 ;
-
-\ reset the definition word list
-set-current
diff --git a/amforth-6.5/msp430/lib/forth-2012/core/evaluate.frt b/amforth-6.5/msp430/lib/forth-2012/core/evaluate.frt
deleted file mode 100644
index 9f4cf3b..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core/evaluate.frt
+++ /dev/null
@@ -1,22 +0,0 @@
-\ evaluate
-\ temporarily redirect the input source
-\ to string buffer. Return the the previous
-\ input source afterwards and continue
-
-\ some helper words
-variable strlen
-variable str
-: source-string str @ strlen @ ;
-
-: evaluate \ i*x addr len -- j*y
- ['] source defer@ >r
- >in @ >r
- 0 >in !
- strlen !
- str !
- ['] source-string to source
- ['] interpret catch
- r> >in !
- r> to source
- throw
-;
diff --git a/amforth-6.5/msp430/lib/forth-2012/core/star-slash-mod.frt b/amforth-6.5/msp430/lib/forth-2012/core/star-slash-mod.frt
deleted file mode 100644
index 741b4cd..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core/star-slash-mod.frt
+++ /dev/null
@@ -1,6 +0,0 @@
-
-\ MSP has another division type
-
-: */mod ( )
- >r m* r> fm/mod
-;
diff --git a/amforth-6.5/msp430/lib/forth-2012/core/value.frt b/amforth-6.5/msp430/lib/forth-2012/core/value.frt
deleted file mode 100644
index 41a7e70..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/core/value.frt
+++ /dev/null
@@ -1,9 +0,0 @@
-\ the value (in RAM)
-
-: value ( n -- )
- (value)
- here , \ compile the RAM address
- ['] @ ,
- ['] ! ,
- here ! 2 allot
-;
diff --git a/amforth-6.5/msp430/lib/forth-2012/double/d-invert.frt b/amforth-6.5/msp430/lib/forth-2012/double/d-invert.frt
deleted file mode 100644
index c951d59..0000000
--- a/amforth-6.5/msp430/lib/forth-2012/double/d-invert.frt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-: dinvert
- swap invert swap invert
-;
diff --git a/amforth-6.5/msp430/lib/int-q.frt b/amforth-6.5/msp430/lib/int-q.frt
deleted file mode 100644
index 828562e..0000000
--- a/amforth-6.5/msp430/lib/int-q.frt
+++ /dev/null
@@ -1,3 +0,0 @@
-
-\ get the GIE flag from status register
-: int? sr@ 8 and 0> ;
diff --git a/amforth-6.5/msp430/lib/run-hayes.frt b/amforth-6.5/msp430/lib/run-hayes.frt
deleted file mode 100644
index c586e95..0000000
--- a/amforth-6.5/msp430/lib/run-hayes.frt
+++ /dev/null
@@ -1,26 +0,0 @@
-\
-\ process this file with amforth-upload.py and
-\ the proper setting of $AMFORTH_LIB (basedir of
-\ you amforth file tree)
-\ WIN (untested, DOS Box)
-\ cd c:\amforth-x.y
-\ set AMFORTH_LIB=c:\amforth-x.y
-\ python tools\amforth-upload.py -t com1: examples\run-hayes.frt
-\ UNIX / MAC (Terminal)
-\ cd $HOME/amforth-x.y
-\ export AMFORTH_LIB=$HOME/amforth-x.y
-\ tools/amforth-upload.py -t /dev/ttyUSB0 examples/run-hayes.frt
-\ enjoy!
-\
-\ it is meant to be run on a newly flashed
-\ controller, e.g. all the dict_* are included
-\
-
-\ include all sources
-#include core.frt
-#include double.frt
-#include marker.frt
-#include tester-amforth.frt
-\ and finally run all the tests
-
-#include core.fr
diff --git a/amforth-6.5/msp430/macros.asm b/amforth-6.5/msp430/macros.asm
deleted file mode 100644
index 2869474..0000000
--- a/amforth-6.5/msp430/macros.asm
+++ /dev/null
@@ -1,150 +0,0 @@
-; ----------------------------------------------------------------------
-; CamelForth for the Texas Instruments MSP430
-; (c) 2009,2014 Bradford J. Rodriguez.
-;
-; This program is free software; you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-;
-; Commercial inquiries should be directed to the author at
-; 115 First St., #105, Collingwood, Ontario L9Y 4W3 Canada
-; or via email to bj@camelforth.com
-; ----------------------------------------------------------------------
-; itc430.h: Register, Model, and Macro declarations -
-; MSP430, Indirect Threaded Code
-; B. Rodriguez 3 Jan 09
-; ----------------------------------------------------------------------
-; Revision History
-; 27 feb 14 bjr - adapted from msp430/forth.h for naken_asm.
-; 26 oct 12 bjr - moved memory usage defines to init430 file.
-; 1 mar 09 bjr - added INFOSTART, changed FLASHSTART to be Main flash address
-; 17 jan 09 bjr - changed IMMEDIATE flag from $00 to $FE to allow
-; use as a token field.
-
-cpu_msp430 EQU 1
-cpu_avr8 EQU 0
-
-
-; FORTH REGISTER USAGE
-
-; Forth virtual machine
-#define RSP SP
-#define PSP R4
-#define IP R5
-#define W R6
-#define TOS R7
-
-#define UP R14 ; User pointer
-#define REG_A R13 ; extended VM register A
-
-#define ISR R15 ; current interrupt index
-
-; Loop parameters in registers
-#define INDEX R8
-#define LIMIT R9
-
-; Scratch registers
-#define X R10
-#define Y R11
-#define Q R12
-
-; T.I. Integer Subroutines Definitions
-#define IROP1 TOS
-#define IROP2L R10
-#define IROP2M R11
-#define IRACL R12
-#define IRACM R13 ; same as reg-a, used in um* only
-#define IRBT W
-
-; INDIRECT-THREADED NEXT
-
-.macro NEXT
-.if WANT_INTERRUPTS==1
- MOV #DO_NEXT, PC
-.else
- MOV @IP+,W ; fetch word address into W
- MOV @W+,PC ; fetch code address into PC, W=PFA
-.endif
-.endm
-
-; BRANCH DESTINATION (RELATIVE BRANCH)
-; For relative branch addresses, i.e., a branch is ADD @IP,IP
-
-.macro DEST(label)
- DW label-$
-.endm
-
-; HEADER CONSTRUCTION MACROS
-
-.macro HEADER(asmname,length,litname,action)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB length
- DB litname
- .align 16
-asmname: DW action
-.endm
-
-.macro CODEHEADER(asmname,length,litname)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB length
- DB litname
- .align 16
-asmname: DW $+2
-.endm
-
-.macro HEADLESS(asmname,action)
-asmname: DW action
-.endm
-
-.macro IMMED(asmname,length,litname,action)
- DW link
- DB 0FEh ; immediate
-.set link = $
- DB length
- DB litname
- .align 16
-asmname: DW action
-.endm
-
-.macro ENVIRONMENT(asmname,length,litname)
- DW envlink
- DB 0FFh ; not immediate
-.set envlink = $
- DB length
- DB litname
- .align 16
-asmname: DW DOCOLON
-.endm
-
-.macro DEFER(asmname,length,litname)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB length
- DB litname
- .align 16
-asmname: DW DODEFER
-.endm
-
-.macro VARIABLE(asmname,length,litname)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB length
- DB litname
- .align 16
-asmname: DW PFA_DOVARIABLE
-.endm
diff --git a/amforth-6.5/msp430/preamble.inc b/amforth-6.5/msp430/preamble.inc
deleted file mode 100644
index 60275f9..0000000
--- a/amforth-6.5/msp430/preamble.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-; default settings for various options
-; override them in the application specific
-; control file. Do not edit this file.
-
-; enable interrupt support. Still WiP thus disabled by default
-.set WANT_INTERRUPTS = 0
-
-; end of customization option
-
-; header links
-.set link = 0
-.set envlink = 0
-
-.include "device.asm"
-.include "compat.inc"
-.include "user.inc"
-
diff --git a/amforth-6.5/msp430/ram.inc b/amforth-6.5/msp430/ram.inc
deleted file mode 100644
index b78e0b5..0000000
--- a/amforth-6.5/msp430/ram.inc
+++ /dev/null
@@ -1,54 +0,0 @@
-; ----------------------------------------------------------------------
-; RAM DATA AREAS
-
-.org RAMSTART
-
-; initialized from info flash
-RAMINFOAREA: ; 128 byte copy from INFO flash or uinit defaults
-CFG_RECOGNIZERLISTLEN: ; RECOGNIZER stack, must be first cell for init-ram.
- DS16 5 ; room for the count word and 4 slots
-CFG_ORDERLISTLEN: ; ORDER stack
- DS16 9 ; room for the count word and 8 slots
-CFG_TURNKEY: DS16 1 ; deferred startup action
-CFG_DP: DS16 1 ; data space pointer (HERE)
-CFG_IDP: DS16 1 ; code space pointer (dictionary)
-CFG_INFODP: DS16 1 ; Info Flash pointer
-CFG_CURRENT: DS16 1 ; Place for new words (CREATE)
-CFG_FORTHWID:DS16 1 ; the Forth wordlist
-CFG_ENVWID: DS16 1 ; wordlist id for environment queries
-CFG_WLSCOPE: DS16 1 ; wordlist scope (wlscope)
-CFG_FORTHRECOGNIZER: DS16 1 ; standard recognizer stack
-.if WANT_INTERRUPTS == 1
-
-CFG_ISRVECS: DS16 10 ; 10 ISR addresses
-
-.endif
-
-; default USER area comes from info flash or, if invalid from uinit.
-UAREA: DS8 SYSUSERSIZE ; standard user area
-APPUSER: DS8 APPUSERSIZE ; not initalized from uinit.
-
-INFODICT:
-
-; leave room for more info-savable data.
-.org (RAMSTART+INFO_SIZE)
-
-; initalized at runtime (e.g. COLD or <# )
-RAM_PAUSE: DS16 1 ; defered multitasker
-RAM_STATE: DS16 1 ; global interpreter state
-RAM_HLD: DS16 1 ; hold pointer
-RAM_LP: DS16 1 ; leave stack pointer
-RAM_NEWEST: DS16 2 ; currently active wordlist entry (NT and WID)
-RAM_LATEST: DS16 1 ; currently active colon definition (XT)
-RAM_NUMBERTIB: DS16 1 ; number of input data
-
-
-; buffer region
-TIBAREA: DS8 TIB_SIZE ; Terminal Input Buffer
-LSTACK: DS16 PSTACK_SIZE ; leave stack grows up into PSTACK area
-PSTACK: DS16 RSTACK_SIZE ; data stack grows downward
-RSTACK: ; end of return stack area
-
-RAMDICT: ; start value for DP / HERE.
-
-ROMDICT EQU FLASHSTART ; use Flash ROM for program dictionary
diff --git a/amforth-6.5/msp430/tools/99-msp430.rules b/amforth-6.5/msp430/tools/99-msp430.rules
deleted file mode 100644
index 1c56a20..0000000
--- a/amforth-6.5/msp430/tools/99-msp430.rules
+++ /dev/null
@@ -1 +0,0 @@
-ATTRS{idVendor}=="0451", ATTRS{idProduct}=="f430", MODE="0660", GROUP="plugdev"
diff --git a/amforth-6.5/msp430/user.inc b/amforth-6.5/msp430/user.inc
deleted file mode 100644
index 47a8995..0000000
--- a/amforth-6.5/msp430/user.inc
+++ /dev/null
@@ -1,25 +0,0 @@
-; Layout of the user area
-;
-
- USER_STATE EQU 0 ; the task state, not the interpreter state
- USER_FOLLOWER EQU 2 ; used by multitasker
- USER_RP EQU 4
- USER_SP0 EQU 6
- USER_SP EQU 8
- USER_HANDLER EQU 10
- USER_BASE EQU 12
-
- USER_EMIT EQU 14
- USER_EMITQ EQU 16
- USER_KEY EQU 18
- USER_KEYQ EQU 20
-
- USER_SOURCE EQU 22
- USER_TO_IN EQU 24
- USER_REFILL EQU 26
-
-USER_P_OK EQU 28
-USER_P_ERR EQU 30
-USER_P_RDY EQU 32
-
- SYSUSERSIZE EQU 34
diff --git a/amforth-6.5/msp430/words/1-minus.asm b/amforth-6.5/msp430/words/1-minus.asm
deleted file mode 100644
index 6c71cc7..0000000
--- a/amforth-6.5/msp430/words/1-minus.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C 1- n1/u1 -- n2/u2 subtract 1 from TOS
- CODEHEADER(XT_1MINUS,2,"1-")
- SUB #1,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/1-plus.asm b/amforth-6.5/msp430/words/1-plus.asm
deleted file mode 100644
index c9d78d2..0000000
--- a/amforth-6.5/msp430/words/1-plus.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C 1+ n1/u1 -- n2/u2 add 1 to TOS
- CODEHEADER(XT_1PLUS,2,"1+")
- ADD #1,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/2-r-from.asm b/amforth-6.5/msp430/words/2-r-from.asm
deleted file mode 100644
index 16ea605..0000000
--- a/amforth-6.5/msp430/words/2-r-from.asm
+++ /dev/null
@@ -1,9 +0,0 @@
-;C 2R> -- d R: d -- pop from return stack
- CODEHEADER(XT_2R_FROM,3,"2r>")
- SUB #4,PSP ; 2
- MOV TOS,2(PSP) ; 4
- MOV @RSP+,TOS
- MOV @RSP+,W
- MOV W,0(PSP) ; 4
-
- NEXT
diff --git a/amforth-6.5/msp430/words/2-slash.asm b/amforth-6.5/msp430/words/2-slash.asm
deleted file mode 100644
index 79abf8e..0000000
--- a/amforth-6.5/msp430/words/2-slash.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C 2/ x1 -- x2 arithmetic right shift
- CODEHEADER(XT_2SLASH,2,"2/")
- RRA TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/2-star.asm b/amforth-6.5/msp430/words/2-star.asm
deleted file mode 100644
index 471dc56..0000000
--- a/amforth-6.5/msp430/words/2-star.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C 2* x1 -- x2 arithmetic left shift
- CODEHEADER(XT_2STAR,2,"2*")
- ADD TOS,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/2-to-r.asm b/amforth-6.5/msp430/words/2-to-r.asm
deleted file mode 100644
index b7e38a2..0000000
--- a/amforth-6.5/msp430/words/2-to-r.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-;C 2>R d -- R: -- d push to return stack
- CODEHEADER(XT_2TO_R,3,"2>r")
- MOV @PSP+,W
- PUSH W
- PUSH TOS
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/a-to-info.asm b/amforth-6.5/msp430/words/a-to-info.asm
deleted file mode 100644
index 302e2fe..0000000
--- a/amforth-6.5/msp430/words/a-to-info.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-; convert a RAM address into an INFO flash address
-; base a>info @ may be 0 or another value
- HEADER(XT_ADDR_TO_INFO,6,"a>info",DOCOLON)
-
- .dw XT_DOLITERAL, INFOSTART, XT_DOLITERAL,RAMINFOAREA,XT_MINUS,XT_PLUS,XT_EXIT
diff --git a/amforth-6.5/msp430/words/align.asm b/amforth-6.5/msp430/words/align.asm
deleted file mode 100644
index a9ba1a5..0000000
--- a/amforth-6.5/msp430/words/align.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C ALIGN -- align HERE
-; IHERE 1 AND IALLOT ;
- HEADER(XT_ALIGN,5,"align",DOCOLON)
- DW XT_IHERE,XT_ONE,XT_AND,XT_IALLOT,XT_EXIT
diff --git a/amforth-6.5/msp430/words/aligned.asm b/amforth-6.5/msp430/words/aligned.asm
deleted file mode 100644
index dfdd37b..0000000
--- a/amforth-6.5/msp430/words/aligned.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C ALIGNED addr -- a-addr align given addr
-; DUP 1 AND + ;
- HEADER(XT_ALIGNED,7,"aligned",DOCOLON)
- DW XT_DUP,XT_ONE,XT_AND,XT_PLUS,XT_EXIT
diff --git a/amforth-6.5/msp430/words/allot.asm b/amforth-6.5/msp430/words/allot.asm
deleted file mode 100644
index 50b80d8..0000000
--- a/amforth-6.5/msp430/words/allot.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C ALLOT n -- allocate n bytes in dict
-; DP +! ;
- HEADER(XT_ALLOT,5,"allot",DOCOLON)
- DW XT_DP,XT_PLUSSTORE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/and.asm b/amforth-6.5/msp430/words/and.asm
deleted file mode 100644
index 7bc3533..0000000
--- a/amforth-6.5/msp430/words/and.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C AND x1 x2 -- x3 logical AND
- CODEHEADER(XT_AND,3,"and")
- AND @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/bm-clear.asm b/amforth-6.5/msp430/words/bm-clear.asm
deleted file mode 100644
index 4cffa1d..0000000
--- a/amforth-6.5/msp430/words/bm-clear.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;Z CCLRB c c-addr -- clear bits in memory byte
- CODEHEADER(XT_BM_CLEAR,8,"bm-clear")
- MOV @PSP+,W
- BIC.B W,0(TOS)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/bm-set.asm b/amforth-6.5/msp430/words/bm-set.asm
deleted file mode 100644
index ac7a071..0000000
--- a/amforth-6.5/msp430/words/bm-set.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;Z CSETB c c-addr -- set bits in memory byte
- CODEHEADER(XT_BM_SET,6,"bm-set")
- MOV @PSP+,W
- BIS.B W,0(TOS)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/bm-test.asm b/amforth-6.5/msp430/words/bm-test.asm
deleted file mode 100644
index ce9ec0d..0000000
--- a/amforth-6.5/msp430/words/bm-test.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;Z CTSTB c c-addr -- c2 test bits in memory byte
- CODEHEADER(XT_BM_TEST,5,"bm-test")
- MOV.B @TOS,TOS
- AND @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/branch.asm b/amforth-6.5/msp430/words/branch.asm
deleted file mode 100644
index 8424672..0000000
--- a/amforth-6.5/msp430/words/branch.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z branch -- branch always
- CODEHEADER(XT_DOBRANCH,6,"branch")
-dobran: ADD @IP,IP ; 2
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/byte-swap.asm b/amforth-6.5/msp430/words/byte-swap.asm
deleted file mode 100644
index 23cd9e7..0000000
--- a/amforth-6.5/msp430/words/byte-swap.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z >< x1 -- x2 swap bytes (not ANSI)
- CODEHEADER(XT_SWAPBYTES,2,"><")
- SWPB TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/c-comma.asm b/amforth-6.5/msp430/words/c-comma.asm
deleted file mode 100644
index 5064768..0000000
--- a/amforth-6.5/msp430/words/c-comma.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;C IC, char -- append char to Code dict
-; XT_IHERE IC! 1 CHARS IALLOT ;
- ; HEADER(ICCOMMA,3,"IC,",DOCOLON)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB 2,"c,"
- .align 16
-XT_CCOMMA: DW DOCOLON
- DW XT_IHERE,XT_CSTOREI,XT_ONE,XT_IALLOT,XT_EXIT
diff --git a/amforth-6.5/msp430/words/c-fetch.asm b/amforth-6.5/msp430/words/c-fetch.asm
deleted file mode 100644
index 232603b..0000000
--- a/amforth-6.5/msp430/words/c-fetch.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C C@ c-addr -- char fetch char from memory
- CODEHEADER(XT_CFETCH,2,"c@")
- MOV.B @TOS,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/c-store.asm b/amforth-6.5/msp430/words/c-store.asm
deleted file mode 100644
index 8969947..0000000
--- a/amforth-6.5/msp430/words/c-store.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C C! char c-addr -- store char in memory
- CODEHEADER(XT_CSTORE,2,"c!")
- MOV @PSP+,W
- MOV.B W,0(TOS)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/cellplus.asm b/amforth-6.5/msp430/words/cellplus.asm
deleted file mode 100644
index c8f4066..0000000
--- a/amforth-6.5/msp430/words/cellplus.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C CELL+ a-addr1 -- a-addr2 add cell size
-; 2 + ;
- CODEHEADER(XT_CELLPLUS,5,"cell+")
- ADD #2,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/cells.asm b/amforth-6.5/msp430/words/cells.asm
deleted file mode 100644
index 46aec5a..0000000
--- a/amforth-6.5/msp430/words/cells.asm
+++ /dev/null
@@ -1,2 +0,0 @@
-;C CELLS n1 -- n2 cells->adrs units
- HEADER(XT_CELLS,5,"cells",XT_2STAR+2)
diff --git a/amforth-6.5/msp430/words/cmove-up.asm b/amforth-6.5/msp430/words/cmove-up.asm
deleted file mode 100644
index 0bbe4a3..0000000
--- a/amforth-6.5/msp430/words/cmove-up.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-;X CMOVE> c-addr1 c-addr2 u -- move from top
-; as defined in the ANSI optional String word set
- CODEHEADER(XT_CMOVEUP,6,"cmove>")
- MOV @PSP+,W ; dest adrs
- MOV @PSP+,X ; src adrs
- CMP #0,TOS
- JZ CMOVU_X
- ADD TOS,W ; start at end
- ADD TOS,X
-CMOVU_1: SUB #1,X
- SUB #1,W
- MOV.B @X,0(W) ; copy byte
- SUB #1,TOS
- JNZ CMOVU_1
-CMOVU_X: MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/cmove.asm b/amforth-6.5/msp430/words/cmove.asm
deleted file mode 100644
index a25b255..0000000
--- a/amforth-6.5/msp430/words/cmove.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-;X CMOVE c-addr1 c-addr2 u -- move from bottom
-; as defined in the ANSI optional String word set
-; On byte machines, CMOVE and CMOVE> are logical
-; factors of MOVE. They are easy to implement on
-; CPUs which have a block-move instruction.
- CODEHEADER(XT_CMOVE,5,"cmove")
- MOV @PSP+,W ; dest adrs
- MOV @PSP+,X ; src adrs
- CMP #0,TOS
- JZ CMOVE_X
-CMOVE_1: MOV.B @X+,0(W) ; copy byte
- ADD #1,W
- SUB #1,TOS
- JNZ CMOVE_1
-CMOVE_X: MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/code.asm b/amforth-6.5/msp430/words/code.asm
deleted file mode 100644
index 73fbf2b..0000000
--- a/amforth-6.5/msp430/words/code.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;U MSP430CODE <name> -- build header for assembler word
-; <builds ihere ihere 2 - i! ;
- HEADER(XT_CODE,4,"code",DOCOLON)
- DW XT_DOCREATE,XT_IHERE,XT_ICELLPLUS,XT_COMMA
- DW XT_REVEAL,XT_EXIT
diff --git a/amforth-6.5/msp430/words/colon-noname.asm b/amforth-6.5/msp430/words/colon-noname.asm
deleted file mode 100644
index 476a344..0000000
--- a/amforth-6.5/msp430/words/colon-noname.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C : -- begin a colon definition
- HEADER(XT_COLONNONAME,7,":noname",DOCOLON)
- DW XT_IHERE,XT_DUP,XT_LATEST,XT_STORE
- DW XT_COMPILE,DOCOLON
- DW XT_RBRACKET
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/comma.asm b/amforth-6.5/msp430/words/comma.asm
deleted file mode 100644
index 0f2c8d1..0000000
--- a/amforth-6.5/msp430/words/comma.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;C I, x -- append cell to Code dict
-; XT_IHERE I! 1 CELLS IALLOT ;
- ; HEADER(COMMA,2,",",DOCOLON)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB 1,","
- .align 16
-XT_COMMA: DW DOCOLON
- DW XT_IHERE,XT_STOREI,XT_TWO,XT_IALLOT,XT_EXIT
diff --git a/amforth-6.5/msp430/words/compare.asm b/amforth-6.5/msp430/words/compare.asm
deleted file mode 100644
index 75a8644..0000000
--- a/amforth-6.5/msp430/words/compare.asm
+++ /dev/null
@@ -1,18 +0,0 @@
-
-HEADER(XT_COMPARE,7,"compare",DOCOLON)
-
-; : compare ( c-addr1 len1 c-addr2 len 2 -- f )
-; f == 0 if both strings are equal
-; f <> 0 if strings differ, details are way more complex
-; rot over <> if ( -- c-addr1 c-addr2 len2)
-; \ string dont have the same length
-; drop drop drop -1 exit then
-; s= ;
-
- DW XT_ROT,XT_OVER,XT_NOTEQUAL
- DW XT_DOCONDBRANCH
- DEST(COMPARE_1)
- DW XT_DROP,XT_2DROP, XT_MINUSONE,XT_EXIT
-COMPARE_1:
- DW XT_SEQUAL
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/d-2slash.asm b/amforth-6.5/msp430/words/d-2slash.asm
deleted file mode 100644
index 06569f3..0000000
--- a/amforth-6.5/msp430/words/d-2slash.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-CODEHEADER(XT_D2SLASH,3,"d2/")
-
- RRA TOS
- RRC @PSP
- NEXT
diff --git a/amforth-6.5/msp430/words/d-2star.asm b/amforth-6.5/msp430/words/d-2star.asm
deleted file mode 100644
index f275f8c..0000000
--- a/amforth-6.5/msp430/words/d-2star.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-CODEHEADER(XT_D2STAR,3,"d2*")
-
- RLA @PSP
- RLC TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/d-minus.asm b/amforth-6.5/msp430/words/d-minus.asm
deleted file mode 100644
index a39db67..0000000
--- a/amforth-6.5/msp430/words/d-minus.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;C d+ d1/ud1 d2/ud2 -- d3/ud3 sub d1-d2
-; d1-lo d1-hi d2-lo d2-hi -- d3-lo d3 -hi
-; 4(PSP) 2(PSP) @(PSP) TOS -- NOS TOS
-
- CODEHEADER(XT_DMINUS,2,"d-")
- SUB 0(PSP),4(PSP) ; subtract contents of scratchregister X from workregister, result is in scratchregister X
- SUBC TOS,2(PSP) ; subtract content of TOS from the 3rd item, result is in 3rd item
- MOV 2(PSP),TOS ; move contoent of 3rd item to TOS
- ADD #4,PSP ; adjust parameterstackpointer, i.e. nip nip
- NEXT
diff --git a/amforth-6.5/msp430/words/d-plus.asm b/amforth-6.5/msp430/words/d-plus.asm
deleted file mode 100644
index 90e62d7..0000000
--- a/amforth-6.5/msp430/words/d-plus.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;C d+ d1/ud1 d2/ud2 -- d3/ud3 add d1+d2
-; d1-lo d1-hi d2-lo d2-hi -- d3-lo d3 -hi
-; 4(PSP) 2(PSP) @(PSP) TOS -- NOS TOS
-
- CODEHEADER(XT_DPLUS,2,"d+")
- ADD 0(PSP), 4(PSP) ; add contents of work- and scratchregister, result is in workregister
- ADDC 2(PSP),TOS ; add content of TOS to the 3rd item, result is in TOS
- ADD #4,PSP ; adjust parameterstackpointer, i.e. nip nip
- NEXT
-
diff --git a/amforth-6.5/msp430/words/dabs.asm b/amforth-6.5/msp430/words/dabs.asm
deleted file mode 100644
index 4f8259e..0000000
--- a/amforth-6.5/msp430/words/dabs.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;X DABS d1 -- +d2 absolute value dbl.prec.
-; DUP ?DNEGATE ;
- HEADER(XT_DABS,4,"dabs",DOCOLON)
- DW XT_DUP,XT_QDNEGATE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/dnegate.asm b/amforth-6.5/msp430/words/dnegate.asm
deleted file mode 100644
index 00afc1c..0000000
--- a/amforth-6.5/msp430/words/dnegate.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;X DNEGATE d1 -- d2 negate double precision
-; XT_SWAP INVERT SWAP INVERT 1 M+ ;
- HEADER(XT_DNEGATE,7,"dnegate",DOCOLON)
- DW XT_SWAP,XT_INVERT,XT_SWAP,XT_INVERT,XT_ONE,XT_MPLUS
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/do-constant.asm b/amforth-6.5/msp430/words/do-constant.asm
deleted file mode 100644
index d700349..0000000
--- a/amforth-6.5/msp430/words/do-constant.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-; DOCREATE's action is for a table in RAM.
-; DOROM is the code action for a table in ROM;
-; it returns the address of the parameter field.
-
-DOROM: ; -- a-addr ; Table in ROM: get PFA into TOS
-PFA_DOCONSTANT:
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV W,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/do-defer.asm b/amforth-6.5/msp430/words/do-defer.asm
deleted file mode 100644
index 46e3e74..0000000
--- a/amforth-6.5/msp430/words/do-defer.asm
+++ /dev/null
@@ -1,16 +0,0 @@
-; : (defer) <builds does> dup @i swap i-cell+ @i execute execute ;
-HEADER(XT_DODEFER,7,"(defer)",DOCOLON)
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_COMPILE
- .dw DODEFER
- .dw XT_EXIT
-
-DODEFER:
- .dw 04030h, dodoes ; that compiles DOES>
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/do-do.asm b/amforth-6.5/msp430/words/do-do.asm
deleted file mode 100644
index cdb0a81..0000000
--- a/amforth-6.5/msp430/words/do-do.asm
+++ /dev/null
@@ -1,25 +0,0 @@
-;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2
-;Z run-time code for DO
-; '83 and ANSI standard loops terminate when the boundary of
-; limit-1 and limit is crossed, in either direction. This can
-; be conveniently implemented by making the limit 8000h, so that
-; arithmetic overflow logic can detect crossing. I learned this
-; trick from Laxen & Perry F83.
-; fudge factor = 8000h-limit, to be added to the start value.
-; ; CODEHEADER(xdo,4,"(do)")
-; DW link
-; DB 0FFh ; not immediate
-;.set link = $
-; DB 4,"(do)"
-; .align 16
-XT_DODO:
-xdo: DW $+2
- SUB #4,RSP ; push old loop values on return stack
- MOV LIMIT,2(RSP)
- MOV INDEX,0(RSP)
- MOV #8000h,LIMIT ; compute 8000h-limit "fudge factor"
- SUB @PSP+,LIMIT
- MOV TOS,INDEX ; loop ctr = index+fudge
- ADD LIMIT,INDEX
- MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/do-does.asm b/amforth-6.5/msp430/words/do-does.asm
deleted file mode 100644
index ebf1dcf..0000000
--- a/amforth-6.5/msp430/words/do-does.asm
+++ /dev/null
@@ -1,28 +0,0 @@
-; DODOES is the code action of a DOES> clause. For ITC Forth:
-; defined word: CFA: doescode
-; PFA: parameter field
-;
-; doescode: MOV #DODOES,PC ; 16-bit direct jump, in two cells
-; high-level thread
-;
-; Note that we use JMP DODOES instead of CALL #DODOES because we can
-; efficiently obtain the thread address. DODOES is entered with W=PFA.
-; It enters the high-level thread with the address of the parameter
-; field on top of stack.
-
-dodoes: ; -- a-addr ; 3 for MOV #DODOES,PC
- SUB #2,PSP ; 1 make room on stack
- MOV TOS,0(PSP) ; 4
- MOV W,TOS ; 1 put defined word's PFA in TOS
- PUSH IP ; 3 save old IP on return stack
- MOV -2(W),IP ; 3 fetch adrs of doescode from defined word
- ADD #4,IP ; 1 skip MOV instruction to get thread adrs
- NEXT ; 4
-
-; OPTION 1 ; OPTION 2
-; MOV #DODOES,PC 3 ; CALL #DODOES 5
-; ... ; ...
-; PUSH IP 3 ; POP W 2
-; MOVE -2(W),IP 3 ; PUSH IP 3
-; ADD #4,IP 1 ; MOV W,IP 1
-
diff --git a/amforth-6.5/msp430/words/do-loop.asm b/amforth-6.5/msp430/words/do-loop.asm
deleted file mode 100644
index b1a3628..0000000
--- a/amforth-6.5/msp430/words/do-loop.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-;Z (loop) R: sys1 sys2 -- | sys1 sys2
-;Z run-time code for LOOP
-; Add 1 to the loop index. If loop terminates, clean up the
-; return stack and skip the branch. Else take the inline branch.
-; Note that LOOP terminates when index=8000h.
-; ; CODEHEADER(xloop,6,"(loop)")
-; DW link
-; DB 0FFh ; not immediate
-;.set link = $
-; DB 6,"(loop)"
-; .align 16
-XT_DOLOOP:
- DW $+2
- ADD #1,INDEX
- BIT #100h,SR ; is overflow bit set?
- JZ dobran ; no overflow = loop
- ADD #2,IP ; overflow = loop done, skip branch ofs
- MOV @RSP+,INDEX ; restore old loop values
- MOV @RSP+,LIMIT
- NEXT
diff --git a/amforth-6.5/msp430/words/do-plusloop.asm b/amforth-6.5/msp430/words/do-plusloop.asm
deleted file mode 100644
index ae41980..0000000
--- a/amforth-6.5/msp430/words/do-plusloop.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-;Z (+loop) n -- R: sys1 sys2 -- | sys1 sys2
-;Z run-time code for +LOOP
-; Add n to the loop index. If loop terminates, clean up the
-; return stack and skip the branch. Else take the inline branch.
-; ; CODEHEADER(xplusloop,7,"(+loop)")
-; DW link
-; DB 0FFh ; not immediate
-;.set link = $
-; DB 7,"(+loop)"
-; .align 16
-XT_DOPLUSLOOP:
- DW $+2
- ADD TOS,INDEX
- MOV @PSP+,TOS ; get new TOS, doesn't change flags
- BIT #100h,SR ; is overflow bit set?
- JZ dobran ; no overflow = loop
- ADD #2,IP ; overflow = loop done, skip branch ofs
- MOV @RSP+,INDEX ; restore old loop values
- MOV @RSP+,LIMIT
- NEXT
diff --git a/amforth-6.5/msp430/words/do-squote.asm b/amforth-6.5/msp430/words/do-squote.asm
deleted file mode 100644
index 3e4e210..0000000
--- a/amforth-6.5/msp430/words/do-squote.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-;Z (IS") -- c-addr u run-time code for S"
-; R> ICOUNT 2DUP + ALIGNED >R ;
-; Harvard model, for string stored in Code space
-; e.g. as used by ."
- ; HEADER(XISQUOTE,5,"(IS\")",DOCOLON)
- DW link
- DB 0FFh ; not immediate
-.set link = $
- DB 4,"(s",'"',')'
- .align 16
-XT_DOSLITERAL:
- DW DOCOLON
-
- DW XT_R_FROM,XT_ICOUNT,XT_2DUP,XT_PLUS,XT_ALIGNED,XT_TO_R
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/do-value.asm b/amforth-6.5/msp430/words/do-value.asm
deleted file mode 100644
index 4910ba5..0000000
--- a/amforth-6.5/msp430/words/do-value.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; : (value) <builds does> dup @i swap i-cell+ @i execute ;
-HEADER(XT_DOVALUE,7,"(value)",DOCOLON)
- .dw XT_DOCREATE
- .dw XT_REVEAL
- .dw XT_COMPILE
- .dw DOVALUE
- .dw XT_EXIT
-
-DOVALUE:
- .dw 04030h, dodoes ; that compiles DOES>
- .dw XT_DUP
- .dw XT_ICELLPLUS
- .dw XT_FETCHI
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/do-variable.asm b/amforth-6.5/msp430/words/do-variable.asm
deleted file mode 100644
index 2198c4b..0000000
--- a/amforth-6.5/msp430/words/do-variable.asm
+++ /dev/null
@@ -1,11 +0,0 @@
-; DOCON, code action of CONSTANT,
-; entered with W=Parameter Field Adrs
-; This is also the action of VARIABLE (Harvard model)
-; This is also the action of CREATE (Harvard model)
-docreate: ; -- a-addr ; ROMable CREATE fetches address from PFA
-DOCON: ; -- x ; CONSTANT fetches cell from PFA to TOS
-PFA_DOVARIABLE:
- SUB #2,PSP ; make room on stack
- MOV TOS,0(PSP)
- MOV @W,TOS ; fetch from parameter field to TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/does.asm b/amforth-6.5/msp430/words/does.asm
deleted file mode 100644
index 235fae7..0000000
--- a/amforth-6.5/msp430/words/does.asm
+++ /dev/null
@@ -1,20 +0,0 @@
-;C DOES> -- change action of latest def'n
-; COMPILE (DOES>)
-; dodoes ,JMP ; IMMEDIATE
-; Note that MSP430 uses a JMP, not a CALL, to DODOES.
- IMMED(XT_DOES,5,"does>",DOCOLON)
- DW XT_COMPILE,XT_DODOES
- DW XT_COMPILE,4030h ; compile a machine jump instruction
- DW XT_COMPILE,dodoes
- DW XT_EXIT
-
-; runtime part of does>
- HEADLESS(XT_DODOES,DOCOLON)
- DW XT_R_FROM
- DW XT_NEWEST
- DW XT_CELLPLUS
- DW XT_FETCH
- DW XT_FETCH
- DW XT_NFA2CFA
- DW XT_STOREI
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/dp.asm b/amforth-6.5/msp430/words/dp.asm
deleted file mode 100644
index 4f8a772..0000000
--- a/amforth-6.5/msp430/words/dp.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z dp -- a-addr holds dictionary ptr
-; 8 USER DP
- VARIABLE(XT_DP,2,"dp")
- DW CFG_DP
diff --git a/amforth-6.5/msp430/words/drop.asm b/amforth-6.5/msp430/words/drop.asm
deleted file mode 100644
index b21df02..0000000
--- a/amforth-6.5/msp430/words/drop.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C DROP x -- drop top of stack
- CODEHEADER(XT_DROP,4,"drop")
- MOV @PSP+,TOS ; 2
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/dup.asm b/amforth-6.5/msp430/words/dup.asm
deleted file mode 100644
index 4c4dbde..0000000
--- a/amforth-6.5/msp430/words/dup.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C DUP x -- x x duplicate top of stack
- CODEHEADER(XT_DUP,3,"dup")
-PUSHTOS: SUB #2,PSP ; 1 push old TOS..
- MOV TOS,0(PSP) ; 4 ..onto stack
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/end-code.asm b/amforth-6.5/msp430/words/end-code.asm
deleted file mode 100644
index e2b4580..0000000
--- a/amforth-6.5/msp430/words/end-code.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;U END-CODE -- mark end of code section
-; ;
- HEADER(XT_ENDCODE,8,"end-code",DOCOLON)
- DW XT_COMPILE,4536h,XT_COMPILE,4630h
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/environment.asm b/amforth-6.5/msp430/words/environment.asm
deleted file mode 100644
index 0fc7e9e..0000000
--- a/amforth-6.5/msp430/words/environment.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z environment -- a-addr Wordlist-ID of the environment
-; 14 USER ENVIRONMENT
- VARIABLE(XT_ENVIRONMENT,11,"environment")
- DW CFG_ENVWID
diff --git a/amforth-6.5/msp430/words/equal.asm b/amforth-6.5/msp430/words/equal.asm
deleted file mode 100644
index 169078c..0000000
--- a/amforth-6.5/msp430/words/equal.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-;C = x1 x2 -- flag test x1=x2
- CODEHEADER(XT_EQUAL,1,"=")
- MOV @PSP+,W
- SUB TOS,W ; x1-x2 in W, flags set
- JZ TOSTRUE
-TOSFALSE: MOV #0,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/execute.asm b/amforth-6.5/msp430/words/execute.asm
deleted file mode 100644
index a8139c0..0000000
--- a/amforth-6.5/msp430/words/execute.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-;C EXECUTE i*x xt -- j*x execute Forth word
-;C at 'xt'
- CODEHEADER(XT_EXECUTE,7,"execute")
- MOV TOS,W ; 1 put word address into W
- MOV @PSP+,TOS ; 2 fetch new TOS
- MOV @W+,PC ; 2 fetch code address into PC, W=PFA
-
diff --git a/amforth-6.5/msp430/words/exit.asm b/amforth-6.5/msp430/words/exit.asm
deleted file mode 100644
index 2a8185a..0000000
--- a/amforth-6.5/msp430/words/exit.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C EXIT -- exit a colon definition
- CODEHEADER(XT_EXIT,4,"exit")
- MOV @RSP+,IP ; 2 pop old IP from return stack
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/fetch.asm b/amforth-6.5/msp430/words/fetch.asm
deleted file mode 100644
index 1dbeffa..0000000
--- a/amforth-6.5/msp430/words/fetch.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C @ a-addr -- x fetch cell from memory
- CODEHEADER(XT_FETCH,1,"@")
- MOV @TOS,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/fill.asm b/amforth-6.5/msp430/words/fill.asm
deleted file mode 100644
index 66e7740..0000000
--- a/amforth-6.5/msp430/words/fill.asm
+++ /dev/null
@@ -1,12 +0,0 @@
-;C FILL c-addr u char -- fill memory with char
- CODEHEADER(XT_FILL,4,"fill")
- MOV @PSP+,X ; count
- MOV @PSP+,W ; address
- CMP #0,X
- JZ FILL_X
-FILL_1: MOV.B TOS,0(W) ; store char in memory
- ADD #1,W
- SUB #1,X
- JNZ FILL_1
-FILL_X: MOV @PSP+,TOS ; pop new TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/fm-mod.asm b/amforth-6.5/msp430/words/fm-mod.asm
deleted file mode 100644
index 4460e8d..0000000
--- a/amforth-6.5/msp430/words/fm-mod.asm
+++ /dev/null
@@ -1,12 +0,0 @@
-;C d1 n1 -- n2 n3 floored signed div'n
-; courtesy of Ed Smeda
- HEADER(FMSLASHMOD,6,"fm/mod",DOCOLON)
- DW XT_DUP,XT_TO_R,XT_2DUP,XT_XOR,XT_TO_R,XT_TO_R
- DW XT_DABS,XT_R_FETCH,XT_ABS,XT_UMSLASHMOD
- DW XT_SWAP,XT_R_FROM,XT_QNEGATE,XT_SWAP,XT_R_FROM,XT_ZEROLESS,XT_DOCONDBRANCH
- DEST(FMMOD1)
- DW XT_NEGATE,XT_OVER,XT_DOCONDBRANCH
- DEST(FMMOD2)
- DW XT_R_FETCH,XT_ROT,XT_MINUS,XT_SWAP,XT_1MINUS
-FMMOD2:
-FMMOD1: DW XT_R_FROM,XT_DROP,XT_EXIT
diff --git a/amforth-6.5/msp430/words/forth-recognizer.asm b/amforth-6.5/msp430/words/forth-recognizer.asm
deleted file mode 100644
index 95340d4..0000000
--- a/amforth-6.5/msp430/words/forth-recognizer.asm
+++ /dev/null
@@ -1,8 +0,0 @@
-;Z dp -- a-addr holds dictionary ptr
-; 8 USER DP
- HEADER(XT_FORTHRECOGNIZER,16,"forth-recognizer",DOVALUE)
-
- DW CFG_FORTHRECOGNIZER
- DW XT_RDEFERFETCH
- DW XT_RDEFERSTORE
-
diff --git a/amforth-6.5/msp430/words/forth-wordlist.asm b/amforth-6.5/msp430/words/forth-wordlist.asm
deleted file mode 100644
index 2a29512..0000000
--- a/amforth-6.5/msp430/words/forth-wordlist.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z dp -- a-addr holds dictionary ptr
-; 8 USER DP
- VARIABLE(XT_FORTHWID,14,"forth-wordlist")
- DW CFG_FORTHWID
diff --git a/amforth-6.5/msp430/words/g-mark.asm b/amforth-6.5/msp430/words/g-mark.asm
deleted file mode 100644
index 2249961..0000000
--- a/amforth-6.5/msp430/words/g-mark.asm
+++ /dev/null
@@ -1,3 +0,0 @@
- HEADLESS(XT_GMARK,DOCOLON)
- DW XT_IHERE,XT_COMPILE,-1
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/g-resolve.asm b/amforth-6.5/msp430/words/g-resolve.asm
deleted file mode 100644
index be39263..0000000
--- a/amforth-6.5/msp430/words/g-resolve.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-
-HEADLESS(XT_GRESOLVE,DOCOLON)
- DW XT_QSTACK
- DW XT_IHERE,XT_OVER,XT_MINUS,XT_SWAP,XT_STOREI
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/get-current.asm b/amforth-6.5/msp430/words/get-current.asm
deleted file mode 100644
index 08abcd0..0000000
--- a/amforth-6.5/msp430/words/get-current.asm
+++ /dev/null
@@ -1,2 +0,0 @@
- HEADER(XT_GET_CURRENT,11,"get-current",DOCOLON)
- DW XT_DOLITERAL,CFG_CURRENT,XT_FETCH,XT_EXIT
diff --git a/amforth-6.5/msp430/words/greater.asm b/amforth-6.5/msp430/words/greater.asm
deleted file mode 100644
index 30979ab..0000000
--- a/amforth-6.5/msp430/words/greater.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;C > n1 n2 -- flag test n1>n2, signed
- HEADER(XT_GREATER,1,">",DOCOLON)
- DW XT_SWAP,XT_LESS,XT_EXIT
diff --git a/amforth-6.5/msp430/words/header.asm b/amforth-6.5/msp430/words/header.asm
deleted file mode 100644
index e1b0781..0000000
--- a/amforth-6.5/msp430/words/header.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-;Z HEADER ( addr len wid -- nt ) create a Forth word header
-; Separate headers model.
- HEADER(XT_HEADER,6,"header",DOCOLON)
- DW XT_FETCH
- DW XT_COMMA ; link
- DW XT_DOLITERAL,0FFh,XT_CCOMMA ; immediate flag - see note below
- DW XT_IHERE,XT_TO_R
- DW XT_SCOMMA
- DW XT_R_FROM
- DW XT_EXIT ; MSP430: headers in I space must be aligned
-; Note for Flashable MSP430: when compiling to RAM, we need to set
-; the immediate byte to 0FFH. When compiling to Flash, the word IC!
-; will not write 0FFH to erased Flash (because the byte is already 0FFH).
-; Thus we can write this byte at a later time (with IMMEDIATE).
diff --git a/amforth-6.5/msp430/words/here.asm b/amforth-6.5/msp430/words/here.asm
deleted file mode 100644
index f86cc76..0000000
--- a/amforth-6.5/msp430/words/here.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C HERE -- addr returns dictionary ptr
-; DP @ ;
- HEADER(XT_HERE,4,"here",DOCOLON)
- DW XT_DP,XT_FETCH,XT_EXIT
diff --git a/amforth-6.5/msp430/words/hld.asm b/amforth-6.5/msp430/words/hld.asm
deleted file mode 100644
index ea6d852..0000000
--- a/amforth-6.5/msp430/words/hld.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z hp -- a-addr HOLD pointer
-; 16 USER HLD
- VARIABLE(XT_HLD,3,"hld")
- DW RAM_HLD
diff --git a/amforth-6.5/msp430/words/i-allot.asm b/amforth-6.5/msp430/words/i-allot.asm
deleted file mode 100644
index 5a74bad..0000000
--- a/amforth-6.5/msp430/words/i-allot.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C IALLOT n -- allocate n bytes in Code dict
-; IDP +! ;
- HEADER(XT_IALLOT,6,"iallot",DOCOLON)
- DW IDP,XT_PLUSSTORE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/i-cellplus.asm b/amforth-6.5/msp430/words/i-cellplus.asm
deleted file mode 100644
index 6c472f9..0000000
--- a/amforth-6.5/msp430/words/i-cellplus.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-
-HEADER(XT_ICELLPLUS,7,"i-cell+",DOCOLON)
- .DW XT_CELLPLUS
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/i-fetch.asm b/amforth-6.5/msp430/words/i-fetch.asm
deleted file mode 100644
index bd0004e..0000000
--- a/amforth-6.5/msp430/words/i-fetch.asm
+++ /dev/null
@@ -1,2 +0,0 @@
-;Z I@ a-addr -- x fetch cell from Instruction memory
- HEADER(XT_FETCHI,2,"@i",XT_FETCH+2)
diff --git a/amforth-6.5/msp430/words/i-here.asm b/amforth-6.5/msp430/words/i-here.asm
deleted file mode 100644
index 7bcac83..0000000
--- a/amforth-6.5/msp430/words/i-here.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C XT_IHERE -- addr returns Code dictionary ptr
-; IDP @ ;
- HEADER(XT_IHERE,5,"ihere",DOCOLON)
- DW IDP,XT_FETCH,XT_EXIT
diff --git a/amforth-6.5/msp430/words/i.asm b/amforth-6.5/msp430/words/i.asm
deleted file mode 100644
index bd6b4eb..0000000
--- a/amforth-6.5/msp430/words/i.asm
+++ /dev/null
@@ -1,8 +0,0 @@
-;C I -- n R: sys1 sys2 -- sys1 sys2
-;C get the innermost loop index
- CODEHEADER(XT_I,1,"i")
- SUB #2,PSP ; make room in TOS
- MOV TOS,0(PSP)
- MOV INDEX,TOS ; index = loopctr - fudge
- SUB LIMIT,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/ic-fetch.asm b/amforth-6.5/msp430/words/ic-fetch.asm
deleted file mode 100644
index c026c0e..0000000
--- a/amforth-6.5/msp430/words/ic-fetch.asm
+++ /dev/null
@@ -1,2 +0,0 @@
-;Z IC@ a-addr -- x fetch char from Instruction memory
- HEADER(XT_CFETCHI,3,"c@i",XT_CFETCH+2)
diff --git a/amforth-6.5/msp430/words/icount.asm b/amforth-6.5/msp430/words/icount.asm
deleted file mode 100644
index d2a8ae2..0000000
--- a/amforth-6.5/msp430/words/icount.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;C COUNT c-addr1 -- c-addr2 u counted->adr/len
- HEADER(XT_ICOUNT,6,"icount",DOCOLON)
- DW XT_DUP,XT_1PLUS,XT_SWAP,XT_CFETCH,XT_EXIT
diff --git a/amforth-6.5/msp430/words/idp.asm b/amforth-6.5/msp430/words/idp.asm
deleted file mode 100644
index f64c348..0000000
--- a/amforth-6.5/msp430/words/idp.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z IDP -- a-addr ROM dictionary pointer
-; 20 USER IDP
- VARIABLE(IDP,3,"idp")
- DW CFG_IDP
diff --git a/amforth-6.5/msp430/words/immediate-q.asm b/amforth-6.5/msp430/words/immediate-q.asm
deleted file mode 100644
index 2660efe..0000000
--- a/amforth-6.5/msp430/words/immediate-q.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( f -- +/-1 )
-; System
-; return +1 if immediate, -1 otherwise, flag from name>flags
- HEADLESS(XT_IMMEDIATEQ,DOCOLON)
- .dw XT_ONE
- .dw XT_AND
- .dw XT_ZEROEQUAL
- .dw XT_DOCONDBRANCH
- DEST(IMMEDIATEQ1)
- .dw XT_ONE
- .dw XT_EXIT
-IMMEDIATEQ1:
- ; not immediate
- .dw XT_TRUE
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/immediate.asm b/amforth-6.5/msp430/words/immediate.asm
deleted file mode 100644
index 9be4150..0000000
--- a/amforth-6.5/msp430/words/immediate.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C IMMEDIATE -- make last def'n immediate
- HEADER(IMMEDIATE,9,"immediate",DOCOLON)
- DW XT_DOLITERAL,0FEh,XT_GET_CURRENT,XT_FETCH,XT_1MINUS,XT_CSTOREI
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/infodp.asm b/amforth-6.5/msp430/words/infodp.asm
deleted file mode 100644
index 6f9faaf..0000000
--- a/amforth-6.5/msp430/words/infodp.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z dp -- a-addr holds dictionary ptr
-; 8 USER DP
- VARIABLE(XT_INFODP,6,"infodp")
- DW CFG_INFODP
diff --git a/amforth-6.5/msp430/words/int-fetch.asm b/amforth-6.5/msp430/words/int-fetch.asm
deleted file mode 100644
index 793cf25..0000000
--- a/amforth-6.5/msp430/words/int-fetch.asm
+++ /dev/null
@@ -1,4 +0,0 @@
- CODEHEADER(XT_INT_FETCH,4,"int@")
- ADD TOS,TOS
- MOV CFG_ISRVECS(TOS),TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/int-off.asm b/amforth-6.5/msp430/words/int-off.asm
deleted file mode 100644
index 71f1d25..0000000
--- a/amforth-6.5/msp430/words/int-off.asm
+++ /dev/null
@@ -1,3 +0,0 @@
- CODEHEADER(XT_INT_OFF,4,"-int")
- DINT
- NEXT
diff --git a/amforth-6.5/msp430/words/int-on.asm b/amforth-6.5/msp430/words/int-on.asm
deleted file mode 100644
index 64b303c..0000000
--- a/amforth-6.5/msp430/words/int-on.asm
+++ /dev/null
@@ -1,3 +0,0 @@
- CODEHEADER(XT_INT_ON,4,"+int")
- EINT
- NEXT
diff --git a/amforth-6.5/msp430/words/int-store.asm b/amforth-6.5/msp430/words/int-store.asm
deleted file mode 100644
index cdb9896..0000000
--- a/amforth-6.5/msp430/words/int-store.asm
+++ /dev/null
@@ -1,5 +0,0 @@
- CODEHEADER(XT_INT_STORE,4,"int!")
- ADD TOS,TOS
- MOV @PSP+,CFG_ISRVECS(TOS)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/int-trap.asm b/amforth-6.5/msp430/words/int-trap.asm
deleted file mode 100644
index 13a2f6d..0000000
--- a/amforth-6.5/msp430/words/int-trap.asm
+++ /dev/null
@@ -1,4 +0,0 @@
- CODEHEADER(XT_TRAP,8,"int-trap")
- MOV TOS,ISR
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/invert.asm b/amforth-6.5/msp430/words/invert.asm
deleted file mode 100644
index 7108b3c..0000000
--- a/amforth-6.5/msp430/words/invert.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C INVERT x1 -- x2 bitwise inversion
- CODEHEADER(XT_INVERT,6,"invert")
- XOR #-1,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/isr-exec.asm b/amforth-6.5/msp430/words/isr-exec.asm
deleted file mode 100644
index de67130..0000000
--- a/amforth-6.5/msp430/words/isr-exec.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-; ( n -- )
-; Interrupt
-; executes an interrupt service routine
- HEADLESS(XT_ISREXEC,DOCOLON)
- .dw XT_INT_FETCH
- .dw XT_EXECUTE
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/itype.asm b/amforth-6.5/msp430/words/itype.asm
deleted file mode 100644
index 68a032e..0000000
--- a/amforth-6.5/msp430/words/itype.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;Z ITYPE c-addr +n -- type line to term'l
-; ?DUP IF from Code space
-; OVER + XT_SWAP DO I IC@ EMIT LOOP
-; ELSE DROP THEN ;
- HEADER(XT_ITYPE,5,"itype",DOCOLON)
- DW XT_TYPE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/j.asm b/amforth-6.5/msp430/words/j.asm
deleted file mode 100644
index 74e9d58..0000000
--- a/amforth-6.5/msp430/words/j.asm
+++ /dev/null
@@ -1,9 +0,0 @@
-
-;C J -- n R: 4*sys -- 4*sys
-;C get the second loop index
- CODEHEADER(XT_J,1,"j")
- SUB #2,PSP ; make room in TOS
- MOV TOS,0(PSP)
- MOV @RSP,TOS ; index = loopctr - fudge
- SUB 2(RSP),TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/l-0.asm b/amforth-6.5/msp430/words/l-0.asm
deleted file mode 100644
index a35ef18..0000000
--- a/amforth-6.5/msp430/words/l-0.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;Z l0 -- a-addr bottom of Leave stack
- VARIABLE(XT_LP0,3,"lp0")
- DW LSTACK
diff --git a/amforth-6.5/msp430/words/l-mark.asm b/amforth-6.5/msp430/words/l-mark.asm
deleted file mode 100644
index af253cd..0000000
--- a/amforth-6.5/msp430/words/l-mark.asm
+++ /dev/null
@@ -1,2 +0,0 @@
- HEADLESS(XT_LMARK,DOCOLON)
- DW XT_IHERE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/l-resolve.asm b/amforth-6.5/msp430/words/l-resolve.asm
deleted file mode 100644
index ec912cd..0000000
--- a/amforth-6.5/msp430/words/l-resolve.asm
+++ /dev/null
@@ -1,4 +0,0 @@
- HEADLESS(XT_LRESOLVE,DOCOLON)
- DW XT_QSTACK
- DW XT_IHERE,XT_MINUS,XT_COMMA
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/latest.asm b/amforth-6.5/msp430/words/latest.asm
deleted file mode 100644
index 029b9fc..0000000
--- a/amforth-6.5/msp430/words/latest.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;Z NEWEST -- a-addr temporary CURRENT storage
-VARIABLE(XT_LATEST,6,"latest")
- DW RAM_LATEST
diff --git a/amforth-6.5/msp430/words/less.asm b/amforth-6.5/msp430/words/less.asm
deleted file mode 100644
index 57b8705..0000000
--- a/amforth-6.5/msp430/words/less.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-;C < n1 n2 -- flag test n1<n2, signed
- CODEHEADER(XT_LESS,1,"<")
- MOV @PSP+,W
- SUB TOS,W ; x1-x2 in W, flags set
- JGE TOSFALSE
-TOSTRUE: MOV #-1,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/lit.asm b/amforth-6.5/msp430/words/lit.asm
deleted file mode 100644
index a186a4f..0000000
--- a/amforth-6.5/msp430/words/lit.asm
+++ /dev/null
@@ -1,8 +0,0 @@
-;Z lit -- x fetch inline literal to stack
-; This is the primtive compiled by LITERAL.
- HEADLESS(XT_DOLITERAL,PFA_DOLITERAL)
-PFA_DOLITERAL:
- SUB #2,PSP ; 1 push old TOS..
- MOV TOS,0(PSP) ; 4 ..onto stack
- MOV @IP+,TOS ; 2 fetch new TOS value
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/lp.asm b/amforth-6.5/msp430/words/lp.asm
deleted file mode 100644
index d59dc88..0000000
--- a/amforth-6.5/msp430/words/lp.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z lp -- a-addr LEAVE-stack pointer
-; 18 USER LP
- VARIABLE(XT_LP,2,"lp")
- DW RAM_LP
diff --git a/amforth-6.5/msp430/words/lshift.asm b/amforth-6.5/msp430/words/lshift.asm
deleted file mode 100644
index 810d680..0000000
--- a/amforth-6.5/msp430/words/lshift.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;C LSHIFT x1 u -- x2 logical L shift u places
- CODEHEADER(LSHIFT,6,"lshift")
- MOV @PSP+,W
- AND #1Fh,TOS ; no need to shift more than 16
- JZ LSH_X
-LSH_1: ADD W,W
- SUB #1,TOS
- JNZ LSH_1
-LSH_X: MOV W,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/m-plus.asm b/amforth-6.5/msp430/words/m-plus.asm
deleted file mode 100644
index 633e2f8..0000000
--- a/amforth-6.5/msp430/words/m-plus.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;X M+ d n -- d add single to double
- CODEHEADER(XT_MPLUS,2,"m+")
- ADD TOS,2(PSP)
- ADDC #0,0(PSP)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/m-star.asm b/amforth-6.5/msp430/words/m-star.asm
deleted file mode 100644
index f1e2b44..0000000
--- a/amforth-6.5/msp430/words/m-star.asm
+++ /dev/null
@@ -1,8 +0,0 @@
-;C M* n1 n2 -- d signed 16*16->32 multiply
-; 2DUP XOR >R carries sign of the result
-; XT_SWAP ABS SWAP ABS UM*
-; R> ?DNEGATE ;
- HEADER(XT_MSTAR,2,"m*",DOCOLON)
- DW XT_2DUP,XT_XOR,XT_TO_R
- DW XT_SWAP,XT_ABS,XT_SWAP,XT_ABS,XT_UMSTAR
- DW XT_R_FROM,XT_QDNEGATE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/mcu-sr-fetch.asm b/amforth-6.5/msp430/words/mcu-sr-fetch.asm
deleted file mode 100644
index 98ab000..0000000
--- a/amforth-6.5/msp430/words/mcu-sr-fetch.asm
+++ /dev/null
@@ -1,5 +0,0 @@
- CODEHEADER(XT_MCU_SR_FETCH,3,"sr@")
- sub #2, PSP
- mov TOS, 0(PSP)
- mov r2, TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/minus.asm b/amforth-6.5/msp430/words/minus.asm
deleted file mode 100644
index cd49f24..0000000
--- a/amforth-6.5/msp430/words/minus.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C - n1/u1 n2/u2 -- n3/u3 subtract n1-n2
- CODEHEADER(XT_MINUS,1,"-")
- MOV @PSP+,W
- SUB TOS,W
- MOV W,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/n_r_from.asm b/amforth-6.5/msp430/words/n_r_from.asm
deleted file mode 100644
index 5ac6ab1..0000000
--- a/amforth-6.5/msp430/words/n_r_from.asm
+++ /dev/null
@@ -1,17 +0,0 @@
-; ( -- x-n .. x-1 n ) (R: x-n .. x-1 n -- )
-; Stack
-; move n items from return stack to data stack
- CODEHEADER(XT_N_R_FROM,3,"nr>")
-
- SUB #2,PSP ; 2
- MOV TOS,0(PSP) ; 4
- MOV @RSP+,X
- MOV X, Y
-PFA_N_R_FROM1:
- MOV @RSP+,TOS
- SUB #2,PSP ; 2
- MOV TOS,0(PSP) ; 4
- SUB #1, X
- jnz PFA_N_R_FROM1
- MOV Y, TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/n_to_r.asm b/amforth-6.5/msp430/words/n_to_r.asm
deleted file mode 100644
index 91807e5..0000000
--- a/amforth-6.5/msp430/words/n_to_r.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ( x-n .. x-1 n -- ) (R: -- x-n .. x-1 n)
-; Stack
-; move n items from data stack to return stack
- CODEHEADER(XT_N_TO_R,3,"n>r")
-
- MOV TOS, X ; save count cell twice
- MOV TOS, Y
-PFA_N_TO_R1:
- MOV @PSP+,TOS
- PUSH TOS
- SUB #1, X
- JNZ PFA_N_TO_R1
- PUSH Y ; old TOS (count)
- MOV @PSP+,TOS ; get new TOS
- NEXT \ No newline at end of file
diff --git a/amforth-6.5/msp430/words/name2flags.asm b/amforth-6.5/msp430/words/name2flags.asm
deleted file mode 100644
index 9af91be..0000000
--- a/amforth-6.5/msp430/words/name2flags.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;Z nfa -- f fetch flag information
- HEADER(XT_NAME2FLAGS,10,"name>flags",DOCOLON)
- DW XT_1MINUS,XT_CFETCHI,XT_EXIT
diff --git a/amforth-6.5/msp430/words/negate.asm b/amforth-6.5/msp430/words/negate.asm
deleted file mode 100644
index 6c2527e..0000000
--- a/amforth-6.5/msp430/words/negate.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C NEGATE x1 -- x2 two's complement
- CODEHEADER(XT_NEGATE,6,"negate")
- XOR #-1,TOS
- ADD #1,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/newest.asm b/amforth-6.5/msp430/words/newest.asm
deleted file mode 100644
index bc6a956..0000000
--- a/amforth-6.5/msp430/words/newest.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;Z NEWEST -- a-addr temporary CURRENT storage
-VARIABLE(XT_NEWEST,6,"newest")
- DW RAM_NEWEST
diff --git a/amforth-6.5/msp430/words/nfa-to-cfa.asm b/amforth-6.5/msp430/words/nfa-to-cfa.asm
deleted file mode 100644
index 160e22f..0000000
--- a/amforth-6.5/msp430/words/nfa-to-cfa.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;Z NFA>CFA nfa -- cfa name adr -> code field
-; HCOUNT 7F AND + ALIGNED ; mask off 'smudge' bit
- HEADER(XT_NFA2CFA,7,"nfa>cfa",DOCOLON)
- DW XT_ICOUNT
- DW XT_DOLITERAL,07Fh,XT_AND,XT_PLUS,XT_ALIGNED,XT_EXIT
diff --git a/amforth-6.5/msp430/words/nfa-to-lfa.asm b/amforth-6.5/msp430/words/nfa-to-lfa.asm
deleted file mode 100644
index 43c0898..0000000
--- a/amforth-6.5/msp430/words/nfa-to-lfa.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;Z NFA>LFA nfa -- lfa name adr -> link field
-; 3 - ;
- HEADER(XT_NFA2LFA,7,"nfa>lfa",DOCOLON)
- DW XT_DOLITERAL,3,XT_MINUS,XT_EXIT
diff --git a/amforth-6.5/msp430/words/nip.asm b/amforth-6.5/msp430/words/nip.asm
deleted file mode 100644
index b9f5299..0000000
--- a/amforth-6.5/msp430/words/nip.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;X NIP x1 x2 -- x2 per stack diagram
- CODEHEADER(XT_NIP,3,"nip")
- ADD #2,PSP ; 1
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/or.asm b/amforth-6.5/msp430/words/or.asm
deleted file mode 100644
index 8bb4cc7..0000000
--- a/amforth-6.5/msp430/words/or.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C OR x1 x2 -- x3 logical OR
- CODEHEADER(XT_OR,2,"or")
- BIS @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/over.asm b/amforth-6.5/msp430/words/over.asm
deleted file mode 100644
index 11b1770..0000000
--- a/amforth-6.5/msp430/words/over.asm
+++ /dev/null
@@ -1,8 +0,0 @@
-;C OVER x1 x2 -- x1 x2 x1 per stack diagram
- CODEHEADER(XT_OVER,4,"over")
- MOV @PSP,W ; 2
- SUB #2,PSP ; 2
- MOV TOS,0(PSP) ; 4
- MOV W,TOS ; 1
- NEXT ; 4
-
diff --git a/amforth-6.5/msp430/words/pause.asm b/amforth-6.5/msp430/words/pause.asm
deleted file mode 100644
index 89362d0..0000000
--- a/amforth-6.5/msp430/words/pause.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-; ( -- )
-; Multitasking
-; Fetch pause vector and execute it. may make a context/task switch
-DEFER(XT_PAUSE,5,"pause")
- .dw RAM_PAUSE
- .dw XT_RDEFERFETCH
- .dw XT_RDEFERSTORE
diff --git a/amforth-6.5/msp430/words/plus-store.asm b/amforth-6.5/msp430/words/plus-store.asm
deleted file mode 100644
index 970057d..0000000
--- a/amforth-6.5/msp430/words/plus-store.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C +! n/u a-addr -- add cell to memory
- CODEHEADER(XT_PLUSSTORE,2,"+!")
- ADD @PSP+,0(TOS)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/plus.asm b/amforth-6.5/msp430/words/plus.asm
deleted file mode 100644
index cb57910..0000000
--- a/amforth-6.5/msp430/words/plus.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C + n1/u1 n2/u2 -- n3/u3 add n1+n2
- CODEHEADER(XT_PLUS,1,"+")
- ADD @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/q-branch.asm b/amforth-6.5/msp430/words/q-branch.asm
deleted file mode 100644
index 5ec1563..0000000
--- a/amforth-6.5/msp430/words/q-branch.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-;Z ?branch x -- branch if TOS zero
- CODEHEADER(XT_DOCONDBRANCH,7,"?branch")
- ADD #0,TOS ; 1 test TOS value
- MOV @PSP+,TOS ; 2 pop new TOS value (doesn't change flags)
- JZ dobran ; 2 if TOS was zero, take the branch
- ADD #2,IP ; 1 else skip the branch destination
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/qdup.asm b/amforth-6.5/msp430/words/qdup.asm
deleted file mode 100644
index 2bb9eb0..0000000
--- a/amforth-6.5/msp430/words/qdup.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C ?DUP x -- 0 | x x DUP if nonzero
- CODEHEADER(XT_QDUP,4,"?dup")
- CMP #0,TOS ; 1 test for TOS nonzero
- JNZ PUSHTOS ; 2
-NODUP: NEXT ; 4
diff --git a/amforth-6.5/msp430/words/r-0.asm b/amforth-6.5/msp430/words/r-0.asm
deleted file mode 100644
index c3599ac..0000000
--- a/amforth-6.5/msp430/words/r-0.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;Z r0 -- a-addr end of return stack
- VARIABLE(XT_RP0,3,"rp0")
- DW RSTACK
diff --git a/amforth-6.5/msp430/words/r-fetch.asm b/amforth-6.5/msp430/words/r-fetch.asm
deleted file mode 100644
index 25de529..0000000
--- a/amforth-6.5/msp430/words/r-fetch.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C R@ -- x R: x -- x fetch from rtn stk
- CODEHEADER(XT_R_FETCH,2,"r@")
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV @RSP,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/r-from.asm b/amforth-6.5/msp430/words/r-from.asm
deleted file mode 100644
index b43ce9a..0000000
--- a/amforth-6.5/msp430/words/r-from.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C R> -- x R: x -- pop from return stack
- CODEHEADER(XT_R_FROM,2,"r>")
- SUB #2,PSP ; 2
- MOV TOS,0(PSP) ; 4
- MOV @RSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/reg-a.asm b/amforth-6.5/msp430/words/reg-a.asm
deleted file mode 100644
index 89d3b8b..0000000
--- a/amforth-6.5/msp430/words/reg-a.asm
+++ /dev/null
@@ -1,95 +0,0 @@
-; ( -- n2 )
-; Extended VM
-; Read memory pointed to by register A (Extended VM)
-CODEHEADER(XT_AFETCH,2,"a@")
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV @REG_A,TOS
- NEXT
-
-; ( n1 -- n2 )
-; Extended VM
-; Read memory pointed to by register A plus offset (Extended VM)
-CODEHEADER(XT_NAFETCH,3,"na@")
- ADD REG_A,TOS
- MOV @TOS,TOS
- NEXT
-
-; ( -- n )
-; Extended VM
-; Read memory pointed to by register A, increment A by 1 cell (Extended VM)
-CODEHEADER(XT_AFETCHPLUS,3,"a@+")
- SUB #2,PSP
- MOV TOS,0(PSP)
- ADD REG_A,TOS
- MOV @TOS,TOS
- ADD #2,REG_A
- NEXT
-
-; ( -- n )
-; Extended VM
-; Read memory pointed to by register A, decrement A by 1 cell (Extended VM)
-CODEHEADER(XT_AFETCHMINUS,3,"a@-")
- SUB #2,PSP
- MOV TOS,0(PSP)
- ADD REG_A,TOS
- MOV @TOS,TOS
- SUB #2,REG_A
- NEXT
-
-; ( n -- )
-; Extended VM
-; Write memory pointed to by register A (Extended VM)
-CODEHEADER(XT_ASTORE,2,"a!")
- MOV TOS,@REG_A
- MOV @PSP+,TOS
- NEXT
-
-; ( n offs -- )
-; Extended VM
-; Write memory pointed to by register A plus offset (Extended VM)
-CODEHEADER(XT_NASTORE,3,"na!")
- ADD REG_A, TOS
- MOV @PSP+,X
- MOV X,@TOS
- MOV @PSP+,TOS
- NEXT
-
-; ( -- n2 )
-; Extended VM
-; Write memory pointed to by register A, increment A by 1 cell (Extended VM)
-CODEHEADER(XT_ASTOREPLUS,3,"a!+")
- MOV TOS,@REG_A
- MOV @PSP+,TOS
- ADD #2,REG_A
- NEXT
-
-; ( -- n2 )
-; Extended VM
-; Write memory pointed to by register A, decrement A by 1 cell (Extended VM)
-CODEHEADER(XT_ASTOREMINUS,3,"a!-")
- MOV TOS,@REG_A
- MOV @PSP+,TOS
- SUB #2,REG_A
- NEXT
-
-; ( n -- )
-; Extended VM
-; Write to A register (Extended VM)
-CODEHEADER(XT_TO_A,2,">a")
- MOV TOS,REG_A
- MOV @PSP+,TOS
- NEXT
-
-; ( n1 -- n2 )
-; Extended VM
-; read the A register (Extended VM)
-CODEHEADER(XT_A_FROM,2,"a>")
- SUB #2,PSP
- MOV REG_A,TOS
- NEXT
-
-; for more information read
-; http://www.complang.tuwien.ac.at/anton/euroforth/ef08/papers/pelc.pdf
-; adapted index based access from X/Y registers
-; note: offset is byte address, not cell!
diff --git a/amforth-6.5/msp430/words/restore.asm b/amforth-6.5/msp430/words/restore.asm
deleted file mode 100644
index ba3534b..0000000
--- a/amforth-6.5/msp430/words/restore.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-; RESTORE copies the first 128 bytes of Info Flash to
-; the User Area and subsequent RAM.
- HEADER(RESTORE,7,"RESTORE",DOCOLON)
- DW XT_DOLITERAL,FLASHINFOAREA
- DW XT_DOLITERAL,RAMINFOAREA
- DW XT_DOLITERAL,INFO_SIZE
- DW XT_ITOD,XT_EXIT
diff --git a/amforth-6.5/msp430/words/rot.asm b/amforth-6.5/msp430/words/rot.asm
deleted file mode 100644
index fe5914b..0000000
--- a/amforth-6.5/msp430/words/rot.asm
+++ /dev/null
@@ -1,7 +0,0 @@
-;C ROT x1 x2 x3 -- x2 x3 x1 per stack diagram
- CODEHEADER(XT_ROT,3,"rot")
- MOV @PSP,W ; 2 fetch x2
- MOV TOS,0(PSP) ; 4 store x3
- MOV 2(PSP),TOS ; 3 fetch x1
- MOV W,2(PSP) ; 4 store x2
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/rp-fetch.asm b/amforth-6.5/msp430/words/rp-fetch.asm
deleted file mode 100644
index 74d723d..0000000
--- a/amforth-6.5/msp430/words/rp-fetch.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;Z RP@ -- a-addr get return stack pointer
- CODEHEADER(XT_RP_FETCH,3,"rp@")
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV RSP,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/rp-store.asm b/amforth-6.5/msp430/words/rp-store.asm
deleted file mode 100644
index 80fa742..0000000
--- a/amforth-6.5/msp430/words/rp-store.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;Z RP! a-addr -- set return stack pointer
- CODEHEADER(XT_RP_STORE,3,"rp!")
- MOV TOS,RSP
- MOV @PSP+,TOS ; 2
- NEXT
diff --git a/amforth-6.5/msp430/words/rshift.asm b/amforth-6.5/msp430/words/rshift.asm
deleted file mode 100644
index d0201ed..0000000
--- a/amforth-6.5/msp430/words/rshift.asm
+++ /dev/null
@@ -1,11 +0,0 @@
-;C RSHIFT x1 u -- x2 logical R shift u places
- CODEHEADER(RSHIFT,6,"rshift")
- MOV @PSP+,W
- AND #1Fh,TOS ; no need to shift more than 16
- JZ RSH_X
-RSH_1: CLRC
- RRC W
- SUB #1,TOS
- JNZ RSH_1
-RSH_X: MOV W,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/s-0.asm b/amforth-6.5/msp430/words/s-0.asm
deleted file mode 100644
index 4e0e63d..0000000
--- a/amforth-6.5/msp430/words/s-0.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;Z s0 -- a-addr end of parameter stack
- VARIABLE(XT_SP0,3,"sp0")
- DW PSTACK
diff --git a/amforth-6.5/msp430/words/s-equal.asm b/amforth-6.5/msp430/words/s-equal.asm
deleted file mode 100644
index 28e6758..0000000
--- a/amforth-6.5/msp430/words/s-equal.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-;Z S= c-addr1 c-addr2 u -- n string compare
-;Z n<0: s1<s2, n=0: s1=s2, n>0: s1>s2
- CODEHEADER(XT_SEQUAL,2,"s=")
- MOV @PSP+,W ; adrs2
- MOV @PSP+,X ; adrs1
- CMP #0,TOS
- JZ SEQU_X
-SEQU_1: CMP.B @W+,0(X) ; compare char1-char2
- JNZ SMISMATCH
- ADD #1,X
- SUB #1,TOS
- JNZ SEQU_1
- ; no mismatch found, strings are equal, TOS=0
- JMP SEQU_X
- ; mismatch found, CY clear if borrow set (s1<s2)
-SMISMATCH: SUBC TOS,TOS ; TOS=-1 if borrow was set
- ADD TOS,TOS ; TOS=-2 or 0
- ADD #1,TOS ; TOS=-1 or +1
-SEQU_X: NEXT ; return result in TOS
diff --git a/amforth-6.5/msp430/words/scomma.asm b/amforth-6.5/msp430/words/scomma.asm
deleted file mode 100644
index 92614e2..0000000
--- a/amforth-6.5/msp430/words/scomma.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-; compiles a string to the dictionary. Does not add a runtime action.
- DW link
- DB 0FEh ; immediate
-.set link = $
- DB 2,"s",','
- .align 16
-XT_SCOMMA:
- DW DOCOLON
- DW XT_DUP,XT_TO_R,XT_CCOMMA,XT_IHERE,XT_R_FETCH,XT_DTOI
- DW XT_R_FROM,XT_IALLOT,XT_ALIGN,XT_EXIT
diff --git a/amforth-6.5/msp430/words/set-current.asm b/amforth-6.5/msp430/words/set-current.asm
deleted file mode 100644
index c76e3e8..0000000
--- a/amforth-6.5/msp430/words/set-current.asm
+++ /dev/null
@@ -1,2 +0,0 @@
- HEADER(XT_SET_CURRENT,11,"set-current",DOCOLON)
- DW XT_DOLITERAL,CFG_CURRENT,XT_STORE,XT_EXIT
diff --git a/amforth-6.5/msp430/words/slash-mod.asm b/amforth-6.5/msp430/words/slash-mod.asm
deleted file mode 100644
index ba5d98c..0000000
--- a/amforth-6.5/msp430/words/slash-mod.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C /MOD n1 n2 -- n3 n4 signed divide/rem'dr
-; >R S>D R> FM/MOD ;
- HEADER(XT_SLASHMOD,4,"/mod",DOCOLON)
- DW XT_TO_R,XT_S2D,XT_R_FROM,FMSLASHMOD,XT_EXIT
diff --git a/amforth-6.5/msp430/words/sm-rem.asm b/amforth-6.5/msp430/words/sm-rem.asm
deleted file mode 100644
index 5415080..0000000
--- a/amforth-6.5/msp430/words/sm-rem.asm
+++ /dev/null
@@ -1,12 +0,0 @@
-;C SM/REM d1 n1 -- n2 n3 symmetric signed div
-; 2DUP XOR >R sign of quotient
-; OVER >R sign of remainder
-; ABS >R DABS R> UM/MOD
-; XT_SWAP R> ?NEGATE
-; XT_SWAP R> ?NEGATE ;
-; Ref. dpANS-6 section 3.2.2.1.
- HEADER(SMSLASHREM,6,"sm/rem",DOCOLON)
- DW XT_2DUP,XT_XOR,XT_TO_R,XT_OVER,XT_TO_R
- DW XT_ABS,XT_TO_R,XT_DABS,XT_R_FROM,XT_UMSLASHMOD
- DW XT_SWAP,XT_R_FROM,XT_QNEGATE,XT_SWAP,XT_R_FROM,XT_QNEGATE
- DW XT_EXIT
diff --git a/amforth-6.5/msp430/words/sp-fetch.asm b/amforth-6.5/msp430/words/sp-fetch.asm
deleted file mode 100644
index fbf573a..0000000
--- a/amforth-6.5/msp430/words/sp-fetch.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;Z SP@ -- a-addr get data stack pointer
- CODEHEADER(XT_SP_FETCH,3,"sp@")
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV PSP,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/sp-store.asm b/amforth-6.5/msp430/words/sp-store.asm
deleted file mode 100644
index 5514744..0000000
--- a/amforth-6.5/msp430/words/sp-store.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;Z SP! a-addr -- set data stack pointer
- CODEHEADER(XT_SP_STORE,3,"sp!")
- MOV TOS,PSP
- MOV @PSP+,TOS ; 2
- NEXT
diff --git a/amforth-6.5/msp430/words/state.asm b/amforth-6.5/msp430/words/state.asm
deleted file mode 100644
index 4527f29..0000000
--- a/amforth-6.5/msp430/words/state.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-;C STATE -- a-addr holds compiler state
-; 6 USER STATE
- VARIABLE(XT_STATE,5,"state")
- DW RAM_STATE
diff --git a/amforth-6.5/msp430/words/store.asm b/amforth-6.5/msp430/words/store.asm
deleted file mode 100644
index a45fdcc..0000000
--- a/amforth-6.5/msp430/words/store.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C ! x a-addr -- store cell in memory
- CODEHEADER(XT_STORE,1,"!")
- MOV @PSP+,0(TOS)
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/swap.asm b/amforth-6.5/msp430/words/swap.asm
deleted file mode 100644
index 7950f18..0000000
--- a/amforth-6.5/msp430/words/swap.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C XT_SWAP x1 x2 -- x2 x1 swap top two items
- CODEHEADER(XT_SWAP,4,"swap")
- MOV @PSP,W ; 2
- MOV TOS,0(PSP) ; 4
- MOV W,TOS ; 1
- NEXT ; 4
diff --git a/amforth-6.5/msp430/words/to-body.asm b/amforth-6.5/msp430/words/to-body.asm
deleted file mode 100644
index b5be7a3..0000000
--- a/amforth-6.5/msp430/words/to-body.asm
+++ /dev/null
@@ -1,3 +0,0 @@
-;C >BODY xt -- a-addr adrs of CREATE data
-; 2+ ; 8086 (3 byte CALL)
- HEADER(XT_TO_BODY,5,">body",XT_CELLPLUS+2)
diff --git a/amforth-6.5/msp430/words/to-r.asm b/amforth-6.5/msp430/words/to-r.asm
deleted file mode 100644
index d4d57b8..0000000
--- a/amforth-6.5/msp430/words/to-r.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C >R x -- R: -- x push to return stack
- CODEHEADER(XT_TO_R,2,">r")
- PUSH TOS
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/turnkey.asm b/amforth-6.5/msp430/words/turnkey.asm
deleted file mode 100644
index 58445cf..0000000
--- a/amforth-6.5/msp430/words/turnkey.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-
-DEFER(XT_TURNKEY,7,"turnkey")
- .dw CFG_TURNKEY
- .dw XT_RDEFERFETCH
- .dw XT_RDEFERSTORE
diff --git a/amforth-6.5/msp430/words/u-less.asm b/amforth-6.5/msp430/words/u-less.asm
deleted file mode 100644
index 2e7b5af..0000000
--- a/amforth-6.5/msp430/words/u-less.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C U< u1 u2 -- flag test u1<u2, unsigned
- CODEHEADER(XT_ULESS,2,"u<")
- MOV @PSP+,W
- SUB TOS,W ; u1-u2 in W, cy clear if borrow
- JNC TOSTRUE
- JMP TOSFALSE
diff --git a/amforth-6.5/msp430/words/uinit.asm b/amforth-6.5/msp430/words/uinit.asm
deleted file mode 100644
index eb4c058..0000000
--- a/amforth-6.5/msp430/words/uinit.asm
+++ /dev/null
@@ -1,39 +0,0 @@
-;Z uinit -- addr initial values for user area
-; MSP430: we also use this to initialize the RAM interrupt
-; vectors, which immediately follow the user area.
-; Per init430f1611.s43, allocate 16 cells for user
-; variables, followed by 30 cells for interrupt vectors.
- HEADER(XT_UINIT,5,"uinit",DOROM)
-; CFG Area
- DW 2,XT_REC_FIND,XT_REC_NUM,0,0
- DW 1,CFG_FORTHWID,0,0,0,0,0,0,0
- DW XT_APPLTURNKEY ; TURNKEY vector
- DW RAMDICT ; HERE / DP
- DW ROMDICT ; IHERE / IDP
- DW INFODICT ; INFOHERE / INFODP
- DW CFG_FORTHWID ; CURRENT
- DW lastword ; FORTH WID
- DW lastenv ; environment WID
- DW XT_GET_CURRENT ; wlscope
- DW CFG_RECOGNIZERLISTLEN ; FORTH-RECOGNIZER
-
-.if WANT_INTERRUPTS==1
- DW XT_NOOP,XT_NOOP,XT_NOOP,XT_NOOP,XT_NOOP
- DW XT_NOOP,XT_NOOP,XT_NOOP,XT_NOOP,XT_NOOP
-.endif
-
-; USER Area
- DW 0,0 ; STATE/FOLLOWER
- DW 0,0,0 ; RP,SP0, SP
- DW 0 ; HANDLER
- DW 10 ; BASE
- DW XT_USART_TX_POLL
- DW XT_USART_TXQ_POLL
- DW XT_USART_RX_POLL
- DW XT_USART_RXQ_POLL
- DW XT_SOURCETIB
- DW 0 ; >IN
- DW XT_REFILLTIB
- DW XT_DEFAULT_PROMPTOK
- DW XT_DEFAULT_PROMPTERROR
- DW XT_DEFAULT_PROMPTREADY
diff --git a/amforth-6.5/msp430/words/um-slash-mod.asm b/amforth-6.5/msp430/words/um-slash-mod.asm
deleted file mode 100644
index 3904e8d..0000000
--- a/amforth-6.5/msp430/words/um-slash-mod.asm
+++ /dev/null
@@ -1,31 +0,0 @@
-;C UM/MOD ud u1 -- u2 u3 unsigned 32/16->16
- CODEHEADER(XT_UMSLASHMOD,6,"um/mod")
- ; IROP1 = TOS register
- MOV @PSP+,IROP2M ; get ud hi
- MOV @PSP,IROP2L ; get ud lo, leave room on stack
-;
-; T.I. UNSIGNED DIVISION SUBROUTINE 32-BIT BY 16-BIT
-; IROP2M|IROP2L : IROP1 -> IRACL REMAINDER IN IROP2M
-; RETURN: CARRY = 0: OK CARRY = 1: QUOTIENT > 16 BITS
-DIVIDE: CLR IRACL ; CLEAR RESULT
- MOV #17,IRBT ; INITIALIZE LOOP COUNTER
-DIV1: CMP IROP1,IROP2M ;
- JLO DIV2
- SUB IROP1,IROP2M
-DIV2: RLC IRACL
- JC DIV4 ; Error: result > 16 bits
- DEC IRBT ; Decrement loop counter
- JZ DIV3 ; Is 0: terminate w/o error
- RLA IROP2L
- RLC IROP2M
- JNC DIV1
- SUB IROP1,IROP2M
- SETC
- JMP DIV2
-DIV3: CLRC ; No error, C = 0
-DIV4: ; Error indication in C
-; END T.I. ROUTINE Section 5.1.5 of MSP430 Family Application Reports
- MOV IROP2M,0(PSP) ; remainder on stack
- MOV IRACL,TOS ; quotient in TOS
- NEXT
-
diff --git a/amforth-6.5/msp430/words/um-star.asm b/amforth-6.5/msp430/words/um-star.asm
deleted file mode 100644
index 7b031b0..0000000
--- a/amforth-6.5/msp430/words/um-star.asm
+++ /dev/null
@@ -1,38 +0,0 @@
-;C UM* u1 u2 -- ud unsigned 16x16->32 mult.
- CODEHEADER(XT_UMSTAR,3,"um*")
-.ifdef MPY
- dint
- mov @PSP, &MPY
- mov TOS, &OP2
- nop ; 1 cycle for calculation
- mov &RESLO, 0(PSP)
- mov &RESHI, TOS
- eint
-.else
- ; IROP1 = TOS register
- MOV @PSP,IROP2L ; get u1, leave room on stack
- PUSH IRACL ; possibly used as register B
-;
-; T.I. SIGNED MULTIPLY SUBROUTINE: IROP1 x IROP2L -> IRACM|IRACL
-MPYU: CLR IRACL ; 0 -> LSBs RESULT
- CLR IRACM ; 0 -> MSBs RESULT
-; UNSIGNED MULTIPLY AND ACCUMULATE SUBROUTINE:
-; (IROP1 x IROP2L) + IRACM|IRACL -> IRACM|IRACL
-MACU: CLR IROP2M ; MSBs MULTIPLIER
- MOV #1,IRBT ; BIT TEST REGISTER
-L_002: BIT IRBT,IROP1 ; TEST ACTUAL BIT
- JZ L_01 ; IF 0: DO NOTHING
- ADD IROP2L,IRACL ; IF 1: ADD MULTIPLIER TO RESULT
- ADDC IROP2M,IRACM
-L_01: RLA IROP2L ; MULTIPLIER x 2
- RLC IROP2M
-;
- RLA IRBT ; NEXT BIT TO TEST
- JNC L_002 ; IF BIT IN CARRY: FINISHED
-; END T.I. ROUTINE section 5.1.1 of MSP430 Family Application Reports
- MOV IRACL,0(PSP) ; low result on stack
- MOV IRACM,TOS ; high result in TOS
- POP IRACL ; possibly used as register B
-
-.endif
- NEXT
diff --git a/amforth-6.5/msp430/words/unloop.asm b/amforth-6.5/msp430/words/unloop.asm
deleted file mode 100644
index ac8e5a6..0000000
--- a/amforth-6.5/msp430/words/unloop.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C UNLOOP -- R: sys1 sys2 -- drop loop parms
- CODEHEADER(XT_UNLOOP,6,"unloop")
- MOV @RSP+,INDEX ; restore old loop values
- MOV @RSP+,LIMIT
- NEXT
diff --git a/amforth-6.5/msp430/words/up.asm b/amforth-6.5/msp430/words/up.asm
deleted file mode 100644
index a3674d1..0000000
--- a/amforth-6.5/msp430/words/up.asm
+++ /dev/null
@@ -1,11 +0,0 @@
-
-CODEHEADER(XT_UP_FETCH,3,"up@")
- SUB #2,PSP
- MOV TOS, 0(PSP)
- MOV UP,TOS
- NEXT
-
-CODEHEADER(XT_UP_STORE,3,"up!")
- MOV TOS,UP
- MOV @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/usart-rx.asm b/amforth-6.5/msp430/words/usart-rx.asm
deleted file mode 100644
index 16bd4c1..0000000
--- a/amforth-6.5/msp430/words/usart-rx.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-;C KEY -- c get character from keyboard
- HEADER(XT_USART_RX_POLL,2,"rx",DOCOLON)
-KEYLOOP:
- .DW XT_KEYQ
- .dw XT_DOCONDBRANCH
- DEST(KEYLOOP)
- .dw XT_DOLITERAL
- .dw USART_RX_DATA
- .dw XT_CFETCH
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/usart-rxq.asm b/amforth-6.5/msp430/words/usart-rxq.asm
deleted file mode 100644
index cc79509..0000000
--- a/amforth-6.5/msp430/words/usart-rxq.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-;X KEY? -- f return true if char waiting
-
-HEADER(XT_USART_RXQ_POLL,3,"rx?",DOCOLON)
- .dw XT_PAUSE
- .dw XT_DOLITERAL
- .dw bm_USART_RXRD
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw USART_RX_CFG
- .dw XT_CFETCH
- .dw XT_AND
- .dw XT_EQUAL
- .dw XT_EXIT
-
diff --git a/amforth-6.5/msp430/words/usart-tx.asm b/amforth-6.5/msp430/words/usart-tx.asm
deleted file mode 100644
index 07b0f5a..0000000
--- a/amforth-6.5/msp430/words/usart-tx.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ----------------------------------------------------------------------
-; TERMINAL I/O (TARGET-SPECIFIC)
-
-;C EMIT c -- output character to console
- HEADER(XT_USART_TX_POLL,2,"tx",DOCOLON)
-
-EMITLOOP:
- .dw XT_EMITQ
- .dw XT_DOCONDBRANCH
- DEST(EMITLOOP)
- .dw XT_DOLITERAL
- .dw USART_TX_DATA
- .dw XT_CSTORE
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/usart-txq.asm b/amforth-6.5/msp430/words/usart-txq.asm
deleted file mode 100644
index 9868346..0000000
--- a/amforth-6.5/msp430/words/usart-txq.asm
+++ /dev/null
@@ -1,15 +0,0 @@
-; ----------------------------------------------------------------------
-; TERMINAL I/O (TARGET-SPECIFIC)
-
-;C EMIT? c -- output character to console
-HEADER(XT_USART_TXQ_POLL,3,"tx?",DOCOLON)
- .dw XT_PAUSE
- .dw XT_DOLITERAL
- .dw bm_USART_TXRD
- .dw XT_DUP
- .dw XT_DOLITERAL
- .dw USART_TX_CFG
- .dw XT_CFETCH
- .dw XT_AND
- .dw XT_EQUAL
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/user.asm b/amforth-6.5/msp430/words/user.asm
deleted file mode 100644
index e436355..0000000
--- a/amforth-6.5/msp430/words/user.asm
+++ /dev/null
@@ -1,9 +0,0 @@
-;Z USER n -- define user variable with offset 'n'
- HEADER(XT_USER,4,"user",DOCOLON)
- DW XT_DOCREATE,XT_COMPILE, DOUSER, XT_COMMA, XT_REVEAL,XT_EXIT
-DOUSER: ; -- a-addr ; add constant to User Pointer, result in TOS
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV @W,TOS
- ADD UP,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/wlscope.asm b/amforth-6.5/msp430/words/wlscope.asm
deleted file mode 100644
index a0f8dd0..0000000
--- a/amforth-6.5/msp430/words/wlscope.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-
-DEFER(XT_WLSCOPE,7,"wlscope")
- .dw CFG_WLSCOPE
- .dw XT_CFGDEFERFETCH
- .dw XT_CFGDEFERSTORE
diff --git a/amforth-6.5/msp430/words/wordlist.asm b/amforth-6.5/msp430/words/wordlist.asm
deleted file mode 100644
index d2b550c..0000000
--- a/amforth-6.5/msp430/words/wordlist.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- wid )
-; Search Order
-; create a new, empty wordlist
-HEADER(XT_WORDLIST,8,"wordlist",DOCOLON)
- .dw XT_INFODP
- .dw XT_FETCH
- .dw XT_ZERO
- .dw XT_OVER
- .dw XT_STORE
- .dw XT_DUP
- .dw XT_CELLPLUS
- .dw XT_INFODP
- .dw XT_STORE
- .dw XT_EXIT
diff --git a/amforth-6.5/msp430/words/xor.asm b/amforth-6.5/msp430/words/xor.asm
deleted file mode 100644
index 2989f4c..0000000
--- a/amforth-6.5/msp430/words/xor.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-
-;C XOR x1 x2 -- x3 logical XOR
- CODEHEADER(XT_XOR,3,"xor")
- XOR @PSP+,TOS
- NEXT
diff --git a/amforth-6.5/msp430/words/zero-equal.asm b/amforth-6.5/msp430/words/zero-equal.asm
deleted file mode 100644
index 2c159e2..0000000
--- a/amforth-6.5/msp430/words/zero-equal.asm
+++ /dev/null
@@ -1,5 +0,0 @@
-;C 0= n/u -- flag return true if TOS=0
- CODEHEADER(XT_ZEROEQUAL,2,"0=")
- SUB #1,TOS ; borrow (clear cy) if TOS was 0
- SUBC TOS,TOS ; TOS=-1 if borrow was set
- NEXT
diff --git a/amforth-6.5/msp430/words/zero-less.asm b/amforth-6.5/msp430/words/zero-less.asm
deleted file mode 100644
index 2b8252f..0000000
--- a/amforth-6.5/msp430/words/zero-less.asm
+++ /dev/null
@@ -1,6 +0,0 @@
-;C 0< n -- flag true if TOS negative
- CODEHEADER(XT_ZEROLESS,2,"0<")
- ADD TOS,TOS ; set cy if TOS negative
- SUBC TOS,TOS ; TOS=-1 if carry was clear
- XOR #-1,TOS ; TOS=-1 if carry was set
- NEXT
diff --git a/amforth-6.5/readme.txt b/amforth-6.5/readme.txt
deleted file mode 100644
index acf0eb1..0000000
--- a/amforth-6.5/readme.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-Author:
- Matthias Trute <mtrute@users.sourceforge.net>
-
-Major Contributors:
- Erich Waelde
- Michael Kalus
- Leon Maurer
- Ullrich Hoffmann
- Karl Lund
- Enoch
- Bradford Rodriguez (MSP430 code from Camelforth 0.5)
-
-License: General Public License (GPL) Version 3 from 2007. See the
-file LICENSE.txt or http://www.gnu.org/licenses/gpl.html. This
-license applies to all files unless a file has some different
-attribution in it.
-
-AmForth is an interactive 16-bit Forth for Atmel ATmega and
-Texas Instruments MSP430 microcontrollers. It does not need
-additional hard or software. It works completely on the
-controller (no cross-compiler). AmForth uses the indirect
-threading forth implementation technique.
-
-ATmega:
-
- The forth dictionary is in the flash memory, new words are compiled
- directly into flash. Since no (widely available) bootloader supports
- an API to write to flash, AmForth uses the bootloader space itself.
-
-MSP430
-
- The Forth dictionary is in the flash or FRAM memory, new words are
- compiled to it. Use SAVE to keep the code accessible across
- reboots. The flash devices cannot rewrite the flash cell once a
- word is written.
-
-AmForth is implemented in assembly and forth. The code is stable
-and well tested. The MSP430 variant is newer and may have less
-features.
-
-All words have Forth 2012 (CORE and various extenion word sets)
-stack diagrams, but not necessarily the complete semantics. Some
-words from the standards are left out, ask for them if you need them.
-
-Development hardware are evaluation boards running various Atmega's
-between 2 and 20 MHz with various external hardware: none,
-led, push-buttons, SD-card, ethernet controller, RF module etc.
-The MSP430 code is tested with Launchpads.
-
-Documentation can be found in the doc/ subdirectory and
-on the homepage http://amforth.sourceforge.net/.
-
-Contact, bug reports, questions, wishes etc:
- mailto:amforth-devel@lists.sourceforge.net
diff --git a/amforth-6.5/tests/assembler-test.frt b/amforth-6.5/tests/assembler-test.frt
deleted file mode 100644
index b769f3d..0000000
--- a/amforth-6.5/tests/assembler-test.frt
+++ /dev/null
@@ -1,58 +0,0 @@
-\ ----- Test AvrAsm -----
-
-only forth also assembler
-
-: loadtos, 24 Y+ ld, 25 Y+ ld, ; \ define macro
-: savetos, -Y 25 st, -Y 24 st, ; \ from macros.asm
-
-code dup_ savetos, end-code \ insert asm code
-code drop_ loadtos, end-code
-
-code ++_ \ ( x1 x2 x3 -- x4 )
- R14 2 ldi, \ + +
- label>
- R16 Y+ ld,
- R17 Y+ ld,
- R24 R16 add,
- R25 R17 adc,
- R14 1 subi,
- <radr brne,
-end-code
-
-previous
-
-\ code demojmp \ demo jump + dup
-\ adr> 0 jmp, \ -+
-\ label> \ | +>-+
-\ clc, \ | | |
-\ adr> rjmp, \ | | +-+
-\ nop, \ | | |
-\ <labelr \ | | +<+
-\ adr> brcc, \ | | +-+
-\ nop, \ | | |
-\ rot <labell \ +> | |
-\ swap <radr rjmp, \ '-+ |
-\ <labelb \ <-+
-\ savetos,
-\ end-code
-
-\ code demojmp \ version with vector
-\ adr> 0 jmp, 0 >lbl \ addr->lbl[0]
-\ label> 1 >lbl
-\ clc,
-\ adr> rjmp, 2 >lbl
-\ nop,
-\ 2 <lbl <labelr
-\ adr> brcc, 3 >lbl
-\ nop,
-\ 0 <lbl <labell \ lbl[0]->tos
-\ 1 <lbl <radr rjmp,
-\ 3 <lbl <labelb
-\ savetos,
-\ end-code
-
-
-2 3 4 ++_ . \ 9
-5 6 drop_ dup_ . . \ 5 5
-
-\ end of file
diff --git a/amforth-6.5/tests/multitask-test.frt b/amforth-6.5/tests/multitask-test.frt
deleted file mode 100644
index a479280..0000000
--- a/amforth-6.5/tests/multitask-test.frt
+++ /dev/null
@@ -1,45 +0,0 @@
-\ lib/multitask-test.frt
-
-$38 constant PORTB
-$37 constant DDRB
-
-include lib/multitask.frt \ load the multitasker
-
-: ms ( n -- ) \ call pause on wait
- 0 ?do pause 1ms loop ;
-
- \ create a persistent task
-variable N
-: init
- $ff PORTB c! \ portB: all pins high
- $ff DDRB c! \ all pins output
- 0 N !
-;
-\ --- task 2 ---
-: run-demo
- begin
- N @ invert PORTB c!
- 1 N +!
- &500 ms
- again
-;
-$40 $40 0 task: task_demo \ create task space
-: start-demo
- task_demo tcb>tid
- activate \ words after this line are run in new task
- run-demo
-;
-: starttasker
- task_demo task-init \ create TCB in RAM
- start-demo \ activate tasks job
-
- onlytask \ make cmd loop task-1
- task_demo tcb>tid alsotask \ start task-2
- multi \ activate multitasking
-;
-: run-turnkey
- applturnkey
- init
- starttasker
-;
-' run-turnkey is turnkey \ make run-turnkey start on power up
diff --git a/amforth-6.5/tests/quotations-test.frt b/amforth-6.5/tests/quotations-test.frt
deleted file mode 100644
index 26057a8..0000000
--- a/amforth-6.5/tests/quotations-test.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ anonymous definitions in a definition
-
-: if-else ( ... f xt1 xt2 -- ... )
-\ Postscript-style if-else
- rot if
- drop
- else
- nip
- then
- execute ;
-
-: test ( f -- )
- [: ." true" ;]
- [: ." false" ;]
- if-else ;
-
-\ 1 test cr \ writes "true"
-\ 0 test cr \ writes "false"
-
diff --git a/amforth-6.5/tests/test-quotations.frt b/amforth-6.5/tests/test-quotations.frt
deleted file mode 100644
index 87c99d5..0000000
--- a/amforth-6.5/tests/test-quotations.frt
+++ /dev/null
@@ -1,19 +0,0 @@
-\ anonymous definitions in a definition
-
-: if-else ( ... f xt1 xt2 -- ... )
-\ Postscript-style if-else
- rot if
- drop
- else
- nip
- then
- execute ;
-
-: test ( f -- )
- [: ." true" ;]
- [: ." false" ;]
- if-else ;
-
-1 test cr \ writes "true"
-0 test cr \ writes "false"
-
diff --git a/amforth-6.5/tests/test-rega.frt b/amforth-6.5/tests/test-rega.frt
deleted file mode 100644
index 58e06c1..0000000
--- a/amforth-6.5/tests/test-rega.frt
+++ /dev/null
@@ -1,41 +0,0 @@
-\ #requires tester-amforth.frt
-
-TESTING VM Register A
-hex
-
-\ ------------------------------------------------------------------------
-TESTING basic assumtions
-
-variable atest 10 allot
-atest >a
-
-0 constant false
--1 constant true
-
-$55aa constant pattern
-
-
-{ a> atest = -> true }
-{ pattern a! -> }
-\ address must not change
-{ a> atest = -> true }
-{ a@ pattern = -> true }
-\ address must not change
-{ a> atest = -> true }
-
-TESTING address changes.
-{ pattern a!+ -> }
-\ address must increase by 1 cell
-{ a> atest cell+ = -> true }
-
-{ pattern a!- -> }
-\ address must decrease by 1 cell
-{ a> atest = -> true }
-
-{ a@+ pattern = -> true }
-\ address must increase by 1 cell
-{ a> atest cell+ = -> true }
-
-{ a@- pattern = -> true }
-\ address must decrease by 1 cell
-{ a> atest = -> true }
diff --git a/amforth-6.5/tools/am4up.c b/amforth-6.5/tools/am4up.c
deleted file mode 100644
index 3c9a46f..0000000
--- a/amforth-6.5/tools/am4up.c
+++ /dev/null
@@ -1,120 +0,0 @@
-// Filter to upload files to amforth from minicom
- // Al Williams http://www.hotsolder.com
-// Originally for the elf (if you were wondering about the names)
-// 17 Sept 2010 -- Public Domain
-// 22 Sept 2010 -- Added forced return at end of file
- #include <stdio.h>
- #include <stdlib.h>
- #include <unistd.h>
- #include <time.h>
-
- // Minicom uploader has stdin connected to serial input,
- // stdout connected to serial output
- // stderr connects back to minicom
- // exit code 0 for success or non zero for fail
-
- // To set this up, use Control+AO and configure file transfer
- // protcols. Set a name and the program file name
- // Set Name=Y, U/D to U, FullScrn to N, IO-Red to Y, and Multi to N
-
-// OR you can put this in /etc/minicom/minirc.amforth
-
-/**************** Start file on line below
-# Machine-generated file - use setup menu in minicom to change parameters.
-pu pname10 YUNYNamforth
-pu pprog10 am4up
-pu baudrate 9600
-pu bits 8
-pu parity N
-pu stopbits 1
-pu minit
-pu mreset
-pu backspace BS
-pu rtscts No
-
- **************** Line above was the last line of the file */
-// Then start minicom like this:
-// minicom -w -D /dev/ttyUSB1 amforth
-// This presumes you have am4up (this file compiled with gcc) on your path
-// and you are using /dev/ttyUSB1.
-//
-// To compile this file:
-// gcc -o am4up am4up.c
-// Then copy the am4up executable to your path somewhere
-
- // The character pacing is handled by waiting for the echo
- // The line pacing is handled by waiting for > or k
- // A ? in the prompt output indicates an error
- // Note you might still be in a defining word so
- // when you get an error you might have to enter a ; to get back
- // to a normal prompt.
-
-
- // wait for prompt -- errc is an error character
- void elfwait(int errc)
- {
- int c;
- // wait for response
- while ((c=getchar())!='>' && c!='k')
- {
- fputc(c,stderr);
- if (c==errc) { fprintf(stderr,"\nError - %c\n",errc); exit(2); }
- }
- fputc(c,stderr);
- }
-
-
- int main(int argc, char *argv[])
- {
- FILE *f=NULL;
- time_t t0,t1;
- int c;
- int lastchar;
- fprintf(stderr,"am4up V2 by Al Williams\nhttp://www.hotsolder.com\nUploading ");
- if (argc>1)
- {
- fprintf(stderr,"%s...\n",argv[1]);
- f=fopen(argv[1],"r");
- }
- if (!f) { fprintf(stderr, "No file\n"); exit(1); }
- putchar('\r'); putchar('\n');
- elfwait('\0');
- time(&t0);
- lastchar='\n';
- while (lastchar!=EOF)
- {
- int c1;
- c= getc(f);
- if (c==EOF && lastchar=='\n') break;
- // newline == CRLF
- if ((c=='\n'||c=='\r') && lastchar=='\n') continue; // blank line
- if (c=='\\' && lastchar=='\n')
- {
- // comment
- while (c!='\n' && c!=EOF) c=getc(f);
- if (c==EOF) break;
- continue;
- }
- // remember last character except leading blanks
- if (c==EOF || lastchar!='\n' || !isspace(c)) lastchar=c;
- if (c=='\t') c=' ';
- if (c=='\n') c='\r';
- if (c==EOF) c='\r'; // final return
- putchar(c);
- // read echo
- do
- {
- c1=getchar();
- fputc(c1,stderr);
- } while (c1!=c);
-
- if (c=='\r' || c==EOF)
- {
- elfwait('?');
- }
- }
- time(&t1);
- fprintf(stderr,"\nTransfer time=%ld seconds\n",t1-t0);
-
- return 0;
- }
diff --git a/amforth-6.5/tools/amforth-shell.py b/amforth-6.5/tools/amforth-shell.py
deleted file mode 100755
index 0c3a72f..0000000
--- a/amforth-6.5/tools/amforth-shell.py
+++ /dev/null
@@ -1,1365 +0,0 @@
-#!/usr/bin/python
-#
-# pySerial based upload & interpreter interaction module for amforth.
-#
-# Copyright 2011 Keith Amidon (camalot@picncipark.org)
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License version 2 as
-# published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-# Patcher remarks:
-# ================
-#
-# This uploader saves dictionary space and words clutter by substituting
-# uC register names and application constants with numbers. The
-# appl_defs.frt (Forth) file in the application's local directory
-# provides the constant definitions. In appl_defs.frt put each constant
-# on a line of its own. The first line, if it begins with a backslash
-# comment, would be echoed to the screen when uploading the Forth
-# code. It is recommended to place in appl_defs.frt global constant
-# definitions which would affect compilation of the library and the
-# project code. For example:
-#
-# \ Project Name
-# $d5 constant CRC8MSB
-# 10 constant max_number_of_users
-#
-# Invoke the shell with the argument --log log.frt to collect the lines
-# which were uploaded to the AmForth system that received an " ok"
-# response (log.frt is just a file-name example). This file can later be
-# uploaded to another system using a tool simpler than the shell. Leave
-# the shell by #exit to close log.frt properly.
-#
-# Invoke the shell with the argument --rtscts to enable serial port
-# RTS/CTS hardware handshake connection.
-#
-# =====================================================================
-# DOCUMENTATION
-# =====================================================================
-# This module module may be used as a script or imported for use as a
-# part of a larger python program.
-#
-# Script Usage
-# ------------
-# When used as a script this module provides two main functions, the
-# ability to reliably upload files to the amforth interpreter and an
-# interpreter interaction mode with line editing, word completion and
-# previous input history. For information on how to access these
-# features when invoking the module as a script, execute it with the
-# --help option and read the following sections on the interaction
-# protocol and local directives.
-#
-#
-# Interaction Protocol
-# --------------------
-# The amforth interaction protocol used by this module is to send a
-# line to amforth character by character, reading the echos as quickly
-# as possible. Once the entire line has been sent it then reads the
-# response up until the " ok" prompt or a prompt that looks like an
-# error response. The character by character handling of echos
-# appears to eliminate unexpected device resets when compared to the
-# line by line method used by previous tools, possibly by eliminating
-# the possibility of serial tx overrun on the device.
-#
-# To further optimize interaction with the device lines are evaluated
-# before sending and redundant whitespace is compressed out. Lines
-# which are all whitespace or whitespace and comments are not sent and
-# the next line is handled.
-#
-#
-# Local Directives
-# ----------------
-# A number of special directives are supported which instruct the
-# script to do something and are handled locally without being sent to
-# amforth. Directives may be specified within comments or outside
-# comments as controlled by the "#directive" directive. They must be
-# the only contents of a line or they will be ignored. The directives
-# include:
-#
-# #include <file>
-# Upload the named <file> before proceeding further.
-#
-# #require <file>
-# Like #include but would skip if <file> was already uploaded
-# during the shell session.
-#
-# #cd <dir>
-# Change the current local directory to the location specified.
-# During uploads, this directive affects the current file and
-# files it includes. Once the current file is complete the old
-# value will be restored.
-#
-# #directive <config>
-# Change how directives are discovered. The valid values for
-# <config> are:
-# none : Stop looking for any directives
-# commented : Only look for directives within comments
-# Commented directives must be the first word of the
-# comment. The remaining text in the comment is the
-# argument provided to the directive. There must
-# not be any other non-whitespace text other than
-# the comment start and (if required) end characters
-# and the directive and any directive argument on a
-# commented directive line. If any other text is
-# present on the line an error will be generated.
-# uncommented : Only look for directives outside comments.
-# Uncommented directives must be the first word of a
-# line and extend to the end of the line. If a
-# directive name exists in a subsequent word of a
-# line it will be sent to the interpreter as a word
-# like any other.
-# all : Allow both commented and uncommented directives.
-# This is the default.
-# During uploads, this directive affects the current file and
-# files it includes. Once the current file is complete the old
-# value will be restored.
-#
-# #timeout <float>
-# Change the timeout value to <float> seconds. Fractional
-# values are supported. During uploads, this directive affects
-# the current file and files it includes. Once the current file
-# is complete the old value will be restored.
-#
-# #timeout-next <float>
-# Change the timeout value for the next line sent to the
-# interpreter to <float> seconds. Fractional values are
-# supported. The timeout returns to its previous value after
-# the next line is sent to the interpreter. If this directive
-# is encountered as the very last line of an upload file it will
-# have no effect.
-#
-# #error-on-output [<yes-or-no>]
-# Controls whether an error is generated if unexpected output
-# occurs during an upload. The default is yes. This directive
-# can not be used in interactive mode as it would not have any
-# effect. During uploads it affects the rest of the current file
-# and any files it includes. The argument is optional. If not
-# given it is assumed to be "yes".
-#
-# #ignore-error [<yes-or-no>]
-# Ignore any error that occurs later in the current upload file
-# or a file it includes. The argument is optional. If given
-# the behavior is set as specified. If not given it is assumed
-# to be "yes".
-#
-# #ignore-error-next [<yes-or-no>]
-# Ignore any error that occurs on the next line. The argument
-# is optional. If given the behavior is set as specified. If
-# not given it is assumed to be "yes".
-#
-# #expect-output-next [<regexp>]
-# Expect specific output on the next line. The argument is
-# optional. If it is not specified a default regular expression
-# of ".*" (match everything) is assumed. This overrides the
-# #error-on-output directive. An error is raised if the output
-# doesn't match the regular expression. It will be ignored if
-# #ignore-error is yes. Use of this directive without an
-# argument is the way to prevent an error on output when
-# #error-on-output is yes
-#
-# #start-string-word <word>
-# Add a word that starts a string. The string will end when a
-# double quote character is read.
-#
-# #quote-char-word <word>
-# Add a word that quotes the immediately next word
-#
-# #interact
-# Start an interactive session before proceeding with file upload.
-# This only makes sense during a file upload.
-#
-# #edit [<filename>]
-# Edit a file. The filename is optional. If it is provided the
-# named file will be edited. If it is not provided and the last
-# upload ended in an error the file that had the error will be
-# edited at the location of the error. If there was no previous
-# upload or the last upload completed successfully but an #edit
-# directive was previously issued with a filename, edit the file
-# previously named. Finally, if none of these apply an error is
-# printed. The editor used can be specified with the --editor
-# option when starting the program or through the EDITOR
-# environment variable.
-#
-# #update-words
-# This directive is only available in an interactive session.
-# It cause the interaction code to reload the list of words used
-# for completion from the amforth interpreter. Typically it is
-# not required as words are updated automatically when the
-# session starts and any time a file is uploaded as a results of
-# a #include directive. The case where it is required is when
-# completion is needed for words defined interactively during
-# the session.
-#
-# #update-cpu
-# This directive is only available in an interactive session.
-# It causes the interaction code to read the controller name
-# from the device and tries to load a specific python module
-# which contains names for registers and addresses. These names
-# can be used in forth code and get replace with the corresponding
-# numbers.
-#
-# #exit
-# Exit an interactive session or the current upload immediately.
-# If encountered during an upload, no further lines from the
-# file will be processed.
-#
-#
-# Programmatic Usage
-# ------------------
-# For programmatic usage, a single class named AMForth is provided.
-# It can be instantiated with no arguments but typically a serial port
-# device and port speed will be provided as the defaults are unlikely
-# to be correct.
-#
-# Once an instance is obtained, and connected the high-level entry
-# points are the "upload_file" and "interact" methods, the former
-# uploading a file to the AMForth interperter and the latter providing
-# an interative interpreter shell with command history and word
-# completion. These methods provide progress information in various
-# cases by calling the function stored in the "progress_callback"
-# property with three arguments, the type of progress being reported,
-# a line number if available (otherwise it is None) and a message with
-# further information. The default progress callback prints this
-# information to the screen in a terse format. Other programs may
-# wish to replace this with their own progress presentation function.
-#
-# Low-level interaction with the AMForth interpreter would typically
-# use the "send_line" and "read_response" methods. Before these can
-# be used the serial connection must be established. The
-# serial_connected property indicates whether a connection currently
-# exists. A good way to obtain a connection and rule out errors in
-# serial communication is to call "find_prompt" which ensures the
-# existence of a serial connection and sends a newline to the AMForth
-# interperter and watches for the echo. This is usually the best way
-# of establishing a connection but the "serial_connect" method will
-# open a connection without sending anything if that is required.
-#
-# Elimination of whitespace and discovery of directives (see below) is
-# provided through the "preprocess_line" method and directives that
-# have common implementations can be handled with the
-# "handle_common_directives" method.
-
-# TODO: - Update comments on most functions explaining what they do.
-
-import argparse
-import atexit
-import copy
-import glob
-import os
-import re
-import readline
-import serial
-import StringIO
-import subprocess
-import sys
-import traceback
-
-class AMForthException(Exception):
- pass
-
-class Behaviors(object):
- """Simple class for storing configurable processing behaviors"""
- def __init__(self):
- self.working_directory = os.getcwd()
- self.filename = None
- self.timeout = 15.0
- self.quote_char_words = ["[char]", "char"]
- self.start_string_words = ['s"', '."', 'abort"']
- self.error_on_output = True
- self.ignore_errors = False
- self.directive_uncommented = True
- self.directive_commented = True
- self.expected_output_regexp = None
-
- @property
- def directive_config(self):
- "Get the current directive configuration"
- if self.directive_uncommented:
- if self.directive_commented:
- return "all"
- else:
- return "uncommented"
- else:
- if self.directive_commented:
- return "commented"
- else:
- return "none"
-
- @directive_config.setter
- def directive_config(self, value):
- "Set the directive configuration"
- if value == "none":
- self.directive_uncommented = False
- self.directive_commented = False
- elif value == "all":
- self.directive_uncommented = True
- self.directive_commented = True
- elif value == "uncommented":
- self.directive_uncommented = True
- self.directive_commented = False
- elif value == "commented":
- self.directive_uncommented = False
- self.directive_commented = True
- else:
- raise AMForthException("Unknown directive config: %s" % value)
-
-
-class BehaviorManager(object):
- """Class for determining currently configured behavior
-
- This class manages the lifetime of behaviors established through
- configuration options and directives to minimize the impact of
- that support on the AMForth class. """
- def __init__(self):
- self.default_behavior = Behaviors()
- self.clear()
-
- def clear(self):
- "Clear out accumulated behavior"
- self._next_line_behavior = None
- self._current_line_behavior = None
- self._file_behaviors = []
-
- @property
- def current_behavior(self):
- """The behavior currently in effect"""
- if self._current_line_behavior:
- return self._current_line_behavior
- elif self._file_behaviors:
- return self._file_behaviors[0]
- else:
- return self.default_behavior
-
- def advance_line(self):
- """Call when changing to the next line"""
- self._current_line_behavior = self._next_line_behavior
- self._next_line_behavior = None
-
- def push_file(self, filename):
- """Call when starting processing a new nested file"""
- behavior = copy.deepcopy(self.current_behavior)
- behavior.filename = filename
- self._file_behaviors.insert(0, behavior)
-
- def pop_file(self):
- """Call when returning from a nested file"""
- del(self._file_behaviors[0])
-
- @property
- def next_line_behavior(self):
- """The behavior to use for the next line"""
- return self._next_line_behavior
-
- @next_line_behavior.setter
- def next_line_behavior(self, behavior):
- self._next_line_behavior = behavior
-
- @property
- def current_file_behavior(self):
- """The behavior for the current file.
-
- Will raise an exception if there is no file currently."""
- return self._file_behaviors[0]
-
- @current_file_behavior.setter
- def current_file_behavior(self, behavior):
- self._file_behaviors[0] = behavior
-
-
-class AMForth(object):
- "Class for interacting with the AMForth interpreter"
-
- amforth_error_cre = re.compile(" \?\? -\d+ \d+ \r\n> $")
- upload_directives = [
- "#cd", "#require", "#include", "#directive", "#ignore-error",
- "#ignore-error-next", "#error-on-output", "#expect-output-next",
- "#string-start-word", "#quote-char-word",
- "#timeout", "#timeout-next", "#interact", "#exit"
- ]
- interact_directives = [
- "#cd", "#edit", "#require", "#include", "#directive", "#ignore-error",
- "#error-on-output", "#string-start-word", "#quote-char-word",
- "#timeout", "#timeout-next", "#update-words", "#exit",
- "#update-cpu", "#update-files"
- ]
- # standard words are usually uppercase, but amforth needs
- # them in lowercase.
- stdwords = [
- # *** Wordset BLOCK
- "BLK","BLOCK","BUFFER","EVALUATE","FLUSH","LOAD","SAVE-BUFFERS",
- "UPDATE",
- # *** Wordset BLOCK-EXT
- "EMPTY-BUFFERS","LIST","REFILL","SCR","THRU",
- # *** Wordset CORE
- "#S","*/MOD","+LOOP","/MOD","0<","0=","1+","1-","2!",
- "2*","2/","2@","2DROP","2DUP","2OVER","2SWAP",">BODY",
- ">IN",">NUMBER",">R","?DUP","ABORT","ABORT\"","ABS",
- "ACCEPT","ALIGN","ALIGNED","ALLOT","AND","BASE","BEGIN",
- "BL","C!","C,","C@","CELL+","CELLS","CHAR","CHAR+",
- "CHARS","CONSTANT","COUNT","CR","CREATE","DECIMAL",
- "DEPTH","DO","DOES>","DROP","DUP","ELSE","EMIT","ENVIRONMENT?",
- "EVALUATE","EXECUTE","EXIT","FILL","FIND","FM/MOD",
- "HERE","HOLD","I","IF","IMMEDIATE","INVERT","J","KEY",
- "LEAVE","LITERAL","LOOP","LSHIFT","M*","MAX","MIN",
- "MOD","MOVE","NEGATE","OR","OVER","POSTPONE","QUIT",
- "R>","R@","RECURSE","REPEAT","ROT","RSHIFT","S\"","S>D",
- "SIGN","SM/REM","SOURCE","SPACE","SPACES","STATE","SWAP",
- "THEN","TYPE","U.","U<","UM*","UM/MOD","UNLOOP","UNTIL",
- "VARIABLE","WHILE","WORD","XOR","[CHAR]",
- # *** Wordset CORE-EXT
- ".R","0<>",
- "0>","2>R","2R>","2R@",":NONAME","?DO","AGAIN","C\"",
- "CASE","COMPILE,","ENDCASE","ENDOF","ERASE","FALSE",
- "HEX","MARKER","NIP","OF","PAD","PARSE","PICK","REFILL",
- "RESTORE-INPUT","ROLL","SAVE-INPUT","SOURCE-ID","TO",
- "TRUE","TUCK","U.R","U>","UNUSED","VALUE","WITHIN",
- "[COMPILE]",
- # *** Wordset CORE-EXT-obsolescent
- "#TIB","CONVERT","EXPECT","QUERY","SPAN",
- "TIB",
- # *** Wordset DOUBLE
- "2CONSTANT","2LITERAL","2VARIABLE","D+","D-",
- "D.","D.R","D0<","D0=","D2*","D2/","D<","D=","D>S",
- "DABS","DMAX","DMIN","DNEGATE","M*/","M+",
- # *** Wordset DOUBLE-EXT
- "2ROT","DU<",
- # *** Wordset EXCEPTION
- "CATCH","THROW",
- # *** Wordset EXCEPTION-EXT
- "ABORT","ABORT\"",
- # *** Wordset FACILITY
- "AT-XY","KEY?","PAGE",
- # *** Wordset FACILITY-EXT
- "EKEY","EKEY>CHAR","EKEY?","EMIT?","MS","TIME&DATE",
- # *** Wordset FILE
- "BIN","CLOSE-FILE","CREATE-FILE","DELETE-FILE","FILE-POSITION",
- "FILE-SIZE","INCLUDE-FILE","INCLUDED","OPEN-FILE","R/O",
- "R/W","READ-FILE","READ-LINE","REPOSITION-FILE","RESIZE-FILE",
- "S\"","SOURCE-ID","W/O","WRITE-FILE","WRITE-LINE",
- # *** Wordset FILE-EXT
- "FILE-STATUS",
- "FLUSH-FILE","REFILL","RENAME-FILE",
- # *** Wordset FLOAT
- ">FLOAT","D>F",
- "F!","F*","F+","F-","F/","F0<","F0=","F<","F>D","F@",
- "FALIGN","FALIGNED","FCONSTANT","FDEPTH","FDROP","FDUP",
- "FLITERAL","FLOAT+","FLOATS","FLOOR","FMAX","FMIN",
- "FNEGATE","FOVER","FROT","FROUND","FSWAP","FVARIABLE",
- "REPRESENT",
- # *** Wordset FLOAT-EXT
- "DF!","DF@","DFALIGN","DFALIGNED","DFLOAT+",
- "DFLOATS","F**","F.","FABS","FACOS","FACOSH","FALOG",
- "FASIN","FASINH","FATAN","FATAN2","FATANH","FCOS","FCOSH",
- "FE.","FEXP","FEXPM1","FLN","FLNP1","FLOG","FS.","FSIN",
- "FSINCOS","FSINH","FSQRT","FTAN","FTANH","F~","PRECISION",
- "SET-PRECISION","SF!","SF@","SFALIGN","SFALIGNED","SFLOAT+",
- "SFLOATS",
- # *** Wordset LOCAL
- "(LOCAL)","TO",
- # *** Wordset LOCAL-EXT
- "LOCALS|",
- # *** Wordset MEMORY
- "ALLOCATE","FREE",
- "RESIZE",
- # *** Wordset SEARCH
- "DEFINITIONS","FIND","FORTH-WORDLIST","GET-CURRENT",
- "GET-ORDER","SEARCH-WORDLIST","SET-CURRENT","SET-ORDER",
- "WORDLIST",
- # *** Wordset SEARCH-EXT
- "ALSO","FORTH","ONLY","ORDER","PREVIOUS",
- # *** Wordset STRING
- "-TRAILING","/STRING","BLANK","CMOVE","CMOVE>","COMPARE",
- "SEARCH","SLITERAL",
- # *** Wordset TOOLS
- ".S","DUMP","SEE","WORDS",
- # *** Wordset TOOLS-EXT
- ";CODE",
- "AHEAD","ASSEMBLER","BYE","CODE","CS-PICK","CS-ROLL",
- "EDITOR","STATE","[ELSE]","[IF]","[THEN]",
- # *** Wordset TOOLS-EXT-obsolescent
- "FORGET",
- # *** Tester wordset
- "T{", "}T",
- ]
- def __init__(self, serial_port="/dev/amforth", rtscts=False, speed=38400):
- self.debug = False
- self.max_line_length = 90
- self.progress_callback = self.print_progress
- self.editor = None
- self._serial_port = serial_port
- self._serial_rtscts = rtscts
- self._serial_speed = speed
- self._serialconn = None
- self._readline_initialized = False
- self._amforth_dp = None
- self._filedirs = {}
- self._search_path = []
- self._uploaded = set()
- self._update_uploaded = False
- self._amforth_words = []
- self._amforth_regs = {}
- self._amforth_cpu = ""
- self._last_error = ()
- self._last_edited_file = None
- self._config = BehaviorManager()
- if os.environ.has_key("AMFORTH_LIB"):
- self._search_list = os.environ["AMFORTH_LIB"].split(":")
- else:
- self._search_list=["."]
-
- # define application constants to substitute
- try:
- ad_file = open("appl_defs.frt")
- ad_line = ad_file.readline()
- ad_mat = re.match("^\\\\\s+(\S.*)\n", ad_line)
- if ad_mat:
- self.progress_callback("Information", None, "appl_defs: " + ad_mat.group(1))
- ad_pat=re.compile("^\s*(\S+)\s+constant\s+(\S+)\s")
- ad_def = {}
- while ad_line:
- ad_mat = ad_pat.match(ad_line)
- if ad_mat:
- ad_def[ad_mat.group(2)] = ad_mat.group(1)
- ad_line = ad_file.readline()
- except:
- ad_def = {}
- self.progress_callback("Information", None, "appl_defs: %d loaded" % len(ad_def))
- self._appl_defs = ad_def
-
- @property
- def serial_port(self):
- "Serial port device attached to AMForth"
- return self._serial_port
-
- @serial_port.setter
- def serial_port(self, value):
- """Set the serial port device attached to AMForth
-
- If the value provided is different than the current value any
- existing serial connection will be closed and a new connection
- opened."""
- if self._serial_port != value:
- self._serial_port = value
- self.serial_reconnect()
-
- @property
- def serial_rtscts(self):
- "RTS/CTS enable of serial connection to AMForth"
- return self._serial_rtscts
-
- @serial_rtscts.setter
- def serial_rtscts(self, value):
- if self._serial_rtscts != value:
- self._serial_rtscts = value
- self.serial_reconnect()
-
- @property
- def serial_speed(self):
- "Speed of the serial connection to AMForth"
- return self._serial_speed
-
- @serial_speed.setter
- def serial_speed(self, value):
- if self._serial_speed != value:
- self._serial_speed = value
- self.serial_reconnect()
-
- @property
- def serial_connected(self):
- "Boolean status for whether currently connected to AMForth"
- return self._serialconn is not None
-
- def main(self):
- "Main function called when module is used as a script"
- upload_files, interact = self.parse_arg()
- try:
- for fn in upload_files:
- if fn == "-":
- self.interact()
- else:
- self.upload_file(fn, install=True)
- if interact:
- self.interact()
- except AMForthException:
- return 1
- except KeyboardInterrupt:
- print "\nAborted with keyboard interrupt"
- except Exception, e:
- print "\n---- Unexpected exception ----"
- traceback.print_exc()
- return 1
- finally:
- self.serial_disconnect()
- if self._log:
- self._log.close()
- return 0
-
- def parse_arg(self):
- "Argument parsing used when module is used as a script"
- parser = argparse.ArgumentParser(description="Interact with AMForth",
- epilog="""
-The environment variable AMFORTH_LIB can be set with to a colon (:) separated
-list of directories that are recursivly searched for file names. If not set,
-the current work directory is used instead.
-
-The script assumes to be located in the standard amforth installation under
-the tools/ directory. It uses files from the core/devices directories for
-additional definitions (e.g. register names)
-"""
- )
- parser.add_argument("--timeout", "-t", action="store",
- type=float, default=15.0,
- help="Response timeout (seconds, float value)")
- parser.add_argument("--port", "-p", action="store",
- type=str, default=self.serial_port, help="Serial port name")
- parser.add_argument("--rtscts", action="store_true",
- default=self.serial_rtscts, help="Serial port RTS/CTS enable")
- parser.add_argument("--speed", "-s", action="store",
- type=int, default=self.serial_speed, help="Serial port speed")
- parser.add_argument("--log", type=argparse.FileType('w'),
- help="Uploaded Forth log-file")
- parser.add_argument("--line-length", "-l", action="store",
- type=int, default=self.max_line_length,
- help="Maximum length of amforth input line")
- parser.add_argument("--interact", "-i", action="store_true",
- help="Enter interactive prompt after upload")
- parser.add_argument("--directive", "-d", action="store",
- default="all",
- help="Local directive configuration (where found)")
- parser.add_argument("--editor", action="store",
- default = os.environ.get("EDITOR", None),
- help="Editor to use for #edit directive")
- parser.add_argument("--no-error-on-output", action="store_true",
- help="Indicate an error if upload causes output")
- parser.add_argument("--ignore-error", action="store_true",
- help="Ignore errors during upload (not recommended)")
- parser.add_argument("--debug-serial", action="store_true",
- help="Output extra info about serial transfers in stderr")
- parser.add_argument("--Include", "-I", action="append",
- help="Add Include directory")
- parser.add_argument("--uploaded-wl", "-U", action="store_true", default=False,
- help="Keep the list of uploaded filenames in the dictionary.")
-
- parser.add_argument("files", nargs="*", help="may be found via the environment variable AMFORTH_LIB")
- arg = parser.parse_args()
- self.debug = arg.debug_serial
- self.max_line_length = arg.line_length
- self._serial_port = arg.port
- self._serial_rtscts = arg.rtscts
- self._serial_speed = arg.speed
- self._log = arg.log
- self._update_uploaded = arg.uploaded_wl
- self.editor = arg.editor
- if arg.Include:
- self._search_list.extend(arg.Include)
- behavior = self._config.current_behavior
- behavior.error_on_output = not arg.no_error_on_output
- behavior.directive_config = arg.directive
- behavior.timeout = arg.timeout
- behavior.ignore_errors = arg.ignore_error
- return arg.files, (arg.interact or len(arg.files) == 0)
-
- def serial_connect(self, port=None, rtscts=None, speed=None):
- """Connect to AMForth on a serial port
-
- The port and speed argument are optional. If not specified
- the current values set in the object are used. These will be
- the defaults if the have not been changed. If either is
- specified corresponding property of the instance will be
- updated to the new value.
-
- This is safe to call even if a connection already exists as
- existing an existing connection will be closed before the new
- connection is made."""
- if port != None:
- self.serial_port = port
- if rtscts != None:
- self.serial_rtscts = rtscts
- if speed != None:
- self.serial_speed = speed
- if self._serialconn:
- self.serial_disconnect()
- try:
- timeout = self._config.current_behavior.timeout
- self._serialconn = serial.Serial(self.serial_port,
- self.serial_speed,
- serial.EIGHTBITS,
- serial.PARITY_NONE,
- serial.STOPBITS_ONE,
- timeout, False,
- self.serial_rtscts,
- None, False)
- except serial.SerialException, e:
- raise AMForthException("Serial port connect failure: %s" % str(e))
-
- def serial_disconnect(self):
- """Disconnect the serial connection to AMForth
-
- This is safe to call even if there is currently no connection."""
- if self._serialconn:
- self._serialconn.close()
- self._serialconn = None
-
- def serial_reconnect(self):
- """Reconnect the serial connection to AMForth
-
- This is the same as calling serial_connect while there is an
- existing connection. It is provided to make the clear when
- the intent is to re-establish an existing connection (usually
- to apply new settings) versus creating a new connectoion."""
- self.serial_connect()
-
- def find_prompt(self):
- "Attempt to find a prompt by sending a newline and verifying echo"
- if not self.serial_connected:
- self.serial_connect()
- # Use a short timeout to quickly detect if can't communicate
- self._serialconn.timeout = 2.0
- try:
- try:
- self.send_line("\n") # Get empty line echo to make sure ready
- self.read_response() # Throw away the response.
- except serial.SerialException, e:
- self.progress_callback("Error", None, str(e))
- raise AMForthException("Failed to get prompt: %s" % str(e))
- finally:
- # Restore the current timeout
- self._serialconn.timeout = self._config.current_behavior.timeout
-
- def upload_file(self, filename, install=False):
- if not install and filename in self._uploaded:
- return False
- else:
- self._uploaded.add(filename)
- self._update_files()
- if os.path.dirname(filename):
- fpath=filename
- self.progress_callback("Information", None, "using "+ filename+" verbatim")
- else:
- if not self._filedirs.has_key(filename):
- self.progress_callback("Error", None, "file "+ filename+" not found in search path")
- raise AMForthException("file " + filename + " not found in search path")
- if len(self._filedirs[filename])!=1:
- # oops, too many files or no one at all found?
- raise AMForthException("Wrong # of file occurances: " + filename + " ("+str(len(self._filedirs[filename]))+")\n\t"+"\n\t".join(self._filedirs[filename]))
- self.progress_callback("Information", None, "using "+ filename+" from"+ self._filedirs[filename][0])
- fpath = os.path.join(self._filedirs[filename][0], filename)
- self._config.push_file(fpath)
- fdir=os.path.dirname(fpath)
- print "**** " + self._config.current_behavior.working_directory
- if os.path.isabs(fdir):
- dirpath = os.path.normpath(fdir)
- else:
- oldpath = self._config.current_behavior.working_directory
- dirpath = os.path.normpath(os.path.join(oldpath, fdir))
- self._config.current_behavior.working_directory = dirpath
-
- try:
- try:
- self.find_prompt()
- except AMForthException, e:
- self.progress_callback("Error", None, str(e))
- raise
- if self._amforth_cpu=="":
- self._update_cpu()
- self._update_files()
- self.progress_callback("File", None, fpath)
- try:
- with open(fpath, "r") as f:
- self._send_file_contents(f)
- except (OSError, IOError), e:
- self.progress_callback("Error", None, str(e))
- raise AMForthException("Unknown file: " + fpath)
- self._last_error = ()
- finally:
- print "**** " + self._config.current_behavior.working_directory
- self._config.pop_file()
- self._serialconn.timeout = self._config.current_behavior.timeout
- try:
- os.chdir(self._config.current_behavior.working_directory)
- except OSError, e:
- errmsg = ("Failed to change to directory '%s': %s"
- % (self._config.current_behavior.working_directory,
- str(e)))
- self.progress_callback("Error", None, errmsg)
- raise AMForthException(errmsg)
- # update the included-wl on the controller
- if self._update_uploaded:
- self.send_line("get-current uploaded-wl set-current create " + filename + " set-current")
- return True
-
- def _send_file_contents(self, f):
- in_comment = False
- lineno = 0
- for full_line in f:
- self._config.advance_line()
- self._serialconn.timeout = self._config.current_behavior.timeout
- try:
- os.chdir(self._config.current_behavior.working_directory)
- except OSError, e:
- errmsg = ("Failed to change to directory '%s': %s"
- % (self._config.current_behavior.working_directory,
- str(e)))
- self.progress_callback("Error", None, errmsg)
- raise AMForthException(errmsg)
- lineno += 1
- if full_line and full_line[-1] == "\n":
- full_line = full_line[:-1]
- if full_line and full_line[-1] == "\r":
- full_line = full_line[:-1]
- line = full_line.strip()
- if len(line) == 0:
- if in_comment:
- self.progress_callback("Comment", lineno, full_line)
- else:
- self.progress_callback("Whitespace", lineno, full_line)
- continue
- try:
- (line, in_comment,
- directive,
- directive_arg) = self.preprocess_line(full_line, in_comment,
- self.upload_directives)
- except AMForthException, e:
- self._record_error(lineno)
- self.progress_callback("Error", lineno, full_line)
- self.progress_callback("Error", None, str(e))
- raise
- if directive:
- self.progress_callback("Directive", lineno, full_line)
- if directive == "#exit":
- break
- elif directive == "#interact":
- self.interact()
- continue
- self.handle_common_directives(directive, directive_arg)
- continue
- if len(line) == 0:
- self.progress_callback("Comment", lineno, full_line)
- continue
- try:
- self.send_line(line)
- except AMForthException, e:
- self._record_error(lineno)
- self.progress_callback("Error", lineno, full_line)
- self.progress_callback("Error", None, str(e))
- raise
- response = self.read_response()
- self.progress_callback("Sent", lineno, full_line)
- if response[-3:] == " ok":
- if len(response) > 3:
- for l in StringIO.StringIO(response[:-3]):
- self.progress_callback("Output", lineno, l.rstrip())
- r = self._config.current_behavior.expected_output_regexp
- if r:
- m = re.match(r, response[:-3], re.MULTILINE)
- response_ok = m is not None
- else:
- response_ok = False
- if not response_ok:
- if self._config.current_behavior.error_on_output:
- errmsg = "Unexpected output after line."
- errmsg += " To allow, specify --no-error-on-output."
- self.progress_callback("Error", lineno, errmsg)
- if not self._config.current_behavior.ignore_errors:
- self._record_error(lineno)
- raise AMForthException(errmsg)
- elif self._log:
- self._log.write(line + "\n")
-
- else:
- self.progress_callback("Error", None, response)
- if not self._config.current_behavior.ignore_errors:
- self._record_error(lineno)
- raise AMForthException("Error in line sent")
-
- def preprocess_line(self, line, in_delim_comment=False, directives=[]):
- # Compresses whitespace, including comments so send minimum
- # data to atmega
- result = []
- comment_words = []
- char_quote = False
- in_string = False
- in_line_comment = False
- directive = None
- directive_arg = []
- words = self._split_space_or_tab(line)
- for iw,w in enumerate(words):
- if in_string:
- try:
- i = w.index('"')
- except ValueError:
- result[-1] += " " + w
- continue
- in_string = False
- result[-1] += " " + w[:i+1]
- result[-1] = result[-1][1:] # remove extra initial space
- w = w[i+1:]
-
- if in_delim_comment:
- try:
- i = w.index(")")
- except ValueError:
- pass
- else:
- in_delim_comment = False
- w = w[i+1:]
-
- if not w:
- continue
- if w in self._appl_defs:
- w = self._appl_defs[w]
- elif w in self._amforth_regs:
- w = self._amforth_regs[w]
- elif w.upper() in self.stdwords:
- w = w.lower()
- if char_quote:
- result.append(w)
- char_quote = False
- continue
-
- if w == "(":
- if not in_delim_comment:
- in_delim_comment = True
- else:
- raise AMForthException("Illegal nested comment")
- continue
-
- if not in_delim_comment and not in_line_comment:
- if w == "\\" and (iw == 0 or words[iw-1].lower() != "postpone"):
- in_line_comment = True
- continue
-
- elif w in self._config.current_behavior.start_string_words:
- in_string = True
- result.append(w)
- result.append('')
- continue
-
- if w in self._config.current_behavior.quote_char_words:
- char_quote = True # no continue deliberately
-
- if directive:
- directive_arg.append(w)
- else:
- if (self._config.current_behavior.directive_uncommented
- and not result
- and w in directives):
- directive = w
- else:
- result.append(w)
- else:
- if directive:
- directive_arg.append(w)
- else:
- if (self._config.current_behavior.directive_commented
- and not result
- and not comment_words
- and w in directives):
- directive = w
- else:
- comment_words.append(w)
-
- if directive and len(result):
- raise AMForthError("Directive must not have other content: %s",
- " ".join(result))
-
- return (" ".join(result), in_delim_comment,
- directive, " ".join(directive_arg))
-
- def _record_error(self, lineno):
- fn = self._config.current_behavior.filename
- if fn:
- self._last_error = (fn, lineno)
-
- def _split_space_or_tab(self, line):
- result = [""]
- for c in line:
- if c == " " or c == "\t":
- result.append("")
- else:
- result[-1] += c
- return result
-
- def handle_common_directives(self, directive, directive_arg):
- if directive == "#include" or directive == "#require":
- fn = directive_arg.strip()
- if self.upload_file(fn, directive == "#include"):
- resume_fn = self._config.current_behavior.filename
- if resume_fn:
- self.progress_callback("File", None, resume_fn + " (resumed)")
- else:
- self.progress_callback("Information", None, "already uploaded")
- elif directive == "#cd":
- dirname = directive_arg.strip()
- if os.path.isabs(dirname):
- dirpath = os.path.normpath(dirname)
- else:
- oldpath = self._config.current_behavior.working_directory
- dirpath = os.path.normpath(os.path.join(oldpath, dirname))
- self._config.current_behavior.working_directory = dirpath
- elif directive == "#timeout":
- try:
- timeout = float(directive_arg)
- except ValueError, e:
- self.progress_callback("Error", None, "Invalid timeout")
- return
- self._config.current_file_behavior.timeout = timeout
- elif directive == "#timeout-next":
- try:
- timeout = float(directive_arg)
- except ValueError, e:
- self.progress_callback("Error", None, "Invalid timeout")
- return
- behavior = copy.deepcopy(self._config.current_behavior)
- behavior.timeout = timeout
- self._config.next_line_behavior = behavior
- elif directive == "#ignore-error":
- v = self._yes_or_no_arg(directive_arg)
- self._config.current_file_behavior.ignore_errors = v
- elif directive == "#ignore-error-next":
- v = self._yes_or_no_arg(directive_arg)
- behavior = copy.deepcopy(self._config.current_behavior)
- behavior.ignore_errors = v
- self._config.next_line_behavior = behavior
- elif directive == "#error-on-output":
- v = self._yes_or_no_arg(directive_arg)
- behavior = self._config.current_file_behavior
- behavior.error_on_output = v
- elif directive == "#expect-output-next":
- regexp = directive_arg.strip()
- if not regexp:
- regexp = ".*"
- behavior = copy.deepcopy(self._config.current_behavior)
- behavior.expected_output_regexp = regexp
- self._config.next_line_behavior = behavior
- elif directive == "#start-string-word":
- behavior = self._config.current_file_behavior
- behavior.start_string_words.append(directive_arg.strip().split(" "))
- elif directive == "#quote-char-word":
- behavior = self._config.current_file_behavior
- behavior.quote_char_words.append(directive_arg.strip().split(" "))
- elif directive == "#directive":
- behavior = self._config.current_file_behavior
- behavior.directive_config = directive_arg.strip()
- else:
- errmsg = "Unknown directive: %s %s" % (directive, directive_arg)
- raise AMForthException(errmsg)
-
- def _yes_or_no_arg(self, directive_arg):
- if not directive_arg:
- return True
- else:
- if directive_arg.lower() == "yes":
- return True
- elif directive_arg.lower() == "no":
- return False
- else:
- errmsg = "Invalid directive argument. Must be yes or no."
- raise AMForthExcetion(errmsg)
-
- def send_line(self, line):
- if len(line) > self.max_line_length - 1: # For newline
- raise AMForthException("Input line > %d char"
- % self.max_line_length)
- if self.debug:
- sys.stderr.write("|a( )" + repr(line)[1:-1] + "\n")
- sys.stderr.write("|s( )")
- for c in line + "\n":
- if self.debug:
- sys.stderr.write(repr(c)[1:-1]+"->")
- sys.stderr.flush()
- self._serialconn.write(c)
- self._serialconn.flush()
- r = self._serialconn.read(1) # Read echo of character we just sent
- while r and (r != c or (c == '\t' and r != ' ')):
- if self.debug:
- sys.stderr.write(repr(r)[1:-1])
- sys.stderr.flush()
- r = self._serialconn.read(1)
- if not r:
- raise AMForthException("Input character not echoed.")
- if self.debug:
- sys.stderr.write(repr(r)[1:-1] + "|")
- sys.stderr.flush()
- if self.debug:
- sys.stderr.write("\n")
-
- def read_response(self):
- if self.debug:
- sys.stderr.write("|r( )")
- response = ""
- r = self._serialconn.read(1)
- while r != "":
- if self.debug:
- sys.stderr.write(repr(r)[1:-1])
- sys.stderr.flush()
- response = response + r
- if response[-3:] == " ok":
- # Interactive prompt read and discarded while handling
- # echo of next line sent.
- break
- elif self.amforth_error_cre.search(response) is not None:
- response = response[:-3] # Don't return prompt in response
- break
- r = self._serialconn.read(1)
- if not response:
- response = "Timed out waiting for ok response"
- if self.debug:
- sys.stderr.write("\n")
- return response
-
- def print_progress(self, type, lineno, info):
- if not lineno:
- print "|%s=%s" % (type[:1], info)
- else:
- print "|%s|%5d|%s" % (type[:1], lineno, info)
-
- def interact(self):
- self.progress_callback("Interact", None,
- "Entering amforth interactive interpreter")
- # Use null filename "file" to capture interactive config
- self._config.push_file(None)
- try:
- self.find_prompt()
- except AMForthException, e:
- self.progress_callback("Error", None, str(e))
- self._config.pop_file()
- raise
- self._init_readline()
- in_comment = False
- while True:
- try:
- if self._amforth_cpu:
- prompt="("+self._amforth_cpu+")> "
- else:
- prompt="> "
- full_line = raw_input(prompt)
- except EOFError, e:
- print ""
- break
- self._config.advance_line()
- self._serialconn.timeout = self._config.current_behavior.timeout
- try:
- os.chdir(self._config.current_behavior.working_directory)
- except OSError, e:
- errmsg = ("Failed to change to directory '%s': %s"
- % (self._config.current_behavior.working_directory,
- str(e)))
- self.progress_callback("Error", None, errmsg)
- raise AMForthException(errmsg)
- (line, in_comment,
- directive,
- directive_arg) = self.preprocess_line(full_line, in_comment,
- self.interact_directives)
- try:
- if directive:
- self.progress_callback("Directive", None, full_line)
- if directive == "#exit":
- break
- elif directive == "#update-words":
- self._update_words()
- continue
- elif directive == "#update-cpu":
- self._update_cpu()
- continue
- elif directive == "#update-files":
- self._update_files()
- continue
- elif directive == "#edit":
- if directive_arg:
- self.edit_file(directive_arg.strip())
- elif self._last_error:
- self.edit_file(*self._last_error)
- elif self._last_edited_file:
- self.edit_file(self._last_edited_file)
- else:
- print "No file to edit"
- continue
- self.handle_common_directives(directive, directive_arg)
- if directive == "#include" or directive == "#require":
- self._update_words()
- continue
- if in_comment or not line:
- continue
- else:
- self.send_line(line)
- print self.read_response()
- except AMForthException, e:
- print "Error: " + str(e)
- self._config.pop_file()
- self._serialconn.timeout = self._config.current_behavior.timeout
- try:
- os.chdir(self._config.current_behavior.working_directory)
- except OSError, e:
- errmsg = ("Failed to change to directory '%s': %s"
- % (self._config.current_behavior.working_directory,
- str(e)))
- self.progress_callback("Error", None, errmsg)
- raise AMForthException(errmsg)
- self.progress_callback("Interact", None,
- "Leaving interactive interpreter")
-
- def _init_readline(self):
- if not self._readline_initialized:
- readline.set_completer_delims(" ")
- readline.set_completer(self._rlcompleter)
- readline.parse_and_bind("tab: complete")
- histfn = os.path.join(os.path.expanduser("~"),
- ".frt-interact.history")
- try:
- readline.read_history_file(histfn)
- except IOError, e:
- pass
- self._update_words()
- self._update_cpu()
- self._update_files()
- self._update_uploaded_files()
- atexit.register(readline.write_history_file, histfn)
-
- def _update_words(self):
- # get all words that are available in the search order
- self.send_line("base @ decimal dp u. base !")
- dp = self.read_response()
- if dp[-3:] != " ok":
- return # Something went wrong, just silently ignore
- dp = int(dp[:-3])
- if self._amforth_dp != dp:
- self._amforth_dp = dp
- self.send_line("words")
- words = self.read_response()
- if words[-3:] != " ok":
- return # Something went wrong, just silently ignore
- self._amforth_words = words.split(" ") + self.interact_directives
-
- def _update_cpu(self):
- self.progress_callback("Information", None, "getting MCU name..")
- self.send_line("s\" cpu\" environment search-wordlist drop execute itype")
- words = self.read_response()
- if words[-3:] != " ok":
- return # Something went wrong, just silently ignore
- mcudef = words[:-3].lower()
- self._amforth_regs = {}
- if mcudef.startswith("msp"):
- flavor="msp430"
- else:
- flavor="avr8"
- self._search_list.insert(0,os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]),"..", flavor, "lib")))
- self._search_list.insert(0,os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]),"..", flavor, "devices",mcudef)))
- sys.path.insert(1,os.path.join(os.path.dirname(sys.argv[0]),"..", flavor, "devices",mcudef))
- try:
- from device import MCUREGS
- self._amforth_regs=MCUREGS
- self._amforth_cpu = words[:-3]
- self.progress_callback("Information", None, "successfully loaded register definitions for " + mcudef)
- except:
- self.progress_callback("Warning", None, "failed loading register definitions for " + mcudef + " .. continuing")
-
- def _update_files(self):
- self.progress_callback("Information", None, "getting filenames on the host")
- self._filedirs = {}
- for p in self._search_list:
- self.progress_callback("Information", None, " Reading "+p)
- for root, dirs, files in os.walk(p):
- for f in files:
-# print f
- fpath=os.path.realpath(os.path.join(root, f))
- fpathdir=os.path.dirname(fpath)
- if self._filedirs.has_key(f):
- # check for duplicates
- for d in self._filedirs[f]:
- if d==fpathdir:
- fpath=None
- if fpath: self._filedirs[f].append(fpathdir)
- else:
- self._filedirs[f]=[fpathdir]
-
- def _update_uploaded_files(self):
- self.progress_callback("Information", None, "getting filenames from the controller")
- self.send_line("uploaded-wl show-wordlist")
- files = self.read_response()
- if files[-3:] != " ok":
- return # Something went wrong, just silently ignore
- for f in files.split(" "):
- self._uploaded.add(f)
- self.progress_callback("Information", None, "already uploaded "+ ", ".join(self._uploaded)+" ")
- self._update_uploaded = True
-
- def _rlcompleter(self, text, state):
- if state == 0:
- line_words = readline.get_line_buffer().split(" ")
- if line_words and line_words[-1] == text:
- line_words = line_words[:-1]
- while line_words and line_words[-1] == "":
- line_words = line_words[:-1]
- if line_words:
- if line_words[-1] in ["#require", "#include", "#edit"]:
- self._rl_matches = [f for f in self._filedirs.keys()
- if f.startswith(text)]
- elif line_words[-1] == "#cd":
- fnames = glob.glob(text + '*')
- self._rl_matches = [f + "/" for f in fnames
- if os.path.isdir(f)]
- elif line_words[-1] == "#directive":
- self._rl_matches = [w for w in ("all ", "uncommented ",
- "commented ", "none ")
- if w.startswith(text)]
- elif line_words[-1] in ["#error-on-output",
- "#ignore-error", "#ignore-error-next"]:
- self._rl_matches = [w for w in ["yes", "no"]
- if w.startswith(text)]
- elif line_words[-1] in ["#exit", "#update-words",
- "#timeout", "#timeout-next"]:
- self._rl_matches = []
- else:
- self._rl_matches = [w + " " for w in self._amforth_words+self._amforth_regs.keys()
- if not text or w.startswith(text)]
- else:
- self._rl_matches = [w + " " for w in self._amforth_words+self._amforth_regs.keys()
- if not text or w.startswith(text)]
- if self._rl_matches:
- return self._rl_matches[0]
- else:
- return None
- else:
- if state < len(self._rl_matches):
- return self._rl_matches[state]
- else:
- return None
-
- def edit_file(self, filename, lineno=0):
- if self.editor:
- # Have to construct command line differently for different
- # editors to be able to move to specific line...
- exename = os.path.basename(self.editor)
- if exename in ["emacs", "emacsclient", "nano"]:
- cmd = [self.editor, "+" + str(lineno), filename]
- elif exename in ["vi", "vim"]:
- cmd = [self.editor, filename, "+" + str(lineno)]
- elif exename == "mcedit":
- cmd = [self.editor, " " + filename, ":" + str(lineno)]
- elif exename == "gedit":
- cmd = [self.editor, "-b", filename, "+" + str(lineno)]
- elif exename == "pn.exe":
- cmd = [self.editor, " --line", " "+str(lineno)+" ", filename]
- else:
- cmd = [self.editor, filename]
- try:
- subprocess.call(cmd)
- self._last_edited_file = filename
- except OSError, e:
- raise AMForthException("Could not start editor: "+self.editor)
- else:
- raise AMForthException("No editor specified. Use --editor or EDITOR environment variable")
-
-if __name__ == "__main__":
- sys.exit(AMForth().main())
-
diff --git a/amforth-6.5/tools/amforth-upload.py b/amforth-6.5/tools/amforth-upload.py
deleted file mode 100755
index 18069dc..0000000
--- a/amforth-6.5/tools/amforth-upload.py
+++ /dev/null
@@ -1,269 +0,0 @@
-#!/usr/bin/env python
-# amforth-upload.py
-#
-# uploads text files containing forth commands to a microcontroller running amforth (v1.3)
-# monitors the output from the microcontroller and uses the character echo to implement a kind of software flow control
-# also waits for a prompt after each line to allow the compiler a chance to run
-#
-# in theory it should never overrun the input buffer on the controller,
-# but it will easily get stuck if the output from the controller is unusual
-#
-# you have to kill any other processes that are accessing the serial port before running this,
-# otherwise it will miss characters that are stolen by the other process and get stuck
-#
-# perhaps a better way to implement this would have been as a program that could be plugged into a terminal program
-# like x/y/zmodem for minicom (except for the difficulty of killing it when it gets confused). oh well.
-#
-# mailto:pix@test.at
-# http://pix.test.at/
-
-# change 26.11.2007
-# mt: state machine extended to handle ok prompt later on the line
-# mt: defined include syntax for files:
-# #include filename
-# e.g. #include lib/ans94/marker.frt
-# mt: an envar AMFORTH_LIB is checked as the list of directories
-# to searched. This list is appended to "." (current work directory)
-#
-import sys
-import getopt
-import os
-import re
-import time
-import fnmatch
-
-global verbose, debug, mcudef
-
-def merge(seq):
- merged = []
- for s in seq:
- for x in s:
- merged.append(x)
- return merged
-
-def search_and_open_file(filename):
- directorylist=["","."]
- filedirs={}
- basefilename=os.path.basename(filename)
- if os.environ.has_key("AMFORTH_LIB"):
- directorylist = merge([directorylist, os.environ["AMFORTH_LIB"].split(":")])
- for p in directorylist:
- for root, dirs, files in os.walk(p):
- for f in files:
- if os.path.join(root, f).endswith("/"+basefilename): # better than fnmatch since it can deal with directiories
- fpath=os.path.realpath(os.path.join(root, f))
- if filedirs.has_key(f):
- for d in filedirs[f]:
- if d==fpath:
- fpath=None
- if fpath: filedirs[f].append(fpath)
- else:
- filedirs[f]=[fpath]
- if len(filedirs[basefilename])==1:
- print "\nusing ", filename," from", filedirs[filename][0]
- filehandle = file(filedirs[filename][0])
- return filehandle
- else:
- # oops, too many files or no one at all no file found?
- print "\n", filename , " was found in ", len(filedirs[basefilename]), " directories"
- print "\t\n".join(filedirs[basefilename])
- print >>sys.stderr, "Sorry, giving up. You should check the controller!"
- sys.exit(2)
-
-def write_line_flow(string,dest):
- # strip comments
- # these probably will strip comment-like structures out of ." .." strings as well.
-
- if debug:
- print >>sys.stderr, "line before comment stripping: "+string
-
- if usemcudef:
- for regname in MCUREGS:
- string = re.sub('(^|\s)+'+regname+'(\s|$)+', " " + MCUREGS[regname] + " ", string)
- if string[-1] != "\n":
- string = string + "\n"
- string = re.sub("(^| )\( .*?\)"," ",string)
- string = re.sub("(^| )\( [^\)]*$"," \n",string)
- #string = re.sub("(^| )\\\\ .*","",string)
-
-# if re.match("^\s*$",string):
-# if verbose:
-# print >>sys.stderr, "skipping empty line"
-# return
-
- if debug:
- print >>sys.stderr, "line after comment stripping: "+string
-
- if re.match("#include ", string):
- filename=re.match("#include (\S+)",string).group(1)
- nested_file = search_and_open_file(filename)
- write_file_flow(nested_file, dest)
- nested_file.close()
- return
-
-
- if verbose:
- print >>sys.stderr, "sending line: "+string
- for o in list(string):
- dest.write(o)
- if o == "\t":
- o = " "
-
- while True:
- i = dest.read(1)
- #print "<"+i+"]",
- #print >>sys.stderr, "["+i+"]"
- sys.stdout.write(i)
- sys.stdout.flush()
- if i == o:
- #print "|",
- break
- #dest.write("\n")
- if verbose:
- print >>sys.stderr, "waiting for prompt"
-
- start, nl, space, o, gt = range(5)
-
- state = start
-
- while True:
- #print >>sys.stderr, "{"+str(state)+"}"
- #dest.write("")
- i = dest.read(1)
- if i=="":
- continue
- #print "<"+i+"]",
- #print >>sys.stderr, "i=["+i+"] state="+str(state)
- sys.stdout.write(i)
- sys.stdout.flush()
- if i==" ":
- state = space
- elif state == start:
- if i == "\r":
- state = nl
- elif i == " ":
- state = space
- continue
- elif state == nl:
- if i == ">":
- state = gt
- else:
- state = start
- continue
- elif state == gt:
- if i == " ":
- if debug:
- print >>sys.stderr, "<matched '^> '>"
- break
- else:
- state = start
- continue
- elif state == space:
- if i == "o":
- state = o
- else:
- state = start
- continue
- elif state == o:
- if i == "k":
- if debug:
- print >>sys.stderr, "<matched ' ok'>"
- break
- else:
- state = start
-
- elif state == space:
- if i == "?":
- state = question
- else:
- state = start
- elif state == question:
- if i == "?":
- if debug:
- print >>sys.stderr, "<matched ' ??'>"
- break
- else:
- state = start
-
-def write_file_flow(in_file,dest):
- while(True):
- line = in_file.readline()
- if len(line)>0:
- write_line_flow(line,dest)
- else:
- break
-
-tty_dev_name = "/dev/ttyS0"
-force = False
-verbose = False
-debug = False
-usemcudef = False
-starttime = time.time()
-
-try:
- opts, args = getopt.getopt(sys.argv[1:],"ht:vfdc:")
-except getopt.GetoptError:
- print >>sys.stderr, "unknown option. try -h"
- sys.exit(1)
-for opt, arg in opts:
- if opt == "-h":
- print >>sys.stderr, "usage: amforth-upload [-h] [-v] [-f] [-t tty] [file1] [file2] [...]"
- print >>sys.stderr, " default tty is "+tty_dev_name
- print >>sys.stderr, " if no files are specified, input is read from the the terminal"
- print >>sys.stderr, " -f will run without checking for other processes accessing the tty"
- print >>sys.stderr, " -v will print extra information during execution"
- print >>sys.stderr, " -t selects the serial device. Default is " + tty_dev_name
- print >>sys.stderr, " -c partname-directory tries to load the device.py file from the partname directory."
- sys.exit(1)
- elif opt == "-t":
- tty_dev_name = arg
- elif opt == "-v":
- verbose = True
- elif opt == "-f":
- force = True
- elif opt == "-d":
- debug = True
- elif opt == "-c":
- mcudef = arg
- if mcudef.startswith("msp"):
- sys.path.append("msp430/devices/"+mcudef)
- else:
- sys.path.append("avr8/devices/"+mcudef)
- try:
- from device import *
- usemcudef = True
- print "using device.py from " + mcudef
- except:
- print "failed using device.py from " + mcudef + " .. continuing"
-
-if not force:
- if not os.system("which lsof > /dev/null 2>&1"):
- if not os.system("lsof " + tty_dev_name):
- print >>sys.stderr, "the above process is accessing "+tty_dev_name+"."
- print >>sys.stderr, "please stop the process and try again."
- print >>sys.stderr, "run with the -f option to force execution anyway"
- sys.exit(1)
- elif not os.system("which fuser >/dev/null 2>&1"):
- if not os.system("fuser -u "+tty_dev_name):
- print >>sys.stderr, "the above process is accessing "+tty_dev_name+"."
- print >>sys.stderr, "please stop the process and try again."
- print >>sys.stderr, "run with the -f option to force execution anyway"
- sys.exit(1)
- else:
- print >>sys.stderr, "couldn't find fuser. so i can't check if "+tty_dev_name+" is in use."
- tty_dev = file(tty_dev_name,"r+",0)
- # get a prompt, clean up the input buffer
- write_line_flow("\n", tty_dev)
- if len(args)<1:
- if verbose:
- print >>sys.stderr, "processing stdin"
- write_file_flow(sys.stdin,tty_dev)
- else:
- for filename in args:
- in_file = search_and_open_file(filename)
- write_file_flow(in_file,tty_dev)
- in_file.close()
-endtime = time.time()
-runtime = endtime - starttime
-print "\ntime: ", runtime, " seconds"
-